[gem5-dev] Change in gem5/gem5[develop]: arch-power: Implement GDB XML target description for PowerPC

[Boris Shingarov (Gerrit) via gem5-dev]

Boris Shingarov has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31114 )



Change subject: arch-power: Implement GDB XML target description for PowerPC
..

arch-power: Implement GDB XML target description for PowerPC

Change-Id: I2610626a7e1464316ebaa770291d4bdcb59e8856
---
A ext/gdb-xml/power.xml
M src/arch/power/SConscript
M src/arch/power/remote_gdb.cc
M src/arch/power/remote_gdb.hh
4 files changed, 118 insertions(+), 0 deletions(-)



diff --git a/ext/gdb-xml/power.xml b/ext/gdb-xml/power.xml
new file mode 100644
index 000..da5a07c
--- /dev/null
+++ b/ext/gdb-xml/power.xml
@@ -0,0 +1,92 @@
+
+
+
+
+
+  powerpc
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript
index 93be38c..607236a 100644
--- a/src/arch/power/SConscript
+++ b/src/arch/power/SConscript
@@ -1,6 +1,7 @@
 # -*- mode:python -*-

 # Copyright (c) 2009 The University of Edinburgh
+# Copyright (c) 2020 LabWare
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -57,3 +58,5 @@
 DebugFlag('Power')

 ISADesc('isa/main.isa')
+
+GdbXml('power.xml', 'gdb_xml_power')
diff --git a/src/arch/power/remote_gdb.cc b/src/arch/power/remote_gdb.cc
index ccee0b1..661c431 100644
--- a/src/arch/power/remote_gdb.cc
+++ b/src/arch/power/remote_gdb.cc
@@ -136,6 +136,7 @@

 #include 

+#include "blobs/gdb_xml_power.hh"
 #include "cpu/thread_state.hh"
 #include "debug/GDBAcc.hh"
 #include "debug/GDBMisc.hh"
@@ -213,3 +214,19 @@
 return 
 }

+bool
+RemoteGDB::getXferFeaturesRead(const std::string , std::string  
)

+{
+#define GDB_XML(x, s) \
+{ x, std::string(reinterpret_cast(Blobs::s), \
+Blobs::s ## _len) }
+static const std::map annexMap {
+GDB_XML("target.xml", gdb_xml_power),
+};
+#undef GDB_XML
+auto it = annexMap.find(annex);
+if (it == annexMap.end())
+return false;
+output = it->second;
+return true;
+}
diff --git a/src/arch/power/remote_gdb.hh b/src/arch/power/remote_gdb.hh
index 1b673bb..3bb726e 100644
--- a/src/arch/power/remote_gdb.hh
+++ b/src/arch/power/remote_gdb.hh
@@ -76,6 +76,12 @@
   public:
 RemoteGDB(System *_system, ThreadContext *tc, int _port);
 BaseGdbRegCache *gdbRegs();
+std::vector
+availableFeatures() const
+{
+return {"qXfer:features:read+"};
+};
+bool getXferFeaturesRead(const std::string , std::string  
);

 };

 } // namespace PowerISA

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31114
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2610626a7e1464316ebaa770291d4bdcb59e8856
Gerrit-Change-Number: 31114
Gerrit-PatchSet: 1
Gerrit-Owner: Boris Shingarov 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: mem: Optionally share the backing store

[Boris Shingarov (Gerrit) via gem5-dev]

Boris Shingarov has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30994 )


Change subject: mem: Optionally share the backing store
..

mem: Optionally share the backing store

This patch adds the ability for a host-OS process external to gem5
to access the backing store via POSIX shared memory.
The new param shared_backstore of the System object is the filename
of the shared memory (i.e., the first argument to shm_open()).

Change-Id: I98c948a32a15049a4515e6c02a14595fb5fe379f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30994
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/physical.cc
M src/mem/physical.hh
M src/sim/System.py
M src/sim/system.cc
4 files changed, 32 insertions(+), 6 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 4bd812c..a03f200 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -71,8 +71,10 @@

 PhysicalMemory::PhysicalMemory(const string& _name,
const vector& _memories,
-   bool mmap_using_noreserve) :
-_name(_name), size(0), mmapUsingNoReserve(mmap_using_noreserve)
+   bool mmap_using_noreserve,
+   const std::string& shared_backstore) :
+_name(_name), size(0), mmapUsingNoReserve(mmap_using_noreserve),
+sharedBackstore(shared_backstore)
 {
 if (mmap_using_noreserve)
 warn("Not reserving swap space. May cause SIGSEGV on actual  
usage\n");

@@ -192,7 +194,23 @@
 // perform the actual mmap
 DPRINTF(AddrRanges, "Creating backing store for range %s with  
size %d\n",

 range.to_string(), range.size());
-int map_flags = MAP_ANON | MAP_PRIVATE;
+
+int shm_fd;
+int map_flags;
+
+if (sharedBackstore.empty()) {
+shm_fd = -1;
+map_flags =  MAP_ANON | MAP_PRIVATE;
+} else {
+DPRINTF(AddrRanges, "Sharing backing store as %s\n",
+sharedBackstore.c_str());
+shm_fd = shm_open(sharedBackstore.c_str(), O_CREAT | O_RDWR, 0666);
+if (shm_fd == -1)
+   panic("Shared memory failed");
+if (ftruncate(shm_fd, range.size()))
+   panic("Setting size of shared memory failed");
+map_flags = MAP_SHARED;
+}

 // to be able to simulate very large memories, the user can opt to
 // pass noreserve to mmap
@@ -202,7 +220,7 @@

 uint8_t* pmem = (uint8_t*) mmap(NULL, range.size(),
 PROT_READ | PROT_WRITE,
-map_flags, -1, 0);
+map_flags, shm_fd, 0);

 if (pmem == (uint8_t*) MAP_FAILED) {
 perror("mmap");
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index 88a5cda..9d4ff9a 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -127,6 +127,8 @@
 // Let the user choose if we reserve swap space when calling mmap
 const bool mmapUsingNoReserve;

+const std::string sharedBackstore;
+
 // The physical memory used to provide the memory in the simulated
 // system
 std::vector backingStore;
@@ -158,7 +160,8 @@
  */
 PhysicalMemory(const std::string& _name,
const std::vector& _memories,
-   bool mmap_using_noreserve);
+   bool mmap_using_noreserve,
+   const std::string& shared_backstore);

 /**
  * Unmap all the backing store we have used.
diff --git a/src/sim/System.py b/src/sim/System.py
index 61fbe0e..e028f48 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -78,6 +78,10 @@
 # I/O bridge or cache
 mem_ranges = VectorParam.AddrRange([], "Ranges that constitute main  
memory")


+shared_backstore = Param.String("", "backstore's shmem segment  
filename, "
+"use to directly address the backstore from another host-OS  
process. "

+"Leave this empty to unset the MAP_SHARED flag.")
+
 cache_line_size = Param.Unsigned(64, "Cache line size in bytes")

 redirect_paths = VectorParam.RedirectPath([], "Path redirections")
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 7841ec0..4e3416e 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -213,7 +213,8 @@
 #else
   kvmVM(nullptr),
 #endif
-  physmem(name() + ".physmem", p->memories, p->mmap_using_noreserve),
+  physmem(name() + ".physmem", p->memories, p->mmap_using_noreserve,
+  p->shared_backstore),
   memoryMode(p->mem_mode),
   _cacheLineSize(p->cache_line_size),
   workItemsBegin(0),

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30994
To unsubscribe, or for help writing mail filters, visit  

[gem5-dev] gem5-20 paper on arXiv

[Jason Lowe-Power via gem5-dev]

Hi everyone!

I'm excited to announce that we've published a new gem5 paper! Right now,
it's available on arXiv at this URL: https://arxiv.org/abs/2007.03152

I tried to reach out to everyone who has been involved in gem5 development
since its inception in 2011. However, I'm certain to have missed people.
Plus, I got 100s of emails about this, and I'm sure one fell through the
cracks. If I missed anyone, I'm so sorry!

We will be "releasing" another version of the paper on arXiv in a few
weeks. So, if you spot any errors or if you wish to be included as an
author of the paper and contributed to gem5 between 2011 and gem5 version
20.0, please open an issue on this github repo:
https://github.com/darchr/gem5-20-paper. See the README
 for
authorship information.

If you use gem5-20.0+, we would appreciate it if you would cite this paper.

Cheers,
Jason
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Initialized some variables

[Anthony Gutierrez (Gerrit) via gem5-dev]

Hello Tony Gutierrez,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/31094

to review the following change.


Change subject: arch-arm: Initialized some variables
..

arch-arm: Initialized some variables

Some of the variables in pauth_helpers.cc
are uninitialized in certain control paths
which causes a compiler warning. We initialize
these to false since they should be updated
to the correct value in all valid code paths.

Change-Id: If34d7daaf2404c2cf014c7b4c0c2f979580f36b9
---
M src/arch/arm/pauth_helpers.cc
1 file changed, 28 insertions(+), 28 deletions(-)



diff --git a/src/arch/arm/pauth_helpers.cc b/src/arch/arm/pauth_helpers.cc
index c88795f..e996fd5 100644
--- a/src/arch/arm/pauth_helpers.cc
+++ b/src/arch/arm/pauth_helpers.cc
@@ -286,9 +286,9 @@
   using the same algorithm and key as AddPACDA().
 */

-bool trapEL2;
-bool trapEL3;
-bool enable;
+bool trapEL2(false);
+bool trapEL3(false);
+bool enable(false);

 uint64_t hi_key= tc->readMiscReg(MISCREG_APDAKeyHi_EL1);
 uint64_t lo_key= tc->readMiscReg(MISCREG_APDAKeyLo_EL1);
@@ -354,9 +354,9 @@
   using the same algorithm and key as AddPACDA().
 */

-bool trapEL2;
-bool trapEL3;
-bool enable;
+bool trapEL2(false);
+bool trapEL3(false);
+bool enable(false);

 uint64_t hi_key= tc->readMiscReg(MISCREG_APDBKeyHi_EL1);
 uint64_t lo_key= tc->readMiscReg(MISCREG_APDBKeyLo_EL1);
@@ -424,9 +424,9 @@
   using the same algorithm and key as AddPACDA().
 */

-bool trapEL2;
-bool trapEL3;
-bool enable;
+bool trapEL2(false);
+bool trapEL3(false);
+bool enable(false);

 uint64_t hi_key= tc->readMiscReg(MISCREG_APIAKeyHi_EL1);
 uint64_t lo_key= tc->readMiscReg(MISCREG_APIAKeyLo_EL1);
@@ -498,9 +498,9 @@
   using the same algorithm and key as AddPACDA().
 */

-bool trapEL2;
-bool trapEL3;
-bool enable;
+bool trapEL2(false);
+bool trapEL3(false);
+bool enable(false);

 uint64_t hi_key= tc->readMiscReg(MISCREG_APIBKeyHi_EL1);
 uint64_t lo_key= tc->readMiscReg(MISCREG_APIBKeyLo_EL1);
@@ -566,9 +566,9 @@
 Fault
 ArmISA::addPACDA(ThreadContext* tc, uint64_t X, uint64_t Y, uint64_t* out)
 {
-bool trapEL2;
-bool trapEL3;
-bool enable;
+bool trapEL2(false);
+bool trapEL3(false);
+bool enable(false);

 uint64_t hi_key= tc->readMiscReg(MISCREG_APDAKeyHi_EL1);
 uint64_t lo_key= tc->readMiscReg(MISCREG_APDAKeyLo_EL1);
@@ -630,9 +630,9 @@
 Fault
 ArmISA::addPACDB(ThreadContext* tc, uint64_t X, uint64_t Y, uint64_t* out)
 {
-bool trapEL2;
-bool trapEL3;
-bool enable;
+bool trapEL2(false);
+bool trapEL3(false);
+bool enable(false);

 uint64_t hi_key= tc->readMiscReg(MISCREG_APDBKeyHi_EL1);
 uint64_t lo_key= tc->readMiscReg(MISCREG_APDBKeyLo_EL1);
@@ -691,8 +691,8 @@
 Fault
 ArmISA::addPACGA(ThreadContext * tc, uint64_t X, uint64_t Y, uint64_t* out)
 {
-bool trapEL2;
-bool trapEL3;
+bool trapEL2(false);
+bool trapEL3(false);

 uint64_t hi_key= tc->readMiscReg(MISCREG_APGAKeyHi_EL1);
 uint64_t lo_key= tc->readMiscReg(MISCREG_APGAKeyLo_EL1);
@@ -738,9 +738,9 @@

 Fault
 ArmISA::addPACIA(ThreadContext * tc, uint64_t X, uint64_t Y, uint64_t*  
out){

-bool trapEL2;
-bool trapEL3;
-bool enable;
+bool trapEL2(false);
+bool trapEL3(false);
+bool enable(false);

 uint64_t hi_key= tc->readMiscReg(MISCREG_APIAKeyHi_EL1);
 uint64_t lo_key= tc->readMiscReg(MISCREG_APIAKeyLo_EL1);
@@ -797,9 +797,9 @@

 Fault
 ArmISA::addPACIB(ThreadContext* tc, uint64_t X, uint64_t Y, uint64_t* out){
-bool trapEL2;
-bool trapEL3;
-bool enable;
+bool trapEL2(false);
+bool trapEL3(false);
+bool enable(false);

 uint64_t hi_key= tc->readMiscReg(MISCREG_APIBKeyHi_EL1);
 uint64_t lo_key= tc->readMiscReg(MISCREG_APIBKeyLo_EL1);
@@ -859,8 +859,8 @@

 Fault
 ArmISA::stripPAC(ThreadContext* tc, uint64_t A, bool data, uint64_t* out){
-bool trapEL2;
-bool trapEL3;
+bool trapEL2(false);
+bool trapEL3(false);

 uint64_t ptr;


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31094
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If34d7daaf2404c2cf014c7b4c0c2f979580f36b9
Gerrit-Change-Number: 31094
Gerrit-PatchSet: 1
Gerrit-Owner: Anthony Gutierrez 
Gerrit-Reviewer: Tony Gutierrez 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Implement GIC DTB auto-generation.

[Chris January (Gerrit) via gem5-dev]

Chris January has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31078 )



Change subject: fastmodel: Implement GIC DTB auto-generation.
..

fastmodel: Implement GIC DTB auto-generation.

Implement generateDeviceTree for FastModelGIC so the interrupt
controller is automatically added to the DTB. This is sufficient to
allow a VExpressFastmodel system model to boot Linux without an
explicit DTB.

Change-Id: I69d86fd8bba1b86768c8a118d2de079a56179854
---
M src/arch/arm/fastmodel/GIC/FastModelGIC.py
1 file changed, 74 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/fastmodel/GIC/FastModelGIC.py  
b/src/arch/arm/fastmodel/GIC/FastModelGIC.py

index d682e85..c1f9b72 100644
--- a/src/arch/arm/fastmodel/GIC/FastModelGIC.py
+++ b/src/arch/arm/fastmodel/GIC/FastModelGIC.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright 2019 Google, Inc.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -24,6 +36,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 from m5.params import *
+from m5.util.fdthelper import *
 from m5.SimObject import SimObject

 from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
@@ -463,6 +476,9 @@
 redistributor = VectorGicv3CommsInitiatorSocket(
 'GIC communication initiator')

+# Used for DTB autogeneration
+_state = FdtState(addr_cells=2, size_cells=2, interrupt_cells=3)
+
 def get_redist_bases(self):
 """
 The format of reg_base_per_redistributor is
@@ -497,3 +513,61 @@
 ]

 return ranges
+
+def interruptCells(self, int_type, int_num, int_flag):
+"""
+Interupt cells generation helper:
+Following specifications described in
+
+ 
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt

+"""
+prop = self._state.interruptCells(0)
+assert len(prop) >= 3
+prop[0] = int_type
+prop[1] = int_num
+prop[2] = int_flag
+return prop
+
+def generateDeviceTree(self, state):
+sc_gic = self.sc_gic
+
+node = FdtNode("interrupt-controller")
+node.appendCompatible(["arm,gic-v3"])
+node.append(self._state.interruptCellsProperty())
+node.append(self._state.addrCellsProperty())
+node.append(self._state.sizeCellsProperty())
+node.append(FdtProperty("ranges"))
+node.append(FdtProperty("interrupt-controller"))
+
+redist_stride = 0x4 if sc_gic.has_gicv4_1 else 0x2
+node.append(FdtPropertyWords("redistributor-stride",
+state.sizeCells(redist_stride)))
+
+regs = (
+state.addrCells(sc_gic.reg_base) +
+state.sizeCells(0x1) +
+state.addrCells(self.get_redist_bases()[0]) +
+state.sizeCells(0x200) )
+
+node.append(FdtPropertyWords("reg", regs))
+node.append(FdtPropertyWords("interrupts",
+self.interruptCells(1, 9, 0xf04)))
+
+node.appendPhandle(self)
+
+# Generate the ITS device tree
+gic_frame_size = 0x1
+its_bases = [
+sc_gic.its0_base, sc_gic.its1_base, sc_gic.its2_base,
+sc_gic.its3_base
+]
+for its_base in its_bases:
+its_node = self.generateBasicPioDeviceNode(state, "gic-its",
+   its_base,
+   2 * gic_frame_size)
+its_node.appendCompatible(["arm,gic-v3-its"])
+its_node.append(FdtProperty("msi-controller"))
+its_node.append(FdtPropertyWords("#msi-cells", [1]))
+node.append(its_node)
+
+yield node

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31078
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I69d86fd8bba1b86768c8a118d2de079a56179854
Gerrit-Change-Number: 31078
Gerrit-PatchSet: 1
Gerrit-Owner: Chris January 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Remove scs_prefix_appli_output binding.

[Chris January (Gerrit) via gem5-dev]

Chris January has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31077 )



Change subject: fastmodel: Remove scs_prefix_appli_output binding.
..

fastmodel: Remove scs_prefix_appli_output binding.

The scx_prefix_appli_output function is removed in recent Fast Models
releases.

Change-Id: I324b911ec7ed68b7d0c324ac20a9795515e4de57
---
M src/arch/arm/fastmodel/fastmodel.cc
1 file changed, 13 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/fastmodel/fastmodel.cc  
b/src/arch/arm/fastmodel/fastmodel.cc

index 27a39fc..96bb744 100644
--- a/src/arch/arm/fastmodel/fastmodel.cc
+++ b/src/arch/arm/fastmodel/fastmodel.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright 2019 Google, Inc.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -52,7 +64,7 @@
 // especially since there are other preferred methods for setting  
up

 // the parameters of a component.
 .def("scx_set_parameter",
- static_cast&)>(

+ static_cast(
  ::scx_set_parameter))
 .def("scx_get_parameter",
  static_cast(
@@ -85,8 +97,6 @@
  pybind11::arg("debug") = false)
 .def("scx_enable_cadi_log", ::scx_enable_cadi_log,
  pybind11::arg("log") = true)
-.def("scx_prefix_appli_output", ::scx_prefix_appli_output,
- pybind11::arg("prefix") = true)
 .def("scx_print_port_number", ::scx_print_port_number,
  pybind11::arg("print") = true)


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31077
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I324b911ec7ed68b7d0c324ac20a9795515e4de57
Gerrit-Change-Number: 31077
Gerrit-PatchSet: 1
Gerrit-Owner: Chris January 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Fix hierachical Iris component names.

[Chris January (Gerrit) via gem5-dev]

Chris January has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31076 )



Change subject: fastmodel: Fix hierachical Iris component names.
..

fastmodel: Fix hierachical Iris component names.

Recent releases of Fast Models structure Iris resources in a hierarchy.
Use the parent resource ID if set to construct the hierachical name of
components when constructing the resource map.

Change-Id: Iafafa26d5aff560c3b2e93894f81f770c0e98079
---
M src/arch/arm/fastmodel/iris/thread_context.cc
1 file changed, 22 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc  
b/src/arch/arm/fastmodel/iris/thread_context.cc

index a2cf2bf..f89180c 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright 2019 Google, Inc.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -205,8 +217,16 @@
 call().resource_getList(_instId, resources);

 ResourceMap resourceMap;
-for (auto : resources)
-resourceMap[resource.name] = resource;
+for (auto : resources) {
+std::string name = resource.name;
+if (resource.parentRscId != iris::IRIS_UINT64_MAX) {
+for (auto : resources) {
+if (parentResource.rscId == resource.parentRscId)
+name = parentResource.name + "." + resource.name;
+}
+}
+resourceMap[name] = resource;
+}

 initFromIrisInstance(resourceMap);


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31076
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iafafa26d5aff560c3b2e93894f81f770c0e98079
Gerrit-Change-Number: 31076
Gerrit-PatchSet: 1
Gerrit-Owner: Chris January 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: configs: Add earlycon to default kernel_cmd.

[Chris January (Gerrit) via gem5-dev]

Chris January has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31074 )



Change subject: configs: Add earlycon to default kernel_cmd.
..

configs: Add earlycon to default kernel_cmd.

The earlyprintk kernel command line argument does not take a value on Arm.
Rather pass early console name using the earlycon command line argument.

Change-Id: Ie14fc425e87c50a0b59fa4270a3743ed4fe97589
---
M configs/example/arm/fs_bigLITTLE.py
1 file changed, 3 insertions(+), 2 deletions(-)



diff --git a/configs/example/arm/fs_bigLITTLE.py  
b/configs/example/arm/fs_bigLITTLE.py

index 228d11c..29f5c6b 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2017, 2019 ARM Limited
+# Copyright (c) 2016-2017, 2019-2020 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -219,7 +219,8 @@
 m5.ticks.fixGlobalFrequency()

 kernel_cmd = [
-"earlyprintk=pl011,0x1c09",
+"earlyprintk",
+"earlycon=pl011,0x1c09",
 "console=ttyAMA0",
 "lpj=19988480",
 "norandmaps",

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31074
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie14fc425e87c50a0b59fa4270a3743ed4fe97589
Gerrit-Change-Number: 31074
Gerrit-PatchSet: 1
Gerrit-Owner: Chris January 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Add missing dependencies.

[Chris January (Gerrit) via gem5-dev]

Chris January has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31075 )



Change subject: fastmodel: Add missing dependencies.
..

fastmodel: Add missing dependencies.

Add -latomic library required by recent Fast Models releases.
Add SystemCExport directory for tlm_has_get_protocol_types.h include.

Change-Id: Ia0c275d55f5077499588228737ed1ff5975cd5db
---
M src/arch/arm/fastmodel/SConscript
1 file changed, 14 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/fastmodel/SConscript  
b/src/arch/arm/fastmodel/SConscript

index 2fd4ba0..afcfbde 100644
--- a/src/arch/arm/fastmodel/SConscript
+++ b/src/arch/arm/fastmodel/SConscript
@@ -1,3 +1,15 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright 2019 Google, Inc.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -94,6 +106,7 @@
 pvlib_home.Dir('include/fmruntime'),
 pvlib_home.Dir('include/fmruntime/eslapi'),
 pvlib_home.Dir('Iris/include'),
+pvlib_home.Dir('examples/SystemCExport/Common'),

 systemc_home.Dir('include'),

@@ -114,6 +127,7 @@
 'armctmodel',
 'fmruntime',
 'IrisSupport',
+'atomic',
 'dl',
 'rt',
 )

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31075
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia0c275d55f5077499588228737ed1ff5975cd5db
Gerrit-Change-Number: 31075
Gerrit-PatchSet: 1
Gerrit-Owner: Chris January 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Implement Level Sensitive PPIs in GICv2

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31056 )



Change subject: dev-arm: Implement Level Sensitive PPIs in GICv2
..

dev-arm: Implement Level Sensitive PPIs in GICv2

JIRA: https://gem5.atlassian.net/browse/GEM5-667

Change-Id: I9ae40f08f4a1de95469ff5ed6788354abafc
Signed-off-by: Giacomo Travaglini 
---
M src/dev/arm/gic_v2.cc
M src/dev/arm/gic_v2.hh
2 files changed, 38 insertions(+), 13 deletions(-)



diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index 302da2f..1a6954d 100644
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -343,7 +343,9 @@
 uint32_t int_num = 1 << (cpuHighestInt[ctx] - SGI_MAX);
 cpuPpiActive[ctx] |= int_num;
 updateRunPri();
-cpuPpiPending[ctx] &= ~int_num;
+if (!isLevelSensitive(ctx, active_int)) {
+cpuPpiPending[ctx] &= ~int_num;
+}

 } else {
 uint32_t int_num = 1 << intNumToBit(cpuHighestInt[ctx]);
@@ -518,7 +520,10 @@

 if (GICD_ICFGR.contains(daddr)) {
 uint32_t ix = (daddr - GICD_ICFGR.start()) >> 2;
-getIntConfig(ctx, ix) = data;
+// Since the GICD_ICFGR0 is RO (WI), we are discarding the write
+// if ix = 0
+if (ix != 0)
+getIntConfig(ctx, ix) = data;
 if (data & NN_CONFIG_MASK)
 warn("GIC N:N mode selected and not supported at this time\n");
 return;
@@ -897,10 +902,16 @@
 void
 GicV2::clearPPInt(uint32_t num, uint32_t cpu)
 {
-DPRINTF(Interrupt, "Clearing PPI %d, cpuTarget %#x: \n",
-num, cpu);
-cpuPpiPending[cpu] &= ~(1 << (num - SGI_MAX));
-updateIntState(intNumToWord(num));
+if (isLevelSensitive(cpu, num)) {
+DPRINTF(Interrupt, "Clearing PPI %d, cpuTarget %#x: \n",
+num, cpu);
+cpuPpiPending[cpu] &= ~(1 << (num - SGI_MAX));
+updateIntState(intNumToWord(num));
+} else {
+/* Nothing to do :
+ * Edge-triggered interrupt remain pending until software
+ * writes GICD_ICPENDR or reads GICC_IAR */
+}
 }

 void
@@ -989,7 +1000,7 @@
 SERIALIZE_ARRAY(iccrpr, CPU_MAX);
 SERIALIZE_ARRAY(intPriority, GLOBAL_INT_LINES);
 SERIALIZE_ARRAY(cpuTarget, GLOBAL_INT_LINES);
-SERIALIZE_ARRAY(intConfig, INT_BITS_MAX * 2);
+SERIALIZE_ARRAY(intConfig, INT_BITS_MAX * 2 - 2);
 SERIALIZE_ARRAY(cpuControl, CPU_MAX);
 SERIALIZE_ARRAY(cpuPriority, CPU_MAX);
 SERIALIZE_ARRAY(cpuBpr, CPU_MAX);
@@ -1016,6 +1027,7 @@
 SERIALIZE_SCALAR(pendingInt);
 SERIALIZE_SCALAR(activeInt);
 SERIALIZE_SCALAR(intGroup);
+SERIALIZE_ARRAY(intConfig, 2);
 SERIALIZE_ARRAY(intPriority, SGI_MAX + PPI_MAX);
 }

@@ -1033,7 +1045,7 @@
 UNSERIALIZE_ARRAY(iccrpr, CPU_MAX);
 UNSERIALIZE_ARRAY(intPriority, GLOBAL_INT_LINES);
 UNSERIALIZE_ARRAY(cpuTarget, GLOBAL_INT_LINES);
-UNSERIALIZE_ARRAY(intConfig, INT_BITS_MAX * 2);
+UNSERIALIZE_ARRAY(intConfig, INT_BITS_MAX * 2 - 2);
 UNSERIALIZE_ARRAY(cpuControl, CPU_MAX);
 UNSERIALIZE_ARRAY(cpuPriority, CPU_MAX);
 UNSERIALIZE_ARRAY(cpuBpr, CPU_MAX);
@@ -1075,6 +1087,7 @@
 UNSERIALIZE_SCALAR(pendingInt);
 UNSERIALIZE_SCALAR(activeInt);
 UNSERIALIZE_SCALAR(intGroup);
+UNSERIALIZE_ARRAY(intConfig, 2);
 UNSERIALIZE_ARRAY(intPriority, SGI_MAX + PPI_MAX);
 }

diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index aefa938..54c95f9 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -192,6 +192,10 @@
  * interrupt group bits for first 32 interrupts, 1b per interrupt  
*/

 uint32_t intGroup;

+/** GICD_ICFGR0, GICD_ICFGR1
+ * interrupt config bits for first 32 interrupts, 2b per interrupt  
*/

+uint32_t intConfig[2];
+
 /** GICD_IPRIORITYR{0..7}
  * interrupt priority for SGIs and PPIs */
 uint8_t intPriority[SGI_MAX + PPI_MAX];
@@ -201,7 +205,7 @@

 BankedRegs() :
 intEnabled(0), pendingInt(0), activeInt(0),
-intGroup(0), intPriority {0}
+intGroup(0), intConfig {0}, intPriority {0}
   {}
 };
 std::vector bankedRegs;
@@ -281,18 +285,26 @@
 }
 }

-/** 2 bit per interrupt signaling if it's level or edge sensitive
+/**
+ * GICD_ICFGR{2...63}
+ * 2 bit per interrupt signaling if it's level or edge sensitive
  * and if it is 1:N or N:N */
-uint32_t intConfig[INT_BITS_MAX*2];
+uint32_t intConfig[INT_BITS_MAX*2 - 2];

-/** GICD_ICFGRn
+/**
+ * Reads the GICD_ICFGRn register.
  * @param ctx context id (PE specific)
  * @param ix interrupt word index
  * @returns the interrupt config word
  */
 uint32_t& getIntConfig(ContextID ctx, uint32_t ix) {
 assert(ix < INT_BITS_MAX*2);
-return 

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Use getIntConfig when reading/writing GICD_ICFGR

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31055 )



Change subject: dev-arm: Use getIntConfig when reading/writing GICD_ICFGR
..

dev-arm: Use getIntConfig when reading/writing GICD_ICFGR

This patch is changing the getIntConfig helper (which has been
used so far by isLevelSensitive only) to make it usable by the
read/writes of the GICD_ICFGR register.

While the helper was previously returning the irq config bits
provided a single irq as an input, this new version is returning
the entire GICD_ICFGR word (read/writable)

JIRA: https://gem5.atlassian.net/browse/GEM5-667

Change-Id: I07e455a9e2819fed1f97a0e372d9d9a2e5ad4801
Signed-off-by: Giacomo Travaglini 
---
M src/dev/arm/gic_v2.cc
M src/dev/arm/gic_v2.hh
2 files changed, 16 insertions(+), 18 deletions(-)



diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index 4ef1517..302da2f 100644
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
+ * Copyright (c) 2010, 2013, 2015-2018, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -72,7 +72,7 @@
   enabled(false), haveGem5Extensions(p->gem5_extensions),
   itLines(p->it_lines),
   intEnabled {}, pendingInt {}, activeInt {},
-  intPriority {}, cpuTarget {}, intConfig {},
+  intPriority {}, intConfig {}, cpuTarget {},
   cpuSgiPending {}, cpuSgiActive {},
   cpuSgiPendingExt {}, cpuSgiActiveExt {},
   cpuPpiPending {}, cpuPpiActive {},
@@ -250,10 +250,7 @@

 if (GICD_ICFGR.contains(daddr)) {
 uint32_t ix = (daddr - GICD_ICFGR.start()) >> 2;
-assert(ix < 64);
-/** @todo software generated interrupts and PPIs
- * can't be configured in some ways */
-return intConfig[ix];
+return getIntConfig(ctx, ix);
 }

 switch(daddr) {
@@ -521,8 +518,7 @@

 if (GICD_ICFGR.contains(daddr)) {
 uint32_t ix = (daddr - GICD_ICFGR.start()) >> 2;
-assert(ix < INT_BITS_MAX*2);
-intConfig[ix] = data;
+getIntConfig(ctx, ix) = data;
 if (data & NN_CONFIG_MASK)
 warn("GIC N:N mode selected and not supported at this time\n");
 return;
diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index 40a9553..aefa938 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2013, 2015-2019 ARM Limited
+ * Copyright (c) 2010, 2013, 2015-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -286,13 +286,13 @@
 uint32_t intConfig[INT_BITS_MAX*2];

 /** GICD_ICFGRn
- * get 2 bit config associated to an interrupt.
+ * @param ctx context id (PE specific)
+ * @param ix interrupt word index
+ * @returns the interrupt config word
  */
-uint8_t getIntConfig(ContextID ctx, uint32_t ix) {
-assert(ix < INT_LINES_MAX);
-const uint8_t cfg_low = intNumToBit(ix * 2);
-const uint8_t cfg_hi = cfg_low + 1;
-return bits(intConfig[intNumToWord(ix * 2)], cfg_hi, cfg_low);
+uint32_t& getIntConfig(ContextID ctx, uint32_t ix) {
+assert(ix < INT_BITS_MAX*2);
+return intConfig[ix];
 }

 /** GICD_ITARGETSR{8..255}
@@ -323,11 +323,13 @@
 }
 }

-bool isLevelSensitive(ContextID ctx, uint32_t ix) {
-if (ix == SPURIOUS_INT) {
+bool isLevelSensitive(ContextID ctx, uint32_t int_num) {
+if (int_num == SPURIOUS_INT) {
 return false;
 } else {
-return bits(getIntConfig(ctx, ix), 1) == 0;
+const auto ix = intNumToWord(int_num * 2);
+const uint8_t cfg_hi = intNumToBit(int_num * 2) + 1;
+return bits(getIntConfig(ctx, ix), cfg_hi) == 0;
 }
 }


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31055
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I07e455a9e2819fed1f97a0e372d9d9a2e5ad4801
Gerrit-Change-Number: 31055
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Move GICv2 intConfig for consistency

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31054 )



Change subject: dev-arm: Move GICv2 intConfig for consistency
..

dev-arm: Move GICv2 intConfig for consistency

Every other helper is placed below the respective array storage

JIRA: https://gem5.atlassian.net/browse/GEM5-667

Change-Id: I398ac23eb68d84a8e0ed856550bfac8e403a86b3
Signed-off-by: Giacomo Travaglini 
---
M src/dev/arm/gic_v2.hh
1 file changed, 4 insertions(+), 4 deletions(-)



diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index 600f9af..40a9553 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -281,6 +281,10 @@
 }
 }

+/** 2 bit per interrupt signaling if it's level or edge sensitive
+ * and if it is 1:N or N:N */
+uint32_t intConfig[INT_BITS_MAX*2];
+
 /** GICD_ICFGRn
  * get 2 bit config associated to an interrupt.
  */
@@ -319,10 +323,6 @@
 }
 }

-/** 2 bit per interrupt signaling if it's level or edge sensitive
- * and if it is 1:N or N:N */
-uint32_t intConfig[INT_BITS_MAX*2];
-
 bool isLevelSensitive(ContextID ctx, uint32_t ix) {
 if (ix == SPURIOUS_INT) {
 return false;

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31054
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I398ac23eb68d84a8e0ed856550bfac8e403a86b3
Gerrit-Change-Number: 31054
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Style fixes for src/dev/arm/gic_v2.hh

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31057 )



Change subject: dev-arm: Style fixes for src/dev/arm/gic_v2.hh
..

dev-arm: Style fixes for src/dev/arm/gic_v2.hh

JIRA: https://gem5.atlassian.net/browse/GEM5-667

Change-Id: I80dce7b72775beabafa3b54e915a369571f2e4c9
Signed-off-by: Giacomo Travaglini 
---
M src/dev/arm/gic_v2.hh
1 file changed, 39 insertions(+), 14 deletions(-)



diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index 54c95f9..088d31e 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -217,7 +217,9 @@
  * 1b per interrupt, 32 bits per word, 31 words */
 uint32_t intEnabled[INT_BITS_MAX-1];

-uint32_t& getIntEnabled(ContextID ctx, uint32_t ix) {
+uint32_t&
+getIntEnabled(ContextID ctx, uint32_t ix)
+{
 if (ix == 0) {
 return getBankedRegs(ctx).intEnabled;
 } else {
@@ -230,7 +232,9 @@
  * 1b per interrupt, 32 bits per word, 31 words */
 uint32_t pendingInt[INT_BITS_MAX-1];

-uint32_t& getPendingInt(ContextID ctx, uint32_t ix) {
+uint32_t&
+getPendingInt(ContextID ctx, uint32_t ix)
+{
 assert(ix < INT_BITS_MAX);
 if (ix == 0) {
 return getBankedRegs(ctx).pendingInt;
@@ -244,7 +248,9 @@
  * 1b per interrupt, 32 bits per word, 31 words */
 uint32_t activeInt[INT_BITS_MAX-1];

-uint32_t& getActiveInt(ContextID ctx, uint32_t ix) {
+uint32_t&
+getActiveInt(ContextID ctx, uint32_t ix)
+{
 assert(ix < INT_BITS_MAX);
 if (ix == 0) {
 return getBankedRegs(ctx).activeInt;
@@ -258,7 +264,9 @@
  * 1b per interrupt, 32 bits per word, 31 words */
 uint32_t intGroup[INT_BITS_MAX-1];

-uint32_t& getIntGroup(ContextID ctx, uint32_t ix) {
+uint32_t&
+getIntGroup(ContextID ctx, uint32_t ix)
+{
 assert(ix < INT_BITS_MAX);
 if (ix == 0) {
 return getBankedRegs(ctx).intGroup;
@@ -276,7 +284,9 @@
  */
 uint8_t intPriority[GLOBAL_INT_LINES];

-uint8_t& getIntPriority(ContextID ctx, uint32_t ix) {
+uint8_t&
+getIntPriority(ContextID ctx, uint32_t ix)
+{
 assert(ix < INT_LINES_MAX);
 if (ix < SGI_MAX + PPI_MAX) {
 return getBankedRegs(ctx).intPriority[ix];
@@ -297,7 +307,9 @@
  * @param ix interrupt word index
  * @returns the interrupt config word
  */
-uint32_t& getIntConfig(ContextID ctx, uint32_t ix) {
+uint32_t&
+getIntConfig(ContextID ctx, uint32_t ix)
+{
 assert(ix < INT_BITS_MAX*2);
 if (ix < 2) {
 /** SGIs and PPIs **/
@@ -312,7 +324,9 @@
  */
 uint8_t cpuTarget[GLOBAL_INT_LINES];

-uint8_t getCpuTarget(ContextID ctx, uint32_t ix) {
+uint8_t
+getCpuTarget(ContextID ctx, uint32_t ix) const
+{
 assert(ctx < sys->threads.numRunning());
 assert(ix < INT_LINES_MAX);
 if (ix < SGI_MAX + PPI_MAX) {
@@ -335,7 +349,9 @@
 }
 }

-bool isLevelSensitive(ContextID ctx, uint32_t int_num) {
+bool
+isLevelSensitive(ContextID ctx, uint32_t int_num)
+{
 if (int_num == SPURIOUS_INT) {
 return false;
 } else {
@@ -345,7 +361,9 @@
 }
 }

-bool isGroup0(ContextID ctx, uint32_t int_num) {
+bool
+isGroup0(ContextID ctx, uint32_t int_num)
+{
 const uint32_t group_reg = getIntGroup(ctx, intNumToWord(int_num));
 return !bits(group_reg, intNumToBit(int_num));
 }
@@ -360,7 +378,9 @@
  * 2) GICC_CTLR.FIQEn: controls whether the CPU interface signals  
Group 0

  * interrupts to a target processor using the FIQ or the IRQ signal
  */
-bool isFiq(ContextID ctx, uint32_t int_num) {
+bool
+isFiq(ContextID ctx, uint32_t int_num)
+{
 const bool is_group0 = isGroup0(ctx, int_num);
 const bool use_fiq = cpuControl[ctx].fiqEn;

@@ -374,7 +394,9 @@
 /** CPU enabled:
  * Checks if GICC_CTLR.EnableGrp0 or EnableGrp1 are set
  */
-bool cpuEnabled(ContextID ctx) const {
+bool
+cpuEnabled(ContextID ctx) const
+{
 return cpuControl[ctx].enableGrp0 ||
cpuControl[ctx].enableGrp1;
 }
@@ -496,7 +518,9 @@
 Tick readDistributor(PacketPtr pkt);
 uint32_t readDistributor(ContextID ctx, Addr daddr,
  size_t resp_sz);
-uint32_t readDistributor(ContextID ctx, Addr daddr) override {
+uint32_t
+readDistributor(ContextID ctx, Addr daddr) override
+{
 return readDistributor(ctx, daddr, 4);
 }

@@ -512,8 +536,9 @@
 Tick writeDistributor(PacketPtr pkt);
 void writeDistributor(ContextID ctx, Addr daddr,
   uint32_t data, size_t data_sz);
-void writeDistributor(ContextID ctx, Addr daddr,
-  uint32_t data) override {
+