[gem5-dev] Change in gem5/gem5[develop]: arch,base,mem,sim: Fix style in base/types.hh and remove extra includes.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39855 )


Change subject: arch,base,mem,sim: Fix style in base/types.hh and remove  
extra includes.

..

arch,base,mem,sim: Fix style in base/types.hh and remove extra includes.

The base/refcnt.hh header was not used in base/types.hh at all, and
enum/ByteOrder.hh was there just so other files could find it. Instead,
this change moves enum/Byteorder.hh to sim/byteswap.hh where it's fits
with the purpose of the header.

This change also fixes some style problems with the code in
base/types.hh itself.

Change-Id: I471ae5cb2cca9169ba8616fb8411b40108a3ffb2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39855
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/freebsd/freebsd.hh
M src/arch/arm/isa_traits.hh
M src/arch/mips/isa_traits.hh
M src/arch/power/isa_traits.hh
M src/arch/riscv/isa_traits.hh
M src/arch/sparc/isa_traits.hh
M src/arch/sparc/solaris/solaris.hh
M src/arch/x86/isa_traits.hh
M src/base/pixel.hh
M src/base/types.hh
M src/mem/packet.hh
M src/sim/byteswap.hh
12 files changed, 36 insertions(+), 19 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/freebsd/freebsd.hh  
b/src/arch/arm/freebsd/freebsd.hh

index ef9da65..23fa0af 100644
--- a/src/arch/arm/freebsd/freebsd.hh
+++ b/src/arch/arm/freebsd/freebsd.hh
@@ -34,6 +34,7 @@
 #define __ARCH_ARM_FREEBSD_FREEBSD_HH__

 #include "kern/freebsd/freebsd.hh"
+#include "sim/byteswap.hh"

 class ArmFreebsd : public FreeBSD
 {
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index 798db72..d8ef5e7 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -43,6 +43,7 @@
 #define __ARCH_ARM_ISA_TRAITS_HH__

 #include "base/types.hh"
+#include "sim/byteswap.hh"

 namespace ArmISA
 {
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index aac595a..cf83d74 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -31,6 +31,7 @@
 #define __ARCH_MIPS_ISA_TRAITS_HH__

 #include "base/types.hh"
+#include "sim/byteswap.hh"

 namespace MipsISA
 {
diff --git a/src/arch/power/isa_traits.hh b/src/arch/power/isa_traits.hh
index 4cf0c44..fd230eb 100644
--- a/src/arch/power/isa_traits.hh
+++ b/src/arch/power/isa_traits.hh
@@ -32,6 +32,7 @@
 #define __ARCH_POWER_ISA_TRAITS_HH__

 #include "base/types.hh"
+#include "sim/byteswap.hh"

 namespace PowerISA
 {
diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index 4cf455d..ee6d8f7 100644
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -43,6 +43,7 @@
 #define __ARCH_RISCV_ISA_TRAITS_HH__

 #include "base/types.hh"
+#include "sim/byteswap.hh"

 namespace RiscvISA
 {
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 3f7cdac..c1690dd 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -30,6 +30,7 @@
 #define __ARCH_SPARC_ISA_TRAITS_HH__

 #include "base/types.hh"
+#include "sim/byteswap.hh"

 namespace SparcISA
 {
diff --git a/src/arch/sparc/solaris/solaris.hh  
b/src/arch/sparc/solaris/solaris.hh

index 0462832..7a5aaaf 100644
--- a/src/arch/sparc/solaris/solaris.hh
+++ b/src/arch/sparc/solaris/solaris.hh
@@ -30,6 +30,7 @@
 #define __ARCH_SPARC_SOLARIS_SOLARIS_HH__

 #include "kern/solaris/solaris.hh"
+#include "sim/byteswap.hh"

 class SparcSolaris : public Solaris
 {
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index dee98dc..befadab 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -39,6 +39,7 @@
 #define __ARCH_X86_ISATRAITS_HH__

 #include "base/types.hh"
+#include "sim/byteswap.hh"

 namespace X86ISA
 {
diff --git a/src/base/pixel.hh b/src/base/pixel.hh
index 7937e89..3cca761 100644
--- a/src/base/pixel.hh
+++ b/src/base/pixel.hh
@@ -47,6 +47,7 @@
 #include "base/cprintf.hh"
 #include "base/str.hh"
 #include "base/types.hh"
+#include "sim/byteswap.hh"

 /**
  * Internal gem5 representation of a Pixel.
diff --git a/src/base/types.hh b/src/base/types.hh
index 7ae573d..0b93073 100644
--- a/src/base/types.hh
+++ b/src/base/types.hh
@@ -42,10 +42,6 @@
 #include 
 #include 

-#include "base/refcnt.hh"
-/* Hide the fact that this enum is generated by Python */
-#include "enums/ByteOrder.hh"
-
 /** uint64_t constant */
 #define ULL(N)  ((uint64_t)N##ULL)
 /** int64_t constant */
@@ -100,35 +96,45 @@
 constexpr operator uint64_t() const { return c; }

 /** Prefix increment operator. */
-Cycles& operator++()
-{ ++c; return *this; }
+Cycles& operator++() { ++c; return *this; }

 /** Prefix decrement operator. Is only temporarily used in the O3 CPU.  
*/

-Cycles& operator--()
-{ assert(c != 0); --c; return *this; }
+Cycles& 

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Moving ExceptionCode to registers.hh for reusability

[Peter Yuen (Gerrit) via gem5-dev]

Peter Yuen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39955 )



Change subject: arch-riscv: Moving ExceptionCode to registers.hh for  
reusability

..

arch-riscv: Moving ExceptionCode to registers.hh for reusability

The ExceptionCode enum was originally defined in faults.hh. However,
it can actually be reused in registers.hh were interrupt bit locations
were previously hardcoded. I hence suggest moving the ExceptionCode
enum definition to registers.hh and have made the replacements for
the bit locations.

Change-Id: I9475f362b98b2a438786b39f6c0da4fb0e68aa02
---
M src/arch/riscv/faults.hh
M src/arch/riscv/registers.hh
2 files changed, 61 insertions(+), 58 deletions(-)



diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index 5e24da2..a078662 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -49,46 +49,6 @@
 FloatInvalid = 0x10
 };

-/*
- * In RISC-V, exception and interrupt codes share some values. They can be
- * differentiated by an 'Interrupt' flag that is enabled for interrupt  
faults

- * but not exceptions. The full fault cause can be computed by placing the
- * exception (or interrupt) code in the least significant bits of the CAUSE
- * CSR and then setting the highest bit of CAUSE with the 'Interrupt' flag.
- * For more details on exception causes, see Chapter 3.1.20 of the RISC-V
- * privileged specification v 1.10. Codes are enumerated in Table 3.6.
- */
-enum ExceptionCode : uint64_t {
-INST_ADDR_MISALIGNED = 0,
-INST_ACCESS = 1,
-INST_ILLEGAL = 2,
-BREAKPOINT = 3,
-LOAD_ADDR_MISALIGNED = 4,
-LOAD_ACCESS = 5,
-STORE_ADDR_MISALIGNED = 6,
-AMO_ADDR_MISALIGNED = 6,
-STORE_ACCESS = 7,
-AMO_ACCESS = 7,
-ECALL_USER = 8,
-ECALL_SUPER = 9,
-ECALL_MACHINE = 11,
-INST_PAGE = 12,
-LOAD_PAGE = 13,
-STORE_PAGE = 15,
-AMO_PAGE = 15,
-
-INT_SOFTWARE_USER = 0,
-INT_SOFTWARE_SUPER = 1,
-INT_SOFTWARE_MACHINE = 3,
-INT_TIMER_USER = 4,
-INT_TIMER_SUPER = 5,
-INT_TIMER_MACHINE = 7,
-INT_EXT_USER = 8,
-INT_EXT_SUPER = 9,
-INT_EXT_MACHINE = 11,
-NumInterruptTypes
-};
-
 class RiscvFault : public FaultBase
 {
   protected:
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 9721635..2ba5d2c 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -93,8 +93,11 @@
 const int ZeroReg = 0;
 const int ReturnAddrReg = 1;
 const int StackPointerReg = 2;
+const int GlobalPointerReg = 3;
 const int ThreadPointerReg = 4;
+const int FramePointerReg = 8;
 const int ReturnValueReg = 10;
+const std::vector ReturnValueRegs = {10, 11};
 const std::vector ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17};
 const int AMOTempReg = 32;

@@ -616,6 +619,46 @@
 Bitfield<0> uie;
 EndBitUnion(STATUS)

+/*
+ * In RISC-V, exception and interrupt codes share some values. They can be
+ * differentiated by an 'Interrupt' flag that is enabled for interrupt  
faults

+ * but not exceptions. The full fault cause can be computed by placing the
+ * exception (or interrupt) code in the least significant bits of the CAUSE
+ * CSR and then setting the highest bit of CAUSE with the 'Interrupt' flag.
+ * For more details on exception causes, see Chapter 3.1.20 of the RISC-V
+ * privileged specification v 1.10. Codes are enumerated in Table 3.6.
+ */
+enum ExceptionCode : uint64_t {
+INST_ADDR_MISALIGNED = 0,
+INST_ACCESS = 1,
+INST_ILLEGAL = 2,
+BREAKPOINT = 3,
+LOAD_ADDR_MISALIGNED = 4,
+LOAD_ACCESS = 5,
+STORE_ADDR_MISALIGNED = 6,
+AMO_ADDR_MISALIGNED = 6,
+STORE_ACCESS = 7,
+AMO_ACCESS = 7,
+ECALL_USER = 8,
+ECALL_SUPER = 9,
+ECALL_MACHINE = 11,
+INST_PAGE = 12,
+LOAD_PAGE = 13,
+STORE_PAGE = 15,
+AMO_PAGE = 15,
+
+INT_SOFTWARE_USER = 0,
+INT_SOFTWARE_SUPER = 1,
+INT_SOFTWARE_MACHINE = 3,
+INT_TIMER_USER = 4,
+INT_TIMER_SUPER = 5,
+INT_TIMER_MACHINE = 7,
+INT_EXT_USER = 8,
+INT_EXT_SUPER = 9,
+INT_EXT_MACHINE = 11,
+NumInterruptTypes
+};
+
 /**
  * These fields are specified in the RISC-V Instruction Set Manual, Volume  
II,
  * v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. Both the  
MIP

@@ -623,15 +666,15 @@
  * this bit union.
  */
 BitUnion64(INTERRUPT)
-Bitfield<11> mei;
-Bitfield<9> sei;
-Bitfield<8> uei;
-Bitfield<7> mti;
-Bitfield<5> sti;
-Bitfield<4> uti;
-Bitfield<3> msi;
-Bitfield<1> ssi;
-Bitfield<0> usi;
+Bitfield mei;
+Bitfield sei;
+Bitfield uei;
+Bitfield mti;
+Bitfield sti;
+Bitfield uti;
+Bitfield msi;
+Bitfield ssi;
+Bitfield usi;
 EndBitUnion(INTERRUPT)

 const off_t MXL_OFFSET = (sizeof(uint64_t) * 8 - 2);
@@ -685,15 +728,15 @@
 STATUS_FS_MASK | STATUS_UPIE_MASK |
 

[gem5-dev] Change in gem5/gem5[develop]: cpu,configs: Add DMA thread to Ruby GPU tester

[Matthew Poremba (Gerrit) via gem5-dev]

Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39936 )



Change subject: cpu,configs: Add DMA thread to Ruby GPU tester
..

cpu,configs: Add DMA thread to Ruby GPU tester

Add a DMA thread tester to the Ruby GPU tester to test the DMA state
machine in the protocol. Currently creates a dummy DMA device to pass
through Ruby.py and scans for the DMA sequencers due to opaqueness of
Ruby.py.

DMA atomics not yet supported as there is no protocol that implements
atomic transitions in the DMA state machine file.

Example run command:
build/GCN3_X86/gem5.opt configs/example/ruby_gpu_random_test.py \
--test-length=1000

Change-Id: I63d83e00fd0dcbb1e34c6704d1c2d49ed4e77722
---
M configs/example/ruby_gpu_random_test.py
A src/cpu/testers/gpu_ruby_test/DmaThread.py
M src/cpu/testers/gpu_ruby_test/ProtocolTester.py
M src/cpu/testers/gpu_ruby_test/SConscript
A src/cpu/testers/gpu_ruby_test/TesterDma.py
A src/cpu/testers/gpu_ruby_test/dma_thread.cc
A src/cpu/testers/gpu_ruby_test/dma_thread.hh
M src/cpu/testers/gpu_ruby_test/protocol_tester.cc
M src/cpu/testers/gpu_ruby_test/protocol_tester.hh
A src/cpu/testers/gpu_ruby_test/tester_dma.cc
A src/cpu/testers/gpu_ruby_test/tester_dma.hh
M src/cpu/testers/gpu_ruby_test/tester_thread.cc
12 files changed, 667 insertions(+), 17 deletions(-)



diff --git a/configs/example/ruby_gpu_random_test.py  
b/configs/example/ruby_gpu_random_test.py

index ae4ff0b..74f3282 100644
--- a/configs/example/ruby_gpu_random_test.py
+++ b/configs/example/ruby_gpu_random_test.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2018-2020 Advanced Micro Devices, Inc.
+# Copyright (c) 2018-2021 Advanced Micro Devices, Inc.
 # All rights reserved.
 #
 # For use for simulation and test purposes only
@@ -81,6 +81,8 @@
   help="Random seed number. Default value (i.e., 0) means \
 using runtime-specific value")
 parser.add_option("--log-file", type="string", default="gpu-ruby-test.log")
+parser.add_option("--num-dmas", type="int", default=0,
+  help="The number of DMA engines to use in tester  
config.")


 (options, args) = parser.parse_args()

@@ -112,6 +114,7 @@
 options.wf_size = 1
 options.wavefronts_per_cu = 1
 options.num_cpus = 1
+options.num_dmas = 1
 options.cu_per_sqc = 1
 options.cu_per_scalar_cache = 1
 options.num_compute_units = 1
@@ -120,6 +123,7 @@
 options.wf_size = 16
 options.wavefronts_per_cu = 4
 options.num_cpus = 4
+options.num_dmas = 2
 options.cu_per_sqc = 4
 options.cu_per_scalar_cache = 4
 options.num_compute_units = 4
@@ -128,6 +132,7 @@
 options.wf_size = 32
 options.wavefronts_per_cu = 4
 options.num_cpus = 4
+options.num_dmas = 4
 options.cu_per_sqc = 4
 options.cu_per_scalar_cache = 4
 options.num_compute_units = 8
@@ -174,6 +179,9 @@
 # For now we're testing only GPU protocol, so we force num_cpus to be 0
 options.num_cpus = 0

+# Number of DMA engines
+n_DMAs = options.num_dmas
+
 # Number of CUs
 n_CUs = options.num_compute_units

@@ -230,9 +238,18 @@
 options.num_cp = 0

 #
+# Make generic DMA sequencer for Ruby to use
+#
+dma_devices = [TesterDma()] * n_DMAs
+system.piobus = IOXBar()
+for _, dma_device in enumerate(dma_devices):
+dma_device.pio = system.piobus.mem_side_ports
+system.dma_devices = dma_devices
+
+#
 # Create the Ruby system
 #
-Ruby.create_system(options, False, system)
+Ruby.create_system(options, False, system, None, system.dma_devices)

 #
 # The tester is most effective when randomization is turned on and
@@ -256,6 +273,7 @@
 for i, ruby_port in enumerate(system.ruby._cpu_ports):
 ruby_port.no_retry_on_stall = True
 ruby_port.using_ruby_tester = True
+ruby_port.mem_request_port = system.piobus.cpu_side_ports

 if i < n_CUs:
 tester.cu_vector_ports = ruby_port.in_ports
@@ -269,17 +287,44 @@
 i += 1

 #
-# No CPU threads are needed for GPU tester
+# Attach DMA ports. Since Ruby.py doesn't return these they need to be  
found.
+# Connect tester's request port to each DMA sequencer's in_ports. This  
assumes

+# the protocol names these system.dma_cntrl<#>.
+#
+dma_ports = []
+for i in range(n_DMAs):
+exec('dma_ports.append(system.dma_cntrl%d.dma_sequencer.in_ports)' % i)
+tester.dma_ports = dma_ports
+
+#
+# Common variables for all types of threads
+#
+thread_clock = SrcClockDomain(clock = '1GHz',
+  voltage_domain = system.voltage_domain)
+g_thread_idx = 0
+
+#
+# No CPU threads are used for GPU tester
 #
 tester.cpu_threads = []

 #
+# Create DMA threads
+#
+dma_threads = []
+print("Creating %i DMAs" % n_DMAs)
+for dma_idx in range(n_DMAs):
+dma_threads.append(DmaThread(thread_id = g_thread_idx,
+ num_lanes = 1, clk_domain = thread_clock,
+ deadlock_threshold = \
+ 

[gem5-dev] Change in gem5/gem5[develop]: cpu: Rename GpuThread in gpu_ruby_test tester

[Matthew Poremba (Gerrit) via gem5-dev]

Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39935 )



Change subject: cpu: Rename GpuThread in gpu_ruby_test tester
..

cpu: Rename GpuThread in gpu_ruby_test tester

The GpuThread class will be used as an abstract class for any thread
type (CPU, GPU, DMA) therefore changing to a more appropriate name.

Change-Id: If241edb53ea405c95b0315c609176c6470b29931
---
M src/cpu/testers/gpu_ruby_test/CpuThread.py
M src/cpu/testers/gpu_ruby_test/GpuWavefront.py
M src/cpu/testers/gpu_ruby_test/README
M src/cpu/testers/gpu_ruby_test/SConscript
R src/cpu/testers/gpu_ruby_test/TesterThread.py
M src/cpu/testers/gpu_ruby_test/address_manager.hh
M src/cpu/testers/gpu_ruby_test/cpu_thread.cc
M src/cpu/testers/gpu_ruby_test/cpu_thread.hh
M src/cpu/testers/gpu_ruby_test/episode.cc
M src/cpu/testers/gpu_ruby_test/episode.hh
M src/cpu/testers/gpu_ruby_test/gpu_wavefront.cc
M src/cpu/testers/gpu_ruby_test/gpu_wavefront.hh
M src/cpu/testers/gpu_ruby_test/protocol_tester.cc
M src/cpu/testers/gpu_ruby_test/protocol_tester.hh
R src/cpu/testers/gpu_ruby_test/tester_thread.cc
R src/cpu/testers/gpu_ruby_test/tester_thread.hh
16 files changed, 95 insertions(+), 95 deletions(-)



diff --git a/src/cpu/testers/gpu_ruby_test/CpuThread.py  
b/src/cpu/testers/gpu_ruby_test/CpuThread.py

index 7124a32..8cb3269 100644
--- a/src/cpu/testers/gpu_ruby_test/CpuThread.py
+++ b/src/cpu/testers/gpu_ruby_test/CpuThread.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2017-2020 Advanced Micro Devices, Inc.
+# Copyright (c) 2017-2021 Advanced Micro Devices, Inc.
 # All rights reserved.
 #
 # For use for simulation and test purposes only
@@ -32,8 +32,8 @@
 from m5.params import *
 from m5.proxy import *

-from m5.objects.GpuThread import GpuThread
+from m5.objects.TesterThread import TesterThread

-class CpuThread(GpuThread):
+class CpuThread(TesterThread):
 type = 'CpuThread'
 cxx_header = "cpu/testers/gpu_ruby_test/cpu_thread.hh"
diff --git a/src/cpu/testers/gpu_ruby_test/GpuWavefront.py  
b/src/cpu/testers/gpu_ruby_test/GpuWavefront.py

index a54870f..d8d7dae 100644
--- a/src/cpu/testers/gpu_ruby_test/GpuWavefront.py
+++ b/src/cpu/testers/gpu_ruby_test/GpuWavefront.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2017-2020 Advanced Micro Devices, Inc.
+# Copyright (c) 2017-2021 Advanced Micro Devices, Inc.
 # All rights reserved.
 #
 # For use for simulation and test purposes only
@@ -32,9 +32,9 @@
 from m5.params import *
 from m5.proxy import *

-from m5.objects.GpuThread import GpuThread
+from m5.objects.TesterThread import TesterThread

-class GpuWavefront(GpuThread):
+class GpuWavefront(TesterThread):
 type = 'GpuWavefront'
 cxx_header = "cpu/testers/gpu_ruby_test/gpu_wavefront.hh"
 cu_id = Param.Int("Compute Unit ID")
diff --git a/src/cpu/testers/gpu_ruby_test/README  
b/src/cpu/testers/gpu_ruby_test/README

index 5627f43..390b503 100644
--- a/src/cpu/testers/gpu_ruby_test/README
+++ b/src/cpu/testers/gpu_ruby_test/README
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2020 Advanced Micro Devices, Inc.
+ * Copyright (c) 2017-2021 Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * For use for simulation and test purposes only
@@ -113,11 +113,11 @@
 location, generates locations for all episodes,
 maintains per-location last writer and validates
 values returned from load actions.
-GpuThread.hh/cc -- This is abstract class for CPU threads and GPU
+TesterThread.hh/cc   -- This is abstract class for CPU threads and GPU
 wavefronts. It generates and executes a series of
 episodes.
 CpuThread.hh/cc  -- Thread class for CPU threads. Not fully  
implemented yet

-GpuWavefront.hh/cc   -- GpuThread class for GPU wavefronts.
+GpuWavefront.hh/cc   -- Thread class for GPU wavefronts.
 Episode.hh/cc-- Class to encapsulate an episode, notably including
 episode load/store structure and ordering.

diff --git a/src/cpu/testers/gpu_ruby_test/SConscript  
b/src/cpu/testers/gpu_ruby_test/SConscript

index d801130..28c8006 100644
--- a/src/cpu/testers/gpu_ruby_test/SConscript
+++ b/src/cpu/testers/gpu_ruby_test/SConscript
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2017-2020 Advanced Micro Devices, Inc.
+# Copyright (c) 2017-2021 Advanced Micro Devices, Inc.
 # All rights reserved.
 #
 # For use for simulation and test purposes only
@@ -40,15 +40,15 @@
 Return()

 SimObject('ProtocolTester.py')
-SimObject('GpuThread.py')
 SimObject('CpuThread.py')
 SimObject('GpuWavefront.py')
+SimObject('TesterThread.py')

 Source('address_manager.cc')
 Source('episode.cc')
 Source('protocol_tester.cc')
-Source('gpu_thread.cc')
 Source('cpu_thread.cc')
 Source('gpu_wavefront.cc')
+Source('tester_thread.cc')

 DebugFlag('ProtocolTest')
diff --git a/src/cpu/testers/gpu_ruby_test/GpuThread.py  

[gem5-dev] Change in gem5/gem5[develop]: cpu: Implement DMA atomic issue in Ruby GPU tester

[Matthew Poremba (Gerrit) via gem5-dev]

Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39937 )



Change subject: cpu: Implement DMA atomic issue in Ruby GPU tester
..

cpu: Implement DMA atomic issue in Ruby GPU tester

This adds the ability to generatic atomic DMA requests using the Ruby
GPU tester.

Change-Id: I2142816b4601229877bb6968cd8ceef54029fa00
---
M src/cpu/testers/gpu_ruby_test/dma_thread.cc
1 file changed, 36 insertions(+), 1 deletion(-)



diff --git a/src/cpu/testers/gpu_ruby_test/dma_thread.cc  
b/src/cpu/testers/gpu_ruby_test/dma_thread.cc

index 254158d..0da3590 100644
--- a/src/cpu/testers/gpu_ruby_test/dma_thread.cc
+++ b/src/cpu/testers/gpu_ruby_test/dma_thread.cc
@@ -174,7 +174,42 @@
 assert(pendingLdStCount == 0);
 assert(pendingAtomicCount == 0);

-// no-op: No DMA protocol exists with Atomics
+Request::Flags flags = Request::ATOMIC_RETURN_OP;
+int lane = 0;
+
+Location location = curAction->getLocation(lane);
+assert(location >= 0);
+
+Addr address = addrManager->getAddress(location);
+
+DPRINTF(ProtocolTest, "%s Episode %d: Issuing Atomic_Inc - Addr %s\n",
+this->getName(), curEpisode->getEpisodeId(),
+printAddress(address));
+
+// must be aligned with store size
+assert(address % sizeof(Value) == 0);
+AtomicOpFunctor *amo_op = new AtomicOpInc();
+auto req = std::make_shared(address, sizeof(Value),
+ flags, tester->requestorId(),
+ 0, threadId,
+ AtomicOpFunctorPtr(amo_op));
+req->setPaddr(address);
+req->setReqInstSeqNum(tester->getActionSeqNum());
+
+PacketPtr pkt = new Packet(req, MemCmd::SwapReq);
+uint8_t* data = new uint8_t[sizeof(Value)];
+pkt->dataDynamic(data);
+pkt->senderState = new ProtocolTester::SenderState(this);
+
+if (!port->sendTimingReq(pkt)) {
+panic("Not expecting failed sendTimingReq\n");
+}
+
+// add an outstanding atomic
+addOutstandingReqs(outstandingAtomics, address, lane, location);
+
+// increment the number of outstanding atomic ops
+pendingAtomicCount++;
 }

 void

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2142816b4601229877bb6968cd8ceef54029fa00
Gerrit-Change-Number: 39937
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba 
Gerrit-MessageType: newchange
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[gem5-dev] Re: Some evidence build times have substantially increased on Jenkins

[Giacomo Travaglini via gem5-dev]

P.S. A lot of other builds would have failed using today's timeout.
Check for example build #176 and #177 of the Nightly (end of December)

This makes a lot of sense as these days overlap with the Compiler-Checks run.
In fact, almost every time we run Compiler-Checks the Nightly takes more than a 
day to complete

Kind Regards

Giacomo


> -Original Message-
> From: Giacomo Travaglini via gem5-dev 
> Sent: 27 January 2021 22:23
> To: gem5 Developer List 
> Cc: Giacomo Travaglini 
> Subject: [gem5-dev] Re: Some evidence build times have substantially
> increased on Jenkins
>
> Hi Bobby,
>
> While I agree there might be something wrong with it, It can be partly
> explained with the sheer amount of patches which is being reviewed and
> merged in these days. This is affecting compilation time in the following 
> ways:
>
> a) Overloading Jenkins with the gem5-develop job -> this is not valid anymore
> as it has been removed
> b) By changing big portions of code, increasing recompilation time (there are
> more translation units to be recompiled)
>
> If I have a look at the Jenkins history for example, most of the Nightlies at 
> the
> beginning of the month had almost no patches
>
> Nighly #180 for example took 13 hours but as you can see had no patches
>
> https://jenkins.gem5.org/job/Nightly/180/
>
> The first run that was testing more than two patches is #183
>
> https://jenkins.gem5.org/job/Nightly/184/
>
> And in fact it took 1 day and two hours to complete. This would have failed
> with the current setup of timing out in 23 hours.
> If you compare #patches with execution time you see a strong correlation
> between these two
>
> Same applies with the compiler check. Now situation is to get a bit better, 
> but
> IMHO in the last few days the combination of a) + b) has been lethal.
>
> There might be something else though
>
> Kind Regards
>
> Giacomo
>
> > -Original Message-
> > From: Bobby Bruce via gem5-dev 
> > Sent: 27 January 2021 21:00
> > To: gem5 Developer List 
> > Cc: Bobby Bruce 
> > Subject: [gem5-dev] Some evidence build times have substantially
> > increased on Jenkins
> >
> > Dear all,
> >
> > As you may have noticed from the mailing list, our nightly builds are
> > failing due to timeouts, as are the compiler checkers. Though this is
> > just a preliminary look at the problem, I've noticed that the gem5
> > build times on our Jenkins have increased substantially. Looking at
> > our last passing compiler checks, gem5 compiled in roughly 1.5 hours:
> > http://jenkins.gem5.org/job/Compiler-
> > Checks/40/. Looking at our first failing compiler checks, this has
> > jumped to roughly 3.5 hours: http://jenkins.gem5.org/job/Compiler-
> Checks/41/.
> >
> > This is just an FYI and a reachout to see if anyone has any ideas why
> > this might be. I'm currently looking to see if I can replicate these
> > poor compile times outside of Jenkins. I have noticed that our Gerrit
> > Kokoro appears to have continued running just fine (no timeouts), so
> > this may be some issue specific to our Jenkins setup.
> >
> >
> > Kind regards,
> > Bobby
> >
> > --
> >
> > Dr. Bobby R. Bruce
> > Room 2235,
> > Kemper Hall, UC Davis
> > Davis,
> > CA, 95616
> >
> >
> > web: https://www.bobbybruce.net
>
> IMPORTANT NOTICE: The contents of this email and any attachments are
> confidential and may also be privileged. If you are not the intended 
> recipient,
> please notify the sender immediately and do not disclose the contents to any
> other person, use it for any purpose, or store or copy the information in any
> medium. Thank you.
> ___
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[gem5-dev] Re: Some evidence build times have substantially increased on Jenkins

[Giacomo Travaglini via gem5-dev]

Hi Bobby,

While I agree there might be something wrong with it, It can be partly 
explained with the sheer amount of patches which
is being reviewed and merged in these days. This is affecting compilation time 
in the following ways:

a) Overloading Jenkins with the gem5-develop job -> this is not valid anymore 
as it has been removed
b) By changing big portions of code, increasing recompilation time (there are 
more translation units to be recompiled)

If I have a look at the Jenkins history for example, most of the Nightlies at 
the beginning of the month had almost no patches

Nighly #180 for example took 13 hours but as you can see had no patches

https://jenkins.gem5.org/job/Nightly/180/

The first run that was testing more than two patches is #183

https://jenkins.gem5.org/job/Nightly/184/

And in fact it took 1 day and two hours to complete. This would have failed 
with the current setup of timing out in 23 hours.
If you compare #patches with execution time you see a strong correlation 
between these two

Same applies with the compiler check. Now situation is to get a bit better, but 
IMHO in the last few days the combination of a) + b) has been lethal.

There might be something else though

Kind Regards

Giacomo

> -Original Message-
> From: Bobby Bruce via gem5-dev 
> Sent: 27 January 2021 21:00
> To: gem5 Developer List 
> Cc: Bobby Bruce 
> Subject: [gem5-dev] Some evidence build times have substantially increased on
> Jenkins
>
> Dear all,
>
> As you may have noticed from the mailing list, our nightly builds are failing 
> due
> to timeouts, as are the compiler checkers. Though this is just a preliminary 
> look
> at the problem, I've noticed that the gem5 build times on our Jenkins have
> increased substantially. Looking at our last passing compiler checks, gem5
> compiled in roughly 1.5 hours: http://jenkins.gem5.org/job/Compiler-
> Checks/40/. Looking at our first failing compiler checks, this has jumped to
> roughly 3.5 hours: http://jenkins.gem5.org/job/Compiler-Checks/41/.
>
> This is just an FYI and a reachout to see if anyone has any ideas why this 
> might
> be. I'm currently looking to see if I can replicate these poor compile times
> outside of Jenkins. I have noticed that our Gerrit Kokoro appears to have
> continued running just fine (no timeouts), so this may be some issue specific 
> to
> our Jenkins setup.
>
>
> Kind regards,
> Bobby
>
> --
>
> Dr. Bobby R. Bruce
> Room 2235,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
>
> web: https://www.bobbybruce.net

IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium. Thank you.
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[gem5-dev] Some evidence build times have substantially increased on Jenkins

[Bobby Bruce via gem5-dev]

Dear all,

As you may have noticed from the mailing list, our nightly builds are
failing due to timeouts, as are the compiler checkers. Though this is just
a preliminary look at the problem, I've noticed that the gem5 build times
on our Jenkins have increased substantially. Looking at our last passing
compiler checks, gem5 compiled in roughly 1.5 hours:
http://jenkins.gem5.org/job/Compiler-Checks/40/. Looking at our first
failing compiler checks, this has jumped to roughly 3.5 hours:
http://jenkins.gem5.org/job/Compiler-Checks/41/.

This is just an FYI and a reachout to see if anyone has any ideas why this
might be. I'm currently looking to see if I can replicate these poor
compile times outside of Jenkins. I have noticed that our Gerrit Kokoro
appears to have continued running just fine (no timeouts), so this may be
some issue specific to our Jenkins setup.

Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net
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[gem5-dev] Change in gem5/gem5[develop]: system: Fix PCI Mem range for VExpress_GEM5_VX DTS

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39915 )



Change subject: system: Fix PCI Mem range for VExpress_GEM5_VX DTS
..

system: Fix PCI Mem range for VExpress_GEM5_VX DTS

This is addressing an issue raised in the mailing list [1]
where setting up a PCI mem bar for an ethernet device
resulted into an overlap of memory ranges:

fatal: system.iobus has two ports responding within range
[0x8000:0x8002]:
system.realview.ethernet.pio
system.iobridge.cpu_side_port

The reason for this is the following:

The PCI mem range in the DTB is using 0x4000 (3rd word) as a
starting address in the PCI domain, which is linked to 0x4000 in the
host domain.

<0x0200 0x0 0x4000  0x0 0x4000  0x0 0x4000>;

However the current mapping scheme works with simple fixed translation
So address 0x4000 in the PCI domain will be mapped to 0x4000 +
0x4000 = 0x8000, which is where DRAM starts

This is aligning with DTB autogeneration, which is setting up a
PCI mem range starting at PCI address = 0 [2]

[1]: https://www.mail-archive.com/gem5-users@gem5.org/msg18941.html
[2]:  
https://github.com/gem5/gem5/blob/v20.1.0.0/src/dev/arm/RealView.py#L161


Change-Id: I4538511453cfd5143fb4613a080780dc86b2244c
Signed-off-by: Giacomo Travaglini 
---
M system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi
M system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi
2 files changed, 4 insertions(+), 4 deletions(-)



diff --git a/system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi

index a84e8e3..2a56150 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi
@@ -66,8 +66,8 @@

reg = <0x0 0x3000 0x0 0x1000>;

-   ranges = <0x0100 0x0 0x  0x0 0x2f00  0x0 
0x0001>,
-<0x0200 0x0 0x4000  0x0 0x4000  0x0 
0x4000>;
+   ranges = <0x0100 0x0 0x0  0x0 0x2f00  0x0 0x0001>,
+<0x0200 0x0 0x0  0x0 0x4000  0x0 0x4000>;

interrupt-map = <0x00 0x0 0x0 0  0 68 1>,
<0x000800 0x0 0x0 0  0 69 1>,
diff --git a/system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi

index 2ea94ac..6dbaa2c 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi
@@ -76,8 +76,8 @@

reg = <0x0 0x3000 0x0 0x1000>;

-   ranges = <0x0100 0x0 0x  0x0 0x2f00  0x0 
0x0001>,
-<0x0200 0x0 0x4000  0x0 0x4000  0x0 
0x4000>;
+   ranges = <0x0100 0x0 0x0  0x0 0x2f00  0x0 0x0001>,
+<0x0200 0x0 0x0  0x0 0x4000  0x0 0x4000>;

/*
  child unit address, #cells = #address-cells

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4538511453cfd5143fb4613a080780dc86b2244c
Gerrit-Change-Number: 39915
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: misc: Remove redundant _params

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39899 )



Change subject: misc: Remove redundant _params
..

misc: Remove redundant _params

Instead of creating yet another _params field, SimObject descendants
should use params() to expose the real type of SimObject::_params they
already have.

Change-Id: I36308e65df9ba3dafdd3fea3e3897cc3073718b4
Signed-off-by: Alexander Klimov 
---
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
M src/arch/arm/fastmodel/GIC/gic.cc
M src/arch/arm/fastmodel/GIC/gic.hh
M src/arch/arm/freebsd/se_workload.hh
M src/arch/arm/linux/se_workload.hh
M src/arch/arm/se_workload.hh
M src/arch/mips/linux/se_workload.hh
M src/arch/mips/se_workload.hh
M src/arch/power/linux/se_workload.hh
M src/arch/power/se_workload.hh
M src/arch/riscv/linux/se_workload.hh
M src/arch/riscv/se_workload.hh
M src/arch/sparc/linux/se_workload.cc
M src/arch/sparc/linux/se_workload.hh
M src/arch/x86/linux/se_workload.cc
M src/arch/x86/linux/se_workload.hh
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu.hh
M src/dev/arm/base_gic.cc
M src/dev/arm/base_gic.hh
M src/dev/arm/generic_timer.cc
M src/sim/kernel_workload.cc
M src/sim/kernel_workload.hh
M src/sim/se_workload.cc
M src/sim/se_workload.hh
M src/sim/sim_object.hh
M src/sim/system.cc
M src/sim/system.hh
M src/sim/workload.hh
32 files changed, 46 insertions(+), 144 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc

index d2b9676..58426fb 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -99,7 +99,7 @@
 }

 CortexA76Cluster::CortexA76Cluster(const Params ) :
-SimObject(p), _params(p), cores(p.cores), evs(p.evs)
+SimObject(p), cores(p.cores), evs(p.evs)
 {
 for (int i = 0; i < p.cores.size(); i++)
 p.cores[i]->setCluster(this, i);
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh

index 68ff1a8..542b8bb 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
@@ -52,18 +52,15 @@
 class CortexA76 : public Iris::CPU
 {
   protected:
-typedef FastModelCortexA76Params Params;
 typedef Iris::CPU Base;
-const Params &_params;

 CortexA76Cluster *cluster = nullptr;
 int num = 0;

-const Params () { return _params; }
-
   public:
+PARAMS(FastModelCortexA76);
 CortexA76(const Params ) :
-Base(p, scx::scx_get_iris_connection_interface()), _params(p)
+Base(p, scx::scx_get_iris_connection_interface())
 {}

 void
@@ -93,13 +90,11 @@
 class CortexA76Cluster : public SimObject
 {
   private:
-typedef FastModelCortexA76ClusterParams Params;
-const Params &_params;
-
 std::vector cores;
 sc_core::sc_module *evs;

   public:
+PARAMS(FastModelCortexA76Cluster);
 template 
 void
 set_evs_param(const std::string , T val)
@@ -111,7 +106,6 @@
 sc_core::sc_module *getEvs() const { return evs; }

 CortexA76Cluster(const Params );
-const Params () { return _params; }

 Port (const std::string _name,
 PortID idx=InvalidPortID) override;
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc  
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc

index 18bb33d..84fce1a 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -94,7 +94,7 @@
 }

 CortexR52Cluster::CortexR52Cluster(const Params ) :
-SimObject(p), _params(p), cores(p.cores), evs(p.evs)
+SimObject(p), cores(p.cores), evs(p.evs)
 {
 for (int i = 0; i < p.cores.size(); i++)
 p.cores[i]->setCluster(this, i);
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh  
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh

index 8332066..bf19e51 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
@@ -52,18 +52,15 @@
 class CortexR52 : public Iris::CPU
 {
   protected:
-typedef FastModelCortexR52Params Params;
 typedef Iris::CPU Base;
-const Params &_params;

 CortexR52Cluster *cluster = nullptr;
 int num = 0;

-const Params () { return _params; }
-
   public:
+PARAMS(FastModelCortexR52);
 CortexR52(const Params ) :
-Base(p, scx::scx_get_iris_connection_interface()), _params(p)
+Base(p, scx::scx_get_iris_connection_interface())
 {}

 template 
@@ -78,9 +75,6 @@
 class CortexR52Cluster : public SimObject
 {
   private:
-typedef FastModelCortexR52ClusterParams Params;
-const Params &_params;
-
 std::vector cores;
 sc_core::sc_module *evs;

@@ -95,8 +89,8 @@
 

[gem5-dev] Change in gem5/gem5[develop]: sim: Define PARAMS macro utility

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39898 )



Change subject: sim: Define PARAMS macro utility
..

sim: Define PARAMS macro utility

To reduce code duplication and to ensure that the result of [1] will not
deteriorate, define a macro to be used in every descendant of SimObject
that needs its own params().

[1] 91d83cc8a12883f2d7493b37f50487cd7f03a9e6

Change-Id: I1a1a0dedf91ae228ea27b8ed324577ee3439ea68
Signed-off-by: Alexander Klimov 
---
M src/sim/sim_object.hh
1 file changed, 16 insertions(+), 1 deletion(-)



diff --git a/src/sim/sim_object.hh b/src/sim/sim_object.hh
index a75f8dd..1e1d553 100644
--- a/src/sim/sim_object.hh
+++ b/src/sim/sim_object.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -314,6 +314,21 @@
 static SimObject *find(const char *name);
 };

+/* Add PARAMS(ClassName) to every descendant of SimObject that needs
+ * params.
+ *
+ * Strictly speaking, we need static_cast here, because the types are
+ * related by inheritance, but since the target type may be
+ * incomplete, the compiler does not know the relation.
+ */
+#define PARAMS(type) \
+using Params = type ## Params;   \
+const Params &   \
+params() const   \
+{\
+return reinterpret_cast(_params); \
+}
+
 /**
  * Base class to wrap object resolving functionality.
  *

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I1a1a0dedf91ae228ea27b8ed324577ee3439ea68
Gerrit-Change-Number: 39898
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: implement POPCNT instruction.

[Tong Shen (Gerrit) via gem5-dev]

Tong Shen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39615 )


Change subject: arch-x86: implement POPCNT instruction.
..

arch-x86: implement POPCNT instruction.

Change-Id: Id6ddc1245c81a17720885f9038d55d0811ef7f4d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39615
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/x86/decoder_tables.cc
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py
M src/arch/x86/isa/microops/regop.isa
4 files changed, 31 insertions(+), 4 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/x86/decoder_tables.cc b/src/arch/x86/decoder_tables.cc
index 7ee5e01..db749cf 100644
--- a/src/arch/x86/decoder_tables.cc
+++ b/src/arch/x86/decoder_tables.cc
@@ -115,7 +115,7 @@
 /*  8 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
 /*  9 */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1,
 /*  A */ 0 , 0 , 0 , 1 , 1 , 1 , 1 , 1 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 1,
-/*  B */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 0 , 0 , 1 , 1 , 1 , 1 , 1 , 1,
+/*  B */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 0 , 1 , 1 , 1 , 1 , 1 , 1,
 /*  C */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
 /*  D */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1,
 /*  E */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1,
@@ -234,7 +234,7 @@
 /*  8 */ ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW,
 /*  9 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
 /*  A */ 0 , 0 , 0 , 0 , BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , BY, 0 , 0 , 0 ,
-/*  B */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , ZW, 0 , BY, 0 , 0 , 0 , 0 , 0 ,
+/*  B */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , BY, 0 , 0 , 0 , 0 , 0 ,
 /*  C */ 0 , 0 , BY, 0 , BY, BY, BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
 /*  D */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
 /*  E */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa  
b/src/arch/x86/isa/decoder/two_byte_opcodes.isa

index f70e7bd..fe8a2bc 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -754,8 +754,7 @@
 }
 0x17: decode OPCODE_OP_BOTTOM3 {
 0x0: decode LEGACY_REP {
-0x0: WarnUnimpl::jmpe_Jz();
-0x1: WarnUnimpl::popcnt_Gv_Ev();
+0x1: POPCNT(Gv,Ev);
 }
 //0x1: group10_UD2();
 0x1: UD2();
diff --git  
a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py  
b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py

index a755d25..05bd3c4 100644
--- a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py
+++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py
@@ -350,4 +350,19 @@
 end:
 fault "NoFault"
 };
+
+def macroop POPCNT_R_R {
+popcnt reg, regm, reg, dataSize=8
+};
+
+def macroop POPCNT_R_M {
+ld t1, seg, sib, disp
+popcnt reg, t1, reg, dataSize=8
+};
+
+def macroop POPCNT_R_P {
+rdip t7
+ld t1, seg, riprel, disp
+popcnt reg, t1, reg, dataSize=8
+};
 '''
diff --git a/src/arch/x86/isa/microops/regop.isa  
b/src/arch/x86/isa/microops/regop.isa

index c465dcc..570c084 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -1764,4 +1764,17 @@
 code = '''
 DestReg = X86ISA::convX87TagsToXTags(FTW);
 '''
+
+class Popcnt(RegOp):
+code = '''
+DestReg =
+merge(DestReg, __builtin_popcountl(psrc1), dataSize);
+'''
+flag_code = '''
+ccFlagBits = ccFlagBits & ~(SFBit | AFBit | ZFBit | PFBit);
+if (findZero(dataSize * 8, SrcReg1)) {
+ccFlagBits = ccFlagBits | ZFBit;
+}
+cfofBits = cfofBits & ~(OFBit | CFBit);
+'''
 }};

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id6ddc1245c81a17720885f9038d55d0811ef7f4d
Gerrit-Change-Number: 39615
Gerrit-PatchSet: 4
Gerrit-Owner: Tong Shen 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Tong Shen 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: misc: Improve robustness of sfdisk parsing in util/gem5img.py

[Richard Cooper (Gerrit) via gem5-dev]

Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39896 )



Change subject: misc: Improve robustness of sfdisk parsing in  
util/gem5img.py

..

misc: Improve robustness of sfdisk parsing in util/gem5img.py

The format of the output of sfdisk can change between versions, and
can also change depending on the details of the disk image being
analysed. For example, extra attributes like grain size in the
preamble have been observed.

The current output parsing is quite brittle, expecting a specific
number of lines of preamble. This change switches to a regular
expression based method which searches the output for the line of
interest. The parsing will still be sensitive to changes in the output
of sfdisk, but hopefully less so than the current method.

Change-Id: If03fe999a4986049ae20709895ec1d1b42166023
---
M util/gem5img.py
1 file changed, 37 insertions(+), 16 deletions(-)



diff --git a/util/gem5img.py b/util/gem5img.py
index e251210..f4e8351 100755
--- a/util/gem5img.py
+++ b/util/gem5img.py
@@ -2,6 +2,18 @@
 #
 # Copyright 2020 Google, Inc.
 #
+# Copyright (c) 2020 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are
 # met: redistributions of source code must retain the above copyright
@@ -38,7 +50,7 @@
 import string
 from subprocess import CalledProcessError, Popen, PIPE, STDOUT
 from sys import exit, argv
-
+import re

 # Some constants.
 MaxLBACylinders = 16383
@@ -161,22 +173,31 @@
 if returncode != 0:
 print(out)
 exit(returncode)
+
+# Parse each line of the sfdisk output looking for the first
+# partition description.
+SFDISK_PARTITION_INFO_RE = re.compile(
+r"^\s*"# Start of line
+r"(?P\S+)"   # Name
+r"\s*:\s*" # Separator
+r"start=\s*(?P\d+),\s*" # Partition start record
+r"size=\s*(?P\d+),\s*"   # Partition size record
+r"type=(?P\d+)"  # Partition type record
+r"\s*$"# End of line
+)
 lines = out.splitlines()
-# Make sure the first few lines of the output look like what we expect.
-assert(lines[0][0] == '#' or lines[0].startswith('label:'))
-assert(lines[1] == 'unit: sectors' or lines[1].startswith('label-id:'))
-assert(lines[2] == '' or lines[2].startswith('device:'))
-if lines[0][0] == '#' :
-# Parsing an 'old style' dump oputput
-# Line 4 has information about the first partition.
-chunks = lines[3].split()
-else :
-# Parsing a 'new style' dump oputput
-# Line 6 has information about the first partition.
-chunks = lines[5].split()
-# The fourth chunk is the offset of the partition in sectors followed  
by

-# a comma. We drop the comma and convert that to an integer.
-sectors = string.atoi(chunks[3][:-1])
+for line in lines :
+match = SFDISK_PARTITION_INFO_RE.match(line)
+if match:
+sectors = int(match.group("start"))
+break
+else:
+# No partition description was found
+print("No partition description was found in sfdisk output:")
+print("\n".join("  {}".format(line.rstrip()) for line in lines))
+print("Could not determine size of first partition.")
+exit(1)
+
 # Free the loopback device and return an answer.
 dev.destroy()
 return sectors * BlockSize

--
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Gerrit-Branch: develop
Gerrit-Change-Id: If03fe999a4986049ae20709895ec1d1b42166023
Gerrit-Change-Number: 39896
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Cooper 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: misc: Fix gem5img when used to manually unmount a disk image.

[Richard Cooper (Gerrit) via gem5-dev]

Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39897 )



Change subject: misc: Fix gem5img when used to manually unmount a disk  
image.

..

misc: Fix gem5img when used to manually unmount a disk image.

When unmounting a disk image manually using the
`gem5img umount mount_point` command, the operation can fail if the
process is unable to stat any of the mounts in the mount table. On
some systems this can occur even when running using sudo.

Added an exception check so any mount points that fail to stat will not
cause the whole script to terminate early.

Change-Id: I69cd2494ad0e8c989e19ecd8af8a811905cd6c09
---
M util/gem5img.py
1 file changed, 7 insertions(+), 4 deletions(-)



diff --git a/util/gem5img.py b/util/gem5img.py
index f4e8351..e5abe79 100755
--- a/util/gem5img.py
+++ b/util/gem5img.py
@@ -210,8 +210,11 @@
 mountTable = mountTable.splitlines()
 for line in mountTable:
 chunks = line.split()
-if os.path.samefile(chunks[2], mountPoint):
-return LoopbackDevice(chunks[0])
+try:
+if os.path.samefile(chunks[2], mountPoint):
+return LoopbackDevice(chunks[0])
+except OSError:
+continue
 return None


@@ -285,8 +288,8 @@
 mountCom.func = mountComFunc

 # A command to unmount the first partition in the image.
-umountCom = Command('umount', 'Unmount the first partition in the disk  
image.',

-[('mount point', 'What mount point to unmount.')])
+umountCom = Command('umount', 'Unmount the disk image mounted at  
mount_point.',

+[('mount_point', 'What mount point to unmount.')])

 def umountComFunc(options, args):
 (mountPoint,) = args

--
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Gerrit-Change-Id: I69cd2494ad0e8c989e19ecd8af8a811905cd6c09
Gerrit-Change-Number: 39897
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Gerrit-Owner: Richard Cooper 
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[gem5-dev] Change in gem5/gem5[develop]: misc: Update util/gem5img.py to work with python3 and python2.

[Richard Cooper (Gerrit) via gem5-dev]

Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39895 )



Change subject: misc: Update util/gem5img.py to work with python3 and  
python2.

..

misc: Update util/gem5img.py to work with python3 and python2.

Tested on Ubuntu 18.04 with Python 3.6.8 and Python 2.7.15+.

Change-Id: Ic8b407ad41dc0d6d37a54a54eeef2b9156d893d6
---
M util/gem5img.py
1 file changed, 9 insertions(+), 7 deletions(-)



diff --git a/util/gem5img.py b/util/gem5img.py
index 03d1f3f..e251210 100755
--- a/util/gem5img.py
+++ b/util/gem5img.py
@@ -30,6 +30,8 @@
 # Script for managing a gem5 disk image.
 #

+from __future__ import print_function
+
 from optparse import OptionParser
 import os
 from os import environ as env
@@ -86,7 +88,7 @@
 def runCommand(command, inputVal=''):
 print("%>", ' '.join(command))
 proc = Popen(command, stdin=PIPE)
-proc.communicate(inputVal)
+proc.communicate(inputVal.encode())
 return proc.returncode

 # Run an external command and capture its output. This is intended to be
@@ -98,7 +100,7 @@
 proc = Popen(command, stderr=STDOUT,
  stdin=PIPE, stdout=PIPE)
 (out, err) = proc.communicate(inputVal)
-return (out, proc.returncode)
+return (out.decode(), proc.returncode)

 # Run a command as root, using sudo if necessary.
 def runPriv(command, inputVal=''):
@@ -120,7 +122,7 @@
 if cleanupDev:
 cleanupDev.destroy()
 exit("Unable to find program %s, check your PATH variable." %  
program)

-return string.strip(out)
+return out.strip()

 class LoopbackDevice(object):
 def __init__(self, devFile=None):
@@ -134,7 +136,7 @@
 if returncode != 0:
 print(out)
 return returncode
-self.devFile = string.strip(out)
+self.devFile = out.strip()
 command = [findProg('losetup'), self.devFile, fileName]
 if offset:
 off = findPartOffset(self.devFile, fileName, 0)
@@ -299,11 +301,11 @@
 # store to disk and which is defined to read as zero.
 fd = os.open(file, os.O_WRONLY | os.O_CREAT)
 os.lseek(fd, size - 1, os.SEEK_SET)
-os.write(fd, '\0')
+os.write(fd, b'\0')

 def newComFunc(options, args):
 (file, mb) = args
-mb = string.atoi(mb)
+mb = int(mb)
 newImage(file, mb)


@@ -366,7 +368,7 @@

 def initComFunc(options, args):
 (path, mb) = args
-mb = string.atoi(mb)
+mb = int(mb)
 newImage(path, mb)
 dev = LoopbackDevice()
 if dev.setup(path) != 0:

--
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Gerrit-Change-Id: Ic8b407ad41dc0d6d37a54a54eeef2b9156d893d6
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[gem5-dev] Build failed in Jenkins: Nightly #200

[jenkins-no-reply--- via gem5-dev]

See 

Changes:

[jiasen.hjs] configs: Added list types of replacement policy.

[gabe.black] arch-arm: Don't use TheISA in the ARM implementation.

[Andreas.Sandberg] base, python: Add a Temperature type and associated param

[Andreas.Sandberg] sim: Use the Temperature param type

[Andreas.Sandberg] python: Require a unit in anyToFrequency and anyToLatency

[gabe.black] riscv: Export the system call ABI for use in gem5 ops.


--
[...truncated 570.04 KB...]
[   OK ] ByteswapTest.swap_byte32 (0 ms)
[ RUN  ] ByteswapTest.swap_byte16
[   OK ] ByteswapTest.swap_byte16 (0 ms)
[ RUN  ] ByteswapTest.swap_byte
[   OK ] ByteswapTest.swap_byte (0 ms)
[ RUN  ] ByteswapTest.htog
[   OK ] ByteswapTest.htog (0 ms)
[ RUN  ] ByteswapTest.gtoh
[   OK ] ByteswapTest.gtoh (0 ms)
[ RUN  ] ByteswapTest.betole
[   OK ] ByteswapTest.betole (0 ms)
[ RUN  ] ByteswapTest.letobe
[   OK ] ByteswapTest.letobe (0 ms)
[--] 8 tests from ByteswapTest (0 ms total)

[--] Global test environment tear-down
[==] 8 tests from 1 test suite ran. (0 ms total)
[  PASSED  ] 8 tests.
[   OK ] UncontendedMutex.Lock (203 ms)
[ RUN  ] UncontendedMutex.HeavyContention
build/NULL/sim/guest_abi.test.prof 
--gtest_output=xml:build/NULL/unittests.prof/sim/guest_abi.test.xml
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 7 tests from 1 test suite.
[--] Global test environment set-up.
[--] 7 tests from GuestABI
[ RUN  ] GuestABI.ABI_1D_args
[   OK ] GuestABI.ABI_1D_args (0 ms)
[ RUN  ] GuestABI.ABI_Prepare
[   OK ] GuestABI.ABI_Prepare (0 ms)
[ RUN  ] GuestABI.ABI_2D_args
[   OK ] GuestABI.ABI_2D_args (0 ms)
[ RUN  ] GuestABI.ABI_TC_init
[   OK ] GuestABI.ABI_TC_init (0 ms)
[ RUN  ] GuestABI.ABI_returns
[   OK ] GuestABI.ABI_returns (1 ms)
[ RUN  ] GuestABI.dumpSimcall
[   OK ] GuestABI.dumpSimcall (0 ms)
[ RUN  ] GuestABI.isVarArgs
[   OK ] GuestABI.isVarArgs (0 ms)
[--] 7 tests from GuestABI (1 ms total)

[--] Global test environment tear-down
[==] 7 tests from 1 test suite ran. (1 ms total)
[  PASSED  ] 7 tests.
build/NULL/sim/proxy_ptr.test.prof 
--gtest_output=xml:build/NULL/unittests.prof/sim/proxy_ptr.test.xml
[   OK ] UncontendedMutex.HeavyContention (266 ms)
[--] 2 tests from UncontendedMutex (495 ms total)

[--] Global test environment tear-down
[==] 2 tests from 1 test suite ran. (496 ms total)
[  PASSED  ] 2 tests.
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 6 tests from 1 test suite.
[--] Global test environment set-up.
[--] 6 tests from ProxyPtr
[ RUN  ] ProxyPtr.Clean
[   OK ] ProxyPtr.Clean (0 ms)
[ RUN  ] ProxyPtr.Dirty
[   OK ] ProxyPtr.Dirty (0 ms)
[ RUN  ] ProxyPtr.LoadAndFlush
[   OK ] ProxyPtr.LoadAndFlush (0 ms)
[ RUN  ] ProxyPtr.ConstOperators
[   OK ] ProxyPtr.ConstOperators (0 ms)
[ RUN  ] ProxyPtr.NonConstOperators
[   OK ] ProxyPtr.NonConstOperators (0 ms)
[ RUN  ] ProxyPtr.GuestABI
[   OK ] ProxyPtr.GuestABI (0 ms)
[--] 6 tests from ProxyPtr (0 ms total)

[--] Global test environment tear-down
[==] 6 tests from 1 test suite ran. (0 ms total)
[  PASSED  ] 6 tests.
 [LINK]  -> NULL/base/temperature.test.prof
build/NULL/base/temperature.test.prof 
--gtest_output=xml:build/NULL/unittests.prof/base/temperature.test.xml
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 6 tests from 1 test suite.
[--] Global test environment set-up.
[--] 6 tests from TemperatureTest
[ RUN  ] TemperatureTest.Constructor
[   OK ] TemperatureTest.Constructor (0 ms)
[ RUN  ] TemperatureTest.Conversion
[   OK ] TemperatureTest.Conversion (0 ms)
[ RUN  ] TemperatureTest.Comparison
[   OK ] TemperatureTest.Comparison (0 ms)
[ RUN  ] TemperatureTest.BinaryOperators
[   OK ] TemperatureTest.BinaryOperators (0 ms)
[ RUN  ] TemperatureTest.AssignmentOperators
[   OK ] TemperatureTest.AssignmentOperators (0 ms)
[ RUN  ] TemperatureTest.OutStream
[   OK ] TemperatureTest.OutStream (0 ms)
[--] 6 tests from TemperatureTest (0 ms total)

[--] Global test environment tear-down
[==] 6 tests from 1 test suite ran. (0 ms total)
[  PASSED  ] 6 tests.
scons: done building targets.
*** Summary of Warnings ***
Warning: Your compiler doesn't support incremental linking and lto at the same
 time, so lto is being disabled. To force lto on anyway, use the
 --force-lto option. That will disable partial linking.
[Nightly] $ /bin/sh -xe /tmp/jenkins1351121216404634574.sh
+ pwd
+ pwd
+ pwd
+ docker run -u : --volume 

[gem5-dev] Change in gem5/gem5[develop]: arch, mem, cpu, systemc: Remove Python 2.7 glue code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39758 )


Change subject: arch, mem, cpu, systemc: Remove Python 2.7 glue code
..

arch, mem, cpu, systemc: Remove Python 2.7 glue code

Remove uses of six and from __future__ imports as they are no longer
needed.

Change-Id: Ib10d01d9398795f46eedeb91a02736f248917b6a
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39758
Reviewed-by: Gabe Black 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
Maintainer: Bobby R. Bruce 
---
M src/arch/arm/fastmodel/SConscript
M src/arch/micro_asm.py
M src/arch/micro_asm_test.py
M src/arch/x86/isa/microops/fpop.isa
M src/arch/x86/isa/microops/limmop.isa
M src/arch/x86/isa/microops/mediaop.isa
M src/arch/x86/isa/microops/regop.isa
M src/cpu/BaseCPU.py
M src/cpu/minor/MinorCPU.py
M src/cpu/o3/O3CPU.py
M src/cpu/simple/BaseSimpleCPU.py
M src/mem/qos/QoSPolicy.py
M src/mem/slicc/main.py
M src/mem/slicc/util.py
M src/systemc/tests/config.py
M src/systemc/tests/verify.py
M src/unittest/genini.py
17 files changed, 10 insertions(+), 48 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/fastmodel/SConscript  
b/src/arch/arm/fastmodel/SConscript

index f5516fa..21b3d3c 100644
--- a/src/arch/arm/fastmodel/SConscript
+++ b/src/arch/arm/fastmodel/SConscript
@@ -35,7 +35,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
 from itertools import cycle

 Import('*')
diff --git a/src/arch/micro_asm.py b/src/arch/micro_asm.py
index 53026c1..0305a02 100644
--- a/src/arch/micro_asm.py
+++ b/src/arch/micro_asm.py
@@ -24,8 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import os
 import sys
 import re
diff --git a/src/arch/micro_asm_test.py b/src/arch/micro_asm_test.py
index e34e06e..8bab7b9 100755
--- a/src/arch/micro_asm_test.py
+++ b/src/arch/micro_asm_test.py
@@ -24,8 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 from micro_asm import MicroAssembler, Combinational_Macroop, Rom_Macroop,  
Rom


 class Bah(object):
diff --git a/src/arch/x86/isa/microops/fpop.isa  
b/src/arch/x86/isa/microops/fpop.isa

index 238fa93..346f0d6 100644
--- a/src/arch/x86/isa/microops/fpop.isa
+++ b/src/arch/x86/isa/microops/fpop.isa
@@ -105,8 +105,6 @@

 let {{

-import six
-
 # Make these empty strings so that concatenating onto
 # them will always work.
 header_output = ""
@@ -199,8 +197,7 @@

 return cls

-@six.add_metaclass(FpOpMeta)
-class FpUnaryOp(X86Microop):
+class FpUnaryOp(X86Microop, metaclass=FpOpMeta):
 # This class itself doesn't act as a microop
 abstract = True

@@ -235,8 +232,7 @@
 "dataSize" : self.dataSize,
 "spm" : self.spm}

-@six.add_metaclass(FpOpMeta)
-class FpBinaryOp(X86Microop):
+class FpBinaryOp(X86Microop, metaclass=FpOpMeta):
 # This class itself doesn't act as a microop
 abstract = True

diff --git a/src/arch/x86/isa/microops/limmop.isa  
b/src/arch/x86/isa/microops/limmop.isa

index b46be03..51310b4 100644
--- a/src/arch/x86/isa/microops/limmop.isa
+++ b/src/arch/x86/isa/microops/limmop.isa
@@ -106,16 +106,12 @@
 }};

 let {{
-import six
-if six.PY3:
-long = int
-
 class LimmOp(X86Microop):
 def __init__(self, dest, imm, dataSize="env.dataSize"):
 self.className = "Limm"
 self.mnemonic = "limm"
 self.dest = dest
-if isinstance(imm, (int, long)):
+if isinstance(imm, int):
 imm = "ULL(%d)" % imm
 self.imm = imm
 self.dataSize = dataSize
@@ -145,7 +141,7 @@
 self.className = "Lfpimm"
 self.mnemonic = "lfpimm"
 self.dest = dest
-if isinstance(imm, (int, long)):
+if isinstance(imm, int):
 imm = "ULL(%d)" % imm
 elif isinstance(imm, float):
 imm = "floatToBits64(%.16f)" % imm
diff --git a/src/arch/x86/isa/microops/mediaop.isa  
b/src/arch/x86/isa/microops/mediaop.isa

index 7e5fd10..e149d44 100644
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -202,8 +202,7 @@
 return cls


-@six.add_metaclass(MediaOpMeta)
-class MediaOp(X86Microop):
+class MediaOp(X86Microop, 

[gem5-dev] Change in gem5/gem5[develop]: tests: Remove Python 2.7 glue code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39757 )


Change subject: tests: Remove Python 2.7 glue code
..

tests: Remove Python 2.7 glue code

Remove uses of six and from __future__ imports as they are no longer
needed.

Change-Id: I74b5250722abe1e202f31a9ec1d4cc04039df168
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39757
Reviewed-by: Jason Lowe-Power 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M tests/configs/gpu-ruby.py
M tests/gem5/configs/base_config.py
M tests/gem5/configs/checkpoint.py
M tests/gem5/configs/switcheroo.py
M tests/gem5/fixture.py
M tests/gem5/fs/linux/arm/run.py
M tests/gem5/memory/test.py
M tests/main.py
M tests/run.py
9 files changed, 4 insertions(+), 17 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/configs/gpu-ruby.py b/tests/configs/gpu-ruby.py
index a463fe3..b561d02 100644
--- a/tests/configs/gpu-ruby.py
+++ b/tests/configs/gpu-ruby.py
@@ -33,8 +33,6 @@
 #  Author: Brad Beckmann
 #

-from __future__ import print_function
-
 import m5
 from m5.objects import *
 from m5.defines import buildEnv
diff --git a/tests/gem5/configs/base_config.py  
b/tests/gem5/configs/base_config.py

index 5623db8..b18cecf 100644
--- a/tests/gem5/configs/base_config.py
+++ b/tests/gem5/configs/base_config.py
@@ -42,12 +42,10 @@
 from common import Options
 from common.Caches import *
 from ruby import Ruby
-from six import add_metaclass

 _have_kvm_support = 'BaseKvmCPU' in globals()

-@add_metaclass(ABCMeta)
-class BaseSystem(object):
+class BaseSystem(object, metaclass=ABCMeta):
 """Base system builder.

 This class provides some basic functionality for creating an ARM
diff --git a/tests/gem5/configs/checkpoint.py  
b/tests/gem5/configs/checkpoint.py

index a652094..3545095 100644
--- a/tests/gem5/configs/checkpoint.py
+++ b/tests/gem5/configs/checkpoint.py
@@ -33,8 +33,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 from multiprocessing import Process
 import sys
 import os
diff --git a/tests/gem5/configs/switcheroo.py  
b/tests/gem5/configs/switcheroo.py

index cb47f90..fb1db81 100644
--- a/tests/gem5/configs/switcheroo.py
+++ b/tests/gem5/configs/switcheroo.py
@@ -33,8 +33,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import m5
 import _m5
 from m5.objects import *
diff --git a/tests/gem5/fixture.py b/tests/gem5/fixture.py
index 467eb43..5ffb248 100644
--- a/tests/gem5/fixture.py
+++ b/tests/gem5/fixture.py
@@ -44,7 +44,8 @@
 import threading
 import gzip

-from six.moves import urllib
+import urllib.error
+import urllib.request

 from testlib.fixture import Fixture
 from testlib.configuration import config, constants
diff --git a/tests/gem5/fs/linux/arm/run.py b/tests/gem5/fs/linux/arm/run.py
index a0d782b..3dccebb 100644
--- a/tests/gem5/fs/linux/arm/run.py
+++ b/tests/gem5/fs/linux/arm/run.py
@@ -36,8 +36,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import sys
 import os
 import os.path
diff --git a/tests/gem5/memory/test.py b/tests/gem5/memory/test.py
index 7b839f2..db20ab5 100644
--- a/tests/gem5/memory/test.py
+++ b/tests/gem5/memory/test.py
@@ -28,7 +28,6 @@
 Test file for simple memory test
 TODO: Add stats checking
 '''
-import six

 from testlib import *

@@ -50,7 +49,7 @@


 for name, params in simple_mem_params:
-args = ['--' + key + '=' + val for key,val in six.iteritems(params)]
+args = ['--' + key + '=' + val for key,val in params.items()]

 gem5_verify_config(
 name='simple_mem_' + name,
diff --git a/tests/main.py b/tests/main.py
index 3287ef1..39717f6 100755
--- a/tests/main.py
+++ b/tests/main.py
@@ -5,7 +5,6 @@

 Discovers and runs all tests from a given root directory.
 '''
-from __future__ import print_function

 import sys
 import os
diff --git a/tests/run.py b/tests/run.py
index a8b612b..c3360ac 100644
--- a/tests/run.py
+++ b/tests/run.py
@@ -36,8 +36,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import os
 import sys
 import re

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop

[gem5-dev] Change in gem5/gem5[develop]: tests: Remove Python 2.7 glue code from testlib

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39759 )


Change subject: tests: Remove Python 2.7 glue code from testlib
..

tests: Remove Python 2.7 glue code from testlib

Remove the dependency on six in testlib.

Change-Id: I247088d119cf8f9d815632eae16a1cbf87930516
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39759
Reviewed-by: Bobby R. Bruce 
Tested-by: kokoro 
---
M ext/testlib/configuration.py
M ext/testlib/handlers.py
M ext/testlib/loader.py
M ext/testlib/log.py
M ext/testlib/terminal.py
5 files changed, 4 insertions(+), 13 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/ext/testlib/configuration.py b/ext/testlib/configuration.py
index e5b7598..f2d93d6 100644
--- a/ext/testlib/configuration.py
+++ b/ext/testlib/configuration.py
@@ -83,7 +83,6 @@
 import os
 import re

-from six import add_metaclass
 from pickle import HIGHEST_PROTOCOL as highest_pickle_protocol

 from testlib.helper import absdirpath, AttrDict, FrozenAttrDict
@@ -602,8 +601,7 @@
 # one in the list will be saved.
 common_args = AttrDict({arg.name:arg for arg in common_args})

-@add_metaclass(abc.ABCMeta)
-class ArgParser(object):
+class ArgParser(object, metaclass=abc.ABCMeta):
 class ExtendAction(argparse.Action):
 def __call__(self, parser, namespace, values, option_string=None):
 items = getattr(namespace, self.dest, [])
diff --git a/ext/testlib/handlers.py b/ext/testlib/handlers.py
index 723a855..b62322f 100644
--- a/ext/testlib/handlers.py
+++ b/ext/testlib/handlers.py
@@ -31,8 +31,6 @@


 '''
-from __future__ import print_function
-
 import multiprocessing
 import os
 import sys
@@ -46,7 +44,7 @@
 import testlib.state as state
 import testlib.terminal as terminal

-from six.moves import queue as Queue
+from queue import Queue
 from testlib.configuration import constants


diff --git a/ext/testlib/loader.py b/ext/testlib/loader.py
index 2d76996..58b1b2e 100644
--- a/ext/testlib/loader.py
+++ b/ext/testlib/loader.py
@@ -67,7 +67,6 @@

 import os
 import re
-import six
 import sys
 import traceback

diff --git a/ext/testlib/log.py b/ext/testlib/log.py
index 1bdb373..fb5907c 100644
--- a/ext/testlib/log.py
+++ b/ext/testlib/log.py
@@ -32,8 +32,6 @@
 '''
 import testlib.wrappers as wrappers

-from six import add_metaclass
-
 class LogLevel():
 Fatal = 0
 Error = 1
@@ -56,8 +54,7 @@
 RecordTypeCounterMetaclass.counter += 1


-@add_metaclass(RecordTypeCounterMetaclass)
-class Record(object):
+class Record(object, metaclass=RecordTypeCounterMetaclass):
 '''
 A generic object that is passed to the :class:`Log` and its handlers.

diff --git a/ext/testlib/terminal.py b/ext/testlib/terminal.py
index bc4c855..be489f5 100644
--- a/ext/testlib/terminal.py
+++ b/ext/testlib/terminal.py
@@ -28,7 +28,6 @@
 import fcntl
 import termios
 import struct
-import six

 # Intended usage example:
 #
@@ -85,7 +84,7 @@
 def __init__(self, cap_string):
 for i, c in enumerate(color_names):
 setattr(self, c, cap_string('setaf', i))
-for name, cap in six.iteritems(capability_map):
+for name, cap in capability_map.items():
 setattr(self, name, cap_string(cap))

 termcap = ColorStrings(cap_string)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I247088d119cf8f9d815632eae16a1cbf87930516
Gerrit-Change-Number: 39759
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Fix compilation error for debug builds.

[Richard Cooper (Gerrit) via gem5-dev]

Richard Cooper has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39760 )


Change subject: sim: Fix compilation error for debug builds.
..

sim: Fix compilation error for debug builds.

https://gem5-review.googlesource.com/c/public/gem5/+/39537 removed the
implicit use of the std:: namespace. This change adds a missing
namespace specifier for debug builds.

Change-Id: I1d70602a870a25f68d7fec4b4931ba7cbbb4f4ca
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39760
Reviewed-by: Daniel Carvalho 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/sim/sim_object.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/sim_object.cc b/src/sim/sim_object.cc
index 17dbd1d..28a0863 100644
--- a/src/sim/sim_object.cc
+++ b/src/sim/sim_object.cc
@@ -160,7 +160,7 @@
 void
 debugObjectBreak(const char *objs)
 {
-SimObject::debugObjectBreak(string(objs));
+SimObject::debugObjectBreak(std::string(objs));
 }
 #endif


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1d70602a870a25f68d7fec4b4931ba7cbbb4f4ca
Gerrit-Change-Number: 39760
Gerrit-PatchSet: 2
Gerrit-Owner: Richard Cooper 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu,mem,sim: Use ADD_STAT macro where possible

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38916 )


Change subject: cpu,mem,sim: Use ADD_STAT macro where possible
..

cpu,mem,sim: Use ADD_STAT macro where possible

Change-Id: I3cf0a2a321742445cf7100115eacbc411c70f4fb
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38916
Reviewed-by: Daniel Carvalho 
Reviewed-by: Andreas Sandberg 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/base.cc
M src/mem/abstract_mem.cc
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/compressors/base.cc
M src/mem/cache/compressors/base_dictionary_compressor.cc
M src/mem/cache/compressors/multi.cc
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/sector_tags.cc
M src/mem/coherent_xbar.cc
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/slicc/symbols/StateMachine.py
M src/mem/xbar.cc
M src/sim/root.cc
M src/sim/workload.hh
16 files changed, 148 insertions(+), 189 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index af928f1..793fc64 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -732,12 +732,10 @@

 BaseCPU::GlobalStats::GlobalStats(::Stats::Group *parent)
 : ::Stats::Group(parent),
-simInsts(this, "sim_insts", "Number of instructions simulated"),
-simOps(this, "sim_ops", "Number of ops (including micro ops)  
simulated"),

-hostInstRate(this, "host_inst_rate",
- "Simulator instruction rate (inst/s)"),
-hostOpRate(this, "host_op_rate",
-   "Simulator op (including micro ops) rate (op/s)")
+ADD_STAT(simInsts, "Number of instructions simulated"),
+ADD_STAT(simOps, "Number of ops (including micro ops) simulated"),
+ADD_STAT(hostInstRate, "Simulator instruction rate (inst/s)"),
+ADD_STAT(hostOpRate, "Simulator op (including micro ops) rate (op/s)")
 {
 simInsts
 .functor(BaseCPU::numSimulatedInsts)
diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index c8853d1..e7c460c 100644
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -111,26 +111,19 @@

 AbstractMemory::MemStats::MemStats(AbstractMemory &_mem)
 : Stats::Group(&_mem), mem(_mem),
-bytesRead(this, "bytes_read",
-  "Number of bytes read from this memory"),
-bytesInstRead(this, "bytes_inst_read",
-  "Number of instructions bytes read from this memory"),
-bytesWritten(this, "bytes_written",
- "Number of bytes written to this memory"),
-numReads(this, "num_reads",
- "Number of read requests responded to by this memory"),
-numWrites(this, "num_writes",
-  "Number of write requests responded to by this memory"),
-numOther(this, "num_other",
- "Number of other requests responded to by this memory"),
-bwRead(this, "bw_read",
-   "Total read bandwidth from this memory (bytes/s)"),
-bwInstRead(this, "bw_inst_read",
-   "Instruction read bandwidth from this memory (bytes/s)"),
-bwWrite(this, "bw_write",
-"Write bandwidth from this memory (bytes/s)"),
-bwTotal(this, "bw_total",
-"Total bandwidth to/from this memory (bytes/s)")
+ADD_STAT(bytesRead, "Number of bytes read from this memory"),
+ADD_STAT(bytesInstRead,
+ "Number of instructions bytes read from this memory"),
+ADD_STAT(bytesWritten, "Number of bytes written to this memory"),
+ADD_STAT(numReads, "Number of read requests responded to by this  
memory"),

+ADD_STAT(numWrites,
+ "Number of write requests responded to by this memory"),
+ADD_STAT(numOther, "Number of other requests responded to by this  
memory"),

+ADD_STAT(bwRead, "Total read bandwidth from this memory (bytes/s)"),
+ADD_STAT(bwInstRead,
+ "Instruction read bandwidth from this memory (bytes/s)"),
+ADD_STAT(bwWrite, "Write bandwidth from this memory (bytes/s)"),
+ADD_STAT(bwTotal, "Total bandwidth to/from this memory (bytes/s)")
 {
 }

diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index d28a34e..023d0a9 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -2104,67 +2104,44 @@
 BaseCache::CacheStats::CacheStats(BaseCache )
 : Stats::Group(), cache(c),

-demandHits(this, "demand_hits", "number of demand (read+write) hits"),
-
-overallHits(this, "overall_hits", "number of overall hits"),
-demandMisses(this, "demand_misses",
- "number of demand (read+write) misses"),
-overallMisses(this, "overall_misses", "number of overall misses"),
-demandMissLatency(this, "demand_miss_latency",
-  "number of 

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fixing RISC-V remote GDB MIP and MIE accesses.

[Peter Yuen (Gerrit) via gem5-dev]

Peter Yuen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39816 )



Change subject: arch-riscv: Fixing RISC-V remote GDB MIP and MIE accesses.
..

arch-riscv: Fixing RISC-V remote GDB MIP and MIE accesses.

Change-Id: I6bd71da5c83e12c06043889bdbef7e4c0cf78190
---
M src/arch/riscv/remote_gdb.cc
1 file changed, 18 insertions(+), 18 deletions(-)



diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index 021b388..da78957 100644
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -211,7 +211,7 @@
 // U mode CSR
 r.ustatus = context->readMiscRegNoEffect(
 CSRData.at(CSR_USTATUS).physIndex) & CSRMasks.at(CSR_USTATUS);
-r.uie = context->readMiscRegNoEffect(
+r.uie = context->readMiscReg(
 CSRData.at(CSR_UIE).physIndex) & CSRMasks.at(CSR_UIE);
 r.utvec = context->readMiscRegNoEffect(
 CSRData.at(CSR_UTVEC).physIndex);
@@ -223,7 +223,7 @@
 CSRData.at(CSR_UCAUSE).physIndex);
 r.utval = context->readMiscRegNoEffect(
 CSRData.at(CSR_UTVAL).physIndex);
-r.uip = context->readMiscRegNoEffect(
+r.uip = context->readMiscReg(
 CSRData.at(CSR_UIP).physIndex) & CSRMasks.at(CSR_UIP);

 // S mode CSR
@@ -233,7 +233,7 @@
 CSRData.at(CSR_SEDELEG).physIndex);
 r.sideleg = context->readMiscRegNoEffect(
 CSRData.at(CSR_SIDELEG).physIndex);
-r.sie = context->readMiscRegNoEffect(
+r.sie = context->readMiscReg(
 CSRData.at(CSR_SIE).physIndex) & CSRMasks.at(CSR_SIE);
 r.stvec = context->readMiscRegNoEffect(
 CSRData.at(CSR_STVEC).physIndex);
@@ -247,7 +247,7 @@
 CSRData.at(CSR_SCAUSE).physIndex);
 r.stval = context->readMiscRegNoEffect(
 CSRData.at(CSR_STVAL).physIndex);
-r.sip = context->readMiscRegNoEffect(
+r.sip = context->readMiscReg(
 CSRData.at(CSR_SIP).physIndex) & CSRMasks.at(CSR_SIP);
 r.satp = context->readMiscRegNoEffect(
 CSRData.at(CSR_SATP).physIndex);
@@ -269,7 +269,7 @@
 CSRData.at(CSR_MEDELEG).physIndex);
 r.mideleg = context->readMiscRegNoEffect(
 CSRData.at(CSR_MIDELEG).physIndex);
-r.mie = context->readMiscRegNoEffect(
+r.mie = context->readMiscReg(
 CSRData.at(CSR_MIE).physIndex) & CSRMasks.at(CSR_MIE);
 r.mtvec = context->readMiscRegNoEffect(
 CSRData.at(CSR_MTVEC).physIndex);
@@ -283,7 +283,7 @@
 CSRData.at(CSR_MCAUSE).physIndex);
 r.mtval = context->readMiscRegNoEffect(
 CSRData.at(CSR_MTVAL).physIndex);
-r.mip = context->readMiscRegNoEffect(
+r.mip = context->readMiscReg(
 CSRData.at(CSR_MIP).physIndex) & CSRMasks.at(CSR_MIP);

 // H mode CSR (to be implemented)
@@ -340,11 +340,11 @@
 newVal = (oldVal & ~mask) | (r.ustatus & mask);
 context->setMiscRegNoEffect(
 CSRData.at(CSR_USTATUS).physIndex, newVal);
-oldVal = context->readMiscRegNoEffect(
+oldVal = context->readMiscReg(
 CSRData.at(CSR_UIE).physIndex);
 mask = CSRMasks.at(CSR_UIE);
 newVal = (oldVal & ~mask) | (r.uie & mask);
-context->setMiscRegNoEffect(
+context->setMiscReg(
 CSRData.at(CSR_UIE).physIndex, newVal);
 context->setMiscRegNoEffect(
 CSRData.at(CSR_UTVEC).physIndex, r.utvec);
@@ -356,11 +356,11 @@
 CSRData.at(CSR_UCAUSE).physIndex, r.ucause);
 context->setMiscRegNoEffect(
 CSRData.at(CSR_UTVAL).physIndex, r.utval);
-oldVal = context->readMiscRegNoEffect(
+oldVal = context->readMiscReg(
 CSRData.at(CSR_UIP).physIndex);
 mask = CSRMasks.at(CSR_UIP);
 newVal = (oldVal & ~mask) | (r.uip & mask);
-context->setMiscRegNoEffect(
+context->setMiscReg(
 CSRData.at(CSR_UIP).physIndex, newVal);

 // S mode CSR
@@ -374,11 +374,11 @@
 CSRData.at(CSR_SEDELEG).physIndex, r.sedeleg);
 context->setMiscRegNoEffect(
 CSRData.at(CSR_SIDELEG).physIndex, r.sideleg);
-oldVal = context->readMiscRegNoEffect(
+oldVal = context->readMiscReg(
 CSRData.at(CSR_SIE).physIndex);
 mask = CSRMasks.at(CSR_SIE);
 newVal = (oldVal & ~mask) | (r.sie & mask);
-context->setMiscRegNoEffect(
+context->setMiscReg(
 CSRData.at(CSR_SIE).physIndex, newVal);
 context->setMiscRegNoEffect(
 CSRData.at(CSR_STVEC).physIndex, r.stvec);
@@ -392,11 +392,11 @@
 CSRData.at(CSR_SCAUSE).physIndex, r.scause);
 context->setMiscRegNoEffect(
 CSRData.at(CSR_STVAL).physIndex, r.stval);
-oldVal = context->readMiscRegNoEffect(
+oldVal = context->readMiscReg(
 CSRData.at(CSR_SIP).physIndex);
 mask = CSRMasks.at(CSR_SIP);
 newVal = (oldVal & ~mask) | (r.sip & mask);
-context->setMiscRegNoEffect(
+context->setMiscReg(
 CSRData.at(CSR_SIP).physIndex, newVal);
 context->setMiscRegNoEffect(
 

[gem5-dev] Change in gem5/gem5[develop]: dev: Fix reset of virtio devices

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39701 )


Change subject: dev: Fix reset of virtio devices
..

dev: Fix reset of virtio devices

The VirtualQueue reset was just resetting the queue address but
it was not touching other cached state and its associated
ring buffers (used and avail)

Change-Id: I55cc767d791825899d62c4cd88b84809527f3f22
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39701
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/virtio/base.cc
M src/dev/virtio/base.hh
2 files changed, 29 insertions(+), 3 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/virtio/base.cc b/src/dev/virtio/base.cc
index 0624c7e..c19cf92 100644
--- a/src/dev/virtio/base.cc
+++ b/src/dev/virtio/base.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, 2016 ARM Limited
+ * Copyright (c) 2014, 2016, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -256,6 +256,16 @@
 }

 void
+VirtQueue::reset()
+{
+_address = 0;
+_last_avail = 0;
+
+avail.reset();
+used.reset();
+}
+
+void
 VirtQueue::setAddress(Addr address)
 {
 const Addr addr_avail(address + _size * sizeof(struct vring_desc));
@@ -366,7 +376,7 @@
 _deviceStatus = 0;

 for (QueueID i = 0; i < _queues.size(); ++i)
-_queues[i]->setAddress(0);
+_queues[i]->reset();
 }

 void
diff --git a/src/dev/virtio/base.hh b/src/dev/virtio/base.hh
index d9ade7f..72ad02e 100644
--- a/src/dev/virtio/base.hh
+++ b/src/dev/virtio/base.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, 2016-2017 ARM Limited
+ * Copyright (c) 2014, 2016-2017, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -305,6 +305,14 @@
 /** @{
  * @name Low-level Device Interface
  */
+
+/**
+ * Reset cached state in this queue and in the associated
+ * ring buffers. A client of this method should be the
+ * VirtIODeviceBase::reset.
+ */
+void reset();
+
 /**
  * Set the base address of this queue.
  *
@@ -464,6 +472,14 @@
 header{0, 0}, ring(size), _proxy(proxy), _base(0),  
byteOrder(bo)

 {}

+/** Reset any state in the ring buffer. */
+void
+reset()
+{
+header = {0, 0};
+_base = 0;
+};
+
 /**
  * Set the base address of the VirtIO ring buffer.
  *

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I55cc767d791825899d62c4cd88b84809527f3f22
Gerrit-Change-Number: 39701
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: RFC: mem: Add a mechanism to push physical addresses in memory requests.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39875 )



Change subject: RFC: mem: Add a mechanism to push physical addresses in  
memory requests.

..

RFC: mem: Add a mechanism to push physical addresses in memory requests.

When a request needs to be translated after its enter the physical
memory domain, the only way to do that currently is to create a whole
new request with the new physical address and to send that onwards.

This change makes it possible to push new physical addresses which will
replace the existing one, with the old addresses accumulating in a stack
so they can be restored as the request returns towards the sender.

This mechanism could hypothetically be extended in the future to cover
even normal translation at the ISA level MMU, and make it easier to add
additional levels of translation for, for instance, virtualization.

It might even make sense to break the MMU out of the CPU itself and
simply put it in line on the way to memory, although that may not be
practical given the high level of bidirectional interaction between the
MMU and the CPU.

Change-Id: I839f6ecd2332432dad7c0e1537c03d0787dba61b
---
M src/mem/request.hh
1 file changed, 19 insertions(+), 0 deletions(-)



diff --git a/src/mem/request.hh b/src/mem/request.hh
index 38b64fd..305606e 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -54,6 +54,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 

 #include "base/amo.hh"
@@ -344,6 +345,8 @@
  */
 Addr _paddr = 0;

+std::stack _paddrs;
+
 /**
  * The size of the request. This field must be set when vaddr or
  * paddr is written via setVirt() or a phys basec constructor, so it is
@@ -536,6 +539,22 @@
 privateFlags.set(VALID_PADDR);
 }

+void
+pushPaddr(Addr paddr)
+{
+assert(hasPaddr());
+_paddrs.emplace(_paddr);
+_paddr = paddr;
+}
+
+void
+popPaddr()
+{
+assert(!_paddrs.empty());
+_paddr = _paddrs.top();
+_paddrs.pop();
+}
+
 /**
  * Generate two requests as if this request had been split into two
  * pieces. The original request can't have been translated already.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I839f6ecd2332432dad7c0e1537c03d0787dba61b
Gerrit-Change-Number: 39875
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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