[gem5-dev] Change in gem5/gem5[develop]: base: Improved less-than operator for AddrRange
Carlos Falquez has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/47279 )
Change subject: base: Improved less-than operator for AddrRange
..
base: Improved less-than operator for AddrRange
The current implementation of the less-than operator
for AddrRange compares intlvMatch values without first
checking that both ranges are interleaved.
This commit modifies the less-than operator to compare
intlvMatch values only if both regions are interleaved.
Otherwise, the operator returns whether the left
address range is interleaved.
This commit also adds AddrRangeMap unit tests
for interleaved address ranges.
JIRA: https://gem5.atlassian.net/browse/GEM5-1010
Change-Id: Id9f14d75d465d472c046995754bdccd441b9470c
Signed-off-by: Carlos Falquez
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47279
Reviewed-by: Daniel Carvalho
Maintainer: Daniel Carvalho
Tested-by: kokoro
---
M src/base/addr_range.hh
M src/base/addr_range_map.test.cc
2 files changed, 100 insertions(+), 5 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/addr_range.hh b/src/base/addr_range.hh
index 12186fa..405d8ba 100644
--- a/src/base/addr_range.hh
+++ b/src/base/addr_range.hh
@@ -593,12 +593,19 @@
*/
bool operator<(const AddrRange& r) const
{
-if (_start != r._start)
+if (_start != r._start) {
return _start < r._start;
-else
-// for now assume that the end is also the same, and that
-// we are looking at the same interleaving bits
-return intlvMatch < r.intlvMatch;
+} else {
+// For now assume that the end is also the same.
+// If both regions are interleaved, assume same interleaving,
+// and compare intlvMatch values.
+// Otherwise, return true if this address range is interleaved.
+if (interleaved() && r.interleaved()) {
+return intlvMatch < r.intlvMatch;
+} else {
+return interleaved();
+}
+}
}
/**
diff --git a/src/base/addr_range_map.test.cc
b/src/base/addr_range_map.test.cc
index fef3a89..74f6bff 100644
--- a/src/base/addr_range_map.test.cc
+++ b/src/base/addr_range_map.test.cc
@@ -40,6 +40,8 @@
#include
+#include
+
#include "base/addr_range_map.hh"
// Converted from legacy unit test framework
@@ -66,3 +68,89 @@
EXPECT_NE(r.contains(RangeIn(20, 30)), r.end());
}
+
+/**
+ * Test AddrRangeMap with interleaved address ranges defined by bitmasks.
+ * An AddrRangeMap containing a set of N interleaved address ranges,
+ * defined with the same start and end address, and including all possible
+ * intlvMatch values 0..N-1, must contain the start address.
+ * For N-way interleaving, log2(N) selection masks are needed.
+ * For N = 16, define the masks as follows,
+ *
+ * masks[0] = 1 << 6
+ * masks[1] = 1 << 7
+ * masks[2] = 1 << 8
+ * masks[3] = 1 << 9
+ *
+ */
+TEST(AddrRangeMapTest, InterleavedTest1)
+{
+const auto N = 16;
+const auto masks = std::vector{
+0x40,
+0x80,
+0x100,
+0x200
+};
+const Addr start = 0x8000;
+const Addr end = 0xc000;
+
+AddrRangeMap r;
+AddrRangeMap::const_iterator i;
+
+// populate AddrRangeMap with N-way interleaved address ranges
+// for all intlvMatch values 0..N-1
+for (int k=0; k < N; k++) {
+r.insert(AddrRange(start, end, masks, k), k);
+}
+// find AddrRange element containing start address
+i = r.contains(start);
+// i must not be the past-the-end iterator
+ASSERT_NE(i, r.end()) << "start address not found in AddrRangeMap";
+// intlvMatch = 0 for start = 0x8000
+EXPECT_EQ(i->second, 0);
+}
+
+/**
+ * Test AddrRangeMap with interleaved address ranges defined by bitmasks.
+ * An AddrRangeMap containing a set of N interleaved address ranges,
+ * defined with the same start and end address, and including all possible
+ * intlvMatch values 0..N-1, must contain the start address.
+ * For N-way interleaving, log2(N) selection masks are needed.
+ * For N = 16, define the masks as described in the
+ * CMN-600 Technical Reference Manual [1], section 2.17.3
+ *
+ * masks[0] = 1 << 6 | 1 << 10 | 1 << 14 | .. | 1 << 50
+ * masks[1] = 1 << 7 | 1 << 11 | 1 << 15 | .. | 1 << 51
+ * masks[2] = 1 << 8 | 1 << 12 | 1 << 16 | .. | 1 << 48
+ * masks[3] = 1 << 9 | 1 << 13 | 1 << 17 | .. | 1 << 49
+ *
+ * [1] https://developer.arm.com/documentation/100180/0302
+ */
+TEST(AddrRangeMapTest, InterleavedTest2)
+{
+const auto N = 16;
+const auto masks = std::vector{
+0x0,
+0x0,
+0x11100,
+0x22200
+};
+const Addr start = 0x8000;
+const Addr end = 0xc000;
+
+
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add doubleword multiply-add instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40905 )
Change subject: arch-power: Add doubleword multiply-add instructions
..
arch-power: Add doubleword multiply-add instructions
This introduces 128-bit addition helpers and adds the
following instructions.
* Multiply-Add Low Doubleword (maddld)
* Multiply-Add High Doubleword (maddhd)
* Multiply-Add High Doubleword Unsigned (maddhdu)
Change-Id: I04e6ea5fb4978b341a6e648424de2930ad41f449
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40905
Reviewed-by: Boris Shingarov
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/insts/integer.cc
M src/arch/power/insts/integer.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/integer.isa
4 files changed, 134 insertions(+), 0 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/integer.cc
b/src/arch/power/insts/integer.cc
index 25c8691..61b7f08 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -117,6 +117,7 @@
{
std::stringstream ss;
bool printSecondSrc = true;
+bool printThirdSrc = false;
// Generate the correct mnemonic
std::string myMnemonic(mnemonic);
@@ -128,6 +129,10 @@
myMnemonic == "subfze" ||
myMnemonic == "neg") {
printSecondSrc = false;
+} else if (myMnemonic == "maddhd" ||
+ myMnemonic == "maddhdu" ||
+ myMnemonic == "maddld") {
+printThirdSrc = true;
}
// Additional characters depending on isa bits being set
@@ -151,6 +156,12 @@
if (_numSrcRegs > 1 && printSecondSrc) {
ss << ", ";
printReg(ss, srcRegIdx(1));
+
+// Print the third source register
+if (_numSrcRegs > 2 && printThirdSrc) {
+ss << ", ";
+printReg(ss, srcRegIdx(2));
+}
}
}
diff --git a/src/arch/power/insts/integer.hh
b/src/arch/power/insts/integer.hh
index 95f1598..fccb7cf 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -134,6 +134,52 @@
{
}
+/* Compute 128-bit sum of 128-bit to 64-bit unsigned integer addition
*/
+inline std::tuple
+add(uint64_t ralo, uint64_t rahi, uint64_t rb) const
+{
+uint64_t slo, shi;
+#if defined(__SIZEOF_INT128__)
+__uint128_t ra = ((__uint128_t)rahi << 64) | ralo;
+__uint128_t sum = ra + rb;
+slo = sum;
+shi = sum >> 64;
+#else
+shi = rahi + ((ralo + rb) < ralo);
+slo = ralo + rb;
+#endif
+return std::make_tuple(slo, shi);
+}
+
+/* Compute 128-bit sum of 128-bit to 64-bit signed integer addition */
+inline std::tuple
+add(uint64_t ralo, int64_t rahi, int64_t rb) const
+{
+uint64_t slo;
+int64_t shi;
+#if defined(__SIZEOF_INT128__)
+__int128_t ra = ((__int128_t)rahi << 64) | ralo;
+__int128_t sum = (__int128_t)ra + rb;
+slo = sum;
+shi = sum >> 64;
+#else
+if (rb < 0) {
+shi = rahi - 1;
+slo = ralo + rb;
+if (slo < rb) {
+shi++;
+}
+} else {
+shi = rahi;
+slo = ralo + rb;
+if (slo < rb) {
+shi++;
+}
+}
+#endif
+return std::make_tuple(slo, shi);
+}
+
/**
* Compute 128-bit product of 64-bit unsigned integer multiplication
* based on https://stackoverflow.com/a/28904636
@@ -177,6 +223,48 @@
return std::make_tuple(plo, (int64_t)phi);
}
+/**
+ * Compute 128-bit result of 64-bit unsigned integer multiplication
+ * followed by addition
+ */
+inline std::tuple
+multiplyAdd(uint64_t ra, uint64_t rb, uint64_t rc) const
+{
+uint64_t rlo, rhi;
+#if defined(__SIZEOF_INT128__)
+__uint128_t res = ((__uint128_t)ra * rb) + rc;
+rlo = res;
+rhi = res >> 64;
+#else
+uint64_t plo, phi;
+std::tie(plo, phi) = multiply(ra, rb);
+std::tie(rlo, rhi) = add(plo, phi, rc);
+#endif
+return std::make_tuple(rlo, rhi);
+}
+
+/**
+ * Compute 128-bit result of 64-bit signed integer multiplication
+ * followed by addition
+ */
+inline std::tuple
+multiplyAdd(int64_t ra, int64_t rb, int64_t rc) const
+{
+uint64_t rlo;
+int64_t rhi;
+#if defined(__SIZEOF_INT128__)
+__int128_t res = (__int128_t)ra * rb + rc;
+rlo = res;
+rhi = res >> 64;
+#else
+uint64_t plo;
+int64_t phi;
+std::tie(plo, phi) = multiply(ra, rb);
+std::tie(rlo, rhi) =
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add fields for VA form instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40904 )
Change subject: arch-power: Add fields for VA form instructions
..
arch-power: Add fields for VA form instructions
This introduces the extended opcode field for VA form
instructions and the RC field that specifes a GPR to
be used as a register operand.
Change-Id: Ibc63b7392cb552613c755463fb34f2ee2362b2b6
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40904
Reviewed-by: Boris Shingarov
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/isa/bitfields.isa
M src/arch/power/isa/operands.isa
2 files changed, 4 insertions(+), 1 deletion(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/bitfields.isa
b/src/arch/power/isa/bitfields.isa
index 84a3a2c..8783081 100644
--- a/src/arch/power/isa/bitfields.isa
+++ b/src/arch/power/isa/bitfields.isa
@@ -38,6 +38,7 @@
def bitfield A_XO <5:1>;
def bitfield DS_XO <1:0>;
def bitfield DX_XO <5:1>;
+def bitfield VA_XO <5:0>;
def bitfield X_XO <10:1>;
def bitfield XFL_XO<10:1>;
def bitfield XFX_XO<10:1>;
@@ -47,6 +48,7 @@
// Register fields
def bitfield RA<20:16>;
def bitfield RB<15:11>;
+def bitfield RC<10:6>;
def bitfield RS<25:21>;
def bitfield RT<25:21>;
def bitfield FRA <20:16>;
diff --git a/src/arch/power/isa/operands.isa
b/src/arch/power/isa/operands.isa
index 8cb39eb..7d85749 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -44,7 +44,8 @@
'Rs': ('IntReg', 'ud', 'RS', 'IsInteger', 1),
'Ra': ('IntReg', 'ud', 'RA', 'IsInteger', 2),
'Rb': ('IntReg', 'ud', 'RB', 'IsInteger', 3),
-'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 4),
+'Rc': ('IntReg', 'ud', 'RC', 'IsInteger', 4),
+'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 5),
# General Purpose Floating Point Reg Operands
'Fa': ('FloatReg', 'df', 'FRA', 'IsFloating', 1),
6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40904
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibc63b7392cb552613c755463fb34f2ee2362b2b6
Gerrit-Change-Number: 40904
Gerrit-PatchSet: 8
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add doubleword multiply instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40903 )
Change subject: arch-power: Add doubleword multiply instructions
..
arch-power: Add doubleword multiply instructions
This introduces 128-bit multiplication helpers and adds
the following instructions.
* Multiply Low Doubleword (mulld[o][.])
* Multiply High Doubleword (mulhd[.])
* Multiply High Doubleword Unsigned (mulhdu[.])
Change-Id: Id579c95468ffe5fe7b5164579ec1dfb18f0b3ab3
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40903
Reviewed-by: Boris Shingarov
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/insts/integer.hh
M src/arch/power/isa/decoder.isa
2 files changed, 85 insertions(+), 16 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/integer.hh
b/src/arch/power/insts/integer.hh
index aafbbec..95f1598 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -134,6 +134,49 @@
{
}
+/**
+ * Compute 128-bit product of 64-bit unsigned integer multiplication
+ * based on https://stackoverflow.com/a/28904636
+ */
+inline std::tuple
+multiply(uint64_t ra, uint64_t rb) const
+{
+uint64_t plo, phi;
+#if defined(__SIZEOF_INT128__)
+__uint128_t prod = (__uint128_t)ra * rb;
+plo = prod;
+phi = prod >> 64;
+#else
+uint64_t ralo = (uint32_t)ra, rahi = ra >> 32;
+uint64_t rblo = (uint32_t)rb, rbhi = rb >> 32;
+uint64_t pp0 = ralo * rblo;
+uint64_t pp1 = rahi * rblo;
+uint64_t pp2 = ralo * rbhi;
+uint64_t pp3 = rahi * rbhi;
+uint64_t c = ((uint32_t)pp1) + ((uint32_t)pp2) + (pp0 >> 32);
+phi = pp3 + (pp2 >> 32) + (pp1 >> 32) + (c >> 32);
+plo = (c << 32) | ((uint32_t)pp0);
+#endif
+return std::make_tuple(plo, phi);
+}
+
+/* Compute 128-bit product of 64-bit signed integer multiplication */
+inline std::tuple
+multiply(int64_t ra, int64_t rb) const
+{
+uint64_t plo, phi;
+#if defined(__SIZEOF_INT128__)
+__int128_t prod = (__int128_t)ra * rb;
+plo = prod;
+phi = prod >> 64;
+#else
+std::tie(plo, phi) = multiply((uint64_t)ra, (uint64_t)rb);
+if (rb < 0) phi -= (uint64_t)ra;
+if (ra < 0) phi -= (uint64_t)rb;
+#endif
+return std::make_tuple(plo, (int64_t)phi);
+}
+
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
};
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index beacd6f..b4c90fc 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -483,10 +483,15 @@
// These instructions are of XO form with bit 21 as the OE bit.
default: decode XO_XO {
-format IntSumOp {
-8: subfc({{ ~Ra }}, {{ Rb }}, {{ 1 }}, true);
-10: addc({{ Ra }}, {{ Rb }}, computeCA = true);
-}
+8: IntSumOp::subfc({{ ~Ra }}, {{ Rb }}, {{ 1 }}, true);
+
+9: IntArithCheckRcOp::mulhdu({{
+uint64_t res;
+std::tie(std::ignore, res) = multiply(Ra, Rb);
+Rt = res;
+}});
+
+10: IntSumOp::addc({{ Ra }}, {{ Rb }}, computeCA = true);
11: IntArithCheckRcOp::mulhwu({{
uint64_t res = (uint64_t)Ra_uw * Rb_uw;
@@ -496,11 +501,19 @@
40: IntSumOp::subf({{ ~Ra }}, {{ Rb }}, {{ 1 }});
-75: IntArithCheckRcOp::mulhw({{
-uint64_t res = (int64_t)Ra_sw * Rb_sw;
-res = res >> 32;
-Rt = res;
-}});
+format IntArithCheckRcOp {
+73: mulhd({{
+int64_t res;
+std::tie(std::ignore, res) = multiply(Ra_sd, Rb_sd);
+Rt = res;
+}});
+
+75: mulhw({{
+uint64_t res = (int64_t)Ra_sw * Rb_sw;
+res = res >> 32;
+Rt = res;
+}});
+}
format IntSumOp {
104: neg({{ ~Ra }}, {{ 1 }});
@@ -512,13 +525,26 @@
234: addme({{ Ra }}, {{ -1ULL }}, {{ xer.ca }}, true);
}
-235: IntArithCheckRcOp::mullw({{
-int64_t res = (int64_t)Ra_sw * Rb_sw;
-if (res != (int32_t)res) {
-setOV = true;
-}
-Rt = res;
-}}, true);
+format IntArithCheckRcOp {
+233: mulld({{
+int64_t src1 = Ra_sd;
+int64_t src2 = Rb_sd;
+
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add PC-relative arithmetic instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40902 )
Change subject: arch-power: Add PC-relative arithmetic instructions
..
arch-power: Add PC-relative arithmetic instructions
This adds the following instructions.
* Add PC Immediate Shifted (addpcis)
Change-Id: Ib88b8e123ffb328e6f692e0fddb237e420ce38a7
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40902
Reviewed-by: Boris Shingarov
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/insts/integer.cc
M src/arch/power/insts/integer.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/integer.isa
4 files changed, 81 insertions(+), 0 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/integer.cc
b/src/arch/power/insts/integer.cc
index 2035b5c..25c8691 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -219,6 +219,51 @@
std::string
+IntDispArithOp::generateDisassembly(
+Addr pc, const Loader::SymbolTable *symtab) const
+{
+std::stringstream ss;
+bool printSrcs = true;
+bool printDisp = true;
+bool negateDisp = false;
+
+// Generate the correct mnemonic
+std::string myMnemonic(mnemonic);
+
+// Special cases
+if (myMnemonic == "addpcis") {
+printSrcs = false;
+if (d == 0) {
+myMnemonic = "lnia";
+printDisp = false;
+} else if (d < 0) {
+myMnemonic = "subpcis";
+negateDisp = true;
+}
+}
+
+ccprintf(ss, "%-10s ", myMnemonic);
+
+// Print the first destination only
+if (_numDestRegs > 0)
+printReg(ss, destRegIdx(0));
+
+// Print the source register
+if (_numSrcRegs > 0 && printSrcs) {
+if (_numDestRegs > 0)
+ss << ", ";
+printReg(ss, srcRegIdx(0));
+}
+
+// Print the displacement
+if (printDisp)
+ss << ", " << (negateDisp ? -d : d);
+
+return ss.str();
+}
+
+
+std::string
IntShiftOp::generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const
{
diff --git a/src/arch/power/insts/integer.hh
b/src/arch/power/insts/integer.hh
index daef626..aafbbec 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -161,6 +161,27 @@
/**
+ * Class for integer arithmetic operations with displacement.
+ */
+class IntDispArithOp : public IntArithOp
+{
+ protected:
+
+int64_t d;
+
+/// Constructor
+IntDispArithOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : IntArithOp(mnem, _machInst, __opClass),
+d(sext<16>((machInst.d0 << 6) | (machInst.d1 << 1) | machInst.d2))
+{
+}
+
+std::string generateDisassembly(
+Addr pc, const Loader::SymbolTable *symtab) const override;
+};
+
+
+/**
* Class for integer operations with a shift.
*/
class IntShiftOp : public IntOp
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index cc3b9f4..beacd6f 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -163,6 +163,10 @@
528: bcctr({{ NIA = CTR & -4ULL; }});
560: bctar({{ NIA = TAR & -4ULL; }}, true);
}
+
+default: decode DX_XO {
+2: IntDispArithOp::addpcis({{ Rt = NIA + (d << 16); }});
+}
}
format IntRotateOp {
diff --git a/src/arch/power/isa/formats/integer.isa
b/src/arch/power/isa/formats/integer.isa
index 8583ba0..183c08b 100644
--- a/src/arch/power/isa/formats/integer.isa
+++ b/src/arch/power/isa/formats/integer.isa
@@ -168,6 +168,17 @@
}};
+// Integer instructions with displacement that perform arithmetic.
+// There are no control flags to set.
+def format IntDispArithOp(code, inst_flags = []) {{
+
+# Generate the class
+(header_output, decoder_output, decode_block, exec_output) = \
+GenAluOp(name, Name, 'IntDispArithOp', code, inst_flags,
BasicDecode,
+ BasicConstructor)
+}};
+
+
// Integer instructions that perform logic operations. The result is
// always written into Ra. All instructions have 2 versions depending on
// whether the Rc bit is set to compute the CR0 code. This is determined
6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40902
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib88b8e123ffb328e6f692e0fddb237e420ce38a7
Gerrit-Change-Number: 40902
Gerrit-PatchSet: 8
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Jason
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add fields for DX form instructions
Boris Shingarov has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/40901 ) Change subject: arch-power: Add fields for DX form instructions .. arch-power: Add fields for DX form instructions This introduces the extended opcode field for DS form instructions and the fields d0, d1 and d2 which are concatenated for specifying a signed integer immediate operand. Change-Id: Id60e85d79f9157d680f813bf90ab6e1e064253a9 Signed-off-by: Sandipan Das Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40901 Reviewed-by: Boris Shingarov Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/arch/power/isa/bitfields.isa M src/arch/power/types.hh 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: Boris Shingarov: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/power/isa/bitfields.isa b/src/arch/power/isa/bitfields.isa index 771a822..84a3a2c 100644 --- a/src/arch/power/isa/bitfields.isa +++ b/src/arch/power/isa/bitfields.isa @@ -37,6 +37,7 @@ def bitfield PO<31:26>; def bitfield A_XO <5:1>; def bitfield DS_XO <1:0>; +def bitfield DX_XO <5:1>; def bitfield X_XO <10:1>; def bitfield XFL_XO<10:1>; def bitfield XFX_XO<10:1>; diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh index 354da59..6f55821 100644 --- a/src/arch/power/types.hh +++ b/src/arch/power/types.hh @@ -55,6 +55,9 @@ Bitfield<15, 0> ui; Bitfield<15, 0> d; Bitfield<15, 2> ds; +Bitfield<15, 6> d0; +Bitfield<20, 16> d1; +Bitfield< 1, 0> d2; // Special purpose register identifier Bitfield<20, 11> spr; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40901 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Id60e85d79f9157d680f813bf90ab6e1e064253a9 Gerrit-Change-Number: 40901 Gerrit-PatchSet: 7 Gerrit-Owner: Sandipan Das Gerrit-Reviewer: Boris Shingarov Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix disassembly for arithmetic instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40900 )
Change subject: arch-power: Fix disassembly for arithmetic instructions
..
arch-power: Fix disassembly for arithmetic instructions
This fixes disassembly generated for integer add and subtract
arithmetic instructions based on the type of operands and the
special use cases for which the Power ISA provides extended
mnemonics.
Change-Id: I89b8271994e4d4b7b16efad170af5eeb5ee1aa10
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40900
Reviewed-by: Boris Shingarov
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/insts/integer.cc
M src/arch/power/insts/integer.hh
2 files changed, 122 insertions(+), 26 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/integer.cc
b/src/arch/power/insts/integer.cc
index 7da5bf5..2035b5c 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -68,15 +68,13 @@
ccprintf(ss, "%-10s ", myMnemonic);
// Print the first destination only
-if (_numDestRegs > 0 && printDest) {
+if (_numDestRegs > 0 && printDest)
printReg(ss, destRegIdx(0));
-}
// Print the (possibly) two source registers
if (_numSrcRegs > 0 && printSrcs) {
-if (_numDestRegs > 0 && printDest) {
+if (_numDestRegs > 0 && printDest)
ss << ", ";
-}
printReg(ss, srcRegIdx(0));
if (_numSrcRegs > 1 && printSecondSrc) {
ss << ", ";
@@ -93,27 +91,16 @@
{
std::stringstream ss;
-// Generate the correct mnemonic
-std::string myMnemonic(mnemonic);
-
-// Special cases
-if (!myMnemonic.compare("addi") && _numSrcRegs == 0) {
-myMnemonic = "li";
-} else if (!myMnemonic.compare("addis") && _numSrcRegs == 0) {
-myMnemonic = "lis";
-}
-ccprintf(ss, "%-10s ", myMnemonic);
+ccprintf(ss, "%-10s ", mnemonic);
// Print the first destination only
-if (_numDestRegs > 0) {
+if (_numDestRegs > 0)
printReg(ss, destRegIdx(0));
-}
// Print the source register
if (_numSrcRegs > 0) {
-if (_numDestRegs > 0) {
+if (_numDestRegs > 0)
ss << ", ";
-}
printReg(ss, srcRegIdx(0));
}
@@ -125,6 +112,113 @@
std::string
+IntArithOp::generateDisassembly(
+Addr pc, const Loader::SymbolTable *symtab) const
+{
+std::stringstream ss;
+bool printSecondSrc = true;
+
+// Generate the correct mnemonic
+std::string myMnemonic(mnemonic);
+
+// Special cases
+if (myMnemonic == "addme" ||
+myMnemonic == "addze" ||
+myMnemonic == "subfme" ||
+myMnemonic == "subfze" ||
+myMnemonic == "neg") {
+printSecondSrc = false;
+}
+
+// Additional characters depending on isa bits being set
+if (oe)
+myMnemonic = myMnemonic + "o";
+if (rc)
+myMnemonic = myMnemonic + ".";
+ccprintf(ss, "%-10s ", myMnemonic);
+
+// Print the first destination only
+if (_numDestRegs > 0)
+printReg(ss, destRegIdx(0));
+
+// Print the first source register
+if (_numSrcRegs > 0) {
+if (_numDestRegs > 0)
+ss << ", ";
+printReg(ss, srcRegIdx(0));
+
+// Print the second source register
+if (_numSrcRegs > 1 && printSecondSrc) {
+ss << ", ";
+printReg(ss, srcRegIdx(1));
+}
+}
+
+return ss.str();
+}
+
+
+std::string
+IntImmArithOp::generateDisassembly(
+Addr pc, const Loader::SymbolTable *symtab) const
+{
+std::stringstream ss;
+bool negateImm = false;
+
+// Generate the correct mnemonic
+std::string myMnemonic(mnemonic);
+
+// Special cases
+if (myMnemonic == "addi") {
+if (_numSrcRegs == 0) {
+myMnemonic = "li";
+} else if (si < 0) {
+myMnemonic = "subi";
+negateImm = true;
+}
+} else if (myMnemonic == "addis") {
+if (_numSrcRegs == 0) {
+myMnemonic = "lis";
+} else if (si < 0) {
+myMnemonic = "subis";
+negateImm = true;
+}
+} else if (myMnemonic == "addic" && si < 0) {
+myMnemonic = "subic";
+negateImm = true;
+} else if (myMnemonic == "addic_") {
+if (si < 0) {
+myMnemonic = "subic.";
+negateImm = true;
+} else {
+myMnemonic = "addic.";
+}
+}
+
+ccprintf(ss, "%-10s ", myMnemonic);
+
+// Print the first destination only
+if (_numDestRegs > 0)
+printReg(ss, destRegIdx(0));
+
+// Print the source register
+if (_numSrcRegs > 0) {
+if (_numDestRegs > 0)
+ss << ", ";
+
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix arithmetic instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40899 )
Change subject: arch-power: Fix arithmetic instructions
..
arch-power: Fix arithmetic instructions
The latest Power ISA introduces two new bits that record
carry and overflow out of bit 31 of the result, namely
CA32 and OV32 respectively, thereby changing the behaviour
of the add and subtract instructions that set them. Also,
now that 64-bit registers are being used, the nature of
the result, i.e. less than, greater than or equal to zero,
must be set by a 64-bit signed comparison of the result
to zero. This fixes the following instructions.
* Add Immediate (addi)
* Add Immediate Shifted (addis)
* Add (add[o][.])
* Subtract From (subf[o][.])
* Add Immediate Carrying (addic)
* Add Immediate Carrying and Record (addic.)
* Subtract From Immediate Carrying (subfic)
* Add Carrying (addc[o][.])
* Subtract From Carrying (subfc[o][.])
* Add Extended (adde[o][.])
* Subtract From Extended (subfe[o][.])
* Add to Zero Extended (addze[o][.])
* Subtract From Zero Extended (subfze[o][.])
* Negate (neg[o][.])
* Multiply Low Immediate (mulli)
* Multiply Low Word (mullw[o][.])
* Multiply High Word (mulhw[.])
* Multiply High Word Unsigned (mulhwu[.])
* Divide Word (divw[o][.])
* Divide Word Unsigned (divwu[o][.])
Change-Id: I8c79f1dca8b19010ed7b734d7ec9bb598df428c3
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40899
Reviewed-by: Boris Shingarov
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/integer.isa
M src/arch/power/regs/misc.hh
3 files changed, 33 insertions(+), 17 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index e993a7b..cc3b9f4 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -38,9 +38,8 @@
format IntImmArithOp {
7: mulli({{
-int32_t src = Ra_sw;
-int64_t prod = src * si;
-Rt = (uint32_t)prod;
+int64_t res = Ra_sd * si;
+Rt = res;
}});
8: subfic({{
@@ -486,15 +485,17 @@
}
11: IntArithCheckRcOp::mulhwu({{
-uint64_t prod = Ra_ud * Rb_ud;
-Rt = prod >> 32;
+uint64_t res = (uint64_t)Ra_uw * Rb_uw;
+res = res >> 32;
+Rt = res;
}});
40: IntSumOp::subf({{ ~Ra }}, {{ Rb }}, {{ 1 }});
75: IntArithCheckRcOp::mulhw({{
-int64_t prod = Ra_sd * Rb_sd;
-Rt = prod >> 32;
+uint64_t res = (int64_t)Ra_sw * Rb_sw;
+res = res >> 32;
+Rt = res;
}});
format IntSumOp {
@@ -508,19 +509,19 @@
}
235: IntArithCheckRcOp::mullw({{
-int64_t prod = Ra_sd * Rb_sd;
-Rt = prod;
-if (prod != (int32_t)prod) {
+int64_t res = (int64_t)Ra_sw * Rb_sw;
+if (res != (int32_t)res) {
setOV = true;
}
+Rt = res;
}}, true);
266: IntSumOp::add({{ Ra }}, {{ Rb }});
format IntArithCheckRcOp {
459: divwu({{
-uint32_t src1 = Ra_sw;
-uint32_t src2 = Rb_sw;
+uint32_t src1 = Ra_uw;
+uint32_t src2 = Rb_uw;
if (src2 != 0) {
Rt = src1 / src2;
} else {
@@ -532,9 +533,8 @@
491: divw({{
int32_t src1 = Ra_sw;
int32_t src2 = Rb_sw;
-if ((src1 != 0x8000 || src2 != 0x)
-&& src2 != 0) {
-Rt = src1 / src2;
+if ((src1 != INT32_MIN || src2 != -1) && src2 != 0) {
+Rt = (uint32_t)(src1 / src2);
} else {
Rt = 0;
setOV = true;
diff --git a/src/arch/power/isa/formats/integer.isa
b/src/arch/power/isa/formats/integer.isa
index b0840ce..8583ba0 100644
--- a/src/arch/power/isa/formats/integer.isa
+++ b/src/arch/power/isa/formats/integer.isa
@@ -44,28 +44,42 @@
'''
computeCACode = '''
-if (findCarry(32, %(result)s, %(inputa)s, %(inputb)s)) {
+if (findCarry(64, %(result)s, %(inputa)s, %(inputb)s)) {
xer.ca = 1;
} else {
xer.ca = 0;
}
+
+if (findCarry(32, %(result)s, %(inputa)s, %(inputb)s)) {
+xer.ca32 = 1;
+} else {
+xer.ca32 = 0;
+}
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Refactor arithmetic instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40898 )
Change subject: arch-power: Refactor arithmetic instructions
..
arch-power: Refactor arithmetic instructions
This changes the base classes for integer arithmetic
instructions and introduces two new classes that are used
to distinguish between instructions using register and
immediate operands.
Decoding has also been consolidated using formats that can
generate code after determining if an instruction records
carry and overflow and also if it records the nature of the
result, i.e. lesser than, greater than or equal to zero.
However, for multiply and divide instructions, the code to
determine if an overflow has occurred has been moved to the
instruction definition itself. The formats have also been
updated to make use of the new base classes.
Change-Id: I23d70ac4bad4d25d876308db0b3564c092bf574c
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40898
Reviewed-by: Boris Shingarov
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/insts/floating.hh
M src/arch/power/insts/integer.cc
M src/arch/power/insts/integer.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/fp.isa
M src/arch/power/isa/formats/integer.isa
M src/arch/power/types.hh
7 files changed, 176 insertions(+), 173 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/floating.hh
b/src/arch/power/insts/floating.hh
index 02dbbb2..ef06901 100644
--- a/src/arch/power/insts/floating.hh
+++ b/src/arch/power/insts/floating.hh
@@ -43,11 +43,12 @@
{
protected:
-bool rcSet;
+bool rc;
/// Constructor
FloatOp(const char *mnem, MachInst _machInst, OpClass __opClass)
- : PowerStaticInst(mnem, _machInst, __opClass)
+ : PowerStaticInst(mnem, _machInst, __opClass),
+rc(machInst.rc)
{
}
diff --git a/src/arch/power/insts/integer.cc
b/src/arch/power/insts/integer.cc
index a65d7b7..7da5bf5 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -61,8 +61,10 @@
}
// Additional characters depending on isa bits being set
-if (oeSet) myMnemonic = myMnemonic + "o";
-if (rcSet) myMnemonic = myMnemonic + ".";
+if (oe)
+myMnemonic = myMnemonic + "o";
+if (rc)
+myMnemonic = myMnemonic + ".";
ccprintf(ss, "%-10s ", myMnemonic);
// Print the first destination only
@@ -116,7 +118,7 @@
}
// Print the immediate value last
-ss << ", " << (int32_t)imm;
+ss << ", " << (int32_t)si;
return ss.str();
}
diff --git a/src/arch/power/insts/integer.hh
b/src/arch/power/insts/integer.hh
index 04222a1..a25e65c 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -51,8 +51,8 @@
{
protected:
-bool rcSet;
-bool oeSet;
+bool rc;
+bool oe;
// Needed for srawi only
uint32_t sh;
@@ -60,7 +60,8 @@
/// Constructor
IntOp(const char *mnem, MachInst _machInst, OpClass __opClass)
: PowerStaticInst(mnem, _machInst, __opClass),
-rcSet(false), oeSet(false)
+rc(machInst.rc),
+oe(machInst.oe)
{
}
@@ -104,14 +105,14 @@
{
protected:
-int32_t imm;
-uint32_t uimm;
+int32_t si;
+uint32_t ui;
/// Constructor
IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
: IntOp(mnem, _machInst, __opClass),
-imm(sext<16>(machInst.si)),
-uimm(machInst.si)
+si(sext<16>(machInst.si)),
+ui(machInst.si)
{
}
@@ -121,6 +122,39 @@
/**
+ * Class for integer arithmetic operations.
+ */
+class IntArithOp : public IntOp
+{
+ protected:
+
+/// Constructor
+IntArithOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : IntOp(mnem, _machInst, __opClass)
+{
+}
+};
+
+
+/**
+ * Class for integer immediate arithmetic operations.
+ */
+class IntImmArithOp : public IntArithOp
+{
+ protected:
+
+int32_t si;
+
+/// Constructor
+IntImmArithOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : IntArithOp(mnem, _machInst, __opClass),
+si(sext<16>(machInst.si))
+{
+}
+};
+
+
+/**
* Class for integer operations with a shift.
*/
class IntShiftOp : public IntOp
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 3f51386..e993a7b 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -39,42 +39,48 @@
format IntImmArithOp {
7: mulli({{
int32_t src = Ra_sw;
-int64_t prod = src * imm;
+int64_t prod = src * si;
Rt = (uint32_t)prod;
}});
-8: subfic({{ int32_t src = ~Ra; Rt = src + imm +
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add atomic load-store instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40897 )
Change subject: arch-power: Add atomic load-store instructions
..
arch-power: Add atomic load-store instructions
This adds the following instructions.
* Load Byte And Reserve Indexed (lbarx)
* Load Halfword And Reserve Indexed (lharx)
* Load Doubleword And Reserve Indexed (ldarx)
* Store Byte Conditional Indexed (stbcx.)
* Store Halfword Conditional Indexed (sthcx.)
* Store Doubleword Conditional Indexed (stdcx.)
Change-Id: Ie85d57e7e111f06dd0f17f9f4d0953be44ef5fb8
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40897
Reviewed-by: Boris Shingarov
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/isa/decoder.isa
1 file changed, 80 insertions(+), 3 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index d0d3dc9..3f51386 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -224,10 +224,29 @@
CR = insertCRField(CR, BF, cr);
}});
+52: LoadIndexOp::lbarx({{
+Rt = Mem_ub;
+Rsv = 1; RsvLen = 1; RsvAddr = EA;
+}});
+
53: LoadIndexUpdateOp::ldux({{ Rt = Mem; }});
55: LoadIndexUpdateOp::lwzux({{ Rt = Mem_uw; }});
60: IntLogicOp::andc({{ Ra = Rs & ~Rb; }});
-87: LoadIndexOp::lbzx({{ Rt = Mem_ub; }});
+
+format LoadIndexOp {
+84: ldarx({{
+Rt = Mem_ud;
+Rsv = 1; RsvLen = 8; RsvAddr = EA;
+}});
+
+87: lbzx({{ Rt = Mem_ub; }});
+
+116: lharx({{
+Rt = Mem_uh;
+Rsv = 1; RsvLen = 2; RsvAddr = EA;
+}});
+}
+
119: LoadIndexUpdateOp::lbzux({{ Rt = Mem_ub; }});
124: IntLogicOp::nor({{ Ra = ~(Rs | Rb); }});
@@ -258,7 +277,27 @@
183: stwux({{ Mem_uw = Rs_uw; }});
}
-215: StoreIndexOp::stbx({{ Mem_ub = Rs_ub; }});
+format StoreIndexOp {
+214: stdcx({{
+bool store_performed = false;
+Mem = Rs;
+if (Rsv) {
+if (RsvLen == 8) {
+if (RsvAddr == EA) {
+store_performed = true;
+}
+}
+}
+Xer xer = XER;
+Cr cr = CR;
+cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
+CR = cr;
+Rsv = 0;
+}});
+
+215: stbx({{ Mem_ub = Rs_ub; }});
+}
+
246: MiscOp::dcbtst({{ }});
247: StoreIndexUpdateOp::stbux({{ Mem_ub = Rs_ub; }});
278: MiscOp::dcbt({{ }});
@@ -319,10 +358,48 @@
660: stdbrx({{ Mem = swap_byte(Rs); }});
662: stwbrx({{ Mem_uw = swap_byte(Rs_uw); }});
663: stfsx({{ Mem_sf = Fs_sf; }});
+
+694: stbcx({{
+bool store_performed = false;
+Mem_ub = Rs_ub;
+if (Rsv) {
+if (RsvLen == 1) {
+if (RsvAddr == EA) {
+store_performed = true;
+}
+}
+}
+Xer xer = XER;
+Cr cr = CR;
+cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
+CR = cr;
+Rsv = 0;
+}});
}
695: StoreIndexUpdateOp::stfsux({{ Mem_sf = Fs_sf; }});
-727: StoreIndexOp::stfdx({{ Mem_df = Fs; }});
+
+format StoreIndexOp {
+726: sthcx({{
+bool store_performed = false;
+Mem_uh = Rs_uh;
+if (Rsv) {
+if (RsvLen == 2) {
+if (RsvAddr == EA) {
+store_performed = true;
+}
+}
+}
+Xer xer = XER;
+Cr cr = CR;
+cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
+CR = cr;
+Rsv = 0;
+}});
+
+727: stfdx({{ Mem_df = Fs; }});
+}
+
759: StoreIndexUpdateOp::stfdux({{ Mem_df = Fs; }});
790: LoadIndexOp::lhbrx({{ Rt = swap_byte(Mem_uh); }});
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie85d57e7e111f06dd0f17f9f4d0953be44ef5fb8
Gerrit-Change-Number: 40897
Gerrit-PatchSet:
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add doubleword load-store instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40895 )
Change subject: arch-power: Add doubleword load-store instructions
..
arch-power: Add doubleword load-store instructions
This introduces new formats for DS form instructions and
adds the following instructions.
* Load Doubleword (ld)
* Load Doubleword Indexed (ldx)
* Load Doubleword with Update (ldu)
* Load Doubleword with Update Indexed (ldux)
* Store Doubleword (std)
* Store Doubleword Indexed (stdx)
* Store Doubleword with Update (stdu)
* Store Doubleword with Update Indexed (stdux)
Change-Id: I2a88364e82a11685e081f57be5fd5afd44335668
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40895
Reviewed-by: Boris Shingarov
Reviewed-by: lkcl
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/mem.isa
2 files changed, 57 insertions(+), 1 deletion(-)
Approvals:
Boris Shingarov: Looks good to me, approved
lkcl: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index c81e65b..d0d3dc9 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -201,6 +201,7 @@
Rsv = 1; RsvLen = 4; RsvAddr = EA;
}});
+21: ldx({{ Rt = Mem; }});
23: lwzx({{ Rt = Mem_uw; }});
}
@@ -223,6 +224,7 @@
CR = insertCRField(CR, BF, cr);
}});
+53: LoadIndexUpdateOp::ldux({{ Rt = Mem; }});
55: LoadIndexUpdateOp::lwzux({{ Rt = Mem_uw; }});
60: IntLogicOp::andc({{ Ra = Rs & ~Rb; }});
87: LoadIndexOp::lbzx({{ Rt = Mem_ub; }});
@@ -230,6 +232,7 @@
124: IntLogicOp::nor({{ Ra = ~(Rs | Rb); }});
format StoreIndexOp {
+149: stdx({{ Mem = Rs }});
150: stwcx({{
bool store_performed = false;
Mem_uw = Rs_uw;
@@ -250,7 +253,11 @@
151: stwx({{ Mem_uw = Rs_uw; }});
}
-183: StoreIndexUpdateOp::stwux({{ Mem = Rs; }});
+format StoreIndexUpdateOp {
+181: stdux({{ Mem = Rs; }});
+183: stwux({{ Mem_uw = Rs_uw; }});
+}
+
215: StoreIndexOp::stbx({{ Mem_ub = Rs_ub; }});
246: MiscOp::dcbtst({{ }});
247: StoreIndexUpdateOp::stbux({{ Mem_ub = Rs_ub; }});
@@ -543,6 +550,8 @@
55: StoreDispUpdateOp::stfdu({{ Mem_df = Fs; }});
58: decode DS_XO {
+0: LoadDispShiftOp::ld({{ Rt = Mem; }});
+1: LoadDispShiftUpdateOp::ldu({{ Rt = Mem; }});
2: LoadDispShiftOp::lwa({{ Rt = Mem_sw; }});
}
@@ -559,6 +568,11 @@
}
}
+62: decode DS_XO {
+0: StoreDispShiftOp::std({{ Mem = Rs; }});
+1: StoreDispShiftUpdateOp::stdu({{ Mem = Rs; }});
+}
+
63: decode A_XO {
format FloatArithOp {
20: fsub({{ Ft = Fa - Fb; }});
diff --git a/src/arch/power/isa/formats/mem.isa
b/src/arch/power/isa/formats/mem.isa
index d2b3ab7..4886296 100644
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -311,6 +311,16 @@
}};
+def format StoreDispShiftOp(memacc_code,
+ea_code = {{ EA = Ra + (ds << 2); }},
+ea_code_ra0 = {{ EA = (ds << 2); }},
+mem_flags = [], inst_flags = []) {{
+(header_output, decoder_output, decode_block, exec_output) = \
+GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
+ 'MemDispShiftOp', 'Store', mem_flags, inst_flags)
+}};
+
+
def format LoadDispUpdateOp(memacc_code, ea_code = {{ EA = Ra + d; }},
mem_flags = [], inst_flags = []) {{
@@ -339,3 +349,35 @@
decode_template = CheckRaZeroDecode,
exec_template_base = 'Store')
}};
+
+
+def format LoadDispShiftUpdateOp(memacc_code,
+ ea_code = {{ EA = Ra + (ds << 2); }},
+ mem_flags = [], inst_flags = []) {{
+
+# Add in the update code
+memacc_code += 'Ra = EA;'
+
+# Generate the class
+(header_output, decoder_output, decode_block, exec_output) = \
+LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags,
inst_flags,
+ base_class = 'MemDispShiftOp',
+ decode_template = CheckRaRtDecode,
+ exec_template_base = 'Load')
+}};
+
+
+def format StoreDispShiftUpdateOp(memacc_code,
+ ea_code = {{ EA = Ra + (ds << 2); }},
+ mem_flags = [], inst_flags = []) {{
+
+# Add in the update code
+memacc_code += 'Ra = EA;'
+
+# Generate the class
+
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix disassembly for load-store instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40894 )
Change subject: arch-power: Fix disassembly for load-store instructions
..
arch-power: Fix disassembly for load-store instructions
This fixes disassembly generated for load-store instructions
based on how the base classess that are used to distinguish
between the types of operands used by these instructions.
Change-Id: I5a0f8644cdc6fec934475536861ad342c0a1fb4c
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40894
Reviewed-by: Boris Shingarov
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/insts/mem.cc
M src/arch/power/insts/mem.hh
2 files changed, 157 insertions(+), 4 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/mem.cc b/src/arch/power/insts/mem.cc
index 3275623..a2954f8 100644
--- a/src/arch/power/insts/mem.cc
+++ b/src/arch/power/insts/mem.cc
@@ -38,6 +38,7 @@
return csprintf("%-10s", mnemonic);
}
+
std::string
MemDispOp::generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const
@@ -59,16 +60,162 @@
// Print the data register for a store
else {
-printReg(ss, srcRegIdx(1));
+if (_numSrcRegs > 0) {
+printReg(ss, srcRegIdx(0));
+}
}
// Print the displacement
ss << ", " << d;
-
-// Print the address register
ss << "(";
-printReg(ss, srcRegIdx(0));
+
+// Print the address register for a load
+if (!flags[IsStore]) {
+if (_numSrcRegs > 0) {
+printReg(ss, srcRegIdx(0));
+}
+
+// The address register is skipped if it is R0
+else {
+ss << "0";
+}
+}
+
+// Print the address register for a store
+else {
+if (_numSrcRegs > 1) {
+printReg(ss, srcRegIdx(1));
+}
+
+// The address register is skipped if it is R0
+else {
+ss << "0";
+}
+}
+
ss << ")";
return ss.str();
}
+
+
+std::string
+MemDispShiftOp::generateDisassembly(
+Addr pc, const Loader::SymbolTable *symtab) const
+{
+std::stringstream ss;
+
+ccprintf(ss, "%-10s ", mnemonic);
+
+// Print the destination only for a load
+if (!flags[IsStore]) {
+if (_numDestRegs > 0) {
+
+// If the instruction updates the source register with the
+// EA, then this source register is placed in position 0,
+// therefore we print the last destination register.
+printReg(ss, destRegIdx(_numDestRegs-1));
+}
+}
+
+// Print the data register for a store
+else {
+if (_numSrcRegs > 0) {
+printReg(ss, srcRegIdx(0));
+}
+}
+
+// Print the displacement
+ss << ", " << (ds << 2);
+ss << "(";
+
+// Print the address register for a load
+if (!flags[IsStore]) {
+if (_numSrcRegs > 0) {
+printReg(ss, srcRegIdx(0));
+}
+
+// The address register is skipped if it is R0
+else {
+ss << "0";
+}
+}
+
+// Print the address register for a store
+else {
+if (_numSrcRegs > 1) {
+printReg(ss, srcRegIdx(1));
+}
+
+// The address register is skipped if it is R0
+else {
+ss << "0";
+}
+}
+
+ss << ")";
+
+return ss.str();
+}
+
+
+std::string
+MemIndexOp::generateDisassembly(
+Addr pc, const Loader::SymbolTable *symtab) const
+{
+std::stringstream ss;
+
+ccprintf(ss, "%-10s ", mnemonic);
+
+// Print the destination only for a load
+if (!flags[IsStore]) {
+if (_numDestRegs > 0) {
+
+// If the instruction updates the source register with the
+// EA, then this source register is placed in position 0,
+// therefore we print the last destination register.
+printReg(ss, destRegIdx(_numDestRegs-1));
+}
+}
+
+// Print the data register for a store
+else {
+if (_numSrcRegs > 0) {
+printReg(ss, srcRegIdx(0));
+}
+}
+
+ss << ", ";
+
+// Print the address registers for a load
+if (!flags[IsStore]) {
+if (_numSrcRegs > 1) {
+printReg(ss, srcRegIdx(0));
+ss << ", ";
+printReg(ss, srcRegIdx(1));
+}
+
+// The first address register is skipped if it is R0
+else if (_numSrcRegs > 0) {
+ss << "0, ";
+printReg(ss, srcRegIdx(0));
+}
+}
+
+// Print the address registers for a store
+else {
+if (_numSrcRegs > 2) {
+printReg(ss, srcRegIdx(1));
+ss << ", ";
+printReg(ss, srcRegIdx(2));
+}
+
+
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Add (BUSY_BLKD,SnpOnceFwd) transition
Carlos Falquez has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/46901 )
Change subject: mem-ruby: Add (BUSY_BLKD,SnpOnceFwd) transition
..
mem-ruby: Add (BUSY_BLKD,SnpOnceFwd) transition
Add (BUSY_BLKD,SnpOnceFwd) cache transition
to the Ruby CHI protocol.
Change-Id: I150880b26dee869b48cfd16fb661b9487527a8cd
Signed-off-by: Carlos Falquez
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46901
Reviewed-by: Jason Lowe-Power
Reviewed-by: Tiago Mück
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Tiago Mück: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
b/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
index d69d28e..0d303fc 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
@@ -685,7 +685,7 @@
transition(BUSY_BLKD,
{SnpCleanInvalid,SnpShared,SnpUnique,SnpSharedFwd,SnpUniqueFwd,
-SnpNotSharedDirtyFwd, SnpOnce}) {
+SnpOnce,SnpOnceFwd,SnpNotSharedDirtyFwd}) {
StallSnoop;
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/46901
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I150880b26dee869b48cfd16fb661b9487527a8cd
Gerrit-Change-Number: 46901
Gerrit-PatchSet: 3
Gerrit-Owner: Carlos Falquez
Gerrit-Reviewer: Carlos Falquez
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python,scons,mem-ruby: Tag origin of generated files
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/47301 )
Change subject: python,scons,mem-ruby: Tag origin of generated files
..
python,scons,mem-ruby: Tag origin of generated files
This will make it easier to backtrack and modify
such files when needed.
Change-Id: If09b6f848e607fb21a0acf2114ce0b9b0aa4751f
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47301
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/SConscript
M src/mem/slicc/symbols/StateMachine.py
M src/mem/slicc/symbols/SymbolTable.py
M src/mem/slicc/symbols/Type.py
M src/python/m5/util/code_formatter.py
5 files changed, 32 insertions(+), 42 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/SConscript b/src/SConscript
index 08cfeee..804160b 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1149,10 +1149,6 @@
# file header
code('''
-/*
- * DO NOT EDIT THIS FILE! Automatically generated by SCons.
- */
-
#include "base/debug.hh"
namespace Debug {
@@ -1206,10 +1202,6 @@
# file header boilerplate
code('''\
-/*
- * DO NOT EDIT THIS FILE! Automatically generated by SCons.
- */
-
#ifndef __DEBUG_${name}_HH__
#define __DEBUG_${name}_HH__
diff --git a/src/mem/slicc/symbols/StateMachine.py
b/src/mem/slicc/symbols/StateMachine.py
index 0c4651d..42b5553 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -272,11 +272,7 @@
c_ident = "%s_Controller" % self.ident
code('''
-/** \\file $c_ident.hh
- *
- * Auto generated C++ code started by $__file__:$__line__
- * Created by slicc definition of Module "${{self.short}}"
- */
+// Created by slicc definition of Module "${{self.short}}"
#ifndef __${ident}_CONTROLLER_HH__
#define __${ident}_CONTROLLER_HH__
@@ -492,11 +488,7 @@
'''
code('''
-/** \\file $c_ident.cc
- *
- * Auto generated C++ code started by $__file__:$__line__
- * Created by slicc definition of Module "${{self.short}}"
- */
+// Created by slicc definition of Module "${{self.short}}"
#include
#include
@@ -1220,7 +1212,6 @@
outputRequest_types = False
code('''
-// Auto generated C++ code started by $__file__:$__line__
// ${ident}: ${{self.short}}
#include
@@ -1343,7 +1334,6 @@
ident = self.ident
code('''
-// Auto generated C++ code started by $__file__:$__line__
// ${ident}: ${{self.short}}
#include
diff --git a/src/mem/slicc/symbols/SymbolTable.py
b/src/mem/slicc/symbols/SymbolTable.py
index e4fc0a3..fb01b01 100644
--- a/src/mem/slicc/symbols/SymbolTable.py
+++ b/src/mem/slicc/symbols/SymbolTable.py
@@ -126,7 +126,6 @@
makeDir(path)
code = self.codeFormatter()
-code('/** Auto generated C++ code started by $__file__:$__line__
*/')
for include_path in includes:
code('#include "${{include_path}}"')
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index a1ca200..c6013f8 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -204,12 +204,6 @@
def printTypeHH(self, path):
code = self.symtab.codeFormatter()
code('''
-/** \\file ${{self.c_ident}}.hh
- *
- *
- * Auto generated C++ code started by $__file__:$__line__
- */
-
#ifndef __${{self.c_ident}}_HH__
#define __${{self.c_ident}}_HH__
@@ -404,11 +398,6 @@
code = self.symtab.codeFormatter()
code('''
-/** \\file ${{self.c_ident}}.cc
- *
- * Auto generated C++ code started by $__file__:$__line__
- */
-
#include
#include
@@ -449,11 +438,6 @@
def printEnumHH(self, path):
code = self.symtab.codeFormatter()
code('''
-/** \\file ${{self.c_ident}}.hh
- *
- * Auto generated C++ code started by $__file__:$__line__
- */
-
#ifndef __${{self.c_ident}}_HH__
#define __${{self.c_ident}}_HH__
@@ -555,11 +539,6 @@
def printEnumCC(self, path):
code = self.symtab.codeFormatter()
code('''
-/** \\file ${{self.c_ident}}.hh
- *
- * Auto generated C++ code started by $__file__:$__line__
- */
-
#include
#include
#include
diff --git a/src/python/m5/util/code_formatter.py
b/src/python/m5/util/code_formatter.py
index 0ca8c98..374e8cc 100644
--- a/src/python/m5/util/code_formatter.py
+++ b/src/python/m5/util/code_formatter.py
@@ -154,6 +154,36 @@
def write(self, *args):
f = open(os.path.join(*args), "w")
+name, extension = os.path.splitext(f.name)
+
+# Add a comment to inform which file generated the generated file
+# to make it easier to backtrack and modify generated code
+frame = inspect.currentframe().f_back
+if re.match('\.(cc|hh|c|h)', extension) is not None:
+f.write(f'''/**
+ * DO
[gem5-dev] Change in gem5/gem5[develop]: dev,sim: Fix compiler not finding specialized byte_swap
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/46322 )
Change subject: dev,sim: Fix compiler not finding specialized byte_swap
..
dev,sim: Fix compiler not finding specialized byte_swap
The specialized version of byte_swap cannot be found by
the compiler. As a temporary workaround to get the major
patch going, move the specialization to the base header
file.
Change-Id: I7d2bfc1c29b70042860ae06cdc043c0490cd8916
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46322
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M src/dev/virtio/base.hh
M src/sim/byteswap.hh
2 files changed, 21 insertions(+), 8 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/virtio/base.hh b/src/dev/virtio/base.hh
index 350e510..6eeb4a4 100644
--- a/src/dev/virtio/base.hh
+++ b/src/dev/virtio/base.hh
@@ -68,17 +68,18 @@
* of byte swapping.
*/
-
-static inline vring_used_elem
-swap_byte(vring_used_elem v)
+template
+inline std::enable_if_t::value, T>
+swap_byte(T v)
{
v.id = swap_byte(v.id);
v.len = swap_byte(v.len);
return v;
}
-static inline vring_desc
-swap_byte(vring_desc v)
+template
+inline std::enable_if_t::value, T>
+swap_byte(T v)
{
v.addr = swap_byte(v.addr);
v.len = swap_byte(v.len);
diff --git a/src/sim/byteswap.hh b/src/sim/byteswap.hh
index 30e63d1..82282ec 100644
--- a/src/sim/byteswap.hh
+++ b/src/sim/byteswap.hh
@@ -33,9 +33,6 @@
#ifndef __SIM_BYTE_SWAP_HH__
#define __SIM_BYTE_SWAP_HH__
-#include "base/types.hh"
-#include "enums/ByteOrder.hh"
-
// This lets us figure out what the byte order of the host system is
#if defined(__linux__)
#include
@@ -55,6 +52,12 @@
#include
+#include "base/types.hh"
+#include "enums/ByteOrder.hh"
+
+struct vring_used_elem;
+struct vring_desc;
+
// These functions actually perform the swapping for parameters of various
bit
// lengths.
inline uint64_t
@@ -135,6 +138,15 @@
return x;
}
+// Make the function visible in case we need to declare a version of it for
+// other types
+template
+std::enable_if_t::value, T>
+swap_byte(T v);
+template
+std::enable_if_t::value, T>
+swap_byte(T v);
+
template
inline std::array
swap_byte(std::array a)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/46322
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7d2bfc1c29b70042860ae06cdc043c0490cd8916
Gerrit-Change-Number: 46322
Gerrit-PatchSet: 5
Gerrit-Owner: Daniel Carvalho
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem: Conclude deprecation of MemObject
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/47299 )
Change subject: mem: Conclude deprecation of MemObject
..
mem: Conclude deprecation of MemObject
This has been marked as deprecated a few versions ago,
so it is safe to conclude its deprecation process.
Change-Id: I20d37700c97264080a7b19cf0cf9ccf8a5b65c32
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47299
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/dev/arm/css/scmi_platform.hh
D src/mem/MemObject.py
M src/mem/SConscript
D src/mem/mem_object.hh
4 files changed, 0 insertions(+), 98 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/css/scmi_platform.hh
b/src/dev/arm/css/scmi_platform.hh
index 5cd52bc..e56f024 100644
--- a/src/dev/arm/css/scmi_platform.hh
+++ b/src/dev/arm/css/scmi_platform.hh
@@ -41,7 +41,6 @@
#include "dev/arm/css/scmi_protocols.hh"
#include "dev/arm/css/scp.hh"
#include "dev/dma_device.hh"
-#include "mem/mem_object.hh"
#include "params/ScmiPlatform.hh"
class Doorbell;
diff --git a/src/mem/MemObject.py b/src/mem/MemObject.py
deleted file mode 100644
index 76b519a..000
--- a/src/mem/MemObject.py
+++ /dev/null
@@ -1,32 +0,0 @@
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-from m5.objects.ClockedObject import ClockedObject
-
-class MemObject(ClockedObject):
-type = 'MemObject'
-abstract = True
-cxx_header = "mem/mem_object.hh"
diff --git a/src/mem/SConscript b/src/mem/SConscript
index edf2985..5d3c5e6 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -53,7 +53,6 @@
SimObject('ExternalMaster.py')
SimObject('ExternalSlave.py')
SimObject('CfiMemory.py')
-SimObject('MemObject.py')
SimObject('SimpleMemory.py')
SimObject('XBar.py')
SimObject('HMCController.py')
diff --git a/src/mem/mem_object.hh b/src/mem/mem_object.hh
deleted file mode 100644
index 916eb26..000
--- a/src/mem/mem_object.hh
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2012 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright
[gem5-dev] Change in gem5/gem5[develop]: mem: Move QoS' MemSinkInterface into gem5::qos
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/47300 )
Change subject: mem: Move QoS' MemSinkInterface into gem5::qos
..
mem: Move QoS' MemSinkInterface into gem5::qos
This class has been mistakenly added outside the
qos namespace.
Change-Id: I12c5dc7558a689c771761754e59d78a8010e422f
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47300
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/qos/QoSMemSinkInterface.py
M src/mem/qos/mem_sink.cc
M src/mem/qos/mem_sink.hh
3 files changed, 12 insertions(+), 11 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/qos/QoSMemSinkInterface.py
b/src/mem/qos/QoSMemSinkInterface.py
index 37ddf78..9b3b89e 100644
--- a/src/mem/qos/QoSMemSinkInterface.py
+++ b/src/mem/qos/QoSMemSinkInterface.py
@@ -38,6 +38,7 @@
class QoSMemSinkInterface(AbstractMemory):
type = 'QoSMemSinkInterface'
cxx_header = "mem/qos/mem_sink.hh"
+cxx_class = 'qos::MemSinkInterface'
def controller(self):
"""
diff --git a/src/mem/qos/mem_sink.cc b/src/mem/qos/mem_sink.cc
index 98a5e3f..f9be06c 100644
--- a/src/mem/qos/mem_sink.cc
+++ b/src/mem/qos/mem_sink.cc
@@ -386,9 +386,9 @@
return mem.recvTimingReq(pkt);
}
-} // namespace qos
-
-QoSMemSinkInterface::QoSMemSinkInterface(const QoSMemSinkInterfaceParams
&_p)
+MemSinkInterface::MemSinkInterface(const QoSMemSinkInterfaceParams &_p)
: AbstractMemory(_p)
{
}
+
+} // namespace qos
diff --git a/src/mem/qos/mem_sink.hh b/src/mem/qos/mem_sink.hh
index 3c229ec..247db22 100644
--- a/src/mem/qos/mem_sink.hh
+++ b/src/mem/qos/mem_sink.hh
@@ -52,12 +52,13 @@
#include "sim/eventq.hh"
struct QoSMemSinkInterfaceParams;
-class QoSMemSinkInterface;
GEM5_DEPRECATED_NAMESPACE(QoS, qos);
namespace qos
{
+class MemSinkInterface;
+
/**
* QoS Memory Sink
*
@@ -177,7 +178,7 @@
/**
* Create pointer to interface of actual media
*/
-QoSMemSinkInterface* const interface;
+MemSinkInterface* const interface;
/** Read request pending */
bool retryRdReq;
@@ -262,19 +263,18 @@
MemSinkCtrlStats stats;
};
-} // namespace qos
-
-class QoSMemSinkInterface : public AbstractMemory
+class MemSinkInterface : public AbstractMemory
{
public:
/** Setting a pointer to the interface */
-void setMemCtrl(qos::MemSinkCtrl* _ctrl) { ctrl = _ctrl; };
+void setMemCtrl(MemSinkCtrl* _ctrl) { ctrl = _ctrl; };
/** Pointer to the controller */
-qos::MemSinkCtrl* ctrl;
+MemSinkCtrl* ctrl;
-QoSMemSinkInterface(const QoSMemSinkInterfaceParams &_p);
+MemSinkInterface(const QoSMemSinkInterfaceParams &_p);
};
+} // namespace qos
#endif /* __MEM_QOS_MEM_SINK_HH__ */
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/47300
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I12c5dc7558a689c771761754e59d78a8010e422f
Gerrit-Change-Number: 47300
Gerrit-PatchSet: 2
Gerrit-Owner: Daniel Carvalho
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Re: gem5 namespace
Thanks, Daniel! We'll put this toward the top of the priority list and be
sure to get it in for the release.
Cheers,
Jason
On Sun, Jun 27, 2021 at 7:58 PM Daniel Carvalho via gem5-dev <
gem5-dev@gem5.org> wrote:
> Dear all,
>
> We have already renamed most of the existing namespaces to snake case.
> Before moving on to the last ones, which may generate more conflicts, I
> have encapsulated most of gem5 in a gem5 namespace. This will ensure that
> these last - and possibly most likely to generate conflicts - renames
> generate less issues. The respective chain can be found in
> https://gem5-review.googlesource.com/c/public/gem5/+/46323/4 .
>
> The approach taken to implement the gem5 namespace was not ideal, since it
> is a huge dump on the whole project instead of a per-dir approach; however,
> it was a trade-off between number of rebasing conflicts that I would have
> to deal with, and the time I had available for this project. To make it at
> least a bit reviewable, I have split it into sub-patches with common
> approaches. These patches will be squashed as soon as they are approved.
>
> Finally, every time I do a git push, many conflicts pop up. This requires
> a lot of effort to support, and processing power to recompile everything
> and make sure everything still works (I don't currently have the latter).
> Also, the next version is on the corner, and it would be great to deliver
> the gem5 namespace with it. Therefore, I would like to get these changes in
> ASAP. When problems show up - and they will - they can be more easily
> fixed, since this change is trivial - one will most likely just need to add
> a "namespace gem5 {" to a specific file that is compiled in a specific
> simulation configuration.
>
> *tl;dr*: Could you review the namespace patches so that we can try to get
> them in for the next version?
>
> Regards,
> Daniel
> Em sexta-feira, 7 de maio de 2021 02:30:13 BRT, Gabe Black via gem5-dev <
> gem5-dev@gem5.org> escreveu:
>
>
> Be warned though, that there are some pitfalls with this namespace
> deprecation approach. The namespaces here are not actually equivalent, and
> so the old deprecated namespace can have things added to it that won't show
> up in the new one. This is probably not that big a deal in practice, and
> should be pretty useful letting people know what's going on, but it's still
> important to be aware of limitations.
>
> Gabe
>
> On Thu, May 6, 2021 at 7:36 AM Jason Lowe-Power via gem5-dev <
> gem5-dev@gem5.org> wrote:
>
> Thanks for putting this all together, Daniel!
>
> IMO, we should do our best with providing deprecation notices, but not
> bend over backwards. For things that are easy to add deprecations to (e.g.,
> function names / class names) we should do it, and for things that have a
> big impact on our users we should provide the warnings. However, if it's
> very difficult to provide the notice *and* if it's for something that is
> unlikely to affect users, then the deprecation warnings are less important.
>
> Example: if we change `panic` to `gem5_panic` (or `GEM5_PANIC`?) we
> definitely need a deprecation warning. This will significantly impact
> users. If, on the other hand, we change a macro that is used in exactly one
> place, it's probably less important
>
> Thanks for coming up with a way to do namespaces! This will be useful.
>
> Cheers,
> Jason
>
> On Thu, May 6, 2021 at 7:06 AM Daniel Carvalho via gem5-dev <
> gem5-dev@gem5.org> wrote:
>
> Glad to see that we are reaching a consensus! Then we will create the
> "gem5" namespace, rename (most) macros to use a "GEM5_" prefix, and will
> rename all namespaces to snake case.
>
>
> I agree that we should do the renaming on a case-by-case basis. I've
> created a new Jira Epic to cover converting all namespaces to snake case:
> https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues/GEM5-974 .
>
>
> Regarding deprecating namespaces, aliases cannot be assigned attributes
> (thus they cannot be marked as deprecated), but I believe this will do the
> trick:
>
>
> #define GEM5_DEPRECATE_NAMESPACE(old_namespace, new_namespace) \
> namespace [[gnu::deprecated("Please use the new namespace: '" \
> #new_namespace "'")]] old_namespace { \
> using namespace new_namespace; \
> }
>
>
> Example:
>
>
> // Suppose we want to rename a namespace from Test to test
> namespace test {
> int var;
> }
> // This can be added to the base file (i.e., the one we know everybody
> will include)
> GEM5_DEPRECATE_NAMESPACE(Test, test)
>
> ...
>
> // In code, somewhere:
> test::var = 2; // Does not show deprecation warning
> Test::var = 2; // Shows deprecation warning
>
>
> Cheers,
>
> Daniel
> Em quarta-feira, 5 de maio de 2021 23:28:31 BRT, Gabe Black via gem5-dev <
> gem5-dev@gem5.org> escreveu:
>
>
> Yeah, we don't have a ton of namespaces already, but having two copies of
> all of them for a while might be messy. I also don't think
