[gem5-dev] Re: Kokoro failures
Are there examples of this timeout happening recently? I can't see any over the past week. There's a separate issue affecting one of Gabe's patches that I'm looking into (here: https://gem5-review.googlesource.com/c/public/gem5/+/56303) but these appear to be due to dynamic libraries not linking correctly. The only change in testing in the last month has been using clang-11 instead of clang-9 to do the clang compilation check. It's possible clang-11 takes longer than clang-9 did? In December I increase the timeout to 7 hours to give us more time to run tests as we were experiencing some timeouts, I think due to the inclusion of some more tests. We could move some tests to the Nightly run fairly easily. -- Dr. Bobby R. Bruce Room 3050, Kemper Hall, UC Davis Davis, CA, 95616 web: https://www.bobbybruce.net On Thu, Feb 3, 2022 at 7:00 AM Giacomo Travaglini < giacomo.travagl...@arm.com> wrote: > Hi all, > > > > I am seeing a lot of failures on kokoro due to timeouts. > > Have we recently added some extra tests to the quick/pre-submit > regressions? > > > > Kind Regards > > > > Giacomo > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Replace MISCREG_CP14/15_UNIMPL with MISCREG_UNKNOWN
Attention is currently required from: Andreas Sandberg, Richard Cooper.
Hello Andreas Sandberg, Richard Cooper,
I'd like you to do a code review.
Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/56426
to review the following change.
Change subject: arch-arm: Replace MISCREG_CP14/15_UNIMPL with
MISCREG_UNKNOWN
..
arch-arm: Replace MISCREG_CP14/15_UNIMPL with MISCREG_UNKNOWN
MISCREG_UNKNOWN is the MiscRegIdx of an invalid AArch64 system
register. There is no need to define extra ids for AArch32 CP14/CP15
registers.
We are therefore removing them in favour of MISCREG_UNKNOWN instead
Signed-off-by: Giacomo Travaglini
Change-Id: Ib41813dfcb6a9cad84b7cef9603bc530cf4b593d
Reviewed-by: Richard Cooper
Reviewed-by: Andreas Sandberg
---
M src/arch/arm/isa/formats/misc.isa
M src/arch/arm/regs/misc.cc
M src/arch/arm/regs/misc.hh
3 files changed, 25 insertions(+), 17 deletions(-)
diff --git a/src/arch/arm/isa/formats/misc.isa
b/src/arch/arm/isa/formats/misc.isa
index 32fccc8..0a11ba5 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -166,7 +166,7 @@
switch (miscReg) {
case MISCREG_NOP:
return new NopInst(machInst);
- case MISCREG_CP14_UNIMPL:
+ case MISCREG_UNKNOWN:
return new FailUnimplemented(isRead ? "mrc unknown" : "mcr
unknown",
machInst,
csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s
unknown",
@@ -211,7 +211,7 @@
case MISCREG_NOP:
return new McrMrcMiscInst(isRead ? "mrc nop" : "mcr nop",
machInst, iss, MISCREG_NOP);
- case MISCREG_CP15_UNIMPL:
+ case MISCREG_UNKNOWN:
return new FailUnimplemented(isRead ? "mrc unkown" : "mcr
unkown",
machInst,
csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s
unknown",
@@ -301,7 +301,7 @@
const bool isRead = bits(machInst, 20);
switch (miscReg) {
- case MISCREG_CP15_UNIMPL:
+ case MISCREG_UNKNOWN:
return new FailUnimplemented(isRead ? "mrc" : "mcr", machInst,
csprintf("miscreg crm:%d opc1:%d 64-bit %s unknown",
crm, opc1, isRead ? "read" : "write"));
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 0e58d93..0a95a55 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -333,7 +333,7 @@
// If we get here then it must be a register that we haven't
implemented
warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
crn, opc1, crm, opc2);
-return MISCREG_CP14_UNIMPL;
+return MISCREG_UNKNOWN;
}
MiscRegIndex
@@ -1143,7 +1143,7 @@
return MISCREG_IMPDEF_UNIMPL;
}
// Unrecognized register
-return MISCREG_CP15_UNIMPL;
+return MISCREG_UNKNOWN;
}
MiscRegIndex
@@ -1202,7 +1202,7 @@
break;
}
// Unrecognized register
-return MISCREG_CP15_UNIMPL;
+return MISCREG_UNKNOWN;
}
std::tuple
@@ -4545,12 +4545,6 @@
.allPrivileges();
InitReg(MISCREG_RAZ)
.allPrivileges().exceptUserMode().writes(0);
-InitReg(MISCREG_CP14_UNIMPL)
- .unimplemented()
- .warnNotFail();
-InitReg(MISCREG_CP15_UNIMPL)
- .unimplemented()
- .warnNotFail();
InitReg(MISCREG_UNKNOWN);
InitReg(MISCREG_IMPDEF_UNIMPL)
.unimplemented()
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index ea58ad2..b70e3fe 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -1059,7 +1059,7 @@
// NUM_PHYS_MISCREGS specifies the number of actual physical
// registers, not considering the following pseudo-registers
-// (dummy registers), like UNKNOWN, CP15_UNIMPL,
MISCREG_IMPDEF_UNIMPL.
+// (dummy registers), like MISCREG_UNKNOWN, MISCREG_IMPDEF_UNIMPL.
// Checkpointing should use this physical index when
// saving/restoring register values.
NUM_PHYS_MISCREGS,
@@ -1067,8 +1067,6 @@
// Dummy registers
MISCREG_NOP,
MISCREG_RAZ,
-MISCREG_CP14_UNIMPL,
-MISCREG_CP15_UNIMPL,
MISCREG_UNKNOWN,
// Implementation defined register: this represent
@@ -2206,8 +2204,6 @@
// Dummy registers
"nop",
"raz",
-"cp14_unimpl",
-"cp15_unimpl",
"unknown",
"impl_defined",
"erridr_el1",
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/56426
To unsubscribe, or for help writing mail filters, visit
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib41813dfcb6a9cad84b7cef9603bc530cf4b593d
Gerrit-Change-Number: 56426
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix typo in SDCR name
Attention is currently required from: Andreas Sandberg, Richard Cooper. Hello Andreas Sandberg, Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/56427 to review the following change. Change subject: arch-arm: Fix typo in SDCR name .. arch-arm: Fix typo in SDCR name SDRC -> SDCR Signed-off-by: Giacomo Travaglini Change-Id: Ib7fce528dbfcb7de2cac73b134cf05e78a186762 Reviewed-by: Richard Cooper Reviewed-by: Andreas Sandberg --- M src/arch/arm/regs/misc.hh 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh index b70e3fe..0966a93 100644 --- a/src/arch/arm/regs/misc.hh +++ b/src/arch/arm/regs/misc.hh @@ -1392,7 +1392,7 @@ "actlr_ns", "actlr_s", "cpacr", -"sdrc", +"sdcr", "scr", "sder", "nsacr", -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/56427 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ib7fce528dbfcb7de2cac73b134cf05e78a186762 Gerrit-Change-Number: 56427 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Andreas Sandberg Gerrit-Attention: Richard Cooper Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Gicv3 implementation of the Gicv3Registers interface
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/55612 )
(
6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: dev-arm: Gicv3 implementation of the Gicv3Registers
interface
..
dev-arm: Gicv3 implementation of the Gicv3Registers interface
Signed-off-by: Giacomo Travaglini
Change-Id: Iba23604cc6f7d5a1de91c287b4546154fcb20535
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55612
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/dev/arm/gic_v3.cc
M src/dev/arm/gic_v3.hh
M src/dev/arm/gic_v3_cpu_interface.cc
M src/dev/arm/gic_v3_cpu_interface.hh
M src/dev/arm/gic_v3_distributor.cc
M src/dev/arm/gic_v3_distributor.hh
M src/dev/arm/gic_v3_redistributor.cc
M src/dev/arm/gic_v3_redistributor.hh
8 files changed, 302 insertions(+), 12 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc
index 223e86a..dde3818 100644
--- a/src/dev/arm/gic_v3.cc
+++ b/src/dev/arm/gic_v3.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 ARM Limited
+ * Copyright (c) 2019-2022 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -54,6 +54,80 @@
namespace gem5
{
+void
+Gicv3Registers::copyDistRegister(Gicv3Registers* from,
+ Gicv3Registers* to,
+ Addr daddr)
+{
+auto val = from->readDistributor(daddr);
+DPRINTF(GIC, "copy dist 0x%x 0x%08x\n", daddr, val);
+to->writeDistributor(daddr, val);
+}
+
+void
+Gicv3Registers::copyRedistRegister(Gicv3Registers* from,
+ Gicv3Registers* to,
+ const ArmISA::Affinity , Addr daddr)
+{
+auto val = from->readRedistributor(aff, daddr);
+DPRINTF(GIC,
+"copy redist (aff3: %d, aff2: %d, aff1: %d, aff0: %d) "
+"0x%x 0x%08x\n",
+aff.aff3, aff.aff2, aff.aff1, aff.aff0, daddr, val);
+
+to->writeRedistributor(aff, daddr, val);
+}
+
+void
+Gicv3Registers::copyCpuRegister(Gicv3Registers* from,
+Gicv3Registers* to,
+const ArmISA::Affinity ,
+ArmISA::MiscRegIndex misc_reg)
+{
+auto val = from->readCpu(aff, misc_reg);
+DPRINTF(GIC,
+"copy cpu (aff3: %d, aff2: %d, aff1: %d, aff0: %d) "
+"%s 0x%08x\n",
+aff.aff3, aff.aff2, aff.aff1, aff.aff0,
+ArmISA::miscRegName[misc_reg], val);
+
+to->writeCpu(aff, misc_reg, val);
+}
+
+void
+Gicv3Registers::clearRedistRegister(Gicv3Registers* to,
+const ArmISA::Affinity , Addr
daddr)
+{
+to->writeRedistributor(aff, daddr, 0x);
+}
+
+void
+Gicv3Registers::copyRedistRange(Gicv3Registers* from,
+Gicv3Registers* to,
+const ArmISA::Affinity ,
+Addr daddr, size_t size)
+{
+for (auto a = daddr; a < daddr + size; a += 4)
+copyRedistRegister(from, to, aff, a);
+}
+
+void
+Gicv3Registers::copyDistRange(Gicv3Registers *from,
+ Gicv3Registers *to,
+ Addr daddr, size_t size)
+{
+for (auto a = daddr; a < daddr + size; a += 4)
+copyDistRegister(from, to, a);
+}
+
+void
+Gicv3Registers::clearDistRange(Gicv3Registers *to, Addr daddr, size_t size)
+{
+for (auto a = daddr; a < daddr + size; a += 4)
+to->writeDistributor(a, 0x);
+}
+
+
Gicv3::Gicv3(const Params )
: BaseGic(p)
{
@@ -240,11 +314,17 @@
return tc->getCpuPtr()->checkInterrupts(tc->threadId());
}
+Gicv3CPUInterface *
+Gicv3::getCPUInterfaceByAffinity(const ArmISA::Affinity ) const
+{
+return getRedistributorByAffinity(aff)->getCPUInterface();
+}
+
Gicv3Redistributor *
-Gicv3::getRedistributorByAffinity(uint32_t affinity) const
+Gicv3::getRedistributorByAffinity(const ArmISA::Affinity ) const
{
for (auto & redistributor : redistributors) {
-if (redistributor->getAffinity() == affinity) {
+if (redistributor->getAffinity() == aff) {
return redistributor;
}
}
@@ -268,6 +348,63 @@
return redistributors[redistributor_id];
}
+uint32_t
+Gicv3::readDistributor(Addr daddr)
+{
+return distributor->read(daddr, 4, false);
+}
+
+uint32_t
+Gicv3::readRedistributor(const ArmISA::Affinity , Addr daddr)
+{
+auto redistributor = getRedistributorByAffinity(aff);
+assert(redistributor);
+return redistributor->read(daddr, 4, false);
+}
+
+RegVal
+Gicv3::readCpu(const ArmISA::Affinity , ArmISA::MiscRegIndex misc_reg)
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Define an Affinity type
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/55705 )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Define an Affinity type
..
arch-arm: Define an Affinity type
Signed-off-by: Giacomo Travaglini
Change-Id: I42461de26886b1ba9e4db5b23a9fb970d3a1efd7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55705
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/arch/arm/types.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
3 files changed, 32 insertions(+), 7 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index a4d1f33..734fe6f 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2017-2018, 2022 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -202,6 +202,13 @@
Bitfield<11, 8> ltcoproc;
EndBitUnion(ExtMachInst)
+BitUnion32(Affinity)
+Bitfield<31, 24> aff3;
+Bitfield<23, 16> aff2;
+Bitfield<15, 8> aff1;
+Bitfield<7, 0> aff0;
+EndBitUnion(Affinity)
+
// Shift types for ARM instructions
enum ArmShiftType
{
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index f81255d..6852aed 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2009-2014, 2016-2020 ARM Limited
+ * Copyright (c) 2009-2014, 2016-2020, 2022 Arm Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -199,13 +199,13 @@
static RegVal
getAff2(ArmSystem *arm_sys, ThreadContext *tc)
{
-return arm_sys->multiThread ? tc->socketId() << 16 : 0;
+return arm_sys->multiThread ? tc->socketId() : 0;
}
static RegVal
getAff1(ArmSystem *arm_sys, ThreadContext *tc)
{
-return arm_sys->multiThread ? tc->cpuId() << 8 : tc->socketId() << 8;
+return arm_sys->multiThread ? tc->cpuId() : tc->socketId();
}
static RegVal
@@ -214,10 +214,14 @@
return arm_sys->multiThread ? tc->threadId() : tc->cpuId();
}
-RegVal
+Affinity
getAffinity(ArmSystem *arm_sys, ThreadContext *tc)
{
-return getAff2(arm_sys, tc) | getAff1(arm_sys, tc) | getAff0(arm_sys,
tc);
+Affinity aff = 0;
+aff.aff0 = getAff0(arm_sys, tc);
+aff.aff1 = getAff1(arm_sys, tc);
+aff.aff2 = getAff2(arm_sys, tc);
+return aff;
}
bool
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 0e5f3bb..00b0acf 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -223,7 +223,7 @@
RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
/** Retrieves MPIDR_EL1.{Aff2,Aff1,Aff0} affinity numbers */
-RegVal getAffinity(ArmSystem *arm_sys, ThreadContext *tc);
+Affinity getAffinity(ArmSystem *arm_sys, ThreadContext *tc);
static inline uint32_t
mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn,
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/55705
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I42461de26886b1ba9e4db5b23a9fb970d3a1efd7
Gerrit-Change-Number: 55705
Gerrit-PatchSet: 8
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Templatize MuxingKvmGic to support flexible hierarchy
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/55611 )
(
8 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Templatize MuxingKvmGic to support flexible
hierarchy
..
arch-arm: Templatize MuxingKvmGic to support flexible hierarchy
By templatizing the MuxingKvmGic we decouple it from the GicV2
class, unlocking non GICv2 (e.g. GICv3) KVM and guest implementations
Signed-off-by: Giacomo Travaglini
Change-Id: I26838903fa7c9f8b9de40678021329cb3390cc74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55611
Tested-by: kokoro
---
M src/arch/arm/kvm/KvmGic.py
M src/arch/arm/kvm/SConscript
M src/arch/arm/kvm/gic.cc
M src/arch/arm/kvm/gic.hh
M src/dev/arm/RealView.py
5 files changed, 104 insertions(+), 66 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/kvm/KvmGic.py b/src/arch/arm/kvm/KvmGic.py
index c435f44..166d261 100644
--- a/src/arch/arm/kvm/KvmGic.py
+++ b/src/arch/arm/kvm/KvmGic.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2015, 2017 ARM Limited
+# Copyright (c) 2015, 2017, 2021 Arm Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -38,10 +38,11 @@
from m5.objects.Gic import GicV2
-class MuxingKvmGic(GicV2):
-type = 'MuxingKvmGic'
+class MuxingKvmGicV2(GicV2):
+type = 'MuxingKvmGicV2'
cxx_header = "arch/arm/kvm/gic.hh"
-cxx_class = 'gem5::MuxingKvmGic'
+cxx_class = 'gem5::MuxingKvmGic'
+cxx_template_params = [ 'class Types' ]
simulate_gic = Param.Bool(False,
"Forcing the simulation to use the gem5 GIC instead of the host
GIC")
diff --git a/src/arch/arm/kvm/SConscript b/src/arch/arm/kvm/SConscript
index 44134a4..d06501f 100644
--- a/src/arch/arm/kvm/SConscript
+++ b/src/arch/arm/kvm/SConscript
@@ -43,7 +43,8 @@
if not (env['USE_KVM'] and env['KVM_ISA'] == 'arm'):
Return()
-SimObject('KvmGic.py', sim_objects=['MuxingKvmGic'], tags='arm isa')
+SimObject('KvmGic.py',
+sim_objects=['MuxingKvmGicV2'], tags='arm isa')
Source('gic.cc', tags='arm isa')
SimObject('BaseArmKvmCPU.py', sim_objects=['BaseArmKvmCPU'], tags='arm
isa')
diff --git a/src/arch/arm/kvm/gic.cc b/src/arch/arm/kvm/gic.cc
index 100f256..7d8ef75 100644
--- a/src/arch/arm/kvm/gic.cc
+++ b/src/arch/arm/kvm/gic.cc
@@ -42,7 +42,7 @@
#include "arch/arm/kvm/base_cpu.hh"
#include "debug/GIC.hh"
#include "debug/Interrupt.hh"
-#include "params/MuxingKvmGic.hh"
+#include "params/MuxingKvmGicV2.hh"
namespace gem5
{
@@ -101,16 +101,16 @@
vm.setIRQLine(line, high);
}
-KvmKernelGicV2::KvmKernelGicV2(KvmVM &_vm, Addr cpu_addr, Addr dist_addr,
- unsigned it_lines)
-: KvmKernelGic(_vm, KVM_DEV_TYPE_ARM_VGIC_V2, it_lines),
- cpuRange(RangeSize(cpu_addr, KVM_VGIC_V2_CPU_SIZE)),
- distRange(RangeSize(dist_addr, KVM_VGIC_V2_DIST_SIZE))
+KvmKernelGicV2::KvmKernelGicV2(KvmVM &_vm,
+ const MuxingKvmGicV2Params )
+: KvmKernelGic(_vm, KVM_DEV_TYPE_ARM_VGIC_V2, p.it_lines),
+ cpuRange(RangeSize(p.cpu_addr, KVM_VGIC_V2_CPU_SIZE)),
+ distRange(RangeSize(p.dist_addr, KVM_VGIC_V2_DIST_SIZE))
{
kdev.setAttr(
-KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_DIST, dist_addr);
+KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_DIST,
p.dist_addr);
kdev.setAttr(
-KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_CPU, cpu_addr);
+KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_CPU, p.cpu_addr);
}
uint32_t
@@ -169,27 +169,24 @@
setGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr, data);
}
-MuxingKvmGic::MuxingKvmGic(const MuxingKvmGicParams )
-: GicV2(p),
- system(*p.system),
- kernelGic(nullptr),
- usingKvm(false)
+template
+MuxingKvmGic::MuxingKvmGic(const Params )
+ : SimGic(p),
+system(*p.system),
+kernelGic(nullptr),
+usingKvm(false)
{
auto vm = system.getKvmVM();
if (vm && !p.simulate_gic) {
-kernelGic = new KvmKernelGicV2(*vm, p.cpu_addr, p.dist_addr,
- p.it_lines);
+kernelGic = new KvmGic(*vm, p);
}
}
-MuxingKvmGic::~MuxingKvmGic()
-{
-}
-
+template
void
-MuxingKvmGic::startup()
+MuxingKvmGic::startup()
{
-GicV2::startup();
+SimGic::startup();
KvmVM *vm = system.getKvmVM();
usingKvm = kernelGic && vm && vm->validEnvironment();
@@ -197,18 +194,20 @@
fromGicToKvm();
}
+template
DrainState
-MuxingKvmGic::drain()
+MuxingKvmGic::drain()
{
if (usingKvm)
fromKvmToGic();
-return GicV2::drain();
+return SimGic::drain();
}
+template
void
-MuxingKvmGic::drainResume()
+MuxingKvmGic::drainResume()
{
-
[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Remove generic BaseGicRegisters interface
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/55703 )
(
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm, dev-arm: Remove generic BaseGicRegisters
interface
..
arch-arm, dev-arm: Remove generic BaseGicRegisters interface
The GICv3 register interface is different from the GICv2 one: from
the presence of redistributor registers up to the system register
implementation of the cpu-interface
We therefore make the current BaseGicRegisters interface GICv2 specific.
We will define a different Gic3Registers interface for GICv3 state
transfer
Signed-off-by: Giacomo Travaglini
Change-Id: I42f15f48cab6e26aaf519e13c2ce70f661801117
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55703
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/arch/arm/kvm/gic.cc
M src/arch/arm/kvm/gic.hh
M src/dev/arm/base_gic.cc
M src/dev/arm/base_gic.hh
M src/dev/arm/gic_v2.cc
M src/dev/arm/gic_v2.hh
6 files changed, 119 insertions(+), 95 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/kvm/gic.cc b/src/arch/arm/kvm/gic.cc
index f6a57da..100f256 100644
--- a/src/arch/arm/kvm/gic.cc
+++ b/src/arch/arm/kvm/gic.cc
@@ -292,13 +292,15 @@
void
MuxingKvmGic::fromGicToKvm()
{
-copyGicState(static_cast(this), kernelGic);
+copyGicState(static_cast(this),
+ static_cast(kernelGic));
}
void
MuxingKvmGic::fromKvmToGic()
{
-copyGicState(kernelGic, static_cast(this));
+copyGicState(static_cast(kernelGic),
+ static_cast(this));
// the values read for the Interrupt Priority Mask Register (PMR)
// have been shifted by three bits due to its having been emulated by
diff --git a/src/arch/arm/kvm/gic.hh b/src/arch/arm/kvm/gic.hh
index 5201f58..af52079 100644
--- a/src/arch/arm/kvm/gic.hh
+++ b/src/arch/arm/kvm/gic.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, 2021 Arm Limited
+ * Copyright (c) 2015-2017, 2021-2022 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -54,7 +54,7 @@
* model. It exposes an API that is similar to that of
* software-emulated GIC models in gem5.
*/
-class KvmKernelGic : public BaseGicRegisters
+class KvmKernelGic
{
public:
/**
@@ -131,7 +131,7 @@
KvmDevice kdev;
};
-class KvmKernelGicV2 : public KvmKernelGic
+class KvmKernelGicV2 : public KvmKernelGic, public GicV2Registers
{
public:
/**
@@ -148,7 +148,7 @@
KvmKernelGicV2(KvmVM , Addr cpu_addr, Addr dist_addr,
unsigned it_lines);
- public: // BaseGicRegisters
+ public: // GicV2Registers
uint32_t readDistributor(ContextID ctx, Addr daddr) override;
uint32_t readCpu(ContextID ctx, Addr daddr) override;
diff --git a/src/dev/arm/base_gic.cc b/src/dev/arm/base_gic.cc
index c738c71..5694c37 100644
--- a/src/dev/arm/base_gic.cc
+++ b/src/dev/arm/base_gic.cc
@@ -80,61 +80,6 @@
return dynamic_cast(_params);
}
-void
-BaseGicRegisters::copyDistRegister(BaseGicRegisters* from,
- BaseGicRegisters* to,
- ContextID ctx, Addr daddr)
-{
-auto val = from->readDistributor(ctx, daddr);
-DPRINTF(GIC, "copy dist 0x%x 0x%08x\n", daddr, val);
-to->writeDistributor(ctx, daddr, val);
-}
-
-void
-BaseGicRegisters::copyCpuRegister(BaseGicRegisters* from,
- BaseGicRegisters* to,
- ContextID ctx, Addr daddr)
-{
-auto val = from->readCpu(ctx, daddr);
-DPRINTF(GIC, "copy cpu 0x%x 0x%08x\n", daddr, val);
-to->writeCpu(ctx, daddr, val);
-}
-
-void
-BaseGicRegisters::copyBankedDistRange(System *sys, BaseGicRegisters* from,
- BaseGicRegisters* to,
- Addr daddr, size_t size)
-{
-for (int ctx = 0; ctx < sys->threads.size(); ++ctx)
-for (auto a = daddr; a < daddr + size; a += 4)
-copyDistRegister(from, to, ctx, a);
-}
-
-void
-BaseGicRegisters::clearBankedDistRange(System *sys, BaseGicRegisters* to,
- Addr daddr, size_t size)
-{
-for (int ctx = 0; ctx < sys->threads.size(); ++ctx)
-for (auto a = daddr; a < daddr + size; a += 4)
-to->writeDistributor(ctx, a, 0x);
-}
-
-void
-BaseGicRegisters::copyDistRange(BaseGicRegisters* from,
-BaseGicRegisters* to,
-Addr daddr, size_t size)
-{
-for (auto a = daddr; a < daddr + size; a += 4)
-copyDistRegister(from, to, 0, a);
-}
-
-void
-BaseGicRegisters::clearDistRange(BaseGicRegisters* to,
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix gem5 build on aarch64 host
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/56346 )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Fix gem5 build on aarch64 host
..
arch-arm: Fix gem5 build on aarch64 host
vm is not a member variable of MuxingKvmGic. This was broken
by:
https://gem5-review.googlesource.com/c/public/gem5/+/56263
Signed-off-by: Giacomo Travaglini
Change-Id: Iee8a3424eb28cfe2bc20df088dc0af05e9e8a7de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56346
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/arch/arm/kvm/gic.cc
1 file changed, 23 insertions(+), 0 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/kvm/gic.cc b/src/arch/arm/kvm/gic.cc
index fd3eef7..f6a57da 100644
--- a/src/arch/arm/kvm/gic.cc
+++ b/src/arch/arm/kvm/gic.cc
@@ -190,6 +190,8 @@
MuxingKvmGic::startup()
{
GicV2::startup();
+
+KvmVM *vm = system.getKvmVM();
usingKvm = kernelGic && vm && vm->validEnvironment();
if (usingKvm)
fromGicToKvm();
@@ -207,6 +209,8 @@
MuxingKvmGic::drainResume()
{
GicV2::drainResume();
+
+KvmVM *vm = system.getKvmVM();
bool use_kvm = kernelGic && vm && vm->validEnvironment();
if (use_kvm != usingKvm) {
// Should only occur due to CPU switches
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/56346
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iee8a3424eb28cfe2bc20df088dc0af05e9e8a7de
Gerrit-Change-Number: 56346
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Use ArmISA::getAffinity in GICv3 redistributor
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/55704 )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: dev-arm: Use ArmISA::getAffinity in GICv3 redistributor
..
dev-arm: Use ArmISA::getAffinity in GICv3 redistributor
The GICv3 redistributor was reading the MPIDR value and manually
extracting the affinity numbers from it. This is not necessary as there
is already a getAffinity helper function
Signed-off-by: Giacomo Travaglini
Change-Id: I6ef150937b51bb065575ed2f432f4f5f0bc38b07
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55704
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/dev/arm/gic_v3_redistributor.cc
1 file changed, 19 insertions(+), 11 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/gic_v3_redistributor.cc
b/src/dev/arm/gic_v3_redistributor.cc
index 225e4cd..adfc5bc 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -1017,17 +1017,7 @@
Gicv3Redistributor::getAffinity() const
{
ThreadContext *tc = gic->getSystem()->threads[cpuId];
-uint64_t mpidr = getMPIDR(gic->getSystem(), tc);
-/*
- * Aff3 = MPIDR[39:32]
- * (Note getMPIDR() returns uint32_t so Aff3 is always 0...)
- * Aff2 = MPIDR[23:16]
- * Aff1 = MPIDR[15:8]
- * Aff0 = MPIDR[7:0]
- * affinity = Aff3.Aff2.Aff1.Aff0
- */
-uint64_t affinity = ((mpidr & 0xff) >> 8) | (mpidr &
(0xff));
-return affinity;
+return gem5::ArmISA::getAffinity(gic->getSystem(), tc);
}
bool
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6ef150937b51bb065575ed2f432f4f5f0bc38b07
Gerrit-Change-Number: 55704
Gerrit-PatchSet: 9
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Kokoro failures
Hi all, I am seeing a lot of failures on kokoro due to timeouts. Have we recently added some extra tests to the quick/pre-submit regressions? Kind Regards Giacomo IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: python: Remove the m5.config and options.py mechanism.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56387 )
Change subject: python: Remove the m5.config and options.py mechanism.
..
python: Remove the m5.config and options.py mechanism.
It appears that there is a mechanism where you could either have a .m5
directory in your home directory, or set an M5_CONFIG environment
variable to some other directory, where you could put an options.py
file. That file would then be passed the options dict which gem5's main
had extracted from its args, which it could modify as it liked.
First, I suspect that this mechanism was basically unknown and was just
a dark corner of gem5 people had forgotten about. Getting rid of it
will help clear out old cruft.
Second, this sort of file reaching in and fiddling with gem5's internal
data structures is dangerous and fragile, and could in almost any case
be replaced with a wrapper script or shell alias.
Change-Id: Ic828716979ea6379f60de796d23281ab075b38ec
---
D src/python/m5/config.py
M src/python/m5/main.py
2 files changed, 23 insertions(+), 56 deletions(-)
diff --git a/src/python/m5/config.py b/src/python/m5/config.py
deleted file mode 100644
index 926ea14..000
--- a/src/python/m5/config.py
+++ /dev/null
@@ -1,48 +0,0 @@
-# Copyright (c) 2008 The Hewlett-Packard Development Company
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-import os
-from os.path import isdir, isfile, join as joinpath
-
-
-confdir = os.environ.get('M5_CONFIG')
-
-if not confdir:
-# HOME is not set when running regressions, due to use of scons
-# Execute() function.
-homedir = os.environ.get('HOME')
-if homedir and isdir(joinpath(homedir, '.m5')):
-confdir = joinpath(homedir, '.m5')
-
-def get(name):
-if not confdir:
-return None
-conffile = joinpath(confdir, name)
-if not isfile(conffile):
-return None
-
-return conffile
-
diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index f649e77..701d9f6 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -61,7 +61,6 @@
def parse_options():
-from . import config
from .options import OptionParser
options = OptionParser(usage=usage, description=brief_copyright)
@@ -155,13 +154,6 @@
option("--list-sim-objects", action='store_true', default=False,
help="List all built-in SimObjects, their params and default
values")
-# load the options.py config file to allow people to set their own
-# default options
-options_file = config.get('options.py')
-if options_file:
-scope = { 'options' : options }
-exec(compile(open(options_file).read(), options_file, 'exec'),
scope)
-
arguments = options.parse_args()
return options,arguments
--
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Gerrit-Change-Id: Ic828716979ea6379f60de796d23281ab075b38ec
Gerrit-Change-Number: 56387
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: util: Rename util/vi to util/vim.
Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56406 ) Change subject: util: Rename util/vi to util/vim. .. util: Rename util/vi to util/vim. Both files there, vimrc and ucode.vim, are for vim specifically, and not old school vi. Calling it vi is misleading and may prevent people from discovering what's there. Change-Id: I8da2e10b0df83ce705a8d9e7c62e33374e740506 --- R util/vim/ucode.vim R util/vim/vimrc 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/util/vi/ucode.vim b/util/vim/ucode.vim similarity index 100% rename from util/vi/ucode.vim rename to util/vim/ucode.vim diff --git a/util/vi/vimrc b/util/vim/vimrc similarity index 100% rename from util/vi/vimrc rename to util/vim/vimrc -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/56406 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I8da2e10b0df83ce705a8d9e7c62e33374e740506 Gerrit-Change-Number: 56406 Gerrit-PatchSet: 1 Gerrit-Owner: Gabe Black Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: scons: Make CC, CXX and PROTOC no longer sticky.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56386 )
Change subject: scons: Make CC, CXX and PROTOC no longer sticky.
..
scons: Make CC, CXX and PROTOC no longer sticky.
These variables will always be imported from the environment, and never
from previous builds. For SCons to actually use these values, they need
to not only be in the environment variables external commands SCons runs
sees, they also have to be promoted to actual SCons construction
variables.
Change-Id: I54035442d70972396f1788bd0773877222d7a7c5
---
M SConstruct
M site_scons/gem5_scons/defaults.py
M src/SConscript
3 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/SConstruct b/SConstruct
index d7cd564..6cdffe5 100755
--- a/SConstruct
+++ b/SConstruct
@@ -253,8 +253,6 @@
global_vars = Variables(global_vars_file, args=ARGUMENTS)
global_vars.AddVariables(
-('CC', 'C compiler', environ.get('CC', main['CC'])),
-('CXX', 'C++ compiler', environ.get('CXX', main['CXX'])),
('CCFLAGS_EXTRA', 'Extra C and C++ compiler flags', ''),
('GEM5PY_CCFLAGS_EXTRA', 'Extra C and C++ gem5py compiler flags', ''),
('GEM5PY_LINKFLAGS_EXTRA', 'Extra marshal gem5py flags', ''),
@@ -262,7 +260,6 @@
('PYTHON_CONFIG', 'Python config binary to use',
[ 'python3-config', 'python-config']
),
-('PROTOC', 'protoc tool', environ.get('PROTOC', 'protoc')),
('BATCH', 'Use batch pool for build and tests', False),
('BATCH_CMD', 'Batch pool submission command name', 'qdo'),
('M5_BUILD_CACHE', 'Cache built objects in this directory', False),
diff --git a/site_scons/gem5_scons/defaults.py
b/site_scons/gem5_scons/defaults.py
index 1f8d5d5..4efaa26 100644
--- a/site_scons/gem5_scons/defaults.py
+++ b/site_scons/gem5_scons/defaults.py
@@ -63,6 +63,16 @@
any([key.startswith(prefix) for prefix in use_prefixes]):
env['ENV'][key] = val
+# These variables from the environment override/become SCons variables,
+# with a default if they weren't in the host environment.
+var_overrides = {
+'CC': env['CC'],
+'CXX': env['CXX'],
+'PROTOC': 'protoc'
+}
+for key,default in var_overrides.items():
+env[key] = env['ENV'].get(key, default)
+
# Tell scons to avoid implicit command dependencies to avoid issues
# with the param wrappes being compiled twice (see
# https://github.com/SCons/scons/issues/2811
diff --git a/src/SConscript b/src/SConscript
index 6c8ccaf..75d15bd 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -239,6 +239,7 @@
root, ext = os.path.splitext(source[0].get_abspath())
return [root + '.pb.cc', root + '.pb.h'], source
+env.SetDefault(PROTOC='protoc')
protoc_action = MakeAction('${PROTOC} --cpp_out ${BUILDDIR} '
'--proto_path ${BUILDDIR} --proto_path ${SOURCE.dir} '
'${SOURCE.get_abspath()}',
--
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Gerrit-Change-Id: I54035442d70972396f1788bd0773877222d7a7c5
Gerrit-Change-Number: 56386
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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