[gem5-dev] [S] Change in gem5/gem5[develop]: cpu-o3: Resolve the skid buffer overflow issue at decode stage
Hanhwi Jang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67231?usp=email )
Change subject: cpu-o3: Resolve the skid buffer overflow issue at decode
stage
..
cpu-o3: Resolve the skid buffer overflow issue at decode stage
When decode width is larger than fetch width, the skid buffer
overflow happens at decode stage. The decode stage assumes
that fetch stage sends instructions as many as the fetch width,
but it sends them at decode width rate.
This patch makes the decode stage set its skid buffer size
according to the decode width.
Change-Id: I90ee43d16c59a4c9305c77bbfad7e4cdb2b9cffa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67231
Maintainer: Jason Lowe-Power
Reviewed-by: Jason Lowe-Power
Reviewed-by: Hanhwi Jang
Reviewed-by: Tom Rollet
Tested-by: kokoro
---
M src/cpu/o3/decode.cc
1 file changed, 24 insertions(+), 1 deletion(-)
Approvals:
Tom Rollet: Looks good to me, but someone else must approve
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
kokoro: Regressions pass
Hanhwi Jang: Looks good to me, approved
diff --git a/src/cpu/o3/decode.cc b/src/cpu/o3/decode.cc
index 9555e32..ac728a2 100644
--- a/src/cpu/o3/decode.cc
+++ b/src/cpu/o3/decode.cc
@@ -77,7 +77,7 @@
decodeWidth, static_cast(MaxWidth));
// @todo: Make into a parameter
-skidBufferMax = (fetchToDecodeDelay + 1) * params.fetchWidth;
+skidBufferMax = (fetchToDecodeDelay + 1) * params.decodeWidth;
for (int tid = 0; tid < MaxThreads; tid++) {
stalls[tid] = {false};
decodeStatus[tid] = Idle;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I90ee43d16c59a4c9305c77bbfad7e4cdb2b9cffa
Gerrit-Change-Number: 67231
Gerrit-PatchSet: 2
Gerrit-Owner: Hanhwi Jang
Gerrit-Reviewer: Hanhwi Jang
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tom Rollet
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: gpu-compute, mem-ruby: Add p_popRequestQueue to some transitions
VISHNU RAMADAS has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67192?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: gpu-compute, mem-ruby: Add p_popRequestQueue to some
transitions
..
gpu-compute, mem-ruby: Add p_popRequestQueue to some transitions
Two W->WI transitions, on events RdBlk and Atomic in the GPU L2 cache
coherence protocol do not clear the request from the request queue upon
completing the transition. This action is not performed in the respone
path. This update adds the p_popRequestQueue action to each of these
transitions to remove the stale request from the queue.
Change-Id: Ia2679fe3dd702f4df2bc114f4607ba40c18d6ff1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67192
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/GPU_VIPER-TCC.sm
1 file changed, 21 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
index ca4c543..0f93339 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
@@ -721,6 +721,7 @@
p_profileHit;
t_allocateTBE;
wb_writeBack;
+p_popRequestQueue;
}
transition(I, RdBlk, IV) {TagArrayRead} {
@@ -815,6 +816,7 @@
p_profileHit;
t_allocateTBE;
wb_writeBack;
+p_popRequestQueue;
}
transition(I, WrVicBlk) {TagArrayRead} {
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia2679fe3dd702f4df2bc114f4607ba40c18d6ff1
Gerrit-Change-Number: 67192
Gerrit-PatchSet: 3
Gerrit-Owner: VISHNU RAMADAS
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: VISHNU RAMADAS
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: gpu-compute, mem-ruby: Update GPU cache bypassing to use TBE
VISHNU RAMADAS has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67191?usp=email )
(
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: gpu-compute, mem-ruby: Update GPU cache bypassing to use
TBE
..
gpu-compute, mem-ruby: Update GPU cache bypassing to use TBE
An earlier commit added support for GLC and SLC AMDGPU instruction
modifiers. These modifiers enable cache bypassing when set. The GLC/SLC
flag information was being threaded through all the way to memory and
back so that appropriate actions could be taken upon receiving a request
and corresponding response. This commit removes the threading and adds
the bypass flag information to TBE. Requests populate this
entry and responses access it to determine the correct set of actions to
execute.
Change-Id: I20ffa6682d109270adb921de078cfd47fb4e137c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67191
Maintainer: Matt Sinclair
Tested-by: kokoro
Reviewed-by: Matt Sinclair
Reviewed-by: Jason Lowe-Power
---
M src/mem/ruby/protocol/GPU_VIPER-TCC.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
3 files changed, 48 insertions(+), 66 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, but someone else must approve; Looks
good to me, approved
kokoro: Regressions pass
Jason Lowe-Power: Looks good to me, approved
diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
index ae14247..ca4c543 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
@@ -283,7 +283,13 @@
peek(responseFromNB_in, ResponseMsg, block_on="addr") {
TBE tbe := TBEs.lookup(in_msg.addr);
Entry cache_entry := getCacheEntry(in_msg.addr);
-if (in_msg.isSLCSet) {
+bool is_slc_set := false;
+
+if (!is_invalid(tbe)) {
+is_slc_set := tbe.isSLCSet;
+}
+
+if (is_slc_set) {
// If the SLC bit is set, the response needs to bypass the
cache
// and should not be allocated an entry.
trigger(Event:Bypass, in_msg.addr, cache_entry, tbe);
@@ -343,6 +349,10 @@
trigger(Event:WrVicBlk, in_msg.addr, cache_entry, tbe);
}
} else if (in_msg.Type == CoherenceRequestType:Atomic) {
+ // Currently the Atomic requests do not have GLC/SLC bit handing
+ // support. The assert ensures that the requests do not have
+ // these set, and therefore do not expect to bypass the cache
+ assert(!in_msg.isSLCSet);
trigger(Event:Atomic, in_msg.addr, cache_entry, tbe);
} else if (in_msg.Type == CoherenceRequestType:RdBlk) {
if (in_msg.isSLCSet) {
@@ -399,8 +409,8 @@
out_msg.State := CoherenceState:Shared;
DPRINTF(RubySlicc, "%s\n", out_msg);
peek(responseFromNB_in, ResponseMsg) {
-out_msg.isGLCSet := in_msg.isGLCSet;
-out_msg.isSLCSet := in_msg.isSLCSet;
+out_msg.isGLCSet := tbe.isGLCSet;
+out_msg.isSLCSet := tbe.isSLCSet;
}
}
enqueue(unblockToNB_out, UnblockMsg, 1) {
@@ -408,8 +418,8 @@
out_msg.Destination.add(mapAddressToMachine(address,
MachineType:Directory));
out_msg.MessageSize := MessageSizeType:Unblock_Control;
peek(responseFromNB_in, ResponseMsg) {
-out_msg.isGLCSet := in_msg.isGLCSet;
-out_msg.isSLCSet := in_msg.isSLCSet;
+out_msg.isGLCSet := tbe.isGLCSet;
+out_msg.isSLCSet := tbe.isSLCSet;
}
DPRINTF(RubySlicc, "%s\n", out_msg);
}
@@ -426,8 +436,8 @@
out_msg.MessageSize := MessageSizeType:Response_Data;
out_msg.Dirty := false;
out_msg.State := CoherenceState:Shared;
- out_msg.isGLCSet := in_msg.isGLCSet;
- out_msg.isSLCSet := in_msg.isSLCSet;
+ out_msg.isGLCSet := tbe.isGLCSet;
+ out_msg.isSLCSet := tbe.isSLCSet;
DPRINTF(RubySlicc, "%s\n", out_msg);
}
enqueue(unblockToNB_out, UnblockMsg, 1) {
@@ -449,8 +459,8 @@
out_msg.Destination.add(mapAddressToMachine(address,
MachineType:Directory));
out_msg.Shared := false; // unneeded for this request
out_msg.MessageSize := in_msg.MessageSize;
- out_msg.isGLCSet := in_msg.isGLCSet;
- out_msg.isSLCSet := in_msg.isSLCSet;
+ out_msg.isGLCSet := tbe.isGLCSet;
+ out_msg.isSLCSet := tbe.isSLCSet;
DPRINTF(RubySlicc, "%s\n", out_msg);
}
}
@@ -467,9 +477,6 @@
out_msg.Sender := machineID;
out_msg.MessageSize := MessageSizeType:Writeback_Control;
out_msg.instSeqNum := in_msg.instSeqNum;
-out_msg.isGLCSet := in_msg.isGLCSet;
-out_msg.isSLCSet
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Read one dword for SGPR base global insts
Matthew Poremba has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/67077?usp=email ) Change subject: arch-vega: Read one dword for SGPR base global insts .. arch-vega: Read one dword for SGPR base global insts Global instructions in Vega can either use a VGPR base address plus instruction offset or SGPR base address plus VGPR offset plus instruction offset. Currently the VGPR address/offset is always read as two dwords. This causes problems if the VGPR number is the last VGPR allocated to a wavefront since the second dword would be beyond the allocation and trip an assert. This changeset sets the operand size of the VGPR operand to one dword when SGPR base is used and two dwords otherwise so initDynOperandInfo does not assert. It also moves the read of the VGPR into the calcAddr method so that the correct ConstVecOperandU## is used to prevent another assertion failure when reading from the register file. These two changes are made to all flat instructions, as global instructions are a subsegement of flat instructions. Change-Id: I79030771aa6deec05ffa5853ca2d8b68943ee0a0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67077 Reviewed-by: Matt Sinclair Maintainer: Matt Sinclair Tested-by: kokoro --- M src/arch/amdgpu/vega/insts/instructions.cc M src/arch/amdgpu/vega/insts/instructions.hh M src/arch/amdgpu/vega/insts/op_encodings.hh 3 files changed, 101 insertions(+), 107 deletions(-) Approvals: Matt Sinclair: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/amdgpu/vega/insts/instructions.cc b/src/arch/amdgpu/vega/insts/instructions.cc index c803656..4b27afa 100644 --- a/src/arch/amdgpu/vega/insts/instructions.cc +++ b/src/arch/amdgpu/vega/insts/instructions.cc @@ -43831,11 +43831,7 @@ gpuDynInst->latency.init(gpuDynInst->computeUnit()); gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod()); -ConstVecOperandU64 addr(gpuDynInst, extData.ADDR); - -addr.read(); - -calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET); +calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET); issueRequestHelper(gpuDynInst); } // execute @@ -43919,11 +43915,7 @@ gpuDynInst->latency.init(gpuDynInst->computeUnit()); gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod()); -ConstVecOperandU64 addr(gpuDynInst, extData.ADDR); - -addr.read(); - -calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET); +calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET); issueRequestHelper(gpuDynInst); } // execute @@ -44008,11 +44000,7 @@ gpuDynInst->latency.init(gpuDynInst->computeUnit()); gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod()); -ConstVecOperandU64 addr(gpuDynInst, extData.ADDR); - -addr.read(); - -calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET); +calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET); issueRequestHelper(gpuDynInst); } // execute @@ -44067,11 +44055,7 @@ gpuDynInst->latency.init(gpuDynInst->computeUnit()); gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod()); -ConstVecOperandU64 addr(gpuDynInst, extData.ADDR); - -addr.read(); - -calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET); +calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET); issueRequestHelper(gpuDynInst); } // execute @@ -44126,11 +44110,7 @@ gpuDynInst->latency.init(gpuDynInst->computeUnit()); gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod()); -ConstVecOperandU64 addr(gpuDynInst, extData.ADDR); - -addr.read(); - -calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET); +calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET); issueRequestHelper(gpuDynInst); } // execute @@ -44194,11 +44174,7 @@ gpuDynInst->latency.init(gpuDynInst->computeUnit()); gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod()); -ConstVecOperandU64 addr(gpuDynInst, extData.ADDR); - -addr.read(); - -calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET); +calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET); issueRequestHelper(gpuDynInst); } // execute @@ -44266,13 +44242,11 @@ gpuDynInst->latency.init(gpuDynInst->computeUnit()); gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod()); -ConstVecOperandU64 addr(gpuDynInst, extData.ADDR); ConstVecOperandU8 data(gpuDynInst, extData.DATA); -addr.read(); data.read(); -calcAddr(gpuDynInst, addr, extData.SADDR,
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Implement ds_write2st64_b64
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67078?usp=email )
Change subject: arch-vega: Implement ds_write2st64_b64
..
arch-vega: Implement ds_write2st64_b64
Write two qwords at offsets multiplied by 8 * 64 bytes.
Change-Id: I0d0e05f3e848c2fd02d32095e32b7f023bd8803b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67078
Reviewed-by: Matt Sinclair
Tested-by: kokoro
Maintainer: Matt Sinclair
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
2 files changed, 62 insertions(+), 1 deletion(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index 4b27afa..6cf01fb 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -36595,8 +36595,52 @@
void
Inst_DS__DS_WRITE2ST64_B64::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (gpuDynInst->exec_mask.none()) {
+wf->decLGKMInstsIssued();
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(
+gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ConstVecOperandU64 data0(gpuDynInst, extData.DATA0);
+ConstVecOperandU64 data1(gpuDynInst, extData.DATA1);
+
+addr.read();
+data0.read();
+data1.read();
+
+calcAddr(gpuDynInst, addr);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+(reinterpret_cast(
+gpuDynInst->d_data))[lane * 2] = data0[lane];
+(reinterpret_cast(
+gpuDynInst->d_data))[lane * 2 + 1] = data1[lane];
+}
+}
+
+
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
} // execute
+
+void
+Inst_DS__DS_WRITE2ST64_B64::initiateAcc(GPUDynInstPtr gpuDynInst)
+{
+Addr offset0 = instData.OFFSET0 * 8 * 64;
+Addr offset1 = instData.OFFSET1 * 8 * 64;
+
+initDualMemWrite(gpuDynInst, offset0, offset1);
+}
+
+void
+Inst_DS__DS_WRITE2ST64_B64::completeAcc(GPUDynInstPtr gpuDynInst)
+{
+}
// --- Inst_DS__DS_CMPST_B64 class methods ---
Inst_DS__DS_CMPST_B64::Inst_DS__DS_CMPST_B64(InFmt_DS *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index 9f017f9..2896732 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -33572,6 +33572,8 @@
} // getOperandSize
void execute(GPUDynInstPtr) override;
+void initiateAcc(GPUDynInstPtr) override;
+void completeAcc(GPUDynInstPtr) override;
}; // Inst_DS__DS_WRITE2ST64_B64
class Inst_DS__DS_CMPST_B64 : public Inst_DS
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0d0e05f3e848c2fd02d32095e32b7f023bd8803b
Gerrit-Change-Number: 67078
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Implement ds_read_i8
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67076?usp=email )
Change subject: arch-vega: Implement ds_read_i8
..
arch-vega: Implement ds_read_i8
Read one byte with sign extended from LDS.
Change-Id: I9cb9b4033c6f834241cba944bc7e6a7ebc5401be
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67076
Maintainer: Matt Sinclair
Tested-by: kokoro
Reviewed-by: Matt Sinclair
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
2 files changed, 60 insertions(+), 1 deletion(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index a54f426..c803656 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -35636,8 +35636,50 @@
void
Inst_DS__DS_READ_I8::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (gpuDynInst->exec_mask.none()) {
+wf->decLGKMInstsIssued();
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(
+gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+
+addr.read();
+
+calcAddr(gpuDynInst, addr);
+
+
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
} // execute
+
+void
+Inst_DS__DS_READ_I8::initiateAcc(GPUDynInstPtr gpuDynInst)
+{
+Addr offset0 = instData.OFFSET0;
+Addr offset1 = instData.OFFSET1;
+Addr offset = (offset1 << 8) | offset0;
+
+initMemRead(gpuDynInst, offset);
+} // initiateAcc
+
+void
+Inst_DS__DS_READ_I8::completeAcc(GPUDynInstPtr gpuDynInst)
+{
+VecOperandU32 vdst(gpuDynInst, extData.VDST);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+vdst[lane] =
(VecElemU32)sext<8>((reinterpret_cast(
+gpuDynInst->d_data))[lane]);
+}
+}
+
+vdst.write();
+} // completeAcc
// --- Inst_DS__DS_READ_U8 class methods ---
Inst_DS__DS_READ_U8::Inst_DS__DS_READ_U8(InFmt_DS *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index f8fc98b..b2cf2b9 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -32848,6 +32848,8 @@
} // getOperandSize
void execute(GPUDynInstPtr) override;
+void initiateAcc(GPUDynInstPtr) override;
+void completeAcc(GPUDynInstPtr) override;
}; // Inst_DS__DS_READ_I8
class Inst_DS__DS_READ_U8 : public Inst_DS
--
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Gerrit-Project: public/gem5
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Gerrit-Change-Id: I9cb9b4033c6f834241cba944bc7e6a7ebc5401be
Gerrit-Change-Number: 67076
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Implement ds_add_u64
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67075?usp=email )
Change subject: arch-vega: Implement ds_add_u64
..
arch-vega: Implement ds_add_u64
This instruction does an atomic add of an unsigned 64-bit data with a
VGPR and value in LDS atomically without return.
Change-Id: I6a7d6713b256607c4e69ddbdef5c83172493c077
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67075
Reviewed-by: Matt Sinclair
Maintainer: Matt Sinclair
Tested-by: kokoro
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
2 files changed, 64 insertions(+), 3 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index 3d9808a..a54f426 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -36088,6 +36088,10 @@
Inst_DS__DS_ADD_U64::Inst_DS__DS_ADD_U64(InFmt_DS *iFmt)
: Inst_DS(iFmt, "ds_add_u64")
{
+setFlag(MemoryRef);
+setFlag(GroupSegment);
+setFlag(AtomicAdd);
+setFlag(AtomicNoReturn);
} // Inst_DS__DS_ADD_U64
Inst_DS__DS_ADD_U64::~Inst_DS__DS_ADD_U64()
@@ -36096,14 +36100,53 @@
// --- description from .arch file ---
// 64b:
-// tmp = MEM[ADDR];
// MEM[ADDR] += DATA[0:1];
-// RETURN_DATA[0:1] = tmp.
void
Inst_DS__DS_ADD_U64::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (gpuDynInst->exec_mask.none()) {
+wf->decLGKMInstsIssued();
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(
+gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ConstVecOperandU64 data(gpuDynInst, extData.DATA0);
+
+addr.read();
+data.read();
+
+calcAddr(gpuDynInst, addr);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+(reinterpret_cast(gpuDynInst->a_data))[lane]
+= data[lane];
+}
+}
+
+
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
} // execute
+
+void
+Inst_DS__DS_ADD_U64::initiateAcc(GPUDynInstPtr gpuDynInst)
+{
+Addr offset0 = instData.OFFSET0;
+Addr offset1 = instData.OFFSET1;
+Addr offset = (offset1 << 8) | offset0;
+
+initAtomicAccess(gpuDynInst, offset);
+} // initiateAcc
+
+void
+Inst_DS__DS_ADD_U64::completeAcc(GPUDynInstPtr gpuDynInst)
+{
+} // completeAcc
// --- Inst_DS__DS_SUB_U64 class methods ---
Inst_DS__DS_SUB_U64::Inst_DS__DS_SUB_U64(InFmt_DS *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index 05a0002..f8fc98b 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -33079,6 +33079,8 @@
}
} // getOperandSize
+void initiateAcc(GPUDynInstPtr gpuDynInst) override;
+void completeAcc(GPUDynInstPtr gpuDynInst) override;
void execute(GPUDynInstPtr) override;
}; // Inst_DS__DS_ADD_U64
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6a7d6713b256607c4e69ddbdef5c83172493c077
Gerrit-Change-Number: 67075
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: base: Specialize bitwise atomics so FP types can be used
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67073?usp=email )
Change subject: base: Specialize bitwise atomics so FP types can be used
..
base: Specialize bitwise atomics so FP types can be used
The current atomic memory operations are templated so any type can be
used. However floating point types can not perform bitwise operations.
The GPU model contains some instructions which do atomics on floating
point types, so they need to be supported. To allow this, template
specialization is added to atomic AND, OR, and XOR which does nothing
if the type is floating point and operates as normal for integral
types.
Change-Id: I60f935756355462e99c59a9da032c5bf5afa246c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67073
Reviewed-by: Matt Sinclair
Reviewed-by: Daniel Carvalho
Tested-by: kokoro
Maintainer: Matt Sinclair
---
M src/base/amo.hh
1 file changed, 52 insertions(+), 3 deletions(-)
Approvals:
kokoro: Regressions pass
Daniel Carvalho: Looks good to me, approved
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
diff --git a/src/base/amo.hh b/src/base/amo.hh
index 81bf069..c990d15 100644
--- a/src/base/amo.hh
+++ b/src/base/amo.hh
@@ -129,30 +129,57 @@
template
class AtomicOpAnd : public TypedAtomicOpFunctor
{
+// Bitwise operations are only legal on integral types
+template
+typename std::enable_if::value, void>::type
+executeImpl(B *b) { *b &= a; }
+
+template
+typename std::enable_if::value, void>::type
+executeImpl(B *b) { }
+
public:
T a;
AtomicOpAnd(T _a) : a(_a) { }
-void execute(T *b) { *b &= a; }
+void execute(T *b) { executeImpl(b); }
AtomicOpFunctor* clone () { return new AtomicOpAnd(a); }
};
template
class AtomicOpOr : public TypedAtomicOpFunctor
{
+// Bitwise operations are only legal on integral types
+template
+typename std::enable_if::value, void>::type
+executeImpl(B *b) { *b |= a; }
+
+template
+typename std::enable_if::value, void>::type
+executeImpl(B *b) { }
+
public:
T a;
AtomicOpOr(T _a) : a(_a) { }
-void execute(T *b) { *b |= a; }
+void execute(T *b) { executeImpl(b); }
AtomicOpFunctor* clone () { return new AtomicOpOr(a); }
};
template
class AtomicOpXor : public TypedAtomicOpFunctor
{
+// Bitwise operations are only legal on integral types
+template
+typename std::enable_if::value, void>::type
+executeImpl(B *b) { *b ^= a; }
+
+template
+typename std::enable_if::value, void>::type
+executeImpl(B *b) { }
+
public:
T a;
AtomicOpXor(T _a) : a(_a) {}
-void execute(T *b) { *b ^= a; }
+void execute(T *b) { executeImpl(b); }
AtomicOpFunctor* clone () { return new AtomicOpXor(a); }
};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I60f935756355462e99c59a9da032c5bf5afa246c
Gerrit-Change-Number: 67073
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Implement ds_add_f32 atomic
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67074?usp=email )
Change subject: arch-vega: Implement ds_add_f32 atomic
..
arch-vega: Implement ds_add_f32 atomic
This instruction does an atomic add of a 32-bit float with a VGPR and
value in LDS atomically without return.
Change-Id: Id4f23a1ab587a23edfd1d88ede1cbcc5bdedc0cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67074
Maintainer: Matt Sinclair
Reviewed-by: Matt Sinclair
Tested-by: kokoro
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
2 files changed, 64 insertions(+), 3 deletions(-)
Approvals:
kokoro: Regressions pass
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index afdfde3..3d9808a 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -34755,6 +34755,10 @@
: Inst_DS(iFmt, "ds_add_f32")
{
setFlag(F32);
+setFlag(MemoryRef);
+setFlag(GroupSegment);
+setFlag(AtomicAdd);
+setFlag(AtomicNoReturn);
} // Inst_DS__DS_ADD_F32
Inst_DS__DS_ADD_F32::~Inst_DS__DS_ADD_F32()
@@ -34763,15 +34767,54 @@
// --- description from .arch file ---
// 32b:
-// tmp = MEM[ADDR];
// MEM[ADDR] += DATA;
-// RETURN_DATA = tmp.
// Floating point add that handles NaN/INF/denormal values.
void
Inst_DS__DS_ADD_F32::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (gpuDynInst->exec_mask.none()) {
+wf->decLGKMInstsIssued();
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(
+gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ConstVecOperandF32 data(gpuDynInst, extData.DATA0);
+
+addr.read();
+data.read();
+
+calcAddr(gpuDynInst, addr);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+(reinterpret_cast(gpuDynInst->a_data))[lane]
+= data[lane];
+}
+}
+
+
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
} // execute
+
+void
+Inst_DS__DS_ADD_F32::initiateAcc(GPUDynInstPtr gpuDynInst)
+{
+Addr offset0 = instData.OFFSET0;
+Addr offset1 = instData.OFFSET1;
+Addr offset = (offset1 << 8) | offset0;
+
+initAtomicAccess(gpuDynInst, offset);
+} // initiateAcc
+
+void
+Inst_DS__DS_ADD_F32::completeAcc(GPUDynInstPtr gpuDynInst)
+{
+} // completeAcc
// --- Inst_DS__DS_WRITE_B8 class methods ---
Inst_DS__DS_WRITE_B8::Inst_DS__DS_WRITE_B8(InFmt_DS *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index 33be33e..05a0002 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -31895,6 +31895,8 @@
}
} // getOperandSize
+void initiateAcc(GPUDynInstPtr gpuDynInst) override;
+void completeAcc(GPUDynInstPtr gpuDynInst) override;
void execute(GPUDynInstPtr) override;
}; // Inst_DS__DS_ADD_F32
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id4f23a1ab587a23edfd1d88ede1cbcc5bdedc0cb
Gerrit-Change-Number: 67074
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: util: Update run_gem5_fs.sh script with AArch64 platform
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/66856?usp=email )
(
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: util: Update run_gem5_fs.sh script with AArch64 platform
..
util: Update run_gem5_fs.sh script with AArch64 platform
The example script is using VExpress_EMM, which is a deprecated platform
and it is referring to an AArch32 kernel. With this patch we
use the VExpress_GEM5_Foundation platform instead and point
to a AArch64 kernel
Change-Id: I961d5d5de71bc284c7492ee7b04088148909ca1b
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66856
Maintainer: Daniel Carvalho
Reviewed-by: Matthias Jung
Reviewed-by: Daniel Carvalho
Tested-by: kokoro
---
M util/tlm/README
M util/tlm/run_gem5_fs.sh
2 files changed, 26 insertions(+), 7 deletions(-)
Approvals:
Matthias Jung: Looks good to me, approved
Daniel Carvalho: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/util/tlm/README b/util/tlm/README
index 8098afa..3ae43c5 100644
--- a/util/tlm/README
+++ b/util/tlm/README
@@ -145,10 +145,9 @@
> ../../build/ARM/gem5.opt ../../configs/example/fs.py \
--tlm-memory=transactor --cpu-type=TimingSimpleCPU --num-cpu=1 \
--mem-type=SimpleMemory --mem-size=512MB --mem-channels=1 --caches \
- --l2cache --machine-type=VExpress_EMM \
- --dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb\
- --kernel=vmlinux.aarch32.ll_20131205.0-gem5\
- --disk-image=linux-aarch32-ael.img
+ --l2cache --machine-type=VExpress_GEM5_Foundation \
+ --kernel=vmlinux.arm64 \
+ --disk-image=ubuntu-18.04-arm64-docker.img
The message "fatal: Can't find port handler type 'tlm_slave'" is okay.
The configuration will be stored in the m5out/ directory
diff --git a/util/tlm/run_gem5_fs.sh b/util/tlm/run_gem5_fs.sh
index 9065cbf..d8ab847 100755
--- a/util/tlm/run_gem5_fs.sh
+++ b/util/tlm/run_gem5_fs.sh
@@ -42,9 +42,9 @@
--mem-size=512MB\
--mem-channels=1\
--caches --l2cache \
---machine-type=VExpress_EMM \
---dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
---kernel=vmlinux.aarch32.ll_20131205.0-gem5
+--machine-type=VExpress_GEM5_Foundation \
+--kernel=vmlinux.arm64 \
+--disk-image=ubuntu-18.04-arm64-docker.img
echo -e "\n${BGre}Run gem5 ${RCol}\n"
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I961d5d5de71bc284c7492ee7b04088148909ca1b
Gerrit-Change-Number: 66856
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Matthias Jung
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Include libraries when building gem5 as a shared object
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/66855?usp=email ) Change subject: scons: Include libraries when building gem5 as a shared object .. scons: Include libraries when building gem5 as a shared object While we include shared libraries in the Executable class, we are not doing it when linking the SharedLib. This means the resulting Shared library won't have the library as a dependency (it won't appear in ldd) and the symbols will remain undefined. Any executable will fail to link with the shared library as the executable will contain undefined references. This bug was exposed when I tried to link util/tlm sources with libgem5.so. As I have libpng/libpng-dev installed in my machine, the shared library included libpng headers, but didn't link to the library as scons didn't append "-lpng" to the linking CL. Those png functions thus remained ubdefined symbols. Change-Id: Id9c4a65607a7177f71659f1ac400a67edf7080fd Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66855 Tested-by: kokoro Reviewed-by: Gabe Black Maintainer: Daniel Carvalho Reviewed-by: Daniel Carvalho Reviewed-by: Bobby Bruce --- M src/SConscript 1 file changed, 36 insertions(+), 0 deletions(-) Approvals: Daniel Carvalho: Looks good to me, but someone else must approve; Looks good to me, approved Gabe Black: Looks good to me, approved kokoro: Regressions pass Bobby Bruce: Looks good to me, approved diff --git a/src/SConscript b/src/SConscript index 4e7139c..51b4bd9 100644 --- a/src/SConscript +++ b/src/SConscript @@ -376,6 +376,12 @@ def declare(self, env): objs = self.srcs_to_objs(env, self.sources(env)) +libs = self.libs(env) +# Higher priority libraries should be earlier in the list. +libs.sort(key=lambda l: l.priority, reverse=True) +if libs: +env.Append(LIBS=list(lib.source for lib in libs)) + date_obj = env.SharedObject(date_source) env.Depends(date_obj, objs) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/66855?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Id9c4a65607a7177f71659f1ac400a67edf7080fd Gerrit-Change-Number: 66855 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [L] Change in gem5/gem5[develop]: base: socket: add UnixSocketAddr for representing socket paths
Simon Park has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/66471?usp=email )
Change subject: base: socket: add UnixSocketAddr for representing socket
paths
..
base: socket: add UnixSocketAddr for representing socket paths
Added UnixSocketAddr that wraps around sockaddr_un. Using this
wrapper, users can create both file based sockets as well as
abstract sockets.
Change-Id: Ibf105b92a6a6ac7fc9136ed307f824c83e45c06c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66471
Maintainer: Gabe Black
Reviewed-by: Gabe Black
Tested-by: kokoro
---
M src/base/SConscript
M src/base/socket.cc
M src/base/socket.hh
M src/base/socket.test.cc
M src/base/str.hh
M src/mem/shared_memory_server.cc
M src/mem/shared_memory_server.hh
7 files changed, 233 insertions(+), 32 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/SConscript b/src/base/SConscript
index e751d0b..4a6b65f 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -68,7 +68,8 @@
Source('random.cc')
Source('remote_gdb.cc')
Source('socket.cc')
-GTest('socket.test', 'socket.test.cc', 'socket.cc')
+SourceLib('z', tags='socket_test')
+GTest('socket.test', 'socket.test.cc', 'socket.cc', 'output.cc',
with_tag('socket_test'))
Source('statistics.cc')
Source('str.cc', add_tags=['gem5 trace', 'gem5 serialize'])
GTest('str.test', 'str.test.cc', 'str.cc')
diff --git a/src/base/socket.cc b/src/base/socket.cc
index 5cf67fd..23f2b40 100644
--- a/src/base/socket.cc
+++ b/src/base/socket.cc
@@ -35,22 +35,88 @@
#include
#include
#include
+#include
#include
#include
#include "base/logging.hh"
+#include "base/output.hh"
+#include "base/str.hh"
#include "base/types.hh"
#include "sim/byteswap.hh"
namespace gem5
{
+namespace
+{
+
+bool
+isSocketNameAbstract(const std::string )
+{
+if (path.empty()) {
+return false;
+}
+// No null byte should be present in the path
+return path.front() == '@';
+}
+
+std::string
+resolve(const std::string )
+{
+if (path.empty()) {
+return path;
+}
+if (isSocketNameAbstract(path)) {
+return '\0' + path.substr(1);
+}
+return simout.resolve(path);
+}
+
+} // namespace
bool ListenSocket::listeningDisabled = false;
bool ListenSocket::anyListening = false;
bool ListenSocket::bindToLoopback = false;
+UnixSocketAddr
+UnixSocketAddr::build(const std::string )
+{
+sockaddr_un addr = {.sun_family = AF_UNIX, .sun_path = {}};
+
+const bool is_abstract = isSocketNameAbstract(path);
+size_t max_len = sizeof(addr.sun_path);
+if (!is_abstract) {
+// File based socket names need to be null terminated
+max_len -= 1;
+}
+
+std::string resolved_path = resolve(path);
+std::string fmt_path = replace(resolved_path, '\0', '@');
+if (resolved_path.size() > max_len) {
+resolved_path = resolved_path.substr(0, max_len);
+const std::string untruncated_path = std::move(fmt_path);
+fmt_path = replace(resolved_path, '\0', '@');
+warn("SocketPath: unix socket path truncated from '%s' to '%s'",
+ untruncated_path, fmt_path);
+}
+
+// We can't use strncpy here, since abstract sockets start with \0
which
+// will make strncpy think that the string is empty.
+memcpy(addr.sun_path, resolved_path.c_str(), resolved_path.size());
+// We can't use sizeof(sockaddr_un) for abstract sockets, since all
+// sizeof(sun_path) bytes are used in representing the path.
+const size_t path_size =
+is_abstract ? resolved_path.size() : sizeof(addr.sun_path);
+const size_t addr_size = offsetof(sockaddr_un, sun_path) + path_size;
+
+return UnixSocketAddr{.addr = std::move(addr),
+ .addrSize = addr_size,
+ .isAbstract = is_abstract,
+ .formattedPath = std::move(fmt_path)};
+}
+
void
ListenSocket::cleanup()
{
diff --git a/src/base/socket.hh b/src/base/socket.hh
index 3375ccc..f3b2760 100644
--- a/src/base/socket.hh
+++ b/src/base/socket.hh
@@ -31,10 +31,44 @@
#include
#include
+#include
+
+#include
namespace gem5
{
+/**
+ * @brief Wrapper around sockaddr_un, so that it can be used for both file
+ * based unix sockets as well as abstract unix sockets.
+ */
+struct UnixSocketAddr
+{
+/**
+ * @brief Builds UnixSocketAddr from the given path.
+ * @pre: `path` either represents a file based unix socket, or an
abstract
+ * unix socket. If `path` represents an abstract socket, it
should
+ * start with the character '@', and it should not have any null
+ * bytes in the name.
+ * @param path: Pathname, where the socket should be instantiated.
+ * @return UnixSocketAddr
+ */
+static UnixSocketAddr build(const
