[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix page size handling when merging stage 1 and 2

[Andreas Sandberg (Gerrit)]

Hello Giacomo Travaglini,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10505

to review the following change.


Change subject: arch-arm: Fix page size handling when merging stage 1 and 2
..

arch-arm: Fix page size handling when merging stage 1 and 2

The current code to merge translation entries from stage 1 and stage 2
doesn't handle cases where the page sizes at the different stages
differ. This change fixes both the case when the hypervisor has a
larger page size and when it has a smaller page size.

Change-Id: Icdf289005bf1e4de4d91d54643924a38d9d77796
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/stage2_lookup.cc
1 file changed, 5 insertions(+), 4 deletions(-)



diff --git a/src/arch/arm/stage2_lookup.cc b/src/arch/arm/stage2_lookup.cc
index 82a29e8..00c515d 100644
--- a/src/arch/arm/stage2_lookup.cc
+++ b/src/arch/arm/stage2_lookup.cc
@@ -88,23 +88,24 @@
 // Now we have the table entries for both stages of translation
 // merge them and insert the result into the stage 1 TLB. See
 // CombineS1S2Desc() in pseudocode
-stage1Te.N = stage2Te->N;
 stage1Te.nonCacheable |= stage2Te->nonCacheable;
 stage1Te.xn   |= stage2Te->xn;

 if (stage1Te.size > stage2Te->size) {
 // Size mismatch also implies vpn mismatch (this is shifted by
 // sizebits!).
-stage1Te.vpn  = s1Req->getVaddr() / (stage2Te->size+1);
+stage1Te.vpn  = s1Req->getVaddr() >> stage2Te->N;
 stage1Te.pfn  = stage2Te->pfn;
 stage1Te.size = stage2Te->size;
+stage1Te.N= stage2Te->N;
 } else if (stage1Te.size < stage2Te->size) {
 // Guest 4K could well be section-backed by host hugepage!  In  
this
 // case a 4K entry is added but pfn needs to be adjusted.  New  
PFN =
 // offset into section PFN given by stage2 IPA treated as a  
stage1

 // page size.
-stage1Te.pfn = (stage2Te->pfn * ((stage2Te->size+1) /  
(stage1Te.size+1))) +

-   (stage2Te->vpn / (stage1Te.size+1));
+const Addr pa = (stage2Te->pfn << stage2Te->N);
+const Addr ipa = (stage1Te.pfn << stage1Te.N);
+stage1Te.pfn = (pa | (ipa & mask(stage2Te->N))) >> stage1Te.N;
 // Size remains smaller of the two.
 } else {
 // Matching sizes

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Icdf289005bf1e4de4d91d54643924a38d9d77796
Gerrit-Change-Number: 10505
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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Re: [gem5-dev] Either delete arm github linux kernel mirrors, or setup auto update, remove issue tracker an link to upstream

[Andreas Sandberg]

On 16/05/2018 08:10, Ciro Santilli wrote:

I recommend keeping them on GitHub but with fixes mentioned on title.

https://github.com/gem5/linux-arm64-gem5
https://github.com/gem5/linux-arm-gem5


I would be OK removing these repositories as they contain the old
kernels (they match arm/linux-{arm,arm64}-legacy on gerrit). The old
kernels used to have different code bases and patches for aarch32 and
aarch64 and were based on a Linaro tree, this was undesirable for
multiple reasons. The new kernel is based on Linus's tree and has a
cleaner branch name policy (gem5 branches are all called gem5/vX.Y). To
avoid having lots of old branch names without any logic, I decided to
deprecate the old repos and create a new unifed kernel repo. The new
kernel lives in the arm/linux repo on gerrit.


They are not getting the latest code it seems, no v4.15 for example.


That's by design since they contain an ancient and broken Linaro kernel.
The new repo contains a kernel based on upstream.

Cheers,
Andreas
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix semihosting arg count for SYS_GET_CMDLINE

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/10022 )


Change subject: arch-arm: Fix semihosting arg count for SYS_GET_CMDLINE
..

arch-arm: Fix semihosting arg count for SYS_GET_CMDLINE

SYS_GET_CMDLINE was declared as having 1 parameter when it is really
supposed to have two parameters.

Change-Id: Ia364abb4b34834f4d5e598b5adee9585e0815ac8
Reported-by: Steve Capper <steve.cap...@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10022
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/semihosting.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 46d964d..51107cb 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -76,7 +76,7 @@
 { 0x11, { "SYS_TIME", ::callTime, 0, 0} },
 { 0x12, { "SYS_SYSTEM", ::callSystem, 2, 2} },
 { 0x13, { "SYS_ERRNO", ::callErrno, 0, 0 } },
-{ 0x15, { "SYS_GET_CMDLINE", ::callGetCmdLine, 1, 1} },
+{ 0x15, { "SYS_GET_CMDLINE", ::callGetCmdLine, 2, 2} },
 { 0x16, { "SYS_HEAPINFO", ::callHeapInfo, 1, 1} },

 // Exit is special and requires custom handling in aarch32.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ia364abb4b34834f4d5e598b5adee9585e0815ac8
Gerrit-Change-Number: 10022
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add support for semihosting STDIO redirection

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/10021 )


Change subject: arch-arm: Add support for semihosting STDIO redirection
..

arch-arm: Add support for semihosting STDIO redirection

The Arm Semihosting layer currently assumes that the guest application
shares STDIO with gem5. This makes it hard to distinguish application
output from gem5's output and makes it impossible to redirect STDIN
when running in interactive mode. Add support for custom STDIO
redirection when instantiating the Semihosting model.

Change-Id: I3411a6b9bfb008ffc3087d8837f59be72bd1e8ae
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanl...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10021
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/ArmSemihosting.py
M src/arch/arm/semihosting.cc
M src/arch/arm/semihosting.hh
3 files changed, 49 insertions(+), 5 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/ArmSemihosting.py b/src/arch/arm/ArmSemihosting.py
index 1da4c49..7846499 100644
--- a/src/arch/arm/ArmSemihosting.py
+++ b/src/arch/arm/ArmSemihosting.py
@@ -46,6 +46,12 @@
 cxx_header = "arch/arm/semihosting.hh"

 cmd_line = Param.String("", "Command line to report to guest");
+stdin = Param.String("stdin",
+ "Standard input (stdin for gem5's terminal)")
+stdout = Param.String("stdout",
+  "Standard output (stdout for gem5's terminal)")
+stderr = Param.String("stderr",
+  "Standard error (stderr for gem5's terminal)")

 mem_reserve = Param.MemorySize("32MB",
 "Amount of memory to reserve at the start of the address map.  
This "

diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 89e1b2e..46d964d 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -121,6 +121,15 @@
 0x3,// EXT_EXIT_EXTENDED, EXT_STDOUT_STDERR
 };

+const std::map ArmSemihosting::stdioMap{
+{"cin",::stdin},
+{"stdin",  ::stdin},
+{"cout",   ::stdout},
+{"stdout", ::stdout},
+{"cerr",   ::stderr},
+{"stderr", ::stderr},
+};
+
 ArmSemihosting::ArmSemihosting(const ArmSemihostingParams *p)
 : SimObject(p),
   cmdLine(p->cmd_line),
@@ -128,7 +137,11 @@
   stackSize(p->stack_size),
   timeBase([p]{ struct tm t = p->time; return mkutctime(); }()),
   tickShift(calcTickShift()),
-  semiErrno(0)
+  semiErrno(0),
+  stdin(getSTDIO("stdin", p->stdin, "r")),
+  stdout(getSTDIO("stdout", p->stdout, "w")),
+  stderr(p->stderr == p->stdout ?
+ stdout : getSTDIO("stderr", p->stderr, "w"))
 {
 // Create an empty place-holder file for position 0 as semi-hosting
 // calls typically expect non-zero file handles.
@@ -681,6 +694,23 @@
 }
 }

+FILE *
+ArmSemihosting::getSTDIO(const char *stream_name,
+ const std::string , const char *mode)
+{
+auto it = stdioMap.find(name);
+if (it == stdioMap.end()) {
+FILE *f = fopen(name.c_str(), mode);
+if (!f) {
+fatal("Failed to open %s (%s): %s\n",
+  stream_name, name, strerror(errno));
+}
+return f;
+} else {
+return it->second;
+}
+}
+
 std::unique_ptr
 ArmSemihosting::FileBase::create(
 ArmSemihosting , const std::string , const char *mode)
@@ -819,11 +849,11 @@

 if (_name == ":tt") {
 if (mode[0] == 'r') {
-file = stdin;
+file = parent.stdin;
 } else if (mode[0] == 'w') {
-file = stdout;
+file = parent.stdout;
 } else if (mode[0] == 'a') {
-file = stderr;
+file = parent.stderr;
 } else {
 warn("Unknown file mode for the ':tt' special file");
 return -EINVAL;
@@ -857,7 +887,9 @@
 bool
 ArmSemihosting::File::isTTY() const
 {
-return file == stdout || file == stderr || file == stdin;
+return file == parent.stdout ||
+file == parent.stderr ||
+file == parent.stdin;
 }

 int64_t
diff --git a/src/arch/arm/semihosting.hh b/src/arch/arm/semihosting.hh
index 14c5f9d..5816460 100644
--- a/src/arch/arm/semihosting.hh
+++ b/src/arch/arm/semihosting.hh
@@ -244,6 +244,9 @@
 };

 std

[gem5-dev] Change in gem5/gem5[master]: base, dev: Fix port message for vnc and terminal

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/10026 )


Change subject: base, dev: Fix port message for vnc and terminal
..

base, dev: Fix port message for vnc and terminal

When running gem5, the simulator outputs the following message to
describe the ports used by the VNC server and ther terminal:

Listening for system connection on port 5900
Listening for system connection on port 3456

The code used to extract the basename ('terminal' or 'vncserver') and
print that instead of system. However, this doesn't seem to work any
more. Change the code to output the full object name instead.

Change-Id: Ib27f66a5f8ba64c7a875b4e2f26a2e2ff48db8f3
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10026
Reviewed-by: Gabe Black <gabebl...@google.com>
Reviewed-by: Jason Lowe-Power <ja...@lowepower.com>
Maintainer: Jason Lowe-Power <ja...@lowepower.com>
---
M src/base/vnc/vncserver.cc
M src/dev/serial/terminal.cc
2 files changed, 4 insertions(+), 10 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved



diff --git a/src/base/vnc/vncserver.cc b/src/base/vnc/vncserver.cc
index 97515ac..a37f1dd 100644
--- a/src/base/vnc/vncserver.cc
+++ b/src/base/vnc/vncserver.cc
@@ -174,11 +174,8 @@
 port++;
 }

-int p1, p2;
-p2 = name().rfind('.') - 1;
-p1 = name().rfind('.', p2);
-ccprintf(cerr, "Listening for %s connection on port %d\n",
- name().substr(p1 + 1, p2 - p1), port);
+ccprintf(cerr, "%s: Listening for connections on port %d\n",
+ name(), port);

 listenEvent = new ListenEvent(this, listener.getfd(), POLLIN);
 pollQueue.schedule(listenEvent);
diff --git a/src/dev/serial/terminal.cc b/src/dev/serial/terminal.cc
index 5e8e52e..bc8c14c 100644
--- a/src/dev/serial/terminal.cc
+++ b/src/dev/serial/terminal.cc
@@ -153,11 +153,8 @@
 port++;
 }

-int p1, p2;
-p2 = name().rfind('.') - 1;
-p1 = name().rfind('.', p2);
-ccprintf(cerr, "Listening for %s connection on port %d\n",
-name().substr(p1+1,p2-p1), port);
+ccprintf(cerr, "%s: Listening for connections on port %d\n",
+ name(), port);

 listenEvent = new ListenEvent(this, listener.getfd(), POLLIN);
 pollQueue.schedule(listenEvent);

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib27f66a5f8ba64c7a875b4e2f26a2e2ff48db8f3
Gerrit-Change-Number: 10026
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Anouk Van Laer <anouk.vanl...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: dev: Add support for a simple debug UART

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/10025 )


Change subject: dev: Add support for a simple debug UART
..

dev: Add support for a simple debug UART

Add a simple memory-mapped device that forwards writes to a serial
devices and treats reads as reads from the device. Unlike real UART
models, this one doesn't support interrupts.

This is useful to implement various debug devices that exist in many
systems.

Change-Id: I1e4300e4d3b70825a15d03f47d4e026941f9066c
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10025
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/serial/SConscript
M src/dev/serial/Uart.py
A src/dev/serial/simple.cc
A src/dev/serial/simple.hh
4 files changed, 180 insertions(+), 0 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/dev/serial/SConscript b/src/dev/serial/SConscript
index b9f13f5..9fe5ece 100644
--- a/src/dev/serial/SConscript
+++ b/src/dev/serial/SConscript
@@ -50,6 +50,7 @@
 SimObject('Uart.py')

 Source('serial.cc')
+Source('simple.cc')
 Source('terminal.cc')
 Source('uart.cc')
 Source('uart8250.cc')
diff --git a/src/dev/serial/Uart.py b/src/dev/serial/Uart.py
index 5333705..029d46c 100644
--- a/src/dev/serial/Uart.py
+++ b/src/dev/serial/Uart.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2018 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2005-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -38,6 +50,14 @@
 platform = Param.Platform(Parent.any, "Platform this device is part  
of.")

 device = Param.SerialDevice(Parent.any, "The terminal")

+class SimpleUart(Uart):
+type = 'SimpleUart'
+cxx_header = "dev/serial/simple.hh"
+big_endian = Param.Bool(False, "Is the device Big Endian?")
+pio_size = Param.Addr(0x4, "Size of address range")
+end_on_eot = Param.Bool(False, "End the simulation when a EOT is "\
+"received on the UART")
+
 class Uart8250(Uart):
 type = 'Uart8250'
 cxx_header = "dev/serial/uart8250.hh"
diff --git a/src/dev/serial/simple.cc b/src/dev/serial/simple.cc
new file mode 100644
index 000..aea94f9
--- /dev/null
+++ b/src/dev/serial/simple.cc
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

[gem5-dev] Change in gem5/gem5[master]: base, dev: Fix port message for vnc and terminal

[Andreas Sandberg (Gerrit)]

Hello Anouk Van Laer,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10026

to review the following change.


Change subject: base, dev: Fix port message for vnc and terminal
..

base, dev: Fix port message for vnc and terminal

When running gem5, the simulator outputs the following message to
describe the ports used by the VNC server and ther terminal:

Listening for system connection on port 5900
Listening for system connection on port 3456

The code used to extract the basename ('terminal' or 'vncserver') and
print that instead of system. However, this doesn't seem to work any
more. Change the code to output the full object name instead.

Change-Id: Ib27f66a5f8ba64c7a875b4e2f26a2e2ff48db8f3
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanl...@arm.com>
---
M src/base/vnc/vncserver.cc
M src/dev/serial/terminal.cc
2 files changed, 4 insertions(+), 10 deletions(-)



diff --git a/src/base/vnc/vncserver.cc b/src/base/vnc/vncserver.cc
index 97515ac..a37f1dd 100644
--- a/src/base/vnc/vncserver.cc
+++ b/src/base/vnc/vncserver.cc
@@ -174,11 +174,8 @@
 port++;
 }

-int p1, p2;
-p2 = name().rfind('.') - 1;
-p1 = name().rfind('.', p2);
-ccprintf(cerr, "Listening for %s connection on port %d\n",
- name().substr(p1 + 1, p2 - p1), port);
+ccprintf(cerr, "%s: Listening for connections on port %d\n",
+ name(), port);

 listenEvent = new ListenEvent(this, listener.getfd(), POLLIN);
 pollQueue.schedule(listenEvent);
diff --git a/src/dev/serial/terminal.cc b/src/dev/serial/terminal.cc
index 5e8e52e..bc8c14c 100644
--- a/src/dev/serial/terminal.cc
+++ b/src/dev/serial/terminal.cc
@@ -153,11 +153,8 @@
 port++;
 }

-int p1, p2;
-p2 = name().rfind('.') - 1;
-p1 = name().rfind('.', p2);
-ccprintf(cerr, "Listening for %s connection on port %d\n",
-name().substr(p1+1,p2-p1), port);
+ccprintf(cerr, "%s: Listening for connections on port %d\n",
+ name(), port);

 listenEvent = new ListenEvent(this, listener.getfd(), POLLIN);
 pollQueue.schedule(listenEvent);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib27f66a5f8ba64c7a875b4e2f26a2e2ff48db8f3
Gerrit-Change-Number: 10026
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Anouk Van Laer <anouk.vanl...@arm.com>
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: dev: Add support for a simple debug UART

[Andreas Sandberg (Gerrit)]

Hello Giacomo Travaglini,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10025

to review the following change.


Change subject: dev: Add support for a simple debug UART
..

dev: Add support for a simple debug UART

Add a simple memory-mapped device that forwards writes to a serial
devices and treats reads as reads from the device. Unlike real UART
models, this one doesn't support interrupts.

This is useful to implement various debug devices that exist in many
systems.

Change-Id: I1e4300e4d3b70825a15d03f47d4e026941f9066c
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/serial/SConscript
M src/dev/serial/Uart.py
A src/dev/serial/simple.cc
A src/dev/serial/simple.hh
4 files changed, 180 insertions(+), 0 deletions(-)



diff --git a/src/dev/serial/SConscript b/src/dev/serial/SConscript
index b9f13f5..9fe5ece 100644
--- a/src/dev/serial/SConscript
+++ b/src/dev/serial/SConscript
@@ -50,6 +50,7 @@
 SimObject('Uart.py')

 Source('serial.cc')
+Source('simple.cc')
 Source('terminal.cc')
 Source('uart.cc')
 Source('uart8250.cc')
diff --git a/src/dev/serial/Uart.py b/src/dev/serial/Uart.py
index 5333705..029d46c 100644
--- a/src/dev/serial/Uart.py
+++ b/src/dev/serial/Uart.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2018 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2005-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -38,6 +50,14 @@
 platform = Param.Platform(Parent.any, "Platform this device is part  
of.")

 device = Param.SerialDevice(Parent.any, "The terminal")

+class SimpleUart(Uart):
+type = 'SimpleUart'
+cxx_header = "dev/serial/simple.hh"
+big_endian = Param.Bool(False, "Is the device Big Endian?")
+pio_size = Param.Addr(0x4, "Size of address range")
+end_on_eot = Param.Bool(False, "End the simulation when a EOT is "\
+"received on the UART")
+
 class Uart8250(Uart):
 type = 'Uart8250'
 cxx_header = "dev/serial/uart8250.hh"
diff --git a/src/dev/serial/simple.cc b/src/dev/serial/simple.cc
new file mode 100644
index 000..aea94f9
--- /dev/null
+++ b/src/dev/serial/simple.cc
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCL

[gem5-dev] Change in gem5/gem5[master]: dev, arm: Add support for HYP & secure timers

[Andreas Sandberg (Gerrit)]

Hello Curtis Dunham,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10023

to review the following change.


Change subject: dev, arm: Add support for HYP & secure timers
..

dev, arm: Add support for HYP & secure timers

Change-Id: I1a4849283f9bd5b1856e1378f7cefc33fc14eebd
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Curtis Dunham <curtis.dun...@arm.com>
---
M src/arch/arm/miscregs.cc
M src/dev/arm/RealView.py
M src/dev/arm/generic_timer.cc
M src/dev/arm/generic_timer.hh
4 files changed, 131 insertions(+), 85 deletions(-)



diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 81ce43e..3e2bcc4 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -3170,7 +3170,6 @@
   .privSecure(!aarch32EL3)
   .monSecure(0);
 InitReg(MISCREG_CNTP_TVAL_S)
-  .unimplemented()
   .bankedChild()
   .secure().user(1);
 InitReg(MISCREG_CNTP_CTL)
@@ -3181,7 +3180,6 @@
   .privSecure(!aarch32EL3)
   .monSecure(0);
 InitReg(MISCREG_CNTP_CTL_S)
-  .unimplemented()
   .bankedChild()
   .secure().user(1);
 InitReg(MISCREG_CNTV_TVAL)
@@ -3189,13 +3187,10 @@
 InitReg(MISCREG_CNTV_CTL)
   .allPrivileges();
 InitReg(MISCREG_CNTHCTL)
-  .unimplemented()
   .hypWrite().monNonSecureRead();
 InitReg(MISCREG_CNTHP_TVAL)
-  .unimplemented()
   .hypWrite().monNonSecureRead();
 InitReg(MISCREG_CNTHP_CTL)
-  .unimplemented()
   .hypWrite().monNonSecureRead();
 InitReg(MISCREG_IL1DATA0)
   .unimplemented()
@@ -3250,7 +3245,6 @@
   .privSecure(!aarch32EL3)
   .monSecure(0);
 InitReg(MISCREG_CNTP_CVAL_S)
-  .unimplemented()
   .bankedChild()
   .secure().user(1);
 InitReg(MISCREG_CNTV_CVAL)
@@ -3258,7 +3252,6 @@
 InitReg(MISCREG_CNTVOFF)
   .hyp().monNonSecure();
 InitReg(MISCREG_CNTHP_CVAL)
-  .unimplemented()
   .hypWrite().monNonSecureRead();
 InitReg(MISCREG_CPUMERRSR)
   .unimplemented()
@@ -3915,31 +3908,23 @@
   .hyp().mon()
   .mapsTo(MISCREG_CNTVOFF); /* 64b */
 InitReg(MISCREG_CNTHCTL_EL2)
-  .unimplemented()
-  .warnNotFail()
-  .mon().monNonSecureWrite(0).hypWrite()
+  .mon().hyp()
   .mapsTo(MISCREG_CNTHCTL);
 InitReg(MISCREG_CNTHP_TVAL_EL2)
-  .unimplemented()
-  .mon().monNonSecureWrite(0).hypWrite()
+  .mon().hyp()
   .mapsTo(MISCREG_CNTHP_TVAL);
 InitReg(MISCREG_CNTHP_CTL_EL2)
-  .unimplemented()
-  .mon().monNonSecureWrite(0).hypWrite()
+  .mon().hyp()
   .mapsTo(MISCREG_CNTHP_CTL);
 InitReg(MISCREG_CNTHP_CVAL_EL2)
-  .unimplemented()
-  .mon().monNonSecureWrite(0).hypWrite()
+  .mon().hyp()
   .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
 InitReg(MISCREG_CNTPS_TVAL_EL1)
-  .unimplemented()
-  .mon().monNonSecureWrite(0).hypWrite();
+  .mon().privSecure();
 InitReg(MISCREG_CNTPS_CTL_EL1)
-  .unimplemented()
-  .mon().monNonSecureWrite(0).hypWrite();
+  .mon().privSecure();
 InitReg(MISCREG_CNTPS_CVAL_EL1)
-  .unimplemented()
-  .mon().monNonSecureWrite(0).hypWrite();
+  .mon().privSecure();
 InitReg(MISCREG_IL1DATA0_EL1)
   .allPrivileges().exceptUserMode();
 InitReg(MISCREG_IL1DATA1_EL1)
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 9b91f46..308de18 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -418,10 +418,10 @@
 cxx_header = "dev/arm/generic_timer.hh"
 system = Param.ArmSystem(Parent.any, "system")
 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
-# @todo: for now only two timers per CPU is supported, which is the
-# normal behaviour when security extensions are disabled.
-int_phys = Param.UInt32("Physical timer interrupt number")
+int_phys_s = Param.UInt32("Physical (S) timer interrupt number")
+int_phys_ns = Param.UInt32("Physical (NS) timer interrupt number")
 int_virt = Param.UInt32("Virtual timer interrupt number")
+int_hyp = Param.UInt32("Hypervisor timer interrupt number")

 def generateDeviceTree(self, state):
 node = FdtNode("timer")
@@ -429,9 +429,12 @@
 node.appendCompatible(["arm,cortex-a15-timer",
"arm,armv7-timer",
"arm,armv8-timer"])
-node.append(FdtPropertyWords("interrupts",
-[1, int(self.int_phys) - 16, 0xf08,
-1, int(self.int_virt) - 16, 0xf08]))
+node.append(FdtPropertyWords("interrupts", [
+1, int(self.int_phys_s) - 16, 0xf08,
+1, int(self.int_phys_ns) - 16, 0xf08,
+1, int(self.int_virt) - 16, 0xf08,
+1,

[gem5-dev] Change in gem5/gem5[master]: system-arm: Update gem5 timer interrupt specification

[Andreas Sandberg (Gerrit)]

Hello Gabor Dozsa,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10024

to review the following change.


Change subject: system-arm: Update gem5 timer interrupt specification
..

system-arm: Update gem5 timer interrupt specification

The DTB for the VExpress_GEM5_V1 was incorrectly flagging timer
interrupts as being edge triggered. Describe the interrupt as being
level triggered to match Juno and FVP.

Change-Id: I9ce4b8959e7cc28d8b208727119ff20e581311f8
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Gabor Dozsa <gabor.do...@arm.com>
---
M system/arm/dt/platforms/vexpress_gem5_v1.dtsi
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/system/arm/dt/platforms/vexpress_gem5_v1.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v1.dtsi

index 4d463e7..d7d77fb 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v1.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v1.dtsi
@@ -51,9 +51,9 @@
timer {
compatible = "arm,cortex-a15-timer",
 "arm,armv7-timer";
-   interrupts = <1 13 0xff01>,
-<1 14 0xff01>,
-<1 11 0xff01>;
+   interrupts = <1 13 0xf08>,
+<1 14 0xf08>,
+<1 11 0xf08>;
clocks = <_sys>;
clock-names="apb_pclk";
};

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I9ce4b8959e7cc28d8b208727119ff20e581311f8
Gerrit-Change-Number: 10024
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabor Dozsa <gabor.do...@arm.com>
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add support for semihosting STDIO redirection

[Andreas Sandberg (Gerrit)]

Hello Anouk Van Laer, Giacomo Travaglini,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10021

to review the following change.


Change subject: arch-arm: Add support for semihosting STDIO redirection
..

arch-arm: Add support for semihosting STDIO redirection

The Arm Semihosting layer currently assumes that the guest application
shares STDIO with gem5. This makes it hard to distinguish application
output from gem5's output and makes it impossible to redirect STDIN
when running in interactive mode. Add support for custom STDIO
redirection when instantiating the Semihosting model.

Change-Id: I3411a6b9bfb008ffc3087d8837f59be72bd1e8ae
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanl...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/ArmSemihosting.py
M src/arch/arm/semihosting.cc
M src/arch/arm/semihosting.hh
3 files changed, 49 insertions(+), 5 deletions(-)



diff --git a/src/arch/arm/ArmSemihosting.py b/src/arch/arm/ArmSemihosting.py
index 1da4c49..7846499 100644
--- a/src/arch/arm/ArmSemihosting.py
+++ b/src/arch/arm/ArmSemihosting.py
@@ -46,6 +46,12 @@
 cxx_header = "arch/arm/semihosting.hh"

 cmd_line = Param.String("", "Command line to report to guest");
+stdin = Param.String("stdin",
+ "Standard input (stdin for gem5's terminal)")
+stdout = Param.String("stdout",
+  "Standard output (stdout for gem5's terminal)")
+stderr = Param.String("stderr",
+  "Standard error (stderr for gem5's terminal)")

 mem_reserve = Param.MemorySize("32MB",
 "Amount of memory to reserve at the start of the address map.  
This "

diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 89e1b2e..46d964d 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -121,6 +121,15 @@
 0x3,// EXT_EXIT_EXTENDED, EXT_STDOUT_STDERR
 };

+const std::map ArmSemihosting::stdioMap{
+{"cin",::stdin},
+{"stdin",  ::stdin},
+{"cout",   ::stdout},
+{"stdout", ::stdout},
+{"cerr",   ::stderr},
+{"stderr", ::stderr},
+};
+
 ArmSemihosting::ArmSemihosting(const ArmSemihostingParams *p)
 : SimObject(p),
   cmdLine(p->cmd_line),
@@ -128,7 +137,11 @@
   stackSize(p->stack_size),
   timeBase([p]{ struct tm t = p->time; return mkutctime(); }()),
   tickShift(calcTickShift()),
-  semiErrno(0)
+  semiErrno(0),
+  stdin(getSTDIO("stdin", p->stdin, "r")),
+  stdout(getSTDIO("stdout", p->stdout, "w")),
+  stderr(p->stderr == p->stdout ?
+ stdout : getSTDIO("stderr", p->stderr, "w"))
 {
 // Create an empty place-holder file for position 0 as semi-hosting
 // calls typically expect non-zero file handles.
@@ -681,6 +694,23 @@
 }
 }

+FILE *
+ArmSemihosting::getSTDIO(const char *stream_name,
+ const std::string , const char *mode)
+{
+auto it = stdioMap.find(name);
+if (it == stdioMap.end()) {
+FILE *f = fopen(name.c_str(), mode);
+if (!f) {
+fatal("Failed to open %s (%s): %s\n",
+  stream_name, name, strerror(errno));
+}
+return f;
+} else {
+return it->second;
+}
+}
+
 std::unique_ptr
 ArmSemihosting::FileBase::create(
 ArmSemihosting , const std::string , const char *mode)
@@ -819,11 +849,11 @@

 if (_name == ":tt") {
 if (mode[0] == 'r') {
-file = stdin;
+file = parent.stdin;
 } else if (mode[0] == 'w') {
-file = stdout;
+file = parent.stdout;
 } else if (mode[0] == 'a') {
-file = stderr;
+file = parent.stderr;
 } else {
 warn("Unknown file mode for the ':tt' special file");
 return -EINVAL;
@@ -857,7 +887,9 @@
 bool
 ArmSemihosting::File::isTTY() const
 {
-return file == stdout || file == stderr || file == stdin;
+return file == parent.stdout ||
+file == parent.stderr ||
+file == parent.stdin;
 }

 int64_t
diff --git a/src/arch/arm/semihosting.hh b/src/arch/arm/semihosting.hh
index 14c5f9d..5816460 100644
--- a/src/arch/arm/semihosting.hh
+++ b/src/arch/arm/semihosting.hh
@@ -244,6 +244,9 @@
 };

 std::vector<std::unique_ptr> files;
+FILE *stdin;
+FILE *stdout;
+FILE *stderr;

   protected: // Helper functions
 unsigned calcTickShift() const {
@@ -342,11 +345,14 @@
 #undef SEMI_CALL

 static const SemiCa

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix semihosting arg count for SYS_GET_CMDLINE

[Andreas Sandberg (Gerrit)]

Hello Giacomo Travaglini,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10022

to review the following change.


Change subject: arch-arm: Fix semihosting arg count for SYS_GET_CMDLINE
..

arch-arm: Fix semihosting arg count for SYS_GET_CMDLINE

SYS_GET_CMDLINE was declared as having 1 parameter when it is really
supposed to have two parameters.

Change-Id: Ia364abb4b34834f4d5e598b5adee9585e0815ac8
Reported-by: Steve Capper <steve.cap...@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/semihosting.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 46d964d..51107cb 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -76,7 +76,7 @@
 { 0x11, { "SYS_TIME", ::callTime, 0, 0} },
 { 0x12, { "SYS_SYSTEM", ::callSystem, 2, 2} },
 { 0x13, { "SYS_ERRNO", ::callErrno, 0, 0 } },
-{ 0x15, { "SYS_GET_CMDLINE", ::callGetCmdLine, 1, 1} },
+{ 0x15, { "SYS_GET_CMDLINE", ::callGetCmdLine, 2, 2} },
 { 0x16, { "SYS_HEAPINFO", ::callHeapInfo, 1, 1} },

 // Exit is special and requires custom handling in aarch32.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ia364abb4b34834f4d5e598b5adee9585e0815ac8
Gerrit-Change-Number: 10022
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: dev, arm: Cleanup Pl050 interrupt handling

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/9769 )


Change subject: dev, arm: Cleanup Pl050 interrupt handling
..

dev, arm: Cleanup Pl050 interrupt handling

Add support for TX interrupts and cleanup existing RX interrupt
handling.

Change-Id: If2e5b0c0cc6fbeb2dce09e7e9d935647516b2c47
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9769
---
M src/dev/arm/RealView.py
M src/dev/arm/kmi.cc
M src/dev/arm/kmi.hh
3 files changed, 71 insertions(+), 77 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 7661db1..9b91f46 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -466,7 +466,6 @@
 class Pl050(AmbaIntDevice):
 type = 'Pl050'
 cxx_header = "dev/arm/kmi.hh"
-int_delay = '1us'
 amba_id = 0x00141050

 ps2 = Param.PS2Device("PS/2 device")
diff --git a/src/dev/arm/kmi.cc b/src/dev/arm/kmi.cc
index 1636d5d..70c64e4 100644
--- a/src/dev/arm/kmi.cc
+++ b/src/dev/arm/kmi.cc
@@ -54,10 +54,9 @@
 Pl050::Pl050(const Pl050Params *p)
 : AmbaIntDevice(p, 0xfff), control(0), status(0x43), clkdiv(0),
   rawInterrupts(0),
-  intEvent([this]{ generateInterrupt(); }, name()),
   ps2(p->ps2)
 {
-ps2->hostRegDataAvailable([this]() { this->updateIntStatus(); });
+ps2->hostRegDataAvailable([this]() { this->updateRxInt(); });
 }

 Tick
@@ -83,8 +82,8 @@

   case kmiData:
 data = ps2->hostDataAvailable() ? ps2->hostRead() : 0;
+updateRxInt();
 DPRINTF(Pl050, "Read Data: %#x\n", (uint32_t)data);
-updateIntStatus();
 break;

   case kmiClkDiv:
@@ -107,21 +106,7 @@
 break;
 }

-switch(pkt->getSize()) {
-  case 1:
-pkt->set(data);
-break;
-  case 2:
-pkt->set(data);
-break;
-  case 4:
-pkt->set(data);
-break;
-  default:
-panic("KMI read size too big?\n");
-break;
-}
-
+pkt->setUintX(data, LittleEndianByteOrder);
 pkt->makeAtomicResponse();
 return pioDelay;
 }
@@ -133,29 +118,36 @@
 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr +  
pioSize);


 Addr daddr = pkt->getAddr() - pioAddr;
+const uint32_t data = pkt->getUintX(LittleEndianByteOrder);

-assert(pkt->getSize() == sizeof(uint8_t));
-
+panic_if(pkt->getSize() != 1,
+ "PL050: Unexpected write size "
+ "(offset: %#x, data: %#x, size: %u)\n",
+ daddr, data, pkt->getSize());

 switch (daddr) {
   case kmiCr:
-DPRINTF(Pl050, "Write Commmand: %#x\n",  
(uint32_t)pkt->get());

-control = pkt->get();
-updateIntStatus();
+DPRINTF(Pl050, "Write Commmand: %#x\n", data);
+// Use the update interrupts helper to make sure any interrupt
+// mask changes are handled correctly.
+setControl((uint8_t)data);
 break;

   case kmiData:
-DPRINTF(Pl050, "Write Data: %#x\n", (uint32_t)pkt->get());
-ps2->hostWrite(pkt->get());
-updateIntStatus();
+DPRINTF(Pl050, "Write Data: %#x\n", data);
+// Clear the TX interrupt before writing new data.
+setTxInt(false);
+ps2->hostWrite((uint8_t)data);
+// Data is written in 0 time, so raise the TX interrupt again.
+setTxInt(true);
 break;

   case kmiClkDiv:
-clkdiv = pkt->get();
+clkdiv = (uint8_t)data;
 break;

   default:
-warn("Tried to write PL050 at offset %#x that doesn't exist\n",  
daddr);

+warn("PL050: Unhandled write of %#x to offset %#x\n", data, daddr);
 break;
 }

@@ -163,18 +155,42 @@
 return pioDelay;
 }

+void
+Pl050::setTxInt(bool value)
+{
+InterruptReg ints = rawInterrupts;
+
+ints.tx = value ? 1 : 0;
+
+setInterrupts(ints);
+}

 void
-Pl050::updateIntStatus()
+Pl050::updateRxInt()
 {
-const bool old_interrupt(getInterrupt());
+InterruptReg ints = rawInterrupts;

-rawInterrupts.rx = ps2->hostDataAvailable() ? 1 : 0;
+ints.rx = ps2->hostDataAvailable() ? 1 : 0;

-if ((!old_interrupt && getInterrupt()) && !intEvent.scheduled()) {
-schedule(intEvent, curTick() + intDelay);
-} else if (old_interrupt && !(getInterrupt())) {
-gic->clearInt(intNum);
+setInterrupts(ints);
+}
+
+void
+Pl050::

[gem5-dev] Change in gem5/gem5[master]: dev, arm: Use the PS/2 framework in the Pl050 model

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/9767 )


Change subject: dev, arm: Use the PS/2 framework in the Pl050 model
..

dev, arm: Use the PS/2 framework in the Pl050 model

The Pl050 KMI model currently has its own keyboard and mouse
models. Use the generic PS/2 interface instead.

Change-Id: I6523d26f8e38bcc8ba399d4d1a131723645d36c7
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9767
Reviewed-by: Gabe Black <gabebl...@google.com>
---
M src/dev/arm/RealView.py
M src/dev/arm/kmi.cc
M src/dev/arm/kmi.hh
3 files changed, 51 insertions(+), 205 deletions(-)

Approvals:
  Gabe Black: Looks good to me, but someone else must approve
  Giacomo Travaglini: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index a59e171..7661db1 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -62,6 +62,7 @@
 from SubSystem import SubSystem
 from Graphics import ImageFormat
 from ClockedObject import ClockedObject
+from PS2 import *

 # Platforms with KVM support should generally use in-kernel GIC
 # emulation. Use a GIC model that automatically switches between
@@ -465,11 +466,11 @@
 class Pl050(AmbaIntDevice):
 type = 'Pl050'
 cxx_header = "dev/arm/kmi.hh"
-vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer  
display")
-is_mouse = Param.Bool(False, "Is this interface a mouse, if not a  
keyboard")

 int_delay = '1us'
 amba_id = 0x00141050

+ps2 = Param.PS2Device("PS/2 device")
+
 def generateDeviceTree(self, state):
 node = self.generateBasicPioDeviceNode(state, 'kmi', self.pio_addr,
0x1000, [int(self.int_num)])
@@ -624,8 +625,8 @@
 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30,
 pio_addr=0x1f000600)
 clcd = Pl111(pio_addr=0x1002, int_num=55)
-kmi0   = Pl050(pio_addr=0x10006000, int_num=52)
-kmi1   = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
+kmi0   = Pl050(pio_addr=0x10006000, int_num=52, ps2=PS2Keyboard())
+kmi1   = Pl050(pio_addr=0x10007000, int_num=53, ps2=PS2TouchKit())
 a9scu  = A9SCU(pio_addr=0x1f00)
 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
 io_shift = 1, ctrl_offset = 2, Command = 0x1,
@@ -753,8 +754,8 @@
 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
 clcd   = Pl111(pio_addr=0x1002, int_num=23)
-kmi0   = Pl050(pio_addr=0x10006000, int_num=20)
-kmi1   = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
+kmi0   = Pl050(pio_addr=0x10006000, int_num=20, ps2=PS2Keyboard())
+kmi1   = Pl050(pio_addr=0x10007000, int_num=21, ps2=PS2TouchKit())

 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff,  
warn_access="1")

 flash_fake= IsaFake(pio_addr=0x4000, pio_size=0x2000-1,
@@ -904,8 +905,8 @@
 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C11,  
clock0='1MHz', clock1='1MHz')
 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C12,  
clock0='1MHz', clock1='1MHz')

 clcd   = Pl111(pio_addr=0x1c1f, int_num=46)
-kmi0   = Pl050(pio_addr=0x1c06, int_num=44)
-kmi1   = Pl050(pio_addr=0x1c07, int_num=45, is_mouse=True)
+kmi0   = Pl050(pio_addr=0x1c06, int_num=44, ps2=PS2Keyboard())
+kmi1   = Pl050(pio_addr=0x1c07, int_num=45, ps2=PS2TouchKit())
 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
 io_shift = 2, ctrl_offset = 2, Command = 0x1,
 BAR0 = 0x1C1A, BAR0Size = '256B',
@@ -1136,8 +1137,8 @@

 uart0 = Pl011(pio_addr=0x1c09, int_num=37)

-kmi0 = Pl050(pio_addr=0x1c06, int_num=44)
-kmi1 = Pl050(pio_addr=0x1c07, int_num=45, is_mouse=True)
+kmi0 = Pl050(pio_addr=0x1c06, int_num=44, ps2=PS2Keyboard())
+kmi1 = Pl050(pio_addr=0x1c07, int_num=45, ps2=PS2TouchKit())

 rtc = PL031(pio_addr=0x1c17, int_num=36)

diff --git a/src/dev/arm/kmi.cc b/src/dev/arm/kmi.cc
index 8b373b8..d80bc14 100644
--- a/src/dev/arm/kmi.cc
+++ b/src/dev/arm/kmi.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2017 ARM Limited
+ * Copyright (c) 2010, 2017-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -48,21 +48,17 @@
 #include "debug/Pl050.hh"
 #include "dev/arm/amba_device.hh"
 #include "dev/ps2.hh"
+#include "dev/ps2/device.hh&qu

[gem5-dev] Change in gem5/gem5[master]: ps2: Unify constant names

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/9770 )


Change subject: ps2: Unify constant names
..

ps2: Unify constant names

Move ps2.hh to dev/ps2/types.hh and update the device models to
consistently use well-known constants from this header.

Change-Id: Iadfdc774495957beb82f3d341107b1e9232ffd4c
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9770
Reviewed-by: Gabe Black <gabebl...@google.com>
Maintainer: Gabe Black <gabebl...@google.com>
---
M src/dev/SConscript
M src/dev/arm/kmi.cc
M src/dev/ps2/SConscript
M src/dev/ps2/device.cc
M src/dev/ps2/keyboard.cc
M src/dev/ps2/keyboard.hh
M src/dev/ps2/mouse.cc
M src/dev/ps2/mouse.hh
M src/dev/ps2/touchkit.cc
M src/dev/ps2/touchkit.hh
R src/dev/ps2/types.cc
R src/dev/ps2/types.hh
12 files changed, 173 insertions(+), 186 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved



diff --git a/src/dev/SConscript b/src/dev/SConscript
index 6939e03..c9526c2 100644
--- a/src/dev/SConscript
+++ b/src/dev/SConscript
@@ -50,7 +50,6 @@
 Source('mc146818.cc')
 Source('pixelpump.cc')
 Source('platform.cc')
-Source('ps2.cc')

 DebugFlag('Intel8254Timer')
 DebugFlag('MC146818')
diff --git a/src/dev/arm/kmi.cc b/src/dev/arm/kmi.cc
index d80bc14..1636d5d 100644
--- a/src/dev/arm/kmi.cc
+++ b/src/dev/arm/kmi.cc
@@ -47,7 +47,6 @@
 #include "base/vnc/vncinput.hh"
 #include "debug/Pl050.hh"
 #include "dev/arm/amba_device.hh"
-#include "dev/ps2.hh"
 #include "dev/ps2/device.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
diff --git a/src/dev/ps2/SConscript b/src/dev/ps2/SConscript
index a73e47a..59bc242 100644
--- a/src/dev/ps2/SConscript
+++ b/src/dev/ps2/SConscript
@@ -47,5 +47,6 @@
 Source('keyboard.cc')
 Source('mouse.cc')
 Source('touchkit.cc')
+Source('types.cc')

 DebugFlag('PS2')
diff --git a/src/dev/ps2/device.cc b/src/dev/ps2/device.cc
index c4d33d5..eb13f81 100644
--- a/src/dev/ps2/device.cc
+++ b/src/dev/ps2/device.cc
@@ -45,7 +45,7 @@

 #include "base/logging.hh"
 #include "debug/PS2.hh"
-#include "dev/ps2.hh"
+#include "dev/ps2/types.hh"
 #include "params/PS2Device.hh"

 PS2Device::PS2Device(const PS2DeviceParams *p)
diff --git a/src/dev/ps2/keyboard.cc b/src/dev/ps2/keyboard.cc
index c9bc219..c7d5c1f 100644
--- a/src/dev/ps2/keyboard.cc
+++ b/src/dev/ps2/keyboard.cc
@@ -45,11 +45,9 @@

 #include "base/logging.hh"
 #include "debug/PS2.hh"
-#include "dev/ps2.hh"
+#include "dev/ps2/types.hh"
 #include "params/PS2Keyboard.hh"

-const uint8_t PS2Keyboard::ID[] = {0xab, 0x83};
-
 PS2Keyboard::PS2Keyboard(const PS2KeyboardParams *p)
 : PS2Device(p),
   shiftDown(false),
@@ -79,7 +77,36 @@
 PS2Keyboard::recv(const std::vector )
 {
 switch (data[0]) {
-  case LEDWrite:
+  case Ps2::ReadID:
+DPRINTF(PS2, "Got keyboard read ID command.\n");
+sendAck();
+send(Ps2::Keyboard::ID);
+return true;
+  case Ps2::Enable:
+DPRINTF(PS2, "Enabling the keyboard.\n");
+enabled = true;
+sendAck();
+return true;
+  case Ps2::Disable:
+DPRINTF(PS2, "Disabling the keyboard.\n");
+enabled = false;
+sendAck();
+return true;
+  case Ps2::DefaultsAndDisable:
+DPRINTF(PS2, "Disabling and resetting the keyboard.\n");
+enabled = false;
+sendAck();
+return true;
+  case Ps2::Reset:
+DPRINTF(PS2, "Resetting keyboard.\n");
+enabled = true;
+sendAck();
+send(Ps2::SelfTestPass);
+return true;
+  case Ps2::Resend:
+panic("Keyboard resend unimplemented.\n");
+
+  case Ps2::Keyboard::LEDWrite:
 if (data.size() == 1) {
 DPRINTF(PS2, "Got LED write command.\n");
 sendAck();
@@ -93,16 +120,11 @@
 sendAck();
 return true;
 }
-  case DiagnosticEcho:
+  case Ps2::Keyboard::DiagnosticEcho:
 panic("Keyboard diagnostic echo unimplemented.\n");
-  case AlternateScanCodes:
+  case Ps2::Keyboard::AlternateScanCodes:
 panic("Accessing alternate scan codes unimplemented.\n");
-  case ReadID:
-DPRINTF(PS2, "Got keyboard read ID command.\n");
-sendAck();
-send((uint8_t *), sizeof(ID));
-return true;
-  case TypematicInfo:
+  case Ps2::Keyboard::TypematicInfo:
 if (data.size() == 1) {
 DPRINTF(PS2, "Setting typematic info.\n");
  

[gem5-dev] Change in gem5/gem5[master]: ps2: Add proper touchscreen command handling

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/9768 )


Change subject: ps2: Add proper touchscreen command handling
..

ps2: Add proper touchscreen command handling

The touchscreen model used ad-hoc mechanisms to enable/disable the
device. Use standard PS/2 commands to activate/deactivate the
device. Add proper TouchKit command handling.

Change-Id: I0c5a2e2b47639f36ab3ee07e3e559f11afa54b9d
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9768
Reviewed-by: Gabe Black <gabebl...@google.com>
---
M src/dev/ps2/touchkit.cc
M src/dev/ps2/touchkit.hh
2 files changed, 82 insertions(+), 21 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/dev/ps2/touchkit.cc b/src/dev/ps2/touchkit.cc
index fd81c57..819b06c 100644
--- a/src/dev/ps2/touchkit.cc
+++ b/src/dev/ps2/touchkit.cc
@@ -54,7 +54,7 @@
 PS2TouchKit::PS2TouchKit(const PS2TouchKitParams *p)
 : PS2Device(p),
   vnc(p->vnc),
-  driverInitialized(false)
+  enabled(false), touchKitEnabled(false)
 {
 if (vnc)
 vnc->setMouse(this);
@@ -65,7 +65,8 @@
 {
 PS2Device::serialize(cp);

-SERIALIZE_SCALAR(driverInitialized);
+SERIALIZE_SCALAR(enabled);
+SERIALIZE_SCALAR(touchKitEnabled);
 }

 void
@@ -73,7 +74,8 @@
 {
 PS2Device::unserialize(cp);

-UNSERIALIZE_SCALAR(driverInitialized);
+UNSERIALIZE_SCALAR(enabled);
+UNSERIALIZE_SCALAR(touchKitEnabled);
 }

 bool
@@ -81,6 +83,9 @@
 {
 switch (data[0]) {
   case Ps2::Ps2Reset:
+DPRINTF(PS2, "Resetting device.\n");
+enabled = false;
+touchKitEnabled = false;
 sendAck();
 send(Ps2::SelfTestPass);
 return true;
@@ -107,9 +112,24 @@

   case Ps2::SetScaling1_1:
   case Ps2::SetScaling1_2:
+sendAck();
+return true;
+
   case Ps2::Disable:
+DPRINTF(PS2, "Disabling device.\n");
+enabled = false;
+sendAck();
+return true;
+
   case Ps2::Enable:
+DPRINTF(PS2, "Enabling device.\n");
+enabled = true;
+sendAck();
+return true;
+
   case Ps2::SetDefaults:
+DPRINTF(PS2, "Setting defaults and disabling device.\n");
+enabled = false;
 sendAck();
 return true;

@@ -121,25 +141,53 @@
 return true;

   case Ps2::TouchKitId:
-sendAck();
-if (data.size() == 1) {
-send(Ps2::TouchKitId);
-send(1);
-send('A');
-
-return false;
-} else if (data.size() == 3) {
-driverInitialized = true;
-return true;
-} else {
-return false;
-}
+return recvTouchKit(data);

   default:
-panic("Unknown byte received: %d\n", data[0]);
+panic("Unknown byte received: %#x\n", data[0]);
 }
 }

+bool
+PS2TouchKit::recvTouchKit(const std::vector )
+{
+// Ack all incoming bytes
+sendAck();
+
+// Packet format is: 0x0A SIZE CMD DATA
+assert(data[0] == Ps2::TouchKitId);
+if (data.size() < 3 || data.size() - 2 < data[1])
+return false;
+
+const uint8_t len = data[1];
+const uint8_t cmd = data[2];
+
+// We have received at least one TouchKit diagnostic
+// command. Enabled TouchKit reports.
+touchKitEnabled = true;
+
+
+switch (cmd) {
+  case TouchKitActive:
+warn_if(len != 1, "Unexpected activate packet length: %u\n", len);
+sendTouchKit('A');
+return true;
+
+  default:
+panic("Unimplemented touchscreen command: %#x\n", cmd);
+}
+}
+
+void
+PS2TouchKit::sendTouchKit(const uint8_t *data, size_t size)
+{
+send(Ps2::TouchKitId);
+send(size);
+for (int i = 0; i < size; ++i)
+send(data[i]);
+}
+
+
 void
 PS2TouchKit::mouseAt(uint16_t x, uint16_t y, uint8_t buttons)
 {
@@ -147,7 +195,7 @@
 // it anything. Similarly we can get vnc mouse events orders of  
magnitude
 // faster than m5 can process them. Only queue up two sets mouse  
movements

 // and don't add more until those are processed.
-if (!driverInitialized || sendPending() > 10)
+if (!enabled || !touchKitEnabled || sendPending() > 10)
 return;

 // Convert screen coordinates to touchpad coordinates
diff --git a/src/dev/ps2/touchkit.hh b/src/dev/ps2/touchkit.hh
index fa1bc52..dc98a78 100644
--- a/src/dev/ps2/touchkit.hh
+++ b/src/dev/ps2/touchkit.hh
@@ -50,6 +50,12 @@
   protected:
 static const uint8_t ID[];

+enum TKCommands {
+TouchKitActive = 'A',
+TouchKitFWRev = 'D',
+TouchKitCtrlType = 'E

[gem5-dev] Change in gem5/gem5[master]: ps2: Implement the keyboard reset command

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/9766 )


Change subject: ps2: Implement the keyboard reset command
..

ps2: Implement the keyboard reset command

Linux tries to reset the PS/2 keyboard at boot.

Change-Id: I727fbf6138b654885d82d85be9d964ee3d3365ef
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9766
Reviewed-by: Gabe Black <gabebl...@google.com>
Maintainer: Gabe Black <gabebl...@google.com>
---
M src/dev/ps2/keyboard.cc
1 file changed, 6 insertions(+), 2 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved



diff --git a/src/dev/ps2/keyboard.cc b/src/dev/ps2/keyboard.cc
index 1f8b544..c9bc219 100644
--- a/src/dev/ps2/keyboard.cc
+++ b/src/dev/ps2/keyboard.cc
@@ -127,6 +127,12 @@
 enabled = false;
 sendAck();
 return true;
+  case Reset:
+DPRINTF(PS2, "Resetting keyboard.\n");
+sendAck();
+enabled = true;
+send(Ps2::SelfTestPass);
+return true;
   case AllKeysToTypematic:
 panic("Setting all keys to typemantic unimplemented.\n");
   case AllKeysToMakeRelease:
@@ -144,8 +150,6 @@
 panic("Setting key to make only unimplemented.\n");
   case Resend:
 panic("Keyboard resend unimplemented.\n");
-  case Reset:
-panic("Keyboard reset unimplemented.\n");
   default:
 panic("Unknown keyboard command %#02x.\n", data[0]);
 }

--
To view, visit https://gem5-review.googlesource.com/9766
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I727fbf6138b654885d82d85be9d964ee3d3365ef
Gerrit-Change-Number: 9766
Gerrit-PatchSet: 5
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: ps2: Unify device data buffering

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/9765 )


Change subject: ps2: Unify device data buffering
..

ps2: Unify device data buffering

All PS/2 device currently implement various ad-hoc mechanisms to
handle multi-byte commands. This is error-prone and makes it hard to
implement new devices. Create a buffering mechanism in the base class
to avoid this.

Change-Id: If5638b0ab68decea8de7631ecead0a9ebad1547b
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9765
Reviewed-by: Gabe Black <gabebl...@google.com>
---
M src/dev/ps2/device.cc
M src/dev/ps2/device.hh
M src/dev/ps2/keyboard.cc
M src/dev/ps2/keyboard.hh
M src/dev/ps2/mouse.cc
M src/dev/ps2/mouse.hh
M src/dev/ps2/touchkit.cc
M src/dev/ps2/touchkit.hh
8 files changed, 111 insertions(+), 126 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/dev/ps2/device.cc b/src/dev/ps2/device.cc
index deedb49..c4d33d5 100644
--- a/src/dev/ps2/device.cc
+++ b/src/dev/ps2/device.cc
@@ -44,12 +44,14 @@
 #include "dev/ps2/device.hh"

 #include "base/logging.hh"
+#include "debug/PS2.hh"
 #include "dev/ps2.hh"
 #include "params/PS2Device.hh"

 PS2Device::PS2Device(const PS2DeviceParams *p)
 : SimObject(p)
 {
+inBuffer.reserve(16);
 }

 void
@@ -58,6 +60,8 @@
 std::vector buffer(outBuffer.size());
 std::copy(outBuffer.begin(), outBuffer.end(), buffer.begin());
 arrayParamOut(cp, "outBuffer", buffer);
+
+SERIALIZE_CONTAINER(inBuffer);
 }

 void
@@ -67,6 +71,8 @@
 arrayParamIn(cp, "outBuffer", buffer);
 for (auto c : buffer)
 outBuffer.push_back(c);
+
+UNSERIALIZE_CONTAINER(inBuffer);
 }

 void
@@ -90,7 +96,10 @@
 void
 PS2Device::hostWrite(uint8_t c)
 {
-recv(c);
+DPRINTF(PS2, "PS2: Host -> device: %#x\n", c);
+inBuffer.push_back(c);
+if (recv(inBuffer))
+inBuffer.clear();
 }

 void
@@ -98,6 +107,7 @@
 {
 assert(data || size == 0);
 while (size) {
+DPRINTF(PS2, "PS2: Device -> host: %#x\n", *data);
 outBuffer.push_back(*(data++));
 size--;
 }
diff --git a/src/dev/ps2/device.hh b/src/dev/ps2/device.hh
index 5252ac8..0ff31d4 100644
--- a/src/dev/ps2/device.hh
+++ b/src/dev/ps2/device.hh
@@ -45,6 +45,7 @@
 #define __DEV_PS2_DEVICE_HH__

 #include 
+#include 

 #include "sim/sim_object.hh"

@@ -92,8 +93,18 @@
   protected: /* Device interface */
 /**
  * Data received from host.
+ *
+ * Data sent to the device is buffered one byte at a time. Each
+ * time a byte is added, this function is called and passed the
+ * current buffer. It should return true if it has consumed the
+ * data and the buffer can be cleared, or false if more data is
+ * needed to process the current command.
+ *
+ * @param data Pending input data (at least one byte)
+ * @return false if more data is needed to process the current
+ * command, true otherwise.
  */
-virtual void recv(uint8_t data) = 0;
+virtual bool recv(const std::vector ) = 0;

 /**
  * Send data from a PS/2 device to a host
@@ -128,6 +139,9 @@
 /** Device -> host FIFO */
 std::deque outBuffer;

+/** Host -> device buffer */
+std::vector inBuffer;
+
 std::function<void()> dataAvailableCallback;
 };

diff --git a/src/dev/ps2/keyboard.cc b/src/dev/ps2/keyboard.cc
index 46b89fa..1f8b544 100644
--- a/src/dev/ps2/keyboard.cc
+++ b/src/dev/ps2/keyboard.cc
@@ -52,7 +52,6 @@

 PS2Keyboard::PS2Keyboard(const PS2KeyboardParams *p)
 : PS2Device(p),
-  lastCommand(NoCommand),
   shiftDown(false),
   enabled(false)
 {
@@ -64,7 +63,6 @@
 PS2Keyboard::serialize(CheckpointOut ) const
 {
 PS2Device::serialize(cp);
-SERIALIZE_SCALAR(lastCommand);
 SERIALIZE_SCALAR(shiftDown);
 SERIALIZE_SCALAR(enabled);
 }
@@ -73,40 +71,28 @@
 PS2Keyboard::unserialize(CheckpointIn )
 {
 PS2Device::unserialize(cp);
-UNSERIALIZE_SCALAR(lastCommand);
 UNSERIALIZE_SCALAR(shiftDown);
 UNSERIALIZE_SCALAR(enabled);
 }

-void
-PS2Keyboard::recv(uint8_t data)
+bool
+PS2Keyboard::recv(const std::vector )
 {
-if (lastCommand != NoCommand) {
-switch (lastCommand) {
-  case LEDWrite:
+switch (data[0]) {
+  case LEDWrite:
+if (data.size() == 1) {
+DPRINTF(PS2, "Got LED write command.\n");
+sendAck();
+return false;
+} else {
 DPRINTF(PS2, "Setting LEDs: "
 "caps lock %s, num lock %s, scroll lock %s\n",
-bits(data, 2) ? &q

[gem5-dev] Change in gem5/gem5[master]: ps2: Unify device data buffering

[Andreas Sandberg (Gerrit)]

Hello Gabe Black, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/9765

to look at the new patch set (#4).

Change subject: ps2: Unify device data buffering
..

ps2: Unify device data buffering

All PS/2 device currently implement various ad-hoc mechanisms to
handle multi-byte commands. This is error-prone and makes it hard to
implement new devices. Create a buffering mechanism in the base class
to avoid this.

Change-Id: If5638b0ab68decea8de7631ecead0a9ebad1547b
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/ps2/device.cc
M src/dev/ps2/device.hh
M src/dev/ps2/keyboard.cc
M src/dev/ps2/keyboard.hh
M src/dev/ps2/mouse.cc
M src/dev/ps2/mouse.hh
M src/dev/ps2/touchkit.cc
M src/dev/ps2/touchkit.hh
8 files changed, 111 insertions(+), 126 deletions(-)


--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: If5638b0ab68decea8de7631ecead0a9ebad1547b
Gerrit-Change-Number: 9765
Gerrit-PatchSet: 4
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newpatchset
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[gem5-dev] Change in gem5/gem5[master]: ps2: Factor out PS/2 devices into their own subsystem

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/9762 )


Change subject: ps2: Factor out PS/2 devices into their own subsystem
..

ps2: Factor out PS/2 devices into their own subsystem

PS/2 devices are currently emulated both in the i8042 model and the
Arm KMI model. This is undesirable since it leads to code duplication.

This change introduces a common PS/2 device interface and factor out
the x86 keyboard and mouse model. A subsequent commit will implement
support for this interface in the Arm KMI model.

Change-Id: I440e83517fd9dce362fdc1676db477cc6eee5211
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9762
Reviewed-by: Gabe Black <gabebl...@google.com>
Maintainer: Gabe Black <gabebl...@google.com>
---
M src/dev/ps2.hh
A src/dev/ps2/PS2.py
A src/dev/ps2/SConscript
A src/dev/ps2/device.cc
A src/dev/ps2/device.hh
A src/dev/ps2/keyboard.cc
A src/dev/ps2/keyboard.hh
A src/dev/ps2/mouse.cc
A src/dev/ps2/mouse.hh
M src/dev/x86/I8042.py
M src/dev/x86/i8042.cc
M src/dev/x86/i8042.hh
12 files changed, 912 insertions(+), 382 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved



diff --git a/src/dev/ps2.hh b/src/dev/ps2.hh
index 9e99867..7b57835 100644
--- a/src/dev/ps2.hh
+++ b/src/dev/ps2.hh
@@ -61,6 +61,7 @@
 ReadId  = 0xf2,
 TpReadId= 0xe1,
 Ack = 0xfa,
+Resend  = 0xfe,
 SetRate = 0xf3,
 Enable  = 0xf4,
 Disable = 0xf5,
diff --git a/src/dev/ps2/PS2.py b/src/dev/ps2/PS2.py
new file mode 100644
index 000..5db3b6e
--- /dev/null
+++ b/src/dev/ps2/PS2.py
@@ -0,0 +1,53 @@
+# Copyright (c) 2017-2018 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
+
+class PS2Device(SimObject):
+type = 'PS2Device'
+cxx_header = "dev/ps2/device.hh"
+abstract = True
+
+class PS2Keyboard(PS2Device):
+type = 'PS2Keyboard'
+cxx_header = "dev/ps2/keyboard.hh"
+
+class PS2Mouse(PS2Device):
+type = 'PS2Mouse'
+cxx_header = "dev/ps2/mouse.hh"
diff --git a/src/dev/ps2/SConscript b/src/dev/ps2/SConscript
new file mode 100644
index 000..acce7be
--- /dev/null
+++ b/src/dev/ps2/SConscript
@@ -0,0 +1,50 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2017-2018 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the s

[gem5-dev] Change in gem5/gem5[master]: ps2: Add VNC support to the keyboard model

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/9763 )


Change subject: ps2: Add VNC support to the keyboard model
..

ps2: Add VNC support to the keyboard model

Add support for keyboard input from the VNC server in the PS/2
keyboard model. The introduced code is based on the functionality in
the Arm PL050 KMI model.

Change-Id: If04a9713e5a15e2149d1a7471b999e3060d8ee7d
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9763
Reviewed-by: Gabe Black <gabebl...@google.com>
Maintainer: Gabe Black <gabebl...@google.com>
---
M src/dev/ps2/PS2.py
M src/dev/ps2/keyboard.cc
M src/dev/ps2/keyboard.hh
M src/dev/x86/I8042.py
4 files changed, 48 insertions(+), 3 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved



diff --git a/src/dev/ps2/PS2.py b/src/dev/ps2/PS2.py
index 5db3b6e..fcbbc28 100644
--- a/src/dev/ps2/PS2.py
+++ b/src/dev/ps2/PS2.py
@@ -48,6 +48,8 @@
 type = 'PS2Keyboard'
 cxx_header = "dev/ps2/keyboard.hh"

+vnc = Param.VncInput(Parent.any, "VNC server providing keyboard input")
+
 class PS2Mouse(PS2Device):
 type = 'PS2Mouse'
 cxx_header = "dev/ps2/mouse.hh"
diff --git a/src/dev/ps2/keyboard.cc b/src/dev/ps2/keyboard.cc
index a942d34..46b89fa 100644
--- a/src/dev/ps2/keyboard.cc
+++ b/src/dev/ps2/keyboard.cc
@@ -45,14 +45,19 @@

 #include "base/logging.hh"
 #include "debug/PS2.hh"
+#include "dev/ps2.hh"
 #include "params/PS2Keyboard.hh"

 const uint8_t PS2Keyboard::ID[] = {0xab, 0x83};

 PS2Keyboard::PS2Keyboard(const PS2KeyboardParams *p)
 : PS2Device(p),
-  lastCommand(NoCommand)
+  lastCommand(NoCommand),
+  shiftDown(false),
+  enabled(false)
 {
+if (p->vnc)
+p->vnc->setKeyboard(this);
 }

 void
@@ -60,6 +65,8 @@
 {
 PS2Device::serialize(cp);
 SERIALIZE_SCALAR(lastCommand);
+SERIALIZE_SCALAR(shiftDown);
+SERIALIZE_SCALAR(enabled);
 }

 void
@@ -67,6 +74,8 @@
 {
 PS2Device::unserialize(cp);
 UNSERIALIZE_SCALAR(lastCommand);
+UNSERIALIZE_SCALAR(shiftDown);
+UNSERIALIZE_SCALAR(enabled);
 }

 void
@@ -114,14 +123,17 @@
 break;
   case Enable:
 DPRINTF(PS2, "Enabling the keyboard.\n");
+enabled = true;
 sendAck();
 break;
   case Disable:
 DPRINTF(PS2, "Disabling the keyboard.\n");
+enabled = false;
 sendAck();
 break;
   case DefaultsAndDisable:
 DPRINTF(PS2, "Disabling and resetting the keyboard.\n");
+enabled = false;
 sendAck();
 break;
   case AllKeysToTypematic:
@@ -148,6 +160,27 @@
 }
 }

+void
+PS2Keyboard::keyPress(uint32_t key, bool down)
+{
+std::list keys;
+
+// convert the X11 keysym into ps2 codes and update the shift
+// state (shiftDown)
+Ps2::keySymToPs2(key, down, shiftDown, keys);
+
+// Drop key presses if the keyboard hasn't been enabled by the
+// host. We do that after translating the key code to ensure that
+// we keep track of the shift state.
+if (!enabled)
+return;
+
+// Insert into our queue of characters
+for (uint8_t c : keys)
+send(c);
+}
+
+
 PS2Keyboard *
 PS2KeyboardParams::create()
 {
diff --git a/src/dev/ps2/keyboard.hh b/src/dev/ps2/keyboard.hh
index 8943e7f..f5d8304 100644
--- a/src/dev/ps2/keyboard.hh
+++ b/src/dev/ps2/keyboard.hh
@@ -44,11 +44,12 @@
 #ifndef __DEV_PS2_KEYBOARD_HH__
 #define __DEV_PS2_KEYBOARD_HH__

+#include "base/vnc/vncinput.hh"
 #include "dev/ps2/device.hh"

 struct PS2KeyboardParams;

-class PS2Keyboard : public PS2Device
+class PS2Keyboard : public PS2Device, VncKeyboard
 {
   protected:
 static const uint8_t ID[];
@@ -78,6 +79,12 @@

 uint16_t lastCommand;

+/** is the shift key currently down */
+bool shiftDown;
+
+/** Is the device enabled? */
+bool enabled;
+
   public:
 PS2Keyboard(const PS2KeyboardParams *p);

@@ -86,6 +93,9 @@

   protected: // PS2Device
 void recv(uint8_t data) override;
+
+  public: // VncKeyboard
+void keyPress(uint32_t key, bool down) override;
 };

 #endif // __DEV_PS2_KEYBOARD_hH__
diff --git a/src/dev/x86/I8042.py b/src/dev/x86/I8042.py
index 9203f40..43e70d6 100644
--- a/src/dev/x86/I8042.py
+++ b/src/dev/x86/I8042.py
@@ -45,5 +45,5 @@
 keyboard_int_pin = Param.X86IntSourcePin(X86IntSourcePin(),
 'Pin to signal the keyboard has data')

-keyboard = Param.PS2Device(PS2Keyboard(), "PS/2 keyboard device")
+keyboard = Param.PS2Device(PS2Keyboard(vnc=NULL), "PS/2 keyboard  
device")

 mouse = Param.PS2Device(PS2Mouse(), "PS/2 mouse devi

[gem5-dev] Change in gem5/gem5[master]: ps2: Add a simple touchscreen model

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/9764 )


Change subject: ps2: Add a simple touchscreen model
..

ps2: Add a simple touchscreen model

Add a touchscreen model that is compatible with Linux's TouchKit
driver. This model is based on the model in the Arm PL050 KMI model.

Change-Id: Id4d88a21a26bb42c455e4d778cd89875f650ac57
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9764
Reviewed-by: Gabe Black <gabebl...@google.com>
Maintainer: Gabe Black <gabebl...@google.com>
---
M src/dev/ps2/PS2.py
M src/dev/ps2/SConscript
A src/dev/ps2/touchkit.cc
A src/dev/ps2/touchkit.hh
4 files changed, 266 insertions(+), 0 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved



diff --git a/src/dev/ps2/PS2.py b/src/dev/ps2/PS2.py
index fcbbc28..55b37f2 100644
--- a/src/dev/ps2/PS2.py
+++ b/src/dev/ps2/PS2.py
@@ -53,3 +53,9 @@
 class PS2Mouse(PS2Device):
 type = 'PS2Mouse'
 cxx_header = "dev/ps2/mouse.hh"
+
+class PS2TouchKit(PS2Device):
+type = 'PS2TouchKit'
+cxx_header = "dev/ps2/touchkit.hh"
+
+vnc = Param.VncInput(Parent.any, "VNC server providing mouse input")
diff --git a/src/dev/ps2/SConscript b/src/dev/ps2/SConscript
index acce7be..a73e47a 100644
--- a/src/dev/ps2/SConscript
+++ b/src/dev/ps2/SConscript
@@ -46,5 +46,6 @@
 Source('device.cc')
 Source('keyboard.cc')
 Source('mouse.cc')
+Source('touchkit.cc')

 DebugFlag('PS2')
diff --git a/src/dev/ps2/touchkit.cc b/src/dev/ps2/touchkit.cc
new file mode 100644
index 000..96dd2e9
--- /dev/null
+++ b/src/dev/ps2/touchkit.cc
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2010, 2017-2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *  William Wang
+ *  Andreas Sandberg
+ */
+
+#include "dev/ps2/touchkit.hh"
+
+#include "base/logging.hh"
+#include "debug/PS2.hh"
+#include "dev/ps2.hh"
+#include "params/PS2TouchKit.hh"
+
+const uint8_t PS2TouchKit::ID[] = {0x00};
+
+PS2TouchKit::PS2TouchKit(const PS2TouchKitParams *p)
+: PS2Device(p),
+  vnc(p->vnc),
+  ackNext(false),
+  driverInitialized(false)
+{
+if (vnc)
+vnc->setMouse(this);
+}
+
+void
+PS2TouchKit::serialize(CheckpointOut ) const
+{
+PS2Device::serialize(cp);
+
+SERIALIZE_SCALAR(ackNext);
+SERIALIZE_SCALAR(driverInitialized);
+}
+
+void
+PS2TouchKit::unserialize(CheckpointIn )
+{
+PS2Device::unserialize(cp);
+
+UNSERIALIZE_SCALAR(ackNext);
+UNSERIALIZE_SCALAR(dri

[gem5-dev] Change in gem5/gem5[master]: mem: Add a helper function to get a word of variable length

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/9761 )


Change subject: mem: Add a helper function to get a word of variable length
..

mem: Add a helper function to get a word of variable length

There are many devices that need to handle reads/writes of different
word sizes. A common pattern is a switch statement that check for the
size of a packet and then calls the corresponding
Packet::(get|set) methods. Simplify this by implementing
Packet::(get|set)UintX helper functions.

The getter reads a word of the size specified in the packet and the
specified endianness. The word is then zero-extended to 64
bits. Conversely, the setter truncates the word down to the size
required in the packet and then byte-swaps it to the desired
endianness.

Change-Id: I2f0c27fe3903abf3859bea13b07c7f5f0fb0809f
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9761
Maintainer: Nikos Nikoleris <nikos.nikole...@arm.com>
---
M src/mem/packet.cc
M src/mem/packet.hh
2 files changed, 56 insertions(+), 2 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved



diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index ffda3d5..7a81cdb 100644
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2017 ARM Limited
+ * Copyright (c) 2011-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -56,6 +56,7 @@
 #include "base/cprintf.hh"
 #include "base/logging.hh"
 #include "base/trace.hh"
+#include "mem/packet_access.hh"

 using namespace std;

@@ -364,6 +365,45 @@
 return sender_state;
 }

+uint64_t
+Packet::getUintX(ByteOrder endian) const
+{
+switch(getSize()) {
+  case 1:
+return (uint64_t)get(endian);
+  case 2:
+return (uint64_t)get(endian);
+  case 4:
+return (uint64_t)get(endian);
+  case 8:
+return (uint64_t)get(endian);
+  default:
+panic("%i isn't a supported word size.\n", getSize());
+}
+}
+
+void
+Packet::setUintX(uint64_t w, ByteOrder endian)
+{
+switch(getSize()) {
+  case 1:
+set((uint8_t)w, endian);
+break;
+  case 2:
+set((uint16_t)w, endian);
+break;
+  case 4:
+set((uint32_t)w, endian);
+break;
+  case 8:
+set((uint64_t)w, endian);
+break;
+  default:
+panic("%i isn't a supported word size.\n", getSize());
+}
+
+}
+
 void
 Packet::print(ostream , const int verbosity, const string ) const
 {
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index b5b882c..a4eeabe 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2017 ARM Limited
+ * Copyright (c) 2012-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -1068,6 +1068,20 @@
 template 
 void set(T v);

+
+/**
+ * Get the data in the packet byte swapped from the specified
+ * endianness and zero-extended to 64 bits.
+ */
+uint64_t getUintX(ByteOrder endian) const;
+
+/**
+ * Set the value in the word w after truncating it to the length
+ * of the packet and then byteswapping it to the desired
+ * endianness.
+ */
+void setUintX(uint64_t w, ByteOrder endian);
+
 /**
  * Copy data into the packet from the provided pointer.
  */

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I2f0c27fe3903abf3859bea13b07c7f5f0fb0809f
Gerrit-Change-Number: 9761
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: ps2: Add a simple touchscreen model

[Andreas Sandberg (Gerrit)]

Hello Gabe Black, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/9764

to look at the new patch set (#4).

Change subject: ps2: Add a simple touchscreen model
..

ps2: Add a simple touchscreen model

Add a touchscreen model that is compatible with Linux's TouchKit
driver. This model is based on the model in the Arm PL050 KMI model.

Change-Id: Id4d88a21a26bb42c455e4d778cd89875f650ac57
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/ps2/PS2.py
M src/dev/ps2/SConscript
A src/dev/ps2/touchkit.cc
A src/dev/ps2/touchkit.hh
4 files changed, 266 insertions(+), 0 deletions(-)


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Gerrit-Change-Id: Id4d88a21a26bb42c455e4d778cd89875f650ac57
Gerrit-Change-Number: 9764
Gerrit-PatchSet: 4
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
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[gem5-dev] Change in gem5/gem5[master]: ps2: Unify device data buffering

[Andreas Sandberg (Gerrit)]

Hello Gabe Black, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/9765

to look at the new patch set (#3).

Change subject: ps2: Unify device data buffering
..

ps2: Unify device data buffering

All PS/2 device currently implement various ad-hoc mechanisms to
handle multi-byte commands. This is error-prone and makes it hard to
implement new devices. Create a buffering mechanism in the base class
to avoid this.

Change-Id: If5638b0ab68decea8de7631ecead0a9ebad1547b
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/ps2/device.cc
M src/dev/ps2/device.hh
M src/dev/ps2/keyboard.cc
M src/dev/ps2/keyboard.hh
M src/dev/ps2/mouse.cc
M src/dev/ps2/mouse.hh
M src/dev/ps2/touchkit.cc
M src/dev/ps2/touchkit.hh
8 files changed, 111 insertions(+), 126 deletions(-)


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Gerrit-Change-Id: If5638b0ab68decea8de7631ecead0a9ebad1547b
Gerrit-Change-Number: 9765
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
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[gem5-dev] Change in gem5/gem5[master]: ps2: Add proper touchscreen command handling

[Andreas Sandberg (Gerrit)]

Hello Gabe Black, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/9768

to look at the new patch set (#3).

Change subject: ps2: Add proper touchscreen command handling
..

ps2: Add proper touchscreen command handling

The touchscreen model used ad-hoc mechanisms to enable/disable the
device. Use standard PS/2 commands to activate/deactivate the
device. Add proper TouchKit command handling.

Change-Id: I0c5a2e2b47639f36ab3ee07e3e559f11afa54b9d
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/ps2/touchkit.cc
M src/dev/ps2/touchkit.hh
2 files changed, 82 insertions(+), 21 deletions(-)


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Gerrit-Change-Id: I0c5a2e2b47639f36ab3ee07e3e559f11afa54b9d
Gerrit-Change-Number: 9768
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
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[gem5-dev] Change in gem5/gem5[master]: ps2: Add VNC support to the keyboard model

[Andreas Sandberg (Gerrit)]

Hello Gabe Black, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/9763

to look at the new patch set (#3).

Change subject: ps2: Add VNC support to the keyboard model
..

ps2: Add VNC support to the keyboard model

Add support for keyboard input from the VNC server in the PS/2
keyboard model. The introduced code is based on the functionality in
the Arm PL050 KMI model.

Change-Id: If04a9713e5a15e2149d1a7471b999e3060d8ee7d
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/ps2/PS2.py
M src/dev/ps2/keyboard.cc
M src/dev/ps2/keyboard.hh
M src/dev/x86/I8042.py
4 files changed, 48 insertions(+), 3 deletions(-)


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Gerrit-Change-Id: If04a9713e5a15e2149d1a7471b999e3060d8ee7d
Gerrit-Change-Number: 9763
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
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[gem5-dev] Change in gem5/gem5[master]: ps2: Unify constant names

[Andreas Sandberg (Gerrit)]

Hello Gabe Black, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/9770

to look at the new patch set (#3).

Change subject: ps2: Unify constant names
..

ps2: Unify constant names

Move ps2.hh to dev/ps2/types.hh and update the device models to
consistently use well-known constants from this header.

Change-Id: Iadfdc774495957beb82f3d341107b1e9232ffd4c
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/SConscript
M src/dev/arm/kmi.cc
M src/dev/ps2/SConscript
M src/dev/ps2/device.cc
M src/dev/ps2/keyboard.cc
M src/dev/ps2/keyboard.hh
M src/dev/ps2/mouse.cc
M src/dev/ps2/mouse.hh
M src/dev/ps2/touchkit.cc
M src/dev/ps2/touchkit.hh
R src/dev/ps2/types.cc
R src/dev/ps2/types.hh
12 files changed, 173 insertions(+), 186 deletions(-)


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Gerrit-Change-Number: 9770
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
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[gem5-dev] Change in gem5/gem5[master]: ps2: Factor out PS/2 devices into their own subsystem

[Andreas Sandberg (Gerrit)]

Hello Gabe Black, Jason Lowe-Power, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/9762

to look at the new patch set (#2).

Change subject: ps2: Factor out PS/2 devices into their own subsystem
..

ps2: Factor out PS/2 devices into their own subsystem

PS/2 devices are currently emulated both in the i8042 model and the
Arm KMI model. This is undesirable since it leads to code duplication.

This change introduces a common PS/2 device interface and factor out
the x86 keyboard and mouse model. A subsequent commit will implement
support for this interface in the Arm KMI model.

Change-Id: I440e83517fd9dce362fdc1676db477cc6eee5211
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/ps2.hh
A src/dev/ps2/PS2.py
A src/dev/ps2/SConscript
A src/dev/ps2/device.cc
A src/dev/ps2/device.hh
A src/dev/ps2/keyboard.cc
A src/dev/ps2/keyboard.hh
A src/dev/ps2/mouse.cc
A src/dev/ps2/mouse.hh
M src/dev/x86/I8042.py
M src/dev/x86/i8042.cc
M src/dev/x86/i8042.hh
12 files changed, 912 insertions(+), 382 deletions(-)


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Gerrit-Change-Number: 9762
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
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[gem5-dev] Change in gem5/gem5[master]: ps2: Add a simple touchscreen model

[Andreas Sandberg (Gerrit)]

Hello Gabe Black, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/9764

to look at the new patch set (#3).

Change subject: ps2: Add a simple touchscreen model
..

ps2: Add a simple touchscreen model

Add a touchscreen model that is compatible with Linux's TouchKit
driver. This model is based on the model in the Arm PL050 KMI model.

Change-Id: Id4d88a21a26bb42c455e4d778cd89875f650ac57
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/dev/ps2/PS2.py
M src/dev/ps2/SConscript
A src/dev/ps2/touchkit.cc
A src/dev/ps2/touchkit.hh
4 files changed, 266 insertions(+), 0 deletions(-)


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Gerrit-Change-Number: 9764
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
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[gem5-dev] Change in gem5/gem5[master]: ps2: Implement the keyboard reset command

[Andreas Sandberg (Gerrit)]

Hello Gabe Black, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/9766

to look at the new patch set (#3).

Change subject: ps2: Implement the keyboard reset command
..

ps2: Implement the keyboard reset command

Linux tries to reset the PS/2 keyboard at boot.

Change-Id: I727fbf6138b654885d82d85be9d964ee3d3365ef
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/ps2/keyboard.cc
1 file changed, 6 insertions(+), 2 deletions(-)


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Gerrit-Change-Id: I727fbf6138b654885d82d85be9d964ee3d3365ef
Gerrit-Change-Number: 9766
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
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[gem5-dev] Change in gem5/gem5[master]: dev, arm: Cleanup Pl050 interrupt handling

[Andreas Sandberg (Gerrit)]

Hello Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/9769

to look at the new patch set (#3).

Change subject: dev, arm: Cleanup Pl050 interrupt handling
..

dev, arm: Cleanup Pl050 interrupt handling

Add support for TX interrupts and cleanup existing RX interrupt
handling.

Change-Id: If2e5b0c0cc6fbeb2dce09e7e9d935647516b2c47
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/arm/RealView.py
M src/dev/arm/kmi.cc
M src/dev/arm/kmi.hh
3 files changed, 71 insertions(+), 77 deletions(-)


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Gerrit-Change-Number: 9769
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
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[gem5-dev] Change in gem5/gem5[master]: ps2: Add VNC support to the keyboard model

[Andreas Sandberg (Gerrit)]

Hello Gabe Black, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/9763

to look at the new patch set (#2).

Change subject: ps2: Add VNC support to the keyboard model
..

ps2: Add VNC support to the keyboard model

Add support for keyboard input from the VNC server in the PS/2
keyboard model. The introduced code is based on the functionality in
the Arm PL050 KMI model.

Change-Id: If04a9713e5a15e2149d1a7471b999e3060d8ee7d
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/ps2/PS2.py
M src/dev/ps2/keyboard.cc
M src/dev/ps2/keyboard.hh
M src/dev/x86/I8042.py
4 files changed, 48 insertions(+), 3 deletions(-)


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Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
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[gem5-dev] Change in gem5/gem5[master]: dev, arm: Use the PS/2 framework in the Pl050 model

[Andreas Sandberg (Gerrit)]

Hello Giacomo Travaglini,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/9767

to review the following change.


Change subject: dev, arm: Use the PS/2 framework in the Pl050 model
..

dev, arm: Use the PS/2 framework in the Pl050 model

The Pl050 KMI model currently has its own keyboard and mouse
models. Use the generic PS/2 interface instead.

Change-Id: I6523d26f8e38bcc8ba399d4d1a131723645d36c7
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/arm/RealView.py
M src/dev/arm/kmi.cc
M src/dev/arm/kmi.hh
3 files changed, 51 insertions(+), 205 deletions(-)



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index a59e171..7661db1 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -62,6 +62,7 @@
 from SubSystem import SubSystem
 from Graphics import ImageFormat
 from ClockedObject import ClockedObject
+from PS2 import *

 # Platforms with KVM support should generally use in-kernel GIC
 # emulation. Use a GIC model that automatically switches between
@@ -465,11 +466,11 @@
 class Pl050(AmbaIntDevice):
 type = 'Pl050'
 cxx_header = "dev/arm/kmi.hh"
-vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer  
display")
-is_mouse = Param.Bool(False, "Is this interface a mouse, if not a  
keyboard")

 int_delay = '1us'
 amba_id = 0x00141050

+ps2 = Param.PS2Device("PS/2 device")
+
 def generateDeviceTree(self, state):
 node = self.generateBasicPioDeviceNode(state, 'kmi', self.pio_addr,
0x1000, [int(self.int_num)])
@@ -624,8 +625,8 @@
 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30,
 pio_addr=0x1f000600)
 clcd = Pl111(pio_addr=0x1002, int_num=55)
-kmi0   = Pl050(pio_addr=0x10006000, int_num=52)
-kmi1   = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
+kmi0   = Pl050(pio_addr=0x10006000, int_num=52, ps2=PS2Keyboard())
+kmi1   = Pl050(pio_addr=0x10007000, int_num=53, ps2=PS2TouchKit())
 a9scu  = A9SCU(pio_addr=0x1f00)
 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
 io_shift = 1, ctrl_offset = 2, Command = 0x1,
@@ -753,8 +754,8 @@
 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
 clcd   = Pl111(pio_addr=0x1002, int_num=23)
-kmi0   = Pl050(pio_addr=0x10006000, int_num=20)
-kmi1   = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
+kmi0   = Pl050(pio_addr=0x10006000, int_num=20, ps2=PS2Keyboard())
+kmi1   = Pl050(pio_addr=0x10007000, int_num=21, ps2=PS2TouchKit())

 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff,  
warn_access="1")

 flash_fake= IsaFake(pio_addr=0x4000, pio_size=0x2000-1,
@@ -904,8 +905,8 @@
 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C11,  
clock0='1MHz', clock1='1MHz')
 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C12,  
clock0='1MHz', clock1='1MHz')

 clcd   = Pl111(pio_addr=0x1c1f, int_num=46)
-kmi0   = Pl050(pio_addr=0x1c06, int_num=44)
-kmi1   = Pl050(pio_addr=0x1c07, int_num=45, is_mouse=True)
+kmi0   = Pl050(pio_addr=0x1c06, int_num=44, ps2=PS2Keyboard())
+kmi1   = Pl050(pio_addr=0x1c07, int_num=45, ps2=PS2TouchKit())
 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
 io_shift = 2, ctrl_offset = 2, Command = 0x1,
 BAR0 = 0x1C1A, BAR0Size = '256B',
@@ -1136,8 +1137,8 @@

 uart0 = Pl011(pio_addr=0x1c09, int_num=37)

-kmi0 = Pl050(pio_addr=0x1c06, int_num=44)
-kmi1 = Pl050(pio_addr=0x1c07, int_num=45, is_mouse=True)
+kmi0 = Pl050(pio_addr=0x1c06, int_num=44, ps2=PS2Keyboard())
+kmi1 = Pl050(pio_addr=0x1c07, int_num=45, ps2=PS2TouchKit())

 rtc = PL031(pio_addr=0x1c17, int_num=36)

diff --git a/src/dev/arm/kmi.cc b/src/dev/arm/kmi.cc
index 8b373b8..d80bc14 100644
--- a/src/dev/arm/kmi.cc
+++ b/src/dev/arm/kmi.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2017 ARM Limited
+ * Copyright (c) 2010, 2017-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -48,21 +48,17 @@
 #include "debug/Pl050.hh"
 #include "dev/arm/amba_device.hh"
 #include "dev/ps2.hh"
+#include "dev/ps2/device.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"

-Pl050::Pl050(const Params *p)
+Pl050::Pl050(const Pl050Params *p)
 : AmbaIntDevice(p, 0xfff), control(0), status(0x43), clkdiv(0)

[gem5-dev] Change in gem5/gem5[master]: mem: Add a helper function to get a word of variable length

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/9761

to review the following change.


Change subject: mem: Add a helper function to get a word of variable length
..

mem: Add a helper function to get a word of variable length

There are many devices that need to handle reads/writes of different
word sizes. A common pattern is a switch statement that check for the
size of a packet and then calls the corresponding
Packet::(get|set) methods. Simplify this by implementing
Packet::(get|set)UintX helper functions.

The getter reads a word of the size specified in the packet and the
specified endianness. The word is then zero-extended to 64
bits. Conversely, the setter truncates the word down to the size
required in the packet and then byte-swaps it to the desired
endianness.

Change-Id: I2f0c27fe3903abf3859bea13b07c7f5f0fb0809f
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
---
M src/mem/packet.cc
M src/mem/packet.hh
2 files changed, 56 insertions(+), 2 deletions(-)



diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index ffda3d5..7a81cdb 100644
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2017 ARM Limited
+ * Copyright (c) 2011-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -56,6 +56,7 @@
 #include "base/cprintf.hh"
 #include "base/logging.hh"
 #include "base/trace.hh"
+#include "mem/packet_access.hh"

 using namespace std;

@@ -364,6 +365,45 @@
 return sender_state;
 }

+uint64_t
+Packet::getUintX(ByteOrder endian) const
+{
+switch(getSize()) {
+  case 1:
+return (uint64_t)get(endian);
+  case 2:
+return (uint64_t)get(endian);
+  case 4:
+return (uint64_t)get(endian);
+  case 8:
+return (uint64_t)get(endian);
+  default:
+panic("%i isn't a supported word size.\n", getSize());
+}
+}
+
+void
+Packet::setUintX(uint64_t w, ByteOrder endian)
+{
+switch(getSize()) {
+  case 1:
+set((uint8_t)w, endian);
+break;
+  case 2:
+set((uint16_t)w, endian);
+break;
+  case 4:
+set((uint32_t)w, endian);
+break;
+  case 8:
+set((uint64_t)w, endian);
+break;
+  default:
+panic("%i isn't a supported word size.\n", getSize());
+}
+
+}
+
 void
 Packet::print(ostream , const int verbosity, const string ) const
 {
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index b5b882c..a4eeabe 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2017 ARM Limited
+ * Copyright (c) 2012-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -1068,6 +1068,20 @@
 template 
 void set(T v);

+
+/**
+ * Get the data in the packet byte swapped from the specified
+ * endianness and zero-extended to 64 bits.
+ */
+uint64_t getUintX(ByteOrder endian) const;
+
+/**
+ * Set the value in the word w after truncating it to the length
+ * of the packet and then byteswapping it to the desired
+ * endianness.
+ */
+void setUintX(uint64_t w, ByteOrder endian);
+
 /**
  * Copy data into the packet from the provided pointer.
  */

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I2f0c27fe3903abf3859bea13b07c7f5f0fb0809f
Gerrit-Change-Number: 9761
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: ps2: Unify device data buffering

[Andreas Sandberg (Gerrit)]

Hello Giacomo Travaglini,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/9765

to review the following change.


Change subject: ps2: Unify device data buffering
..

ps2: Unify device data buffering

All PS/2 device currently implement various ad-hoc mechanisms to
handle multi-byte commands. This is error-prone and makes it hard to
implement new devices. Create a buffering mechanism in the base class
to avoid this.

Change-Id: If5638b0ab68decea8de7631ecead0a9ebad1547b
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/ps2/device.cc
M src/dev/ps2/device.hh
M src/dev/ps2/keyboard.cc
M src/dev/ps2/keyboard.hh
M src/dev/ps2/mouse.cc
M src/dev/ps2/mouse.hh
M src/dev/ps2/touchkit.cc
M src/dev/ps2/touchkit.hh
8 files changed, 111 insertions(+), 126 deletions(-)



diff --git a/src/dev/ps2/device.cc b/src/dev/ps2/device.cc
index 7019423..073e015 100644
--- a/src/dev/ps2/device.cc
+++ b/src/dev/ps2/device.cc
@@ -44,12 +44,14 @@
 #include "dev/ps2/device.hh"

 #include "base/logging.hh"
+#include "debug/PS2.hh"
 #include "dev/ps2.hh"
 #include "params/PS2Device.hh"

 PS2Device::PS2Device(const PS2DeviceParams *p)
 : SimObject(p)
 {
+inBuffer.reserve(16);
 }

 void
@@ -58,6 +60,8 @@
 std::vector buffer(outBuffer.size());
 std::copy(outBuffer.begin(), outBuffer.end(), buffer.begin());
 arrayParamOut(cp, "outBuffer", buffer);
+
+SERIALIZE_CONTAINER(inBuffer);
 }

 void
@@ -67,6 +71,8 @@
 arrayParamIn(cp, "outBuffer", buffer);
 for (auto c : buffer)
 outBuffer.push_back(c);
+
+UNSERIALIZE_CONTAINER(inBuffer);
 }

 void
@@ -89,7 +95,10 @@
 void
 PS2Device::hostWrite(uint8_t c)
 {
-recv(c);
+DPRINTF(PS2, "PS2: Host -> device: %#x\n", c);
+inBuffer.push_back(c);
+if (recv(inBuffer))
+inBuffer.clear();
 }

 void
@@ -97,6 +106,7 @@
 {
 assert(data || size == 0);
 while (size) {
+DPRINTF(PS2, "PS2: Device -> host: %#x\n", *data);
 outBuffer.push_back(*(data++));
 size--;
 }
diff --git a/src/dev/ps2/device.hh b/src/dev/ps2/device.hh
index 342a8c2..b485c5e 100644
--- a/src/dev/ps2/device.hh
+++ b/src/dev/ps2/device.hh
@@ -45,6 +45,7 @@
 #define __DEV_PS2_DEVICE_HH__

 #include 
+#include 

 #include "sim/sim_object.hh"

@@ -92,8 +93,18 @@
   protected: /* Device interface */
 /**
  * Data received from host.
+ *
+ * This method is called whenever the host sends a byte to the
+ * device. The device model may request buffering in the base
+ * class by returning false. Once all data in the buffer has been
+ * processed, the method should return true which clears the
+ * buffer.
+ *
+ * @param data Pending input data (at least one byte)
+ * @return false if more data is needed to process the current
+ * command, true otherwise.
  */
-virtual void recv(uint8_t data) = 0;
+virtual bool recv(const std::vector ) = 0;

 /**
  * Send data from a PS/2 device to a host
@@ -125,6 +136,9 @@
 /** Device -> host FIFO */
 std::deque outBuffer;

+/** Host -> device buffer */
+std::vector inBuffer;
+
 std::function<void()> dataAvailableCallback;
 };

diff --git a/src/dev/ps2/keyboard.cc b/src/dev/ps2/keyboard.cc
index 46b89fa..1f8b544 100644
--- a/src/dev/ps2/keyboard.cc
+++ b/src/dev/ps2/keyboard.cc
@@ -52,7 +52,6 @@

 PS2Keyboard::PS2Keyboard(const PS2KeyboardParams *p)
 : PS2Device(p),
-  lastCommand(NoCommand),
   shiftDown(false),
   enabled(false)
 {
@@ -64,7 +63,6 @@
 PS2Keyboard::serialize(CheckpointOut ) const
 {
 PS2Device::serialize(cp);
-SERIALIZE_SCALAR(lastCommand);
 SERIALIZE_SCALAR(shiftDown);
 SERIALIZE_SCALAR(enabled);
 }
@@ -73,40 +71,28 @@
 PS2Keyboard::unserialize(CheckpointIn )
 {
 PS2Device::unserialize(cp);
-UNSERIALIZE_SCALAR(lastCommand);
 UNSERIALIZE_SCALAR(shiftDown);
 UNSERIALIZE_SCALAR(enabled);
 }

-void
-PS2Keyboard::recv(uint8_t data)
+bool
+PS2Keyboard::recv(const std::vector )
 {
-if (lastCommand != NoCommand) {
-switch (lastCommand) {
-  case LEDWrite:
+switch (data[0]) {
+  case LEDWrite:
+if (data.size() == 1) {
+DPRINTF(PS2, "Got LED write command.\n");
+sendAck();
+return false;
+} else {
 DPRINTF(PS2, "Setting LEDs: "
 "caps lock %s, num lock %s, scroll lock %s\n",
-bits(data, 2) ? "on" : "off",
-bits(data, 1) ? "on" : "off",
-bits(data, 0) ? "on" : "off");
+bi

[gem5-dev] Change in gem5/gem5[master]: ps2: Add VNC support to the keyboard model

[Andreas Sandberg (Gerrit)]

Hello Giacomo Travaglini,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/9763

to review the following change.


Change subject: ps2: Add VNC support to the keyboard model
..

ps2: Add VNC support to the keyboard model

Add support for keyboard input from the VNC server in the PS/2
keyboard model. The introduced code is based on the functionality in
the Arm PL050 KMI model.

Change-Id: If04a9713e5a15e2149d1a7471b999e3060d8ee7d
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/ps2/PS2.py
M src/dev/ps2/keyboard.cc
M src/dev/ps2/keyboard.hh
3 files changed, 47 insertions(+), 2 deletions(-)



diff --git a/src/dev/ps2/PS2.py b/src/dev/ps2/PS2.py
index 5db3b6e..da7eae9 100644
--- a/src/dev/ps2/PS2.py
+++ b/src/dev/ps2/PS2.py
@@ -48,6 +48,8 @@
 type = 'PS2Keyboard'
 cxx_header = "dev/ps2/keyboard.hh"

+vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer")
+
 class PS2Mouse(PS2Device):
 type = 'PS2Mouse'
 cxx_header = "dev/ps2/mouse.hh"
diff --git a/src/dev/ps2/keyboard.cc b/src/dev/ps2/keyboard.cc
index a942d34..46b89fa 100644
--- a/src/dev/ps2/keyboard.cc
+++ b/src/dev/ps2/keyboard.cc
@@ -45,14 +45,19 @@

 #include "base/logging.hh"
 #include "debug/PS2.hh"
+#include "dev/ps2.hh"
 #include "params/PS2Keyboard.hh"

 const uint8_t PS2Keyboard::ID[] = {0xab, 0x83};

 PS2Keyboard::PS2Keyboard(const PS2KeyboardParams *p)
 : PS2Device(p),
-  lastCommand(NoCommand)
+  lastCommand(NoCommand),
+  shiftDown(false),
+  enabled(false)
 {
+if (p->vnc)
+p->vnc->setKeyboard(this);
 }

 void
@@ -60,6 +65,8 @@
 {
 PS2Device::serialize(cp);
 SERIALIZE_SCALAR(lastCommand);
+SERIALIZE_SCALAR(shiftDown);
+SERIALIZE_SCALAR(enabled);
 }

 void
@@ -67,6 +74,8 @@
 {
 PS2Device::unserialize(cp);
 UNSERIALIZE_SCALAR(lastCommand);
+UNSERIALIZE_SCALAR(shiftDown);
+UNSERIALIZE_SCALAR(enabled);
 }

 void
@@ -114,14 +123,17 @@
 break;
   case Enable:
 DPRINTF(PS2, "Enabling the keyboard.\n");
+enabled = true;
 sendAck();
 break;
   case Disable:
 DPRINTF(PS2, "Disabling the keyboard.\n");
+enabled = false;
 sendAck();
 break;
   case DefaultsAndDisable:
 DPRINTF(PS2, "Disabling and resetting the keyboard.\n");
+enabled = false;
 sendAck();
 break;
   case AllKeysToTypematic:
@@ -148,6 +160,27 @@
 }
 }

+void
+PS2Keyboard::keyPress(uint32_t key, bool down)
+{
+std::list keys;
+
+// convert the X11 keysym into ps2 codes and update the shift
+// state (shiftDown)
+Ps2::keySymToPs2(key, down, shiftDown, keys);
+
+// Drop key presses if the keyboard hasn't been enabled by the
+// host. We do that after translating the key code to ensure that
+// we keep track of the shift state.
+if (!enabled)
+return;
+
+// Insert into our queue of characters
+for (uint8_t c : keys)
+send(c);
+}
+
+
 PS2Keyboard *
 PS2KeyboardParams::create()
 {
diff --git a/src/dev/ps2/keyboard.hh b/src/dev/ps2/keyboard.hh
index 8943e7f..f5d8304 100644
--- a/src/dev/ps2/keyboard.hh
+++ b/src/dev/ps2/keyboard.hh
@@ -44,11 +44,12 @@
 #ifndef __DEV_PS2_KEYBOARD_HH__
 #define __DEV_PS2_KEYBOARD_HH__

+#include "base/vnc/vncinput.hh"
 #include "dev/ps2/device.hh"

 struct PS2KeyboardParams;

-class PS2Keyboard : public PS2Device
+class PS2Keyboard : public PS2Device, VncKeyboard
 {
   protected:
 static const uint8_t ID[];
@@ -78,6 +79,12 @@

 uint16_t lastCommand;

+/** is the shift key currently down */
+bool shiftDown;
+
+/** Is the device enabled? */
+bool enabled;
+
   public:
 PS2Keyboard(const PS2KeyboardParams *p);

@@ -86,6 +93,9 @@

   protected: // PS2Device
 void recv(uint8_t data) override;
+
+  public: // VncKeyboard
+void keyPress(uint32_t key, bool down) override;
 };

 #endif // __DEV_PS2_KEYBOARD_hH__

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: If04a9713e5a15e2149d1a7471b999e3060d8ee7d
Gerrit-Change-Number: 9763
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: ps2: Add a simple touchscreen model

[Andreas Sandberg (Gerrit)]

Hello Giacomo Travaglini,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/9764

to review the following change.


Change subject: ps2: Add a simple touchscreen model
..

ps2: Add a simple touchscreen model

Add a touchscreen model that is compatible with Linux's TouchKit
driver. This model is based on the model in the Arm PL050 KMI model.

Change-Id: Id4d88a21a26bb42c455e4d778cd89875f650ac57
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/ps2/PS2.py
M src/dev/ps2/SConscript
A src/dev/ps2/touchkit.cc
A src/dev/ps2/touchkit.hh
4 files changed, 266 insertions(+), 0 deletions(-)



diff --git a/src/dev/ps2/PS2.py b/src/dev/ps2/PS2.py
index da7eae9..951ace0 100644
--- a/src/dev/ps2/PS2.py
+++ b/src/dev/ps2/PS2.py
@@ -53,3 +53,9 @@
 class PS2Mouse(PS2Device):
 type = 'PS2Mouse'
 cxx_header = "dev/ps2/mouse.hh"
+
+class PS2TouchKit(PS2Device):
+type = 'PS2TouchKit'
+cxx_header = "dev/ps2/touchkit.hh"
+
+vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer")
diff --git a/src/dev/ps2/SConscript b/src/dev/ps2/SConscript
index acce7be..a73e47a 100644
--- a/src/dev/ps2/SConscript
+++ b/src/dev/ps2/SConscript
@@ -46,5 +46,6 @@
 Source('device.cc')
 Source('keyboard.cc')
 Source('mouse.cc')
+Source('touchkit.cc')

 DebugFlag('PS2')
diff --git a/src/dev/ps2/touchkit.cc b/src/dev/ps2/touchkit.cc
new file mode 100644
index 000..e5ee3ef
--- /dev/null
+++ b/src/dev/ps2/touchkit.cc
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2010, 2017-2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *  William Wang
+ *  Andreas Sandberg
+ */
+
+#include "dev/ps2/touchkit.hh"
+
+#include "base/logging.hh"
+#include "debug/PS2.hh"
+#include "dev/ps2.hh"
+#include "params/PS2TouchKit.hh"
+
+const uint8_t PS2TouchKit::ID[] = {0x00};
+
+PS2TouchKit::PS2TouchKit(const PS2TouchKitParams *p)
+: PS2Device(p),
+  vnc(p->vnc),
+  ackNext(false),
+  driverInitialized(false)
+{
+if (vnc)
+vnc->setMouse(this);
+}
+
+void
+PS2TouchKit::serialize(CheckpointOut ) const
+{
+PS2Device::serialize(cp);
+
+SERIALIZE_SCALAR(ackNext);
+SERIALIZE_SCALAR(driverInitialized);
+}
+
+void
+PS2TouchKit::unserialize(CheckpointIn )
+{
+PS2Device::unserialize(cp);
+
+UNSERIALIZE_SCALAR(ackNext);
+UNSERIALIZE_SCALAR(driverInitialized);
+}
+
+void
+PS2TouchKit::recv(uint8_t data)
+{
+if (ackNext) {
+ackNext--;
+sendAck();
+return;
+}
+
+switch (data) {
+  case Ps2::Ps2Reset:
+se

[gem5-dev] Change in gem5/gem5[master]: dev, arm: Cleanup Pl050 interrupt handling

[Andreas Sandberg (Gerrit)]

Hello Giacomo Travaglini,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/9769

to review the following change.


Change subject: dev, arm: Cleanup Pl050 interrupt handling
..

dev, arm: Cleanup Pl050 interrupt handling

Add support for TX interrupts and cleanup existing RX interrupt
handling.

Change-Id: If2e5b0c0cc6fbeb2dce09e7e9d935647516b2c47
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/arm/RealView.py
M src/dev/arm/kmi.cc
M src/dev/arm/kmi.hh
3 files changed, 65 insertions(+), 74 deletions(-)



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 7661db1..9b91f46 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -466,7 +466,6 @@
 class Pl050(AmbaIntDevice):
 type = 'Pl050'
 cxx_header = "dev/arm/kmi.hh"
-int_delay = '1us'
 amba_id = 0x00141050

 ps2 = Param.PS2Device("PS/2 device")
diff --git a/src/dev/arm/kmi.cc b/src/dev/arm/kmi.cc
index d80bc14..e6e54a4 100644
--- a/src/dev/arm/kmi.cc
+++ b/src/dev/arm/kmi.cc
@@ -55,10 +55,9 @@
 Pl050::Pl050(const Pl050Params *p)
 : AmbaIntDevice(p, 0xfff), control(0), status(0x43), clkdiv(0),
   rawInterrupts(0),
-  intEvent([this]{ generateInterrupt(); }, name()),
   ps2(p->ps2)
 {
-ps2->hostRegDataAvailable([this]() { this->updateIntStatus(); });
+ps2->hostRegDataAvailable([this]() { this->updateRxInt(); });
 }

 Tick
@@ -84,8 +83,8 @@

   case kmiData:
 data = ps2->hostDataAvailable() ? ps2->hostRead() : 0;
+updateRxInt();
 DPRINTF(Pl050, "Read Data: %#x\n", (uint32_t)data);
-updateIntStatus();
 break;

   case kmiClkDiv:
@@ -108,21 +107,7 @@
 break;
 }

-switch(pkt->getSize()) {
-  case 1:
-pkt->set(data);
-break;
-  case 2:
-pkt->set(data);
-break;
-  case 4:
-pkt->set(data);
-break;
-  default:
-panic("KMI read size too big?\n");
-break;
-}
-
+pkt->setUintX(data, LittleEndianByteOrder);
 pkt->makeAtomicResponse();
 return pioDelay;
 }
@@ -134,29 +119,33 @@
 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr +  
pioSize);


 Addr daddr = pkt->getAddr() - pioAddr;
+const uint32_t data = pkt->getUintX(LittleEndianByteOrder);

 assert(pkt->getSize() == sizeof(uint8_t));

-
 switch (daddr) {
   case kmiCr:
 DPRINTF(Pl050, "Write Commmand: %#x\n",  
(uint32_t)pkt->get());

-control = pkt->get();
-updateIntStatus();
+// Use the update interrupts helper to make sure any interrupt
+// mask changes are handled correctly.
+updateRawInts(0, 0, (uint8_t)data);
 break;

   case kmiData:
 DPRINTF(Pl050, "Write Data: %#x\n", (uint32_t)pkt->get());
-ps2->hostWrite(pkt->get());
-updateIntStatus();
+// Clear the TX interrupt before writing new data.
+setTxInt(false);
+ps2->hostWrite((uint8_t)data);
+// Data is written in 0 time, so raise the TX interrupt again.
+setTxInt(true);
 break;

   case kmiClkDiv:
-clkdiv = pkt->get();
+clkdiv = (uint8_t)data;
 break;

   default:
-warn("Tried to write PL050 at offset %#x that doesn't exist\n",  
daddr);

+warn("PL050: Unhandled write of %#x to offset %#x\n", data, daddr);
 break;
 }

@@ -164,18 +153,44 @@
 return pioDelay;
 }

+void
+Pl050::setTxInt(bool value)
+{
+InterruptReg set = 0, clear = 0;
+
+set.tx = value ? 1 : 0;
+clear.tx = !value ? 1 : 0;
+
+updateRawInts(set, clear, control);
+}

 void
-Pl050::updateIntStatus()
+Pl050::updateRxInt()
 {
-const bool old_interrupt(getInterrupt());
+InterruptReg set = 0, clear = 0;

-rawInterrupts.rx = ps2->hostDataAvailable() ? 1 : 0;
+set.rx = ps2->hostDataAvailable() ? 1 : 0;
+clear.rx = !ps2->hostDataAvailable() ? 1 : 0;

-if ((!old_interrupt && getInterrupt()) && !intEvent.scheduled()) {
-schedule(intEvent, curTick() + intDelay);
-} else if (old_interrupt && !(getInterrupt())) {
-gic->clearInt(intNum);
+updateRawInts(set, clear, control);
+}
+
+void
+Pl050::updateRawInts(InterruptReg set, InterruptReg clear, ControlReg  
control)

+{
+const bool old_pending(getInterrupt());
+this->control = control;
+rawInterrupts = (rawInterrupts & ~clear) | set;
+const bool new_pending(getInterrupt());
+
+if (!old_pending && new_pending) {
+DPRINTF(Pl050, "Ge

[gem5-dev] Change in gem5/gem5[master]: ps2: Factor out PS/2 devices into their own subsystem

[Andreas Sandberg (Gerrit)]

Hello Giacomo Travaglini,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/9762

to review the following change.


Change subject: ps2: Factor out PS/2 devices into their own subsystem
..

ps2: Factor out PS/2 devices into their own subsystem

PS/2 devices are currently emulated both in the i8042 model and the
Arm KMI model. This is undesirable since it leads to code duplication.

This change introduces a common PS/2 device interface and factor out
the x86 keyboard and mouse model. A subsequent commit will implement
support for this interface in the Arm KMI model.

Change-Id: I440e83517fd9dce362fdc1676db477cc6eee5211
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/ps2.hh
A src/dev/ps2/PS2.py
A src/dev/ps2/SConscript
A src/dev/ps2/device.cc
A src/dev/ps2/device.hh
A src/dev/ps2/keyboard.cc
A src/dev/ps2/keyboard.hh
A src/dev/ps2/mouse.cc
A src/dev/ps2/mouse.hh
M src/dev/x86/I8042.py
M src/dev/x86/i8042.cc
M src/dev/x86/i8042.hh
12 files changed, 908 insertions(+), 382 deletions(-)



diff --git a/src/dev/ps2.hh b/src/dev/ps2.hh
index 9e99867..7b57835 100644
--- a/src/dev/ps2.hh
+++ b/src/dev/ps2.hh
@@ -61,6 +61,7 @@
 ReadId  = 0xf2,
 TpReadId= 0xe1,
 Ack = 0xfa,
+Resend  = 0xfe,
 SetRate = 0xf3,
 Enable  = 0xf4,
 Disable = 0xf5,
diff --git a/src/dev/ps2/PS2.py b/src/dev/ps2/PS2.py
new file mode 100644
index 000..5db3b6e
--- /dev/null
+++ b/src/dev/ps2/PS2.py
@@ -0,0 +1,53 @@
+# Copyright (c) 2017-2018 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
+
+class PS2Device(SimObject):
+type = 'PS2Device'
+cxx_header = "dev/ps2/device.hh"
+abstract = True
+
+class PS2Keyboard(PS2Device):
+type = 'PS2Keyboard'
+cxx_header = "dev/ps2/keyboard.hh"
+
+class PS2Mouse(PS2Device):
+type = 'PS2Mouse'
+cxx_header = "dev/ps2/mouse.hh"
diff --git a/src/dev/ps2/SConscript b/src/dev/ps2/SConscript
new file mode 100644
index 000..acce7be
--- /dev/null
+++ b/src/dev/ps2/SConscript
@@ -0,0 +1,50 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2017-2018 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all dist

[gem5-dev] Change in gem5/gem5[master]: ps2: Unify constant names

[Andreas Sandberg (Gerrit)]

Hello Giacomo Travaglini,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/9770

to review the following change.


Change subject: ps2: Unify constant names
..

ps2: Unify constant names

Move ps2.hh to dev/ps2/types.hh and update the device models to
consistently use well-known constants from this header.

Change-Id: Iadfdc774495957beb82f3d341107b1e9232ffd4c
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/SConscript
M src/dev/arm/kmi.cc
M src/dev/ps2/SConscript
M src/dev/ps2/device.cc
M src/dev/ps2/keyboard.cc
M src/dev/ps2/keyboard.hh
M src/dev/ps2/mouse.cc
M src/dev/ps2/mouse.hh
M src/dev/ps2/touchkit.cc
M src/dev/ps2/touchkit.hh
R src/dev/ps2/types.cc
R src/dev/ps2/types.hh
12 files changed, 167 insertions(+), 174 deletions(-)



diff --git a/src/dev/SConscript b/src/dev/SConscript
index 6939e03..c9526c2 100644
--- a/src/dev/SConscript
+++ b/src/dev/SConscript
@@ -50,7 +50,6 @@
 Source('mc146818.cc')
 Source('pixelpump.cc')
 Source('platform.cc')
-Source('ps2.cc')

 DebugFlag('Intel8254Timer')
 DebugFlag('MC146818')
diff --git a/src/dev/arm/kmi.cc b/src/dev/arm/kmi.cc
index e6e54a4..6603ef9 100644
--- a/src/dev/arm/kmi.cc
+++ b/src/dev/arm/kmi.cc
@@ -47,7 +47,6 @@
 #include "base/vnc/vncinput.hh"
 #include "debug/Pl050.hh"
 #include "dev/arm/amba_device.hh"
-#include "dev/ps2.hh"
 #include "dev/ps2/device.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
diff --git a/src/dev/ps2/SConscript b/src/dev/ps2/SConscript
index a73e47a..59bc242 100644
--- a/src/dev/ps2/SConscript
+++ b/src/dev/ps2/SConscript
@@ -47,5 +47,6 @@
 Source('keyboard.cc')
 Source('mouse.cc')
 Source('touchkit.cc')
+Source('types.cc')

 DebugFlag('PS2')
diff --git a/src/dev/ps2/device.cc b/src/dev/ps2/device.cc
index 073e015..8275cfc 100644
--- a/src/dev/ps2/device.cc
+++ b/src/dev/ps2/device.cc
@@ -45,7 +45,7 @@

 #include "base/logging.hh"
 #include "debug/PS2.hh"
-#include "dev/ps2.hh"
+#include "dev/ps2/types.hh"
 #include "params/PS2Device.hh"

 PS2Device::PS2Device(const PS2DeviceParams *p)
diff --git a/src/dev/ps2/keyboard.cc b/src/dev/ps2/keyboard.cc
index 78e287f..5e7dbcc 100644
--- a/src/dev/ps2/keyboard.cc
+++ b/src/dev/ps2/keyboard.cc
@@ -45,7 +45,7 @@

 #include "base/logging.hh"
 #include "debug/PS2.hh"
-#include "dev/ps2.hh"
+#include "dev/ps2/types.hh"
 #include "params/PS2Keyboard.hh"

 const uint8_t PS2Keyboard::ID[] = {0xab, 0x83};
@@ -79,7 +79,36 @@
 PS2Keyboard::recv(const std::vector )
 {
 switch (data[0]) {
-  case LEDWrite:
+  case Ps2::ReadID:
+DPRINTF(PS2, "Got keyboard read ID command.\n");
+sendAck();
+send((uint8_t *), sizeof(ID));
+return true;
+  case Ps2::Enable:
+DPRINTF(PS2, "Enabling the keyboard.\n");
+enabled = true;
+sendAck();
+return true;
+  case Ps2::Disable:
+DPRINTF(PS2, "Disabling the keyboard.\n");
+enabled = false;
+sendAck();
+return true;
+  case Ps2::DefaultsAndDisable:
+DPRINTF(PS2, "Disabling and resetting the keyboard.\n");
+enabled = false;
+sendAck();
+return true;
+  case Ps2::Reset:
+DPRINTF(PS2, "Resetting keyboard.\n");
+enabled = false;
+sendAck();
+send(Ps2::SelfTestPass);
+return true;
+  case Ps2::Resend:
+panic("Keyboard resend unimplemented.\n");
+
+  case Ps2::Keyboard::LEDWrite:
 if (data.size() == 1) {
 DPRINTF(PS2, "Got LED write command.\n");
 sendAck();
@@ -93,16 +122,11 @@
 sendAck();
 return true;
 }
-  case DiagnosticEcho:
+  case Ps2::Keyboard::DiagnosticEcho:
 panic("Keyboard diagnostic echo unimplemented.\n");
-  case AlternateScanCodes:
+  case Ps2::Keyboard::AlternateScanCodes:
 panic("Accessing alternate scan codes unimplemented.\n");
-  case ReadID:
-DPRINTF(PS2, "Got keyboard read ID command.\n");
-sendAck();
-send((uint8_t *), sizeof(ID));
-return true;
-  case TypematicInfo:
+  case Ps2::Keyboard::TypematicInfo:
 if (data.size() == 1) {
 DPRINTF(PS2, "Setting typematic info.\n");
 sendAck();
@@ -112,44 +136,21 @@
 sendAck();
 return true;
 }
-  case Enable:
-DPRINTF(PS2, "Enabling the keyboard.\n");
-enabled = true;
-sendAck();
-return true;
-  case Disable:
-DPRINTF(PS2, "Disabling the ke

[gem5-dev] Change in gem5/gem5[master]: ps2: Implement the keyboard reset command

[Andreas Sandberg (Gerrit)]

Hello Giacomo Travaglini,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/9766

to review the following change.


Change subject: ps2: Implement the keyboard reset command
..

ps2: Implement the keyboard reset command

Linux tries to reset the PS/2 keyboard at boot.

Change-Id: I727fbf6138b654885d82d85be9d964ee3d3365ef
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/ps2/keyboard.cc
1 file changed, 6 insertions(+), 2 deletions(-)



diff --git a/src/dev/ps2/keyboard.cc b/src/dev/ps2/keyboard.cc
index 1f8b544..78e287f 100644
--- a/src/dev/ps2/keyboard.cc
+++ b/src/dev/ps2/keyboard.cc
@@ -127,6 +127,12 @@
 enabled = false;
 sendAck();
 return true;
+  case Reset:
+DPRINTF(PS2, "Resetting keyboard.\n");
+sendAck();
+enabled = false;
+send(Ps2::SelfTestPass);
+return true;
   case AllKeysToTypematic:
 panic("Setting all keys to typemantic unimplemented.\n");
   case AllKeysToMakeRelease:
@@ -144,8 +150,6 @@
 panic("Setting key to make only unimplemented.\n");
   case Resend:
 panic("Keyboard resend unimplemented.\n");
-  case Reset:
-panic("Keyboard reset unimplemented.\n");
   default:
 panic("Unknown keyboard command %#02x.\n", data[0]);
 }

--
To view, visit https://gem5-review.googlesource.com/9766
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I727fbf6138b654885d82d85be9d964ee3d3365ef
Gerrit-Change-Number: 9766
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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Re: [gem5-dev] Fix opengrok or remove the link from gem.org sidebar

[Andreas Sandberg]

How about switching to a hosted service that integrates with our git
repositories directly?

I have played around with insight.io, but it seems like they require you
to login to the server using your GitHub credentials to access public
repos. Something that doesn't require a separate login would be ideal.
Does anyone know of anything?

Cheers,
Andreas


On 07/04/2018 22:12, Gabe Black wrote:

I don't think removing the link is helpful. We should fix the service it
links to.

Gabe

On Sat, Apr 7, 2018 at 1:14 PM, Ciro Santilli  wrote:


Ping.


Can we remove the link until it gets fixed?


From: gem5-dev  on behalf of Gabe Black <
gabebl...@google.com>
Sent: Tuesday, March 13, 2018 10:33:44 PM
To: gem5 Developer List
Subject: Re: [gem5-dev] Fix opengrok or remove the link from gem.org
sidebar

For whatever reason, I find that my administrative access on gem5.org
comes
and goes, and has currently went. I think Ali set up opengrok and so would
be best placed to fix it. It was useful back when we first set it up, and
it would be good to fix it.

Gabe

On Tue, Mar 13, 2018 at 5:56 AM, Ciro Santilli 
wrote:


Did you manage to fix it? Still seems broken to me.


If not, can we just remove the link for now, and put it back up if

someone

fixes it?


Looks bad for the project to have a broken link on the sidebar 


From: gem5-dev  on behalf of Gabe Black <
gabebl...@google.com>
Sent: Tuesday, February 27, 2018 12:40:39 AM
To: gem5 Developer List
Subject: Re: [gem5-dev] Fix opengrok or remove the link from gem.org
sidebar

It looks like changing to git would be pretty easy, since that's handled

in

/etc/cron.daily/opengrok:

#!/bin/bash
cd /var/opengrok/src/gem5
hg pull
hg update
/z/opengrok/bin/OpenGrok update


On Mon, Feb 26, 2018 at 4:39 PM, Gabe Black 

wrote:

Also it doesn't help that I don't have permission to access any of the
logs for tomcat or apache. But looking at the output of ps -ef, I don't

see

tomcat running, so I don't think the opengrok server bit is running

which

would fit with the other bit of log I was able to access.

Also I notice that the source opengrok is indexing is mercurial. It
wouldn't be a bad idea to change that over to git.

Gabe

On Mon, Feb 26, 2018 at 4:30 PM, Gabe Black 

wrote:

I'm not up on how opengrok is hooked into the gem5.org site, but I
ssh-ed in and saw this in one of the log files:

2018-02-24 06:42:31.799-0500 INFO t1 Indexer.sendToConfigHost: Send
configuration to: localhost:2424
2018-02-24 06:42:31.813-0500 SEVERE t1 Indexer.sendToConfigHost:

Failed

to send configuration to localhost:2424 (is web application server

running

with opengrok deploye
d?)

It looks like some of the config may have been damaged, or some piece

of

the setup hasn't been started like it's supposed to be. Without more
information about how it's *supposed* to work, it's hard to say.

Gabe

On Fri, Feb 23, 2018 at 6:08 AM, Ciro Santilli 

Re: [gem5-dev] Fwd: Make me a collaborator on GitHub to better manage issues

[Andreas Sandberg]

Hi Everyone,

I think the first thing we need to establish is whether we want to use
GitHub for issue tracking in the first place. The issue tracker there
was left enabled by accident.

As some of you may recall, we used to run a Flyspray-based issue tracker
a long time ago. If memory serves me right, we ended up shutting down
the tracker since it was mainly used for spam and none of the devs was
using it.

Cheers,
Andreas


On 07/04/2018 21:20, Ciro Santilli wrote:

Can I be made a collaborator on GitHub https://github.com/gem5/gem5 to help
manage the issues there?

This is my account: https://github.com/cirosantilli-work

I want this permission to be able to:

- close resolved issues
- tag issues appropriately, specially by architecture when appropriate
- fix formatting problems

and I will not use it for anything else.

I have been supporting users often on the mailing list / GitHub / Stack
Overflow over the last month, and Andreas can also serve as my reference.
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[gem5-dev] GDB in KVM (was: Re: virtual timer in ARM KVM)

[Andreas Sandberg]

On 05/04/2018 23:12, Gabe Black wrote:
On Thu, Apr 5, 2018 at 8:14 AM, Andreas Sandberg 
<andreas.sandb...@arm.com<mailto:andreas.sandb...@arm.com>> wrote:


I've also seen very weird behavior as far as how many instructions KVM
thinks are being executed per tick, so I wouldn't discount there being
something off about how it's keeping track of time. I haven't been able to
attach GDB to the KVM VCPUs for instance, even though it looks like all the
pieces are there for that to work. It seems that KVM is supposed to exit
after a given number of instructions, but it's just not for some reason.

I have used GDB in the past, but the support is very flaky. To use GDB
with KVM, I had to force a thread context sync on every KVM entry/exit.
You can do this by setting the alwaysSyncTC  param, but it will kill
your performance. The proper fix for this issue is to implement a custom
KVM thread context that lazily synchronises individual registers instead
of only synchronising on drain (and some other calls).


This sounds to me like you had problems with it giving you valid information or 
running commands properly. I had problems with it even breaking into gdb in the 
first place, with the vcpus just running free until gdb gave up. I saw messages 
about the event which was supposed to cause the CPUs to stop already being 
scheduled, so I think it was just never getting triggered by the kvm cpu for 
some reason. We're going to be getting a bigger and better machine to run KVM 
simulations on in the relatively near future, and my hope is that some of these 
weird issues magically go away on different hardware.

I think there are two classes of problems here, context synchronisation and 
multi-threaded KVM issues. The description above only really covers the context 
synchronisation issue. The root cause is that we try to synchronise the TC 
lazily to avoid the cost of transferring a lot of state between gem5 and the 
kernel. The simulator tries to keep track of when the TC is dirty by setting 
threadContextDirty and when KVM has dirty state by setting kvmStateDirty.

Whenever gem5 might want to access the TC (e.g., when getContext() is called or 
on drain()), we call syncThreadContext() that updates the TC if the KVM state 
is dirty. Conversely, whenever we enter KVM, we update the KVM state if the TC 
is dirty.

If I remember correctly, the GDB was holding on to a pointer to the TC, which 
meant that the thread context wasn't synchronised properly. That's why it 
started working when I enabled alwaysSyncTC.

I think you might be hitting the other class of problems as well. IIRC, gdb 
uses the instruction event queue to trigger an exit into gem5. This should work 
in a single-threaded setup since events are inserted while the CPU isn't 
running. When entering into KVM, we calculate the number of instructions to 
execute and call setupInstCounter() to arm a perf counter that triggers an exit 
after a fixed number of instructions. If the instruction event is inserted from 
a different thread, we'd need to first stop the CPU and then insert the event 
to ensure that it is handled correctly. The best solution is probably to force 
a global barrier as and call kick() on all KVM CPUs to ensure that the exit 
from KVM. Another option would be to schedule the instruction stop (you'll 
probably have to lock the CPUs EQ for this) and then call kick() to force the 
CPU to service the instruction queue.

//Andreas
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Re: [gem5-dev] virtual timer in ARM KVM

[Andreas Sandberg]

On 05/04/2018 03:42, Gabe Black wrote:

Hi folks. I'm continuing to try to iron out problems with KVM on ARM, and
the problem I'm working on specifically right now is that the mouse device
gets spurious bad command bytes which panics gem5.

What I've found so far is that the guest kernel will frequently time out
while waiting for an ACK to a byte it sent to the mouse, even though the
timeout looks like it should be 200ms, the simulation quantum I'm using is
1ms, and the delay between an event and the corresponding interrupt is
configured to be 1us. I think this eventually throws the PS2 driver out of
whack, and it ends up sending a data byte (or something else?) to the mouse
which the mouse misinterprets as a command, causing the panic.


Last time I looked at this, I suspected that the PS/2 model wasn't
clearing some interrupts. The GIC model in gem5 normally doesn't worry
about that and raises an interrupt every time someone calls the
sendInt(). The behaviour I have observed from the kernel is that it
doesn't post a new interrupt unless you first clear the old interrupt.
This caused some issues with a other models in the past (IIRC, the UART).

Make sure you test this in a single-threaded simulator as well to avoid
other weirdness due to thread syncrhonisation in gem5. I assume you're
already doing this though.


My current theory for why that's happening is that even when the VM is not
running, the hardware supported virtual timer the CPU may have scheduled to
keep track of its timeout may be "running" in the sense that the kernel
will update it to reflect the descheduled time once the VM is running
again. That could mean that 200ms of real time could pass, looking like
200ms of simulated time to the VCPU even if a smaller amount of actual
execution time was supposed to happen. I'm not sure if that's a correct
interpretation, but this ASPLOS paper *seems* to say something like that is
possible.

http://www.cs.columbia.edu/~cdall/pubs/asplos019-dall.pdf


I have never been happy with the way we handle the timer on the Arm KVM
CPUs. It's possible to re-sync the virtual counter when entering into
KVM.  A simple way to test that would be to update KVM_REG_ARM_TIMER_CNT
/ MISCREG_CNTVCT whenever entering into KVM. The Linux side should
update the virtual timer offset when you write an absolute time to this
register.

This should work for Linux, but you might have issues with other OSes
that insist on using the physical timer instead of the virtual timer.


I've also seen very weird behavior as far as how many instructions KVM
thinks are being executed per tick, so I wouldn't discount there being
something off about how it's keeping track of time. I haven't been able to
attach GDB to the KVM VCPUs for instance, even though it looks like all the
pieces are there for that to work. It seems that KVM is supposed to exit
after a given number of instructions, but it's just not for some reason.


I have used GDB in the past, but the support is very flaky. To use GDB
with KVM, I had to force a thread context sync on every KVM entry/exit.
You can do this by setting the alwaysSyncTC  param, but it will kill
your performance. The proper fix for this issue is to implement a custom
KVM thread context that lazily synchronises individual registers instead
of only synchronising on drain (and some other calls).

Cheers,
Andreas

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Re: [gem5-dev] Multicore ARM v8 KVM based simulation

[Andreas Sandberg]

The performance impact shouldn't be too bad. I did some scalability tests using 
LU from SPLASH 2 years ago. IIRC, I was using an 8-core Westmere-EX based 
system at the time. Native throughput for that benchmark was ~30GIPS @ 8 cores. 
When running in KVM, I got something like ~15GIPS with a 1ms quantum and 10GIPS 
with a 0.5ms quantum. Unfortunately, I don't have that data for any Arm-based 
system.

Turning on the HDLCD will probably reduce throughput quite a bit, but it should 
be running in a functional refresh mode (10Hz by default) when running in KVM. 
It's far from optimised, but should work. We had some KMI issues last time I 
looked at this. IIRC, the KMI model doesn't clear interrupts correctly, which 
confuses the interrupt model in the kernel.

Setting up event queues for KVM automatically would definitely be desirable. As 
you, painfully, noticed, this is currently the responsibility of the config 
script. The Arm example scripts do it already and should work out of the box. I 
suspect it might be tricky to get this right from inside the simulator without 
some re-architecting of the simulator core. What we would have to do is to add 
an API to allocate semi-private EQs from inside C++. Since Python provides an 
EQ number that get allocated in C++ at instantiation time, we would have to 
defer EQ allocation until init() is called or create a better mechanism to 
allocate EQs from Python instead of having a plain EQ index. We still want a 
way to force the old behaviour when simulating single-core systems since that 
makes debugging a lot easier.

Cheers,
Andreas

On 29/03/2018 01:14, Gabe Black wrote:
Ok, I think I figured it out, and it all has to do with the simulation quantum. 
If the quantum is too big, the kernel might poke hardware and expect to get an 
interrupt within a certain period of time. It could be that the CPU gets to the 
end of its timeout before the simulated hardware has had a chance to trigger an 
interrupt, even though the interrupt would happen first if the event queues 
were held in tighter sync. If I decrease the size of the quantum from 500ms 
(per your suggestion) to 1ms, then I see the errors from the keyboard/mouse 
drivers and the ATA driver go away, at least in the one CPU/multiple event 
queue configuration.

I'm going to do some more testing to make sure there isn't some other problem 
that pops up, and also to characterize the performance impact which I'm hopeful 
won't be too bad.

Also, I was thinking it would be nice if KVM CPUs could set up their event 
queues in some more automatic, less error prone way. Before I knew that they 
needed their own event queue (which I think is just institutional knowledge 
that isn't documented/warned about/etc.?), I had no idea what was going wrong 
when just dropping in some KVM CPUs in place of regular CPUs. I don't have a 
fully fleshed out plan for how to do that, but it doesn't *seem* like something 
that should be that hard to do.

Gabe

On Mon, Mar 26, 2018 at 7:06 PM, Gabe Black 
<gabebl...@google.com<mailto:gabebl...@google.com>> wrote:
I looked into this a little further, and I see the same problem happen with one 
CPU but with the CPU and the devices in different event queues. I haven't 
figured out exactly where things go wrong, but it looks like a write DMA is set 
up but doesn't happen for some reason. I'm not sure if the DMA starts but then 
gets stuck, or if it never starts at all. It could also be that the DMA 
happens, but the completion event (which is what doesn't seem to happen) is 
mishandled because of the additional event queue.

I turned on the DMA debug flag, but that produced so much debug output that my 
tools are crashing. I'll have to see what I can do to narrow things down a bit.

Gabe

On Thu, Mar 22, 2018 at 11:28 AM, Gabe Black 
<gabebl...@google.com<mailto:gabebl...@google.com>> wrote:
Ok, thanks. We're deciding internally what approach to use to tackle this.

Gabe

On Wed, Mar 21, 2018 at 3:01 AM, Andreas Sandberg 
<andreas.sandb...@arm.com<mailto:andreas.sandb...@arm.com>> wrote:

Hi Gabe,

There are issues with the IDE model that prevent it from working with in-kernel 
GIC emulation. I believe the model doesn't clear interrupts correctly, which 
confuses the host kernel. I tried to debug this at some point, but wasn't able 
to do much immaediate progress and decided it wasn't worth the effort. The 
VirtIO block devices doesn't suffer from this problem.

Using the VirtIO device by default seems like a good idea to me. It doesn't 
simulate any timing, but that might not be a huge deal since the IDE device 
doesn't provide realistic timing anyway. It would be really awesome if we had a 
modern storage controller (e.g., NVMe or AHCI) and proper storage timing models.

Cheers,
Andreas

On 20/03/2018 23:38, Gabe Black wrote:
My next question is about disks. I see that the fs_bigLITTLE.py script uses 
PciVirtIO to set up its disks, where I'm using I

Re: [gem5-dev] Multicore ARM v8 KVM based simulation

[Andreas Sandberg]

gabebl...@google.com>> wrote:
Ok, thanks. We're deciding internally what approach to use to tackle this.

Gabe

On Wed, Mar 21, 2018 at 3:01 AM, Andreas Sandberg 
<andreas.sandb...@arm.com<mailto:andreas.sandb...@arm.com>> wrote:

Hi Gabe,

There are issues with the IDE model that prevent it from working with in-kernel 
GIC emulation. I believe the model doesn't clear interrupts correctly, which 
confuses the host kernel. I tried to debug this at some point, but wasn't able 
to do much immaediate progress and decided it wasn't worth the effort. The 
VirtIO block devices doesn't suffer from this problem.

Using the VirtIO device by default seems like a good idea to me. It doesn't 
simulate any timing, but that might not be a huge deal since the IDE device 
doesn't provide realistic timing anyway. It would be really awesome if we had a 
modern storage controller (e.g., NVMe or AHCI) and proper storage timing models.

Cheers,
Andreas

On 20/03/2018 23:38, Gabe Black wrote:
My next question is about disks. I see that the fs_bigLITTLE.py script uses 
PciVirtIO to set up its disks, where I'm using IDE which I inherited from the 
fs.py scripts I used as reference. The problem I'm seeing is that the IDE 
controllers seem to be mangling commands and dropping interrupts, so this 
difference looks particularly suspicious. Is there a KVM related reason you're 
using PciVirtIO? Is this something that *should* work with IDE bug doesn't, or 
do I have to use PciVirtIO for things to work properly? I'm not familiar with 
PciVirtIO beyond briefly skimming the source for it in gem5. Is this something 
we should consider using globally as a replacement for IDE, even in simulations 
where we're trying to be really realistic?

Thanks again for all the help.

Gabe

On Tue, Mar 20, 2018 at 3:14 PM, Gabe Black 
<gabebl...@google.com<mailto:gabebl...@google.com>> wrote:
Ok, that (multiple event queues) made things way better. There are still some 
glitches to figure out, but at least it makes good forward progress at a 
reasonable speed. Thanks!

Gabe

On Mon, Mar 19, 2018 at 5:12 PM, Gabe Black 
<gabebl...@google.com<mailto:gabebl...@google.com>> wrote:
This is on an chromebook based on the RK3399 with only ~4GB of RAM which is not 
ideal, although we have a bigger machine in the works for the future. I agree 
with your reasoning and don't think option 1 is a problem. We're using static 
DTBs so I don't think that's an issue either. In my script, I'm not doing 
anything smart with the event queues, so that's likely at least part of the 
problem. When I tried using fs_bigLITTLE.py I ran into what looked like a 
similar issue so that might not be the whole story, but it's definitely 
something I should fix up. I'll let you know how that goes!

Gabe

On Mon, Mar 19, 2018 at 4:30 AM, Andreas Sandberg 
<andreas.sandb...@arm.com<mailto:andreas.sandb...@arm.com>> wrote:

Hmm, OK, this is very strange.

What type of hardware are you running on? Is it an A57-based chip or something 
else? Also, what's your simulation quantum? I have been able to run with a 
0.5ms quantum  (5e8 ticks).

I think the following trace of two CPUs running in KVM should be roughly 
equivalent to the trace you shared earlier. It was generated on a commercially 
available 8xA57 (16GiB ram) using the following command (gem5 rev 9dc44b417):

gem5.opt -r --debug-flags Kvm,KvmIO,KvmRun configs/example/arm/fs_bigLITTLE.py \
   --sim-quantum '0.5ms' \
   --cpu-type kvm --big-cpus 0 --little-cpus 2 \
   --dtb system/arm/dt/armv8_gem5_v1_2cpu.dtb --kernel 
vmlinux.aarch64.4.4-d318f95d0c

Note that the tick counts are a bit weird since we have three different event 
queues at play (1 for devices and one per CPU).

 0: system.littleCluster.cpus0: KVM: Executing for 5 ticks
 0: system.littleCluster.cpus1: KVM: Executing for 5 ticks
 0: system.littleCluster.cpus0: KVM: Executed 79170 instructions in 176363 
cycles (88181504 ticks, sim cycles: 176363).
88182000: system.littleCluster.cpus0: handleKvmExit (exit_reason: 6)
88182000: system.littleCluster.cpus0: KVM: Handling MMIO (w: 1, addr: 
0x1c090024, len: 4)
88332000: system.littleCluster.cpus0: Entering KVM...
88332000: system.littleCluster.cpus0: KVM: Executing for 411668000 ticks
88332000: system.littleCluster.cpus0: KVM: Executed 4384 instructions in 16854 
cycles (8427000 ticks, sim cycles: 16854).
96759000: system.littleCluster.cpus0: handleKvmExit (exit_reason: 6)
96759000: system.littleCluster.cpus0: KVM: Handling MMIO (w: 1, addr: 
0x1c090030, len: 4)
 0: system.littleCluster.cpus1: KVM: Executed 409368 instructions in 666400 
cycles (33320 ticks, sim cycles: 666400).
33320: system.littleCluster.cpus1: Entering KVM...
33320: system.littleCluster.cpus1: KVM: Executing for 16680 ticks
96909000: system.littleCluster.cpus0: Entering KVM...
96909000: system.littleCluster.cpus0: KVM: Executing for 403091000 ticks
96909000: sy

Re: [gem5-dev] Protobuf compilation errors

[Andreas Sandberg]

Agreed. Using the old SWIG trick and use a less strict environment for
some external dependencies (e.g., ProtoBuf) seems like the right thing
to do. Thanks for looking into this! I would've done it myself if I had
a better understanding of the build system.

Most of the issues I have run into were related to specific protobuf
versions. I believe protobuf 3.3.0 had some issues with some headers
referring to undefined macros. Some other, older versions (2.6.1 or
2.4.1), triggered a misleading indentation warning.

Maybe the right solution is to not treat warnings as errors for protobuf
sources?

Thanks,
Andreas


On 21/03/2018 22:00, Gabe Black wrote:

I definitely don't think we should disable -Wall or -Werror. I'll look into
ways to disable that check in specific cases. Surprisingly I haven't run
into this problem on my workstation even though I've hit a bunch of other
problems related to very up to date tool versions, but maybe it's just
because I usually use gcc and not clang? I might need some help to make
sure any potential fix actually fixes things.

Gabe

On Wed, Mar 21, 2018 at 9:29 AM, Matthias Jung <jun...@eit.uni-kl.de> wrote:


Hey,

by the way, when we talk about protobuf, I recently found this:

 https://capnproto.org

Its claimed, that capnproto is faster than protobuf,
However, I cannot confirm that because I have not tried it.

Has somebody else experience with capnproto?

Best,
Matthias


Am 21.03.2018 um 16:37 schrieb Matteo Andreozzi <

matteo.andreo...@arm.com>:

Hi Andreas,
Thanks for sending this out. I’ve been experiencing issues on Mac using

clang, the issue in detail is:

Scons tries to build a test program including message.h from protobuf to

check if the protobuf C libraries are present

Protobuf versions later than 3.3.0 use the LANG_CXX11 macro without

defining it first, in at least one of their files (atom.h).

This causes the compilation of the test program to fail , due to the

-Wundef directive being set, and scons assuming that no protobuf is
available in the system.

The quick and dirty fix which I have on my local workspace is to remove

-Wundef from Sconstruct, which anyway never triggered before with the
exception of protobuf (on MSC_VER in the past, now on LANG_CXX11), see
below:

 main.Append(CCFLAGS=['-fno-strict-aliasing'])
 # Enable -Wall and -Wextra and then disable the few warnings that
 # we consistently violate
-main.Append(CCFLAGS=['-Wall', '-Wundef', '-Wextra',
+main.Append(CCFLAGS=['-Wall', '-Wextra',
  '-Wno-sign-compare', '-Wno-unused-parameter'])
 # We always compile using C++11
 main.Append(CXXFLAGS=['-std=c++11'])


From: Andreas Sandberg <andreas.sandb...@arm.com>
Date: Wednesday, 21 March 2018 at 15:25
To: gem5 Developer List <gem5-dev@gem5.org>
Cc: Gabe Black <gabebl...@google.com>, Matteo Andreozzi <

matteo.andreo...@arm.com>

Subject: Protobuf compilation errors

Hi Everyone,

We have been experiencing some issues with some combinations of
different versions of protobuf and gcc/clang. Most of the issues seem to
be related to undefined macros (-Wundef), but I have some vague memories
of other issues as well (unclear indentation?).

In the short term, it seems like we need to disable -Werror for files
that are generated by protoc. Another option would be to add
-Wno-error=undef to the global environment. What would be the preferred
solution here? I think I'm in favour of the former, but don't understand
the build system well enough to implement it.

Cheers,
Andreas


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[gem5-dev] Protobuf compilation errors

[Andreas Sandberg]

Hi Everyone,

We have been experiencing some issues with some combinations of
different versions of protobuf and gcc/clang. Most of the issues seem to
be related to undefined macros (-Wundef), but I have some vague memories
of other issues as well (unclear indentation?).

In the short term, it seems like we need to disable -Werror for files
that are generated by protoc. Another option would be to add
-Wno-error=undef to the global environment. What would be the preferred
solution here? I think I'm in favour of the former, but don't understand
the build system well enough to implement it.

Cheers,
Andreas

IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
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Re: [gem5-dev] Multicore ARM v8 KVM based simulation

[Andreas Sandberg]

Hi Gabe,

There are issues with the IDE model that prevent it from working with in-kernel 
GIC emulation. I believe the model doesn't clear interrupts correctly, which 
confuses the host kernel. I tried to debug this at some point, but wasn't able 
to do much immaediate progress and decided it wasn't worth the effort. The 
VirtIO block devices doesn't suffer from this problem.

Using the VirtIO device by default seems like a good idea to me. It doesn't 
simulate any timing, but that might not be a huge deal since the IDE device 
doesn't provide realistic timing anyway. It would be really awesome if we had a 
modern storage controller (e.g., NVMe or AHCI) and proper storage timing models.

Cheers,
Andreas

On 20/03/2018 23:38, Gabe Black wrote:
My next question is about disks. I see that the fs_bigLITTLE.py script uses 
PciVirtIO to set up its disks, where I'm using IDE which I inherited from the 
fs.py scripts I used as reference. The problem I'm seeing is that the IDE 
controllers seem to be mangling commands and dropping interrupts, so this 
difference looks particularly suspicious. Is there a KVM related reason you're 
using PciVirtIO? Is this something that *should* work with IDE bug doesn't, or 
do I have to use PciVirtIO for things to work properly? I'm not familiar with 
PciVirtIO beyond briefly skimming the source for it in gem5. Is this something 
we should consider using globally as a replacement for IDE, even in simulations 
where we're trying to be really realistic?

Thanks again for all the help.

Gabe

On Tue, Mar 20, 2018 at 3:14 PM, Gabe Black 
<gabebl...@google.com<mailto:gabebl...@google.com>> wrote:
Ok, that (multiple event queues) made things way better. There are still some 
glitches to figure out, but at least it makes good forward progress at a 
reasonable speed. Thanks!

Gabe

On Mon, Mar 19, 2018 at 5:12 PM, Gabe Black 
<gabebl...@google.com<mailto:gabebl...@google.com>> wrote:
This is on an chromebook based on the RK3399 with only ~4GB of RAM which is not 
ideal, although we have a bigger machine in the works for the future. I agree 
with your reasoning and don't think option 1 is a problem. We're using static 
DTBs so I don't think that's an issue either. In my script, I'm not doing 
anything smart with the event queues, so that's likely at least part of the 
problem. When I tried using fs_bigLITTLE.py I ran into what looked like a 
similar issue so that might not be the whole story, but it's definitely 
something I should fix up. I'll let you know how that goes!

Gabe

On Mon, Mar 19, 2018 at 4:30 AM, Andreas Sandberg 
<andreas.sandb...@arm.com<mailto:andreas.sandb...@arm.com>> wrote:

Hmm, OK, this is very strange.

What type of hardware are you running on? Is it an A57-based chip or something 
else? Also, what's your simulation quantum? I have been able to run with a 
0.5ms quantum  (5e8 ticks).

I think the following trace of two CPUs running in KVM should be roughly 
equivalent to the trace you shared earlier. It was generated on a commercially 
available 8xA57 (16GiB ram) using the following command (gem5 rev 9dc44b417):

gem5.opt -r --debug-flags Kvm,KvmIO,KvmRun configs/example/arm/fs_bigLITTLE.py \
   --sim-quantum '0.5ms' \
   --cpu-type kvm --big-cpus 0 --little-cpus 2 \
   --dtb system/arm/dt/armv8_gem5_v1_2cpu.dtb --kernel 
vmlinux.aarch64.4.4-d318f95d0c

Note that the tick counts are a bit weird since we have three different event 
queues at play (1 for devices and one per CPU).

 0: system.littleCluster.cpus0: KVM: Executing for 5 ticks
 0: system.littleCluster.cpus1: KVM: Executing for 5 ticks
 0: system.littleCluster.cpus0: KVM: Executed 79170 instructions in 176363 
cycles (88181504 ticks, sim cycles: 176363).
88182000: system.littleCluster.cpus0: handleKvmExit (exit_reason: 6)
88182000: system.littleCluster.cpus0: KVM: Handling MMIO (w: 1, addr: 
0x1c090024, len: 4)
88332000: system.littleCluster.cpus0: Entering KVM...
88332000: system.littleCluster.cpus0: KVM: Executing for 411668000 ticks
88332000: system.littleCluster.cpus0: KVM: Executed 4384 instructions in 16854 
cycles (8427000 ticks, sim cycles: 16854).
96759000: system.littleCluster.cpus0: handleKvmExit (exit_reason: 6)
96759000: system.littleCluster.cpus0: KVM: Handling MMIO (w: 1, addr: 
0x1c090030, len: 4)
 0: system.littleCluster.cpus1: KVM: Executed 409368 instructions in 666400 
cycles (33320 ticks, sim cycles: 666400).
33320: system.littleCluster.cpus1: Entering KVM...
33320: system.littleCluster.cpus1: KVM: Executing for 16680 ticks
96909000: system.littleCluster.cpus0: Entering KVM...
96909000: system.littleCluster.cpus0: KVM: Executing for 403091000 ticks
96909000: system.littleCluster.cpus0: KVM: Executed 4384 instructions in 15257 
cycles (7628500 ticks, sim cycles: 15257).
104538000: system.littleCluster.cpus0: handleKvmExit (exit_reason: 6)
104538000: system.littleCluster.cpus0: KVM: Handling M

Re: [gem5-dev] Multicore ARM v8 KVM based simulation

[Andreas Sandberg]

gt; wrote:
Some output which I think is suspicious:

55462000: system.cpus0: Entering KVM...
55462000: system.cpus0: KVM: Executing for 1506000 ticks
55462000: system.cpus0: KVM: Executed 5159 instructions in 13646 cycles 
(6823000 ticks, sim cycles: 13646).
56968000: system.cpus1: Entering KVM...
56968000: system.cpus1: KVM: Executing for 5317000 ticks
56968000: system.cpus1: KVM: Executed 7229 instructions in 14379 cycles 
(7189500 ticks, sim cycles: 14379).
62285000: system.cpus0: Entering KVM...
62285000: system.cpus0: KVM: Executing for 1872500 ticks
62285000: system.cpus0: KVM: Executed 5159 instructions in 13496 cycles 
(6748000 ticks, sim cycles: 13496).
64157500: system.cpus1: Entering KVM...
64157500: system.cpus1: KVM: Executing for 4875500 ticks
64157500: system.cpus1: KVM: Executed 6950 instructions in 13863 cycles 
(6931500 ticks, sim cycles: 13863).
69033000: system.cpus0: Entering KVM...
69033000: system.cpus0: KVM: Executing for 2056000 ticks
69033000: system.cpus0: KVM: Executed 5159 instructions in 13454 cycles 
(6727000 ticks, sim cycles: 13454).
71089000: system.cpus1: Entering KVM...
71089000: system.cpus1: KVM: Executing for 4671000 ticks
71089000: system.cpus1: KVM: Executed 6950 instructions in 13861 cycles 
(6930500 ticks, sim cycles: 13861).
7576: system.cpus0: Entering KVM...
7576: system.cpus0: KVM: Executing for 2259500 ticks
7576: system.cpus0: KVM: Executed 5159 instructions in 13688 cycles 
(6844000 ticks, sim cycles: 13688).

[...]

126512000: system.cpus0: handleKvmExit (exit_reason: 6)
126512000: system.cpus0: KVM: Handling MMIO (w: 1, addr: 0x1c090024, len: 4)
126512000: system.cpus0: In updateThreadContext():

[...]

126512000: system.cpus0:   PC := 0xd8 (t: 0, a64: 1)

On Wed, Mar 14, 2018 at 7:37 PM, Gabe Black 
<gabebl...@google.com<mailto:gabebl...@google.com>> wrote:
I tried it just now, and I still don't see anything on the console. I switched 
back to using my own script since it's a bit simpler (it doesn't use all the 
configs/common stuff), and started looking at the KVM debug output. I see that 
both cpus claim to execute instructions, although cpu1 didn't take an exit in 
the output I was looking at. cpu0 took four exits, two which touched some UART 
registers, and two which touched RealView registes, the V2M_SYS_CFGDATA and 
V2M_SYS_CFGCTRL registers judging by the comments in the bootloader assembly 
file.

After that they claim to be doing stuff, although I see no further console 
output or KVM exits. The accesses themselves and their PCs are from the 
bootloader blob, and so I'm pretty confident that it's starting that and 
executing some of those instructions. One thing that looks very odd now that I 
think about it, is that the KVM messages about entering and executing 
instructions (like those below) seem to say that cpu0 has executed thousands of 
instructions, but the exits I see seem to correspond to the first maybe 50 
instructions it should be seeing in the bootloader blob. Are those values bogus 
for some reason? Is there some existing debug output which would let me see 
where KVM thinks it is periodically to see if it's in the kernel or if it went 
bananas and is executing random memory somewhere? Or if it just got stuck 
waiting for some event that's not going to show up?

Are there any important CLs which haven't made their way into upstream somehow?

Gabe

On Wed, Mar 14, 2018 at 4:28 AM, Andreas Sandberg 
<andreas.sandb...@arm.com<mailto:andreas.sandb...@arm.com>> wrote:
Have you tried using the fs_bigLITTLE script in configs/examples/arm?
That's the script I have been using for testing.

I just tested the script with 8 little CPUs and 0 big CPUs and it seems
to work. Timing is a bit temperamental though, so you might need to
override the simulation quantum. The default is 1ms, you might need to
decrease it to something slightly smaller (I'm currently using 0.5ms).
Another caveat is that there seem to be some issues related to dtb
auto-generation that affect KVM guests. We are currently testing a
solution for this issue.

Cheers,
Andreas



On 12/03/2018 22:26, Gabe Black wrote:
I'm trying to run in FS mode, to boot android/linux.

Gabe

On Mon, Mar 12, 2018 at 3:26 PM, Dutu, Alexandru 
<alexandru.d...@amd.com<mailto:alexandru.d...@amd.com>>
wrote:

Hi Gabe,

Are you running SE or FS mode?

Thanks,
Alex

-Original Message-
From: gem5-dev 
[mailto:gem5-dev-boun...@gem5.org<mailto:gem5-dev-boun...@gem5.org>] On Behalf 
Of Gabe Black
Sent: Friday, March 9, 2018 5:46 PM
To: gem5 Developer List <gem5-dev@gem5.org<mailto:gem5-dev@gem5.org>>
Subject: [gem5-dev] Multicore ARM v8 KVM based simulation

Hi folks. I have a config script set up where I can run a KVM based ARM v8
simulation just fine when I have a single CPU in it, but when I try running
with more than one CPU, it just seems to get lost and not do anything. Is
this a configuration that's supported? If so, are there

Re: [gem5-dev] Multicore ARM v8 KVM based simulation

[Andreas Sandberg]

Have you tried using the fs_bigLITTLE script in configs/examples/arm?
That's the script I have been using for testing.

I just tested the script with 8 little CPUs and 0 big CPUs and it seems
to work. Timing is a bit temperamental though, so you might need to
override the simulation quantum. The default is 1ms, you might need to
decrease it to something slightly smaller (I'm currently using 0.5ms).
Another caveat is that there seem to be some issues related to dtb
auto-generation that affect KVM guests. We are currently testing a
solution for this issue.

Cheers,
Andreas


On 12/03/2018 22:26, Gabe Black wrote:

I'm trying to run in FS mode, to boot android/linux.

Gabe

On Mon, Mar 12, 2018 at 3:26 PM, Dutu, Alexandru 
wrote:


Hi Gabe,

Are you running SE or FS mode?

Thanks,
Alex

-Original Message-
From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Gabe Black
Sent: Friday, March 9, 2018 5:46 PM
To: gem5 Developer List 
Subject: [gem5-dev] Multicore ARM v8 KVM based simulation

Hi folks. I have a config script set up where I can run a KVM based ARM v8
simulation just fine when I have a single CPU in it, but when I try running
with more than one CPU, it just seems to get lost and not do anything. Is
this a configuration that's supported? If so, are there any caveats to how
it's set up? I may be missing something simple, but it's not apparent to me
at the moment.

Gabe
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[gem5-dev] Linux 4.14 and 4.15 with gem5 patches now available for Arm

[Andreas Sandberg]

Hi Everyone,

I'm happy to announce that we have just completed testing of the
gem5-specific patches for Linux 4.14 and 4.15. The new kernel sources
can be downloaded from the gem5/v4.14 [1] and gem5/v4.15 branches in the
arm/linux [3] project on Gerrit. Most users should prefer the 4.14
kernel as this is the latest LTS release of Linux. See the wiki [4] for
build instructions.

The kernels comes with default configurations for Armv7 and Armv8 and
has the same set of gem5-specific patches as the older 4.x kernels.
These patches add support for:

  * gem5's GICv2 extensions. This enables support for up to 255 CPUs if
the gem5 extensions are enabled in the GIC (set gem5_extensions to True
in your configuration script).
  * A virtual DRM connector. This makes it possible to use gem5's
display models without a proper HDMI encoder model.
  * The custom FBIOGET_DMABUF IOCTL. This change is useful to avoid a
CPU-side memcpy between the GPU's render buffer and the framebuffer for
Android setups that using NoMali.
  * gem5's DVFS controller.
  * General gem5 instrumentation.

Additionally, the upstream 4.15 kernel includes support for the Arm
Scalable Vector Extensions (SVE) that can be used with the beta
implementation of SVE for gem5 [5].

Known issues:

 * Recent Linux kernels don't expose the task struct in thread_info.
This affects gem5's instrumentation. Some of the Streamline support in
gem5 likely needs to be updated to support new kernels.

If you need to post any new kernel changes, please make sure to post
them to the gem5/v4.14 branch on gerrit.

Cheers,
Andreas

[1] https://gem5.googlesource.com/arm/linux/+/refs/heads/gem5/v4.14
[2] https://gem5.googlesource.com/arm/linux/+/refs/heads/gem5/v4.15
[3] https://gem5-review.googlesource.com/#/admin/projects/arm/linux
[4] http://gem5.org/ARM_Kernel
[5] https://gem5-review.googlesource.com/#/admin/projects/arm/gem5,branches
IMPORTANT NOTICE: The contents of this email and any attachments are 
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[gem5-dev] Change in public/gem5[master]: arch-arm: Semihosting not available in syscall emulation

[Andreas Sandberg (Gerrit)]

Andreas Sandberg merged this change by Giacomo Travaglini. (  
https://gem5-review.googlesource.com/8367 )


Change subject: arch-arm: Semihosting not available in syscall emulation
..

arch-arm: Semihosting not available in syscall emulation

Arm Semihosting is not available in syscall emulation since we don't
have an Arm system in that scenario. Trying to use it in "se" mode will
make getArmSystem assertion fail.

Change-Id: I4cf49ae801ec6e6c93134ac6ae2a0f412040684c
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8367
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/arch/arm/system.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index caef6dc..a540a63 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -273,7 +273,7 @@
 bool
 ArmSystem::haveSemihosting(ThreadContext *tc)
 {
-return getArmSystem(tc)->haveSemihosting();
+return FullSystem && getArmSystem(tc)->haveSemihosting();
 }

 uint64_t

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I4cf49ae801ec6e6c93134ac6ae2a0f412040684c
Gerrit-Change-Number: 8367
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
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[gem5-dev] Change in public/gem5[master]: cpu-o3: Don't add non-speculative mem barriers to the IQ twice

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/8374



Change subject: cpu-o3: Don't add non-speculative mem barriers to the IQ  
twice

..

cpu-o3: Don't add non-speculative mem barriers to the IQ twice

There are cases where the IEW adds a non-speculative instruction to
the IQ twice. This can happen if an instruction is flagged as
IsMemBarrier and IsNonSpeculative. Avoid adding non-speculative
instructions in the IEW to the IQ by checking if it has been added
already.

Change-Id: Ifcff676a451b57b2406ce00ed8dae19ed399515f
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Javier Setoain <javier.seto...@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrie...@arm.com>
---
M src/cpu/o3/iew_impl.hh
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 80d7adc..8270a71 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -1100,7 +1100,7 @@
 add_to_iq = true;
 }

-if (inst->isNonSpeculative()) {
+if (add_to_iq && inst->isNonSpeculative()) {
 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
 "encountered, skipping.\n", tid);


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ifcff676a451b57b2406ce00ed8dae19ed399515f
Gerrit-Change-Number: 8374
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
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[gem5-dev] Change in public/gem5[master]: mem: Refactor port proxies to support secure accesses

[Andreas Sandberg (Gerrit)]

Andreas Sandberg merged this change by Andreas Sandberg. (  
https://gem5-review.googlesource.com/8364 )


Change subject: mem: Refactor port proxies to support secure accesses
..

mem: Refactor port proxies to support secure accesses

The current physical port proxy doesn't know how to tag memory
accesses as secure. Refactor the class slightly to create a set of
methods (readBlobPhys, writeBlobPhys, memsetBlobPhys) that always
access physical memory and take a set of Request::Flags as an
argument. The new port proxy, SecurePortProxy, uses this interface to
issue secure physical accesses.

Change-Id: I8232a4b35025be04ec8f91a00f0580266bacb338
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8364
Maintainer: Nikos Nikoleris <nikos.nikole...@arm.com>
---
M src/mem/fs_translating_port_proxy.cc
M src/mem/fs_translating_port_proxy.hh
M src/mem/port_proxy.cc
M src/mem/port_proxy.hh
M src/mem/se_translating_port_proxy.cc
M src/mem/se_translating_port_proxy.hh
6 files changed, 87 insertions(+), 24 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved



diff --git a/src/mem/fs_translating_port_proxy.cc  
b/src/mem/fs_translating_port_proxy.cc

index 616c12e..ef86bf7 100644
--- a/src/mem/fs_translating_port_proxy.cc
+++ b/src/mem/fs_translating_port_proxy.cc
@@ -84,7 +84,7 @@
 else
 paddr = TheISA::vtophys(gen.addr());

-PortProxy::readBlob(paddr, p, gen.size());
+PortProxy::readBlobPhys(paddr, 0, p, gen.size());
 p += gen.size();
 }
 }
@@ -101,7 +101,7 @@
 else
 paddr = TheISA::vtophys(gen.addr());

-PortProxy::writeBlob(paddr, p, gen.size());
+PortProxy::writeBlobPhys(paddr, 0, p, gen.size());
 p += gen.size();
 }
 }
@@ -118,7 +118,7 @@
 else
 paddr = TheISA::vtophys(gen.addr());

-PortProxy::memsetBlob(paddr, v, gen.size());
+PortProxy::memsetBlobPhys(paddr, 0, v, gen.size());
 }
 }

diff --git a/src/mem/fs_translating_port_proxy.hh  
b/src/mem/fs_translating_port_proxy.hh

index e7b74d0..d4b4eb5 100644
--- a/src/mem/fs_translating_port_proxy.hh
+++ b/src/mem/fs_translating_port_proxy.hh
@@ -81,20 +81,20 @@

 FSTranslatingPortProxy(MasterPort , unsigned int cacheLineSize);

-virtual ~FSTranslatingPortProxy();
+~FSTranslatingPortProxy();

 /** Version of readblob that translates virt->phys and deals
   * with page boundries. */
-virtual void readBlob(Addr addr, uint8_t *p, int size) const;
+void readBlob(Addr addr, uint8_t *p, int size) const override;

 /** Version of writeBlob that translates virt->phys and deals
   * with page boundries. */
-virtual void writeBlob(Addr addr, const uint8_t *p, int size) const;
+void writeBlob(Addr addr, const uint8_t *p, int size) const override;

 /**
  * Fill size bytes starting at addr with byte value val.
  */
-virtual void memsetBlob(Addr address, uint8_t  v, int size) const;
+void memsetBlob(Addr address, uint8_t  v, int size) const override;
 };

 void CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen);
diff --git a/src/mem/port_proxy.cc b/src/mem/port_proxy.cc
index f40c64e..d454ef7 100644
--- a/src/mem/port_proxy.cc
+++ b/src/mem/port_proxy.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012, 2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -42,11 +42,12 @@
 #include "base/chunk_generator.hh"

 void
-PortProxy::readBlob(Addr addr, uint8_t *p, int size) const
+PortProxy::readBlobPhys(Addr addr, Request::Flags flags,
+uint8_t *p, int size) const
 {
 for (ChunkGenerator gen(addr, size, _cacheLineSize); !gen.done();
  gen.next()) {
-Request req(gen.addr(), gen.size(), 0, Request::funcMasterId);
+Request req(gen.addr(), gen.size(), flags, Request::funcMasterId);
 Packet pkt(, MemCmd::ReadReq);
 pkt.dataStatic(p);
 _port.sendFunctional();
@@ -55,11 +56,12 @@
 }

 void
-PortProxy::writeBlob(Addr addr, const uint8_t *p, int size) const
+PortProxy::writeBlobPhys(Addr addr, Request::Flags flags,
+ const uint8_t *p, int size) const
 {
 for (ChunkGenerator gen(addr, size, _cacheLineSize); !gen.done();
  gen.next()) {
-Request req(gen.addr(), gen.size(), 0, Request::funcMasterId);
+Request req(gen.addr(), gen.size(), flags, Request::funcMasterId);
 Packet pkt(, MemCmd::WriteReq);
 pkt.dataStaticConst(p);
 _port.sendFunctional();
@@ -68,13 +70,33 @@
 }

 void
-PortProxy::memsetBlob(Addr addr, uint8_t v, int size) const
+PortProxy::memsetBlobPh

[gem5-dev] Change in public/gem5[master]: arch-arm: Add aarch64 semihosting support

[Andreas Sandberg (Gerrit)]

Andreas Sandberg merged this change by Andreas Sandberg. (  
https://gem5-review.googlesource.com/8147 )


Change subject: arch-arm: Add aarch64 semihosting support
..

arch-arm: Add aarch64 semihosting support

Add basic support for Arm Semihosting 2.0 simulation calls [1]. These
calls let the guest system call a simulator or debugger to request
OS-like support when running bare metal code.

With the exception of SYS_SYSTEM, this implementation supports all of
the Semihosting 2.0 specification in aarch64.

[1] https://developer.arm.com/docs/100863/latest/preface

Change-Id: I08c153c18a4a4fb9f95d318e2a029724935192a7
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8147
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
A src/arch/arm/ArmSemihosting.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/SConscript
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/misc64.isa
A src/arch/arm/semihosting.cc
A src/arch/arm/semihosting.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
9 files changed, 1,423 insertions(+), 4 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/arch/arm/ArmSemihosting.py b/src/arch/arm/ArmSemihosting.py
new file mode 100644
index 000..1da4c49
--- /dev/null
+++ b/src/arch/arm/ArmSemihosting.py
@@ -0,0 +1,56 @@
+# Copyright (c) 2018 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.params import *
+from m5.SimObject import *
+
+from Serial import SerialDevice
+from Terminal import Terminal
+
+class ArmSemihosting(SimObject):
+type = 'ArmSemihosting'
+cxx_header = "arch/arm/semihosting.hh"
+
+cmd_line = Param.String("", "Command line to report to guest");
+
+mem_reserve = Param.MemorySize("32MB",
+"Amount of memory to reserve at the start of the address map.  
This "

+"memory won't be used by the heap reported to an application.");
+stack_size = Param.MemorySize("32MB", "Application stack size");
+
+time = Param.Time('01/01/2009',
+  "System time to use ('Now' for actual time)")
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 5687477..ec44331 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -41,6 +41,7 @@
 from m5.util.fdthelper import *

 from System import System
+from ArmSemihosting import ArmSemihosting

 class ArmMachineType(Enum):
 map = {
@@ -79,6 +80,9 @@
 have_large_asid_64 = Param.Bool(False,
 "True if ASID is 16 bits in AArch64 (ARMv

[gem5-dev] Change in public/gem5[master]: arch-arm: Add support for secure state in semihosting

[Andreas Sandberg (Gerrit)]

Andreas Sandberg merged this change by Andreas Sandberg. (  
https://gem5-review.googlesource.com/8365 )


Change subject: arch-arm: Add support for secure state in semihosting
..

arch-arm: Add support for secure state in semihosting

The semihosting component currently issues non-secure memory accesses
using the standard port proxy. This doesn't work when the guest is
running in secure state.

Change-Id: Id34b142cfcd9d77b455c040ae7f7397c29aebbc6
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8365
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/semihosting.cc
M src/arch/arm/semihosting.hh
2 files changed, 32 insertions(+), 11 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 98b50f4..89e1b2e 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -157,7 +157,7 @@
 }

 std::vector argv(call->argc64 + 1);
-PortProxy  = tc->getPhysProxy();
+PortProxy  = physProxy(tc);
 ByteOrder endian = ArmISA::byteOrder(tc);

 DPRINTF(Semihosting, "Semihosting call64: %s(0x%x)\n", call->name,  
param);

@@ -192,7 +192,7 @@
 }

 std::vector argv(call->argc32 + 1);
-PortProxy  = tc->getPhysProxy();
+PortProxy  = physProxy(tc);
 ByteOrder endian = ArmISA::byteOrder(tc);

 DPRINTF(Semihosting, "Semihosting call32: %s(0x%x)\n", call->name,  
param);

@@ -236,13 +236,30 @@
 files[i] = FileBase::create(*this, cp, csprintf("file%i", i));
 }

+PortProxy &
+ArmSemihosting::physProxy(ThreadContext *tc)
+{
+if (ArmISA::inSecureState(tc)) {
+if (!physProxyS) {
+System *sys = tc->getSystemPtr();
+physProxyS.reset(new SecurePortProxy(
+ sys->getSystemPort(),
+ sys->cacheLineSize()));
+}
+return *physProxyS;
+} else {
+return tc->getPhysProxy();
+}
+}
+
+
 std::string
 ArmSemihosting::readString(ThreadContext *tc, Addr ptr, size_t len)
 {
 std::vector buf(len + 1);

 buf[len] = '\0';
-tc->getPhysProxy().readBlob(ptr, (uint8_t *)buf.data(), len);
+physProxy(tc).readBlob(ptr, (uint8_t *)buf.data(), len);

 return std::string(buf.data());
 }
@@ -302,7 +319,7 @@
 ArmSemihosting::callWriteC(ThreadContext *tc, bool aarch64,
std::vector )
 {
-const char c = tc->getPhysProxy().read(argv[0]);
+const char c = physProxy(tc).read(argv[0]);

 DPRINTF(Semihosting, "Semihosting SYS_WRITEC('%c')\n", c);
 std::cout.put(c);
@@ -315,7 +332,7 @@
std::vector )
 {
 DPRINTF(Semihosting, "Semihosting SYS_WRITE0(...)\n");
-PortProxy  = tc->getPhysProxy();
+PortProxy  = physProxy(tc);
 for (Addr addr = (Addr)argv[0]; ; ++addr) {
 char data = proxy.read(addr);
 if (data == 0)
@@ -335,7 +352,7 @@
 return RetErrno(argv[3], EBADF);

 std::vector buffer(argv[3]);
-tc->getPhysProxy().readBlob(argv[2], buffer.data(), buffer.size());
+physProxy(tc).readBlob(argv[2], buffer.data(), buffer.size());

 int64_t ret = files[argv[1]]->write(buffer.data(), buffer.size());
 if (ret < 0) {
@@ -362,7 +379,7 @@
 } else {
 panic_if(ret > buffer.size(), "Read longer than buffer size.");

-tc->getPhysProxy().writeBlob(argv[2], buffer.data(), ret);
+physProxy(tc).writeBlob(argv[2], buffer.data(), ret);

 // Return the number of bytes not written
 return retOK(argv[3] - ret);
@@ -449,7 +466,7 @@
 if (path_len >= max_len)
 return retError(ENOSPC);

-tc->getPhysProxy().writeBlob(
+physProxy(tc).writeBlob(
 guest_buf, (const uint8_t *)path, path_len + 1);
 return retOK(0);
 }
@@ -519,7 +536,7 @@
std::vector )
 {
 if (cmdLine.size() + 1 < argv[2]) {
-PortProxy  = tc->getPhysProxy();
+PortProxy  = physProxy(tc);
 ByteOrder endian = ArmISA::byteOrder(tc);
 proxy.writeBlob(
 (Addr)argv[1],
@@ -576,7 +593,7 @@
heap_base, heap_limit, stack_base, stack_limit);

 Addr base = argv[1];
-PortProxy  = tc->getPhysProxy();
+PortProxy  = physProxy(tc);
 ByteOrder endian = ArmISA::byteOrder(tc);
 if (aarch64) {
 proxy.writeHtoG(base + 0 * 8, heap_base, endian);
@@ -631,7 +648,7 @@
 ArmSemihosting::callElapsed(ThreadContext *tc, bool aarch64,
 std::vector )
 {
-PortProxy  = tc->getPhysProxy();
+PortProxy  =

[gem5-dev] Change in public/gem5[master]: arch-arm: Add aarch64 semihosting support

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/8147

to look at the new patch set (#5).

Change subject: arch-arm: Add aarch64 semihosting support
..

arch-arm: Add aarch64 semihosting support

Add basic support for Arm Semihosting 2.0 simulation calls [1]. These
calls let the guest system call a simulator or debugger to request
OS-like support when running bare metal code.

With the exception of SYS_SYSTEM, this implementation supports all of
the Semihosting 2.0 specification in aarch64.

[1] https://developer.arm.com/docs/100863/latest/preface

Change-Id: I08c153c18a4a4fb9f95d318e2a029724935192a7
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
---
A src/arch/arm/ArmSemihosting.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/SConscript
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/misc64.isa
A src/arch/arm/semihosting.cc
A src/arch/arm/semihosting.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
9 files changed, 1,423 insertions(+), 4 deletions(-)


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Gerrit-Change-Number: 8147
Gerrit-PatchSet: 5
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
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[gem5-dev] Change in public/gem5[master]: mem: Refactor port proxies to support secure accesses

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/8364

to review the following change.


Change subject: mem: Refactor port proxies to support secure accesses
..

mem: Refactor port proxies to support secure accesses

The current physical port proxy doesn't know how to tag memory
accesses as secure. Refactor the class slightly to create a set of
methods (readBlobPhys, writeBlobPhys, memsetBlobPhys) that always
access physical memory and take a set of Request::Flags as an
argument. The new port proxy, SecurePortProxy, uses this interface to
issue secure physical accesses.

Change-Id: I8232a4b35025be04ec8f91a00f0580266bacb338
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
---
M src/mem/fs_translating_port_proxy.cc
M src/mem/fs_translating_port_proxy.hh
M src/mem/port_proxy.cc
M src/mem/port_proxy.hh
M src/mem/se_translating_port_proxy.cc
M src/mem/se_translating_port_proxy.hh
6 files changed, 87 insertions(+), 24 deletions(-)



diff --git a/src/mem/fs_translating_port_proxy.cc  
b/src/mem/fs_translating_port_proxy.cc

index 616c12e..ef86bf7 100644
--- a/src/mem/fs_translating_port_proxy.cc
+++ b/src/mem/fs_translating_port_proxy.cc
@@ -84,7 +84,7 @@
 else
 paddr = TheISA::vtophys(gen.addr());

-PortProxy::readBlob(paddr, p, gen.size());
+PortProxy::readBlobPhys(paddr, 0, p, gen.size());
 p += gen.size();
 }
 }
@@ -101,7 +101,7 @@
 else
 paddr = TheISA::vtophys(gen.addr());

-PortProxy::writeBlob(paddr, p, gen.size());
+PortProxy::writeBlobPhys(paddr, 0, p, gen.size());
 p += gen.size();
 }
 }
@@ -118,7 +118,7 @@
 else
 paddr = TheISA::vtophys(gen.addr());

-PortProxy::memsetBlob(paddr, v, gen.size());
+PortProxy::memsetBlobPhys(paddr, 0, v, gen.size());
 }
 }

diff --git a/src/mem/fs_translating_port_proxy.hh  
b/src/mem/fs_translating_port_proxy.hh

index e7b74d0..d4b4eb5 100644
--- a/src/mem/fs_translating_port_proxy.hh
+++ b/src/mem/fs_translating_port_proxy.hh
@@ -81,20 +81,20 @@

 FSTranslatingPortProxy(MasterPort , unsigned int cacheLineSize);

-virtual ~FSTranslatingPortProxy();
+~FSTranslatingPortProxy();

 /** Version of readblob that translates virt->phys and deals
   * with page boundries. */
-virtual void readBlob(Addr addr, uint8_t *p, int size) const;
+void readBlob(Addr addr, uint8_t *p, int size) const override;

 /** Version of writeBlob that translates virt->phys and deals
   * with page boundries. */
-virtual void writeBlob(Addr addr, const uint8_t *p, int size) const;
+void writeBlob(Addr addr, const uint8_t *p, int size) const override;

 /**
  * Fill size bytes starting at addr with byte value val.
  */
-virtual void memsetBlob(Addr address, uint8_t  v, int size) const;
+void memsetBlob(Addr address, uint8_t  v, int size) const override;
 };

 void CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen);
diff --git a/src/mem/port_proxy.cc b/src/mem/port_proxy.cc
index f40c64e..d454ef7 100644
--- a/src/mem/port_proxy.cc
+++ b/src/mem/port_proxy.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012, 2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -42,11 +42,12 @@
 #include "base/chunk_generator.hh"

 void
-PortProxy::readBlob(Addr addr, uint8_t *p, int size) const
+PortProxy::readBlobPhys(Addr addr, Request::Flags flags,
+uint8_t *p, int size) const
 {
 for (ChunkGenerator gen(addr, size, _cacheLineSize); !gen.done();
  gen.next()) {
-Request req(gen.addr(), gen.size(), 0, Request::funcMasterId);
+Request req(gen.addr(), gen.size(), flags, Request::funcMasterId);
 Packet pkt(, MemCmd::ReadReq);
 pkt.dataStatic(p);
 _port.sendFunctional();
@@ -55,11 +56,12 @@
 }

 void
-PortProxy::writeBlob(Addr addr, const uint8_t *p, int size) const
+PortProxy::writeBlobPhys(Addr addr, Request::Flags flags,
+ const uint8_t *p, int size) const
 {
 for (ChunkGenerator gen(addr, size, _cacheLineSize); !gen.done();
  gen.next()) {
-Request req(gen.addr(), gen.size(), 0, Request::funcMasterId);
+Request req(gen.addr(), gen.size(), flags, Request::funcMasterId);
 Packet pkt(, MemCmd::WriteReq);
 pkt.dataStaticConst(p);
 _port.sendFunctional();
@@ -68,13 +70,33 @@
 }

 void
-PortProxy::memsetBlob(Addr addr, uint8_t v, int size) const
+PortProxy::memsetBlobPhys(Addr addr, Request::Flags flags,
+  uint8_t v, int size) const
 {
 // quick and dirty...
 uint8_t *buf = new uint8_t[size];

 std::memset(b

[gem5-dev] Change in public/gem5[master]: arch-arm: Fix big endian support in {Load, Store}Double64

[Andreas Sandberg (Gerrit)]

Andreas Sandberg merged this change by Chuan Zhu. (  
https://gem5-review.googlesource.com/8145 )


Change subject: arch-arm: Fix big endian support in {Load,Store}Double64
..

arch-arm: Fix big endian support in {Load,Store}Double64

{Load, Store}Double64 didn't consider some of the big-endian
situations. Added big-endian related data conversions to correct them.

Change-Id: I8840613f94446e6042276779d1f02350ab57987f
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8145
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/str64.isa
2 files changed, 42 insertions(+), 18 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/isa/insts/ldr64.isa  
b/src/arch/arm/isa/insts/ldr64.isa

index e035e1d..8c966e4 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -228,23 +228,31 @@
 if self.size == 4:
 accCode = '''
 uint64_t data = cSwap(Mem_ud,  
isBigEndian64(xc->tcBase()));

-AA64FpDestP0_uw = (uint32_t)data;
+AA64FpDestP0_uw = isBigEndian64(xc->tcBase())
+? (data >> 32)
+: (uint32_t)data;
 AA64FpDestP1_uw = 0;
 AA64FpDestP2_uw = 0;
 AA64FpDestP3_uw = 0;
-AA64FpDest2P0_uw = (data >> 32);
+AA64FpDest2P0_uw = isBigEndian64(xc->tcBase())
+? (uint32_t)data
+: (data >> 32);
 AA64FpDest2P1_uw = 0;
 AA64FpDest2P2_uw = 0;
 AA64FpDest2P3_uw = 0;
 '''
 elif self.size == 8:
 accCode = '''
-AA64FpDestP0_uw = (uint32_t)Mem_tud[0];
-AA64FpDestP1_uw = (uint32_t)(Mem_tud[0] >> 32);
+uint64_t data_a = cSwap(Mem_tud[0],
+ 
isBigEndian64(xc->tcBase()));

+uint64_t data_b = cSwap(Mem_tud[1],
+ 
isBigEndian64(xc->tcBase()));

+AA64FpDestP0_uw = (uint32_t)data_a;
+AA64FpDestP1_uw = (uint32_t)(data_a >> 32);
 AA64FpDestP2_uw = 0;
 AA64FpDestP3_uw = 0;
-AA64FpDest2P0_uw = (uint32_t)Mem_tud[1];
-AA64FpDest2P1_uw = (uint32_t)(Mem_tud[1] >> 32);
+AA64FpDest2P0_uw = (uint32_t)data_b;
+AA64FpDest2P1_uw = (uint32_t)(data_b >> 32);
 AA64FpDest2P2_uw = 0;
 AA64FpDest2P3_uw = 0;
 '''
@@ -254,26 +262,38 @@
 accCode = '''
 uint64_t data = cSwap(Mem_ud,

isBigEndian64(xc->tcBase()));

-XDest = sext<32>((uint32_t)data);
-XDest2 = sext<32>(data >> 32);
+XDest = isBigEndian64(xc->tcBase())
+? sext<32>(data >> 32)
+: sext<32>((uint32_t)data);
+XDest2 = isBigEndian64(xc->tcBase())
+ ? sext<32>((uint32_t)data)
+ : sext<32>(data >> 32);
 '''
 elif self.size == 8:
 accCode = '''
-XDest = Mem_tud[0];
-XDest2 = Mem_tud[1];
+XDest = cSwap(Mem_tud[0],
+  isBigEndian64(xc->tcBase()));
+XDest2 = cSwap(Mem_tud[1],
+   isBigEndian64(xc->tcBase()));
 '''
 else:
 if self.size == 4:
 accCode = '''
 uint64_t data = cSwap(Mem_ud,

isBigEndian64(xc->tcBase()));

-XDest = (uint32_t)data;
-XDest2 = data >> 32;
+XDest = isBigEndian64(xc->tcBase())
+  

[gem5-dev] Change in public/gem5[master]: arch-arm: Fix big endian support in do{Long, L1, L2}Descriptor

[Andreas Sandberg (Gerrit)]

Andreas Sandberg merged this change by Chuan Zhu. (  
https://gem5-review.googlesource.com/8144 )


Change subject: arch-arm: Fix big endian support in do{Long,L1,L2}Descriptor
..

arch-arm: Fix big endian support in do{Long,L1,L2}Descriptor

do{Long,L1,L2}Descriptor was not able to load descriptors correctly
for big-endian situations, causing recognised Descriptors.  Added
big-endian related data conversions to correct them.

Change-Id: I0fdfbbdf56f94bbed19172acae1b6e4a0382b5a0
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8144
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/arch/arm/table_walker.cc
M src/arch/arm/utility.hh
2 files changed, 14 insertions(+), 0 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 428556b..3c79e43 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -1423,6 +1423,9 @@
 return;
 }

+currState->l1Desc.data = htog(currState->l1Desc.data,
+  byteOrder(currState->tc));
+
 DPRINTF(TLB, "L1 descriptor for %#x is %#x\n",
 currState->vaddr_tainted, currState->l1Desc.data);
 TlbEntry te;
@@ -1518,6 +1521,9 @@
 return;
 }

+currState->longDesc.data = htog(currState->longDesc.data,
+byteOrder(currState->tc));
+
 DPRINTF(TLB, "L%d descriptor for %#llx is %#llx (%s)\n",
 currState->longDesc.lookupLevel, currState->vaddr_tainted,
 currState->longDesc.data,
@@ -1709,6 +1715,9 @@
 return;
 }

+currState->l2Desc.data = htog(currState->l2Desc.data,
+  byteOrder(currState->tc));
+
 DPRINTF(TLB, "L2 descriptor for %#x is %#x\n",
 currState->vaddr_tainted, currState->l2Desc.data);
 TlbEntry te;
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 8efe4ad..796ded7 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -348,6 +348,11 @@
  */
 uint8_t encodePhysAddrRange64(int pa_size);

+inline ByteOrder byteOrder(ThreadContext *tc)
+{
+return isBigEndian64(tc) ? BigEndianByteOrder : LittleEndianByteOrder;
+};
+
 }

 #endif

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Gerrit-Branch: master
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Gerrit-Change-Id: I0fdfbbdf56f94bbed19172acae1b6e4a0382b5a0
Gerrit-Change-Number: 8144
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Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
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[gem5-dev] Change in public/gem5[master]: arch-arm: Add support for automatic reset addr selection

[Andreas Sandberg (Gerrit)]

Andreas Sandberg merged this change by Andreas Sandberg. (  
https://gem5-review.googlesource.com/8143 )


Change subject: arch-arm: Add support for automatic reset addr selection
..

arch-arm: Add support for automatic reset addr selection

Add an option to automatically set the aarch64 reset vector to the
entry point of the kernel. This is useful when running bare metal
workloads that don't use a normal boot loader.

Change-Id: Id472f865d461f0d8d8ea8efe5db582c170de0b90
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrie...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8143
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/system.cc
2 files changed, 7 insertions(+), 3 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index f76140b..5687477 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2009, 2012-2013, 2015-2017 ARM Limited
+# Copyright (c) 2009, 2012-2013, 2015-2018 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -72,6 +72,8 @@
 reset_addr_64 = Param.Addr(0x0,
 "Reset address if the highest implemented exception level is 64  
bits "

 "(ARMv8)")
+auto_reset_addr_64 = Param.Bool(False,
+"Determine reset address from kernel entry point if no boot  
loader")

 phys_addr_range_64 = Param.UInt8(40,
 "Supported physical address range in bits when using AArch64  
(ARMv8)")

 have_large_asid_64 = Param.Bool(False,
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 097a87b..50ac4ae 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2015,2017 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2015,2017-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -62,7 +62,9 @@
   _haveVirtualization(p->have_virtualization),
   _genericTimer(nullptr),
   _highestELIs64(p->highest_el_is_64),
-  _resetAddr64(p->reset_addr_64),
+  _resetAddr64(p->auto_reset_addr_64 ?
+   (kernelEntry & loadAddrMask) + loadAddrOffset :
+   p->reset_addr_64),
   _physAddrRange64(p->phys_addr_range_64),
   _haveLargeAsid64(p->have_large_asid_64),
   _m5opRange(p->m5ops_base ?

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Id472f865d461f0d8d8ea8efe5db582c170de0b90
Gerrit-Change-Number: 8143
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Assignee: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
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[gem5-dev] Change in public/gem5[master]: arch-arm: Decode Brk64 instructions

[Andreas Sandberg (Gerrit)]

Andreas Sandberg merged this change by Andreas Sandberg. (  
https://gem5-review.googlesource.com/8142 )


Change subject: arch-arm: Decode Brk64 instructions
..

arch-arm: Decode Brk64 instructions

The brk instruction in aarch64 was decoded as an unimplemented
instruction. Fix that.

Change-Id: I3eb36a016ab56d882426c5cdef3a0b594de0f9cd
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8142
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/isa/formats/aarch64.isa
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 0179f2f..0cb8e9c 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -254,7 +254,7 @@
   case 0x03:
 return new Smc64(machInst);
   case 0x04:
-return new FailUnimplemented("brk", machInst);
+return new Brk64(machInst);
   case 0x08:
 return new FailUnimplemented("hlt", machInst);
   case 0x15:

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Gerrit-Change-Number: 8142
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Assignee: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
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[gem5-dev] Change in public/gem5[master]: mem: Add PortProxy read/write helper with explicit endianness

[Andreas Sandberg (Gerrit)]

Andreas Sandberg merged this change by Andreas Sandberg. (  
https://gem5-review.googlesource.com/8146 )


Change subject: mem: Add PortProxy read/write helper with explicit  
endianness

..

mem: Add PortProxy read/write helper with explicit endianness

Change-Id: Ia9a11ca68b2892dafd02f2c37324b99b35c77d34
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8146
Reviewed-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/mem/port_proxy.hh
1 file changed, 32 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/mem/port_proxy.hh b/src/mem/port_proxy.hh
index e9ddeec..ac1873b 100644
--- a/src/mem/port_proxy.hh
+++ b/src/mem/port_proxy.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013 ARM Limited
+ * Copyright (c) 2011-2013, 2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -123,6 +123,20 @@
 template 
 void write(Addr address, T data) const;

+/**
+ * Read sizeof(T) bytes from address and return as object T.
+ * Performs selected endianness transform.
+ */
+template 
+T readGtoH(Addr address, ByteOrder guest_byte_order) const;
+
+/**
+ * Write object T to address. Writes sizeof(T) bytes.
+ * Performs selected endianness transform.
+ */
+template 
+void writeHtoG(Addr address, T data, ByteOrder guest_byte_order) const;
+
 #if THE_ISA != NULL_ISA
 /**
  * Read sizeof(T) bytes from address and return as object T.
@@ -157,6 +171,23 @@
 writeBlob(address, (uint8_t*), sizeof(T));
 }

+template 
+T
+PortProxy::readGtoH(Addr address, ByteOrder byte_order) const
+{
+T data;
+readBlob(address, (uint8_t*), sizeof(T));
+return gtoh(data, byte_order);
+}
+
+template 
+void
+PortProxy::writeHtoG(Addr address, T data, ByteOrder byte_order) const
+{
+data = htog(data, byte_order);
+writeBlob(address, (uint8_t*), sizeof(T));
+}
+
 #if THE_ISA != NULL_ISA
 template 
 T

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Gerrit-Change-Id: Ia9a11ca68b2892dafd02f2c37324b99b35c77d34
Gerrit-Change-Number: 8146
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
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[gem5-dev] Change in public/gem5[master]: sim: Add gtoh/htog helpers that take an explicit endianness

[Andreas Sandberg (Gerrit)]

Andreas Sandberg merged this change by Chuan Zhu. (  
https://gem5-review.googlesource.com/8201 )


Change subject: sim: Add gtoh/htog helpers that take an explicit endianness
..

sim: Add gtoh/htog helpers that take an explicit endianness

Add helper functions to swap between guest byte order and host byte
order that take a guest endianness as a parameter. These functions are
called htog and htog to be consistent with the helper functions that
extract guest byte order from a compile time constant.

Change-Id: Ie6be7dfd3b7a58ad6bfb57b25be5f85b5f425929
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8201
Reviewed-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/sim/byteswap.hh
1 file changed, 14 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/sim/byteswap.hh b/src/sim/byteswap.hh
index 2c3517f..a46f8f5 100644
--- a/src/sim/byteswap.hh
+++ b/src/sim/byteswap.hh
@@ -154,6 +154,20 @@
 #error Invalid Endianess
 #endif

+template 
+inline T htog(T value, ByteOrder guest_byte_order)
+{
+return guest_byte_order == BigEndianByteOrder ?
+htobe(value) : htole(value);
+}
+
+template 
+inline T gtoh(T value, ByteOrder guest_byte_order)
+{
+return guest_byte_order == BigEndianByteOrder ?
+betoh(value) : letoh(value);
+}
+
 namespace BigEndianGuest
 {
 const ByteOrder GuestByteOrder = BigEndianByteOrder;

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Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
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[gem5-dev] Change in public/gem5[master]: dev: Remove unused interrupt controller in Terminal

[Andreas Sandberg (Gerrit)]

Andreas Sandberg merged this change by Andreas Sandberg. (  
https://gem5-review.googlesource.com/8141 )


Change subject: dev: Remove unused interrupt controller in Terminal
..

dev: Remove unused interrupt controller in Terminal

Change-Id: I412d0b5edf2a08217792fa2ed1e511c17d3d31d4
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8141
Reviewed-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/dev/serial/Terminal.py
M src/dev/serial/terminal.hh
2 files changed, 0 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/dev/serial/Terminal.py b/src/dev/serial/Terminal.py
index 863c487..8644916 100644
--- a/src/dev/serial/Terminal.py
+++ b/src/dev/serial/Terminal.py
@@ -34,7 +34,6 @@
 class Terminal(SerialDevice):
 type = 'Terminal'
 cxx_header = "dev/serial/terminal.hh"
-intr_control = Param.IntrControl(Parent.any, "interrupt controller")
 port = Param.TcpPort(3456, "listen port")
 number = Param.Int(0, "terminal number")
 output = Param.Bool(True, "Enable output dump to file")
diff --git a/src/dev/serial/terminal.hh b/src/dev/serial/terminal.hh
index 48bfc07..9e114de 100644
--- a/src/dev/serial/terminal.hh
+++ b/src/dev/serial/terminal.hh
@@ -42,7 +42,6 @@
 #include "base/circlebuf.hh"
 #include "base/pollevent.hh"
 #include "base/socket.hh"
-#include "cpu/intr_control.hh"
 #include "dev/serial/serial.hh"
 #include "params/Terminal.hh"
 #include "sim/sim_object.hh"

--
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Gerrit-Change-Number: 8141
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
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[gem5-dev] Change in public/gem5[master]: arch-arm: Add aarch64 semihosting support

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/8147

to look at the new patch set (#3).

Change subject: arch-arm: Add aarch64 semihosting support
..

arch-arm: Add aarch64 semihosting support

Add basic support for Arm Semihosting 2.0 simulation calls [1]. These
calls let the guest system call a simulator or debugger to request
OS-like support when running bare metal code.

With the exception of SYS_SYSTEM, this implementation supports all of
the Semihosting 2.0 specification in aarch64.

[1] https://developer.arm.com/docs/100863/latest/preface

Change-Id: I08c153c18a4a4fb9f95d318e2a029724935192a7
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
---
A src/arch/arm/ArmSemihosting.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/SConscript
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/misc64.isa
A src/arch/arm/semihosting.cc
A src/arch/arm/semihosting.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
9 files changed, 1,419 insertions(+), 4 deletions(-)


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Gerrit-Change-Number: 8147
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
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[gem5-dev] Change in public/gem5[master]: sim: Add gtoh/htog helpers that take an explicit endianness

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/8201



Change subject: sim: Add gtoh/htog helpers that take an explicit endianness
..

sim: Add gtoh/htog helpers that take an explicit endianness

Add helper functions to swap between guest byte order and host byte
order that take a guest endianness as a parameter. These functions are
called htog and htog to be consistent with the helper functions that
extract guest byte order from a compile time constant.

Change-Id: Ie6be7dfd3b7a58ad6bfb57b25be5f85b5f425929
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/sim/byteswap.hh
1 file changed, 14 insertions(+), 0 deletions(-)



diff --git a/src/sim/byteswap.hh b/src/sim/byteswap.hh
index 2c3517f..a46f8f5 100644
--- a/src/sim/byteswap.hh
+++ b/src/sim/byteswap.hh
@@ -154,6 +154,20 @@
 #error Invalid Endianess
 #endif

+template 
+inline T htog(T value, ByteOrder guest_byte_order)
+{
+return guest_byte_order == BigEndianByteOrder ?
+htobe(value) : htole(value);
+}
+
+template 
+inline T gtoh(T value, ByteOrder guest_byte_order)
+{
+return guest_byte_order == BigEndianByteOrder ?
+betoh(value) : letoh(value);
+}
+
 namespace BigEndianGuest
 {
 const ByteOrder GuestByteOrder = BigEndianByteOrder;

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[gem5-dev] Change in public/gem5[master]: arch-arm: Add support for automatic reset addr selection

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/8143

to look at the new patch set (#2).

Change subject: arch-arm: Add support for automatic reset addr selection
..

arch-arm: Add support for automatic reset addr selection

Add an option to automatically set the aarch64 reset vector to the
entry point of the kernel. This is useful when running bare metal
workloads that don't use a normal boot loader.

Change-Id: Id472f865d461f0d8d8ea8efe5db582c170de0b90
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrie...@arm.com>
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/system.cc
2 files changed, 7 insertions(+), 3 deletions(-)


--
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Gerrit-Change-Id: Id472f865d461f0d8d8ea8efe5db582c170de0b90
Gerrit-Change-Number: 8143
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Assignee: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerrit-CC: Giacomo Travaglini <giacomo.travagl...@arm.com>
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[gem5-dev] Change in public/gem5[master]: arch-arm: Fix big endian support in do{Long, L1, L2}Descriptor

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/8144 )


Change subject: arch-arm: Fix big endian support in do{Long,L1,L2}Descriptor
..

arch-arm: Fix big endian support in do{Long,L1,L2}Descriptor

do{Long,L1,L2}Descriptor was not able to load descriptors correctly
for big-endian situations, causing recognised Descriptors.  Added
big-endian related data conversions to correct them.

Change-Id: I0fdfbbdf56f94bbed19172acae1b6e4a0382b5a0
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/arch/arm/table_walker.cc
M src/arch/arm/utility.hh
2 files changed, 14 insertions(+), 0 deletions(-)


--
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Gerrit-Change-Number: 8144
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
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[gem5-dev] Change in public/gem5[master]: arch-arm: Fix big endian support in {Load, Store}Double64

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/8145



Change subject: arch-arm: Fix big endian support in {Load,Store}Double64
..

arch-arm: Fix big endian support in {Load,Store}Double64

{Load, Store}Double64 didn't consider some of the big-endian
situations. Added big-endian related data conversions to correct them.

Change-Id: I8840613f94446e6042276779d1f02350ab57987f
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/str64.isa
2 files changed, 42 insertions(+), 18 deletions(-)



diff --git a/src/arch/arm/isa/insts/ldr64.isa  
b/src/arch/arm/isa/insts/ldr64.isa

index e035e1d..8c966e4 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -228,23 +228,31 @@
 if self.size == 4:
 accCode = '''
 uint64_t data = cSwap(Mem_ud,  
isBigEndian64(xc->tcBase()));

-AA64FpDestP0_uw = (uint32_t)data;
+AA64FpDestP0_uw = isBigEndian64(xc->tcBase())
+? (data >> 32)
+: (uint32_t)data;
 AA64FpDestP1_uw = 0;
 AA64FpDestP2_uw = 0;
 AA64FpDestP3_uw = 0;
-AA64FpDest2P0_uw = (data >> 32);
+AA64FpDest2P0_uw = isBigEndian64(xc->tcBase())
+? (uint32_t)data
+: (data >> 32);
 AA64FpDest2P1_uw = 0;
 AA64FpDest2P2_uw = 0;
 AA64FpDest2P3_uw = 0;
 '''
 elif self.size == 8:
 accCode = '''
-AA64FpDestP0_uw = (uint32_t)Mem_tud[0];
-AA64FpDestP1_uw = (uint32_t)(Mem_tud[0] >> 32);
+uint64_t data_a = cSwap(Mem_tud[0],
+ 
isBigEndian64(xc->tcBase()));

+uint64_t data_b = cSwap(Mem_tud[1],
+ 
isBigEndian64(xc->tcBase()));

+AA64FpDestP0_uw = (uint32_t)data_a;
+AA64FpDestP1_uw = (uint32_t)(data_a >> 32);
 AA64FpDestP2_uw = 0;
 AA64FpDestP3_uw = 0;
-AA64FpDest2P0_uw = (uint32_t)Mem_tud[1];
-AA64FpDest2P1_uw = (uint32_t)(Mem_tud[1] >> 32);
+AA64FpDest2P0_uw = (uint32_t)data_b;
+AA64FpDest2P1_uw = (uint32_t)(data_b >> 32);
 AA64FpDest2P2_uw = 0;
 AA64FpDest2P3_uw = 0;
 '''
@@ -254,26 +262,38 @@
 accCode = '''
 uint64_t data = cSwap(Mem_ud,

isBigEndian64(xc->tcBase()));

-XDest = sext<32>((uint32_t)data);
-XDest2 = sext<32>(data >> 32);
+XDest = isBigEndian64(xc->tcBase())
+? sext<32>(data >> 32)
+: sext<32>((uint32_t)data);
+XDest2 = isBigEndian64(xc->tcBase())
+ ? sext<32>((uint32_t)data)
+ : sext<32>(data >> 32);
 '''
 elif self.size == 8:
 accCode = '''
-XDest = Mem_tud[0];
-XDest2 = Mem_tud[1];
+XDest = cSwap(Mem_tud[0],
+  isBigEndian64(xc->tcBase()));
+XDest2 = cSwap(Mem_tud[1],
+   isBigEndian64(xc->tcBase()));
 '''
 else:
 if self.size == 4:
 accCode = '''
 uint64_t data = cSwap(Mem_ud,

isBigEndian64(xc->tcBase()));

-XDest = (uint32_t)data;
-XDest2 = data >> 32;
+XDest = isBigEndian64(xc->tcBase())
+? (data >> 32)
+: (uint32_t)data;
+XDest2 = isBigEndian64(xc->tcBase())
+? (uint32_t)data
+  

[gem5-dev] Change in public/gem5[master]: dev: Remove unused interrupt controller in Terminal

[Andreas Sandberg (Gerrit)]

Hello Giacomo Travaglini,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/8141

to review the following change.


Change subject: dev: Remove unused interrupt controller in Terminal
..

dev: Remove unused interrupt controller in Terminal

Change-Id: I412d0b5edf2a08217792fa2ed1e511c17d3d31d4
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/serial/Terminal.py
M src/dev/serial/terminal.hh
2 files changed, 0 insertions(+), 2 deletions(-)



diff --git a/src/dev/serial/Terminal.py b/src/dev/serial/Terminal.py
index 863c487..8644916 100644
--- a/src/dev/serial/Terminal.py
+++ b/src/dev/serial/Terminal.py
@@ -34,7 +34,6 @@
 class Terminal(SerialDevice):
 type = 'Terminal'
 cxx_header = "dev/serial/terminal.hh"
-intr_control = Param.IntrControl(Parent.any, "interrupt controller")
 port = Param.TcpPort(3456, "listen port")
 number = Param.Int(0, "terminal number")
 output = Param.Bool(True, "Enable output dump to file")
diff --git a/src/dev/serial/terminal.hh b/src/dev/serial/terminal.hh
index 48bfc07..9e114de 100644
--- a/src/dev/serial/terminal.hh
+++ b/src/dev/serial/terminal.hh
@@ -42,7 +42,6 @@
 #include "base/circlebuf.hh"
 #include "base/pollevent.hh"
 #include "base/socket.hh"
-#include "cpu/intr_control.hh"
 #include "dev/serial/serial.hh"
 #include "params/Terminal.hh"
 #include "sim/sim_object.hh"

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Gerrit-Change-Number: 8141
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[gem5-dev] Change in public/gem5[master]: arch-arm: Add aarch64 semihosting support

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris, Giacomo Travaglini,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/8147

to review the following change.


Change subject: arch-arm: Add aarch64 semihosting support
..

arch-arm: Add aarch64 semihosting support

Add basic support for Arm Semihosting 2.0 simulation calls [1]. These
calls let the guest system call a simulator or debugger to request
OS-like support when running bare metal code.

With the exception of SYS_SYSTEM, this implementation supports all of
the Semihosting 2.0 specification in aarch64.

[1] https://developer.arm.com/docs/100863/latest/preface

Change-Id: I08c153c18a4a4fb9f95d318e2a029724935192a7
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
---
A src/arch/arm/ArmSemihosting.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/SConscript
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/misc64.isa
A src/arch/arm/semihosting.cc
A src/arch/arm/semihosting.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
9 files changed, 1,419 insertions(+), 4 deletions(-)



diff --git a/src/arch/arm/ArmSemihosting.py b/src/arch/arm/ArmSemihosting.py
new file mode 100644
index 000..1da4c49
--- /dev/null
+++ b/src/arch/arm/ArmSemihosting.py
@@ -0,0 +1,56 @@
+# Copyright (c) 2018 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.params import *
+from m5.SimObject import *
+
+from Serial import SerialDevice
+from Terminal import Terminal
+
+class ArmSemihosting(SimObject):
+type = 'ArmSemihosting'
+cxx_header = "arch/arm/semihosting.hh"
+
+cmd_line = Param.String("", "Command line to report to guest");
+
+mem_reserve = Param.MemorySize("32MB",
+"Amount of memory to reserve at the start of the address map.  
This "

+"memory won't be used by the heap reported to an application.");
+stack_size = Param.MemorySize("32MB", "Application stack size");
+
+time = Param.Time('01/01/2009',
+  "System time to use ('Now' for actual time)")
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 5687477..ec44331 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -41,6 +41,7 @@
 from m5.util.fdthelper import *

 from System import System
+from ArmSemihosting import ArmSemihosting

 class ArmMachineType(Enum):
 map = {
@@ -79,6 +80,9 @@
 have_large_asid_64 = Param.Bool(False,
 "True if ASID is 16 bits in AArch64 (ARMv8)")

+semihosting = Param.ArmSemihosting(NULL,
+"Enable support for the Arm semihosting by settings this  
parameter")

+
 m5ops_base = Pa

[gem5-dev] Change in public/gem5[master]: arch-arm: Decode Brk64 instructions

[Andreas Sandberg (Gerrit)]

Hello Giacomo Travaglini,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/8142

to review the following change.


Change subject: arch-arm: Decode Brk64 instructions
..

arch-arm: Decode Brk64 instructions

The brk instruction in aarch64 was decoded as an unimplemented
instruction. Fix that.

Change-Id: I3eb36a016ab56d882426c5cdef3a0b594de0f9cd
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/isa/formats/aarch64.isa
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 0179f2f..0cb8e9c 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -254,7 +254,7 @@
   case 0x03:
 return new Smc64(machInst);
   case 0x04:
-return new FailUnimplemented("brk", machInst);
+return new Brk64(machInst);
   case 0x08:
 return new FailUnimplemented("hlt", machInst);
   case 0x15:

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[gem5-dev] Change in public/gem5[master]: arch-arm: Fix big endian support in do{Long, L1, L2}Descriptor

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/8144



Change subject: arch-arm: Fix big endian support in do{Long,L1,L2}Descriptor
..

arch-arm: Fix big endian support in do{Long,L1,L2}Descriptor

do{Long,L1,L2}Descriptor was not able to load descriptors
correctly for big-endian situations, causing recognised
Descriptors.
Added big-endian related data conversions to correct them.

Change-Id: I0fdfbbdf56f94bbed19172acae1b6e4a0382b5a0
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/arch/arm/table_walker.cc
M src/arch/arm/utility.hh
M src/sim/byteswap.hh
3 files changed, 18 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 428556b..3c79e43 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -1423,6 +1423,9 @@
 return;
 }

+currState->l1Desc.data = htog(currState->l1Desc.data,
+  byteOrder(currState->tc));
+
 DPRINTF(TLB, "L1 descriptor for %#x is %#x\n",
 currState->vaddr_tainted, currState->l1Desc.data);
 TlbEntry te;
@@ -1518,6 +1521,9 @@
 return;
 }

+currState->longDesc.data = htog(currState->longDesc.data,
+byteOrder(currState->tc));
+
 DPRINTF(TLB, "L%d descriptor for %#llx is %#llx (%s)\n",
 currState->longDesc.lookupLevel, currState->vaddr_tainted,
 currState->longDesc.data,
@@ -1709,6 +1715,9 @@
 return;
 }

+currState->l2Desc.data = htog(currState->l2Desc.data,
+  byteOrder(currState->tc));
+
 DPRINTF(TLB, "L2 descriptor for %#x is %#x\n",
 currState->vaddr_tainted, currState->l2Desc.data);
 TlbEntry te;
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 8efe4ad..53431b9 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -348,6 +348,11 @@
  */
 uint8_t encodePhysAddrRange64(int pa_size);

+inline ByteOrder byteOrder(ThreadContext *tc)
+{
+return isBigEndian64(tc)?BigEndianByteOrder:LittleEndianByteOrder;
+};
+
 }

 #endif
diff --git a/src/sim/byteswap.hh b/src/sim/byteswap.hh
index 2c3517f..4ed1f20 100644
--- a/src/sim/byteswap.hh
+++ b/src/sim/byteswap.hh
@@ -153,6 +153,10 @@
 #else
 #error Invalid Endianess
 #endif
+template  inline T htog(T value, ByteOrder guest_byte_order)
+{return (guest_byte_order==BigEndianByteOrder) ? htobe(value) :  
htole(value);}

+template  inline T gtoh(T value, ByteOrder guest_byte_order)
+{return (guest_byte_order==BigEndianByteOrder) ? betoh(value) :  
letoh(value);}


 namespace BigEndianGuest
 {

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[gem5-dev] Change in public/gem5[master]: arch-arm: Add support for automatic reset addr selection

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/8143

to review the following change.


Change subject: arch-arm: Add support for automatic reset addr selection
..

arch-arm: Add support for automatic reset addr selection

Add an option to automatically set the aarch64 reset vector to the
entry point of the kernel. This is useful when running bare metal
workloads that don't use a normal boot loader.x

Change-Id: Id472f865d461f0d8d8ea8efe5db582c170de0b90
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrie...@arm.com>
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/system.cc
2 files changed, 7 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index f76140b..5687477 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2009, 2012-2013, 2015-2017 ARM Limited
+# Copyright (c) 2009, 2012-2013, 2015-2018 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -72,6 +72,8 @@
 reset_addr_64 = Param.Addr(0x0,
 "Reset address if the highest implemented exception level is 64  
bits "

 "(ARMv8)")
+auto_reset_addr_64 = Param.Bool(False,
+"Determine reset address from kernel entry point if no boot  
loader")

 phys_addr_range_64 = Param.UInt8(40,
 "Supported physical address range in bits when using AArch64  
(ARMv8)")

 have_large_asid_64 = Param.Bool(False,
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 097a87b..50ac4ae 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2015,2017 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2015,2017-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -62,7 +62,9 @@
   _haveVirtualization(p->have_virtualization),
   _genericTimer(nullptr),
   _highestELIs64(p->highest_el_is_64),
-  _resetAddr64(p->reset_addr_64),
+  _resetAddr64(p->auto_reset_addr_64 ?
+   (kernelEntry & loadAddrMask) + loadAddrOffset :
+   p->reset_addr_64),
   _physAddrRange64(p->phys_addr_range_64),
   _haveLargeAsid64(p->have_large_asid_64),
   _m5opRange(p->m5ops_base ?

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[gem5-dev] Change in public/gem5[master]: mem: Add PortProxy read/write helper with explicit endianness

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris, Giacomo Travaglini,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/8146

to review the following change.


Change subject: mem: Add PortProxy read/write helper with explicit  
endianness

..

mem: Add PortProxy read/write helper with explicit endianness

Change-Id: Ia9a11ca68b2892dafd02f2c37324b99b35c77d34
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
---
M src/mem/port_proxy.hh
1 file changed, 32 insertions(+), 1 deletion(-)



diff --git a/src/mem/port_proxy.hh b/src/mem/port_proxy.hh
index e9ddeec..ac1873b 100644
--- a/src/mem/port_proxy.hh
+++ b/src/mem/port_proxy.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013 ARM Limited
+ * Copyright (c) 2011-2013, 2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -123,6 +123,20 @@
 template 
 void write(Addr address, T data) const;

+/**
+ * Read sizeof(T) bytes from address and return as object T.
+ * Performs selected endianness transform.
+ */
+template 
+T readGtoH(Addr address, ByteOrder guest_byte_order) const;
+
+/**
+ * Write object T to address. Writes sizeof(T) bytes.
+ * Performs selected endianness transform.
+ */
+template 
+void writeHtoG(Addr address, T data, ByteOrder guest_byte_order) const;
+
 #if THE_ISA != NULL_ISA
 /**
  * Read sizeof(T) bytes from address and return as object T.
@@ -157,6 +171,23 @@
 writeBlob(address, (uint8_t*), sizeof(T));
 }

+template 
+T
+PortProxy::readGtoH(Addr address, ByteOrder byte_order) const
+{
+T data;
+readBlob(address, (uint8_t*), sizeof(T));
+return gtoh(data, byte_order);
+}
+
+template 
+void
+PortProxy::writeHtoG(Addr address, T data, ByteOrder byte_order) const
+{
+data = htog(data, byte_order);
+writeBlob(address, (uint8_t*), sizeof(T));
+}
+
 #if THE_ISA != NULL_ISA
 template 
 T

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[gem5-dev] Change in public/gem5[master]: stats: Add beta support for HDF5 stat dumps

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/8121

to review the following change.


Change subject: stats: Add beta support for HDF5 stat dumps
..

stats: Add beta support for HDF5 stat dumps

This changeset add support for stat dumps in the HDF5 file
format. HDF5 is a binary data format that represents data in a
file-system-like balanced tree. It has native support for
N-dimensional arrays and binary data (e.g., frame buffers).

It has the following benefits over traditional text stat files:

  * Efficient storage of time series (multiple stat dumps)

  * Fast lookup of stats

  * Plenty of existing tooling (e.g., Python libraries and graphical
viewers)

  * File format can be used to store frame buffers together with
normal stats.

Drawbacks:

  * Large startup cost (single stat dump larger than text equivalent)

  * Stat dumps are slower than text

Known limitations:

  * Inferred stat paths don't always match the object hierarchy since
they are inferred from the stat name. Fixing this would require a
significant stat framework refactor. This means that the file
format isn't entirely stable.

  * Distributions and histograms aren't supported.

HDF5 stat output can be enabled using the 'h5' URL scheme when
overriding the stat file name on gem5's command line. The following
parameters are supported:

  * chunking (unsigned): Number of time steps to pre-allocate
(default: 10)

  * desc (bool): Output stat descriptions (default: True)

  * formulas (bool): Output derived stats (default: True)

Example gem5 command line:

./build/ARM/gem5.opt \
  --stats-file="h5://stats.h5?desc=False;formulas=False" \
  configs/example/fs.py

Example Python stat consumer that computes IPC:
  import h5py

  f = h5py.File('stats.h5', 'r')
  group = f['/system/cpu']
  for i, c in zip(group['committedInsts'], group['numCycles']):
  print i, c, i / c

Change-Id: I351c6cbff2fb7bef9012f47876ba227ed288975b
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
---
M SConstruct
M src/base/SConscript
A src/base/stats/hdf5.cc
A src/base/stats/hdf5.hh
M src/python/m5/stats/__init__.py
M src/python/pybind11/stats.cc
6 files changed, 497 insertions(+), 5 deletions(-)



diff --git a/SConstruct b/SConstruct
index df647e7..ff13911 100755
--- a/SConstruct
+++ b/SConstruct
@@ -1,6 +1,6 @@
 # -*- mode:python -*-

-# Copyright (c) 2013, 2015-2017 ARM Limited
+# Copyright (c) 2013, 2015-2018 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -901,6 +901,15 @@
 main['HAVE_PERF_ATTR_EXCLUDE_HOST'] = conf.CheckMember(
 'linux/perf_event.h', 'struct perf_event_attr', 'exclude_host')

+have_hdf5 = \
+conf.CheckLibWithHeader('hdf5', 'hdf5.h', 'C',
+'H5Fcreate("", 0, 0, 0);') and \
+conf.CheckLibWithHeader('hdf5_cpp', 'H5Cpp.h', 'C++',
+'H5::H5File("", 0);')
+if not have_hdf5:
+print "Warning: Couldn't find any HDF5 C++ libraries. Disabling"
+print " HDF5 support."
+

 ##
 #
@@ -1003,14 +1012,15 @@
 EnumVariable('PROTOCOL', 'Coherence protocol for Ruby', 'None',
   all_protocols),
 EnumVariable('BACKTRACE_IMPL', 'Post-mortem dump implementation',
- backtrace_impls[-1], backtrace_impls)
+ backtrace_impls[-1], backtrace_impls),
+BoolVariable('USE_HDF5', 'Enable the HDF5 support', have_hdf5),
 )

 # These variables get exported to #defines in config/*.hh (see  
src/SConscript).
 export_vars +=  
['USE_FENV', 'SS_COMPATIBLE_FP', 'TARGET_ISA', 'TARGET_GPU_ISA',

 'CP_ANNOTATE', 'USE_POSIX_CLOCK', 'USE_KVM', 'USE_TUNTAP',
 'PROTOCOL', 'HAVE_PROTOBUF', 'HAVE_PERF_ATTR_EXCLUDE_HOST',
-'USE_PNG']
+'USE_PNG', 'USE_HDF5']

 ###
 #
diff --git a/src/base/SConscript b/src/base/SConscript
index a90b784..1f241c9 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -78,6 +78,8 @@
 Source('loader/symtab.cc')

 Source('stats/text.cc')
+if env['USE_HDF5']:
+Source('stats/hdf5.cc')

 GTest('bituniontest', 'bituniontest.cc')

diff --git a/src/base/stats/hdf5.cc b/src/base/stats/hdf5.cc
new file mode 100644
index 000..308bb10
--- /dev/null
+++ b/src/base/stats/hdf5.cc
@@ -0,0 +1,336 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware im

Re: [gem5-dev] Non-ISA specific use of ExtMachInst

[Andreas Sandberg]

On 23/01/2018 23:10, Gabe Black wrote:
Trimmed, responses inline.

On Tue, Jan 23, 2018 at 2:23 AM, Andreas Sandberg 
<andreas.sandb...@arm.com<mailto:andreas.sandb...@arm.com>> wrote:
On 22/01/2018 23:53, Gabe Black wrote:

It isn't really undermining the idea of having multiple ISAs in the same binary. The 
biggest "problem" is that you won't be able to use a detailed timing model for 
one ISA with another ISA. That's probably fine though. I'm pretty sure it would be hard 
to make a timing model that is realistic for both Arm and x86 given that we most likely 
classify instructions in slightly different ways.

It's problematic to have features which fundamentally don't work for a particular 
ISA, although that's not what I'm talking about. I'm talking about the #ifdef which 
is based on the arch since the X86 ExtMachInst can't be &-ed against and won't 
compile that way.


A simple solution would be to just add create a instAsUint32 method in the static 
instruction interface and stub that on x86. The code would "just work" in that 
case, but it would be a bit ugly.


The problem is that different microarchitectures would need different 
classifications (i.e., different uarchs route the same instruction to 
differently) and some instructions don't have fixed latencies (e.g., division). 
We could grow the number of instruction classes, but that probably won't scale 
since each new microarchitecture we want to model would need new instruction 
classes. Similarly, each time we implement a new divider (or some other clever 
gadget), we'd need to implement a custom timing model in C++.


Yeah, I mispoke when I said latencies. What I should have said was that the 
instructions would be classified into groups, and then those groups would be 
matched against by function units in the CPU model instead of using bitfields.

That should work. I think got lost in the latency calculation DSL that is 
actually completely independent of the instruction matcher.


Alternatively you could make your decoder programmable where it would take some 
sort of classifier which would apply groupings in the decoder itself? This 
would also make the CPU model more efficient since the instructions aren't 
going to change groups, but they still get reclassified every time the execute.

That's definitely a possibility, but if we make that classifier a part of the 
C++ world, we effectively encode parts of our timing models in C++. That would 
be highly undesirable and would make it a lot harder to make and distribute new 
custom timing models. This sort of mechanism could work if we make instruction 
classification programmable from Python and add the ability to define custom 
instruction classes in Python (I'm not sure how different it would be from what 
we do currently though). It wouldn't solve the issue for variable latency 
instructions though.


What I was thinking is that instead of having an pseudo ISA independent mechanism 
living in the CPU which is really a second decoder, you could have the same mechanism 
live in the ARM decoder and just tag instructions with groups. So instead of saying 
this unit works with instructions where i & 0xf = 0xa, you'd say instructions where 
i & 0xf = 0xa go in group 2, and function units 1, 3 and 5 act on group 2. Then the 
CPU model is generic since it's just operating on group numbers which are totally 
artificial and independent of ISA, and the ISA specific part (grouping instructions) is 
in the decoder which is already inherently very ISA dependent. By making an instance of 
the decoder programmable, the decoder for cpu X can be set up to group instructions 
different than cpu Y, and in an equivalent way to how cpu X's functional units used to 
claim instructions.

This sounds like a sensible design if we allow additional groups to be defined 
from the configuration script. We could probably do that by defining a 
model-specific range in the OpClass enum. We would also need to have a separate 
decoder and decoder cache instance per CPU instance if to be able to simulate 
multiple microarchitectures (e.g., a bL system) at the same time.

Cheers,
Andreas


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Re: [gem5-dev] Non-ISA specific use of ExtMachInst

[Andreas Sandberg]

On 22/01/2018 23:53, Gabe Black wrote:


On Mon, Jan 22, 2018 at 2:38 AM, Andreas Sandberg 
<andreas.sandb...@arm.com<mailto:andreas.sandb...@arm.com>> wrote:
Hi Gabe,


On 21/01/2018 06:34, Gabe Black wrote:
Hi folks. ExtMachInst is a type which is defined per ISA, and is *almost*
not used outside of ISA specific code. The three uses for it that I see
right now are as a type in the decode cache when decoding instructions, the
protobuf based instruction tracer, and the MinorCPU.

The decode cache is tightly bound to the decode function which is already
highly ISA dependent, so I don't forsee a big problem pushing those
together and handling them at the same time.

Sounds reasonable. Except for detailed arch-specific timing models and
debugging, there should be little need to expose the encoding in the
pipeline.

A simple solution would be to just use a 64-bit ExtMachInst
representation in the StaticInst interface and just stub it for x86.
That would retain existing functionality and wouldn't be particularly
intrusive.


That would be an improvement, but I really want to avoid having features which 
are fundamentally incompatible with certain ISAs like that. That's opposed to 
features which just might not be implemented yet but which could with some 
straightforward and reasonable amount of effort.




The protobuf tracer unfortunately stores a raw 32 bit integer value to
record what the instruction was, and this field is required. I'd like to
make this field optional, and to also add an optional byte array which can
be used to store instructions which don't fit neatly into a 32 bit integer.
This shouldn't affect the efficiency of the protobuf format as it's used
today, it would just enable its use in more places. Also, the protobuf
tracer would need to call, say, a virtual function to encode the
instruction in whatever way is appropriate. Alternatively, all instructions
could be encoded as an array of bytes which would make that interface more
generic. It would be, I think, one byte less efficient storage wise when
storing instructions that are consistently 32 bits, but would be more
efficient for 16 bit instructions and equivalent for ones that would be
forced to use an array of bytes anyway.

Another option would be to completely remove the encoding from the Inst
message and add a add architecture-specific Encoding messages (possibly
using PB's extensions mechanism to extend Inst). Unfortunately, this has
the potentially make the code ugly if we want to maintain PB as an
optional dependency.


Yeah, I was thinking of how to avoid making this a protobuf tracer specific 
aspect of each StaticInst flavor. My best idea so far is to add a function 
which generically serializes an instruction as a sequence of bytes, and then 
use that to fill in the protobuf. If there are exactly 4 bytes returned, then 
you can use the old format which would be slightly more efficient. If there are 
more or less, then you'd use the new byte array version. That could also 
theoretically be used for other things like serializing inflight instructions 
or something, although realistically it would just be to loosen the coupling to 
the protobuf tracer in the foreseeable future.

This sounds like a good option and could be used to drive the instruction 
matcher in Minor. I'm not sure how it would affect performance compared to 
using a fixed-size ExtMachInst, but it probably isn't that bad.



The MinorCPU really should not be reaching into instructions and looking at
their bytes. The idea that there's necessarily some sort of mask and
compare that can be done to determine what type of operation an instruction
is is very fragile, not only because it assumes those operations make
sense, but also that the instructions actually have such a pattern. This is
evidenced by the fact that there's already an #ifdef around this bit of
code.

We actually make extensive use of this functionality. Take the HPI core
model in configs/common/cores/arm as an example. In order to get good
correlation against existing in-order Arm cores, we use the bit matching
functionality to route instructions to FUs and assign latencies to
individual instructions. This has allowed us to achieve much tighter
correlation against existing in-order cores than what we could achieve

Latencies and FU routing has traditionally been done using instruction
classes in gem5. However, because different cores classify instructions
in slightly different ways, this would make the ISA code timing model
specific. This is clearly undesirable.

Is the MinorCPU used? The easiest thing to do would be to nuke it, but if
anyone is using it or is particularly attached to it we should try to keep
it. Alternatively, the interesting bits could be returned by a virtual
function on the StaticInst object. This still assumes that there's some
sort of magical pattern to mask and compare against, but at least it will
compile for everything and hides the ExtMachInst type within the

Re: [gem5-dev] Non-ISA specific use of ExtMachInst

[Andreas Sandberg]

Hi Gabe,


On 21/01/2018 06:34, Gabe Black wrote:

Hi folks. ExtMachInst is a type which is defined per ISA, and is *almost*
not used outside of ISA specific code. The three uses for it that I see
right now are as a type in the decode cache when decoding instructions, the
protobuf based instruction tracer, and the MinorCPU.

The decode cache is tightly bound to the decode function which is already
highly ISA dependent, so I don't forsee a big problem pushing those
together and handling them at the same time.


Sounds reasonable. Except for detailed arch-specific timing models and
debugging, there should be little need to expose the encoding in the
pipeline.

A simple solution would be to just use a 64-bit ExtMachInst
representation in the StaticInst interface and just stub it for x86.
That would retain existing functionality and wouldn't be particularly
intrusive.


The protobuf tracer unfortunately stores a raw 32 bit integer value to
record what the instruction was, and this field is required. I'd like to
make this field optional, and to also add an optional byte array which can
be used to store instructions which don't fit neatly into a 32 bit integer.
This shouldn't affect the efficiency of the protobuf format as it's used
today, it would just enable its use in more places. Also, the protobuf
tracer would need to call, say, a virtual function to encode the
instruction in whatever way is appropriate. Alternatively, all instructions
could be encoded as an array of bytes which would make that interface more
generic. It would be, I think, one byte less efficient storage wise when
storing instructions that are consistently 32 bits, but would be more
efficient for 16 bit instructions and equivalent for ones that would be
forced to use an array of bytes anyway.


Another option would be to completely remove the encoding from the Inst
message and add a add architecture-specific Encoding messages (possibly
using PB's extensions mechanism to extend Inst). Unfortunately, this has
the potentially make the code ugly if we want to maintain PB as an
optional dependency.


The MinorCPU really should not be reaching into instructions and looking at
their bytes. The idea that there's necessarily some sort of mask and
compare that can be done to determine what type of operation an instruction
is is very fragile, not only because it assumes those operations make
sense, but also that the instructions actually have such a pattern. This is
evidenced by the fact that there's already an #ifdef around this bit of
code.


We actually make extensive use of this functionality. Take the HPI core
model in configs/common/cores/arm as an example. In order to get good
correlation against existing in-order Arm cores, we use the bit matching
functionality to route instructions to FUs and assign latencies to
individual instructions. This has allowed us to achieve much tighter
correlation against existing in-order cores than what we could achieve

Latencies and FU routing has traditionally been done using instruction
classes in gem5. However, because different cores classify instructions
in slightly different ways, this would make the ISA code timing model
specific. This is clearly undesirable.


Is the MinorCPU used? The easiest thing to do would be to nuke it, but if
anyone is using it or is particularly attached to it we should try to keep
it. Alternatively, the interesting bits could be returned by a virtual
function on the StaticInst object. This still assumes that there's some
sort of magical pattern to mask and compare against, but at least it will
compile for everything and hides the ExtMachInst type within the ISA.
Really, since we're already determining whether an instruction is a branch,
integer operation, etc., we should just use those flags and not try to
redecode the instruction in the CPU. That also leaks instruction encoding
into the configuration which makes that more fragile and ISA specialized as
well. Dealing with the MinorCPU is the part of this I most want feedback on.


The minor CPU is used a lot. It's the model you need to simulate a small
core in a bitLITTLE configuration. Unfortunately, we simply can't get
good enough correlation against existing designs if we use just the
instruction flags, so keeping the bit matching magic is a hard
requirement from our sides.

Cheers,
Andreas


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[gem5-dev] Change in public/gem5[master]: util: Add an option to specify paths in list_changes.py

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/7461 )


Change subject: util: Add an option to specify paths in list_changes.py
..

util: Add an option to specify paths in list_changes.py

Add an option to restrict change lists to changes that touch one or
more subdirectories in the source tree.

Change-Id: Id4e34fe300fdc3657505e2e188c727e583bcf611
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7461
Reviewed-by: Brandon Potter <brandon.pot...@amd.com>
---
M util/maint/list_changes.py
1 file changed, 12 insertions(+), 8 deletions(-)

Approvals:
  Brandon Potter: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/util/maint/list_changes.py b/util/maint/list_changes.py
index 78e4442..3d9be8d 100755
--- a/util/maint/list_changes.py
+++ b/util/maint/list_changes.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python2
 #
-# Copyright (c) 2017 ARM Limited
+# Copyright (c) 2017-2018 Arm Limited
 # All rights reserved
 #
 # The license below extends only to copyright in the software and shall
@@ -105,7 +105,7 @@
 def __str__(self):
 return "%s: %s" % (self.rev[0:8], self.log[0])

-def list_revs(branch, baseline=None):
+def list_revs(branch, baseline=None, paths=[]):
 """Get a generator that lists git revisions that exist in 'branch'. If
 the optional parameter 'baseline' is specified, the generator
 excludes commits that exist on that branch.
@@ -119,7 +119,9 @@
 else:
 query = str(branch)

-changes = subprocess.check_output([ "git", "rev-list", query ])
+changes = subprocess.check_output(
+[ "git", "rev-list", query, '--'] + paths
+)

 if changes == "":
 return
@@ -128,9 +130,9 @@
 assert rev != ""
 yield Commit(rev)

-def list_changes(upstream, feature):
-feature_revs = tuple(list_revs(upstream, feature))
-upstream_revs = tuple(list_revs(feature, upstream))
+def list_changes(upstream, feature, paths=[]):
+feature_revs = tuple(list_revs(upstream, feature, paths=paths))
+upstream_revs = tuple(list_revs(feature, upstream, paths=paths))

 feature_cids = dict([
 (c.change_id, c) for c in feature_revs if c.change_id is not None  
])

@@ -173,11 +175,13 @@
 parser.add_argument("--deep-search", action="store_true",
 help="Use a deep search to find incorrectly " \
 "rebased changes")
+parser.add_argument("paths", metavar="PATH", type=str, nargs="*",
+help="Paths to list changes for")

 args = parser.parse_args()

 incoming, outgoing, common, upstream_unknown, feature_unknown = \
-list_changes(args.upstream, args.feature)
+list_changes(args.upstream, args.feature, paths=args.paths)

 if incoming:
 print "Incoming changes:"
@@ -210,7 +214,7 @@

 if args.deep_search:
 print "Incorrectly rebased changes:"
-all_upstream_revs = list_revs(args.upstream)
+all_upstream_revs = list_revs(args.upstream, paths=args.paths)
 all_upstream_cids = dict([
 (c.change_id, c) for c in all_upstream_revs \
 if c.change_id is not None ])

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Id4e34fe300fdc3657505e2e188c727e583bcf611
Gerrit-Change-Number: 7461
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Brandon Potter <brandon.pot...@amd.com>
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[gem5-dev] Change in public/gem5[master]: util: Add an option to specify paths in list_changes.py

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/7461



Change subject: util: Add an option to specify paths in list_changes.py
..

util: Add an option to specify paths in list_changes.py

Add an option to restrict change lists to changes that touch one or
more subdirectories in the source tree.

Change-Id: Id4e34fe300fdc3657505e2e188c727e583bcf611
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu@arm.com>
---
M util/maint/list_changes.py
1 file changed, 12 insertions(+), 8 deletions(-)



diff --git a/util/maint/list_changes.py b/util/maint/list_changes.py
index 78e4442..3d9be8d 100755
--- a/util/maint/list_changes.py
+++ b/util/maint/list_changes.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python2
 #
-# Copyright (c) 2017 ARM Limited
+# Copyright (c) 2017-2018 Arm Limited
 # All rights reserved
 #
 # The license below extends only to copyright in the software and shall
@@ -105,7 +105,7 @@
 def __str__(self):
 return "%s: %s" % (self.rev[0:8], self.log[0])

-def list_revs(branch, baseline=None):
+def list_revs(branch, baseline=None, paths=[]):
 """Get a generator that lists git revisions that exist in 'branch'. If
 the optional parameter 'baseline' is specified, the generator
 excludes commits that exist on that branch.
@@ -119,7 +119,9 @@
 else:
 query = str(branch)

-changes = subprocess.check_output([ "git", "rev-list", query ])
+changes = subprocess.check_output(
+[ "git", "rev-list", query, '--'] + paths
+)

 if changes == "":
 return
@@ -128,9 +130,9 @@
 assert rev != ""
 yield Commit(rev)

-def list_changes(upstream, feature):
-feature_revs = tuple(list_revs(upstream, feature))
-upstream_revs = tuple(list_revs(feature, upstream))
+def list_changes(upstream, feature, paths=[]):
+feature_revs = tuple(list_revs(upstream, feature, paths=paths))
+upstream_revs = tuple(list_revs(feature, upstream, paths=paths))

 feature_cids = dict([
 (c.change_id, c) for c in feature_revs if c.change_id is not None  
])

@@ -173,11 +175,13 @@
 parser.add_argument("--deep-search", action="store_true",
 help="Use a deep search to find incorrectly " \
 "rebased changes")
+parser.add_argument("paths", metavar="PATH", type=str, nargs="*",
+help="Paths to list changes for")

 args = parser.parse_args()

 incoming, outgoing, common, upstream_unknown, feature_unknown = \
-list_changes(args.upstream, args.feature)
+list_changes(args.upstream, args.feature, paths=args.paths)

 if incoming:
 print "Incoming changes:"
@@ -210,7 +214,7 @@

 if args.deep_search:
 print "Incorrectly rebased changes:"
-all_upstream_revs = list_revs(args.upstream)
+all_upstream_revs = list_revs(args.upstream, paths=args.paths)
 all_upstream_cids = dict([
 (c.change_id, c) for c in all_upstream_revs \
 if c.change_id is not None ])

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id4e34fe300fdc3657505e2e188c727e583bcf611
Gerrit-Change-Number: 7461
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
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Re: [gem5-dev] Using branching in gem5 public

[Andreas Sandberg]

Hi Tony,

Both you and Brad should have the necessary admin bits to create new
projects. You can create a new project from the review system. The
parent directory ('arm' in our case) should be created with 'Only serve
as parent for other projects' set and inherit permissions from
All-Projects. You can then change the configuration in your parent
project to suit your needs. A small gotcha is that you shouldn't include
a leading slash in the project name (e.g., our gem5 repo is called
arm/gem5).

We ended up adding a separate group of users that have rights to push
directly to the repo and require a member of that group to set the
maintainer flags when other users submit code. You can use our config
[1] as a starting point if you need something similar.

Cheers,
Andreas

[1] https://gem5.googlesource.com/arm/+/refs/meta/config


On 19/12/2017 17:06, Gutierrez, Anthony wrote:

Hi Andreas,

This all makes sense, and I think for our purposes a separate AMD/ repo similar 
to ARM's setup (option 1 as you say) would be perfect for us. Do you have 
permissions to create a new repo for AMD? Or can you give me permissions to do 
so?

Thanks,
Tony

-Original Message-
From: Andreas Sandberg [mailto:andreas.sandb...@arm.com]
Sent: Thursday, December 14, 2017 10:01 AM
To: gem5 Developer List <gem5-dev@gem5.org>; Gutierrez, Anthony 
<anthony.gutier...@amd.com>
Subject: Re: [gem5-dev] Using branching in gem5 public

Hi Tony,

I'm generally all for using branches, we use them extensively internally. IMO, 
the options we have in gerrit for what both of us are trying to accomplish, us 
with SVE and you with the GPU, are as follows:

1. We create different repositories per user / institution and push between 
repos.
2. We create branch "namespaces" in the main repo (e.g., arm/**, amd/**,
users/a.hacker/**)

Gerrit is able to handle permissions and policies (e.g., whether some users can 
push without review and who is allowed to review) per branch as well as per 
repo. There are some differences in what you can do and how you do it, but in 
general, they are roughly equivalent when it comes to permissions.

We obviously already went with option one. The main benefit, as I see it, of 
this option is that we don't pollute the branch namespace with pre-release 
changes. I would argue that this option scales a bit better in terms of 
usability as well. Once you start having a lot of working branches, cloning the 
repo will be pretty annoying. The Linux uses a similar strategy and most 
well-known kernel devs have their own repos on git.kernel.org and Linus curates 
the master repo.

Cheers,
Andreas

On 14/12/2017 16:29, Gutierrez, Anthony wrote:

Hi All,

I have a question about using branches in the mainline gem5 repo. I see ARM 
have a separate repo here: 
https://gem5-review.googlesource.com/admin/projects/arm/gem5. It is used for 
staging ARM features under development. At AMD we would like to do something 
similar, as we have some significant changes to the GPU model we would like to 
push out to the public. We were thinking about doing so with branches, and were 
wondering what others thought about branches? I'm sure it's been discussed 
somewhat in the past, but I can't find much searching through old posts.

What I was thinking would be to have institutional branches, like AMD or ARM 
branches, and perhaps users from those institutions who are also gem5 
maintainers could have user specific branches. We use branches a lot internally 
and find them extremely useful. So I'd like to get a better idea why there is 
an aversion to using branches on the public tree, if there is such an aversion.

-Tony
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[gem5-dev] Change in public/gem5[master]: cpu-tester: Added ExitGen to TrafficGen

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5723 )


Change subject: cpu-tester: Added ExitGen to TrafficGen
..

cpu-tester: Added ExitGen to TrafficGen

Added the ExitGen to the TrafficGenerator which allows an EXIT
state to be added to the TrafficGen configuration file. Entering this
state will cause the simulation to exit immediately. Please note that
if multiple TrafficGen instances have an EXIT state, the first of these
to be encountered will cause the simulation to terminate.

Change-Id: Ieea51f05ffb780771f007787a2b119f79143d0c1
Reviewed-by: Sascha Bischoff <sascha.bisch...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5723
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/cpu/testers/traffic_gen/SConscript
A src/cpu/testers/traffic_gen/exit_gen.cc
A src/cpu/testers/traffic_gen/exit_gen.hh
M src/cpu/testers/traffic_gen/traffic_gen.cc
M src/cpu/testers/traffic_gen/traffic_gen.hh
5 files changed, 143 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/cpu/testers/traffic_gen/SConscript  
b/src/cpu/testers/traffic_gen/SConscript

index d73819b..74d0279 100644
--- a/src/cpu/testers/traffic_gen/SConscript
+++ b/src/cpu/testers/traffic_gen/SConscript
@@ -47,6 +47,7 @@
 Source('base_gen.cc')
 Source('dram_gen.cc')
 Source('dram_rot_gen.cc')
+Source('exit_gen.cc')
 Source('idle_gen.cc')
 Source('linear_gen.cc')
 Source('random_gen.cc')
diff --git a/src/cpu/testers/traffic_gen/exit_gen.cc  
b/src/cpu/testers/traffic_gen/exit_gen.cc

new file mode 100644
index 000..8a07160
--- /dev/null
+++ b/src/cpu/testers/traffic_gen/exit_gen.cc
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Riken Gohil
+ */
+
+#include "base/misc.hh"
+#include "base/trace.hh"
+#include "debug/TrafficGen.hh"
+#include "exit_gen.hh"
+#include "sim/sim_exit.hh"
+
+void
+ExitGen::enter()
+{
+DPRINTF(TrafficGen, "%s has encountered the exit state and will "
+"terminate the simulation.\n", name());
+exitSimLoop(name() + " has encountered the exit state and will "
+"terminate the simulation.\n");
+}
+
+PacketPtr
+ExitGen::getNextPacket()
+{
+panic("Simulation should have exited");
+return NULL;
+}
+
+Tick
+ExitGen::nextPacketTick(bool elastic, Tick delay) const
+{
+return MaxTick;
+}
diff --git a/src/cpu/testers/traffic_gen/exit_gen.hh  
b/src/cpu/testers/traffic_gen/exit_gen.hh

new file mode 100644
index 000..45087e6
--- /dev/null
+++ b/src/cpu/testers/t

Re: [gem5-dev] A bug in src/cpu/BaseCPU.py

[Andreas Sandberg]

Hi David,

We removed the default ISA instance from the isa param and update the
code in createThreads() to avoid a bug where custom CPU models can't
override the ISA correctly. The createThreads() helper is designed to
create the appropriate number of ISAs for an MT core if they haven't
been instantiated manually. Configuration scripts are expected to call
cpu.createThreads() on /all/ (this includes swithced out CPUs) before
instantiating the C++ world.

Asutin Harris recently contributed a change to the example configuration
script that makes the switched out CPUs use the same ISA instances as
the main CPUs (config: Fix need to set ISA of switch cpus.). Make sure
that you have this commit in your repository since this fixes CPU
switching issues in these scripts. If you are using your own
configuration scripts, you need to make sure that you call
cpu.createThreads() for all of the CPUs.

Cheers,
Andreas

On 18/12/2017 17:58, David Kim wrote:

Hello,

I think there is a bug in src/cpu/BaseCPU.py, which results in the failure
to add the appropriate 'isa' information in 'switch_cpus' parameters.
Because of this, when '-r' option is added to the commandline (restoring
from checkpoint), the isa section of the 'switch_cpus' parameters in the
config.ini file (under output directory, e.g. m5out) becomes empty so it
prevents from restoring gem5 from checkpoint.

I have checked the same file of the older repository, and found the recent
BaseCPU.py creates isa instance with 'empty' list while previous one did
with 'isa_class.'

Here is my suggested update.

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index d174f274a..18d9a6d3e 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -167,24 +167,24 @@ class BaseCPU(MemObject):
  itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
  interrupts = VectorParam.SparcInterrupts(
  [], "Interrupt Controller")
-isa = VectorParam.SparcISA([], "ISA instance")
+isa = VectorParam.SparcISA([ default_isa_class() ], "ISA instance")
  elif buildEnv['TARGET_ISA'] == 'alpha':
  dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
  itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
  interrupts = VectorParam.AlphaInterrupts(
  [], "Interrupt Controller")
-isa = VectorParam.AlphaISA([], "ISA instance")
+isa = VectorParam.AlphaISA([ default_isa_class() ], "ISA instance")
  elif buildEnv['TARGET_ISA'] == 'x86':
  dtb = Param.X86TLB(X86TLB(), "Data TLB")
  itb = Param.X86TLB(X86TLB(), "Instruction TLB")
  interrupts = VectorParam.X86LocalApic([], "Interrupt Controller")
-isa = VectorParam.X86ISA([], "ISA instance")
+isa = VectorParam.X86ISA([ default_isa_class() ], "ISA instance")
  elif buildEnv['TARGET_ISA'] == 'mips':
  dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
  itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
  interrupts = VectorParam.MipsInterrupts(
  [], "Interrupt Controller")
-isa = VectorParam.MipsISA([], "ISA instance")
+isa = VectorParam.MipsISA([ default_isa_class() ], "ISA instance")
  elif buildEnv['TARGET_ISA'] == 'arm':
  dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
  itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
@@ -192,20 +192,20 @@ class BaseCPU(MemObject):
  dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
  interrupts = VectorParam.ArmInterrupts(
  [], "Interrupt Controller")
-isa = VectorParam.ArmISA([], "ISA instance")
+isa = VectorParam.ArmISA([ default_isa_class() ], "ISA instance")
  elif buildEnv['TARGET_ISA'] == 'power':
  UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
  dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
  itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
  interrupts = VectorParam.PowerInterrupts(
  [], "Interrupt Controller")
-isa = VectorParam.PowerISA([], "ISA instance")
+isa = VectorParam.PowerISA([ default_isa_class() ], "ISA instance")
  elif buildEnv['TARGET_ISA'] == 'riscv':
  dtb = Param.RiscvTLB(RiscvTLB(), "Data TLB")
  itb = Param.RiscvTLB(RiscvTLB(), "Instruction TLB")
  interrupts = VectorParam.RiscvInterrupts(
  [], "Interrupt Controller")
-isa = VectorParam.RiscvISA([], "ISA instance")
+isa = VectorParam.RiscvISA([ default_isa_class() ], "ISA instance")
  else:
  print "Don't know what TLB to use for ISA %s" % \
  buildEnv['TARGET_ISA']

Thanks.

Regards,
Dong Wan Kim
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[gem5-dev] Change in public/gem5[master]: scons, tests: Fix occasional linking error

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/6641 )


Change subject: scons, tests: Fix occasional linking error
..

scons, tests: Fix occasional linking error

There are some cases where scons incorrectly adds the same object
multiple times to the linker command line. This seems to be caused by
the test's source list being updated in place when determining test
framework dependencies. Fix this by explicitly copying the source list
and manipulate the copy.

Without this change, the following command fails:
scons ./build/ARM/unittests.opt/base/pixeltest.xml

Whereas this command succeeds:
scons ./build/ARM/base/pixeltest.opt

Change-Id: I642efdf9d62a5478e49ba51efe1a3a5ba453e21f
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6641
Reviewed-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-by: Gabe Black <gabebl...@google.com>
---
M src/SConscript
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/SConscript b/src/SConscript
index a98fbc4..1c53160 100755
--- a/src/SConscript
+++ b/src/SConscript
@@ -1092,7 +1092,7 @@
 gtestlib_sources = Source.all.with_tag('gtest lib')
 gtest_out_dir = Dir(new_env['BUILDDIR']).Dir('unittests.%s' % label)
 for test in GTest.all:
-test_sources = test.sources
+test_sources = list(test.sources)
 if not test.skip_lib:
 test_sources += gtestlib_sources
 for f in test.filters:

--
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Gerrit-Branch: master
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Gerrit-Change-Id: I642efdf9d62a5478e49ba51efe1a3a5ba453e21f
Gerrit-Change-Number: 6641
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Assignee: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
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[gem5-dev] Change in public/gem5[master]: scons, tests: Add support for GTest XML generation

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/6624 )


Change subject: scons, tests: Add support for GTest XML generation
..

scons, tests: Add support for GTest XML generation

The GTest framework supports result generation in XML (JUnit). Enable
this by creating unit test specific targets in the
build/${BUILD_OPTS}/unittests.${VARIANT} directory. Targets in the
directory use the following naming convention:

${SRC_PATH}/${TEST_NAME}.xml

For example, the opt version of the bitunion test built for ARM would
have this path:

build/ARM/unittests.opt/base/bituniontest.xml

Change-Id: I174dff16817734db05b08ce1d5bcf52e8697bbac
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6624
Reviewed-by: Gabe Black <gabebl...@google.com>
---
M src/SConscript
1 file changed, 6 insertions(+), 5 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/SConscript b/src/SConscript
index 57a2d96..a98fbc4 100755
--- a/src/SConscript
+++ b/src/SConscript
@@ -1090,7 +1090,7 @@
 gtest_env.Append(LIBS=gtest_env['GTEST_LIBS'])
 gtest_env.Append(CPPFLAGS=gtest_env['GTEST_CPPFLAGS'])
 gtestlib_sources = Source.all.with_tag('gtest lib')
-gtests = []
+gtest_out_dir = Dir(new_env['BUILDDIR']).Dir('unittests.%s' % label)
 for test in GTest.all:
 test_sources = test.sources
 if not test.skip_lib:
@@ -1098,11 +1098,12 @@
 for f in test.filters:
 test_sources += Source.all.apply_filter(f)
 test_objs = [ s.static(gtest_env) for s in test_sources ]
-gtests.append(gtest_env.Program(
-test.dir.File('%s.%s' % (test.target, label)), test_objs))
+test_binary = gtest_env.Program(
+test.dir.File('%s.%s' % (test.target, label)), test_objs)

-gtest_target = Dir(new_env['BUILDDIR']).File('unittests.%s' % label)
-AlwaysBuild(gtest_env.Command(gtest_target, gtests, gtests))
+AlwaysBuild(gtest_env.Command(
+gtest_out_dir.File("%s/%s.xml" % (test.dir, test.target)),
+test_binary, "${SOURCES[0]} --gtest_output=xml:${TARGETS[0]}"))

 progname = exename
 if strip:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I174dff16817734db05b08ce1d5bcf52e8697bbac
Gerrit-Change-Number: 6624
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Assignee: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
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[gem5-dev] Change in public/gem5[master]: scons: Make sure GTests have the right environment variables

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/6623 )


Change subject: scons: Make sure GTests have the right environment variables
..

scons: Make sure GTests have the right environment variables

SCons currently scrubs the environment variables used by GTests too
aggressively. This breaks systems where libraries are installed in
non-standard locations that need to be specified in
LD_LIBRARY_PATH. Run said tests in the gtest_env SCons environment
which white-lists the important environment variables.

Change-Id: I5fc8fb5e51f09644dc976ee97b21c78ab349bf7d
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6623
Reviewed-by: Gabe Black <gabebl...@google.com>
---
M src/SConscript
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/SConscript b/src/SConscript
index 7cd7116..57a2d96 100755
--- a/src/SConscript
+++ b/src/SConscript
@@ -1102,7 +1102,7 @@
 test.dir.File('%s.%s' % (test.target, label)), test_objs))

 gtest_target = Dir(new_env['BUILDDIR']).File('unittests.%s' % label)
-AlwaysBuild(Command(gtest_target, gtests, gtests))
+AlwaysBuild(gtest_env.Command(gtest_target, gtests, gtests))

 progname = exename
 if strip:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I5fc8fb5e51f09644dc976ee97b21c78ab349bf7d
Gerrit-Change-Number: 6623
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Assignee: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
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[gem5-dev] Change in public/gem5[master]: scons, tests: Fix occasional linking error

[Andreas Sandberg (Gerrit)]

Hello Giacomo Travaglini,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/6641

to review the following change.


Change subject: scons, tests: Fix occasional linking error
..

scons, tests: Fix occasional linking error

There are some cases where scons incorrectly adds the same object
multiple times to the linker command line. This seems to be caused by
the test's source list being updated in place when determining test
framework dependencies. Fix this by explicitly copying the source list
and manipulate the copy.

Without this change, the following command fails:
scons ./build/ARM/unittests.opt/base/pixeltest.xml

Whereas this command succeeds:
scons ./build/ARM/base/pixeltest.opt

Change-Id: I642efdf9d62a5478e49ba51efe1a3a5ba453e21f
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
---
M src/SConscript
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/SConscript b/src/SConscript
index a98fbc4..1c53160 100755
--- a/src/SConscript
+++ b/src/SConscript
@@ -1092,7 +1092,7 @@
 gtestlib_sources = Source.all.with_tag('gtest lib')
 gtest_out_dir = Dir(new_env['BUILDDIR']).Dir('unittests.%s' % label)
 for test in GTest.all:
-test_sources = test.sources
+test_sources = list(test.sources)
 if not test.skip_lib:
 test_sources += gtestlib_sources
 for f in test.filters:

--
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Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I642efdf9d62a5478e49ba51efe1a3a5ba453e21f
Gerrit-Change-Number: 6641
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
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[gem5-dev] Change in public/gem5[master]: scons: Make sure GTests have the right environment variables

[Andreas Sandberg (Gerrit)]

Hello Giacomo Travaglini,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/6623

to review the following change.


Change subject: scons: Make sure GTests have the right environment variables
..

scons: Make sure GTests have the right environment variables

SCons currently scrubs the environment variables used by GTests too
aggressively. This breaks systems where libraries are installed in
non-standard locations that need to be specified in
LD_LIBRARY_PATH. Run said tests in the gtest_env SCons environment
which white-lists the important environment variables.

Change-Id: I5fc8fb5e51f09644dc976ee97b21c78ab349bf7d
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
---
M src/SConscript
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/SConscript b/src/SConscript
index 7cd7116..57a2d96 100755
--- a/src/SConscript
+++ b/src/SConscript
@@ -1102,7 +1102,7 @@
 test.dir.File('%s.%s' % (test.target, label)), test_objs))

 gtest_target = Dir(new_env['BUILDDIR']).File('unittests.%s' % label)
-AlwaysBuild(Command(gtest_target, gtests, gtests))
+AlwaysBuild(gtest_env.Command(gtest_target, gtests, gtests))

 progname = exename
 if strip:

--
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Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5fc8fb5e51f09644dc976ee97b21c78ab349bf7d
Gerrit-Change-Number: 6623
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
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[gem5-dev] Change in public/gem5[master]: scons, tests: Add support for GTest XML generation

[Andreas Sandberg (Gerrit)]

Hello Giacomo Travaglini,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/6624

to review the following change.


Change subject: scons, tests: Add support for GTest XML generation
..

scons, tests: Add support for GTest XML generation

The GTest framework supports result generation in XML (JUnit). Enable
this by creating unit test specific targets in the
build/${BUILD_OPTS}/unittests.${VARIANT} directory. Targets in the
directory use the following naming convention:

${SRC_PATH}/${TEST_NAME}.xml

For example, the opt version of the bitunion test built for ARM would
have this path:

build/ARM/unittests.opt/base/bituniontest.xml

Change-Id: I174dff16817734db05b08ce1d5bcf52e8697bbac
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
---
M src/SConscript
1 file changed, 6 insertions(+), 5 deletions(-)



diff --git a/src/SConscript b/src/SConscript
index 57a2d96..a98fbc4 100755
--- a/src/SConscript
+++ b/src/SConscript
@@ -1090,7 +1090,7 @@
 gtest_env.Append(LIBS=gtest_env['GTEST_LIBS'])
 gtest_env.Append(CPPFLAGS=gtest_env['GTEST_CPPFLAGS'])
 gtestlib_sources = Source.all.with_tag('gtest lib')
-gtests = []
+gtest_out_dir = Dir(new_env['BUILDDIR']).Dir('unittests.%s' % label)
 for test in GTest.all:
 test_sources = test.sources
 if not test.skip_lib:
@@ -1098,11 +1098,12 @@
 for f in test.filters:
 test_sources += Source.all.apply_filter(f)
 test_objs = [ s.static(gtest_env) for s in test_sources ]
-gtests.append(gtest_env.Program(
-test.dir.File('%s.%s' % (test.target, label)), test_objs))
+test_binary = gtest_env.Program(
+test.dir.File('%s.%s' % (test.target, label)), test_objs)

-gtest_target = Dir(new_env['BUILDDIR']).File('unittests.%s' % label)
-AlwaysBuild(gtest_env.Command(gtest_target, gtests, gtests))
+AlwaysBuild(gtest_env.Command(
+gtest_out_dir.File("%s/%s.xml" % (test.dir, test.target)),
+test_binary, "${SOURCES[0]} --gtest_output=xml:${TARGETS[0]}"))

 progname = exename
 if strip:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I174dff16817734db05b08ce1d5bcf52e8697bbac
Gerrit-Change-Number: 6624
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
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[gem5-dev] Linux 4.9 kernel for gem5 now available for Arm

[Andreas Sandberg]

Hi Everyone,

I'm happy to announce that we have just completed testing of the
gem5-specific patches for Linux 4.9. The new kernel is can be downloaded
from the gem5/v4.9 branch in the arm/linux [1] repository.

The kernel comes with default configurations for Armv7 and Armv8 and has
the same set of gem5-specific patches as the older 4.x kernels. These
patches add support for:

  * gem5's GICv2 extensions. This enables support for up to 255 CPUs if
the gem5 extensions are enabled in the GIC (set gem5_extensions to True
in your configuration script).
  * A virtual DRM connector. This makes it possible to use gem5's
display models without a proper HDMI encoder model.
  * The custom FBIOGET_DMABUF IOCTL. This change is useful to avoid a
CPU-side memcpy between the GPU's render buffer and the framebuffer for
Android setups that using NoMali.
  * gem5's DVFS controller.
  * General gem5 instrumentation.

Cheers,
Andreas

[1] https://gem5-review.googlesource.com/#/admin/projects/arm/linux
[2] http://gem5.org/ARM_Kernel

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[gem5-dev] Updated gem5 Linux kernel repo structure for Arm kernels

[Andreas Sandberg]

Hi Everyone,

I have just uploaded the Linux kernel repos we used to host on GitHub to
Google Source. While doing so, I slightly re-arranged the branches in
the work better for the new unified kernel trees with both aarch64 and
aarch32 support. I have updated the build instructions on the Wiki [0]
to reflect these changes. See below for an overview and the rationale
behind the change.

As of Linux 4.3 we started producing unified kernel repositories since
most of the changes we need for gem5 apply to both Armv7 and Armv8. In
the past, we used to have two repositories: linux-arm-gem5 [1], and
linux-arm64-gem5 [2].  The first of the two repositories contained both
the legacy Linaro-based Armv7 kernel and the new unified (Armv7 and
Armv8) kernel. The second repository only contained the legacy Armv8
kernel (also based on Linaro's source tree).

To avoid confusing branch names, the two repositories from GitHub have
been split into three repositories on the new Git server. The first
repository, arm/linux [3], contains the new unified kernels. All gem5
kernels live in branches named gem5/vX.Y, where the version number
corresponds to the upstream kernel version they are based on. We
currently base these branches on the original release by Linus (e.g.,
4.4.0) rather than the latest stable.

Legacy kernels have been migrated to arm/linux-arm-legacy [4] and
arm/linux-arm64-legacy [5]. These repositories contain the old release
branches and tags. They should however not be used for new experimental
setup since they rely on old platform configurations in gem5 with known
bugs.

We haven't configured mirroring to GitHub yet, so the kernel
repositories there currently don't match the repositories on Gerrit.

Cheers,
Andreas

[0] http://gem5.org/ARM_Kernel
[1] https://github.com/gem5/linux-arm-gem5
[2] https://github.com/gem5/linux-arm64-gem5
[3] https://gem5-review.googlesource.com/#/admin/projects/arm/linux
[4]
https://gem5-review.googlesource.com/#/admin/projects/arm/linux-arm-legacy
[5]
https://gem5-review.googlesource.com/#/admin/projects/arm/linux-arm64-legacy

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[gem5-dev] Change in public/gem5[master]: cpu: Don't override ISA if provided by user

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/6121 )


Change subject: cpu: Don't override ISA if provided by user
..

cpu: Don't override ISA if provided by user

The BaseCPU.createThreads() method currently overrides the BaseCPU.isa
parameter. This is sometimes undesirable. Change the behavior so that
the default value for the isa parameter is the empty list and teach
createThreads() to only override the ISA if none has been specified.

Change-Id: I2ac5535e55fc57057e294d3c6a93088b33bf7b84
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6121
Reviewed-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/cpu/BaseCPU.py
1 file changed, 22 insertions(+), 15 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 1bf2c1e..d174f27 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -60,37 +60,37 @@
 from AlphaTLB import AlphaDTB, AlphaITB
 from AlphaInterrupts import AlphaInterrupts
 from AlphaISA import AlphaISA
-isa_class = AlphaISA
+default_isa_class = AlphaISA
 elif buildEnv['TARGET_ISA'] == 'sparc':
 from SparcTLB import SparcTLB
 from SparcInterrupts import SparcInterrupts
 from SparcISA import SparcISA
-isa_class = SparcISA
+default_isa_class = SparcISA
 elif buildEnv['TARGET_ISA'] == 'x86':
 from X86TLB import X86TLB
 from X86LocalApic import X86LocalApic
 from X86ISA import X86ISA
-isa_class = X86ISA
+default_isa_class = X86ISA
 elif buildEnv['TARGET_ISA'] == 'mips':
 from MipsTLB import MipsTLB
 from MipsInterrupts import MipsInterrupts
 from MipsISA import MipsISA
-isa_class = MipsISA
+default_isa_class = MipsISA
 elif buildEnv['TARGET_ISA'] == 'arm':
 from ArmTLB import ArmTLB, ArmStage2IMMU, ArmStage2DMMU
 from ArmInterrupts import ArmInterrupts
 from ArmISA import ArmISA
-isa_class = ArmISA
+default_isa_class = ArmISA
 elif buildEnv['TARGET_ISA'] == 'power':
 from PowerTLB import PowerTLB
 from PowerInterrupts import PowerInterrupts
 from PowerISA import PowerISA
-isa_class = PowerISA
+default_isa_class = PowerISA
 elif buildEnv['TARGET_ISA'] == 'riscv':
 from RiscvTLB import RiscvTLB
 from RiscvInterrupts import RiscvInterrupts
 from RiscvISA import RiscvISA
-isa_class = RiscvISA
+default_isa_class = RiscvISA

 class BaseCPU(MemObject):
 type = 'BaseCPU'
@@ -167,24 +167,24 @@
 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
 interrupts = VectorParam.SparcInterrupts(
 [], "Interrupt Controller")
-isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
+isa = VectorParam.SparcISA([], "ISA instance")
 elif buildEnv['TARGET_ISA'] == 'alpha':
 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
 interrupts = VectorParam.AlphaInterrupts(
 [], "Interrupt Controller")
-isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
+isa = VectorParam.AlphaISA([], "ISA instance")
 elif buildEnv['TARGET_ISA'] == 'x86':
 dtb = Param.X86TLB(X86TLB(), "Data TLB")
 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
 interrupts = VectorParam.X86LocalApic([], "Interrupt Controller")
-isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
+isa = VectorParam.X86ISA([], "ISA instance")
 elif buildEnv['TARGET_ISA'] == 'mips':
 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
 interrupts = VectorParam.MipsInterrupts(
 [], "Interrupt Controller")
-isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
+isa = VectorParam.MipsISA([], "ISA instance")
 elif buildEnv['TARGET_ISA'] == 'arm':
 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
@@ -192,20 +192,20 @@
 dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
 interrupts = VectorParam.ArmInterrupts(
 [], "Interrupt Controller")
-isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
+isa = VectorParam.ArmISA([], "ISA instance")
 elif buildEnv['TARGET_ISA'] == 'power':
 UnifiedTLB = Param.Bool(True

[gem5-dev] Change in public/gem5[master]: cpu-minor: Add missing instruction stats

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5732 )


Change subject: cpu-minor: Add missing instruction stats
..

cpu-minor: Add missing instruction stats

Change-Id: I811b552989caf3601ac65a128dbee6b7bb405d7f
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
[ Updated to use IsVector instruction flag. ]
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5732
Reviewed-by: Gabe Black <gabebl...@google.com>
---
M src/cpu/minor/fetch2.cc
M src/cpu/minor/fetch2.hh
M src/cpu/minor/pipeline.cc
M src/cpu/minor/pipeline.hh
4 files changed, 63 insertions(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/cpu/minor/fetch2.cc b/src/cpu/minor/fetch2.cc
index 986f1f2..ba898d9 100644
--- a/src/cpu/minor/fetch2.cc
+++ b/src/cpu/minor/fetch2.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014 ARM Limited
+ * Copyright (c) 2013-2014,2016 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -415,6 +415,17 @@
 dyn_inst->pc = fetch_info.pc;
 DPRINTF(Fetch, "decoder inst %s\n", *dyn_inst);

+// Collect some basic inst class stats
+if (decoded_inst->isLoad())
+loadInstructions++;
+else if (decoded_inst->isStore())
+storeInstructions++;
+else if (decoded_inst->isVector())
+vecInstructions++;
+else if (decoded_inst->isFloating())
+fpInstructions++;
+else if (decoded_inst->isInteger())
+intInstructions++;

 DPRINTF(Fetch, "Instruction extracted from line %s"
 " lineWidth: %d output_index: %d inputIndex: %d"
@@ -594,6 +605,37 @@
 }

 void
+Fetch2::regStats()
+{
+using namespace Stats;
+
+intInstructions
+.name(name() + ".int_instructions")
+.desc("Number of integer instructions successfully decoded")
+.flags(total);
+
+fpInstructions
+.name(name() + ".fp_instructions")
+.desc("Number of floating point instructions successfully decoded")
+.flags(total);
+
+vecInstructions
+.name(name() + ".vec_instructions")
+.desc("Number of SIMD instructions successfully decoded")
+.flags(total);
+
+loadInstructions
+.name(name() + ".load_instructions")
+.desc("Number of memory load instructions successfully decoded")
+.flags(total);
+
+storeInstructions
+.name(name() + ".store_instructions")
+.desc("Number of memory store instructions successfully decoded")
+.flags(total);
+}
+
+void
 Fetch2::minorTrace() const
 {
 std::ostringstream data;
diff --git a/src/cpu/minor/fetch2.hh b/src/cpu/minor/fetch2.hh
index 33c683b..c66fbd8 100644
--- a/src/cpu/minor/fetch2.hh
+++ b/src/cpu/minor/fetch2.hh
@@ -165,6 +165,13 @@
 std::vector fetchInfo;
 ThreadID threadPriority;

+/** Stats */
+Stats::Scalar intInstructions;
+Stats::Scalar fpInstructions;
+Stats::Scalar vecInstructions;
+Stats::Scalar loadInstructions;
+Stats::Scalar storeInstructions;
+
   protected:
 /** Get a piece of data to work on from the inputBuffer, or 0 if there
  *  is no data. */
@@ -206,6 +213,8 @@

 void minorTrace() const;

+void regStats();
+
 /** Is this stage drained?  For Fetch2, draining is initiated by
  *  Execute halting Fetch1 causing Fetch2 to naturally drain.
  *  Branch predictions are ignored by Fetch1 during halt */
diff --git a/src/cpu/minor/pipeline.cc b/src/cpu/minor/pipeline.cc
index 08dc3db..b5659ac 100644
--- a/src/cpu/minor/pipeline.cc
+++ b/src/cpu/minor/pipeline.cc
@@ -106,6 +106,14 @@
 }

 void
+Pipeline::regStats()
+{
+Ticked::regStats();
+
+fetch2.regStats();
+}
+
+void
 Pipeline::minorTrace() const
 {
 fetch1.minorTrace();
diff --git a/src/cpu/minor/pipeline.hh b/src/cpu/minor/pipeline.hh
index ca96d50..351af6f 100644
--- a/src/cpu/minor/pipeline.hh
+++ b/src/cpu/minor/pipeline.hh
@@ -128,6 +128,9 @@

 void minorTrace() const;

+/** Stats registering */
+void regStats();
+
 /** Functions below here are BaseCPU operations passed on to pipeline
  *  stages */


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerr

[gem5-dev] Change in public/gem5[master]: cpu: Don't override ISA if provided by user

[Andreas Sandberg (Gerrit)]

Hello Gabe Black, Jason Lowe-Power, Alec Roelke, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/6121

to look at the new patch set (#2).

Change subject: cpu: Don't override ISA if provided by user
..

cpu: Don't override ISA if provided by user

The BaseCPU.createThreads() method currently overrides the BaseCPU.isa
parameter. This is sometimes undesirable. Change the behavior so that
the default value for the isa parameter is the empty list and teach
createThreads() to only override the ISA if none has been specified.

Change-Id: I2ac5535e55fc57057e294d3c6a93088b33bf7b84
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu@arm.com>
---
M src/cpu/BaseCPU.py
1 file changed, 22 insertions(+), 15 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I2ac5535e55fc57057e294d3c6a93088b33bf7b84
Gerrit-Change-Number: 6121
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Alec Roelke <ar...@virginia.edu>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
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[gem5-dev] Change in public/gem5[master]: cpu-o3: Add missing vector stat initializers

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/6101 )


Change subject: cpu-o3: Add missing vector stat initializers
..

cpu-o3: Add missing vector stat initializers

All of the O3 vector stats added by 'arch: ISA parser additions of
vector registers' are currently missing their stat initializers. Add
the missing stat initialization to InstructionQueue::regStats.

Change-Id: Idc4b8e2824120a2542d8a604340a1b41bde6aa28
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6101
Reviewed-by: Gabe Black <gabebl...@google.com>
Reviewed-by: Jason Lowe-Power <ja...@lowepower.com>
Maintainer: Jason Lowe-Power <ja...@lowepower.com>
---
M src/cpu/o3/inst_queue_impl.hh
1 file changed, 20 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved



diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 3da72fd..f70f662 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -369,6 +369,21 @@
 .desc("Number of floating instruction queue wakeup accesses")
 .flags(total);

+vecInstQueueReads
+.name(name() + ".vec_inst_queue_reads")
+.desc("Number of vector instruction queue reads")
+.flags(total);
+
+vecInstQueueWrites
+.name(name() + ".vec_inst_queue_writes")
+.desc("Number of vector instruction queue writes")
+.flags(total);
+
+vecInstQueueWakeupAccesses
+.name(name() + ".vec_inst_queue_wakeup_accesses")
+.desc("Number of vector instruction queue wakeup accesses")
+.flags(total);
+
 intAluAccesses
 .name(name() + ".int_alu_accesses")
 .desc("Number of integer alu accesses")
@@ -379,6 +394,11 @@
 .desc("Number of floating point alu accesses")
 .flags(total);

+vecAluAccesses
+.name(name() + ".vec_alu_accesses")
+.desc("Number of vector alu accesses")
+.flags(total);
+
 }

 template 

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Idc4b8e2824120a2542d8a604340a1b41bde6aa28
Gerrit-Change-Number: 6101
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
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