[gem5-dev] [S] Change in gem5/gem5[develop]: base: Use the MSB rather than the LSB in AddrRange:removeIntlvBits
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/70057?usp=email )
Change subject: base: Use the MSB rather than the LSB in
AddrRange:removeIntlvBits
..
base: Use the MSB rather than the LSB in AddrRange:removeIntlvBits
In many cases, the LSB (as constrained by the masks) of an interleaved
address range falls within the virtual page offset. For typical
workloads, the page offset and the least significant bits have more
entropy than the most significant bits. Consequently, removing a
bit closer to the MSB preserves bits tends to provide a more uniform
utilization of resources.
Change-Id: I361d8130d080a1be23f85de12afef0432efcd11e
Signed-off-by: Nikos Nikoleris
---
M src/base/addr_range.hh
M src/base/addr_range.test.cc
2 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/src/base/addr_range.hh b/src/base/addr_range.hh
index 11fb1cd..40545ba 100644
--- a/src/base/addr_range.hh
+++ b/src/base/addr_range.hh
@@ -523,17 +523,17 @@
}
// Get the LSB set from each mask
-int masks_lsb[masks.size()];
+int masks_msb[masks.size()];
for (unsigned int i = 0; i < masks.size(); i++) {
-masks_lsb[i] = ctz64(masks[i]);
+masks_msb[i] = sizeof(Addr) * 8 - clz64(masks[i]) - 1;
}
// we need to sort the list of bits we will discard as we
// discard them one by one starting.
-std::sort(masks_lsb, masks_lsb + masks.size());
+std::sort(masks_msb, masks_msb + masks.size());
for (unsigned int i = 0; i < masks.size(); i++) {
-const int intlv_bit = masks_lsb[i];
+const int intlv_bit = masks_msb[i];
if (intlv_bit > 0) {
// on every iteration we remove one bit from the input
// address, and therefore the lowest invtl_bit has
@@ -562,15 +562,15 @@
}
// Get the LSB set from each mask
-int masks_lsb[masks.size()];
+int masks_msb[masks.size()];
for (unsigned int i = 0; i < masks.size(); i++) {
-masks_lsb[i] = ctz64(masks[i]);
+masks_msb[i] = sizeof(Addr) * CHAR_BIT - clz64(masks[i]) - 1;
}
// Add bits one-by-one from the LSB side.
-std::sort(masks_lsb, masks_lsb + masks.size());
+std::sort(masks_msb, masks_msb + masks.size());
for (unsigned int i = 0; i < masks.size(); i++) {
-const int intlv_bit = masks_lsb[i];
+const int intlv_bit = masks_msb[i];
if (intlv_bit > 0) {
// on every iteration we add one bit from the input
// address, but the lowest invtl_bit in the iteration is
@@ -583,7 +583,7 @@
}
for (unsigned int i = 0; i < masks.size(); i++) {
-const int lsb = ctz64(masks[i]);
+const int lsb = sizeof(Addr) * CHAR_BIT - clz64(masks[i]) - 1;
const Addr intlv_bit = bits(intlvMatch, i);
// Calculate the mask ignoring the LSB
const Addr masked = a & masks[i] & ~(1 << lsb);
diff --git a/src/base/addr_range.test.cc b/src/base/addr_range.test.cc
index 1e86154..bf7d2f7 100644
--- a/src/base/addr_range.test.cc
+++ b/src/base/addr_range.test.cc
@@ -743,16 +743,17 @@
uint8_t intlv_match = 1;
AddrRange r(start, end, masks, intlv_match);
-Addr input = (1 << 9) | (1 << 8) | 1;
+Addr input = (1 << 10) | (1 << 9) | (1 << 3);
/*
* (1 << 8) and 1 are interleaving bits to be removed.
*/
Addr output = r.removeIntlvBits(input);
/*
- * The bit, formally at position 9, is now at 7.
+ * The bit, previously at position 10, is now at 9 and the bit
+ * previously at position 9, is now at 8 and bit 3 has been discarded.
*/
-EXPECT_EQ((1 << 7), output);
+EXPECT_EQ((1 << 9) | (1 << 8), output);
/*
* Re-adding the interleaving.
@@ -826,7 +827,7 @@
uint8_t intlv_match = 0;
AddrRange r(start, end, masks, intlv_match);
-Addr value = ((1 << 10) | (1 << 9) | (1 << 8) | (1 << 2) | (1 << 1) |
1);
+Addr value = ((1 << 10) | (1 << 9) | (1 << 8) | (1 << 4) | (1 << 1) |
1);
Addr value_interleaving_bits_removed =
((1 << 9) | (1 << 8) | (1 << 7) | (1 << 1) |
1);
--
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[gem5-dev] [S] Change in gem5/gem5[develop]: python: Ensure that m5.internal.params is available
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67797?usp=email )
Change subject: python: Ensure that m5.internal.params is available
..
python: Ensure that m5.internal.params is available
Add an import to m5.internal.params which became necessary after:
95f9017c2e configs,python: Clean some cruft out of m5.objects.
This import is necessary but also causes problems when scons calls
build_tools/sim_object_param_struct_hh.py to generate
params/SimObject.hh. m5.internal.params itself imports _m5 and _m5 is
unavalailable resulting in an ImportError. This is bening and we can
safely ignore it.
Change-Id: I3809e81284e730fb9c9e0e7e91bd61b801d73f90
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67797
Maintainer: Giacomo Travaglini
Tested-by: kokoro
Reviewed-by: Giacomo Travaglini
---
M src/python/m5/SimObject.py
M src/python/m5/internal/params.py
2 files changed, 40 insertions(+), 4 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index b5dfca9..6caa532 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -445,6 +445,9 @@
return cls.__name__
def getCCClass(cls):
+# Ensure that m5.internal.params is available.
+import m5.internal.params
+
return getattr(m5.internal.params, cls.pybind_class)
# See ParamValue.cxx_predecls for description.
diff --git a/src/python/m5/internal/params.py
b/src/python/m5/internal/params.py
index 8762a69..8225d0b 100644
--- a/src/python/m5/internal/params.py
+++ b/src/python/m5/internal/params.py
@@ -37,8 +37,17 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import inspect
-import _m5
-for name, module in inspect.getmembers(_m5):
-if name.startswith("param_") or name.startswith("enum_"):
-exec("from _m5.%s import *" % name)
+try:
+# Avoid ImportErrors at build time when _m5 is not available
+import _m5
+
+in_gem5 = True
+except ImportError:
+# The import failed, we're being called from the build system
+in_gem5 = False
+
+if in_gem5:
+for name, module in inspect.getmembers(_m5):
+if name.startswith("param_") or name.startswith("enum_"):
+exec("from _m5.%s import *" % name)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3809e81284e730fb9c9e0e7e91bd61b801d73f90
Gerrit-Change-Number: 67797
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: python: Ensure that m5.internal.params is available
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67797?usp=email )
Change subject: python: Ensure that m5.internal.params is available
..
python: Ensure that m5.internal.params is available
Add an import to m5.internal.params which became necessary after:
95f9017c2e configs,python: Clean some cruft out of m5.objects.
This import is necessary but also causes problems when scons calls
build_tools/sim_object_param_struct_hh.py to generate
params/SimObject.hh. m5.internal.params itself imports _m5 and _m5 is
unavalailable resulting in an ImportError. This is bening and we can
safely ignore it.
Change-Id: I3809e81284e730fb9c9e0e7e91bd61b801d73f90
Signed-off-by: Nikos Nikoleris
---
M src/python/m5/SimObject.py
M src/python/m5/internal/params.py
2 files changed, 35 insertions(+), 4 deletions(-)
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index b5dfca9..e3ff0ab 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -445,6 +445,8 @@
return cls.__name__
def getCCClass(cls):
+# Ensure that m5.internal.params is available.
+import m5.internal.params
return getattr(m5.internal.params, cls.pybind_class)
# See ParamValue.cxx_predecls for description.
diff --git a/src/python/m5/internal/params.py
b/src/python/m5/internal/params.py
index 8762a69..8225d0b 100644
--- a/src/python/m5/internal/params.py
+++ b/src/python/m5/internal/params.py
@@ -37,8 +37,17 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import inspect
-import _m5
-for name, module in inspect.getmembers(_m5):
-if name.startswith("param_") or name.startswith("enum_"):
-exec("from _m5.%s import *" % name)
+try:
+# Avoid ImportErrors at build time when _m5 is not available
+import _m5
+
+in_gem5 = True
+except ImportError:
+# The import failed, we're being called from the build system
+in_gem5 = False
+
+if in_gem5:
+for name, module in inspect.getmembers(_m5):
+if name.startswith("param_") or name.startswith("enum_"):
+exec("from _m5.%s import *" % name)
--
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Gerrit-Change-Number: 67797
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Gerrit-Owner: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: base: Make the random number generator public
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47859 )
Change subject: base: Make the random number generator public
..
base: Make the random number generator public
There are cases where we need a random number generator engine. The
Random class has such an engine but its interface currently only
allows for generating random numbers. To make sure we can reuse the
same random number generator in as many places as possible this patch
makes the engine in the Random class public.
Change-Id: I80153dd39f5b0d12537e4c0cf54773e7725b2a94
Signed-off-by: Nikos Nikoleris
---
M src/base/random.hh
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/base/random.hh b/src/base/random.hh
index 9a3d696..55d7245 100644
--- a/src/base/random.hh
+++ b/src/base/random.hh
@@ -61,14 +61,15 @@
class Random : public Serializable
{
- private:
-
-std::mt19937_64 gen;
-
public:
/**
* @ingroup api_base_utils
+ */
+std::mt19937_64 gen;
+
+/**
+ * @ingroup api_base_utils
* @{
*/
Random();
--
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[gem5-dev] Change in gem5/gem5[develop]: cpu-minor: Substitute calls to functions removed in c++-17
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47799 )
Change subject: cpu-minor: Substitute calls to functions removed in c++-17
..
cpu-minor: Substitute calls to functions removed in c++-17
Change-Id: Ib15234b37e577afd7ff186f1ba7cc5896aea1430
Signed-off-by: Nikos Nikoleris
---
M src/cpu/minor/cpu.hh
M src/cpu/minor/execute.cc
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh
index 57b73b7..929048f 100644
--- a/src/cpu/minor/cpu.hh
+++ b/src/cpu/minor/cpu.hh
@@ -44,6 +44,8 @@
#ifndef __CPU_MINOR_CPU_HH__
#define __CPU_MINOR_CPU_HH__
+#include
+
#include "base/compiler.hh"
#include "cpu/minor/activity.hh"
#include "cpu/minor/stats.hh"
@@ -184,7 +186,11 @@
for (ThreadID i = 0; i < numThreads; i++) {
prio_list.push_back(i);
}
-std::random_shuffle(prio_list.begin(), prio_list.end());
+
+std::random_device r;
+std::shuffle(prio_list.begin(), prio_list.end(),
+ std::default_random_engine(r()));
+
return prio_list;
}
diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index 793ed7e..81850cb 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -37,6 +37,8 @@
#include "cpu/minor/execute.hh"
+#include
+
#include "arch/locked_mem.hh"
#include "cpu/minor/cpu.hh"
#include "cpu/minor/exec_context.hh"
@@ -1685,7 +1687,7 @@
stalled.str(), executeInfo[0].drainState, isInbetweenInsts(0));
std::for_each(funcUnits.begin(), funcUnits.end(),
-std::mem_fun(::minorTrace));
+std::mem_fn(::minorTrace));
executeInfo[0].inFlightInsts->minorTrace();
executeInfo[0].inFUMemInsts->minorTrace();
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Fix indexing policies in prefetchers
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37597 )
Change subject: mem-cache: Fix indexing policies in prefetchers
..
mem-cache: Fix indexing policies in prefetchers
Many prefetches use a set-associative array for their internal
state. In most cases, either the address or the PC of a request is
used to calculate the index in these arrays. The index depends on the
size of the *tracked* block and the associativity. This patch moves
the index calculation inside the indexing to policy to fix some bugs
and allow more flexibility.
Change-Id: Ia2273cb34705fecce10480881e102ad1764050e0
Signed-off-by: Nikos Nikoleris
---
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/prefetch/access_map_pattern_matching.cc
M src/mem/cache/prefetch/irregular_stream_buffer.cc
M src/mem/cache/prefetch/spatio_temporal_memory_streaming.cc
4 files changed, 42 insertions(+), 21 deletions(-)
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index 758803f..f8f39bc 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012, 2014, 2019 ARM Limited
+# Copyright (c) 2012, 2014, 2019-2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -299,8 +299,9 @@
access_map_table_assoc = Param.Unsigned(8,
"Associativity of the access map table")
access_map_table_indexing_policy = Param.BaseIndexingPolicy(
-SetAssociative(entry_size = 1, assoc =
Parent.access_map_table_assoc,
-size = Parent.access_map_table_entries),
+SetAssociative(entry_size=Self.hot_zone_size,
+ assoc=Parent.access_map_table_assoc,
+ size=Parent.access_map_table_entries),
"Indexing policy of the access map table")
access_map_table_replacement_policy =
Param.BaseReplacementPolicy(LRURP(),
"Replacement policy of the access map table")
@@ -340,6 +341,10 @@
"Number of entries in the table")
table_assoc = Param.Unsigned(128,
"Associativity of the table")
+
+# FIXME: Highly unlikely that 1 is the right value for entry_size.
+# I would expect the instruction size would be a more sensible
+# value to avoid underutilizing the table.
table_indexing_policy = Param.BaseIndexingPolicy(
SetAssociative(entry_size = 1, assoc = Parent.table_assoc,
size = Parent.table_entries),
@@ -369,6 +374,10 @@
"Associativity of the training unit")
training_unit_entries = Param.MemorySize("128",
"Number of entries of the training unit")
+
+# FIXME: Highly unlikely that 1 is the right value for entry_size.
+# I would expect the instruction size would be a more sensible
+# value to avoid underutilizing the table.
training_unit_indexing_policy = Param.BaseIndexingPolicy(
SetAssociative(entry_size = 1, assoc = Parent.training_unit_assoc,
size = Parent.training_unit_entries),
@@ -383,17 +392,17 @@
address_map_cache_entries = Param.MemorySize("128",
"Number of entries of the PS/SP AMCs")
ps_address_map_cache_indexing_policy = Param.BaseIndexingPolicy(
-SetAssociative(entry_size = 1,
-assoc = Parent.address_map_cache_assoc,
-size = Parent.address_map_cache_entries),
+SetAssociative(entry_size=Self.prefetch_candidates_per_entry,
+ assoc=Parent.address_map_cache_assoc,
+ size=Parent.address_map_cache_entries),
"Indexing policy of the Physical-to-Structural Address Map Cache")
ps_address_map_cache_replacement_policy = Param.BaseReplacementPolicy(
LRURP(),
"Replacement policy of the Physical-to-Structural Address Map
Cache")
sp_address_map_cache_indexing_policy = Param.BaseIndexingPolicy(
-SetAssociative(entry_size = 1,
-assoc = Parent.address_map_cache_assoc,
-size = Parent.address_map_cache_entries),
+SetAssociative(entry_size=Self.prefetch_candidates_per_entry,
+ assoc=Parent.address_map_cache_assoc,
+ size=Parent.address_map_cache_entries),
"Indexing policy of the Structural-to-Physical Address Mao Cache")
sp_address_map_cache_replacement_policy = Param.BaseReplacementPolicy(
LRURP(),
@@ -463,9 +472,9 @@
active_generation_table_assoc = Param.Unsigned(64,
"Associativity of the active generation table")
active_generation_table_indexing_policy = Param.BaseIndexingPolicy(
-SetAssociative(entry_size = 1,
-assoc = Parent.active_generation_table_assoc,
-size = Parent.active_generation_table_entries),
+SetAssociative(entry_size=Self.spatial_region_size,
+
[gem5-dev] Change in gem5/gem5[develop]: base: Add operator~() in ChannelAddr class
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37595 )
Change subject: base: Add operator~() in ChannelAddr class
..
base: Add operator~() in ChannelAddr class
Change-Id: I3e9c0130d1bd110ad9d42c851a16a9de322e0fb4
Signed-off-by: Nikos Nikoleris
---
M src/base/channel_addr.hh
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/base/channel_addr.hh b/src/base/channel_addr.hh
index 2cfe380..0c2b65b 100644
--- a/src/base/channel_addr.hh
+++ b/src/base/channel_addr.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -129,6 +129,10 @@
return ChannelAddr(a - b.a);
}
+constexpr ChannelAddr operator~() const {
+return ChannelAddr(~a);
+}
+
constexpr bool operator>(const ChannelAddr ) const { return a > b.a;
}
constexpr bool operator>=(const ChannelAddr ) const { return a >=
b.a; }
constexpr bool operator<(const ChannelAddr ) const { return a < b.a;
}
--
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[gem5-dev] Change in gem5/gem5[develop]: util: Relax commit message checker to allow fixups
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37598 )
Change subject: util: Relax commit message checker to allow fixups
..
util: Relax commit message checker to allow fixups
Change-Id: I094de0a9cb65af0ba0a8700d77cd51c6537d7beb
Signed-off-by: Nikos Nikoleris
---
M util/git-commit-msg.py
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/util/git-commit-msg.py b/util/git-commit-msg.py
index 9cba896..836bc4d 100755
--- a/util/git-commit-msg.py
+++ b/util/git-commit-msg.py
@@ -113,10 +113,12 @@
commit_message_lines = commit_message.splitlines()
commit_header = commit_message_lines[0]
commit_header_match = \
-re.search("^(\S[\w\-][,\s*[\w\-]+]*:.+\S$)", commit_header)
+re.search("^(fixup! )?(\S[\w\-][,\s*[\w\-]+]*:.+\S$)", commit_header)
if ((commit_header_match is None)):
_printErrorQuit("Invalid commit header")
-_validateTags(commit_header)
+if commit_header_match.group(1) == "fixup! ":
+sys.exit(0)
+_validateTags(commit_header_match.group(2))
# Make sure commit title does not exceed threshold. This line is limited to
# a smaller number because version control systems may add a prefix,
causing
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I094de0a9cb65af0ba0a8700d77cd51c6537d7beb
Gerrit-Change-Number: 37598
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: ext: Disable range-loop-analysis warnings for pybind11
Nikos Nikoleris has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/35296 ) Change subject: ext: Disable range-loop-analysis warnings for pybind11 .. ext: Disable range-loop-analysis warnings for pybind11 Change-Id: I9d9e118c1c70c2f6b11260fff31ecd763e491115 Signed-off-by: Nikos Nikoleris --- M ext/pybind11/include/pybind11/pybind11.h 1 file changed, 1 insertion(+), 0 deletions(-) diff --git a/ext/pybind11/include/pybind11/pybind11.h b/ext/pybind11/include/pybind11/pybind11.h index a9ee31a..04ef30f 100644 --- a/ext/pybind11/include/pybind11/pybind11.h +++ b/ext/pybind11/include/pybind11/pybind11.h @@ -12,6 +12,7 @@ #ifdef __clang__ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wunused-value" +#pragma clang diagnostic warning "-Wrange-loop-analysis" #endif #if defined(__INTEL_COMPILER) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35296 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I9d9e118c1c70c2f6b11260fff31ecd763e491115 Gerrit-Change-Number: 35296 Gerrit-PatchSet: 1 Gerrit-Owner: Nikos Nikoleris Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[release-staging-v20.1.0.0]: mem: Fix some reference use in range loops
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34776 )
Change subject: mem: Fix some reference use in range loops
..
mem: Fix some reference use in range loops
This change fixes two cases of range loops, one where we can't use
lvalue reference, and one more where we have to use an lvalue
reference as we can't create a copy. In both cases clang would warn.
Change-Id: I760aa094af66be32a150bad37acc21d6fd512a65
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34776
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/common/BoolVec.cc
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
M src/mem/ruby/system/Sequencer.cc
3 files changed, 5 insertions(+), 5 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/common/BoolVec.cc b/src/mem/ruby/common/BoolVec.cc
index 603f714..1c29532 100644
--- a/src/mem/ruby/common/BoolVec.cc
+++ b/src/mem/ruby/common/BoolVec.cc
@@ -41,8 +41,8 @@
#include
std::ostream& operator<<(std::ostream& os, const BoolVec& myvector) {
-for (const auto& it: myvector) {
-os << " " << it;
+for (const bool e: myvector) {
+os << " " << e;
}
return os;
}
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
index 8ff8884..155d134 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -256,8 +256,8 @@
countBoolVec(BoolVec bVec)
{
int count = 0;
-for (const auto : bVec) {
-if (it) {
+for (const bool e: bVec) {
+if (e) {
count++;
}
}
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index 75c58d6..dbc85c4 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -167,7 +167,7 @@
int total_outstanding = 0;
for (const auto _entry : m_RequestTable) {
-for (const auto seq_req : table_entry.second) {
+for (const auto _req : table_entry.second) {
if (current_time - seq_req.issue_time < m_deadlock_threshold)
continue;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.1.0.0
Gerrit-Change-Id: I760aa094af66be32a150bad37acc21d6fd512a65
Gerrit-Change-Number: 34776
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-CC: Bobby R. Bruce
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem: Fix some reference use in range loops
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34776 )
Change subject: mem: Fix some reference use in range loops
..
mem: Fix some reference use in range loops
This change fixes two cases of range loops, one where we can't use
lvalue reference, and one more where we have to use an lvalue
reference as we can't create a copy. In both cases clang would warn.
Change-Id: I760aa094af66be32a150bad37acc21d6fd512a65
Signed-off-by: Nikos Nikoleris
---
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
M src/mem/ruby/system/Sequencer.cc
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
index 8ff8884..317bded 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -256,8 +256,8 @@
countBoolVec(BoolVec bVec)
{
int count = 0;
-for (const auto : bVec) {
-if (it) {
+for (const auto &: bVec) {
+if (e) {
count++;
}
}
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index 75c58d6..dbc85c4 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -167,7 +167,7 @@
int total_outstanding = 0;
for (const auto _entry : m_RequestTable) {
-for (const auto seq_req : table_entry.second) {
+for (const auto _req : table_entry.second) {
if (current_time - seq_req.issue_time < m_deadlock_threshold)
continue;
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I760aa094af66be32a150bad37acc21d6fd512a65
Gerrit-Change-Number: 34776
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: scons: Avoid the unsupported option -Wno-c99-designator in MacOS
Nikos Nikoleris has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/33775 ) Change subject: scons: Avoid the unsupported option -Wno-c99-designator in MacOS .. scons: Avoid the unsupported option -Wno-c99-designator in MacOS Change-Id: I4d95c75915b17531bdd6d9161eb266bb91cd7bef Signed-off-by: Nikos Nikoleris Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33775 Reviewed-by: Gabe Black Reviewed-by: Jason Lowe-Power Maintainer: Gabe Black Tested-by: kokoro --- M SConstruct 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, approved Gabe Black: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/SConstruct b/SConstruct index d229ab8..4e47bda 100755 --- a/SConstruct +++ b/SConstruct @@ -440,7 +440,8 @@ # interchangeably. '-Wno-mismatched-tags', ]) -if compareVersions(clang_version, "10.0") >= 0: +if sys.platform != "darwin" and \ + compareVersions(clang_version, "10.0") >= 0: main.Append(CCFLAGS=['-Wno-c99-designator']) if compareVersions(clang_version, "8.0") >= 0: -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/33775 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I4d95c75915b17531bdd6d9161eb266bb91cd7bef Gerrit-Change-Number: 33775 Gerrit-PatchSet: 2 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch: Remove unused variable pcbb from ThreadInfo
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/33776 )
Change subject: arch: Remove unused variable pcbb from ThreadInfo
..
arch: Remove unused variable pcbb from ThreadInfo
Change-Id: Ib9e46934f1613c98758662cba26a46fcc2a76146
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33776
Reviewed-by: Gabe Black
Reviewed-by: Jason Lowe-Power
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/generic/linux/threadinfo.hh
1 file changed, 2 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/generic/linux/threadinfo.hh
b/src/arch/generic/linux/threadinfo.hh
index 0127105..e5ba7e2 100644
--- a/src/arch/generic/linux/threadinfo.hh
+++ b/src/arch/generic/linux/threadinfo.hh
@@ -39,7 +39,6 @@
private:
ThreadContext *tc;
System *sys;
-Addr pcbb;
ByteOrder byteOrder;
@@ -62,8 +61,8 @@
}
public:
-ThreadInfo(ThreadContext *_tc, Addr _pcbb = 0)
-: tc(_tc), sys(tc->getSystemPtr()), pcbb(_pcbb),
+ThreadInfo(ThreadContext *_tc)
+: tc(_tc), sys(tc->getSystemPtr()),
byteOrder(tc->getSystemPtr()->getGuestByteOrder())
{
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib9e46934f1613c98758662cba26a46fcc2a76146
Gerrit-Change-Number: 33776
Gerrit-PatchSet: 2
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Add missing overrides in the *Fault classes
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33777 )
Change subject: sim: Add missing overrides in the *Fault classes
..
sim: Add missing overrides in the *Fault classes
Change-Id: I7a74df78f0f85ccf7fd896f98b301c1f998c1497
Signed-off-by: Nikos Nikoleris
---
M src/sim/faults.hh
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/src/sim/faults.hh b/src/sim/faults.hh
index e9a57c6..4b5c1a5 100644
--- a/src/sim/faults.hh
+++ b/src/sim/faults.hh
@@ -55,7 +55,11 @@
public:
UnimpFault(std::string _str) : panicStr(_str) {}
-FaultName name() const { return "Unimplemented simulator feature"; }
+FaultName
+name() const override
+{
+return "Unimplemented simulator feature";
+}
void invoke(ThreadContext *tc, const StaticInstPtr =
StaticInst::nullStaticInstPtr) override;
};
@@ -63,7 +67,7 @@
class ReExec : public FaultBase
{
public:
-virtual FaultName name() const { return "Re-execution fault"; }
+virtual FaultName name() const override { return "Re-execution fault";
}
void invoke(ThreadContext *tc, const StaticInstPtr =
StaticInst::nullStaticInstPtr) override;
};
@@ -78,7 +82,7 @@
class SyscallRetryFault : public FaultBase
{
public:
-virtual FaultName name() const { return "System call retry fault"; }
+FaultName name() const override { return "System call retry fault"; }
SyscallRetryFault() {}
void invoke(ThreadContext *tc, const StaticInstPtr =
StaticInst::nullStaticInstPtr) override;
@@ -89,7 +93,7 @@
private:
Addr vaddr;
public:
-FaultName name() const { return "Generic page table fault"; }
+FaultName name() const override { return "Generic page table fault"; }
GenericPageTableFault(Addr va) : vaddr(va) {}
void invoke(ThreadContext *tc, const StaticInstPtr =
StaticInst::nullStaticInstPtr) override;
@@ -101,7 +105,7 @@
private:
Addr vaddr;
public:
-FaultName name() const { return "Generic alignment fault"; }
+FaultName name() const override { return "Generic alignment fault"; }
GenericAlignmentFault(Addr va) : vaddr(va) {}
void invoke(ThreadContext *tc, const StaticInstPtr =
StaticInst::nullStaticInstPtr) override;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7a74df78f0f85ccf7fd896f98b301c1f998c1497
Gerrit-Change-Number: 33777
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: scons: Avoid the unsupported option -Wno-c99-designator in MacOS
Nikos Nikoleris has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/33775 ) Change subject: scons: Avoid the unsupported option -Wno-c99-designator in MacOS .. scons: Avoid the unsupported option -Wno-c99-designator in MacOS Change-Id: I4d95c75915b17531bdd6d9161eb266bb91cd7bef Signed-off-by: Nikos Nikoleris --- M SConstruct 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/SConstruct b/SConstruct index bbfa37a..efd2a9d 100755 --- a/SConstruct +++ b/SConstruct @@ -473,7 +473,8 @@ # interchangeably. '-Wno-mismatched-tags', ]) -if compareVersions(clang_version, "10.0") >= 0: +if sys.platform != "darwin" and \ + compareVersions(clang_version, "10.0") >= 0: main.Append(CCFLAGS=['-Wno-c99-designator']) if compareVersions(clang_version, "8.0") >= 0: -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/33775 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I4d95c75915b17531bdd6d9161eb266bb91cd7bef Gerrit-Change-Number: 33775 Gerrit-PatchSet: 1 Gerrit-Owner: Nikos Nikoleris Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch: Remove unused variable pcbb from ThreadInfo
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33776 )
Change subject: arch: Remove unused variable pcbb from ThreadInfo
..
arch: Remove unused variable pcbb from ThreadInfo
Change-Id: Ib9e46934f1613c98758662cba26a46fcc2a76146
Signed-off-by: Nikos Nikoleris
---
M src/arch/generic/linux/threadinfo.hh
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/arch/generic/linux/threadinfo.hh
b/src/arch/generic/linux/threadinfo.hh
index 0127105..e5ba7e2 100644
--- a/src/arch/generic/linux/threadinfo.hh
+++ b/src/arch/generic/linux/threadinfo.hh
@@ -39,7 +39,6 @@
private:
ThreadContext *tc;
System *sys;
-Addr pcbb;
ByteOrder byteOrder;
@@ -62,8 +61,8 @@
}
public:
-ThreadInfo(ThreadContext *_tc, Addr _pcbb = 0)
-: tc(_tc), sys(tc->getSystemPtr()), pcbb(_pcbb),
+ThreadInfo(ThreadContext *_tc)
+: tc(_tc), sys(tc->getSystemPtr()),
byteOrder(tc->getSystemPtr()->getGuestByteOrder())
{
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ib9e46934f1613c98758662cba26a46fcc2a76146
Gerrit-Change-Number: 33776
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem: Use beats_per_clock as the DDR data rate for DRAMPower
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30056 )
Change subject: mem: Use beats_per_clock as the DDR data rate for DRAMPower
..
mem: Use beats_per_clock as the DDR data rate for DRAMPower
The data rate is used by the drampower lib to estimate the power
consumption of the DRAM Core. Previously, we used the formula:
burst_cycles = divCeil(p->tBURST_MAX, p->tCK);
data_rate = p->burst_length / burst_cycles;
to derive the data_rate. However, under certain configurations this
formula computes the wrong result due to rounding errors. This patch
simplifies the way we derive the data_rate by passing the value of the
DRAM parameter beats_per_clock.
Change-Id: Ic8cd35bb4641d9c0a704675d2672a6fe4f4ec13e
Signed-off-by: Nikos Nikoleris
Reviewed-by: Wendy Elsasser
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30056
Tested-by: kokoro
Reviewed-by: Daniel Carvalho
---
M src/mem/drampower.cc
M src/mem/drampower.hh
2 files changed, 1 insertion(+), 17 deletions(-)
Approvals:
Wendy Elsasser: Looks good to me, approved
Daniel Carvalho: Looks good to me, but someone else must approve
Nikos Nikoleris: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/drampower.cc b/src/mem/drampower.cc
index f506928..13551a0 100644
--- a/src/mem/drampower.cc
+++ b/src/mem/drampower.cc
@@ -53,7 +53,7 @@
archSpec.nbrOfBanks = p->banks_per_rank;
// One DRAMPower instance per rank, hence set this to 1
archSpec.nbrOfRanks = 1;
-archSpec.dataRate = getDataRate(p);
+archSpec.dataRate = p->beats_per_clock;
// For now we can ignore the number of columns and rows as they
// are not used in the power calculation.
archSpec.nbrOfColumns = 0;
@@ -146,14 +146,3 @@
{
return p->VDD2 == 0 ? false : true;
}
-
-uint8_t
-DRAMPower::getDataRate(const DRAMCtrlParams* p)
-{
-uint32_t burst_cycles = divCeil(p->tBURST_MAX, p->tCK);
-uint8_t data_rate = p->burst_length / burst_cycles;
-// 4 for GDDR5
-if (data_rate != 1 && data_rate != 2 && data_rate != 4 && data_rate !=
8)
-fatal("Got unexpected data rate %d, should be 1 or 2 or 4 or 8\n");
-return data_rate;
-}
diff --git a/src/mem/drampower.hh b/src/mem/drampower.hh
index ed47476..da24bca 100644
--- a/src/mem/drampower.hh
+++ b/src/mem/drampower.hh
@@ -74,11 +74,6 @@
static Data::MemPowerSpec getPowerParams(const DRAMCtrlParams* p);
/**
- * Determine data rate, either one or two.
- */
-static uint8_t getDataRate(const DRAMCtrlParams* p);
-
-/**
* Determine if DRAM has two voltage domains (or one)
*/
static bool hasTwoVDD(const DRAMCtrlParams* p);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic8cd35bb4641d9c0a704675d2672a6fe4f4ec13e
Gerrit-Change-Number: 30056
Gerrit-PatchSet: 4
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Matthias Jung
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Wendy Elsasser
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem: Fix latency handling in MemDelay
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30055 )
Change subject: mem: Fix latency handling in MemDelay
..
mem: Fix latency handling in MemDelay
MemDelay wouldn't consume pre-existing delays in the packet and
therefore the latency it adds would overlap with them. This patch
fixes the MemDelay to properly account for them.
Change-Id: I7330fbf1c8161a21523a0b4aab31c72e34bce650
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30055
Reviewed-by: Daniel Carvalho
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/mem/mem_delay.cc
1 file changed, 14 insertions(+), 3 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/mem_delay.cc b/src/mem/mem_delay.cc
index 83177fd..9adc072 100644
--- a/src/mem/mem_delay.cc
+++ b/src/mem/mem_delay.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 ARM Limited
+ * Copyright (c) 2018, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -87,7 +87,12 @@
bool
MemDelay::MasterPort::recvTimingResp(PacketPtr pkt)
{
-const Tick when = curTick() + parent.delayResp(pkt);
+// technically the packet only reaches us after the header delay,
+// and typically we also need to deserialise any payload
+const Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
+pkt->headerDelay = pkt->payloadDelay = 0;
+
+const Tick when = curTick() + parent.delayResp(pkt) + receive_delay;
parent.slavePort.schedTimingResp(pkt, when);
@@ -136,7 +141,13 @@
bool
MemDelay::SlavePort::recvTimingReq(PacketPtr pkt)
{
-const Tick when = curTick() + parent.delayReq(pkt);
+// technically the packet only reaches us after the header
+// delay, and typically we also need to deserialise any
+// payload
+Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
+pkt->headerDelay = pkt->payloadDelay = 0;
+
+const Tick when = curTick() + parent.delayReq(pkt) + receive_delay;
parent.masterPort.schedTimingReq(pkt, when);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7330fbf1c8161a21523a0b4aab31c72e34bce650
Gerrit-Change-Number: 30055
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Assignee: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem: Add a header latency parameter to the XBar
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30054 )
Change subject: mem: Add a header latency parameter to the XBar
..
mem: Add a header latency parameter to the XBar
The XBar uses the concept of Layers to model throughput and
instantiates one Layer per master. As it forwards a packet to and from
master, the corresponding Layer is marked as occupied for a number of
cycles. Requests/responses to/from a master are blocked while the
corresponding Layer is occupied. Previously the delay would be
calculated based on the formula 1 + size / width, which assumes that
the Layer is always occupied for 1 cycle while processing the packet
header. This changes makes the header latency a parameter which
defaults to 1.
Change-Id: I12752ab4415617a94fbd8379bcd2ae8982f91fd8
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30054
Reviewed-by: Daniel Carvalho
Tested-by: kokoro
---
M src/mem/XBar.py
M src/mem/coherent_xbar.cc
M src/mem/xbar.cc
M src/mem/xbar.hh
4 files changed, 15 insertions(+), 7 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/XBar.py b/src/mem/XBar.py
index deed98f..84aae99 100644
--- a/src/mem/XBar.py
+++ b/src/mem/XBar.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012, 2015, 2017, 2019 ARM Limited
+# Copyright (c) 2012, 2015, 2017, 2019-2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -68,6 +68,11 @@
forward_latency = Param.Cycles("Forward latency")
response_latency = Param.Cycles("Response latency")
+# The XBar uses one Layer per master. Each Layer forwards a packet
+# to its destination and is occupied for header_latency + size /
+# width cycles
+header_latency = Param.Cycles(1, "Header latency")
+
# Width governing the throughput of the crossbar
width = Param.Unsigned("Datapath width per port (bytes)")
diff --git a/src/mem/coherent_xbar.cc b/src/mem/coherent_xbar.cc
index 952bd41..7fb9c34 100644
--- a/src/mem/coherent_xbar.cc
+++ b/src/mem/coherent_xbar.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2019 ARM Limited
+ * Copyright (c) 2011-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -180,7 +180,7 @@
calcPacketTiming(pkt, xbar_delay);
// determine how long to be crossbar layer is busy
-Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
+Tick packetFinishTime = clockEdge(headerLatency) + pkt->payloadDelay;
// is this the destination point for this packet? (e.g. true if
// this xbar is the PoC for a cache maintenance operation to the
@@ -471,7 +471,7 @@
calcPacketTiming(pkt, xbar_delay);
// determine how long to be crossbar layer is busy
-Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
+Tick packetFinishTime = clockEdge(headerLatency) + pkt->payloadDelay;
if (snoopFilter && !system->bypassCaches()) {
// let the snoop filter inspect the response and update its state
@@ -619,7 +619,7 @@
calcPacketTiming(pkt, xbar_delay);
// determine how long to be crossbar layer is busy
-Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
+Tick packetFinishTime = clockEdge(headerLatency) + pkt->payloadDelay;
// forward it either as a snoop response or a normal response
if (forwardAsSnoop) {
diff --git a/src/mem/xbar.cc b/src/mem/xbar.cc
index 9920216..f0b4ba3 100644
--- a/src/mem/xbar.cc
+++ b/src/mem/xbar.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2015, 2018-2019 ARM Limited
+ * Copyright (c) 2011-2015, 2018-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -56,6 +56,7 @@
frontendLatency(p->frontend_latency),
forwardLatency(p->forward_latency),
responseLatency(p->response_latency),
+ headerLatency(p->header_latency),
width(p->width),
gotAddrRanges(p->port_default_connection_count +
p->port_master_connection_count, false),
diff --git a/src/mem/xbar.hh b/src/mem/xbar.hh
index 4488f74..086d7f4 100644
--- a/src/mem/xbar.hh
+++ b/src/mem/xbar.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2015, 2018-2019 ARM Limited
+ * Copyright (c) 2011-2015, 2018-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -307,6 +307,8 @@
const Cycles frontendLatency;
const Cycles forwardLatency;
const Cycles responseLatency;
+/** Cycles the layer is occupied processing the packet header */
+const Cycles headerLatency;
/** the width of the xbar in bytes */
const uint32_t width;
--
To view, visit
[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Make indexing policies range-aware
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30095 )
Change subject: mem-cache: Make indexing policies range-aware
..
mem-cache: Make indexing policies range-aware
Change-Id: Ibdee97be47f9bd4161d74c5625ab7d5036bad689
Signed-off-by: Nikos Nikoleris
---
M src/mem/cache/tags/indexing_policies/IndexingPolicies.py
M src/mem/cache/tags/indexing_policies/base.cc
M src/mem/cache/tags/indexing_policies/base.hh
M src/mem/cache/tags/indexing_policies/set_associative.cc
M src/mem/cache/tags/indexing_policies/set_associative.hh
M src/mem/cache/tags/indexing_policies/skewed_associative.cc
M src/mem/cache/tags/indexing_policies/skewed_associative.hh
7 files changed, 85 insertions(+), 30 deletions(-)
diff --git a/src/mem/cache/tags/indexing_policies/IndexingPolicies.py
b/src/mem/cache/tags/indexing_policies/IndexingPolicies.py
index 7414ddf..058a1c9 100644
--- a/src/mem/cache/tags/indexing_policies/IndexingPolicies.py
+++ b/src/mem/cache/tags/indexing_policies/IndexingPolicies.py
@@ -42,6 +42,10 @@
# Get the associativity
assoc = Param.Int(Parent.assoc, "associativity")
+# Get the address range used by the parent (cache)
+addr_ranges = VectorParam.AddrRange(Parent.addr_ranges,
+"Address range used by the cache")
+
class SetAssociative(BaseIndexingPolicy):
type = 'SetAssociative'
cxx_class = 'SetAssociative'
diff --git a/src/mem/cache/tags/indexing_policies/base.cc
b/src/mem/cache/tags/indexing_policies/base.cc
index 6a799e6..25fd0d0 100644
--- a/src/mem/cache/tags/indexing_policies/base.cc
+++ b/src/mem/cache/tags/indexing_policies/base.cc
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2018 Inria
- * Copyright (c) 2012-2014,2017 ARM Limited
+ * Copyright (c) 2012-2014,2017,2020 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -48,6 +48,7 @@
#include
+#include "base/channel_addr.hh"
#include "base/intmath.hh"
#include "base/logging.hh"
#include "mem/cache/replacement_policies/replaceable_entry.hh"
@@ -56,7 +57,8 @@
: SimObject(p), assoc(p->assoc),
numSets(p->size / (p->entry_size * assoc)),
setShift(floorLog2(p->entry_size)), setMask(numSets - 1),
sets(numSets),
- tagShift(setShift + floorLog2(numSets))
+ tagShift(setShift + floorLog2(numSets)),
+ range(p->addr_ranges)
{
fatal_if(!isPowerOf2(numSets), "# of sets must be non-zero and a
power " \
"of 2");
@@ -95,5 +97,22 @@
Addr
BaseIndexingPolicy::extractTag(const Addr addr) const
{
-return (addr >> tagShift);
+// addr is physical, tags are extracted from relative
+ChannelAddr ch_addr(range, addr);
+return Addr(ch_addr) >> tagShift;
+}
+
+std::vector
+BaseIndexingPolicy::getPossibleEntries(const Addr addr) const
+{
+return getPossibleEntries(ChannelAddr(range, addr));
+}
+
+Addr
+BaseIndexingPolicy::regenerateAddr(const Addr tag,
+ const ReplaceableEntry* entry) const
+{
+// _regenerateAddr returns an offset into the range
+ChannelAddr ch_addr = getChannelAddr(tag, entry);
+return ch_addr.getPA(range);
}
diff --git a/src/mem/cache/tags/indexing_policies/base.hh
b/src/mem/cache/tags/indexing_policies/base.hh
index 9a56b54..803ff61 100644
--- a/src/mem/cache/tags/indexing_policies/base.hh
+++ b/src/mem/cache/tags/indexing_policies/base.hh
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2018 Inria
- * Copyright (c) 2012-2014,2017 ARM Limited
+ * Copyright (c) 2012-2014,2017,2020 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -49,6 +49,7 @@
#include
+#include "base/channel_addr.hh"
#include "params/BaseIndexingPolicy.hh"
#include "sim/sim_object.hh"
@@ -93,6 +94,33 @@
*/
const int tagShift;
+/**
+ * The range covered by this indexing policy's cache.
+ */
+const AddrRange range;
+
+/**
+ * Find all possible entries for insertion and replacement of a
+ * relative address in this range. Called by getPossibleEntries
+ * with a relative address.
+ *
+ * @param addr The addr to a find possible entries for.
+ * @return The possible entries.
+ */
+virtual std::vector getPossibleEntries(
+const ChannelAddr ch_addr) const = 0;
+
+/**
+ * Regenerate an entry's address from its tag and assigned indexing
bits.
+ * Called by regenerateAddr, should produce a relative address
+ *
+ * @param tag The tag bits.
+ * @param entry The entry.
+ * @return the entry's original address relative to the range.
+ */
+virtual ChannelAddr getChannelAddr(
+const Addr tag, const ReplaceableEntry* entry) const = 0;
+
public:
/**
* Convenience typedef.
@@ -143,8 +171,7 @@
* @param addr The addr to
[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Add support for blocking the cache on fills
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30096 )
Change subject: mem-cache: Add support for blocking the cache on fills
..
mem-cache: Add support for blocking the cache on fills
Change-Id: I0b15139cf457e4c34d4f11a6b95ca4f6bd64e4ce
Signed-off-by: Nikos Nikoleris
---
M src/mem/cache/Cache.py
M src/mem/cache/base.cc
M src/mem/cache/base.hh
3 files changed, 44 insertions(+), 9 deletions(-)
diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py
index 4f4e445..a55ed2a 100644
--- a/src/mem/cache/Cache.py
+++ b/src/mem/cache/Cache.py
@@ -79,6 +79,9 @@
tag_latency = Param.Cycles("Tag lookup latency")
data_latency = Param.Cycles("Data access latency")
+block_on_fills = Param.Bool(False, "Block the cache for further "
+"read/writes until fill completes")
+fill_latency = Param.Cycles(Self.data_latency, "Fill latency")
response_latency = Param.Cycles("Latency for the return path on a
miss");
warmup_percentage = Param.Percent(0,
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 0187703..6614d16 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -92,7 +92,8 @@
lookupLatency(p->tag_latency),
dataLatency(p->data_latency),
forwardLatency(p->tag_latency),
- fillLatency(p->data_latency),
+ blockOnFills(p->block_on_fills),
+ fillLatency(p->fill_latency),
responseLatency(p->response_latency),
sequentialAccess(p->sequential_access),
numTarget(p->tgts_per_mshr),
@@ -104,6 +105,8 @@
noTargetMSHR(nullptr),
missCount(p->max_miss_count),
addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
+ dataArrayUnblockEvent([this]{ clearBlocked(Blocked_DataArray); },
+name()),
system(p->system),
stats(*this)
{
@@ -1171,8 +1174,15 @@
// When the packet metadata arrives, the tag lookup will be done
while
// the payload is arriving. Then the block will be ready to access
as
// soon as the fill is done
-blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
-std::max(cyclesToTicks(tag_latency),
(uint64_t)pkt->payloadDelay));
+const Tick fill_done_tick = clockEdge(fillLatency) +
pkt->headerDelay +
+std::max(cyclesToTicks(tag_latency),
(uint64_t)pkt->payloadDelay);
+
+if (system->isTimingMode() && blockOnFills) {
+setBlocked(Blocked_DataArray);
+reschedule(dataArrayUnblockEvent, clockEdge(fillLatency),
true);
+}
+
+blk->setWhenReady(fill_done_tick);
return true;
} else if (pkt->cmd == MemCmd::CleanEvict) {
@@ -1245,8 +1255,15 @@
// When the packet metadata arrives, the tag lookup will be done
while
// the payload is arriving. Then the block will be ready to access
as
// soon as the fill is done
-blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
-std::max(cyclesToTicks(tag_latency),
(uint64_t)pkt->payloadDelay));
+const Tick fill_done_tick = clockEdge(fillLatency) +
pkt->headerDelay +
+std::max(cyclesToTicks(tag_latency),
(uint64_t)pkt->payloadDelay);
+
+if (system->isTimingMode() && blockOnFills) {
+setBlocked(Blocked_DataArray);
+schedule(dataArrayUnblockEvent, clockEdge(fillLatency));
+}
+
+blk->setWhenReady(fill_done_tick);
// If this a write-through packet it will be sent to cache below
return !pkt->writeThrough();
@@ -1383,6 +1400,10 @@
DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n",
addr, is_secure ? "s" : "ns", old_state, blk->print());
+// The block will be ready when the payload arrives and the fill is
done
+const Tick fill_done_tick = clockEdge(fillLatency) + pkt->headerDelay +
+pkt->payloadDelay;
+
// if we got new data, copy it in (checking for a read response
// and a response that has data is the same in the end)
if (pkt->isRead()) {
@@ -1391,10 +1412,12 @@
assert(pkt->getSize() == blkSize);
pkt->writeDataToBlock(blk->data, blkSize);
+if (system->isTimingMode() && blockOnFills) {
+setBlocked(Blocked_DataArray);
+schedule(dataArrayUnblockEvent, clockEdge(fillLatency));
+}
}
-// The block will be ready when the payload arrives and the fill is
done
-blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
- pkt->payloadDelay);
+blk->setWhenReady(fill_done_tick);
return blk;
}
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 3efc7c7..1f02c86 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -105,6 +105,7 @@
Blocked_NoMSHRs = MSHRQueue_MSHRs,
[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Add support for blocking on reads
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30097 )
Change subject: mem-cache: Add support for blocking on reads
..
mem-cache: Add support for blocking on reads
Change-Id: I1aab914956640e38e72df0da392cfaa9f95be0d6
Signed-off-by: Nikos Nikoleris
---
M src/mem/cache/Cache.py
M src/mem/cache/base.cc
M src/mem/cache/base.hh
3 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py
index a55ed2a..14668ea 100644
--- a/src/mem/cache/Cache.py
+++ b/src/mem/cache/Cache.py
@@ -79,6 +79,10 @@
tag_latency = Param.Cycles("Tag lookup latency")
data_latency = Param.Cycles("Data access latency")
+block_on_reads = Param.Bool(False, "Block the cache for further "
+"read/writes until read completes")
+data_read_latency = Param.Cycles(Self.data_latency,
+ "Data array read latency")
block_on_fills = Param.Bool(False, "Block the cache for further "
"read/writes until fill completes")
fill_latency = Param.Cycles(Self.data_latency, "Fill latency")
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 6614d16..5a0075c 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -92,6 +92,8 @@
lookupLatency(p->tag_latency),
dataLatency(p->data_latency),
forwardLatency(p->tag_latency),
+ blockOnReads(p->block_on_reads),
+ dataArrayReadLatency(p->data_read_latency),
blockOnFills(p->block_on_fills),
fillLatency(p->fill_latency),
responseLatency(p->response_latency),
@@ -219,6 +221,10 @@
assert(pkt->payloadDelay == 0);
pkt->makeTimingResponse();
+if (blockOnReads && pkt->isRead()) {
+setBlocked(Blocked_DataArray);
+schedule(dataArrayUnblockEvent,
clockEdge(dataArrayReadLatency));
+}
// In this case we are considering request_time that takes
// into account the delay of the xbar, if any, and just
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 1f02c86..6d9b602 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -858,6 +858,9 @@
*/
const Cycles forwardLatency;
+const bool blockOnReads;
+const Cycles dataArrayReadLatency;
+
const bool blockOnFills;
/**
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30097
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1aab914956640e38e72df0da392cfaa9f95be0d6
Gerrit-Change-Number: 30097
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: base: Fix ChannelAddr<->Addr conversation
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30094 )
Change subject: base: Fix ChannelAddr<->Addr conversation
..
base: Fix ChannelAddr<->Addr conversation
Previously calculating a ChannelAddr from an Addr and converting back
ignored that the start of the address range can be different than
0. After this change, ChannelAddr is always an address in the
continuous range [0, MaxChannelAddr).
Change-Id: Icd8b611c43da7f8ff102c1872b175be59ece7ae9
Signed-off-by: Nikos Nikoleris
---
M src/base/channel_addr.hh
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/base/channel_addr.hh b/src/base/channel_addr.hh
index 06fae72..56812c7 100644
--- a/src/base/channel_addr.hh
+++ b/src/base/channel_addr.hh
@@ -63,14 +63,14 @@
constexpr ChannelAddr() : a(0) { }
ChannelAddr(const AddrRange , Addr _a)
-: a(range.removeIntlvBits(_a)) {}
+: a(range.removeIntlvBits(_a) - range.start()) {}
ChannelAddr(const ChannelAddr &) = default;
ChannelAddr =(const ChannelAddr &) = default;
Addr getPA(const AddrRange ) const {
-return range.addIntlvBits(a);
+return range.addIntlvBits(a) + range.start();
}
constexpr ChannelAddr operator|(const Type b) const {
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Icd8b611c43da7f8ff102c1872b175be59ece7ae9
Gerrit-Change-Number: 30094
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem: Add a header latency parameter to the XBar
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30054 )
Change subject: mem: Add a header latency parameter to the XBar
..
mem: Add a header latency parameter to the XBar
The XBar uses the concept of Layers to model throughput and
instantiates one Layer per master. As it forwards a packet to and from
master, the corresponding Layer is marked as occupied for a number of
cycles. Requests/responses to/from a master are blocked while the
corresponding Layer is occupied. Previously the delay would be
calculated based on the formula 1 + size / width, which assumes that
the Layer is always occupied for 1 cycle while processing the packet
header. This changes makes the header latency a parameter which
defaults to 1.
Change-Id: I12752ab4415617a94fbd8379bcd2ae8982f91fd8
Signed-off-by: Nikos Nikoleris
---
M src/mem/XBar.py
M src/mem/coherent_xbar.cc
M src/mem/xbar.cc
M src/mem/xbar.hh
4 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/src/mem/XBar.py b/src/mem/XBar.py
index deed98f..84aae99 100644
--- a/src/mem/XBar.py
+++ b/src/mem/XBar.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012, 2015, 2017, 2019 ARM Limited
+# Copyright (c) 2012, 2015, 2017, 2019-2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -68,6 +68,11 @@
forward_latency = Param.Cycles("Forward latency")
response_latency = Param.Cycles("Response latency")
+# The XBar uses one Layer per master. Each Layer forwards a packet
+# to its destination and is occupied for header_latency + size /
+# width cycles
+header_latency = Param.Cycles(1, "Header latency")
+
# Width governing the throughput of the crossbar
width = Param.Unsigned("Datapath width per port (bytes)")
diff --git a/src/mem/coherent_xbar.cc b/src/mem/coherent_xbar.cc
index 952bd41..7fb9c34 100644
--- a/src/mem/coherent_xbar.cc
+++ b/src/mem/coherent_xbar.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2019 ARM Limited
+ * Copyright (c) 2011-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -180,7 +180,7 @@
calcPacketTiming(pkt, xbar_delay);
// determine how long to be crossbar layer is busy
-Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
+Tick packetFinishTime = clockEdge(headerLatency) + pkt->payloadDelay;
// is this the destination point for this packet? (e.g. true if
// this xbar is the PoC for a cache maintenance operation to the
@@ -471,7 +471,7 @@
calcPacketTiming(pkt, xbar_delay);
// determine how long to be crossbar layer is busy
-Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
+Tick packetFinishTime = clockEdge(headerLatency) + pkt->payloadDelay;
if (snoopFilter && !system->bypassCaches()) {
// let the snoop filter inspect the response and update its state
@@ -619,7 +619,7 @@
calcPacketTiming(pkt, xbar_delay);
// determine how long to be crossbar layer is busy
-Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
+Tick packetFinishTime = clockEdge(headerLatency) + pkt->payloadDelay;
// forward it either as a snoop response or a normal response
if (forwardAsSnoop) {
diff --git a/src/mem/xbar.cc b/src/mem/xbar.cc
index 9920216..f0b4ba3 100644
--- a/src/mem/xbar.cc
+++ b/src/mem/xbar.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2015, 2018-2019 ARM Limited
+ * Copyright (c) 2011-2015, 2018-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -56,6 +56,7 @@
frontendLatency(p->frontend_latency),
forwardLatency(p->forward_latency),
responseLatency(p->response_latency),
+ headerLatency(p->header_latency),
width(p->width),
gotAddrRanges(p->port_default_connection_count +
p->port_master_connection_count, false),
diff --git a/src/mem/xbar.hh b/src/mem/xbar.hh
index 4488f74..086d7f4 100644
--- a/src/mem/xbar.hh
+++ b/src/mem/xbar.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2015, 2018-2019 ARM Limited
+ * Copyright (c) 2011-2015, 2018-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -307,6 +307,8 @@
const Cycles frontendLatency;
const Cycles forwardLatency;
const Cycles responseLatency;
+/** Cycles the layer is occupied processing the packet header */
+const Cycles headerLatency;
/** the width of the xbar in bytes */
const uint32_t width;
--
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[gem5-dev] Change in gem5/gem5[develop]: mem: Fix latency handling in MemDelay
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30055 )
Change subject: mem: Fix latency handling in MemDelay
..
mem: Fix latency handling in MemDelay
MemDelay wouldn't consume pre-existing delays in the packet and
therefore the latency it adds would overlap with them. This patch
fixes the MemDelay to properly account for them.
Change-Id: I7330fbf1c8161a21523a0b4aab31c72e34bce650
Signed-off-by: Nikos Nikoleris
---
M src/mem/mem_delay.cc
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/src/mem/mem_delay.cc b/src/mem/mem_delay.cc
index 83177fd..52c1ca8 100644
--- a/src/mem/mem_delay.cc
+++ b/src/mem/mem_delay.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 ARM Limited
+ * Copyright (c) 2018, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -87,7 +87,13 @@
bool
MemDelay::MasterPort::recvTimingResp(PacketPtr pkt)
{
-const Tick when = curTick() + parent.delayResp(pkt);
+// technically the packet only reaches us after the header delay,
+// and typically we also need to deserialise any payload (unless
+// the two sides of the bridge are synchronous)
+const Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
+pkt->headerDelay = pkt->payloadDelay = 0;
+
+const Tick when = curTick() + parent.delayResp(pkt) + receive_delay;
parent.slavePort.schedTimingResp(pkt, when);
@@ -136,7 +142,14 @@
bool
MemDelay::SlavePort::recvTimingReq(PacketPtr pkt)
{
-const Tick when = curTick() + parent.delayReq(pkt);
+// technically the packet only reaches us after the header
+// delay, and typically we also need to deserialise any
+// payload (unless the two sides of the bridge are
+// synchronous)
+Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
+pkt->headerDelay = pkt->payloadDelay = 0;
+
+const Tick when = curTick() + parent.delayReq(pkt) + receive_delay;
parent.masterPort.schedTimingReq(pkt, when);
--
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Gerrit-Change-Id: I7330fbf1c8161a21523a0b4aab31c72e34bce650
Gerrit-Change-Number: 30055
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem: Use beats_per_clock as the DDR data rate for DRAMPower
Hello Wendy Elsasser,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/30056
to review the following change.
Change subject: mem: Use beats_per_clock as the DDR data rate for DRAMPower
..
mem: Use beats_per_clock as the DDR data rate for DRAMPower
The data rate is used by the drampower lib to estimate the power
consumption of the DRAM Core. Previously, we used the formula:
burst_cycles = divCeil(p->tBURST_MAX, p->tCK);
data_rate = p->burst_length / burst_cycles;
to derive the date_rate. However, under certain configurations this
formula computes the wrong result due to rounding errors. This patch
simplifies the way we derive the date_rate by passing the value of the
DRAM parameter beats_per_clock.
Change-Id: Ic8cd35bb4641d9c0a704675d2672a6fe4f4ec13e
Signed-off-by: Nikos Nikoleris
Reviewed-by: Wendy Elsasser
---
M src/mem/drampower.cc
M src/mem/drampower.hh
2 files changed, 1 insertion(+), 17 deletions(-)
diff --git a/src/mem/drampower.cc b/src/mem/drampower.cc
index f506928..13551a0 100644
--- a/src/mem/drampower.cc
+++ b/src/mem/drampower.cc
@@ -53,7 +53,7 @@
archSpec.nbrOfBanks = p->banks_per_rank;
// One DRAMPower instance per rank, hence set this to 1
archSpec.nbrOfRanks = 1;
-archSpec.dataRate = getDataRate(p);
+archSpec.dataRate = p->beats_per_clock;
// For now we can ignore the number of columns and rows as they
// are not used in the power calculation.
archSpec.nbrOfColumns = 0;
@@ -146,14 +146,3 @@
{
return p->VDD2 == 0 ? false : true;
}
-
-uint8_t
-DRAMPower::getDataRate(const DRAMCtrlParams* p)
-{
-uint32_t burst_cycles = divCeil(p->tBURST_MAX, p->tCK);
-uint8_t data_rate = p->burst_length / burst_cycles;
-// 4 for GDDR5
-if (data_rate != 1 && data_rate != 2 && data_rate != 4 && data_rate !=
8)
-fatal("Got unexpected data rate %d, should be 1 or 2 or 4 or 8\n");
-return data_rate;
-}
diff --git a/src/mem/drampower.hh b/src/mem/drampower.hh
index ed47476..da24bca 100644
--- a/src/mem/drampower.hh
+++ b/src/mem/drampower.hh
@@ -74,11 +74,6 @@
static Data::MemPowerSpec getPowerParams(const DRAMCtrlParams* p);
/**
- * Determine data rate, either one or two.
- */
-static uint8_t getDataRate(const DRAMCtrlParams* p);
-
-/**
* Determine if DRAM has two voltage domains (or one)
*/
static bool hasTwoVDD(const DRAMCtrlParams* p);
--
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Gerrit-Change-Id: Ic8cd35bb4641d9c0a704675d2672a6fe4f4ec13e
Gerrit-Change-Number: 30056
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Wendy Elsasser
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: scons: Build the marshal binary in a bare minimum environment
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28428 )
Change subject: scons: Build the marshal binary in a bare minimum
environment
..
scons: Build the marshal binary in a bare minimum environment
This change adds an additional bare minimum environment that includes
python only and changes the marshal binary to compile using it.
Change-Id: Id5d1ee6899796d746d8dc1a004cfe4795f040c55
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28428
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M SConstruct
M src/SConscript
2 files changed, 10 insertions(+), 7 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index 3345148..ba4affa 100755
--- a/SConstruct
+++ b/SConstruct
@@ -709,6 +709,10 @@
if not conf.CheckLib(lib):
error("Can't find library %s required by python." % lib)
+main.Prepend(CPPPATH=Dir('ext/pybind11/include/'))
+# Bare minimum environment that only includes python
+base_py_env = main.Clone()
+
# On Solaris you need to use libsocket for socket ops
if not
conf.CheckLibWithHeader(None, 'sys/socket.h', 'C++', 'accept(0,0,0);'):
if not conf.CheckLibWithHeader('socket', 'sys/socket.h',
@@ -1100,8 +1104,6 @@
gdb_xml_dir = joinpath(ext_dir, 'gdb-xml')
Export('gdb_xml_dir')
-main.Prepend(CPPPATH=Dir('ext/pybind11/include/'))
-
###
#
# This builder and wrapper method are used to set up a directory with
@@ -1259,7 +1261,8 @@
# The src/SConscript file sets up the build rules in 'env' according
# to the configured variables. It returns a list of environments,
# one for each variant build (debug, opt, etc.)
-SConscript('src/SConscript', variant_dir = variant_path, exports
= 'env')
+SConscript('src/SConscript', variant_dir=variant_path,
+ exports=['env', 'base_py_env'])
# base help text
Help('''
diff --git a/src/SConscript b/src/SConscript
index c7251fc..134e2a5 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1,6 +1,6 @@
# -*- mode:python -*-
-# Copyright (c) 2018 ARM Limited
+# Copyright (c) 2018, 2020 ARM Limited
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
@@ -1140,7 +1140,7 @@
# Build a small helper that marshals the Python code using the same
# version of Python as gem5. This is in an unorthodox location to
# avoid building it for every variant.
-py_marshal = env.Program('marshal', 'python/marshal.cc')[0]
+py_marshal = base_py_env.Program('marshal', 'python/marshal.cc')[0]
# Embed python files. All .py files that have been indicated by a
# PySource() call in a SConscript need to be embedded into the M5
@@ -1196,8 +1196,8 @@
code.write(str(target[0]))
for source in PySource.all:
-env.Command(source.cpp, [ py_marshal, source.tnode ],
-MakeAction(embedPyFile, Transform("EMBED PY")))
+base_py_env.Command(source.cpp, [ py_marshal, source.tnode ],
+MakeAction(embedPyFile, Transform("EMBED PY")))
Source(source.cpp, tags=source.tags, add_tags='python')
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id5d1ee6899796d746d8dc1a004cfe4795f040c55
Gerrit-Change-Number: 28428
Gerrit-PatchSet: 2
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Build the marshal binary in a bare minimum environment
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28428 )
Change subject: scons: Build the marshal binary in a bare minimum
environment
..
scons: Build the marshal binary in a bare minimum environment
This change adds an additional bare minimum environment that includes
python only and changes the marshal binary to compile using it.
Change-Id: Id5d1ee6899796d746d8dc1a004cfe4795f040c55
Signed-off-by: Nikos Nikoleris
---
M SConstruct
M src/SConscript
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/SConstruct b/SConstruct
index 3345148..ba4affa 100755
--- a/SConstruct
+++ b/SConstruct
@@ -709,6 +709,10 @@
if not conf.CheckLib(lib):
error("Can't find library %s required by python." % lib)
+main.Prepend(CPPPATH=Dir('ext/pybind11/include/'))
+# Bare minimum environment that only includes python
+base_py_env = main.Clone()
+
# On Solaris you need to use libsocket for socket ops
if not
conf.CheckLibWithHeader(None, 'sys/socket.h', 'C++', 'accept(0,0,0);'):
if not conf.CheckLibWithHeader('socket', 'sys/socket.h',
@@ -1100,8 +1104,6 @@
gdb_xml_dir = joinpath(ext_dir, 'gdb-xml')
Export('gdb_xml_dir')
-main.Prepend(CPPPATH=Dir('ext/pybind11/include/'))
-
###
#
# This builder and wrapper method are used to set up a directory with
@@ -1259,7 +1261,8 @@
# The src/SConscript file sets up the build rules in 'env' according
# to the configured variables. It returns a list of environments,
# one for each variant build (debug, opt, etc.)
-SConscript('src/SConscript', variant_dir = variant_path, exports
= 'env')
+SConscript('src/SConscript', variant_dir=variant_path,
+ exports=['env', 'base_py_env'])
# base help text
Help('''
diff --git a/src/SConscript b/src/SConscript
index c7251fc..134e2a5 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1,6 +1,6 @@
# -*- mode:python -*-
-# Copyright (c) 2018 ARM Limited
+# Copyright (c) 2018, 2020 ARM Limited
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
@@ -1140,7 +1140,7 @@
# Build a small helper that marshals the Python code using the same
# version of Python as gem5. This is in an unorthodox location to
# avoid building it for every variant.
-py_marshal = env.Program('marshal', 'python/marshal.cc')[0]
+py_marshal = base_py_env.Program('marshal', 'python/marshal.cc')[0]
# Embed python files. All .py files that have been indicated by a
# PySource() call in a SConscript need to be embedded into the M5
@@ -1196,8 +1196,8 @@
code.write(str(target[0]))
for source in PySource.all:
-env.Command(source.cpp, [ py_marshal, source.tnode ],
-MakeAction(embedPyFile, Transform("EMBED PY")))
+base_py_env.Command(source.cpp, [ py_marshal, source.tnode ],
+MakeAction(embedPyFile, Transform("EMBED PY")))
Source(source.cpp, tags=source.tags, add_tags='python')
--
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Gerrit-Change-Number: 28428
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm, mem-ruby, sim: Add missing overrides
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28168 )
Change subject: arch-arm, mem-ruby, sim: Add missing overrides
..
arch-arm, mem-ruby, sim: Add missing overrides
Change-Id: I5ab18960bd61953e6846426adb657818f825
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28168
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/arm/isa.hh
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/Sequencer.hh
M src/sim/kernel_workload.hh
4 files changed, 15 insertions(+), 15 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 5fec2db..b4fbbbf 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -726,14 +726,14 @@
unsigned eCount);
void
-serialize(CheckpointOut ) const
+serialize(CheckpointOut ) const override
{
DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
}
void
-unserialize(CheckpointIn )
+unserialize(CheckpointIn ) override
{
DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
diff --git a/src/mem/ruby/system/GPUCoalescer.hh
b/src/mem/ruby/system/GPUCoalescer.hh
index 620b5ee..1321173 100644
--- a/src/mem/ruby/system/GPUCoalescer.hh
+++ b/src/mem/ruby/system/GPUCoalescer.hh
@@ -102,9 +102,9 @@
void wakeup(); // Used only for deadlock detection
void printProgress(std::ostream& out) const;
-void resetStats();
+void resetStats() override;
void collateStats();
-void regStats();
+void regStats() override;
void writeCallback(Addr address, DataBlock& data);
@@ -157,18 +157,18 @@
void recordCPWriteCallBack(MachineID myMachID, MachineID senderMachID);
// Alternate implementations in VIPER Coalescer
-virtual RequestStatus makeRequest(PacketPtr pkt);
+virtual RequestStatus makeRequest(PacketPtr pkt) override;
-int outstandingCount() const { return m_outstanding_count; }
+int outstandingCount() const override { return m_outstanding_count; }
bool
-isDeadlockEventScheduled() const
+isDeadlockEventScheduled() const override
{
return deadlockCheckEvent.scheduled();
}
void
-descheduleDeadlockEvent()
+descheduleDeadlockEvent() override
{
deschedule(deadlockCheckEvent);
}
diff --git a/src/mem/ruby/system/Sequencer.hh
b/src/mem/ruby/system/Sequencer.hh
index 0569478..bb2819b 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -86,9 +86,9 @@
// Public Methods
void wakeup(); // Used only for deadlock detection
-void resetStats();
+void resetStats() override;
void collateStats();
-void regStats();
+void regStats() override;
void writeCallback(Addr address,
DataBlock& data,
@@ -106,14 +106,14 @@
const Cycles forwardRequestTime = Cycles(0),
const Cycles firstResponseTime = Cycles(0));
-RequestStatus makeRequest(PacketPtr pkt);
+RequestStatus makeRequest(PacketPtr pkt) override;
bool empty() const;
-int outstandingCount() const { return m_outstanding_count; }
+int outstandingCount() const override { return m_outstanding_count; }
-bool isDeadlockEventScheduled() const
+bool isDeadlockEventScheduled() const override
{ return deadlockCheckEvent.scheduled(); }
-void descheduleDeadlockEvent()
+void descheduleDeadlockEvent() override
{ deschedule(deadlockCheckEvent); }
void print(std::ostream& out) const;
diff --git a/src/sim/kernel_workload.hh b/src/sim/kernel_workload.hh
index 972a539..b88051a 100644
--- a/src/sim/kernel_workload.hh
+++ b/src/sim/kernel_workload.hh
@@ -98,7 +98,7 @@
}
bool
-insertSymbol(Addr address, const std::string )
+insertSymbol(Addr address, const std::string ) override
{
return kernelSymtab->insert(address, symbol);
}
--
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Gerrit-Change-Id: I5ab18960bd61953e6846426adb657818f825
Gerrit-Change-Number: 28168
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType:
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Removed the unused parameter m_id from VirtualChannel
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28171 )
Change subject: mem-ruby: Removed the unused parameter m_id from
VirtualChannel
..
mem-ruby: Removed the unused parameter m_id from VirtualChannel
Change-Id: Ie6f8db9b1cb0d0e0ca694c631c6662413fd833c1
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28171
Reviewed-by: Jason Lowe-Power
Reviewed-by: Srikant Bharadwaj
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/mem/ruby/network/garnet2.0/InputUnit.cc
M src/mem/ruby/network/garnet2.0/VirtualChannel.cc
M src/mem/ruby/network/garnet2.0/VirtualChannel.hh
3 files changed, 4 insertions(+), 5 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Srikant Bharadwaj: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/network/garnet2.0/InputUnit.cc
b/src/mem/ruby/network/garnet2.0/InputUnit.cc
index 8fdce06..640e3b4 100644
--- a/src/mem/ruby/network/garnet2.0/InputUnit.cc
+++ b/src/mem/ruby/network/garnet2.0/InputUnit.cc
@@ -52,7 +52,7 @@
// Instantiating the virtual channels
virtualChannels.reserve(m_num_vcs);
for (int i=0; i < m_num_vcs; i++) {
-virtualChannels.emplace_back(i);
+virtualChannels.emplace_back();
}
}
diff --git a/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
b/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
index 3b077d4..a469a84 100644
--- a/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
+++ b/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
@@ -31,8 +31,8 @@
#include "mem/ruby/network/garnet2.0/VirtualChannel.hh"
-VirtualChannel::VirtualChannel(int id)
- : m_id(id), inputBuffer(), m_vc_state(IDLE_, Cycles(0)),
m_output_port(-1),
+VirtualChannel::VirtualChannel()
+ : inputBuffer(), m_vc_state(IDLE_, Cycles(0)), m_output_port(-1),
m_enqueue_time(INFINITE_), m_output_vc(-1)
{
}
diff --git a/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
b/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
index 52963c8..752dfb4 100644
--- a/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
+++ b/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
@@ -40,7 +40,7 @@
class VirtualChannel
{
public:
-VirtualChannel(int id);
+VirtualChannel();
~VirtualChannel() = default;
bool need_stage(flit_stage stage, Cycles time);
@@ -89,7 +89,6 @@
uint32_t functionalWrite(Packet *pkt);
private:
-int m_id;
flitBuffer inputBuffer;
std::pair m_vc_state;
int m_output_port;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie6f8db9b1cb0d0e0ca694c631c6662413fd833c1
Gerrit-Change-Number: 28171
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Srikant Bharadwaj
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Avoid const from member due to ::operator=(...)
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28249 )
Change subject: mem-ruby: Avoid const from member due to
::operator=(...)
..
mem-ruby: Avoid const from member due to ::operator=(...)
Change-Id: I172f48ce8ee4a3870165309342dadc2ac39ded9a
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28249
Reviewed-by: Matthew Poremba
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/mem/ruby/slicc_interface/Message.hh
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Matthew Poremba: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/slicc_interface/Message.hh
b/src/mem/ruby/slicc_interface/Message.hh
index 0c2e0aa..1044fe0 100644
--- a/src/mem/ruby/slicc_interface/Message.hh
+++ b/src/mem/ruby/slicc_interface/Message.hh
@@ -104,7 +104,7 @@
void setVnet(int net) { vnet = net; }
private:
-const Tick m_time;
+Tick m_time;
Tick m_LastEnqueueTime; // my last enqueue time
Tick m_DelayedTicks; // my delayed cycles
uint64_t m_msg_counter; // FIXME, should this be a 64-bit value?
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I172f48ce8ee4a3870165309342dadc2ac39ded9a
Gerrit-Change-Number: 28249
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix inconsistency in variable name
Nikos Nikoleris has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/28172 ) Change subject: arch-arm: Fix inconsistency in variable name .. arch-arm: Fix inconsistency in variable name Change-Id: I091a2d0cc8bfa7b8d98c4f508d175868d0fd7249 Signed-off-by: Nikos Nikoleris Reviewed-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28172 Maintainer: Giacomo Travaglini Tested-by: kokoro --- M src/arch/arm/freebsd/process.cc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/freebsd/process.cc b/src/arch/arm/freebsd/process.cc index 3955f85..d8a7d68 100644 --- a/src/arch/arm/freebsd/process.cc +++ b/src/arch/arm/freebsd/process.cc @@ -118,7 +118,7 @@ void *holdp = (void *)buf2.bufferPtr(); size_t *holdlenp = (size_t *)buf3.bufferPtr(); -ret = sysctl((int *)hnamep, namelen, holdp, holdlenp, hnewp, newlen); +ret = sysctl((int *)hnamep, nameLen, holdp, holdlenp, hnewp, newlen); buf.copyOut(tc->getVirtProxy()); buf2.copyOut(tc->getVirtProxy()); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28172 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I091a2d0cc8bfa7b8d98c4f508d175868d0fd7249 Gerrit-Change-Number: 28172 Gerrit-PatchSet: 3 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Downgrade constexpr causing build errors to const
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28167 )
Change subject: arch-arm: Downgrade constexpr causing build errors to const
..
arch-arm: Downgrade constexpr causing build errors to const
Change-Id: Idf5ae62603b6181d44aaaef91b774fa7b26eb718
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28167
Tested-by: kokoro
---
M src/arch/arm/aapcs32.hh
1 file changed, 7 insertions(+), 7 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/aapcs32.hh b/src/arch/arm/aapcs32.hh
index fd63483..e2e5d09 100644
--- a/src/arch/arm/aapcs32.hh
+++ b/src/arch/arm/aapcs32.hh
@@ -489,12 +489,12 @@
if (state.variadic)
return getArgument(tc, state);
-int index = state.allocate(Float{}, 1);
+const int index = state.allocate(Float{}, 1);
if (index >= 0) {
constexpr int lane_per_reg = 16 / sizeof(Float);
-constexpr int reg = index / lane_per_reg;
-constexpr int lane = index % lane_per_reg;
+const int reg = index / lane_per_reg;
+const int lane = index % lane_per_reg;
RegId id(VecRegClass, reg);
auto val = tc->readVecReg(id);
@@ -558,14 +558,14 @@
if (useBaseABI(state))
return getArgument(tc, state);
-int base = state.allocate(Elem{}, Count);
+const int base = state.allocate(Elem{}, Count);
if (base >= 0) {
constexpr int lane_per_reg = 16 / sizeof(Elem);
HA ha;
for (int i = 0; i < Count; i++) {
-constexpr int index = base + i;
-constexpr int reg = index / lane_per_reg;
-constexpr int lane = index % lane_per_reg;
+const int index = base + i;
+const int reg = index / lane_per_reg;
+const int lane = index % lane_per_reg;
RegId id(VecRegClass, reg);
auto val = tc->readVecReg(id);
--
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Gerrit-Change-Id: Idf5ae62603b6181d44aaaef91b774fa7b26eb718
Gerrit-Change-Number: 28167
Gerrit-PatchSet: 4
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Disable unsupported -Wl,--as-needed in MacOS
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28173 )
Change subject: scons: Disable unsupported -Wl,--as-needed in MacOS
..
scons: Disable unsupported -Wl,--as-needed in MacOS
Change-Id: Id6f8199b818217c4fcf4b80efdb7cc9e1d14e32b
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28173
Reviewed-by: Jason Lowe-Power
Maintainer: Gabe Black
Tested-by: kokoro
---
M SConstruct
1 file changed, 4 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index 215c0b6..3345148 100755
--- a/SConstruct
+++ b/SConstruct
@@ -359,7 +359,10 @@
main.Append(CCFLAGS=['-I/usr/local/include'])
main.Append(CXXFLAGS=['-I/usr/local/include'])
-main.Append(LINKFLAGS='-Wl,--as-needed')
+# On Mac OS X/Darwin the default linker doesn't support the
+# option --as-needed
+if sys.platform != "darwin":
+main.Append(LINKFLAGS='-Wl,--as-needed')
main['FILTER_PSHLINKFLAGS'] = lambda x: str(x).replace(' -shared', '')
main['PSHLINKFLAGS'] =
main.subst('${FILTER_PSHLINKFLAGS(SHLINKFLAGS)}')
if GetOption('gold_linker'):
--
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Gerrit-Change-Id: Id6f8199b818217c4fcf4b80efdb7cc9e1d14e32b
Gerrit-Change-Number: 28173
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix access modifier in Arm*ProcessBits class
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28248 )
Change subject: arch-arm: Fix access modifier in Arm*ProcessBits class
..
arch-arm: Fix access modifier in Arm*ProcessBits class
Change-Id: Ie983abc94dd9e62bbec3f584b70b0d04d6e8305d
Reviewed-by: Giacomo Travaglini
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28248
Reviewed-by: Bobby R. Bruce
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/arm/freebsd/process.hh
M src/arch/arm/linux/process.hh
2 files changed, 3 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/freebsd/process.hh
b/src/arch/arm/freebsd/process.hh
index ac0092e..d52512a 100644
--- a/src/arch/arm/freebsd/process.hh
+++ b/src/arch/arm/freebsd/process.hh
@@ -39,7 +39,7 @@
class ArmFreebsdProcessBits
{
- protected:
+ public:
struct SyscallABI {};
};
diff --git a/src/arch/arm/linux/process.hh b/src/arch/arm/linux/process.hh
index 0662d9f..0c15c28 100644
--- a/src/arch/arm/linux/process.hh
+++ b/src/arch/arm/linux/process.hh
@@ -1,5 +1,5 @@
/*
-* Copyright (c) 2011-2012 ARM Limited
+ * Copyright (c) 2011-2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -47,7 +47,7 @@
class ArmLinuxProcessBits
{
- protected:
+ public:
struct SyscallABI {};
};
--
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Gerrit-Change-Id: Ie983abc94dd9e62bbec3f584b70b0d04d6e8305d
Gerrit-Change-Number: 28248
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix function signature inconsistencies in semihosting
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28170 )
Change subject: arch-arm: Fix function signature inconsistencies in
semihosting
..
arch-arm: Fix function signature inconsistencies in semihosting
Change-Id: Icb1aa30cb67b676d49681f68e1d62b3af409e26b
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28170
Reviewed-by: Gabe Black
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/semihosting.cc
1 file changed, 6 insertions(+), 6 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 7718cd0..7711a86 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -305,7 +305,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callClose(ThreadContext *tc, uint64_t handle)
+ArmSemihosting::callClose(ThreadContext *tc, Handle handle)
{
if (handle > files.size()) {
DPRINTF(Semihosting, "Semihosting SYS_CLOSE(%i): Illegal file\n");
@@ -350,7 +350,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callWrite(ThreadContext *tc, uint64_t handle, Addr addr,
+ArmSemihosting::callWrite(ThreadContext *tc, Handle handle, Addr addr,
size_t size)
{
if (handle > files.size() || !files[handle])
@@ -371,7 +371,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callRead(ThreadContext *tc, uint64_t handle, Addr addr,
+ArmSemihosting::callRead(ThreadContext *tc, Handle handle, Addr addr,
size_t size)
{
if (handle > files.size() || !files[handle])
@@ -404,7 +404,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callIsTTY(ThreadContext *tc, uint64_t handle)
+ArmSemihosting::callIsTTY(ThreadContext *tc, Handle handle)
{
if (handle > files.size() || !files[handle])
return retError(EBADF);
@@ -418,7 +418,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callSeek(ThreadContext *tc, uint64_t handle, uint64_t pos)
+ArmSemihosting::callSeek(ThreadContext *tc, Handle handle, uint64_t pos)
{
if (handle > files.size() || !files[handle])
return retError(EBADF);
@@ -432,7 +432,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callFLen(ThreadContext *tc, uint64_t handle)
+ArmSemihosting::callFLen(ThreadContext *tc, Handle handle)
{
if (handle > files.size() || !files[handle])
return retError(EBADF);
--
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Gerrit-Change-Id: Icb1aa30cb67b676d49681f68e1d62b3af409e26b
Gerrit-Change-Number: 28170
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Fix mismatch between #ifndef and #define in varargs.hh
Nikos Nikoleris has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/28169 ) Change subject: sim: Fix mismatch between #ifndef and #define in varargs.hh .. sim: Fix mismatch between #ifndef and #define in varargs.hh Change-Id: I558b6c3c69a5003a77cc95b414e620715c3dbbae Signed-off-by: Nikos Nikoleris Reviewed-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28169 Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- M src/sim/guest_abi/varargs.hh 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Gabe Black: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/sim/guest_abi/varargs.hh b/src/sim/guest_abi/varargs.hh index 41e3c62..6a19db8 100644 --- a/src/sim/guest_abi/varargs.hh +++ b/src/sim/guest_abi/varargs.hh @@ -26,7 +26,7 @@ */ #ifndef __SIM_GUEST_ABI_VARARGS_HH__ -#define __SIM_GUEST_ABI_VARRAGS_HH__ +#define __SIM_GUEST_ABI_VARARGS_HH__ #include #include -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28169 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I558b6c3c69a5003a77cc95b414e620715c3dbbae Gerrit-Change-Number: 28169 Gerrit-PatchSet: 3 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim: Inheritance fixes in varargs
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28250 )
Change subject: sim: Inheritance fixes in varargs
..
sim: Inheritance fixes in varargs
Change-Id: I3c6027223893363df098d1990a4ad3d07c2ff5ff
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28250
Reviewed-by: Bobby R. Bruce
Reviewed-by: Jason Lowe-Power
Reviewed-by: Gabe Black
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/sim/guest_abi/varargs.hh
1 file changed, 4 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Gabe Black: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/guest_abi/varargs.hh b/src/sim/guest_abi/varargs.hh
index 6a19db8..07ed2a1 100644
--- a/src/sim/guest_abi/varargs.hh
+++ b/src/sim/guest_abi/varargs.hh
@@ -70,6 +70,8 @@
class VarArgsBase : public VarArgsBase
{
public:
+virtual ~VarArgsBase() = default;
+
// The virtual function takes a reference parameter so that the
different
// _getImpl methods can co-exist through overloading.
virtual void _getImpl(First &) = 0;
@@ -126,6 +128,8 @@
// Declare state to pass to the Argument<>::get methods.
ThreadContext *tc;
typename ABI::State state;
+// Make sure base class _getImpl-es don't get hidden by ours.
+using Base::_getImpl;
// Give the "using" statement in our subclass something to refer to.
void _getImpl();
--
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Gerrit-Change-Id: I3c6027223893363df098d1990a4ad3d07c2ff5ff
Gerrit-Change-Number: 28250
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim-power: Creation of PowerState class
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28049 )
Change subject: sim-power: Creation of PowerState class
..
sim-power: Creation of PowerState class
This commit does not make any functional changes but just rearranges
the existing code with regard to the power states. Previously, all
code regarding power states was in the ClockedObjects. However, it
seems more logical and cleaner to move this code into a separate
class, called PowerState. The PowerState is a now SimObject. Every
ClockedObject has a PowerState but this patch also allows for objects
with PowerState which are not ClockedObjects.
Change-Id: Id2db86dc14f140dc9d0912a8a7de237b9df9120d
Reviewed-by: Andreas Sandberg
Reviewed-by: Sascha Bischoff
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28049
Reviewed-by: Bobby R. Bruce
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M configs/example/arm/fs_power.py
M src/cpu/base.cc
M src/dev/arm/fvp_base_pwr_ctrl.cc
M src/sim/ClockedObject.py
A src/sim/PowerState.py
M src/sim/SConscript
M src/sim/clocked_object.cc
M src/sim/clocked_object.hh
M src/sim/power/power_model.cc
A src/sim/power_state.cc
A src/sim/power_state.hh
11 files changed, 432 insertions(+), 231 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/example/arm/fs_power.py
b/configs/example/arm/fs_power.py
index abc759e..72c6292 100644
--- a/configs/example/arm/fs_power.py
+++ b/configs/example/arm/fs_power.py
@@ -114,7 +114,7 @@
if not isinstance(cpu, m5.objects.BaseCPU):
continue
-cpu.default_p_state = "ON"
+cpu.power_state.default_state = "ON"
cpu.power_model = CpuPowerModel(cpu.path())
# Example power model for the L2 Cache of the bigCluster
@@ -122,7 +122,7 @@
if not isinstance(l2, m5.objects.Cache):
continue
-l2.default_p_state = "ON"
+l2.power_state.default_state = "ON"
l2.power_model = L2PowerModel(l2.path())
bL.instantiate(options)
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index d9cbc1c..3647482 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -329,11 +329,11 @@
}
if (_switchedOut)
-ClockedObject::pwrState(Enums::PwrState::OFF);
+powerState->set(Enums::PwrState::OFF);
// Assumption CPU start to operate instantaneously without any latency
-if (ClockedObject::pwrState() == Enums::PwrState::UNDEFINED)
-ClockedObject::pwrState(Enums::PwrState::ON);
+if (powerState->get() == Enums::PwrState::UNDEFINED)
+powerState->set(Enums::PwrState::ON);
}
@@ -463,7 +463,7 @@
return;
}
-if (ClockedObject::pwrState() == Enums::PwrState::CLK_GATED &&
+if (powerState->get() == Enums::PwrState::CLK_GATED &&
powerGatingOnIdle) {
assert(!enterPwrGatingEvent.scheduled());
// Schedule a power gating event when clock gated for the specified
@@ -492,7 +492,7 @@
if (enterPwrGatingEvent.scheduled())
deschedule(enterPwrGatingEvent);
// For any active thread running, update CPU power state to active (ON)
-ClockedObject::pwrState(Enums::PwrState::ON);
+powerState->set(Enums::PwrState::ON);
updateCycleCounters(CPU_STATE_WAKEUP);
}
@@ -513,7 +513,7 @@
updateCycleCounters(CPU_STATE_SLEEP);
// All CPU threads suspended, enter lower power state for the CPU
-ClockedObject::pwrState(Enums::PwrState::CLK_GATED);
+powerState->set(Enums::PwrState::CLK_GATED);
// If pwrGatingLatency is set to 0 then this mechanism is disabled
if (powerGatingOnIdle) {
@@ -532,7 +532,7 @@
void
BaseCPU::enterPwrGating(void)
{
-ClockedObject::pwrState(Enums::PwrState::OFF);
+powerState->set(Enums::PwrState::OFF);
}
void
@@ -548,7 +548,7 @@
flushTLBs();
// Go to the power gating state
-ClockedObject::pwrState(Enums::PwrState::OFF);
+powerState->set(Enums::PwrState::OFF);
}
void
@@ -561,7 +561,7 @@
_pid = oldCPU->getPid();
_taskId = oldCPU->taskId();
// Take over the power state of the switchedOut CPU
-ClockedObject::pwrState(oldCPU->pwrState());
+powerState->set(oldCPU->powerState->get());
previousState = oldCPU->previousState;
previousCycle = oldCPU->previousCycle;
diff --git a/src/dev/arm/fvp_base_pwr_ctrl.cc
b/src/dev/arm/fvp_base_pwr_ctrl.cc
index a6650b8..5113c92 100644
--- a/src/dev/arm/fvp_base_pwr_ctrl.cc
+++ b/src/dev/arm/fvp_base_pwr_ctrl.cc
@@ -280,7 +280,7 @@
npwrs->pc = 0;
}
}
-tc->getCpuPtr()->pwrState(Enums::PwrState::ON);
+tc->getCpuPtr()->powerState->set(Enums::PwrState::ON);
}
void
@@ -295,7 +295,7 @@
pwrs->pc = 0;
// Clear power-on reason
pwrs->wk = 0;
-
[gem5-dev] Change in gem5/gem5[develop]: configs: Change fs_power.py to use absolute paths for stats
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27893 )
Change subject: configs: Change fs_power.py to use absolute paths for stats
..
configs: Change fs_power.py to use absolute paths for stats
fs_power.py is an example script that demonstrates how power models
can be used with gem5. Previously, the formulas used to calculate the
dynamic and static power of the cores and the L2 cache were using
stats in equations as determined by their path relative to the
SimObject where the power model is attached to or full paths. This CL
changes these formulas to refer to the stats only by their full paths.
Change-Id: I91ea16c88c6a884fce90fd4cd2dfabcba4a1326c
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27893
Reviewed-by: Bobby R. Bruce
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M configs/example/arm/fs_power.py
1 file changed, 35 insertions(+), 25 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/example/arm/fs_power.py
b/configs/example/arm/fs_power.py
index 13afe90..abc759e 100644
--- a/configs/example/arm/fs_power.py
+++ b/configs/example/arm/fs_power.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2017 ARM Limited
+# Copyright (c) 2017, 2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -49,42 +49,52 @@
class CpuPowerOn(MathExprPowerModel):
-# 2A per IPC, 3pA per cache miss
-# and then convert to Watt
-dyn = "voltage * (2 * ipc + " \
-"3 * 0.1 * dcache.overall_misses / sim_seconds)"
-st = "4 * temp"
+def __init__(self, cpu_path, **kwargs):
+super(CpuPowerOn, self).__init__(**kwargs)
+# 2A per IPC, 3pA per cache miss
+# and then convert to Watt
+self.dyn = "voltage * (2 * {}.ipc + 3 * 0.1 * " \
+"{}.dcache.overall_misses /
sim_seconds)".format(cpu_path,
+
cpu_path)
+self.st = "4 * temp"
class CpuPowerOff(MathExprPowerModel):
dyn = "0"
st = "0"
class CpuPowerModel(PowerModel):
-pm = [
-CpuPowerOn(), # ON
-CpuPowerOff(), # CLK_GATED
-CpuPowerOff(), # SRAM_RETENTION
-CpuPowerOff(), # OFF
-]
+def __init__(self, cpu_path, **kwargs):
+super(CpuPowerModel, self).__init__(**kwargs)
+self.pm = [
+CpuPowerOn(cpu_path), # ON
+CpuPowerOff(), # CLK_GATED
+CpuPowerOff(), # SRAM_RETENTION
+CpuPowerOff(), # OFF
+]
class L2PowerOn(MathExprPowerModel):
-# Example to report l2 Cache overall_accesses
-# The estimated power is converted to Watt and will vary based on the
size of the cache
-dyn = "overall_accesses*0.18000"
-st = "(voltage * 3)/10"
+def __init__(self, l2_path, **kwargs):
+super(L2PowerOn, self).__init__(**kwargs)
+# Example to report l2 Cache overall_accesses
+# The estimated power is converted to Watt and will vary based
+# on the size of the cache
+self.dyn = "{}.overall_accesses * 0.18000".format(l2_path)
+self.st = "(voltage * 3)/10"
class L2PowerOff(MathExprPowerModel):
dyn = "0"
st = "0"
class L2PowerModel(PowerModel):
-# Choose a power model for every power state
-pm = [
-L2PowerOn(), # ON
-L2PowerOff(), # CLK_GATED
-L2PowerOff(), # SRAM_RETENTION
-L2PowerOff(), # OFF
-]
+def __init__(self, l2_path, **kwargs):
+super(L2PowerModel, self).__init__(**kwargs)
+# Choose a power model for every power state
+self.pm = [
+L2PowerOn(l2_path), # ON
+L2PowerOff(), # CLK_GATED
+L2PowerOff(), # SRAM_RETENTION
+L2PowerOff(), # OFF
+]
def main():
@@ -105,7 +115,7 @@
continue
cpu.default_p_state = "ON"
-cpu.power_model = CpuPowerModel()
+cpu.power_model = CpuPowerModel(cpu.path())
# Example power model for the L2 Cache of the bigCluster
for l2 in root.system.bigCluster.l2.descendants():
@@ -113,7 +123,7 @@
continue
l2.default_p_state = "ON"
-l2.power_model = L2PowerModel()
+l2.power_model = L2PowerModel(l2.path())
bL.instantiate(options)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27893
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I91ea16c88c6a884fce90fd4cd2dfabcba4a1326c
Gerrit-Change-Number: 27893
Gerrit-PatchSet: 3
[gem5-dev] Change in gem5/gem5[develop]: sim-power: Addition of PowerDomains
Nikos Nikoleris has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/28051 ) Change subject: sim-power: Addition of PowerDomains .. sim-power: Addition of PowerDomains PowerDomains group multiple objects together to regulate their power state. There are 2 types of objects in a PowerDomain: leaders and followers. The power state of a PowerDomain is the most performant power state of any of the leaders. The power state of the followers is determined by the power state of the PowerDomain they belong to: they need to be in a power state which is more or equally performant to the power state of the PowerDomain. Leaders can be ClockedObjects or other PowerDomains. Followers can only be ClockedObjects. PowerDomains can be be nested but a PowerDomain can only be a leader of another PowerDomain, NOT a follower. PowerDomains are not present in the hierarchy by default, the user needs to create and configure them in the configuration file. The user can add an hierachy by setting the led_by parameter. gem5 will then create leaders and followers for each domain and calculate the allowed power states for the domain. Objects in a PowerDomain need to have at least the ON state in the possible_states. An example of a powerDomain config is: pd = PowerDomain() cpu0 = BaseCPU() cpu1 = BaseCPU() shared_cache = BaseCache() cache.power_state.led_by = pd pd.led_by = [cpu0, cpu1] This will create a PowerDomain, where the CPUs determine their own power states and the shared cache (via the PowerDomain) follows those power states (when possible). Change-Id: I4c4cd01f06d45476c6e0fb2afeb778613733e2ff Reviewed-by: Andreas Sandberg Reviewed-by: Sascha Bischoff Signed-off-by: Nikos Nikoleris Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28051 Reviewed-by: Bobby R. Bruce Maintainer: Jason Lowe-Power Tested-by: kokoro --- A src/sim/PowerDomain.py M src/sim/PowerState.py M src/sim/SConscript A src/sim/power_domain.cc A src/sim/power_domain.hh M src/sim/power_state.cc M src/sim/power_state.hh 7 files changed, 587 insertions(+), 2 deletions(-) Approvals: Bobby R. Bruce: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved kokoro: Regressions pass diff --git a/src/sim/PowerDomain.py b/src/sim/PowerDomain.py new file mode 100644 index 000..9d45252 --- /dev/null +++ b/src/sim/PowerDomain.py @@ -0,0 +1,49 @@ +# Copyright (c) 2017, 2019-2020 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +import sys + +from m5.params import * +from m5.objects.PowerState import PowerState + +# A power domain groups multiple ClockedObjects and creates a +# hierarchy in which follower ClockedObjects (caches for example) can +# change power state depeding on what the leader objects (CPUs for +# example) do. The power domain is the link between these. +class PowerDomain(PowerState): +type =
[gem5-dev] Change in gem5/gem5[develop]: sim-power: Specify the states a PowerState object can be in
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28050 )
Change subject: sim-power: Specify the states a PowerState object can be in
..
sim-power: Specify the states a PowerState object can be in
This commit adds the concept of possible power states to the
PowerState SimObject. This is a list of the power states a specific
object can be in. Before transitioning to a power state, a PowerState
object will first check if the requested power states is actually an
allowed state. The user can restricted the power states a
ClockedObject can go to during configuration. In addition, this change
sets the power states, a CPU can be in.
Change-Id: Ida414a87554a14f09767a272b54b5d19bfc8e911
Reviewed-by: Andreas Sandberg
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28050
Reviewed-by: Bobby R. Bruce
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/cpu/BaseCPU.py
M src/sim/PowerState.py
M src/sim/power_state.cc
M src/sim/power_state.hh
4 files changed, 28 insertions(+), 1 deletion(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 67d95d0..ab70d1d 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -303,3 +303,7 @@
cpus_node.append(node)
yield cpus_node
+
+def __init__(self, **kwargs):
+super(BaseCPU, self).__init__(**kwargs)
+self.power_state.possible_states=['ON', 'CLK_GATED', 'OFF']
diff --git a/src/sim/PowerState.py b/src/sim/PowerState.py
index 59491ec..bfa53e2 100644
--- a/src/sim/PowerState.py
+++ b/src/sim/PowerState.py
@@ -62,6 +62,11 @@
# routine
default_state = Param.PwrState("UNDEFINED", "Default Power State")
+# Possible power states this object can be in sorted from the most
+# to the least performant
+possible_states = VectorParam.PwrState(
+[], "Power states this object can be in")
+
clk_gate_min = Param.Latency('1ns',"Min value of the distribution")
clk_gate_max = Param.Latency('1s',"Max value of the distribution")
clk_gate_bins = Param.Unsigned('20', "# bins in clk gated
distribution")
diff --git a/src/sim/power_state.cc b/src/sim/power_state.cc
index 28b0b83..a2ed7fe 100644
--- a/src/sim/power_state.cc
+++ b/src/sim/power_state.cc
@@ -41,7 +41,9 @@
PowerState::PowerState(const PowerStateParams *p) :
SimObject(p), _currState(p->default_state),
-stats(*this)
+possibleStates(p->possible_states.begin(),
+ p->possible_states.end()),
+prvEvalTick(0), stats(*this)
{
}
@@ -68,6 +70,11 @@
void
PowerState::set(Enums::PwrState p)
{
+// Check if this power state is actually allowed by checking whether
it is
+// present in pwrStateToIndex-dictionary
+panic_if(possibleStates.find(p) == possibleStates.end(),
+ "Cannot go to %s in %s \n", Enums::PwrStateStrings[p],
name());
+
// Function should ideally be called only when there is a state change
if (_currState == p) {
warn_once("PowerState: Already in the requested power state, "
diff --git a/src/sim/power_state.hh b/src/sim/power_state.hh
index 8b93b45..4565c2b 100644
--- a/src/sim/power_state.hh
+++ b/src/sim/power_state.hh
@@ -98,11 +98,22 @@
*/
void computeStats();
+/**
+ * Return the power states this object can be in
+ */
+std::set getPossibleStates() const
+{
+return possibleStates;
+}
+
protected:
/** To keep track of the current power state */
Enums::PwrState _currState;
+/** The possible power states this object can be in */
+const std::set possibleStates;
+
/** Last tick the power stats were calculated */
Tick prvEvalTick = 0;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28050
To unsubscribe, or for help writing mail filters, visit
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ida414a87554a14f09767a272b54b5d19bfc8e911
Gerrit-Change-Number: 28050
Gerrit-PatchSet: 4
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Anouk Van Laer
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim-power: Fix the way the power model accesses stats
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27892 )
Change subject: sim-power: Fix the way the power model accesses stats
..
sim-power: Fix the way the power model accesses stats
With the introduction of StatGroups the organization of stats has
changed and the power modeling framework has been broken. This CL uses
the new function Stats::resolve to retrieve pointers to the necesary
stats and use them in the power estimation formulas.
Change-Id: Iedaa97eeddf51f7a0a1f222918715da309943be3
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27892
Maintainer: Jason Lowe-Power
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
---
M src/sim/power/mathexpr_powermodel.cc
M src/sim/power/mathexpr_powermodel.hh
2 files changed, 23 insertions(+), 81 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/power/mathexpr_powermodel.cc
b/src/sim/power/mathexpr_powermodel.cc
index 13af0fd..71131f5 100644
--- a/src/sim/power/mathexpr_powermodel.cc
+++ b/src/sim/power/mathexpr_powermodel.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017 ARM Limited
+ * Copyright (c) 2016-2017, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -46,75 +46,39 @@
#include "sim/sim_object.hh"
MathExprPowerModel::MathExprPowerModel(const Params *p)
-: PowerModelState(p), dyn_expr(p->dyn), st_expr(p->st), failed(false)
+: PowerModelState(p), dyn_expr(p->dyn), st_expr(p->st)
{
-// Calculate the name of the object we belong to
-std::vector path;
-tokenize(path, name(), '.', true);
-// It's something like xyz.power_model.pm2
-assert(path.size() > 2);
-for (unsigned i = 0; i < path.size() - 2; i++)
-basename += path[i] + ".";
}
void
MathExprPowerModel::startup()
{
-// Create a map with stats and pointers for quick access
-// Has to be done here, since we need access to the statsList
-for (auto & i: Stats::statsList()) {
-if (i->name.find(basename) == 0) {
-// Add stats for this sim object and its child objects
-stats_map[i->name.substr(basename.size())] = i;
-} else if (i->name.find(".") == std::string::npos) {
-// Add global stats (sim_seconds, for example)
-stats_map[i->name] = i;
+for (auto expr: {dyn_expr, st_expr}) {
+std::vector vars = expr.getVariables();
+
+for (auto var: vars) {
+// Automatic variables:
+if (var == "temp" || var == "voltage" || var
== "clock_period") {
+continue;
+}
+
+auto *info = Stats::resolve(var);
+fatal_if(!info, "Failed to evaluate %s in expression:\n%s\n",
+ var, expr.toStr());
+statsMap[var] = info;
}
}
-
-tryEval(st_expr);
-const bool st_failed = failed;
-
-tryEval(dyn_expr);
-const bool dyn_failed = failed;
-
-if (st_failed || dyn_failed) {
-const auto *p = dynamic_cast(params());
-assert(p);
-
-fatal("Failed to evaluate power expressions:\n%s%s%s\n",
- st_failed ? p->st : "",
- st_failed && dyn_failed ? "\n" : "",
- dyn_failed ? p->dyn : "");
-}
}
double
MathExprPowerModel::eval(const MathExpr ) const
{
-const double value = tryEval(expr);
-
-// This shouldn't happen unless something went wrong the equations
-// were verified in startup().
-panic_if(failed, "Failed to evaluate power expression '%s'\n",
- expr.toStr());
-
-return value;
-}
-
-double
-MathExprPowerModel::tryEval(const MathExpr ) const
-{
-failed = false;
-const double value = expr.eval(
+return expr.eval(
std::bind(::getStatValue,
this, std::placeholders::_1)
);
-
-return value;
}
-
double
MathExprPowerModel::getStatValue(const std::string ) const
{
@@ -127,18 +91,13 @@
return clocked_object->voltage();
} else if (name=="clock_period") {
return clocked_object->clockPeriod();
-}
-
-// Try to cast the stat, only these are supported right now
-const auto it = stats_map.find(name);
-if (it == stats_map.cend()) {
-warn("Failed to find stat '%s'\n", name);
-failed = true;
-return 0;
}
+const auto it = statsMap.find(name);
+assert(it != statsMap.cend());
const Info *info = it->second;
+// Try to cast the stat, only these are supported right now
auto si = dynamic_cast(info);
if (si)
return si->value();
diff --git a/src/sim/power/mathexpr_powermodel.hh
b/src/sim/power/mathexpr_powermodel.hh
index d8bd239..1edb800 100644
--- a/src/sim/power/mathexpr_powermodel.hh
+++
[gem5-dev] Change in gem5/gem5[develop]: base, python, sim: Add support for resoving a stat using its name
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27891 )
Change subject: base, python, sim: Add support for resoving a stat using
its name
..
base, python, sim: Add support for resoving a stat using its name
This CL adds resolve, a function in the Stats namespace that allows
access to a stat as specified by its name.
Change-Id: I4fa8bed394b4cb35d9c6cf5d8db062b8d6bb9ca5
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27891
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/base/statistics.cc
M src/base/statistics.hh
2 files changed, 15 insertions(+), 2 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/statistics.cc b/src/base/statistics.cc
index 036029b..e4315ba 100644
--- a/src/base/statistics.cc
+++ b/src/base/statistics.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited
+ * Copyright (c) 2019-2020 Arm Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -54,6 +54,7 @@
#include "base/str.hh"
#include "base/time.hh"
#include "base/trace.hh"
+#include "sim/root.hh"
using namespace std;
@@ -573,6 +574,17 @@
fatal("No registered Stats::reset handler");
}
+const Info *
+resolve(const std::string )
+{
+const auto = nameMap().find(name);
+if (it != nameMap().cend()) {
+return it->second;
+} else {
+return Root::root()->resolveStat(name);
+}
+}
+
void
registerDumpCallback(Callback *cb)
{
diff --git a/src/base/statistics.hh b/src/base/statistics.hh
index 24a0d06..8f665fe 100644
--- a/src/base/statistics.hh
+++ b/src/base/statistics.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited
+ * Copyright (c) 2019-2020 Arm Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -3349,6 +3349,7 @@
void reset();
void enable();
bool enabled();
+const Info* resolve(const std::string );
/**
* Register reset and dump handlers. These are the functions which
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I4fa8bed394b4cb35d9c6cf5d8db062b8d6bb9ca5
Gerrit-Change-Number: 27891
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Add support for resolving stats within groups by name
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27890 )
Change subject: base: Add support for resolving stats within groups by name
..
base: Add support for resolving stats within groups by name
This change adds a member function to the Group class that returns a
stat given its name. The function will go through all stats in the
group and its subgroups and will return the stat that matches the
name. For example, if g is the Group system.bigCluster.cpus then a
call to
p = g.resolveStat("ipc")
will return a pointer to the stat system.bigCluster.cpus.ipc.
Change-Id: I5af8401b38b41aee611728f6d1a595f99d22d9de
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27890
Reviewed-by: Bobby R. Bruce
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/base/stats/group.cc
M src/base/stats/group.hh
M src/python/pybind11/stats.cc
3 files changed, 51 insertions(+), 2 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/stats/group.cc b/src/base/stats/group.cc
index d054b7a..06eaa46 100644
--- a/src/base/stats/group.cc
+++ b/src/base/stats/group.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited
+ * Copyright (c) 2019, 2020 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -117,6 +117,38 @@
statGroups[name] = block;
}
+const Info *
+Group::resolveStat(std::string name) const
+{
+auto pos = name.find(".");
+if (pos == std::string::npos) {
+// look for the stat in this group
+for (auto : stats) {
+if (info->name == name) {
+return info;
+}
+}
+} else {
+// look for the stat in subgroups
+const std::string gname = name.substr(0, pos);
+for (auto : statGroups) {
+if (g.first == gname) {
+return g.second->resolveStat(name.substr(pos + 1));
+}
+}
+}
+
+// finally look for the stat in groups that have been merged
+for (auto : mergedStatGroups) {
+auto info = g->resolveStat(name);
+if (info) {
+return info;
+}
+}
+
+return nullptr;
+}
+
void
Group::mergeStatGroup(Group *block)
{
diff --git a/src/base/stats/group.hh b/src/base/stats/group.hh
index f54df5c..4fd9e79 100644
--- a/src/base/stats/group.hh
+++ b/src/base/stats/group.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited
+ * Copyright (c) 2019, 2020 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -157,6 +157,22 @@
*/
void addStatGroup(const char *name, Group *block);
+/**
+ * Resolve a stat by its name within this group.
+ *
+ * This method goes through the stats in this group and sub-groups
+ * and returns a pointer to the the stat that matches the provided
+ * name. The input name has to be relative to the name of this
+ * group. For example, if this group is the SimObject
+ * system.bigCluster.cpus and we want the stat
+ * system.bigCluster.cpus.ipc, the input param should be the
+ * string "ipc".
+ *
+ * @param name Name of the desired stat
+ * @return Pointer to the stat with the provided name
+ */
+const Info * resolveStat(std::string name) const;
+
private:
/**
* Merge the contents (stats & children) of a block to this block.
diff --git a/src/python/pybind11/stats.cc b/src/python/pybind11/stats.cc
index 32c3b8b..1149eba 100644
--- a/src/python/pybind11/stats.cc
+++ b/src/python/pybind11/stats.cc
@@ -128,5 +128,6 @@
.def("getStats", ::Group::getStats)
.def("getStatGroups", ::Group::getStatGroups)
.def("addStatGroup", ::Group::addStatGroup)
+.def("resolveStat", ::Group::resolveStat)
;
}
--
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Gerrit-Change-Id: I5af8401b38b41aee611728f6d1a595f99d22d9de
Gerrit-Change-Number: 27890
Gerrit-PatchSet: 2
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Add function that returns all variables in a MathExpr
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27889 )
Change subject: sim: Add function that returns all variables in a MathExpr
..
sim: Add function that returns all variables in a MathExpr
This changes adds support for retrieving all variables in a math
expression. The added function can be called in all valid expressions
and will return the variables in a vector of strings.
Change-Id: I086ba04aa1f798400c97a0b6bf982018a2457c64
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27889
Reviewed-by: Bobby R. Bruce
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/sim/mathexpr.cc
M src/sim/mathexpr.hh
2 files changed, 37 insertions(+), 4 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/mathexpr.cc b/src/sim/mathexpr.cc
index f80c535..0cbcd90 100644
--- a/src/sim/mathexpr.cc
+++ b/src/sim/mathexpr.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 ARM Limited
+ * Copyright (c) 2016, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -174,3 +174,17 @@
return ret;
}
+void
+MathExpr::getVariables(const Node *n,
+ std::vector ) const
+{
+if (!n || n->op == sValue || n->op == nInvalid) {
+return;
+} else if (n->op == sVariable) {
+variables.push_back(n->variable);
+} else {
+getVariables(n->l, variables);
+getVariables(n->r, variables);
+}
+}
+
diff --git a/src/sim/mathexpr.hh b/src/sim/mathexpr.hh
index b8db739..3dfe2b8 100644
--- a/src/sim/mathexpr.hh
+++ b/src/sim/mathexpr.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 ARM Limited
+ * Copyright (c) 2016, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -42,6 +42,7 @@
#include
#include
#include
+#include
class MathExpr {
public:
@@ -66,6 +67,22 @@
*/
double eval(EvalCallback fn) const { return eval(root, fn); }
+/**
+ * Return all variables in the this expression.
+ *
+ * This function starts from the root node and traverses all nodes
+ * while adding the variables it finds to a vector. Returns the
+ * found variables in a vector of strings
+ *
+ * @return A Vector with the names of all variables
+*/
+std::vector getVariables() const
+{
+std::vector vars;
+getVariables(root, vars);
+return vars;
+}
+
private:
enum Operator {
bAdd, bSub, bMul, bDiv, bPow, uNeg, sValue, sVariable, nInvalid
@@ -119,8 +136,10 @@
/** Eval a node */
double eval(const Node *n, EvalCallback fn) const;
+
+/** Return all variable reachable from a node to a vector of
+ * strings */
+void getVariables(const Node *n, std::vector ) const;
};
#endif
-
-
--
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Gerrit-Change-Id: I086ba04aa1f798400c97a0b6bf982018a2457c64
Gerrit-Change-Number: 27889
Gerrit-PatchSet: 2
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Inheritance fixes in varargs
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28250 )
Change subject: sim: Inheritance fixes in varargs
..
sim: Inheritance fixes in varargs
Change-Id: I3c6027223893363df098d1990a4ad3d07c2ff5ff
Signed-off-by: Nikos Nikoleris
---
M src/sim/guest_abi/varargs.hh
1 file changed, 4 insertions(+), 0 deletions(-)
diff --git a/src/sim/guest_abi/varargs.hh b/src/sim/guest_abi/varargs.hh
index 6a19db8..07ed2a1 100644
--- a/src/sim/guest_abi/varargs.hh
+++ b/src/sim/guest_abi/varargs.hh
@@ -70,6 +70,8 @@
class VarArgsBase : public VarArgsBase
{
public:
+virtual ~VarArgsBase() = default;
+
// The virtual function takes a reference parameter so that the
different
// _getImpl methods can co-exist through overloading.
virtual void _getImpl(First &) = 0;
@@ -126,6 +128,8 @@
// Declare state to pass to the Argument<>::get methods.
ThreadContext *tc;
typename ABI::State state;
+// Make sure base class _getImpl-es don't get hidden by ours.
+using Base::_getImpl;
// Give the "using" statement in our subclass something to refer to.
void _getImpl();
--
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Gerrit-Change-Id: I3c6027223893363df098d1990a4ad3d07c2ff5ff
Gerrit-Change-Number: 28250
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Gerrit-Owner: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Avoid const from member due to ::operator=(...)
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28249 )
Change subject: mem-ruby: Avoid const from member due to
::operator=(...)
..
mem-ruby: Avoid const from member due to ::operator=(...)
Change-Id: I172f48ce8ee4a3870165309342dadc2ac39ded9a
Signed-off-by: Nikos Nikoleris
---
M src/mem/ruby/slicc_interface/Message.hh
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mem/ruby/slicc_interface/Message.hh
b/src/mem/ruby/slicc_interface/Message.hh
index 0c2e0aa..1044fe0 100644
--- a/src/mem/ruby/slicc_interface/Message.hh
+++ b/src/mem/ruby/slicc_interface/Message.hh
@@ -104,7 +104,7 @@
void setVnet(int net) { vnet = net; }
private:
-const Tick m_time;
+Tick m_time;
Tick m_LastEnqueueTime; // my last enqueue time
Tick m_DelayedTicks; // my delayed cycles
uint64_t m_msg_counter; // FIXME, should this be a 64-bit value?
--
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Gerrit-Change-Id: I172f48ce8ee4a3870165309342dadc2ac39ded9a
Gerrit-Change-Number: 28249
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Remove unused SFINAE causing compilation errors
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28251 )
Change subject: arch-arm: Remove unused SFINAE causing compilation errors
..
arch-arm: Remove unused SFINAE causing compilation errors
clang on MacOS is unable to deduce the template parameters with the
following warning which is turned to an error due to -Werror
build/ARM/arch/arm/aapcs64.hh:90:8: error:
class template partial specialization contains template parameters
that cannot be deduced; this partial specialization will never be used
[-Wunusable-partial-specialization]
Change-Id: Id3cf820c636a5479e2ccd761817cc29a530fe5cc
Signed-off-by: Nikos Nikoleris
---
M src/arch/arm/aapcs64.hh
1 file changed, 0 insertions(+), 4 deletions(-)
diff --git a/src/arch/arm/aapcs64.hh b/src/arch/arm/aapcs64.hh
index 203846d..4dff86a 100644
--- a/src/arch/arm/aapcs64.hh
+++ b/src/arch/arm/aapcs64.hh
@@ -86,10 +86,6 @@
template
struct IsAapcs64ShortVector : public std::false_type {};
-template
-struct IsAapcs64ShortVector> : public
std::true_type
-{};
-
/*
* Composite Types
*/
--
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Gerrit-Change-Number: 28251
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix access modifier in Arm*ProcessBits class
Hello Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28248
to review the following change.
Change subject: arch-arm: Fix access modifier in Arm*ProcessBits class
..
arch-arm: Fix access modifier in Arm*ProcessBits class
Change-Id: Ie983abc94dd9e62bbec3f584b70b0d04d6e8305d
Reviewed-by: Giacomo Travaglini
Signed-off-by: Nikos Nikoleris
---
M src/arch/arm/freebsd/process.hh
M src/arch/arm/linux/process.hh
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/arch/arm/freebsd/process.hh
b/src/arch/arm/freebsd/process.hh
index ac0092e..d52512a 100644
--- a/src/arch/arm/freebsd/process.hh
+++ b/src/arch/arm/freebsd/process.hh
@@ -39,7 +39,7 @@
class ArmFreebsdProcessBits
{
- protected:
+ public:
struct SyscallABI {};
};
diff --git a/src/arch/arm/linux/process.hh b/src/arch/arm/linux/process.hh
index 0662d9f..0c15c28 100644
--- a/src/arch/arm/linux/process.hh
+++ b/src/arch/arm/linux/process.hh
@@ -1,5 +1,5 @@
/*
-* Copyright (c) 2011-2012 ARM Limited
+ * Copyright (c) 2011-2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -47,7 +47,7 @@
class ArmLinuxProcessBits
{
- protected:
+ public:
struct SyscallABI {};
};
--
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Gerrit-Reviewer: Giacomo Travaglini
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Remove alignment specified from alias declararions
Nikos Nikoleris has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/28252 ) Change subject: arch-arm: Remove alignment specified from alias declararions .. arch-arm: Remove alignment specified from alias declararions This causes a compilation error on MacOS and it's unclear whether it should be allowed in the first place. In addition, it doesn't seem to be used at the moment. https://stackoverflow.com/questions/15788947/where-can-i-use-alignas-in-c11 Change-Id: Icae4b21de62d69efe4937bdf9a51a473a5323acb Signed-off-by: Nikos Nikoleris --- M src/arch/arm/aapcs64.hh 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/arch/arm/aapcs64.hh b/src/arch/arm/aapcs64.hh index 4dff86a..d2e45a9 100644 --- a/src/arch/arm/aapcs64.hh +++ b/src/arch/arm/aapcs64.hh @@ -74,8 +74,7 @@ // appropriate alignment requirement. template -using Aapcs64ShortVectorCandidate = -alignas(sizeof(T) * count) uint8_t [sizeof(T) * count]; +using Aapcs64ShortVectorCandidate = uint8_t [sizeof(T) * count]; template using Aapcs64ShortVector = Aapcs64ShortVectorCandidatehttps://gem5-review.googlesource.com/c/public/gem5/+/28252 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Icae4b21de62d69efe4937bdf9a51a473a5323acb Gerrit-Change-Number: 28252 Gerrit-PatchSet: 1 Gerrit-Owner: Nikos Nikoleris Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix function signature inconsistencies in semihosting
Hello Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28170
to review the following change.
Change subject: arch-arm: Fix function signature inconsistencies in
semihosting
..
arch-arm: Fix function signature inconsistencies in semihosting
Change-Id: Icb1aa30cb67b676d49681f68e1d62b3af409e26b
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
---
M src/arch/arm/semihosting.cc
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 7718cd0..7711a86 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -305,7 +305,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callClose(ThreadContext *tc, uint64_t handle)
+ArmSemihosting::callClose(ThreadContext *tc, Handle handle)
{
if (handle > files.size()) {
DPRINTF(Semihosting, "Semihosting SYS_CLOSE(%i): Illegal file\n");
@@ -350,7 +350,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callWrite(ThreadContext *tc, uint64_t handle, Addr addr,
+ArmSemihosting::callWrite(ThreadContext *tc, Handle handle, Addr addr,
size_t size)
{
if (handle > files.size() || !files[handle])
@@ -371,7 +371,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callRead(ThreadContext *tc, uint64_t handle, Addr addr,
+ArmSemihosting::callRead(ThreadContext *tc, Handle handle, Addr addr,
size_t size)
{
if (handle > files.size() || !files[handle])
@@ -404,7 +404,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callIsTTY(ThreadContext *tc, uint64_t handle)
+ArmSemihosting::callIsTTY(ThreadContext *tc, Handle handle)
{
if (handle > files.size() || !files[handle])
return retError(EBADF);
@@ -418,7 +418,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callSeek(ThreadContext *tc, uint64_t handle, uint64_t pos)
+ArmSemihosting::callSeek(ThreadContext *tc, Handle handle, uint64_t pos)
{
if (handle > files.size() || !files[handle])
return retError(EBADF);
@@ -432,7 +432,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callFLen(ThreadContext *tc, uint64_t handle)
+ArmSemihosting::callFLen(ThreadContext *tc, Handle handle)
{
if (handle > files.size() || !files[handle])
return retError(EBADF);
--
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Gerrit-Change-Number: 28170
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Giacomo Travaglini
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm, mem-ruby, sim: Add missing overrides
Hello Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28168
to review the following change.
Change subject: arch-arm, mem-ruby, sim: Add missing overrides
..
arch-arm, mem-ruby, sim: Add missing overrides
Change-Id: I5ab18960bd61953e6846426adb657818f825
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
---
M src/arch/arm/isa.hh
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/Sequencer.hh
M src/sim/kernel_workload.hh
4 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 5fec2db..b4fbbbf 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -726,14 +726,14 @@
unsigned eCount);
void
-serialize(CheckpointOut ) const
+serialize(CheckpointOut ) const override
{
DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
}
void
-unserialize(CheckpointIn )
+unserialize(CheckpointIn ) override
{
DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
diff --git a/src/mem/ruby/system/GPUCoalescer.hh
b/src/mem/ruby/system/GPUCoalescer.hh
index 620b5ee..1321173 100644
--- a/src/mem/ruby/system/GPUCoalescer.hh
+++ b/src/mem/ruby/system/GPUCoalescer.hh
@@ -102,9 +102,9 @@
void wakeup(); // Used only for deadlock detection
void printProgress(std::ostream& out) const;
-void resetStats();
+void resetStats() override;
void collateStats();
-void regStats();
+void regStats() override;
void writeCallback(Addr address, DataBlock& data);
@@ -157,18 +157,18 @@
void recordCPWriteCallBack(MachineID myMachID, MachineID senderMachID);
// Alternate implementations in VIPER Coalescer
-virtual RequestStatus makeRequest(PacketPtr pkt);
+virtual RequestStatus makeRequest(PacketPtr pkt) override;
-int outstandingCount() const { return m_outstanding_count; }
+int outstandingCount() const override { return m_outstanding_count; }
bool
-isDeadlockEventScheduled() const
+isDeadlockEventScheduled() const override
{
return deadlockCheckEvent.scheduled();
}
void
-descheduleDeadlockEvent()
+descheduleDeadlockEvent() override
{
deschedule(deadlockCheckEvent);
}
diff --git a/src/mem/ruby/system/Sequencer.hh
b/src/mem/ruby/system/Sequencer.hh
index 0569478..bb2819b 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -86,9 +86,9 @@
// Public Methods
void wakeup(); // Used only for deadlock detection
-void resetStats();
+void resetStats() override;
void collateStats();
-void regStats();
+void regStats() override;
void writeCallback(Addr address,
DataBlock& data,
@@ -106,14 +106,14 @@
const Cycles forwardRequestTime = Cycles(0),
const Cycles firstResponseTime = Cycles(0));
-RequestStatus makeRequest(PacketPtr pkt);
+RequestStatus makeRequest(PacketPtr pkt) override;
bool empty() const;
-int outstandingCount() const { return m_outstanding_count; }
+int outstandingCount() const override { return m_outstanding_count; }
-bool isDeadlockEventScheduled() const
+bool isDeadlockEventScheduled() const override
{ return deadlockCheckEvent.scheduled(); }
-void descheduleDeadlockEvent()
+void descheduleDeadlockEvent() override
{ deschedule(deadlockCheckEvent); }
void print(std::ostream& out) const;
diff --git a/src/sim/kernel_workload.hh b/src/sim/kernel_workload.hh
index 972a539..b88051a 100644
--- a/src/sim/kernel_workload.hh
+++ b/src/sim/kernel_workload.hh
@@ -98,7 +98,7 @@
}
bool
-insertSymbol(Addr address, const std::string )
+insertSymbol(Addr address, const std::string ) override
{
return kernelSymtab->insert(address, symbol);
}
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I5ab18960bd61953e6846426adb657818f825
Gerrit-Change-Number: 28168
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim: Fix mismatch between #ifndef and #define in varargs.hh
Hello Giacomo Travaglini, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/28169 to review the following change. Change subject: sim: Fix mismatch between #ifndef and #define in varargs.hh .. sim: Fix mismatch between #ifndef and #define in varargs.hh Change-Id: I558b6c3c69a5003a77cc95b414e620715c3dbbae Signed-off-by: Nikos Nikoleris Reviewed-by: Giacomo Travaglini --- M src/sim/guest_abi/varargs.hh 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/sim/guest_abi/varargs.hh b/src/sim/guest_abi/varargs.hh index 41e3c62..6a19db8 100644 --- a/src/sim/guest_abi/varargs.hh +++ b/src/sim/guest_abi/varargs.hh @@ -26,7 +26,7 @@ */ #ifndef __SIM_GUEST_ABI_VARARGS_HH__ -#define __SIM_GUEST_ABI_VARRAGS_HH__ +#define __SIM_GUEST_ABI_VARARGS_HH__ #include #include -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28169 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I558b6c3c69a5003a77cc95b414e620715c3dbbae Gerrit-Change-Number: 28169 Gerrit-PatchSet: 1 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix inconsistency in variable name
Hello Giacomo Travaglini, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/28172 to review the following change. Change subject: arch-arm: Fix inconsistency in variable name .. arch-arm: Fix inconsistency in variable name Change-Id: I091a2d0cc8bfa7b8d98c4f508d175868d0fd7249 Signed-off-by: Nikos Nikoleris Reviewed-by: Giacomo Travaglini --- M src/arch/arm/freebsd/process.cc 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/arm/freebsd/process.cc b/src/arch/arm/freebsd/process.cc index 3955f85..d8a7d68 100644 --- a/src/arch/arm/freebsd/process.cc +++ b/src/arch/arm/freebsd/process.cc @@ -118,7 +118,7 @@ void *holdp = (void *)buf2.bufferPtr(); size_t *holdlenp = (size_t *)buf3.bufferPtr(); -ret = sysctl((int *)hnamep, namelen, holdp, holdlenp, hnewp, newlen); +ret = sysctl((int *)hnamep, nameLen, holdp, holdlenp, hnewp, newlen); buf.copyOut(tc->getVirtProxy()); buf2.copyOut(tc->getVirtProxy()); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28172 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I091a2d0cc8bfa7b8d98c4f508d175868d0fd7249 Gerrit-Change-Number: 28172 Gerrit-PatchSet: 1 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Removed the unused parameter m_id from VirtualChannel
Hello Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28171
to review the following change.
Change subject: mem-ruby: Removed the unused parameter m_id from
VirtualChannel
..
mem-ruby: Removed the unused parameter m_id from VirtualChannel
Change-Id: Ie6f8db9b1cb0d0e0ca694c631c6662413fd833c1
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
---
M src/mem/ruby/network/garnet2.0/InputUnit.cc
M src/mem/ruby/network/garnet2.0/VirtualChannel.cc
M src/mem/ruby/network/garnet2.0/VirtualChannel.hh
3 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/src/mem/ruby/network/garnet2.0/InputUnit.cc
b/src/mem/ruby/network/garnet2.0/InputUnit.cc
index 8fdce06..640e3b4 100644
--- a/src/mem/ruby/network/garnet2.0/InputUnit.cc
+++ b/src/mem/ruby/network/garnet2.0/InputUnit.cc
@@ -52,7 +52,7 @@
// Instantiating the virtual channels
virtualChannels.reserve(m_num_vcs);
for (int i=0; i < m_num_vcs; i++) {
-virtualChannels.emplace_back(i);
+virtualChannels.emplace_back();
}
}
diff --git a/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
b/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
index 3b077d4..a469a84 100644
--- a/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
+++ b/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
@@ -31,8 +31,8 @@
#include "mem/ruby/network/garnet2.0/VirtualChannel.hh"
-VirtualChannel::VirtualChannel(int id)
- : m_id(id), inputBuffer(), m_vc_state(IDLE_, Cycles(0)),
m_output_port(-1),
+VirtualChannel::VirtualChannel()
+ : inputBuffer(), m_vc_state(IDLE_, Cycles(0)), m_output_port(-1),
m_enqueue_time(INFINITE_), m_output_vc(-1)
{
}
diff --git a/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
b/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
index 52963c8..752dfb4 100644
--- a/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
+++ b/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
@@ -40,7 +40,7 @@
class VirtualChannel
{
public:
-VirtualChannel(int id);
+VirtualChannel();
~VirtualChannel() = default;
bool need_stage(flit_stage stage, Cycles time);
@@ -89,7 +89,6 @@
uint32_t functionalWrite(Packet *pkt);
private:
-int m_id;
flitBuffer inputBuffer;
std::pair m_vc_state;
int m_output_port;
--
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Gerrit-Change-Number: 28171
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[gem5-dev] Change in gem5/gem5[develop]: scons: Disable unsupported -Wl,--as-needed in MacOS
Hello Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28173
to review the following change.
Change subject: scons: Disable unsupported -Wl,--as-needed in MacOS
..
scons: Disable unsupported -Wl,--as-needed in MacOS
Change-Id: Id6f8199b818217c4fcf4b80efdb7cc9e1d14e32b
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
---
M SConstruct
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/SConstruct b/SConstruct
index 215c0b6..3345148 100755
--- a/SConstruct
+++ b/SConstruct
@@ -359,7 +359,10 @@
main.Append(CCFLAGS=['-I/usr/local/include'])
main.Append(CXXFLAGS=['-I/usr/local/include'])
-main.Append(LINKFLAGS='-Wl,--as-needed')
+# On Mac OS X/Darwin the default linker doesn't support the
+# option --as-needed
+if sys.platform != "darwin":
+main.Append(LINKFLAGS='-Wl,--as-needed')
main['FILTER_PSHLINKFLAGS'] = lambda x: str(x).replace(' -shared', '')
main['PSHLINKFLAGS'] =
main.subst('${FILTER_PSHLINKFLAGS(SHLINKFLAGS)}')
if GetOption('gold_linker'):
--
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Gerrit-Change-Id: Id6f8199b818217c4fcf4b80efdb7cc9e1d14e32b
Gerrit-Change-Number: 28173
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Giacomo Travaglini
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Make variable const to allow derived constexpr
Hello Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28167
to review the following change.
Change subject: arch-arm: Make variable const to allow derived constexpr
..
arch-arm: Make variable const to allow derived constexpr
Change-Id: Idf5ae62603b6181d44aaaef91b774fa7b26eb718
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
---
M src/arch/arm/aapcs32.hh
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/arch/arm/aapcs32.hh b/src/arch/arm/aapcs32.hh
index fd63483..269c83f 100644
--- a/src/arch/arm/aapcs32.hh
+++ b/src/arch/arm/aapcs32.hh
@@ -558,7 +558,7 @@
if (useBaseABI(state))
return getArgument(tc, state);
-int base = state.allocate(Elem{}, Count);
+const int base = state.allocate(Elem{}, Count);
if (base >= 0) {
constexpr int lane_per_reg = 16 / sizeof(Elem);
HA ha;
--
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Gerrit-Change-Number: 28167
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[gem5-dev] Change in gem5/gem5[develop]: sim-power: Creation of PowerState class
Hello Andreas Sandberg, Anouk Van Laer,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28049
to review the following change.
Change subject: sim-power: Creation of PowerState class
..
sim-power: Creation of PowerState class
This commit does not make any functional changes but just rearranges
the existing code with regard to the power states. Previously, all
code regarding power states was in the ClockedObjects. However, it
seems more logical and cleaner to move this code into a separate
class, called PowerState. The PowerState is a now SimObject. Every
ClockedObject has a PowerState but this patch also allows for objects
with PowerState which are not ClockedObjects.
Change-Id: Id2db86dc14f140dc9d0912a8a7de237b9df9120d
Reviewed-by: Andreas Sandberg
Reviewed-by: Sascha Bischoff
Signed-off-by: Nikos Nikoleris
---
M configs/example/arm/fs_power.py
M src/cpu/base.cc
M src/dev/arm/fvp_base_pwr_ctrl.cc
M src/sim/ClockedObject.py
A src/sim/PowerState.py
M src/sim/SConscript
M src/sim/clocked_object.cc
M src/sim/clocked_object.hh
M src/sim/power/power_model.cc
A src/sim/power_state.cc
A src/sim/power_state.hh
11 files changed, 432 insertions(+), 231 deletions(-)
diff --git a/configs/example/arm/fs_power.py
b/configs/example/arm/fs_power.py
index abc759e..72c6292 100644
--- a/configs/example/arm/fs_power.py
+++ b/configs/example/arm/fs_power.py
@@ -114,7 +114,7 @@
if not isinstance(cpu, m5.objects.BaseCPU):
continue
-cpu.default_p_state = "ON"
+cpu.power_state.default_state = "ON"
cpu.power_model = CpuPowerModel(cpu.path())
# Example power model for the L2 Cache of the bigCluster
@@ -122,7 +122,7 @@
if not isinstance(l2, m5.objects.Cache):
continue
-l2.default_p_state = "ON"
+l2.power_state.default_state = "ON"
l2.power_model = L2PowerModel(l2.path())
bL.instantiate(options)
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index c0788db..493f08b 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -329,11 +329,11 @@
}
if (_switchedOut)
-ClockedObject::pwrState(Enums::PwrState::OFF);
+powerState->set(Enums::PwrState::OFF);
// Assumption CPU start to operate instantaneously without any latency
-if (ClockedObject::pwrState() == Enums::PwrState::UNDEFINED)
-ClockedObject::pwrState(Enums::PwrState::ON);
+if (powerState->get() == Enums::PwrState::UNDEFINED)
+powerState->set(Enums::PwrState::ON);
}
@@ -463,7 +463,7 @@
return;
}
-if (ClockedObject::pwrState() == Enums::PwrState::CLK_GATED &&
+if (powerState->get() == Enums::PwrState::CLK_GATED &&
powerGatingOnIdle) {
assert(!enterPwrGatingEvent.scheduled());
// Schedule a power gating event when clock gated for the specified
@@ -492,7 +492,7 @@
if (enterPwrGatingEvent.scheduled())
deschedule(enterPwrGatingEvent);
// For any active thread running, update CPU power state to active (ON)
-ClockedObject::pwrState(Enums::PwrState::ON);
+powerState->set(Enums::PwrState::ON);
updateCycleCounters(CPU_STATE_WAKEUP);
}
@@ -513,7 +513,7 @@
updateCycleCounters(CPU_STATE_SLEEP);
// All CPU threads suspended, enter lower power state for the CPU
-ClockedObject::pwrState(Enums::PwrState::CLK_GATED);
+powerState->set(Enums::PwrState::CLK_GATED);
// If pwrGatingLatency is set to 0 then this mechanism is disabled
if (powerGatingOnIdle) {
@@ -532,7 +532,7 @@
void
BaseCPU::enterPwrGating(void)
{
-ClockedObject::pwrState(Enums::PwrState::OFF);
+powerState->set(Enums::PwrState::OFF);
}
void
@@ -548,7 +548,7 @@
flushTLBs();
// Go to the power gating state
-ClockedObject::pwrState(Enums::PwrState::OFF);
+powerState->set(Enums::PwrState::OFF);
}
void
@@ -561,7 +561,7 @@
_pid = oldCPU->getPid();
_taskId = oldCPU->taskId();
// Take over the power state of the switchedOut CPU
-ClockedObject::pwrState(oldCPU->pwrState());
+powerState->set(oldCPU->powerState->get());
previousState = oldCPU->previousState;
previousCycle = oldCPU->previousCycle;
diff --git a/src/dev/arm/fvp_base_pwr_ctrl.cc
b/src/dev/arm/fvp_base_pwr_ctrl.cc
index a6650b8..5113c92 100644
--- a/src/dev/arm/fvp_base_pwr_ctrl.cc
+++ b/src/dev/arm/fvp_base_pwr_ctrl.cc
@@ -280,7 +280,7 @@
npwrs->pc = 0;
}
}
-tc->getCpuPtr()->pwrState(Enums::PwrState::ON);
+tc->getCpuPtr()->powerState->set(Enums::PwrState::ON);
}
void
@@ -295,7 +295,7 @@
pwrs->pc = 0;
// Clear power-on reason
pwrs->wk = 0;
-tc->getCpuPtr()->pwrState(Enums::PwrState::OFF);
+tc->getCpuPtr()->powerState->set(Enums::PwrState::OFF);
}
void
diff --git a/src/sim/ClockedObject.py b/src/sim/ClockedObject.py
index 3819093..8732613
[gem5-dev] Change in gem5/gem5[develop]: sim-power: Specify the states a PowerState object can be in
Hello Andreas Sandberg, Anouk Van Laer,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28050
to review the following change.
Change subject: sim-power: Specify the states a PowerState object can be in
..
sim-power: Specify the states a PowerState object can be in
This commit adds the concept of possible power states to the
PowerState SimObject. This is a list of the power states a specific
object can be in. Before transitioning to a power state, a PowerState
object will first check if the requested power states is actually an
allowed state. The user can restricted the power states a
ClockedObject can go to during configuration. In addition, this change
sets the power states, a CPU can be in.
Change-Id: Ida414a87554a14f09767a272b54b5d19bfc8e911
Reviewed-by: Andreas Sandberg
Signed-off-by: Nikos Nikoleris
---
M src/cpu/BaseCPU.py
M src/sim/PowerState.py
M src/sim/power_state.cc
M src/sim/power_state.hh
4 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 53652bf..feb0eed 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -302,3 +302,7 @@
cpus_node.append(node)
yield cpus_node
+
+def __init__(self, **kwargs):
+super(BaseCPU, self).__init__(**kwargs)
+self.power_state.possible_states=['ON', 'CLK_GATED', 'OFF']
diff --git a/src/sim/PowerState.py b/src/sim/PowerState.py
index 59491ec..bfa53e2 100644
--- a/src/sim/PowerState.py
+++ b/src/sim/PowerState.py
@@ -62,6 +62,11 @@
# routine
default_state = Param.PwrState("UNDEFINED", "Default Power State")
+# Possible power states this object can be in sorted from the most
+# to the least performant
+possible_states = VectorParam.PwrState(
+[], "Power states this object can be in")
+
clk_gate_min = Param.Latency('1ns',"Min value of the distribution")
clk_gate_max = Param.Latency('1s',"Max value of the distribution")
clk_gate_bins = Param.Unsigned('20', "# bins in clk gated
distribution")
diff --git a/src/sim/power_state.cc b/src/sim/power_state.cc
index 7074dd6..a2ed7fe 100644
--- a/src/sim/power_state.cc
+++ b/src/sim/power_state.cc
@@ -40,8 +40,10 @@
#include "base/logging.hh"
PowerState::PowerState(const PowerStateParams *p) :
-SimObject(p), _currState(p->default_state), prvEvalTick(0),
-stats(*this)
+SimObject(p), _currState(p->default_state),
+possibleStates(p->possible_states.begin(),
+ p->possible_states.end()),
+prvEvalTick(0), stats(*this)
{
}
@@ -68,6 +70,11 @@
void
PowerState::set(Enums::PwrState p)
{
+// Check if this power state is actually allowed by checking whether
it is
+// present in pwrStateToIndex-dictionary
+panic_if(possibleStates.find(p) == possibleStates.end(),
+ "Cannot go to %s in %s \n", Enums::PwrStateStrings[p],
name());
+
// Function should ideally be called only when there is a state change
if (_currState == p) {
warn_once("PowerState: Already in the requested power state, "
diff --git a/src/sim/power_state.hh b/src/sim/power_state.hh
index 8cb3b3b..af7527f 100644
--- a/src/sim/power_state.hh
+++ b/src/sim/power_state.hh
@@ -98,11 +98,22 @@
*/
void computeStats();
+/**
+ * Return the power states this object can be in
+ */
+std::set getPossibleStates() const
+{
+return possibleStates;
+}
+
protected:
/** To keep track of the current power state */
Enums::PwrState _currState;
+/** The possible power states this object can be in */
+const std::set possibleStates;
+
/** Last tick the power stats were calculated */
Tick prvEvalTick;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28050
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ida414a87554a14f09767a272b54b5d19bfc8e911
Gerrit-Change-Number: 28050
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Anouk Van Laer
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim-power: Addition of PowerDomains
Hello Andreas Sandberg, Anouk Van Laer, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/28051 to review the following change. Change subject: sim-power: Addition of PowerDomains .. sim-power: Addition of PowerDomains PowerDomains group multiple objects together to regulate their power state. There are 2 types of objects in a PowerDomain: leaders and followers. The power state of a PowerDomain is the most performant power state of any of the leaders. The power state of the followers is determined by the power state of the PowerDomain they belong to: they need to be in a power state which is more or equally performant to the power state of the PowerDomain. Leaders can be ClockedObjects or other PowerDomains. Followers can only be ClockedObjects. PowerDomains can be be nested but a PowerDomain can only be a leader of another PowerDomain, NOT a follower. PowerDomains are not present in the hierarchy by default, the user needs to create and configure them in the configuration file. The user can add an hierachy by setting the led_by parameter. gem5 will then create leaders and followers for each domain and calculate the allowed power states for the domain. Objects in a PowerDomain need to have at least the ON state in the possible_states. An example of a powerDomain config is: pd = PowerDomain() cpu0 = BaseCPU() cpu1 = BaseCPU() shared_cache = BaseCache() cache.power_state.led_by = pd pd.led_by = [cpu0, cpu1] This will create a PowerDomain, where the CPUs determine their own power states and the shared cache (via the PowerDomain) follows those power states (when possible). Change-Id: I4c4cd01f06d45476c6e0fb2afeb778613733e2ff Reviewed-by: Andreas Sandberg Reviewed-by: Sascha Bischoff Signed-off-by: Nikos Nikoleris --- A src/sim/PowerDomain.py M src/sim/PowerState.py M src/sim/SConscript A src/sim/power_domain.cc A src/sim/power_domain.hh M src/sim/power_state.cc M src/sim/power_state.hh 7 files changed, 585 insertions(+), 2 deletions(-) diff --git a/src/sim/PowerDomain.py b/src/sim/PowerDomain.py new file mode 100644 index 000..9d45252 --- /dev/null +++ b/src/sim/PowerDomain.py @@ -0,0 +1,49 @@ +# Copyright (c) 2017, 2019-2020 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +import sys + +from m5.params import * +from m5.objects.PowerState import PowerState + +# A power domain groups multiple ClockedObjects and creates a +# hierarchy in which follower ClockedObjects (caches for example) can +# change power state depeding on what the leader objects (CPUs for +# example) do. The power domain is the link between these. +class PowerDomain(PowerState): +type = 'PowerDomain' +cxx_header = 'sim/power_domain.hh' + diff --git a/src/sim/PowerState.py b/src/sim/PowerState.py index bfa53e2..30f62e0 100644 --- a/src/sim/PowerState.py +++ b/src/sim/PowerState.py @@ -70,3
