from:"Yu\-hsin Wang \(Gerrit\) via gem5\-dev"

[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Update default environment comments

2023-07-07 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/72058?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: scons: Update default environment comments
..

scons: Update default environment comments

Change-Id: Ib6dcf1a6390010682365f393241c1e022aeeb813
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/72058
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M site_scons/gem5_scons/defaults.py
1 file changed, 10 insertions(+), 10 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/site_scons/gem5_scons/defaults.py  
b/site_scons/gem5_scons/defaults.py

index 944f7e5..aeca94f 100644
--- a/site_scons/gem5_scons/defaults.py
+++ b/site_scons/gem5_scons/defaults.py
@@ -44,7 +44,7 @@


 def EnvDefaults(env):
-# export TERM so that clang reports errors in color
+# initialize the toolchain related env with host environment
 use_vars = set(
 [
 "AS",
@@ -60,15 +60,15 @@
 "PROTOC",
 "PYTHONPATH",
 "RANLIB",
-"TERM",
-"PYTHON_CONFIG",
-"CCFLAGS_EXTRA",
-"GEM5PY_CCFLAGS_EXTRA",
-"GEM5PY_LINKFLAGS_EXTRA",
-"LINKFLAGS_EXTRA",
-"LANG",
-"LC_CTYPE",
-"DISPLAY",
+"TERM",  # for clang reports errors in color
+"PYTHON_CONFIG",  # gem5 specific build env
+"CCFLAGS_EXTRA",  # gem5 specific build env
+"GEM5PY_CCFLAGS_EXTRA",  # gem5 specific build env
+"GEM5PY_LINKFLAGS_EXTRA",  # gem5 specific build env
+"LINKFLAGS_EXTRA",  # gem5 specific build env
+"LANG",  # for work with non-ascii directory path
+"LC_CTYPE",  # for work with non-ascii directory path
+"DISPLAY",  # for gui program, ex kconfig guiconfig
 ]
 )


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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib6dcf1a6390010682365f393241c1e022aeeb813
Gerrit-Change-Number: 72058
Gerrit-PatchSet: 3
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: kokoro 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: scons: Add -rdynamic when building python embed binary

2023-07-05 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/72040?usp=email )


 (

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: scons: Add -rdynamic when building python embed binary
..

scons: Add -rdynamic when building python embed binary

When you build Python from scratch, the modules would be separated
shared libraries. They would be dlopen when doing module import. To make
the separated shared libraries can share the symbol in the binary, we
should add -rdynamic when compliing.

Change-Id: I26bf9fd7ea5068fd2d08c8f059b37ff34073e8c2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/72040
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/SConscript
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved




diff --git a/src/SConscript b/src/SConscript
index 1b44303..f54a881 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -626,6 +626,7 @@
 gem5py_m5_env = gem5py_env.Clone()
 gem5py_env.Append(CPPPATH=env['CPPPATH'])
 gem5py_env.Append(LIBS='z')
+gem5py_env.Append(LINKFLAGS='-rdynamic')
 gem5py_env.Program(gem5py, 'python/gem5py.cc')[0]
 m5_module_source = \
 Source.all.with_all_tags(env, 'm5_module', 'gem5 lib')
@@ -647,6 +648,7 @@
 #

 env['SHOBJSUFFIX'] = '${OBJSUFFIX}s'
+env.Append(LINKFLAGS='-rdynamic')

 envs = {
 'debug': env.Clone(ENV_LABEL='debug', OBJSUFFIX='.do'),

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Gerrit-MessageType: merged
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Gerrit-Change-Id: I26bf9fd7ea5068fd2d08c8f059b37ff34073e8c2
Gerrit-Change-Number: 72040
Gerrit-PatchSet: 4
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
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Gerrit-CC: Roger Chang 
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[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Update default environment comments

2023-07-05 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/72058?usp=email )



Change subject: scons: Update default environment comments
..

scons: Update default environment comments

Change-Id: Ib6dcf1a6390010682365f393241c1e022aeeb813
---
M site_scons/gem5_scons/defaults.py
1 file changed, 10 insertions(+), 10 deletions(-)



diff --git a/site_scons/gem5_scons/defaults.py  
b/site_scons/gem5_scons/defaults.py

index 944f7e5..aeca94f 100644
--- a/site_scons/gem5_scons/defaults.py
+++ b/site_scons/gem5_scons/defaults.py
@@ -44,7 +44,7 @@


 def EnvDefaults(env):
-# export TERM so that clang reports errors in color
+# initialize the toolchain related env with host environment
 use_vars = set(
 [
 "AS",
@@ -60,15 +60,15 @@
 "PROTOC",
 "PYTHONPATH",
 "RANLIB",
-"TERM",
-"PYTHON_CONFIG",
-"CCFLAGS_EXTRA",
-"GEM5PY_CCFLAGS_EXTRA",
-"GEM5PY_LINKFLAGS_EXTRA",
-"LINKFLAGS_EXTRA",
-"LANG",
-"LC_CTYPE",
-"DISPLAY",
+"TERM",  # for clang reports errors in color
+"PYTHON_CONFIG",  # gem5 specific build env
+"CCFLAGS_EXTRA",  # gem5 specific build env
+"GEM5PY_CCFLAGS_EXTRA",  # gem5 specific build env
+"GEM5PY_LINKFLAGS_EXTRA",  # gem5 specific build env
+"LINKFLAGS_EXTRA",  # gem5 specific build env
+"LANG",  # for work with non-ascii directory path
+"LC_CTYPE",  # for work with non-ascii directory path
+"DISPLAY",  # for gui program, ex kconfig guiconfig
 ]
 )


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[gem5-dev] [XS] Change in gem5/gem5[develop]: scons: Pass the CPATH environment variable through to SCons.

2023-07-05 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/72038?usp=email )


Change subject: scons: Pass the CPATH environment variable through to SCons.
..

scons: Pass the CPATH environment variable through to SCons.

For sandbox environment, the default include may be override by CPATH.
To make the SCons can work in this environment, we need to pass CPATH
into SCons.

Change-Id: I1015f20a553a2e18595c8d2a89b209ca665879fd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/72038
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M site_scons/gem5_scons/defaults.py
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/site_scons/gem5_scons/defaults.py  
b/site_scons/gem5_scons/defaults.py

index f800b67..944f7e5 100644
--- a/site_scons/gem5_scons/defaults.py
+++ b/site_scons/gem5_scons/defaults.py
@@ -52,6 +52,7 @@
 "CC",
 "CXX",
 "HOME",
+"CPATH",
 "LD_LIBRARY_PATH",
 "LIBRARY_PATH",
 "PATH",

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Gerrit-Change-Number: 72038
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Yu-hsin Wang 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: scons: Add -rdynamic when building gem5py

2023-07-05 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/72040?usp=email )



Change subject: scons: Add -rdynamic when building gem5py
..

scons: Add -rdynamic when building gem5py

When you build Python from scratch, the modules would be separated
shared libraries. They would be dlopen when doing module import. To make
the separated shared libraries can share the symbol in gem5py binary, we
should add -rdynamic when compliing.

Change-Id: I26bf9fd7ea5068fd2d08c8f059b37ff34073e8c2
---
M src/SConscript
1 file changed, 1 insertion(+), 0 deletions(-)



diff --git a/src/SConscript b/src/SConscript
index 1b44303..55e87c1 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -626,6 +626,7 @@
 gem5py_m5_env = gem5py_env.Clone()
 gem5py_env.Append(CPPPATH=env['CPPPATH'])
 gem5py_env.Append(LIBS='z')
+gem5py_env.Append(LINKFLAGS='-rdynamic')
 gem5py_env.Program(gem5py, 'python/gem5py.cc')[0]
 m5_module_source = \
 Source.all.with_all_tags(env, 'm5_module', 'gem5 lib')

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[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Use pkgconfig to get correct Protobuf dependency

2023-07-04 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/72039?usp=email )



Change subject: scons: Use pkgconfig to get correct Protobuf dependency
..

scons: Use pkgconfig to get correct Protobuf dependency

Latest protobuf library depends on abseil libraries. We should rely on
pkgconfig to give us correct dependency. We still keep the old check as
fallback.

Change-Id: I529ea1f61e5bbc16b2520ab1badff3d8264f1c33
---
M src/proto/SConsopts
1 file changed, 4 insertions(+), 10 deletions(-)



diff --git a/src/proto/SConsopts b/src/proto/SConsopts
index 6b5b25d..fab29bc 100644
--- a/src/proto/SConsopts
+++ b/src/proto/SConsopts
@@ -50,14 +50,6 @@
 warning('protoc version', min_protoc_version, 'or newer  
required.\n'

 'Installed version:', protoc_version[1])
 else:
-# Attempt to determine the appropriate include path and
-# library path using pkg-config, that means we also need to
-# check for pkg-config. Note that it is possible to use
-# protobuf without the involvement of pkg-config. Later on we
-# check go a library config check and at that point the test
-# will fail if libprotobuf cannot be found.
-if conf.env['HAVE_PKG_CONFIG']:
-conf.CheckPkgConfig('protobuf', '--cflags', '--libs-only-L')
 conf.env['HAVE_PROTOC'] = True

 # If we have the protobuf compiler, also make sure we have the
@@ -65,9 +57,11 @@
 # automatically added to the LIBS environment variable. After
 # this, we can use the HAVE_PROTOBUF flag to determine if we have
 # got both protoc and libprotobuf available.
-conf.env['CONF']['HAVE_PROTOBUF'] = conf.env['HAVE_PROTOC'] and \
+conf.env['CONF']['HAVE_PROTOBUF'] = conf.env['HAVE_PROTOC'] and (
+(conf.env['HAVE_PKG_CONFIG'] and
+ conf.CheckPkgConfig('protobuf', '--cflags', '--libs')) or
 conf.CheckLibWithHeader('protobuf', 'google/protobuf/message.h',
-'C++', 'GOOGLE_PROTOBUF_VERIFY_VERSION;')
+'C++', 'GOOGLE_PROTOBUF_VERIFY_VERSION;'))

 # If we have the compiler but not the library, print another warning.
 if main['HAVE_PROTOC'] and not main['CONF']['HAVE_PROTOBUF']:

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[gem5-dev] [XS] Change in gem5/gem5[develop]: scons: Pass the CPATH environment variable through to SCons.

2023-07-04 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/72038?usp=email )



Change subject: scons: Pass the CPATH environment variable through to SCons.
..

scons: Pass the CPATH environment variable through to SCons.

For sandbox environment, the default include may be override by CPATH.
To make the SCons can work in this environment, we need to pass CPATH
into SCons.

Change-Id: I1015f20a553a2e18595c8d2a89b209ca665879fd
---
M site_scons/gem5_scons/defaults.py
1 file changed, 1 insertion(+), 0 deletions(-)



diff --git a/site_scons/gem5_scons/defaults.py  
b/site_scons/gem5_scons/defaults.py

index f800b67..944f7e5 100644
--- a/site_scons/gem5_scons/defaults.py
+++ b/site_scons/gem5_scons/defaults.py
@@ -52,6 +52,7 @@
 "CC",
 "CXX",
 "HOME",
+"CPATH",
 "LD_LIBRARY_PATH",
 "LIBRARY_PATH",
 "PATH",

--
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch: set multiline re as default in isa_parser

2023-06-15 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71019?usp=email )


Change subject: arch: set multiline re as default in isa_parser
..

arch: set multiline re as default in isa_parser

In python3.11, it requires the global specifier should be the first
token of regex. However it's not possible when using ply library.
Instead, we set the rules are multiline regex by default and modifies
those single line rules.

Ref: https://github.com/dabeaz/ply/issues/282

Change-Id: I7bdbfeb97a9dd74f45c1890a76f8cc16100e5a42
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71019
Reviewed-by: Richard Cooper 
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/isa_parser/isa_parser.py
1 file changed, 6 insertions(+), 5 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass
  Richard Cooper: Looks good to me, but someone else must approve




diff --git a/src/arch/isa_parser/isa_parser.py  
b/src/arch/isa_parser/isa_parser.py

index 0f29840..5be50a1 100755
--- a/src/arch/isa_parser/isa_parser.py
+++ b/src/arch/isa_parser/isa_parser.py
@@ -514,6 +514,7 @@
 class ISAParser(Grammar):
 def __init__(self, output_dir):
 super().__init__()
+self.lex_kwargs["reflags"] = int(re.MULTILINE)
 self.output_dir = output_dir

 self.filename = None  # for output file watermarking/scaremongering
@@ -851,7 +852,7 @@
 # String literal.  Note that these use only single quotes, and
 # can span multiple lines.
 def t_STRLIT(self, t):
-r"(?m)'([^'])+'"
+r"'([^'])+'"
 # strip off quotes
 t.value = t.value[1:-1]
 t.lexer.lineno += t.value.count("\n")
@@ -860,19 +861,19 @@
 # "Code literal"... like a string literal, but delimiters are
 # '{{' and '}}' so they get formatted nicely under emacs c-mode
 def t_CODELIT(self, t):
-r"(?m)\{\{([^\}]|}(?!\}))+\}\}"
+r"\{\{([^\}]|}(?!\}))+\}\}"
 # strip off {{ & }}
 t.value = t.value[2:-2]
 t.lexer.lineno += t.value.count("\n")
 return t

 def t_CPPDIRECTIVE(self, t):
-r"^\#[^\#].*\n"
+r"^\#[^\#][^\n]*\n"
 t.lexer.lineno += t.value.count("\n")
 return t

 def t_NEWFILE(self, t):
-r'^\#\#newfile\s+"[^"]*"\n'
+r'^\#\#newfile\s+"[^"\n]*"\n'
 self.fileNameStack.push(t.lexer.lineno)
 t.lexer.lineno = LineTracker(t.value[11:-2])

@@ -892,7 +893,7 @@

 # Comments
 def t_comment(self, t):
-r"//.*"
+r"//[^\n]*\n"

 # Completely ignored characters
 t_ignore = " \t\x0c"

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Gerrit-Change-Number: 71019
Gerrit-PatchSet: 3
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: fastmodel: only support single line literal when paring project file

2023-06-15 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71018?usp=email )


Change subject: fastmodel: only support single line literal when paring  
project file

..

fastmodel: only support single line literal when paring project file

In python3.11, it requires the global specifier should be the first
token of regex. However it's not possible when using ply library. In
fastmodel case, we actually don't need to support multiline string
literal. We fix this issue by just making the string literal single
line.

Ref: https://github.com/dabeaz/ply/issues/282

Change-Id: I746b628db7ad4c1d7834f1a1b2c1243cef68aa01
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71018
Tested-by: kokoro 
Maintainer: Bobby Bruce 
Reviewed-by: Bobby Bruce 
---
M src/arch/arm/fastmodel/SConscript
1 file changed, 1 insertion(+), 2 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/SConscript  
b/src/arch/arm/fastmodel/SConscript

index 3bc9aa5..7c6019e 100644
--- a/src/arch/arm/fastmodel/SConscript
+++ b/src/arch/arm/fastmodel/SConscript
@@ -218,10 +218,9 @@
 t_ID = r'[A-Za-z_]\w*'

 def t_STRLIT(self, t):
-r'(?m)"([^"])*"'
+r'"([^"])*"'
 # strip off quotes
 t.value = t.value[1:-1]
-t.lexer.lineno += t.value.count('\n')
 return t

 t_EQUALS = r'='

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Gerrit-Change-Number: 71018
Gerrit-PatchSet: 3
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Earl Ou 
Gerrit-CC: kokoro 
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[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: add src include path by default

2023-05-31 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71118?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: fastmodel: add src include path by default
..

fastmodel: add src include path by default

We have some customized protocols in gem5 repository and they require
the include path from src directory. It causes the users of those
protocols need to handle the include path correctly by theirselve. This
is tedious and unstable. We should add the default include path in
SIMGEN command line to prevent issues.

Change-Id: I2a3748646567635d131a8fb4099e02e332691e97
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71118
Reviewed-by: Wei-Han Chen 
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/arch/arm/fastmodel/CortexA76/x1/x1.sgproj
M src/arch/arm/fastmodel/CortexA76/x2/x2.sgproj
M src/arch/arm/fastmodel/CortexA76/x3/x3.sgproj
M src/arch/arm/fastmodel/CortexA76/x4/x4.sgproj
M src/arch/arm/fastmodel/CortexR52/x1/x1.sgproj
M src/arch/arm/fastmodel/CortexR52/x2/x2.sgproj
M src/arch/arm/fastmodel/CortexR52/x3/x3.sgproj
M src/arch/arm/fastmodel/CortexR52/x4/x4.sgproj
M src/arch/arm/fastmodel/GIC/GIC.sgproj
M src/arch/arm/fastmodel/PL330_DMAC/PL330.sgproj
M src/arch/arm/fastmodel/SConscript
11 files changed, 4 insertions(+), 19 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass
  Wei-Han Chen: Looks good to me, approved




diff --git a/src/arch/arm/fastmodel/CortexA76/x1/x1.sgproj  
b/src/arch/arm/fastmodel/CortexA76/x1/x1.sgproj

index f3fd0db..7101b49 100644
--- a/src/arch/arm/fastmodel/CortexA76/x1/x1.sgproj
+++ b/src/arch/arm/fastmodel/CortexA76/x1/x1.sgproj
@@ -16,8 +16,6 @@
 SIMGEN_COMMAND_LINE = "--num-comps-file 50";
 TARGET_SYSTEMC = "1";
 TARGET_SYSTEMC_AUTO = "1";
-
-INCLUDE_DIRS="../../../../../";
 }
 files
 {
diff --git a/src/arch/arm/fastmodel/CortexA76/x2/x2.sgproj  
b/src/arch/arm/fastmodel/CortexA76/x2/x2.sgproj

index abec8ad..54327dc 100644
--- a/src/arch/arm/fastmodel/CortexA76/x2/x2.sgproj
+++ b/src/arch/arm/fastmodel/CortexA76/x2/x2.sgproj
@@ -16,8 +16,6 @@
 SIMGEN_COMMAND_LINE = "--num-comps-file 50";
 TARGET_SYSTEMC = "1";
 TARGET_SYSTEMC_AUTO = "1";
-
-INCLUDE_DIRS="../../../../../";
 }
 files
 {
diff --git a/src/arch/arm/fastmodel/CortexA76/x3/x3.sgproj  
b/src/arch/arm/fastmodel/CortexA76/x3/x3.sgproj

index 666b1dc..5809b31 100644
--- a/src/arch/arm/fastmodel/CortexA76/x3/x3.sgproj
+++ b/src/arch/arm/fastmodel/CortexA76/x3/x3.sgproj
@@ -16,8 +16,6 @@
 SIMGEN_COMMAND_LINE = "--num-comps-file 50";
 TARGET_SYSTEMC = "1";
 TARGET_SYSTEMC_AUTO = "1";
-
-INCLUDE_DIRS="../../../../../";
 }
 files
 {
diff --git a/src/arch/arm/fastmodel/CortexA76/x4/x4.sgproj  
b/src/arch/arm/fastmodel/CortexA76/x4/x4.sgproj

index e3c9063..1866c98 100644
--- a/src/arch/arm/fastmodel/CortexA76/x4/x4.sgproj
+++ b/src/arch/arm/fastmodel/CortexA76/x4/x4.sgproj
@@ -16,8 +16,6 @@
 SIMGEN_COMMAND_LINE = "--num-comps-file 50";
 TARGET_SYSTEMC = "1";
 TARGET_SYSTEMC_AUTO = "1";
-
-INCLUDE_DIRS="../../../../../";
 }
 files
 {
diff --git a/src/arch/arm/fastmodel/CortexR52/x1/x1.sgproj  
b/src/arch/arm/fastmodel/CortexR52/x1/x1.sgproj

index 9d2a574..83c0584 100644
--- a/src/arch/arm/fastmodel/CortexR52/x1/x1.sgproj
+++ b/src/arch/arm/fastmodel/CortexR52/x1/x1.sgproj
@@ -16,8 +16,6 @@
 SIMGEN_COMMAND_LINE = "--num-comps-file 50";
 TARGET_SYSTEMC = "1";
 TARGET_SYSTEMC_AUTO = "1";
-
-INCLUDE_DIRS="../../../../../";
 }
 files
 {
diff --git a/src/arch/arm/fastmodel/CortexR52/x2/x2.sgproj  
b/src/arch/arm/fastmodel/CortexR52/x2/x2.sgproj

index e103170..ab8399a 100644
--- a/src/arch/arm/fastmodel/CortexR52/x2/x2.sgproj
+++ b/src/arch/arm/fastmodel/CortexR52/x2/x2.sgproj
@@ -16,8 +16,6 @@
 SIMGEN_COMMAND_LINE = "--num-comps-file 50";
 TARGET_SYSTEMC = "1";
 TARGET_SYSTEMC_AUTO = "1";
-
-INCLUDE_DIRS="../../../../../";
 }
 files
 {
diff --git a/src/arch/arm/fastmodel/CortexR52/x3/x3.sgproj  
b/src/arch/arm/fastmodel/CortexR52/x3/x3.sgproj

index 0c92809..a9bfa3f 100644
--- a/src/arch/arm/fastmodel/CortexR52/x3/x3.sgproj
+++ b/src/arch/arm/fastmodel/CortexR52/x3/x3.sgproj
@@ -16,8 +16,6 @@
 SIMGEN_COMMAND_LINE = "--num-comps-file 50";
 TARGET_SYSTEMC = "1";
 TARGET_SYSTEMC_AUTO = "1";
-
-INCLUDE_DIRS="../../../../../";
 }
 files
 {
diff --git a/src/arch/arm/fastmodel/CortexR52/x4/x4.sgproj  
b/src/arch/arm/fastmodel/CortexR52/x4/x4.sgproj

index 6a145fd..dc33376 100644
--- a/src/arch/arm/fastmodel/CortexR52/x4/x4.sgproj
+++ b/src/arch/arm/fastmodel/CortexR52/x4/x4.sgproj
@@ -16,8 +16,6 @@
 SIMGEN_COMMAND_LINE = "--num-comps-file 50";
 TARGET_SYSTEMC = "1";
 TARGET_SYSTEMC_AUTO = "1";
-
-

[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: add src include path by default

2023-05-30 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71118?usp=email )



Change subject: fastmodel: add src include path by default
..

fastmodel: add src include path by default

We have some customized protocols in gem5 repository and they require
the include path from src directory. It causes the users of those
protocols need to handle the include path correctly by theirselve. This
is tedious and unstable. We should add the default include path in
SIMGEN command line to prevent issues.

Change-Id: I2a3748646567635d131a8fb4099e02e332691e97
---
M src/arch/arm/fastmodel/CortexA76/x1/x1.sgproj
M src/arch/arm/fastmodel/CortexA76/x2/x2.sgproj
M src/arch/arm/fastmodel/CortexA76/x3/x3.sgproj
M src/arch/arm/fastmodel/CortexA76/x4/x4.sgproj
M src/arch/arm/fastmodel/CortexR52/x1/x1.sgproj
M src/arch/arm/fastmodel/CortexR52/x2/x2.sgproj
M src/arch/arm/fastmodel/CortexR52/x3/x3.sgproj
M src/arch/arm/fastmodel/CortexR52/x4/x4.sgproj
M src/arch/arm/fastmodel/GIC/GIC.sgproj
M src/arch/arm/fastmodel/PL330_DMAC/PL330.sgproj
M src/arch/arm/fastmodel/SConscript
11 files changed, 4 insertions(+), 19 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexA76/x1/x1.sgproj  
b/src/arch/arm/fastmodel/CortexA76/x1/x1.sgproj

index f3fd0db..7101b49 100644
--- a/src/arch/arm/fastmodel/CortexA76/x1/x1.sgproj
+++ b/src/arch/arm/fastmodel/CortexA76/x1/x1.sgproj
@@ -16,8 +16,6 @@
 SIMGEN_COMMAND_LINE = "--num-comps-file 50";
 TARGET_SYSTEMC = "1";
 TARGET_SYSTEMC_AUTO = "1";
-
-INCLUDE_DIRS="../../../../../";
 }
 files
 {
diff --git a/src/arch/arm/fastmodel/CortexA76/x2/x2.sgproj  
b/src/arch/arm/fastmodel/CortexA76/x2/x2.sgproj

index abec8ad..54327dc 100644
--- a/src/arch/arm/fastmodel/CortexA76/x2/x2.sgproj
+++ b/src/arch/arm/fastmodel/CortexA76/x2/x2.sgproj
@@ -16,8 +16,6 @@
 SIMGEN_COMMAND_LINE = "--num-comps-file 50";
 TARGET_SYSTEMC = "1";
 TARGET_SYSTEMC_AUTO = "1";
-
-INCLUDE_DIRS="../../../../../";
 }
 files
 {
diff --git a/src/arch/arm/fastmodel/CortexA76/x3/x3.sgproj  
b/src/arch/arm/fastmodel/CortexA76/x3/x3.sgproj

index 666b1dc..5809b31 100644
--- a/src/arch/arm/fastmodel/CortexA76/x3/x3.sgproj
+++ b/src/arch/arm/fastmodel/CortexA76/x3/x3.sgproj
@@ -16,8 +16,6 @@
 SIMGEN_COMMAND_LINE = "--num-comps-file 50";
 TARGET_SYSTEMC = "1";
 TARGET_SYSTEMC_AUTO = "1";
-
-INCLUDE_DIRS="../../../../../";
 }
 files
 {
diff --git a/src/arch/arm/fastmodel/CortexA76/x4/x4.sgproj  
b/src/arch/arm/fastmodel/CortexA76/x4/x4.sgproj

index e3c9063..1866c98 100644
--- a/src/arch/arm/fastmodel/CortexA76/x4/x4.sgproj
+++ b/src/arch/arm/fastmodel/CortexA76/x4/x4.sgproj
@@ -16,8 +16,6 @@
 SIMGEN_COMMAND_LINE = "--num-comps-file 50";
 TARGET_SYSTEMC = "1";
 TARGET_SYSTEMC_AUTO = "1";
-
-INCLUDE_DIRS="../../../../../";
 }
 files
 {
diff --git a/src/arch/arm/fastmodel/CortexR52/x1/x1.sgproj  
b/src/arch/arm/fastmodel/CortexR52/x1/x1.sgproj

index 9d2a574..83c0584 100644
--- a/src/arch/arm/fastmodel/CortexR52/x1/x1.sgproj
+++ b/src/arch/arm/fastmodel/CortexR52/x1/x1.sgproj
@@ -16,8 +16,6 @@
 SIMGEN_COMMAND_LINE = "--num-comps-file 50";
 TARGET_SYSTEMC = "1";
 TARGET_SYSTEMC_AUTO = "1";
-
-INCLUDE_DIRS="../../../../../";
 }
 files
 {
diff --git a/src/arch/arm/fastmodel/CortexR52/x2/x2.sgproj  
b/src/arch/arm/fastmodel/CortexR52/x2/x2.sgproj

index e103170..ab8399a 100644
--- a/src/arch/arm/fastmodel/CortexR52/x2/x2.sgproj
+++ b/src/arch/arm/fastmodel/CortexR52/x2/x2.sgproj
@@ -16,8 +16,6 @@
 SIMGEN_COMMAND_LINE = "--num-comps-file 50";
 TARGET_SYSTEMC = "1";
 TARGET_SYSTEMC_AUTO = "1";
-
-INCLUDE_DIRS="../../../../../";
 }
 files
 {
diff --git a/src/arch/arm/fastmodel/CortexR52/x3/x3.sgproj  
b/src/arch/arm/fastmodel/CortexR52/x3/x3.sgproj

index 0c92809..a9bfa3f 100644
--- a/src/arch/arm/fastmodel/CortexR52/x3/x3.sgproj
+++ b/src/arch/arm/fastmodel/CortexR52/x3/x3.sgproj
@@ -16,8 +16,6 @@
 SIMGEN_COMMAND_LINE = "--num-comps-file 50";
 TARGET_SYSTEMC = "1";
 TARGET_SYSTEMC_AUTO = "1";
-
-INCLUDE_DIRS="../../../../../";
 }
 files
 {
diff --git a/src/arch/arm/fastmodel/CortexR52/x4/x4.sgproj  
b/src/arch/arm/fastmodel/CortexR52/x4/x4.sgproj

index 6a145fd..dc33376 100644
--- a/src/arch/arm/fastmodel/CortexR52/x4/x4.sgproj
+++ b/src/arch/arm/fastmodel/CortexR52/x4/x4.sgproj
@@ -16,8 +16,6 @@
 SIMGEN_COMMAND_LINE = "--num-comps-file 50";
 TARGET_SYSTEMC = "1";
 TARGET_SYSTEMC_AUTO = "1";
-
-INCLUDE_DIRS="../../../../../";
 }
 files
 {
diff --git a/src/arch/arm/fastmodel/GIC/GIC.sgproj  
b/src/arch/arm/fastmodel/GIC/GIC.sgproj

index aa5e6ae..fd5c04a 100644
--- a/src/arch/arm/fastmodel/GIC/GIC.sgproj
+++ b/src/arch/arm/fastmodel/GIC/GIC.sgproj
@@ -5,7 +5,7 @@
 ACTIVE_CONFIG_WINDOWS  = "Win64-Release-VC2015";
 config "gcc"
 {
-ADDITIONAL_COMPILER_SETTINGS = "-O3 -Wall -std=c++14 -Wno-deprecated

[gem5-dev] [S] Change in gem5/gem5[develop]: arch: set multiline re as default in isa_parser

2023-05-29 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71019?usp=email )



Change subject: arch: set multiline re as default in isa_parser
..

arch: set multiline re as default in isa_parser

In python3.11, it requires the global specifier should be the first
token of regex. However it's not possible when using ply library.
Instead, we set the rules are multiline regex by default and modifies
those single line rules.

Ref: https://github.com/dabeaz/ply/issues/282

Change-Id: I7bdbfeb97a9dd74f45c1890a76f8cc16100e5a42
---
M src/arch/isa_parser/isa_parser.py
1 file changed, 6 insertions(+), 5 deletions(-)



diff --git a/src/arch/isa_parser/isa_parser.py  
b/src/arch/isa_parser/isa_parser.py

index 0f29840..9ff5723 100755
--- a/src/arch/isa_parser/isa_parser.py
+++ b/src/arch/isa_parser/isa_parser.py
@@ -514,6 +514,7 @@
 class ISAParser(Grammar):
 def __init__(self, output_dir):
 super().__init__()
+self.lex_kwargs['reflags'] = int(re.MULTILINE)
 self.output_dir = output_dir

 self.filename = None  # for output file watermarking/scaremongering
@@ -851,7 +852,7 @@
 # String literal.  Note that these use only single quotes, and
 # can span multiple lines.
 def t_STRLIT(self, t):
-r"(?m)'([^'])+'"
+r"'([^'])+'"
 # strip off quotes
 t.value = t.value[1:-1]
 t.lexer.lineno += t.value.count("\n")
@@ -860,19 +861,19 @@
 # "Code literal"... like a string literal, but delimiters are
 # '{{' and '}}' so they get formatted nicely under emacs c-mode
 def t_CODELIT(self, t):
-r"(?m)\{\{([^\}]|}(?!\}))+\}\}"
+r"\{\{([^\}]|}(?!\}))+\}\}"
 # strip off {{ & }}
 t.value = t.value[2:-2]
 t.lexer.lineno += t.value.count("\n")
 return t

 def t_CPPDIRECTIVE(self, t):
-r"^\#[^\#].*\n"
+r"^\#[^\#][^\n]*\n"
 t.lexer.lineno += t.value.count("\n")
 return t

 def t_NEWFILE(self, t):
-r'^\#\#newfile\s+"[^"]*"\n'
+r'^\#\#newfile\s+"[^"\n]*"\n'
 self.fileNameStack.push(t.lexer.lineno)
 t.lexer.lineno = LineTracker(t.value[11:-2])

@@ -892,7 +893,7 @@

 # Comments
 def t_comment(self, t):
-r"//.*"
+r"//[^\n]*\n"

 # Completely ignored characters
 t_ignore = " \t\x0c"

--
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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7bdbfeb97a9dd74f45c1890a76f8cc16100e5a42
Gerrit-Change-Number: 71019
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: fastmodel: only support single line literal when paring project file

2023-05-29 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71018?usp=email )



Change subject: fastmodel: only support single line literal when paring  
project file

..

fastmodel: only support single line literal when paring project file

In python3.11, it requires the global specifier should be the first
token of regex. However it's not possible when using ply library. In
fastmodel case, we actually don't need to support multiline string
literal. We fix this issue by just making the string literal single
line.

Ref: https://github.com/dabeaz/ply/issues/282

Change-Id: I746b628db7ad4c1d7834f1a1b2c1243cef68aa01
---
M src/arch/arm/fastmodel/SConscript
1 file changed, 1 insertion(+), 2 deletions(-)



diff --git a/src/arch/arm/fastmodel/SConscript  
b/src/arch/arm/fastmodel/SConscript

index 9d9d183..0a81e9e 100644
--- a/src/arch/arm/fastmodel/SConscript
+++ b/src/arch/arm/fastmodel/SConscript
@@ -218,10 +218,9 @@
 t_ID = r'[A-Za-z_]\w*'

 def t_STRLIT(self, t):
-r'(?m)"([^"])*"'
+r'"([^"])*"'
 # strip off quotes
 t.value = t.value[1:-1]
-t.lexer.lineno += t.value.count('\n')
 return t

 t_EQUALS = r'='

--
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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I746b628db7ad4c1d7834f1a1b2c1243cef68aa01
Gerrit-Change-Number: 71018
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang 
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[gem5-dev] [M] Change in gem5/gem5[develop]: fastmodel: skip vector registers update in remote gdb

2023-03-22 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69177?usp=email )


Change subject: fastmodel: skip vector registers update in remote gdb
..

fastmodel: skip vector registers update in remote gdb

iris::ThreadContext doesn't implement the write interface for vector
registers. Skip that part in fastmodel remote_gdb to make updating
common registers work at least.

Change-Id: Ifa071f5dff4bdeee7361ae824b4b76e0b2805460
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69177
Maintainer: Gabe Black 
Reviewed-by: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/remote_gdb.cc
M src/arch/arm/fastmodel/remote_gdb.hh
M src/arch/arm/remote_gdb.hh
M src/base/remote_gdb.hh
4 files changed, 64 insertions(+), 16 deletions(-)

Approvals:
  kokoro: Regressions pass
  Gabe Black: Looks good to me, approved; Looks good to me, approved




diff --git a/src/arch/arm/fastmodel/remote_gdb.cc  
b/src/arch/arm/fastmodel/remote_gdb.cc

index e13fee8..d8dddad 100644
--- a/src/arch/arm/fastmodel/remote_gdb.cc
+++ b/src/arch/arm/fastmodel/remote_gdb.cc
@@ -27,13 +27,42 @@
 #include "arch/arm/fastmodel/remote_gdb.hh"

 #include "arch/arm/fastmodel/iris/thread_context.hh"
+#include "arch/arm/utility.hh"
+#include "base/trace.hh"
+#include "debug/GDBAcc.hh"

 namespace gem5 {

+using namespace ArmISA;
+
 namespace fastmodel {

+void
+FastmodelRemoteGDB::AArch64GdbRegCache::setRegs(ThreadContext *context)  
const

+{
+DPRINTF(GDBAcc, "setRegs in remotegdb \n");
+
+for (int i = 0; i < 31; ++i)
+context->setReg(int_reg::x(i), r.x[i]);
+auto pc_state = context->pcState().as();
+pc_state.set(r.pc);
+context->pcState(pc_state);
+context->setMiscRegNoEffect(MISCREG_CPSR, r.cpsr);
+// Update the stack pointer. This should be done after
+// updating CPSR/PSTATE since that might affect how SPX gets
+// mapped.
+context->setReg(int_reg::Spx, r.spx);
+
+// Remove the vector registers update in FastmodelRemoteGDB since it's  
not

+// implemented in iris::ThreadContext.
+warn("Skip update vector registers in remotegdb\n");
+
+context->setMiscRegNoEffect(MISCREG_FPSR, r.fpsr);
+context->setMiscRegNoEffect(MISCREG_FPCR, r.fpcr);
+}
+
 FastmodelRemoteGDB::FastmodelRemoteGDB(System *_system, int port)
-: gem5::ArmISA::RemoteGDB(_system, port)
+: gem5::ArmISA::RemoteGDB(_system, port), regCache64(this)
 {
 }

@@ -57,5 +86,14 @@
 return true;
 }

+BaseGdbRegCache*
+FastmodelRemoteGDB::gdbRegs()
+{
+if (inAArch64(context()))
+return 
+else
+return 
+}
+
 }  // namespace fastmodel
 }  // namespace gem5
diff --git a/src/arch/arm/fastmodel/remote_gdb.hh  
b/src/arch/arm/fastmodel/remote_gdb.hh

index 93cf882..75dc658 100644
--- a/src/arch/arm/fastmodel/remote_gdb.hh
+++ b/src/arch/arm/fastmodel/remote_gdb.hh
@@ -36,14 +36,24 @@
 namespace fastmodel
 {

-class FastmodelRemoteGDB : public gem5::ArmISA::RemoteGDB
+class FastmodelRemoteGDB : public ArmISA::RemoteGDB
 {
   public:
 FastmodelRemoteGDB(System *_system, int port);

-  private:
+  protected:
+class AArch64GdbRegCache : public ArmISA::RemoteGDB::AArch64GdbRegCache
+{
+  using ArmISA::RemoteGDB::AArch64GdbRegCache::AArch64GdbRegCache;
+  public:
+void setRegs(ThreadContext*) const override;
+};
+
 bool readBlob(Addr vaddr, size_t size, char *data) override;
 bool writeBlob(Addr vaddr, size_t size, const char *data) override;
+BaseGdbRegCache* gdbRegs() override;
+
+AArch64GdbRegCache regCache64;
 };

 }  // namespace fastmodel
diff --git a/src/arch/arm/remote_gdb.hh b/src/arch/arm/remote_gdb.hh
index 8e512a4..aeb2db6 100644
--- a/src/arch/arm/remote_gdb.hh
+++ b/src/arch/arm/remote_gdb.hh
@@ -68,7 +68,7 @@
 class AArch32GdbRegCache : public BaseGdbRegCache
 {
   using BaseGdbRegCache::BaseGdbRegCache;
-  private:
+  protected:
 struct GEM5_PACKED
 {
   uint32_t gpr[16];
@@ -77,12 +77,12 @@
   uint32_t fpscr;
 } r;
   public:
-char *data() const { return (char *) }
-size_t size() const { return sizeof(r); }
-void getRegs(ThreadContext*);
-void setRegs(ThreadContext*) const;
+char *data() const override { return (char *) }
+size_t size() const override { return sizeof(r); }
+void getRegs(ThreadContext*) override;
+void setRegs(ThreadContext*) const override;
 const std::string
-name() const
+name() const override
 {
 return gdb->name() + ".AArch32GdbRegCache";
 }
@@ -91,7 +91,7 @@
 class AArch64GdbRegCache : public BaseGdbRegCache
 {
   using BaseGdbRegCache::BaseGdbRegCache;
-  private:
+  protected:
 struct GEM5_PACKED
 {
   uint64_t x[31];
@@ -103,12 +103,12 @@
   uint32_t fpcr;

[gem5-dev] [M] Change in gem5/gem5[develop]: fastmodel: skip vector registers update in remote gdb

2023-03-21 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69177?usp=email )



Change subject: fastmodel: skip vector registers update in remote gdb
..

fastmodel: skip vector registers update in remote gdb

iris::ThreadContext doesn't implement the write interface for vector
registers. Skip that part in fastmodel remote_gdb to make updating
common registers work at least.

Change-Id: Ifa071f5dff4bdeee7361ae824b4b76e0b2805460
---
M src/arch/arm/fastmodel/remote_gdb.cc
M src/arch/arm/fastmodel/remote_gdb.hh
M src/arch/arm/remote_gdb.hh
M src/base/remote_gdb.hh
4 files changed, 64 insertions(+), 16 deletions(-)



diff --git a/src/arch/arm/fastmodel/remote_gdb.cc  
b/src/arch/arm/fastmodel/remote_gdb.cc

index e13fee8..d8dddad 100644
--- a/src/arch/arm/fastmodel/remote_gdb.cc
+++ b/src/arch/arm/fastmodel/remote_gdb.cc
@@ -27,13 +27,42 @@
 #include "arch/arm/fastmodel/remote_gdb.hh"

 #include "arch/arm/fastmodel/iris/thread_context.hh"
+#include "arch/arm/utility.hh"
+#include "base/trace.hh"
+#include "debug/GDBAcc.hh"

 namespace gem5 {

+using namespace ArmISA;
+
 namespace fastmodel {

+void
+FastmodelRemoteGDB::AArch64GdbRegCache::setRegs(ThreadContext *context)  
const

+{
+DPRINTF(GDBAcc, "setRegs in remotegdb \n");
+
+for (int i = 0; i < 31; ++i)
+context->setReg(int_reg::x(i), r.x[i]);
+auto pc_state = context->pcState().as();
+pc_state.set(r.pc);
+context->pcState(pc_state);
+context->setMiscRegNoEffect(MISCREG_CPSR, r.cpsr);
+// Update the stack pointer. This should be done after
+// updating CPSR/PSTATE since that might affect how SPX gets
+// mapped.
+context->setReg(int_reg::Spx, r.spx);
+
+// Remove the vector registers update in FastmodelRemoteGDB since it's  
not

+// implemented in iris::ThreadContext.
+warn("Skip update vector registers in remotegdb\n");
+
+context->setMiscRegNoEffect(MISCREG_FPSR, r.fpsr);
+context->setMiscRegNoEffect(MISCREG_FPCR, r.fpcr);
+}
+
 FastmodelRemoteGDB::FastmodelRemoteGDB(System *_system, int port)
-: gem5::ArmISA::RemoteGDB(_system, port)
+: gem5::ArmISA::RemoteGDB(_system, port), regCache64(this)
 {
 }

@@ -57,5 +86,14 @@
 return true;
 }

+BaseGdbRegCache*
+FastmodelRemoteGDB::gdbRegs()
+{
+if (inAArch64(context()))
+return 
+else
+return 
+}
+
 }  // namespace fastmodel
 }  // namespace gem5
diff --git a/src/arch/arm/fastmodel/remote_gdb.hh  
b/src/arch/arm/fastmodel/remote_gdb.hh

index 93cf882..75dc658 100644
--- a/src/arch/arm/fastmodel/remote_gdb.hh
+++ b/src/arch/arm/fastmodel/remote_gdb.hh
@@ -36,14 +36,24 @@
 namespace fastmodel
 {

-class FastmodelRemoteGDB : public gem5::ArmISA::RemoteGDB
+class FastmodelRemoteGDB : public ArmISA::RemoteGDB
 {
   public:
 FastmodelRemoteGDB(System *_system, int port);

-  private:
+  protected:
+class AArch64GdbRegCache : public ArmISA::RemoteGDB::AArch64GdbRegCache
+{
+  using ArmISA::RemoteGDB::AArch64GdbRegCache::AArch64GdbRegCache;
+  public:
+void setRegs(ThreadContext*) const override;
+};
+
 bool readBlob(Addr vaddr, size_t size, char *data) override;
 bool writeBlob(Addr vaddr, size_t size, const char *data) override;
+BaseGdbRegCache* gdbRegs() override;
+
+AArch64GdbRegCache regCache64;
 };

 }  // namespace fastmodel
diff --git a/src/arch/arm/remote_gdb.hh b/src/arch/arm/remote_gdb.hh
index 8e512a4..aeb2db6 100644
--- a/src/arch/arm/remote_gdb.hh
+++ b/src/arch/arm/remote_gdb.hh
@@ -68,7 +68,7 @@
 class AArch32GdbRegCache : public BaseGdbRegCache
 {
   using BaseGdbRegCache::BaseGdbRegCache;
-  private:
+  protected:
 struct GEM5_PACKED
 {
   uint32_t gpr[16];
@@ -77,12 +77,12 @@
   uint32_t fpscr;
 } r;
   public:
-char *data() const { return (char *) }
-size_t size() const { return sizeof(r); }
-void getRegs(ThreadContext*);
-void setRegs(ThreadContext*) const;
+char *data() const override { return (char *) }
+size_t size() const override { return sizeof(r); }
+void getRegs(ThreadContext*) override;
+void setRegs(ThreadContext*) const override;
 const std::string
-name() const
+name() const override
 {
 return gdb->name() + ".AArch32GdbRegCache";
 }
@@ -91,7 +91,7 @@
 class AArch64GdbRegCache : public BaseGdbRegCache
 {
   using BaseGdbRegCache::BaseGdbRegCache;
-  private:
+  protected:
 struct GEM5_PACKED
 {
   uint64_t x[31];
@@ -103,12 +103,12 @@
   uint32_t fpcr;
 } r;
   public:
-char *data() const { return (char *) }
-size_t size() const { return sizeof(r); }
-void getRegs(ThreadContext*);
-void setRegs(ThreadContext*) const;
+char *data() const

[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: delay the breakpoint event handle to simulation stop

2023-03-19 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68697?usp=email )


Change subject: fastmodel: delay the breakpoint event handle to simulation  
stop

..

fastmodel: delay the breakpoint event handle to simulation stop

The fastmodel simulation would be paused when it hits a breakpoint.
However, the order of stop event happens after the breakpoint event. If
we handle the breakpoint logic in the breakpoint event, it may cause
somehow status unsynchronized. To make the behavior stable, we delay the
breakpoint handle until the simulation stop event called.

Change-Id: I0083561f561af71370ccaa066220b72ed7831b78
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68697
Reviewed-by: Earl Ou 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/iris/thread_context.cc
M src/arch/arm/fastmodel/iris/thread_context.hh
2 files changed, 21 insertions(+), 12 deletions(-)

Approvals:
  Earl Ou: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc  
b/src/arch/arm/fastmodel/iris/thread_context.cc

index 45e020d..462995a 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -269,6 +269,22 @@
 return iris::E_ok;
 }

+// Handle the breakpoint event at simulation is stopped if needed.
+if (bpAddr.has_value()) {
+auto it = getOrAllocBp(bpAddr.value());
+
+std::shared_ptr events = it->second->events;
+auto e_it = events->begin();
+while (e_it != events->end()) {
+PCEvent *e = *e_it;
+// Advance e_it here since e might remove itself from the list.
+e_it++;
+e->process(this);
+}
+
+bpAddr.reset();
+}
+
 // If simulation time has stopped for any reason, IRIS helpfully clears
 // all stepping counters and we need to set them back. We might also  
need
 // to service events based on the current number of executed  
instructions.

@@ -286,19 +302,10 @@
 uint64_t esId, const iris::IrisValueMap , uint64_t time,
 uint64_t sInstId, bool syncEc, std::string _message_out)
 {
+// Handle the breakpoint event later when the fastmodel simulation is
+// stopped.
 Addr pc = fields.at("PC").getU64();
-
-auto it = getOrAllocBp(pc);
-
-std::shared_ptr events = it->second->events;
-auto e_it = events->begin();
-while (e_it != events->end()) {
-PCEvent *e = *e_it;
-// Advance e_it here since e might remove itself from the list.
-e_it++;
-e->process(this);
-}
-
+bpAddr = pc;
 return iris::E_ok;
 }

diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh  
b/src/arch/arm/fastmodel/iris/thread_context.hh

index 05209e6..88c6746 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -31,6 +31,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 

 #include "arch/arm/fastmodel/iris/memory_spaces.hh"
@@ -133,6 +134,7 @@
 using BpInfoIt = BpInfoMap::iterator;

 BpInfoMap bps;
+std::optional bpAddr;

 BpInfoIt getOrAllocBp(Addr pc);


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0083561f561af71370ccaa066220b72ed7831b78
Gerrit-Change-Number: 68697
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Wei-Han Chen 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: delay the breakpoint event handle to simulation stop

2023-03-07 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68697?usp=email )



Change subject: fastmodel: delay the breakpoint event handle to simulation  
stop

..

fastmodel: delay the breakpoint event handle to simulation stop

The fastmodel simulation would be paused when it hits a breakpoint.
However, the order of stop event happens after the breakpoint event. If
we handle the breakpoint logic in the breakpoint event, it may cause
somehow status unsynchronized. To make the behavior stable, we delay the
breakpoint handle until the simulation stop event called.

Change-Id: I0083561f561af71370ccaa066220b72ed7831b78
---
M src/arch/arm/fastmodel/iris/thread_context.cc
M src/arch/arm/fastmodel/iris/thread_context.hh
2 files changed, 21 insertions(+), 12 deletions(-)



diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc  
b/src/arch/arm/fastmodel/iris/thread_context.cc

index 45e020d..462995a 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -269,6 +269,22 @@
 return iris::E_ok;
 }

+// Handle the breakpoint event at simulation is stopped if needed.
+if (bpAddr.has_value()) {
+auto it = getOrAllocBp(bpAddr.value());
+
+std::shared_ptr events = it->second->events;
+auto e_it = events->begin();
+while (e_it != events->end()) {
+PCEvent *e = *e_it;
+// Advance e_it here since e might remove itself from the list.
+e_it++;
+e->process(this);
+}
+
+bpAddr.reset();
+}
+
 // If simulation time has stopped for any reason, IRIS helpfully clears
 // all stepping counters and we need to set them back. We might also  
need
 // to service events based on the current number of executed  
instructions.

@@ -286,19 +302,10 @@
 uint64_t esId, const iris::IrisValueMap , uint64_t time,
 uint64_t sInstId, bool syncEc, std::string _message_out)
 {
+// Handle the breakpoint event later when the fastmodel simulation is
+// stopped.
 Addr pc = fields.at("PC").getU64();
-
-auto it = getOrAllocBp(pc);
-
-std::shared_ptr events = it->second->events;
-auto e_it = events->begin();
-while (e_it != events->end()) {
-PCEvent *e = *e_it;
-// Advance e_it here since e might remove itself from the list.
-e_it++;
-e->process(this);
-}
-
+bpAddr = pc;
 return iris::E_ok;
 }

diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh  
b/src/arch/arm/fastmodel/iris/thread_context.hh

index 05209e6..88c6746 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -31,6 +31,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 

 #include "arch/arm/fastmodel/iris/memory_spaces.hh"
@@ -133,6 +134,7 @@
 using BpInfoIt = BpInfoMap::iterator;

 BpInfoMap bps;
+std::optional bpAddr;

 BpInfoIt getOrAllocBp(Addr pc);


--
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Gerrit-Branch: develop
Gerrit-Change-Id: I0083561f561af71370ccaa066220b72ed7831b78
Gerrit-Change-Number: 68697
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang 
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: mem: Implemement backdoor interface for Bridge

2023-01-11 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67291?usp=email )


Change subject: mem: Implemement backdoor interface for Bridge
..

mem: Implemement backdoor interface for Bridge

Change-Id: I5ff62b03c34e41395a957a0799925ddd9c275458
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67291
Reviewed-by: Nicolas Boichat 
Tested-by: kokoro 
Maintainer: Gabe Black 
Reviewed-by: Gabe Black 
---
M src/mem/bridge.cc
M src/mem/bridge.hh
2 files changed, 49 insertions(+), 8 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  Nicolas Boichat: Looks good to me, but someone else must approve
  kokoro: Regressions pass




diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index 0f744f7..36832eb 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -347,6 +347,14 @@
 return delay * bridge.clockPeriod() + memSidePort.sendAtomic(pkt);
 }

+Tick
+Bridge::BridgeResponsePort::recvAtomicBackdoor(
+PacketPtr pkt, MemBackdoorPtr )
+{
+return delay * bridge.clockPeriod() + memSidePort.sendAtomicBackdoor(
+pkt, backdoor);
+}
+
 void
 Bridge::BridgeResponsePort::recvFunctional(PacketPtr pkt)
 {
@@ -371,6 +379,13 @@
 memSidePort.sendFunctional(pkt);
 }

+void
+Bridge::BridgeResponsePort::recvMemBackdoorReq(
+const MemBackdoorReq , MemBackdoorPtr )
+{
+memSidePort.sendMemBackdoorReq(req, backdoor);
+}
+
 bool
 Bridge::BridgeRequestPort::trySatisfyFunctional(PacketPtr pkt)
 {
diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index f56cef1..e4a6837 100644
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -195,23 +195,35 @@

 /** When receiving a timing request from the peer port,
 pass it to the bridge. */
-bool recvTimingReq(PacketPtr pkt);
+bool recvTimingReq(PacketPtr pkt) override;

 /** When receiving a retry request from the peer port,
 pass it to the bridge. */
-void recvRespRetry();
+void recvRespRetry() override;

-/** When receiving a Atomic requestfrom the peer port,
+/** When receiving an Atomic request from the peer port,
 pass it to the bridge. */
-Tick recvAtomic(PacketPtr pkt);
+Tick recvAtomic(PacketPtr pkt) override;
+
+/** When receiving an Atomic backdoor request from the peer port,
+pass it to the bridge. */
+Tick recvAtomicBackdoor(
+PacketPtr pkt, MemBackdoorPtr ) override;
+

 /** When receiving a Functional request from the peer port,
 pass it to the bridge. */
-void recvFunctional(PacketPtr pkt);
+void recvFunctional(PacketPtr pkt) override;
+
+/** When receiving a Functional backdoor request from the peer  
port,

+pass it to the bridge. */
+void recvMemBackdoorReq(
+const MemBackdoorReq , MemBackdoorPtr ) override;
+

 /** When receiving a address range request the peer port,
 pass it to the bridge. */
-AddrRangeList getAddrRanges() const;
+AddrRangeList getAddrRanges() const override;
 };


@@ -303,11 +315,11 @@

 /** When receiving a timing request from the peer port,
 pass it to the bridge. */
-bool recvTimingResp(PacketPtr pkt);
+bool recvTimingResp(PacketPtr pkt) override;

 /** When receiving a retry request from the peer port,
 pass it to the bridge. */
-void recvReqRetry();
+void recvReqRetry() override;
 };

 /** Response port of the bridge. */

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5ff62b03c34e41395a957a0799925ddd9c275458
Gerrit-Change-Number: 67291
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Nicolas Boichat 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Yan Lee 
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: mem: Implemement backdoor interface for Bridge

2023-01-10 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67291?usp=email )



Change subject: mem: Implemement backdoor interface for Bridge
..

mem: Implemement backdoor interface for Bridge

Change-Id: I5ff62b03c34e41395a957a0799925ddd9c275458
---
M src/mem/bridge.cc
M src/mem/bridge.hh
2 files changed, 44 insertions(+), 8 deletions(-)



diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index 0f744f7..36832eb 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -347,6 +347,14 @@
 return delay * bridge.clockPeriod() + memSidePort.sendAtomic(pkt);
 }

+Tick
+Bridge::BridgeResponsePort::recvAtomicBackdoor(
+PacketPtr pkt, MemBackdoorPtr )
+{
+return delay * bridge.clockPeriod() + memSidePort.sendAtomicBackdoor(
+pkt, backdoor);
+}
+
 void
 Bridge::BridgeResponsePort::recvFunctional(PacketPtr pkt)
 {
@@ -371,6 +379,13 @@
 memSidePort.sendFunctional(pkt);
 }

+void
+Bridge::BridgeResponsePort::recvMemBackdoorReq(
+const MemBackdoorReq , MemBackdoorPtr )
+{
+memSidePort.sendMemBackdoorReq(req, backdoor);
+}
+
 bool
 Bridge::BridgeRequestPort::trySatisfyFunctional(PacketPtr pkt)
 {
diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index f56cef1..e4a6837 100644
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -195,23 +195,35 @@

 /** When receiving a timing request from the peer port,
 pass it to the bridge. */
-bool recvTimingReq(PacketPtr pkt);
+bool recvTimingReq(PacketPtr pkt) override;

 /** When receiving a retry request from the peer port,
 pass it to the bridge. */
-void recvRespRetry();
+void recvRespRetry() override;

-/** When receiving a Atomic requestfrom the peer port,
+/** When receiving an Atomic request from the peer port,
 pass it to the bridge. */
-Tick recvAtomic(PacketPtr pkt);
+Tick recvAtomic(PacketPtr pkt) override;
+
+/** When receiving an Atomic backdoor request from the peer port,
+pass it to the bridge. */
+Tick recvAtomicBackdoor(
+PacketPtr pkt, MemBackdoorPtr ) override;
+

 /** When receiving a Functional request from the peer port,
 pass it to the bridge. */
-void recvFunctional(PacketPtr pkt);
+void recvFunctional(PacketPtr pkt) override;
+
+/** When receiving a Functional backdoor request from the peer  
port,

+pass it to the bridge. */
+void recvMemBackdoorReq(
+const MemBackdoorReq , MemBackdoorPtr ) override;
+

 /** When receiving a address range request the peer port,
 pass it to the bridge. */
-AddrRangeList getAddrRanges() const;
+AddrRangeList getAddrRanges() const override;
 };


@@ -303,11 +315,11 @@

 /** When receiving a timing request from the peer port,
 pass it to the bridge. */
-bool recvTimingResp(PacketPtr pkt);
+bool recvTimingResp(PacketPtr pkt) override;

 /** When receiving a retry request from the peer port,
 pass it to the bridge. */
-void recvReqRetry();
+void recvReqRetry() override;
 };

 /** Response port of the bridge. */

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Gerrit-Owner: Yu-hsin Wang 
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[gem5-dev] [S] Change in gem5/gem5[develop]: mem: Implement and use the recvMemBackdoorReq func.

2022-12-08 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66551?usp=email )



Change subject: mem: Implement and use the recvMemBackdoorReq func.
..

mem: Implement and use the recvMemBackdoorReq func.

In the previous change, we miss some model supporting atomic backdoor.
We should also implement the recvMemBackdoorReq to them.

Change-Id: I4706d215aa4a5d18fe4306b2387f9c8750cb4b4a
---
M src/mem/hbm_ctrl.cc
M src/mem/hbm_ctrl.hh
M src/mem/thread_bridge.cc
M src/mem/thread_bridge.hh
4 files changed, 39 insertions(+), 0 deletions(-)



diff --git a/src/mem/hbm_ctrl.cc b/src/mem/hbm_ctrl.cc
index 99618c4..747e714 100644
--- a/src/mem/hbm_ctrl.cc
+++ b/src/mem/hbm_ctrl.cc
@@ -150,6 +150,21 @@
 return latency;
 }

+void
+HBMCtrl::recvMemBackdoorReq(const MemBackdoorReq ,
+MemBackdoorPtr )
+{
+auto  = req.range();
+if (pc0Int && pc0Int->getAddrRange().isSubset(range)) {
+pc0Int->getBackdoor(backdoor);
+} else if (pc1Int && pc1Int->getAddrRange().isSubset(range)) {
+pc1Int->getBackdoor(backdoor);
+}
+else {
+panic("Can't handle address range for range %s\n",  
range.to_string());

+}
+}
+
 bool
 HBMCtrl::writeQueueFullPC0(unsigned int neededEntries) const
 {
diff --git a/src/mem/hbm_ctrl.hh b/src/mem/hbm_ctrl.hh
index c9045f0..a6ecf6c 100644
--- a/src/mem/hbm_ctrl.hh
+++ b/src/mem/hbm_ctrl.hh
@@ -259,6 +259,8 @@
 Tick recvAtomic(PacketPtr pkt) override;
 Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr )  
override;

 void recvFunctional(PacketPtr pkt) override;
+void recvMemBackdoorReq(const MemBackdoorReq ,
+MemBackdoorPtr &_backdoor) override;
 bool recvTimingReq(PacketPtr pkt) override;

 };
diff --git a/src/mem/thread_bridge.cc b/src/mem/thread_bridge.cc
index 3f76ef4..efaf19a 100644
--- a/src/mem/thread_bridge.cc
+++ b/src/mem/thread_bridge.cc
@@ -84,6 +84,14 @@
 device_.out_port_.sendFunctional(pkt);
 }

+void
+ThreadBridge::IncomingPort::recvMemBackdoorReq(const MemBackdoorReq ,
+   MemBackdoorPtr )
+{
+EventQueue::ScopedMigration migrate(device_.eventQueue());
+device_.out_port_.sendMemBackdoorReq(req, backdoor);
+}
+
 ThreadBridge::OutgoingPort::OutgoingPort(const std::string ,
  ThreadBridge )
 : RequestPort(name, ), device_(device)
diff --git a/src/mem/thread_bridge.hh b/src/mem/thread_bridge.hh
index 28c9591..92cb078 100644
--- a/src/mem/thread_bridge.hh
+++ b/src/mem/thread_bridge.hh
@@ -61,6 +61,8 @@

 // FunctionalResponseProtocol
 void recvFunctional(PacketPtr pkt) override;
+void recvMemBackdoorReq(const MemBackdoorReq ,
+MemBackdoorPtr ) override;

   private:
 ThreadBridge _;

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[gem5-dev] [S] Change in gem5/gem5[develop]: systemc: replace the deprecated std::iterator

2022-12-06 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66351?usp=email )


Change subject: systemc: replace the deprecated std::iterator
..

systemc: replace the deprecated std::iterator

std::iterator is deprecated in c++17. We can just declare the
required types for iterator traits directly without the helper.

Change-Id: I789e2c2b13e56cc391527686109df8b779474d09
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66351
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/systemc/ext/utils/sc_vector.hh
1 file changed, 23 insertions(+), 9 deletions(-)

Approvals:
  kokoro: Regressions pass
  Gabe Black: Looks good to me, approved; Looks good to me, approved




diff --git a/src/systemc/ext/utils/sc_vector.hh  
b/src/systemc/ext/utils/sc_vector.hh

index ef0d7dc..c1d9ded 100644
--- a/src/systemc/ext/utils/sc_vector.hh
+++ b/src/systemc/ext/utils/sc_vector.hh
@@ -49,6 +49,7 @@

 #include 

+#include 
 #include 
 #include 
 #include 
@@ -259,10 +260,7 @@

 template  >
-class sc_vector_iter :
-public std::iterator,
-private AccessPolicy
+class sc_vector_iter : private AccessPolicy
 {
   private:
 typedef Element ElementType;
@@ -282,8 +280,6 @@
 template 
 friend class sc_vector_iter;

-typedef std::iterator
-BaseType;
 typedef sc_vector_iter ThisType;
 typedef sc_vector VectorType;
 typedef std::vector StorageType;
@@ -315,9 +311,11 @@
 // Conforms to Random Access Iterator category.
 // See ISO/IEC 14882:2003(E), 24.1 [lib.iterator.requirements]

-typedef typename BaseType::difference_type difference_type;
-typedef typename BaseType::reference reference;
-typedef typename BaseType::pointer pointer;
+using difference_type = std::ptrdiff_t;
+using value_type = typename AccessPolicy::Type;
+using reference = typename AccessPolicy::Type &;
+using pointer = typename AccessPolicy::Type *;
+using iterator_category = std::random_access_iterator_tag;

 sc_vector_iter() : Policy(), it_() {}


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Gerrit-Change-Number: 66351
Gerrit-PatchSet: 3
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
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[gem5-dev] [S] Change in gem5/gem5[develop]: systemc: fix the payload and packet association in Gem5ToTlm bridge

2022-12-06 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66054?usp=email )


Change subject: systemc: fix the payload and packet association in  
Gem5ToTlm bridge

..

systemc: fix the payload and packet association in Gem5ToTlm bridge

If a request is initiated by systemc, passed through TlmToGem5 bridge
and Gem5ToTlm bridge, it wouldn't have the systemc extension about the
association. This feature is also used in TlmToGem5 bridge to detect if
the packet is allocated in the current instance in async interface. In
that case, we would lose the association in the Gem5ToTlm bridge async
interface. For not making wide change, we need an extra way to support
the association in Gem5ToTlm bridge async interface.

This change adds another map to record the association and clears when
the TLM transaction is completed.

Change-Id: I486441e813236ea2cabd1bd6cbb085b08d75ec8f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66054
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/systemc/tlm_bridge/gem5_to_tlm.cc
M src/systemc/tlm_bridge/gem5_to_tlm.hh
2 files changed, 39 insertions(+), 4 deletions(-)

Approvals:
  kokoro: Regressions pass
  Gabe Black: Looks good to me, approved; Looks good to me, approved




diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.cc  
b/src/systemc/tlm_bridge/gem5_to_tlm.cc

index a5eb9df..5159752 100644
--- a/src/systemc/tlm_bridge/gem5_to_tlm.cc
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.cc
@@ -231,10 +231,10 @@
 }
 }
 if (phase == tlm::BEGIN_RESP) {
-auto  = Gem5SystemC::Gem5Extension::getExtension(trans);
-auto packet = extension.getPacket();
+PacketPtr packet = packetMap[];

 sc_assert(!blockingResponse);
+sc_assert(packet);

 bool need_retry = false;

@@ -258,6 +258,7 @@
 sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
 socket->nb_transport_fw(trans, fw_phase, delay);
 // Release the transaction with all the extensions.
+packetMap.erase();
 trans.release();
 }
 }
@@ -433,11 +434,13 @@
 sc_assert(phase == tlm::BEGIN_REQ);
 // Accepted but is now blocking until END_REQ (exclusion rule).
 blockingRequest = trans;
+packetMap.emplace(trans, packet);
 } else if (status == tlm::TLM_UPDATED) {
 // The Timing annotation must be honored:
 sc_assert(phase == tlm::END_REQ || phase == tlm::BEGIN_RESP);
 // Accepted but is now blocking until END_REQ (exclusion rule).
 blockingRequest = trans;
+packetMap.emplace(trans, packet);
 auto cb = [this, trans, phase]() { pec(*trans, phase); };
 auto event = new EventFunctionWrapper(
 cb, "pec", true, getPriorityOfTlmPhase(phase));
@@ -477,8 +480,8 @@

 tlm::tlm_generic_payload *trans = blockingResponse;
 blockingResponse = nullptr;
-PacketPtr packet =
-Gem5SystemC::Gem5Extension::getExtension(trans).getPacket();
+PacketPtr packet = packetMap[blockingResponse];
+sc_assert(packet);

 bool need_retry = !bridgeResponsePort.sendTimingResp(packet);

@@ -488,6 +491,7 @@
 tlm::tlm_phase phase = tlm::END_RESP;
 socket->nb_transport_fw(*trans, phase, delay);
 // Release transaction with all the extensions
+packetMap.erase(trans);
 trans->release();
 }

diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.hh  
b/src/systemc/tlm_bridge/gem5_to_tlm.hh

index 23415b8..35d6ba3 100644
--- a/src/systemc/tlm_bridge/gem5_to_tlm.hh
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.hh
@@ -61,6 +61,7 @@

 #include 
 #include 
+#include 

 #include "mem/backdoor.hh"
 #include "mem/port.hh"
@@ -173,6 +174,12 @@
  */
 tlm::tlm_generic_payload *blockingResponse;

+/**
+ * A map to record the association between payload and packet. This  
helps us

+ * could get the correct packet when handling nonblocking interfaces.
+ */
+std::unordered_map  
packetMap;

+
 gem5::AddrRangeList addrRanges;

   protected:

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Gerrit-Change-Number: 66054
Gerrit-PatchSet: 4
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
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[gem5-dev] [S] Change in gem5/gem5[develop]: systemc: replace the deprecated std::iterator

2022-12-02 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66351?usp=email )



Change subject: systemc: replace the deprecated std::iterator
..

systemc: replace the deprecated std::iterator

std::iterator is deprecated in c++17. We can just declare the
required types for iterator traits directly without the helper.

Change-Id: I789e2c2b13e56cc391527686109df8b779474d09
---
M src/systemc/ext/utils/sc_vector.hh
1 file changed, 17 insertions(+), 9 deletions(-)



diff --git a/src/systemc/ext/utils/sc_vector.hh  
b/src/systemc/ext/utils/sc_vector.hh

index ef0d7dc..e11440f 100644
--- a/src/systemc/ext/utils/sc_vector.hh
+++ b/src/systemc/ext/utils/sc_vector.hh
@@ -49,6 +49,7 @@

 #include 

+#include 
 #include 
 #include 
 #include 
@@ -259,10 +260,7 @@

 template  >
-class sc_vector_iter :
-public std::iterator,
-private AccessPolicy
+class sc_vector_iter : private AccessPolicy
 {
   private:
 typedef Element ElementType;
@@ -282,8 +280,6 @@
 template 
 friend class sc_vector_iter;

-typedef std::iterator
-BaseType;
 typedef sc_vector_iter ThisType;
 typedef sc_vector VectorType;
 typedef std::vector StorageType;
@@ -315,9 +311,9 @@
 // Conforms to Random Access Iterator category.
 // See ISO/IEC 14882:2003(E), 24.1 [lib.iterator.requirements]

-typedef typename BaseType::difference_type difference_type;
-typedef typename BaseType::reference reference;
-typedef typename BaseType::pointer pointer;
+using difference_type = std::ptrdiff_t;
+using reference = typename AccessPolicy::Type &;
+using pointer = typename AccessPolicy::Type *;

 sc_vector_iter() : Policy(), it_() {}


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[gem5-dev] [S] Change in gem5/gem5[develop]: systemc: fix extension not found TlmToGem5 bridge response path

2022-11-30 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66053?usp=email )


Change subject: systemc: fix extension not found TlmToGem5 bridge response  
path

..

systemc: fix extension not found TlmToGem5 bridge response path

The gem5 packet has two ways to associate to the TLM payload. If the
request is initiated from gem5, they would be associated by TLM
extension. If the request is initiated from systemc, they would be
associated by SenderState. So current implementation apparently only
took care the request initiated from gem5 only. We need to update the
logic to take care both.

This change moves the response sync out of beginSendResp and sync it
before calling the function.

Change-Id: If415fbe33249b75e549086d9ca36eda3c20f7ec2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66053
Reviewed-by: Earl Ou 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M src/systemc/tlm_bridge/tlm_to_gem5.cc
1 file changed, 27 insertions(+), 10 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved
  Earl Ou: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.cc  
b/src/systemc/tlm_bridge/tlm_to_gem5.cc

index 468ea83..47a2fba 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.cc
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.cc
@@ -207,14 +207,6 @@
 TlmToGem5Bridge::sendBeginResp(tlm::tlm_generic_payload ,
  sc_core::sc_time )
 {
-Gem5SystemC::Gem5Extension *extension = nullptr;
-trans.get_extension(extension);
-panic_if(extension == nullptr,
- "Missing gem5 extension when sending BEGIN_RESP");
-auto pkt = extension->getPacket();
-
-setPayloadResponse(trans, pkt);
-
 tlm::tlm_phase phase = tlm::BEGIN_RESP;

 auto status = socket->nb_transport_bw(trans, phase, delay);
@@ -252,6 +244,7 @@
 sendEndReq(trans);
 if (!needsResponse) {
 auto delay = sc_core::SC_ZERO_TIME;
+setPayloadResponse(trans, pkt);
 sendBeginResp(trans, delay);
 }
 trans.release();
@@ -481,6 +474,8 @@
 sc_assert(tlmSenderState != nullptr);

 auto  = tlmSenderState->trans;
+setPayloadResponse(trans, pkt);
+sendBeginResp(trans, delay);

 Gem5SystemC::Gem5Extension *extension = nullptr;
 trans.get_extension(extension);
@@ -493,7 +488,6 @@
 if (extension == nullptr)
 destroyPacket(pkt);

-sendBeginResp(trans, delay);
 trans.release();

 return true;
@@ -512,12 +506,12 @@
 bool needsResponse = pendingPacket->needsResponse();
 if (bmp.sendTimingReq(pendingPacket)) {
 waitForRetry = false;
-pendingPacket = nullptr;

 auto  = *pendingRequest;
 sendEndReq(trans);
 if (!needsResponse) {
 auto delay = sc_core::SC_ZERO_TIME;
+setPayloadResponse(trans, pendingPacket);
 sendBeginResp(trans, delay);
 }
 trans.release();

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Gerrit-Change-Number: 66053
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
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[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: correct the Iris namespace for FastModel 11.19

2022-11-30 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66071?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: fastmodel: correct the Iris namespace for FastModel 11.19
..

fastmodel: correct the Iris namespace for FastModel 11.19

Change-Id: I3f899699ce27ffdc5bbed311fec9f38c62027a80
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66071
Reviewed-by: Earl Ou 
Tested-by: kokoro 
Maintainer: Bobby Bruce 
---
M src/arch/arm/fastmodel/iris/thread_context.cc
1 file changed, 16 insertions(+), 3 deletions(-)

Approvals:
  Earl Ou: Looks good to me, approved
  kokoro: Regressions pass
  Bobby Bruce: Looks good to me, approved




diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc  
b/src/arch/arm/fastmodel/iris/thread_context.cc

index b12536d..45e020d 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -441,9 +441,9 @@
 ThreadContext::readMem(
 iris::MemorySpaceId space, Addr addr, void *p, size_t size)
 {
-iris::r0master::MemoryReadResult r;
+iris::MemoryReadResult r;
 auto err = call().memory_read(_instId, r, space, addr, 1, size);
-panic_if(err != iris::r0master::E_ok, "readMem failed.");
+panic_if(err != iris::E_ok, "readMem failed.");
 std::memcpy(p, r.data.data(), size);
 }

@@ -455,7 +455,7 @@
 std::memcpy(data.data(), p, size);
 iris::MemoryWriteResult r;
 auto err = call().memory_write(_instId, r, space, addr, 1, size, data);
-panic_if(err != iris::r0master::E_ok, "writeMem failed.");
+panic_if(err != iris::E_ok, "writeMem failed.");
 }

 bool

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Gerrit-Change-Id: I3f899699ce27ffdc5bbed311fec9f38c62027a80
Gerrit-Change-Number: 66071
Gerrit-PatchSet: 3
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Wei-Han Chen 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: correct the Iris namespace for FastModel 11.19

2022-11-24 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66071?usp=email )



Change subject: fastmodel: correct the Iris namespace for FastModel 11.19
..

fastmodel: correct the Iris namespace for FastModel 11.19

Change-Id: I3f899699ce27ffdc5bbed311fec9f38c62027a80
---
M src/arch/arm/fastmodel/iris/thread_context.cc
1 file changed, 12 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc  
b/src/arch/arm/fastmodel/iris/thread_context.cc

index b12536d..45e020d 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -441,9 +441,9 @@
 ThreadContext::readMem(
 iris::MemorySpaceId space, Addr addr, void *p, size_t size)
 {
-iris::r0master::MemoryReadResult r;
+iris::MemoryReadResult r;
 auto err = call().memory_read(_instId, r, space, addr, 1, size);
-panic_if(err != iris::r0master::E_ok, "readMem failed.");
+panic_if(err != iris::E_ok, "readMem failed.");
 std::memcpy(p, r.data.data(), size);
 }

@@ -455,7 +455,7 @@
 std::memcpy(data.data(), p, size);
 iris::MemoryWriteResult r;
 auto err = call().memory_write(_instId, r, space, addr, 1, size, data);
-panic_if(err != iris::r0master::E_ok, "writeMem failed.");
+panic_if(err != iris::E_ok, "writeMem failed.");
 }

 bool

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[gem5-dev] [S] Change in gem5/gem5[develop]: systemc: fix extension not found TlmToGem5 bridge response path

2022-11-23 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66053?usp=email )



Change subject: systemc: fix extension not found TlmToGem5 bridge response  
path

..

systemc: fix extension not found TlmToGem5 bridge response path

The gem5 packet has two ways to associate to the TLM payload. If the
request is initiated from gem5, they would be associated by TLM
extension. If the request is initiated from systemc, they would be
associated by SenderState. So current implementation apparently only
took care the request initiated from gem5 only. We need to update the
logic to take care both.

This change moves the response sync out of beginSendResp and sync it
before calling the function.

Change-Id: If415fbe33249b75e549086d9ca36eda3c20f7ec2
---
M src/systemc/tlm_bridge/tlm_to_gem5.cc
1 file changed, 23 insertions(+), 10 deletions(-)



diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.cc  
b/src/systemc/tlm_bridge/tlm_to_gem5.cc

index 468ea83..47a2fba 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.cc
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.cc
@@ -207,14 +207,6 @@
 TlmToGem5Bridge::sendBeginResp(tlm::tlm_generic_payload ,
  sc_core::sc_time )
 {
-Gem5SystemC::Gem5Extension *extension = nullptr;
-trans.get_extension(extension);
-panic_if(extension == nullptr,
- "Missing gem5 extension when sending BEGIN_RESP");
-auto pkt = extension->getPacket();
-
-setPayloadResponse(trans, pkt);
-
 tlm::tlm_phase phase = tlm::BEGIN_RESP;

 auto status = socket->nb_transport_bw(trans, phase, delay);
@@ -252,6 +244,7 @@
 sendEndReq(trans);
 if (!needsResponse) {
 auto delay = sc_core::SC_ZERO_TIME;
+setPayloadResponse(trans, pkt);
 sendBeginResp(trans, delay);
 }
 trans.release();
@@ -481,6 +474,8 @@
 sc_assert(tlmSenderState != nullptr);

 auto  = tlmSenderState->trans;
+setPayloadResponse(trans, pkt);
+sendBeginResp(trans, delay);

 Gem5SystemC::Gem5Extension *extension = nullptr;
 trans.get_extension(extension);
@@ -493,7 +488,6 @@
 if (extension == nullptr)
 destroyPacket(pkt);

-sendBeginResp(trans, delay);
 trans.release();

 return true;
@@ -512,12 +506,12 @@
 bool needsResponse = pendingPacket->needsResponse();
 if (bmp.sendTimingReq(pendingPacket)) {
 waitForRetry = false;
-pendingPacket = nullptr;

 auto  = *pendingRequest;
 sendEndReq(trans);
 if (!needsResponse) {
 auto delay = sc_core::SC_ZERO_TIME;
+setPayloadResponse(trans, pendingPacket);
 sendBeginResp(trans, delay);
 }
 trans.release();

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If415fbe33249b75e549086d9ca36eda3c20f7ec2
Gerrit-Change-Number: 66053
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang 
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: systemc: fix the payload and packet association in Gem5ToTlm bridge

2022-11-23 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66054?usp=email )



Change subject: systemc: fix the payload and packet association in  
Gem5ToTlm bridge

..

systemc: fix the payload and packet association in Gem5ToTlm bridge

If a request is initiated by systemc, passed through TlmToGem5 bridge
and Gem5ToTlm bridge, it wouldn't have the systemc extension about the
association. This feature is also used in TlmToGem5 bridge to detect if
the packet is allocated in the current instance in async interface. In
that case, we would lose the association in the Gem5ToTlm bridge async
interface. For not making wide change, we need an extra way to support
the association in Gem5ToTlm bridge async interface.

This change adds another map to record the association and clears when
the TLM transaction is completed.

Change-Id: I486441e813236ea2cabd1bd6cbb085b08d75ec8f
---
M src/systemc/tlm_bridge/gem5_to_tlm.cc
M src/systemc/tlm_bridge/gem5_to_tlm.hh
2 files changed, 35 insertions(+), 4 deletions(-)



diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.cc  
b/src/systemc/tlm_bridge/gem5_to_tlm.cc

index a5eb9df..5159752 100644
--- a/src/systemc/tlm_bridge/gem5_to_tlm.cc
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.cc
@@ -231,10 +231,10 @@
 }
 }
 if (phase == tlm::BEGIN_RESP) {
-auto  = Gem5SystemC::Gem5Extension::getExtension(trans);
-auto packet = extension.getPacket();
+PacketPtr packet = packetMap[];

 sc_assert(!blockingResponse);
+sc_assert(packet);

 bool need_retry = false;

@@ -258,6 +258,7 @@
 sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
 socket->nb_transport_fw(trans, fw_phase, delay);
 // Release the transaction with all the extensions.
+packetMap.erase();
 trans.release();
 }
 }
@@ -433,11 +434,13 @@
 sc_assert(phase == tlm::BEGIN_REQ);
 // Accepted but is now blocking until END_REQ (exclusion rule).
 blockingRequest = trans;
+packetMap.emplace(trans, packet);
 } else if (status == tlm::TLM_UPDATED) {
 // The Timing annotation must be honored:
 sc_assert(phase == tlm::END_REQ || phase == tlm::BEGIN_RESP);
 // Accepted but is now blocking until END_REQ (exclusion rule).
 blockingRequest = trans;
+packetMap.emplace(trans, packet);
 auto cb = [this, trans, phase]() { pec(*trans, phase); };
 auto event = new EventFunctionWrapper(
 cb, "pec", true, getPriorityOfTlmPhase(phase));
@@ -477,8 +480,8 @@

 tlm::tlm_generic_payload *trans = blockingResponse;
 blockingResponse = nullptr;
-PacketPtr packet =
-Gem5SystemC::Gem5Extension::getExtension(trans).getPacket();
+PacketPtr packet = packetMap[blockingResponse];
+sc_assert(packet);

 bool need_retry = !bridgeResponsePort.sendTimingResp(packet);

@@ -488,6 +491,7 @@
 tlm::tlm_phase phase = tlm::END_RESP;
 socket->nb_transport_fw(*trans, phase, delay);
 // Release transaction with all the extensions
+packetMap.erase(trans);
 trans->release();
 }

diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.hh  
b/src/systemc/tlm_bridge/gem5_to_tlm.hh

index 23415b8..35d6ba3 100644
--- a/src/systemc/tlm_bridge/gem5_to_tlm.hh
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.hh
@@ -61,6 +61,7 @@

 #include 
 #include 
+#include 

 #include "mem/backdoor.hh"
 #include "mem/port.hh"
@@ -173,6 +174,12 @@
  */
 tlm::tlm_generic_payload *blockingResponse;

+/**
+ * A map to record the association between payload and packet. This  
helps us

+ * could get the correct packet when handling nonblocking interfaces.
+ */
+std::unordered_map  
packetMap;

+
 gem5::AddrRangeList addrRanges;

   protected:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I486441e813236ea2cabd1bd6cbb085b08d75ec8f
Gerrit-Change-Number: 66054
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang 
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: fastmodel: CortexR52 export standbywfi signal

2022-11-21 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65534?usp=email )


Change subject: fastmodel: CortexR52 export standbywfi signal
..

fastmodel: CortexR52 export standbywfi signal

Change-Id: Ic9ed9a3e35f068e151725d36e7fff391013ff5d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65534
Reviewed-by: Gabe Black 
Tested-by: kokoro 
Maintainer: Gabe Black 
---
M src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
M src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
M src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
M src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
M src/arch/arm/fastmodel/common/signal_receiver.hh
9 files changed, 85 insertions(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py  
b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py

index 4970ae2..1e267f0 100644
--- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
+++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
@@ -31,7 +31,7 @@
 from m5.objects.ArmISA import ArmISA
 from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
 from m5.objects.ResetPort import ResetResponsePort
-from m5.objects.IntPin import IntSinkPin, VectorIntSinkPin
+from m5.objects.IntPin import IntSourcePin, IntSinkPin, VectorIntSinkPin
 from m5.objects.Iris import IrisBaseCPU
 from m5.objects.SystemC import SystemC_ScModule

@@ -56,6 +56,9 @@
 "processor logic, including debug logic."
 )
 halt = IntSinkPin("Raising this signal will put the core into halt  
mode.")

+standbywfi = IntSourcePin(
+"This signal indicates if a core is in WFI state."
+)

 CFGEND = Param.Bool(
 False,
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc  
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc

index be83082..9dfe7a5 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -92,6 +92,10 @@
 // Since PPIs are indexed both by core and by number, modify the  
name

 // to hold the core number.
 return evs->gem5_getPort(csprintf("%s_%d", if_name, num), idx);
+} else if (if_name == "standbywfi") {
+// Since standbywfi is indexed by fanout, modify the name to hold  
the

+// core number.
+return evs->gem5_getPort(csprintf("%s_%d", if_name, num), idx);
 } else if (if_name == "amba" || if_name == "llpp" || if_name  
== "flash" ||

if_name == "core_reset" || if_name == "poweron_reset" ||
if_name == "halt") {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc  
b/src/arch/arm/fastmodel/CortexR52/evs.cc

index 6887c6c..734323e 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -79,6 +79,7 @@
 core_reset(name + ".core_reset", 0),
 poweron_reset(name + ".poweron_reset", 0),
 halt(name + ".halt", 0),
+standbywfi(name + ".standbywfi"),
 cfgvectable((name + "cfgvectable").c_str())
 {
 for (int i = 0; i < Evs::PpiCount; i++) {
@@ -88,6 +89,7 @@
 core_reset.signal_out.bind(evs->core_reset[cpu]);
 poweron_reset.signal_out.bind(evs->poweron_reset[cpu]);
 halt.signal_out.bind(evs->halt[cpu]);
+evs->standbywfi[cpu].bind(standbywfi.signal_in);
 cfgvectable.bind(evs->cfgvectable[cpu]);
 }

@@ -161,6 +163,14 @@
 panic("Couldn't find CPU number in %s.", if_name);
 }
 return *this->corePins.at(cpu)->ppis.at(idx);
+} else if (if_name.substr(0, 10) == "standbywfi") {
+int cpu;
+try {
+cpu = std::stoi(if_name.substr(11));
+} catch (const std::invalid_argument ) {
+panic("Couldn't find CPU number in %s.", if_name);
+}
+return this->corePins.at(cpu)->standbywfi.getSignalOut(idx);
 } else {
 return Base::gem5_getPort(if_name, idx);
 }
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh  
b/src/arch/arm/fastmodel/CortexR52/evs.hh

index 535d678..02ef1ae 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -110,6 +110,7 @@
 SignalSender core_reset;
 SignalSender poweron_reset;
 SignalSender halt;
+SignalReceiverInt standbywfi;

 SignalInitiator cfgvectable;
 };
diff --git a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa  
b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa

index 2a7299d..2738ba2 100644
--- a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
@@ -53,6 +53,9 @@
 self.dbg_reset => core.presetdbg;

[gem5-dev] [M] Change in gem5/gem5[develop]: fastmodel: CortexR52 export standbywfi signal

2022-11-16 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65534?usp=email )



Change subject: fastmodel: CortexR52 export standbywfi signal
..

fastmodel: CortexR52 export standbywfi signal

Change-Id: Ic9ed9a3e35f068e151725d36e7fff391013ff5d1
---
M src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
M src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
M src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
M src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
8 files changed, 53 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py  
b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py

index 4970ae2..1e267f0 100644
--- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
+++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
@@ -31,7 +31,7 @@
 from m5.objects.ArmISA import ArmISA
 from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
 from m5.objects.ResetPort import ResetResponsePort
-from m5.objects.IntPin import IntSinkPin, VectorIntSinkPin
+from m5.objects.IntPin import IntSourcePin, IntSinkPin, VectorIntSinkPin
 from m5.objects.Iris import IrisBaseCPU
 from m5.objects.SystemC import SystemC_ScModule

@@ -56,6 +56,9 @@
 "processor logic, including debug logic."
 )
 halt = IntSinkPin("Raising this signal will put the core into halt  
mode.")

+standbywfi = IntSourcePin(
+"This signal indicates if a core is in WFI state."
+)

 CFGEND = Param.Bool(
 False,
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc  
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc

index be83082..fdfce2b 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -99,6 +99,8 @@
 // index. Also verify that that index is not being used.
 assert(idx == InvalidPortID);
 return evs->gem5_getPort(if_name, num);
+} else if (if_name == "standbywfi") {
+return evs->gem5_getPort(if_name, num);
 } else {
 return SimObject::getPort(if_name, idx);
 }
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc  
b/src/arch/arm/fastmodel/CortexR52/evs.cc

index 6887c6c..c18c58c 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -79,6 +79,7 @@
 core_reset(name + ".core_reset", 0),
 poweron_reset(name + ".poweron_reset", 0),
 halt(name + ".halt", 0),
+standbywfi(name + ".standbywfi"),
 cfgvectable((name + "cfgvectable").c_str())
 {
 for (int i = 0; i < Evs::PpiCount; i++) {
@@ -88,10 +89,10 @@
 core_reset.signal_out.bind(evs->core_reset[cpu]);
 poweron_reset.signal_out.bind(evs->poweron_reset[cpu]);
 halt.signal_out.bind(evs->halt[cpu]);
+evs->standbywfi[cpu].bind(standbywfi.signal_in);
 cfgvectable.bind(evs->cfgvectable[cpu]);
 }

-
 template 
 ScxEvsCortexR52::ScxEvsCortexR52(
 const sc_core::sc_module_name _name, const Params ) :
@@ -143,6 +144,8 @@
 return this->corePins.at(idx)->poweron_reset;
 } else if (if_name == "halt") {
 return this->corePins.at(idx)->halt;
+} else if (if_name == "standbywfi") {
+return this->corePins.at(idx)->standbywfi.signal_out;
 } else if (if_name == "ext_slave") {
 return this->ext_slave;
 } else if (if_name == "top_reset") {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh  
b/src/arch/arm/fastmodel/CortexR52/evs.hh

index 535d678..5f9a117 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -83,6 +83,23 @@
 template 
 using SignalInitiator = amba_pv::signal_master_port;

+class SignalReceiverInt : public SignalReceiver
+{
+  public:
+IntSourcePin signal_out;
+
+explicit SignalReceiverInt(const std::string )
+: SignalReceiver(name),
+  signal_out(name + ".signal_out", 0, this)
+{
+onChange([this](bool status) {
+if (!signal_out.isConnected())
+return;
+status ? signal_out.raise() : signal_out.lower();
+});
+}
+};
+
 std::string name;
 Evs *evs;
 int cpu;
@@ -110,6 +127,7 @@
 SignalSender core_reset;
 SignalSender poweron_reset;
 SignalSender halt;
+SignalReceiverInt standbywfi;

 SignalInitiator cfgvectable;
 };
diff --git a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa  
b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa

index 2a7299d..2738ba2 100644
--- a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
+++

[gem5-dev] [XL] Change in gem5/gem5[develop]: ext: upgrade to googletest 1.12.0

2022-11-02 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65211?usp=email )


Change subject: ext: upgrade to googletest 1.12.0
..

ext: upgrade to googletest 1.12.0

Upgrade googletest to 1.12.0
upstream commit: 15460959cbbfa20e66ef0b5ab497367e47fc0a04

sha1sum e1e4ab7f4add6d403c37970a83a596b3081077d6 generated by command:
find . -type f ! -name SConscript ! -path "./.*" -print0 \
| sort -z | xargs -0 sha1sum | sha1sum

This upgrade is mainly for solving the infinite-recursion warning from
g++12

ext/googletest/googlemock/include/gmock/internal/gmock-internal-utils.h: In  
function ‘testing::internal::Invalid()gem5::Port&’:
ext/googletest/googlemock/include/gmock/internal/gmock-internal-utils.h:296:10:  
error:  
infinite recursion detected [-Werror=infinite-recursion]

  296 | inline T Invalid() {
  |  ^~~
ext/googletest/googlemock/include/gmock/internal/gmock-internal-utils.h:301:20:  
note:  
recursive call

  301 |   return Invalid();
  |  ~~^~
ext/googletest/googlemock/include/gmock/internal/gmock-internal-utils.h: In  
function ‘testing::internal::Invalidstd::char_traits, std::allocator >  
const&>()std::__cxx11::basic_string,  
std::allocator > const&’:
ext/googletest/googlemock/include/gmock/internal/gmock-internal-utils.h:296:10:  
error:  
infinite recursion detected [-Werror=infinite-recursion]

  296 | inline T Invalid() {
  |  ^~~
ext/googletest/googlemock/include/gmock/internal/gmock-internal-utils.h:301:20:  
note:  
recursive call

  301 |   return Invalid();
  |  ~~^~

Change-Id: I14594f7bc148281784043b3f715173316e6d62d4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65211
Maintainer: Gabe Black 
Reviewed-by: Gabe Black 
Tested-by: kokoro 
---
M ext/googletest/BUILD.bazel
M ext/googletest/CMakeLists.txt
M ext/googletest/CONTRIBUTING.md
M ext/googletest/CONTRIBUTORS
M ext/googletest/README.md
M ext/googletest/WORKSPACE
M ext/googletest/ci/linux-presubmit.sh
M ext/googletest/docs/advanced.md
M ext/googletest/docs/faq.md
M ext/googletest/docs/gmock_cheat_sheet.md
M ext/googletest/docs/gmock_cook_book.md
M ext/googletest/docs/gmock_faq.md
M ext/googletest/docs/gmock_for_dummies.md
M ext/googletest/docs/primer.md
M ext/googletest/docs/quickstart-bazel.md
M ext/googletest/docs/reference/matchers.md
M ext/googletest/docs/reference/mocking.md
M ext/googletest/docs/reference/testing.md
M ext/googletest/googlemock/CMakeLists.txt
M ext/googletest/googlemock/README.md
M ext/googletest/googlemock/include/gmock/gmock-actions.h
M ext/googletest/googlemock/include/gmock/gmock-cardinalities.h
M ext/googletest/googlemock/include/gmock/gmock-function-mocker.h
M ext/googletest/googlemock/include/gmock/gmock-matchers.h
M ext/googletest/googlemock/include/gmock/gmock-more-actions.h
M ext/googletest/googlemock/include/gmock/gmock-more-matchers.h
M ext/googletest/googlemock/include/gmock/gmock-nice-strict.h
M ext/googletest/googlemock/include/gmock/gmock-spec-builders.h
M ext/googletest/googlemock/include/gmock/gmock.h
M ext/googletest/googlemock/include/gmock/internal/custom/README.md
M  
ext/googletest/googlemock/include/gmock/internal/custom/gmock-generated-actions.h

M ext/googletest/googlemock/include/gmock/internal/custom/gmock-matchers.h
M ext/googletest/googlemock/include/gmock/internal/custom/gmock-port.h
M ext/googletest/googlemock/include/gmock/internal/gmock-internal-utils.h
M ext/googletest/googlemock/include/gmock/internal/gmock-port.h
D ext/googletest/googlemock/scripts/README.md
D ext/googletest/googlemock/scripts/fuse_gmock_files.py
D ext/googletest/googlemock/scripts/generator/LICENSE
D ext/googletest/googlemock/scripts/generator/README
D ext/googletest/googlemock/scripts/generator/README.cppclean
D ext/googletest/googlemock/scripts/generator/cpp/__init__.py
D ext/googletest/googlemock/scripts/generator/cpp/ast.py
D ext/googletest/googlemock/scripts/generator/cpp/gmock_class.py
D ext/googletest/googlemock/scripts/generator/cpp/gmock_class_test.py
D ext/googletest/googlemock/scripts/generator/cpp/keywords.py
D ext/googletest/googlemock/scripts/generator/cpp/tokenize.py
D ext/googletest/googlemock/scripts/generator/cpp/utils.py
D ext/googletest/googlemock/scripts/generator/gmock_gen.py
M ext/googletest/googlemock/src/gmock-cardinalities.cc
M ext/googletest/googlemock/src/gmock-internal-utils.cc
M ext/googletest/googlemock/src/gmock-matchers.cc
M ext/googletest/googlemock/src/gmock-spec-builders.cc
M ext/googletest/googlemock/src/gmock.cc
M ext/googletest/googlemock/src/gmock_main.cc
M ext/googletest/googlemock/test/BUILD.bazel
M ext/googletest/googlemock/test/gmock-actions_test.cc
M ext/googletest/googlemock/test/gmock-cardinalities_test.cc
M ext/googletest/googlemock/test/gmock-function-mocker_test.cc
M ext/googletest/googlemock/test/gmock-internal-utils_test.cc
A

[gem5-dev] [XL] Change in gem5/gem5[develop]: ext: upgrade to googletest 1.12.0

2022-11-02 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65211?usp=email )



Change subject: ext: upgrade to googletest 1.12.0
..

ext: upgrade to googletest 1.12.0

Upgrade googletest to 1.12.0
upstream commit: 15460959cbbfa20e66ef0b5ab497367e47fc0a04

sha1sum e1e4ab7f4add6d403c37970a83a596b3081077d6 generated by command:
find . -type f ! -name SConscript ! -path "./.*" -print0 \
| sort -z | xargs -0 sha1sum | sha1sum

This upgrade is mainly for solving the infinite-recursion warning from
g++12

ext/googletest/googlemock/include/gmock/internal/gmock-internal-utils.h: In  
function ‘testing::internal::Invalid()gem5::Port&’:
ext/googletest/googlemock/include/gmock/internal/gmock-internal-utils.h:296:10:  
error:  
infinite recursion detected [-Werror=infinite-recursion]

  296 | inline T Invalid() {
  |  ^~~
ext/googletest/googlemock/include/gmock/internal/gmock-internal-utils.h:301:20:  
note:  
recursive call

  301 |   return Invalid();
  |  ~~^~
ext/googletest/googlemock/include/gmock/internal/gmock-internal-utils.h: In  
function ‘testing::internal::Invalidstd::char_traits, std::allocator >  
const&>()std::__cxx11::basic_string,  
std::allocator > const&’:
ext/googletest/googlemock/include/gmock/internal/gmock-internal-utils.h:296:10:  
error:  
infinite recursion detected [-Werror=infinite-recursion]

  296 | inline T Invalid() {
  |  ^~~
ext/googletest/googlemock/include/gmock/internal/gmock-internal-utils.h:301:20:  
note:  
recursive call

  301 |   return Invalid();
  |  ~~^~

Change-Id: I14594f7bc148281784043b3f715173316e6d62d4
---
M ext/googletest/BUILD.bazel
M ext/googletest/CMakeLists.txt
M ext/googletest/CONTRIBUTING.md
M ext/googletest/CONTRIBUTORS
M ext/googletest/README.md
M ext/googletest/WORKSPACE
M ext/googletest/ci/linux-presubmit.sh
M ext/googletest/docs/advanced.md
M ext/googletest/docs/faq.md
M ext/googletest/docs/gmock_cheat_sheet.md
M ext/googletest/docs/gmock_cook_book.md
M ext/googletest/docs/gmock_faq.md
M ext/googletest/docs/gmock_for_dummies.md
M ext/googletest/docs/primer.md
M ext/googletest/docs/quickstart-bazel.md
M ext/googletest/docs/reference/matchers.md
M ext/googletest/docs/reference/mocking.md
M ext/googletest/docs/reference/testing.md
M ext/googletest/googlemock/CMakeLists.txt
M ext/googletest/googlemock/README.md
M ext/googletest/googlemock/include/gmock/gmock-actions.h
M ext/googletest/googlemock/include/gmock/gmock-cardinalities.h
M ext/googletest/googlemock/include/gmock/gmock-function-mocker.h
M ext/googletest/googlemock/include/gmock/gmock-matchers.h
M ext/googletest/googlemock/include/gmock/gmock-more-actions.h
M ext/googletest/googlemock/include/gmock/gmock-more-matchers.h
M ext/googletest/googlemock/include/gmock/gmock-nice-strict.h
M ext/googletest/googlemock/include/gmock/gmock-spec-builders.h
M ext/googletest/googlemock/include/gmock/gmock.h
M ext/googletest/googlemock/include/gmock/internal/custom/README.md
M  
ext/googletest/googlemock/include/gmock/internal/custom/gmock-generated-actions.h

M ext/googletest/googlemock/include/gmock/internal/custom/gmock-matchers.h
M ext/googletest/googlemock/include/gmock/internal/custom/gmock-port.h
M ext/googletest/googlemock/include/gmock/internal/gmock-internal-utils.h
M ext/googletest/googlemock/include/gmock/internal/gmock-port.h
D ext/googletest/googlemock/scripts/README.md
D ext/googletest/googlemock/scripts/fuse_gmock_files.py
D ext/googletest/googlemock/scripts/generator/LICENSE
D ext/googletest/googlemock/scripts/generator/README
D ext/googletest/googlemock/scripts/generator/README.cppclean
D ext/googletest/googlemock/scripts/generator/cpp/__init__.py
D ext/googletest/googlemock/scripts/generator/cpp/ast.py
D ext/googletest/googlemock/scripts/generator/cpp/gmock_class.py
D ext/googletest/googlemock/scripts/generator/cpp/gmock_class_test.py
D ext/googletest/googlemock/scripts/generator/cpp/keywords.py
D ext/googletest/googlemock/scripts/generator/cpp/tokenize.py
D ext/googletest/googlemock/scripts/generator/cpp/utils.py
D ext/googletest/googlemock/scripts/generator/gmock_gen.py
M ext/googletest/googlemock/src/gmock-cardinalities.cc
M ext/googletest/googlemock/src/gmock-internal-utils.cc
M ext/googletest/googlemock/src/gmock-matchers.cc
M ext/googletest/googlemock/src/gmock-spec-builders.cc
M ext/googletest/googlemock/src/gmock.cc
M ext/googletest/googlemock/src/gmock_main.cc
M ext/googletest/googlemock/test/BUILD.bazel
M ext/googletest/googlemock/test/gmock-actions_test.cc
M ext/googletest/googlemock/test/gmock-cardinalities_test.cc
M ext/googletest/googlemock/test/gmock-function-mocker_test.cc
M ext/googletest/googlemock/test/gmock-internal-utils_test.cc
A ext/googletest/googlemock/test/gmock-matchers-arithmetic_test.cc
A ext/googletest/googlemock/test/gmock-matchers-comparisons_test.cc
A

[gem5-dev] [M] Change in gem5/gem5[develop]: systemc: sync the response error between gem5 packet and tlm payload

2022-10-31 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64591?usp=email )


Change subject: systemc: sync the response error between gem5 packet and  
tlm payload

..

systemc: sync the response error between gem5 packet and tlm payload

For now we don't return the correct error status to the upstream of the
protocol conversion bridge. This prevents from the requestor to
distinguish if the response is good or not. This change fixes the issue.

Change-Id: Iec2a388b50fb1bd4fd97ece19e9061138b0b0a1f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64591
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Reviewed-by: Earl Ou 
Tested-by: kokoro 
---
M src/systemc/tlm_bridge/gem5_to_tlm.cc
M src/systemc/tlm_bridge/tlm_to_gem5.cc
M src/systemc/tlm_bridge/tlm_to_gem5.hh
3 files changed, 63 insertions(+), 24 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Earl Ou: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.cc  
b/src/systemc/tlm_bridge/gem5_to_tlm.cc

index 07e4821..10f7d1a 100644
--- a/src/systemc/tlm_bridge/gem5_to_tlm.cc
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.cc
@@ -194,6 +194,24 @@
 return trans;
 }

+void
+setPacketResponse(PacketPtr pkt, tlm::tlm_generic_payload )
+{
+pkt->makeResponse();
+
+auto resp = trans.get_response_status();
+switch (resp) {
+  case tlm::TLM_OK_RESPONSE:
+break;
+  case tlm::TLM_COMMAND_ERROR_RESPONSE:
+pkt->setBadCommand();
+break;
+  default:
+pkt->setBadAddress();
+break;
+}
+}
+
 template 
 void
 Gem5ToTlmBridge::pec(
@@ -225,7 +243,7 @@
 // we make a response packet before sending it back to the  
initiator

 // side gem5 module.
 if (packet->needsResponse()) {
-packet->makeResponse();
+setPacketResponse(packet, trans);
 }
 if (packet->isResponse()) {
 need_retry = !bridgeResponsePort.sendTimingResp(packet);
@@ -296,7 +314,7 @@
 }

 if (packet->needsResponse())
-packet->makeResponse();
+setPacketResponse(packet, *trans);

 trans->release();

@@ -328,6 +346,7 @@
 backdoor = getBackdoor(*trans);
 }

+// Always set success response in Backdoor case.
 if (packet->needsResponse())
 packet->makeResponse();

diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.cc  
b/src/systemc/tlm_bridge/tlm_to_gem5.cc

index 7aec14f..703e118 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.cc
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.cc
@@ -178,6 +178,18 @@
 return std::make_pair(pkt, true);
 }

+void
+setPayloadResponse(tlm::tlm_generic_payload , PacketPtr pkt)
+{
+if (!pkt->isError()) {
+trans.set_response_status(tlm::TLM_OK_RESPONSE);
+} else if (pkt->isRead() || pkt->isWrite()) {
+trans.set_response_status(tlm::TLM_COMMAND_ERROR_RESPONSE);
+} else {
+trans.set_response_status(tlm::TLM_ADDRESS_ERROR_RESPONSE);
+}
+}
+
 template 
 void
 TlmToGem5Bridge::sendEndReq(tlm::tlm_generic_payload )
@@ -195,9 +207,15 @@
 TlmToGem5Bridge::sendBeginResp(tlm::tlm_generic_payload ,
  sc_core::sc_time )
 {
-tlm::tlm_phase phase = tlm::BEGIN_RESP;
+Gem5SystemC::Gem5Extension *extension = nullptr;
+trans.get_extension(extension);
+panic_if(extension == nullptr,
+ "Missing gem5 extension when sending BEGIN_RESP");
+auto pkt = extension->getPacket();

-trans.set_response_status(tlm::TLM_OK_RESPONSE);
+setPayloadResponse(trans, pkt);
+
+tlm::tlm_phase phase = tlm::BEGIN_RESP;

 auto status = socket->nb_transport_bw(trans, phase, delay);

@@ -252,8 +270,6 @@

 responseInProgress = false;

-checkTransaction(trans);
-
 if (needToSendRetry) {
 bmp.sendRetryResp();
 needToSendRetry = false;
@@ -269,18 +285,6 @@

 template 
 void
-TlmToGem5Bridge::checkTransaction(tlm::tlm_generic_payload  
)

-{
-if (trans.is_response_error()) {
-std::stringstream ss;
-ss << "Transaction returned with error, response status = "
-   << trans.get_response_string();
-SC_REPORT_ERROR("TLM-2", ss.str().c_str());
-}
-}
-
-template 
-void
 TlmToGem5Bridge::invalidateDmi(const gem5::MemBackdoor )
 {
 socket->invalidate_direct_mem_ptr(
@@ -362,10 +366,10 @@
 // clean up
 delete senderState;

+setPayloadResponse(trans, pkt);
+
 if (pkt_created)
 destroyPacket(pkt);
-
-trans.set_response_status(tlm::TLM_OK_RESPONSE);
 }

 template 
@@ -437,11 +441,11 @@
 // clean up
 delete senderState;

+setPayloadResponse(trans, pkt);
+
 if (pkt_created)
 destroyPacket(pkt);

-trans.set_response_status(tlm::TLM_OK_RESPONSE);
-
 return

[gem5-dev] [S] Change in gem5/gem5[develop]: mem: introduce bad command error to packet commands

2022-10-31 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64872?usp=email )


Change subject: mem: introduce bad command error to packet commands
..

mem: introduce bad command error to packet commands

The bad command is used to model a request is sent to target but the
target cannot make it. The bad command error is designed to model AXI
SLVERR.

Change-Id: I8142df36a5ed3e461493796266821a2b30a3415e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64872
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Earl Ou 
---
M src/mem/packet.cc
M src/mem/packet.hh
2 files changed, 37 insertions(+), 0 deletions(-)

Approvals:
  Earl Ou: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  kokoro: Regressions pass




diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index 3cd1bb9..31dc330 100644
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -214,6 +214,10 @@
 { {IsResponse, IsError}, InvalidCmd, "InvalidDestError" },
 /* BadAddressError   -- memory address invalid */
 { {IsResponse, IsError}, InvalidCmd, "BadAddressError" },
+/* ReadError -- packet dest unable to fulfill read command */
+{ {IsRead, IsResponse, IsError}, InvalidCmd, "ReadError" },
+/* WriteError -- packet dest unable to fulfill write command */
+{ {IsWrite, IsResponse, IsError}, InvalidCmd, "WriteError" },
 /* FunctionalReadError */
 { {IsRead, IsResponse, IsError}, InvalidCmd, "FunctionalReadError" },
 /* FunctionalWriteError */
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 7d32634..9238dbe 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -133,6 +133,8 @@
 // compatibility
 InvalidDestError,  // packet dest field invalid
 BadAddressError,   // memory address invalid
+ReadError, // packet dest unable to fulfill read command
+WriteError,// packet dest unable to fulfill write command
 FunctionalReadError, // unable to fulfill functional read
 FunctionalWriteError, // unable to fulfill functional write
 // Fake simulator-only commands
@@ -785,6 +787,19 @@
 cmd = MemCmd::BadAddressError;
 }

+// Command error conditions. The request is sent to target but the  
target

+// cannot make it.
+void
+setBadCommand()
+{
+assert(isResponse());
+if (isWrite()) {
+cmd = MemCmd::WriteError;
+} else {
+cmd = MemCmd::ReadError;
+}
+}
+
 void copyError(Packet *pkt) { assert(pkt->isError()); cmd = pkt->cmd; }

 Addr getAddr() const { assert(flags.isSet(VALID_ADDR)); return addr; }

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/64872?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8142df36a5ed3e461493796266821a2b30a3415e
Gerrit-Change-Number: 64872
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Yan Lee 
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: dev: Add a special reset interface to consolidate reset logic

2022-04-26 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58810 )


Change subject: dev: Add a special reset interface to consolidate reset  
logic

..

dev: Add a special reset interface to consolidate reset logic

How to reset a model correctly is very different between models. Take
cpu models for instance, they have different reset pins for different
parts(typically one for each core, one for shared component, one for
debug interface). To make users more easily to reset the model, here we
want to introduce a special reset port. By implementing the port, users
can simply request a whole reset to the model. If users want to do
partial resets, users still can access the raw pins to achieve what they
want.

Change-Id: I746121d16441e021dc3392aeae1a6d9fa33d637a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58810
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
A src/dev/ResetPort.py
M src/dev/SConscript
A src/dev/reset_port.cc
A src/dev/reset_port.hh
4 files changed, 200 insertions(+), 0 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/ResetPort.py b/src/dev/ResetPort.py
new file mode 100644
index 000..d7140c5
--- /dev/null
+++ b/src/dev/ResetPort.py
@@ -0,0 +1,47 @@
+# Copyright 2022 Google, Inc.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.params import Port, VectorPort
+
+RESET_REQUEST_ROLE = 'Reset Request'
+RESET_RESPONSE_ROLE = 'Reset Response'
+Port.compat(RESET_REQUEST_ROLE, RESET_RESPONSE_ROLE)
+
+# ResetRequestPort is an artifact request port for reset purpose.
+class ResetRequestPort(Port):
+def __init__(self, desc):
+super().__init__(RESET_REQUEST_ROLE, desc, is_source=True)
+
+# ResetResponsePort is an artifact response port for reset purpose.
+# The owner should perform whole reset when receiving a request.
+class ResetResponsePort(Port):
+def __init__(self, desc):
+super().__init__(RESET_RESPONSE_ROLE, desc)
+
+# VectorResetRequestPort presents a bank of artifact reset request
+# ports.
+class VectorResetRequestPort(VectorPort):
+def __init__(self, desc):
+super().__init__(RESET_REQUEST_ROLE, desc, is_source=True)
diff --git a/src/dev/SConscript b/src/dev/SConscript
index bc2fe98..44a7cc9 100644
--- a/src/dev/SConscript
+++ b/src/dev/SConscript
@@ -38,6 +38,9 @@
 SimObject('IntPin.py', sim_objects=[])
 Source('intpin.cc')

+SimObject('ResetPort.py', sim_objects=[])
+Source('reset_port.cc')
+
 DebugFlag('IsaFake')
 DebugFlag('DMA')

diff --git a/src/dev/reset_port.cc b/src/dev/reset_port.cc
new file mode 100644
index 000..8d32c7d
--- /dev/null
+++ b/src/dev/reset_port.cc
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2022 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific

[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: Add CortexR52 model reset port

2022-04-26 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58813 )


Change subject: fastmodel: Add CortexR52 model reset port
..

fastmodel: Add CortexR52 model reset port

The model reset is an aggregated logic to reset the whole model. The
port helps us to simulate the reboot process.

Change-Id: I15101bfe11dee40b63cc29c2befb610beb3d32aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58813
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
4 files changed, 41 insertions(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py  
b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py

index 615935e..c9e21e6 100644
--- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
+++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
@@ -30,6 +30,7 @@
 from m5.objects.ArmInterrupts import ArmInterrupts
 from m5.objects.ArmISA import ArmISA
 from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
+from m5.objects.ResetPort import ResetResponsePort
 from m5.objects.IntPin import IntSinkPin, VectorIntSinkPin
 from m5.objects.Iris import IrisBaseCPU
 from m5.objects.SystemC import SystemC_ScModule
@@ -116,6 +117,7 @@
 top_reset = IntSinkPin('This signal resets timer and interrupt  
controller.')
 dbg_reset = IntSinkPin('Initialize the shared debug APB, Cross  
Trigger ' \

 'Interface (CTI), and Cross Trigger Matrix (CTM) logic.')
+model_reset = ResetResponsePort('A reset port to reset the whole  
cluster.')


 CLUSTER_ID = Param.UInt16(0, "CLUSTER_ID[15:8] equivalent to " \
 "CFGMPIDRAFF2, CLUSTER_ID[7:0] equivalent to CFGMPIDRAFF1")
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc  
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc

index 2b92b2a..be83082 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -159,7 +159,7 @@
 if (if_name == "spi") {
 return evs->gem5_getPort(if_name, idx);
 } else if (if_name == "ext_slave" || if_name == "top_reset" ||
-   if_name == "dbg_reset") {
+   if_name == "dbg_reset" || if_name == "model_reset") {
 assert(idx == InvalidPortID);
 return evs->gem5_getPort(if_name, idx);
 } else {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc  
b/src/arch/arm/fastmodel/CortexR52/evs.cc

index f9f1583..6887c6c 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -99,6 +99,7 @@
 ext_slave(Base::ext_slave, p.name + ".ext_slave", -1),
 top_reset(p.name + ".top_reset", 0),
 dbg_reset(p.name + ".dbg_reset", 0),
+model_reset(p.name + ".model_reset", -1, this),
 params(p)
 {
 for (int i = 0; i < CoreCount; i++)
@@ -148,6 +149,8 @@
 return this->top_reset;
 } else if (if_name == "dbg_reset") {
 return this->dbg_reset;
+} else if (if_name == "model_reset") {
+return this->model_reset;
 } else if (if_name == "spi") {
 return *this->spis.at(idx);
 } else if (if_name.substr(0, 3) == "ppi") {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh  
b/src/arch/arm/fastmodel/CortexR52/evs.hh

index eee44c7..535d678 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -37,6 +37,7 @@
 #include "arch/arm/fastmodel/protocol/exported_clock_rate_control.hh"
 #include "arch/arm/fastmodel/protocol/signal_interrupt.hh"
 #include "dev/intpin.hh"
+#include "dev/reset_port.hh"
 #include "mem/port_proxy.hh"
 #include "params/FastModelScxEvsCortexR52x1.hh"
 #include "params/FastModelScxEvsCortexR52x2.hh"
@@ -125,6 +126,8 @@

 SignalSender dbg_reset;

+ResetResponsePort model_reset;
+
 CortexR52Cluster *gem5CpuCluster;

 const Params 
@@ -145,6 +148,22 @@
 this->signalInterrupt->spi(num, false);
 }

+void
+requestReset()
+{
+// Reset all cores.
+for (auto _pin : corePins) {
+core_pin->poweron_reset.signal_out.set_state(0, true);
+core_pin->poweron_reset.signal_out.set_state(0, false);
+}
+// Reset L2 system.
+this->top_reset.signal_out.set_state(0, true);
+this->top_reset.signal_out.set_state(0, false);
+// Reset debug APB.
+this->dbg_reset.signal_out.set_state(0, true);
+this->dbg_reset.signal_out.set_state(0, false);
+}
+
 Port _getPort(const std::string _name, int idx) override;

 void

--
To view, visit

[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: Add CortexA76 model reset port

2022-04-26 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58814 )


Change subject: fastmodel: Add CortexA76 model reset port
..

fastmodel: Add CortexA76 model reset port

The model reset is an aggregated logic to reset the whole model. The
port helps us to simulate the reboot process.

Change-Id: I9aacc398b299e26e4675f7229db1afc8f6c8a34f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58814
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
4 files changed, 46 insertions(+), 2 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py  
b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py

index 9a56f29..3f98162 100644
--- a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
+++ b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
@@ -31,6 +31,7 @@
 from m5.objects.ArmISA import ArmISA
 from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
 from m5.objects.FastModelGIC import Gicv3CommsTargetSocket
+from m5.objects.ResetPort import ResetResponsePort
 from m5.objects.IntPin import IntSinkPin
 from m5.objects.Gic import ArmPPI
 from m5.objects.Iris import IrisBaseCPU
@@ -172,6 +173,7 @@
 'all resettable registers in DynamIQ.')
 dbg_reset = IntSinkPin('Initialize the shared debug APB, Cross  
Trigger ' \

 'Interface (CTI), and Cross Trigger Matrix (CTM) logic.')
+model_reset = ResetResponsePort('A reset port to reset the whole  
cluster.')


 # These parameters are described in "Fast Models Reference Manual"  
section

 # 3.4.19, "ARMCortexA7x1CT".
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc

index e67a0f6..9280a04 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -104,7 +104,8 @@
 Port &
 CortexA76::getPort(const std::string _name, PortID idx)
 {
-if (if_name == "redistributor" || if_name == "core_reset")
+if (if_name == "redistributor" || if_name == "core_reset" ||
+if_name == "poweron_reset")
 return cluster->getEvs()->gem5_getPort(if_name, num);
 else
 return Base::getPort(if_name, idx);
@@ -200,7 +201,7 @@
 CortexA76Cluster::getPort(const std::string _name, PortID idx)
 {
 if (if_name == "amba" || if_name == "top_reset" ||
-if_name == "dbg_reset") {
+if_name == "dbg_reset" || if_name == "model_reset") {
 return evs->gem5_getPort(if_name, idx);
 } else {
 return SimObject::getPort(if_name, idx);
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc  
b/src/arch/arm/fastmodel/CortexA76/evs.cc

index d54ad78..1c06935 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -71,12 +71,30 @@
 }

 template 
+void
+ScxEvsCortexA76::requestReset()
+{
+// Reset all cores.
+for (auto _reset : this->poweron_reset) {
+poweron_reset->signal_out.set_state(0, true);
+poweron_reset->signal_out.set_state(0, false);
+}
+// Reset DSU.
+this->top_reset.signal_out.set_state(0, true);
+this->top_reset.signal_out.set_state(0, false);
+// Reset debug APB.
+this->dbg_reset.signal_out.set_state(0, true);
+this->dbg_reset.signal_out.set_state(0, false);
+}
+
+template 
 ScxEvsCortexA76::ScxEvsCortexA76(
 const sc_core::sc_module_name _name, const Params ) :
 Base(mod_name),
 amba(Base::amba, p.name + ".amba", -1),
 top_reset(p.name + ".top_reset", 0),
 dbg_reset(p.name + ".dbg_reset", 0),
+model_reset(p.name + ".model_reset", -1, this),
 params(p)
 {
 for (int i = 0; i < CoreCount; i++) {
@@ -178,6 +196,8 @@
 return top_reset;
 else if (if_name == "dbg_reset")
 return dbg_reset;
+else if (if_name == "model_reset")
+return model_reset;
 else
 return Base::gem5_getPort(if_name, idx);
 }
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh  
b/src/arch/arm/fastmodel/CortexA76/evs.hh

index e1b6aed..081e80f 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -35,6 +35,7 @@
 #include "arch/arm/fastmodel/common/signal_sender.hh"
 #include "arch/arm/fastmodel/iris/cpu.hh"
 #include "arch/arm/fastmodel/protocol/exported_clock_rate_control.hh"
+#include "dev/reset_port.hh"
 #include "mem/port_proxy.hh"
 #include "params/FastModelScxEvsCortexA76x1.hh"
 #include "params/FastModelScxEvsCortexA76x2.hh"
@@ -98,6 +99,8 @@

 SignalSender dbg_reset;

+ResetResponsePort

[gem5-dev] [M] Change in gem5/gem5[develop]: fastmodel: Export more CortexR52 reset pin

2022-04-13 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58811 )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: fastmodel: Export more CortexR52 reset pin
..

fastmodel: Export more CortexR52 reset pin

Change-Id: I20f34ae2061e886b35fe9439dbb8e25ce3571e4f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58811
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
M src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
M src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
M src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
8 files changed, 45 insertions(+), 7 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py  
b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py

index 710584d..615935e 100644
--- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
+++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
@@ -114,6 +114,8 @@

 ext_slave = AmbaTargetSocket(64, 'AMBA target socket')
 top_reset = IntSinkPin('This signal resets timer and interrupt  
controller.')
+dbg_reset = IntSinkPin('Initialize the shared debug APB, Cross  
Trigger ' \

+'Interface (CTI), and Cross Trigger Matrix (CTM) logic.')

 CLUSTER_ID = Param.UInt16(0, "CLUSTER_ID[15:8] equivalent to " \
 "CFGMPIDRAFF2, CLUSTER_ID[7:0] equivalent to CFGMPIDRAFF1")
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc  
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc

index 85a4c2a..2b92b2a 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -158,7 +158,8 @@
 {
 if (if_name == "spi") {
 return evs->gem5_getPort(if_name, idx);
-} else if (if_name == "ext_slave" || if_name == "top_reset") {
+} else if (if_name == "ext_slave" || if_name == "top_reset" ||
+   if_name == "dbg_reset") {
 assert(idx == InvalidPortID);
 return evs->gem5_getPort(if_name, idx);
 } else {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc  
b/src/arch/arm/fastmodel/CortexR52/evs.cc

index 720f1cc..f9f1583 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -96,9 +96,10 @@
 ScxEvsCortexR52::ScxEvsCortexR52(
 const sc_core::sc_module_name _name, const Params ) :
 Base(mod_name),
-params(p),
 ext_slave(Base::ext_slave, p.name + ".ext_slave", -1),
-top_reset(p.name + ".top_reset", 0)
+top_reset(p.name + ".top_reset", 0),
+dbg_reset(p.name + ".dbg_reset", 0),
+params(p)
 {
 for (int i = 0; i < CoreCount; i++)
 corePins.emplace_back(new CorePins(this, i));
@@ -109,6 +110,7 @@
 }

 top_reset.signal_out.bind(Base::top_reset);
+dbg_reset.signal_out.bind(Base::dbg_reset);

 clockRateControl.bind(this->clock_rate_s);
 signalInterrupt.bind(this->signal_interrupt);
@@ -144,6 +146,8 @@
 return this->ext_slave;
 } else if (if_name == "top_reset") {
 return this->top_reset;
+} else if (if_name == "dbg_reset") {
+return this->dbg_reset;
 } else if (if_name == "spi") {
 return *this->spis.at(idx);
 } else if (if_name.substr(0, 3) == "ppi") {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh  
b/src/arch/arm/fastmodel/CortexR52/evs.hh

index fa9d7fe..eee44c7 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -119,14 +119,16 @@

 std::vector> spis;

-CortexR52Cluster *gem5CpuCluster;
-
-const Params 
-
 AmbaTarget ext_slave;

 SignalSender top_reset;

+SignalSender dbg_reset;
+
+CortexR52Cluster *gem5CpuCluster;
+
+const Params 
+
   public:
 ScxEvsCortexR52(const Params ) : ScxEvsCortexR52(p.name.c_str(), p)  
{}
 ScxEvsCortexR52(const sc_core::sc_module_name _name, const Params  
);
diff --git a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa  
b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa

index 36f3279..2a7299d 100644
--- a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
@@ -45,9 +45,12 @@
 core.flash_m => self.flash;
 core.pvbus_core_m => self.amba;
 self.ext_slave => core.ext_slave_s;
+
+// Reset signals.
 self.core_reset => core.reset;
 self.poweron_reset => core.cpuporeset;
 self.top_reset => core.topreset;
+self.dbg_reset => core.presetdbg;
 self.halt =>

[gem5-dev] [M] Change in gem5/gem5[develop]: fastmodel: Export more CortexA76 reset pin

2022-04-13 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58812 )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: fastmodel: Export more CortexA76 reset pin
..

fastmodel: Export more CortexA76 reset pin

Change-Id: I386cf659fa77b2005f808fde51ef772ac0a57735
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58812
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
M src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
M src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
M src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
M src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
8 files changed, 93 insertions(+), 3 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py  
b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py

index c7d46ff..9a56f29 100644
--- a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
+++ b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
@@ -31,6 +31,7 @@
 from m5.objects.ArmISA import ArmISA
 from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
 from m5.objects.FastModelGIC import Gicv3CommsTargetSocket
+from m5.objects.IntPin import IntSinkPin
 from m5.objects.Gic import ArmPPI
 from m5.objects.Iris import IrisBaseCPU
 from m5.objects.SystemC import SystemC_ScModule
@@ -46,6 +47,10 @@
 evs = Parent.evs

 redistributor = Gicv3CommsTargetSocket('GIC communication target')
+core_reset = IntSinkPin('Raising this signal will put the core into ' \
+'reset mode.')
+poweron_reset = IntSinkPin('Power on reset. Initializes all the ' \
+   'processor logic, including debug logic.')

 CFGEND = Param.Bool(False, "Endianness configuration at reset.  "\
 "0, little endian. 1, big endian.")
@@ -163,6 +168,10 @@
 "Non-secure physical timer event")

 amba = AmbaInitiatorSocket(64, 'AMBA initiator socket')
+top_reset = IntSinkPin('A single cluster-wide power on reset signal  
for ' \

+'all resettable registers in DynamIQ.')
+dbg_reset = IntSinkPin('Initialize the shared debug APB, Cross  
Trigger ' \

+'Interface (CTI), and Cross Trigger Matrix (CTM) logic.')

 # These parameters are described in "Fast Models Reference Manual"  
section

 # 3.4.19, "ARMCortexA7x1CT".
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc

index e77e734..e67a0f6 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -104,7 +104,7 @@
 Port &
 CortexA76::getPort(const std::string _name, PortID idx)
 {
-if (if_name == "redistributor")
+if (if_name == "redistributor" || if_name == "core_reset")
 return cluster->getEvs()->gem5_getPort(if_name, num);
 else
 return Base::getPort(if_name, idx);
@@ -199,7 +199,8 @@
 Port &
 CortexA76Cluster::getPort(const std::string _name, PortID idx)
 {
-if (if_name == "amba") {
+if (if_name == "amba" || if_name == "top_reset" ||
+if_name == "dbg_reset") {
 return evs->gem5_getPort(if_name, idx);
 } else {
 return SimObject::getPort(if_name, idx);
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc  
b/src/arch/arm/fastmodel/CortexA76/evs.cc

index 935d139..d54ad78 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -73,7 +73,10 @@
 template 
 ScxEvsCortexA76::ScxEvsCortexA76(
 const sc_core::sc_module_name _name, const Params ) :
-Base(mod_name), amba(Base::amba, p.name + ".amba", -1),
+Base(mod_name),
+amba(Base::amba, p.name + ".amba", -1),
+top_reset(p.name + ".top_reset", 0),
+dbg_reset(p.name + ".dbg_reset", 0),
 params(p)
 {
 for (int i = 0; i < CoreCount; i++) {
@@ -93,6 +96,10 @@
 new SignalReceiver(csprintf("cntpnsirq[%d]", i)));
 rvbaraddr.emplace_back(new SignalInitiator(
 csprintf("rvbaraddr[%d]", i).c_str()));
+core_reset.emplace_back(
+new SignalSender(csprintf("core_reset[%d]", i), 0));
+poweron_reset.emplace_back(
+new SignalSender(csprintf("poweron_reset[%d]", i), 0));

 Base::cnthpirq[i].bind(cnthpirq[i]->signal_in);
 Base::cnthvirq[i].bind(cnthvirq[i]->signal_in);
@@ -104,8 +111,13 @@
 Base::vcpumntirq[i].bind(vcpumntirq[i]->signal_in);
 Base::cntpnsirq[i].bind(cntpnsirq[i]->signal_in);

[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Fix script failed when default files not found

2022-04-12 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58809 )


Change subject: scons: Fix script failed when default files not found
..

scons: Fix script failed when default files not found

Change-Id: Ic673783cb5050159a141a869ca17b1ac09a924ef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58809
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M SConstruct
1 file changed, 14 insertions(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/SConstruct b/SConstruct
index cf130c1..95ebff1 100755
--- a/SConstruct
+++ b/SConstruct
@@ -633,7 +633,7 @@
 (' or '.join(current_vars_files), default_vars_file))
 else:
 error("Cannot find variables file(s) %s or default  
file(s) %s" %

-(' or '.join(current_vars_file),
+(' or '.join(current_vars_files),
  ' or '.join(default_vars_files)))
 Exit(1)


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/58809
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic673783cb5050159a141a869ca17b1ac09a924ef
Gerrit-Change-Number: 58809
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: Export more CortexR52 reset pin

2022-04-11 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58811 )



Change subject: fastmodel: Export more CortexR52 reset pin
..

fastmodel: Export more CortexR52 reset pin

Change-Id: I20f34ae2061e886b35fe9439dbb8e25ce3571e4f
---
M src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
M src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
M src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
M src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
8 files changed, 41 insertions(+), 7 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py  
b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py

index 710584d..615935e 100644
--- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
+++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
@@ -114,6 +114,8 @@

 ext_slave = AmbaTargetSocket(64, 'AMBA target socket')
 top_reset = IntSinkPin('This signal resets timer and interrupt  
controller.')
+dbg_reset = IntSinkPin('Initialize the shared debug APB, Cross  
Trigger ' \

+'Interface (CTI), and Cross Trigger Matrix (CTM) logic.')

 CLUSTER_ID = Param.UInt16(0, "CLUSTER_ID[15:8] equivalent to " \
 "CFGMPIDRAFF2, CLUSTER_ID[7:0] equivalent to CFGMPIDRAFF1")
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc  
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc

index 85a4c2a..2b92b2a 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -158,7 +158,8 @@
 {
 if (if_name == "spi") {
 return evs->gem5_getPort(if_name, idx);
-} else if (if_name == "ext_slave" || if_name == "top_reset") {
+} else if (if_name == "ext_slave" || if_name == "top_reset" ||
+   if_name == "dbg_reset") {
 assert(idx == InvalidPortID);
 return evs->gem5_getPort(if_name, idx);
 } else {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc  
b/src/arch/arm/fastmodel/CortexR52/evs.cc

index 720f1cc..f9f1583 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -96,9 +96,10 @@
 ScxEvsCortexR52::ScxEvsCortexR52(
 const sc_core::sc_module_name _name, const Params ) :
 Base(mod_name),
-params(p),
 ext_slave(Base::ext_slave, p.name + ".ext_slave", -1),
-top_reset(p.name + ".top_reset", 0)
+top_reset(p.name + ".top_reset", 0),
+dbg_reset(p.name + ".dbg_reset", 0),
+params(p)
 {
 for (int i = 0; i < CoreCount; i++)
 corePins.emplace_back(new CorePins(this, i));
@@ -109,6 +110,7 @@
 }

 top_reset.signal_out.bind(Base::top_reset);
+dbg_reset.signal_out.bind(Base::dbg_reset);

 clockRateControl.bind(this->clock_rate_s);
 signalInterrupt.bind(this->signal_interrupt);
@@ -144,6 +146,8 @@
 return this->ext_slave;
 } else if (if_name == "top_reset") {
 return this->top_reset;
+} else if (if_name == "dbg_reset") {
+return this->dbg_reset;
 } else if (if_name == "spi") {
 return *this->spis.at(idx);
 } else if (if_name.substr(0, 3) == "ppi") {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh  
b/src/arch/arm/fastmodel/CortexR52/evs.hh

index fa9d7fe..eee44c7 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -119,14 +119,16 @@

 std::vector> spis;

-CortexR52Cluster *gem5CpuCluster;
-
-const Params 
-
 AmbaTarget ext_slave;

 SignalSender top_reset;

+SignalSender dbg_reset;
+
+CortexR52Cluster *gem5CpuCluster;
+
+const Params 
+
   public:
 ScxEvsCortexR52(const Params ) : ScxEvsCortexR52(p.name.c_str(), p)  
{}
 ScxEvsCortexR52(const sc_core::sc_module_name _name, const Params  
);
diff --git a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa  
b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa

index 36f3279..2a7299d 100644
--- a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
@@ -45,9 +45,12 @@
 core.flash_m => self.flash;
 core.pvbus_core_m => self.amba;
 self.ext_slave => core.ext_slave_s;
+
+// Reset signals.
 self.core_reset => core.reset;
 self.poweron_reset => core.cpuporeset;
 self.top_reset => core.topreset;
+self.dbg_reset => core.presetdbg;
 self.halt => core.cpuhalt;

 // Clocks.
@@ -77,6 +80,7 @@
 slave port poweron_reset[1];
 slave port halt[1];
 slave port top_reset;
+slave port dbg_reset;
 slave port cfgvectable[1];

 slave port clock_rate_s
diff --git a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa  
b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa

index 492d289..9100a5b 100644
---

[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: Add CortexA76 artifact reset port

2022-04-11 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58814 )



Change subject: fastmodel: Add CortexA76 artifact reset port
..

fastmodel: Add CortexA76 artifact reset port

The artifact reset is an aggregated logic to reset the whole model. The
port helps us to simulate the reboot process.

Change-Id: I9aacc398b299e26e4675f7229db1afc8f6c8a34f
---
M src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
4 files changed, 40 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py  
b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py

index 9a56f29..420b499 100644
--- a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
+++ b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
@@ -31,6 +31,7 @@
 from m5.objects.ArmISA import ArmISA
 from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
 from m5.objects.FastModelGIC import Gicv3CommsTargetSocket
+from m5.objects.FastModelResetPort import FastModelResetResponsePort
 from m5.objects.IntPin import IntSinkPin
 from m5.objects.Gic import ArmPPI
 from m5.objects.Iris import IrisBaseCPU
@@ -172,6 +173,8 @@
 'all resettable registers in DynamIQ.')
 dbg_reset = IntSinkPin('Initialize the shared debug APB, Cross  
Trigger ' \

 'Interface (CTI), and Cross Trigger Matrix (CTM) logic.')
+artifact_reset = FastModelResetResponsePort(
+'An artifact reset port to reset the whole cluster.')

 # These parameters are described in "Fast Models Reference Manual"  
section

 # 3.4.19, "ARMCortexA7x1CT".
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc

index e67a0f6..24f873b 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -104,7 +104,8 @@
 Port &
 CortexA76::getPort(const std::string _name, PortID idx)
 {
-if (if_name == "redistributor" || if_name == "core_reset")
+if (if_name == "redistributor" || if_name == "core_reset" ||
+if_name == "poweron_reset")
 return cluster->getEvs()->gem5_getPort(if_name, num);
 else
 return Base::getPort(if_name, idx);
@@ -200,7 +201,7 @@
 CortexA76Cluster::getPort(const std::string _name, PortID idx)
 {
 if (if_name == "amba" || if_name == "top_reset" ||
-if_name == "dbg_reset") {
+if_name == "dbg_reset" || if_name == "artifact_reset") {
 return evs->gem5_getPort(if_name, idx);
 } else {
 return SimObject::getPort(if_name, idx);
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc  
b/src/arch/arm/fastmodel/CortexA76/evs.cc

index d54ad78..76b2840 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -71,12 +71,27 @@
 }

 template 
+void
+ScxEvsCortexA76::requestReset()
+{
+// Reset all cores.
+for (auto _reset : this->poweron_reset) {
+poweron_reset->signal_out.set_state(0, true);
+}
+// Reset DSU.
+this->top_reset.signal_out.set_state(0, true);
+// Reset debug APB.
+this->dbg_reset.signal_out.set_state(0, true);
+}
+
+template 
 ScxEvsCortexA76::ScxEvsCortexA76(
 const sc_core::sc_module_name _name, const Params ) :
 Base(mod_name),
 amba(Base::amba, p.name + ".amba", -1),
 top_reset(p.name + ".top_reset", 0),
 dbg_reset(p.name + ".dbg_reset", 0),
+artifact_reset(p.name + ".artifact_reset", -1, this),
 params(p)
 {
 for (int i = 0; i < CoreCount; i++) {
@@ -178,6 +193,8 @@
 return top_reset;
 else if (if_name == "dbg_reset")
 return dbg_reset;
+else if (if_name == "artifact_reset")
+return artifact_reset;
 else
 return Base::gem5_getPort(if_name, idx);
 }
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh  
b/src/arch/arm/fastmodel/CortexA76/evs.hh

index e1b6aed..28a473d 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -31,6 +31,7 @@
 #include 

 #include "arch/arm/fastmodel/amba_ports.hh"
+#include "arch/arm/fastmodel/common/reset_port.hh"
 #include "arch/arm/fastmodel/common/signal_receiver.hh"
 #include "arch/arm/fastmodel/common/signal_sender.hh"
 #include "arch/arm/fastmodel/iris/cpu.hh"
@@ -98,6 +99,8 @@

 SignalSender dbg_reset;

+ResetResponsePort artifact_reset;
+
 CortexA76Cluster *gem5CpuCluster;

 const Params 
@@ -126,6 +129,8 @@
 void setCluster(SimObject *cluster) override;

 void setResetAddr(int core, Addr addr, bool secure) override;
+
+void requestReset();
 };

 struct ScxEvsCortexA76x1Types

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/58814
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[gem5-dev] [M] Change in gem5/gem5[develop]: fastmodel: Add a special reset interface to consolidate reset logic

2022-04-11 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58810 )



Change subject: fastmodel: Add a special reset interface to consolidate  
reset logic

..

fastmodel: Add a special reset interface to consolidate reset logic

How to reset a model correctly is very different between models. Take
cpu models for instance, they have different reset pins for different
parts(typically one for each core, one for shared component, one for
debug interface). To make users more easily to reset the model, here we
want to introduce a special reset port. By implementing the port, users
can simply request a whole reset to the model. If users want to do
partial resets, users still can access the raw pins to achieve what they
want.

Change-Id: I746121d16441e021dc3392aeae1a6d9fa33d637a
---
A src/arch/arm/fastmodel/common/FastModelResetPort.py
A src/arch/arm/fastmodel/common/SConscript
A src/arch/arm/fastmodel/common/reset_port.cc
A src/arch/arm/fastmodel/common/reset_port.hh
4 files changed, 229 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/fastmodel/common/FastModelResetPort.py  
b/src/arch/arm/fastmodel/common/FastModelResetPort.py

new file mode 100644
index 000..b33a7fa
--- /dev/null
+++ b/src/arch/arm/fastmodel/common/FastModelResetPort.py
@@ -0,0 +1,50 @@
+# Copyright 2022 Google, Inc.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.params import *
+
+RESET_REQUEST_ROLE = 'FastModel Reset Request'
+RESET_RESPONSE_ROLE = 'FastModel Reset Response'
+Port.compat(RESET_REQUEST_ROLE, RESET_RESPONSE_ROLE)
+
+# FastModelResetRequestPort is an artifact request port for reset purpose.
+class FastModelResetRequestPort(Port):
+def __init__(self, desc):
+super(FastModelResetRequestPort, self).__init__(
+RESET_REQUEST_ROLE, desc, is_source=True)
+
+# FastModelResetResponsePort is an artifact response port for reset  
purpose.

+# The owner should perform whole reset when receiving a request.
+class FastModelResetResponsePort(Port):
+def __init__(self, desc):
+super(FastModelResetResponsePort, self).__init__(
+RESET_RESPONSE_ROLE, desc)
+
+# VectorFastModelResetRequestPort presents a bank of artifact reset request
+# ports.
+class VectorFastModelResetRequestPort(VectorPort):
+def __init__(self, desc):
+super(VectorFastModelResetRequestPort, self).__init__(
+RESET_REQUEST_ROLE, desc, is_source=True)
diff --git a/src/arch/arm/fastmodel/common/SConscript  
b/src/arch/arm/fastmodel/common/SConscript

new file mode 100644
index 000..46826f5
--- /dev/null
+++ b/src/arch/arm/fastmodel/common/SConscript
@@ -0,0 +1,30 @@
+# Copyright 2022 Google, Inc.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND

[gem5-dev] [M] Change in gem5/gem5[develop]: fastmodel: Export more CortexA76 reset pin

2022-04-11 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58812 )



Change subject: fastmodel: Export more CortexA76 reset pin
..

fastmodel: Export more CortexA76 reset pin

Change-Id: I386cf659fa77b2005f808fde51ef772ac0a57735
---
M src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
M src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
M src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
M src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
M src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
8 files changed, 89 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py  
b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py

index c7d46ff..9a56f29 100644
--- a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
+++ b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
@@ -31,6 +31,7 @@
 from m5.objects.ArmISA import ArmISA
 from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
 from m5.objects.FastModelGIC import Gicv3CommsTargetSocket
+from m5.objects.IntPin import IntSinkPin
 from m5.objects.Gic import ArmPPI
 from m5.objects.Iris import IrisBaseCPU
 from m5.objects.SystemC import SystemC_ScModule
@@ -46,6 +47,10 @@
 evs = Parent.evs

 redistributor = Gicv3CommsTargetSocket('GIC communication target')
+core_reset = IntSinkPin('Raising this signal will put the core into ' \
+'reset mode.')
+poweron_reset = IntSinkPin('Power on reset. Initializes all the ' \
+   'processor logic, including debug logic.')

 CFGEND = Param.Bool(False, "Endianness configuration at reset.  "\
 "0, little endian. 1, big endian.")
@@ -163,6 +168,10 @@
 "Non-secure physical timer event")

 amba = AmbaInitiatorSocket(64, 'AMBA initiator socket')
+top_reset = IntSinkPin('A single cluster-wide power on reset signal  
for ' \

+'all resettable registers in DynamIQ.')
+dbg_reset = IntSinkPin('Initialize the shared debug APB, Cross  
Trigger ' \

+'Interface (CTI), and Cross Trigger Matrix (CTM) logic.')

 # These parameters are described in "Fast Models Reference Manual"  
section

 # 3.4.19, "ARMCortexA7x1CT".
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc

index e77e734..e67a0f6 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -104,7 +104,7 @@
 Port &
 CortexA76::getPort(const std::string _name, PortID idx)
 {
-if (if_name == "redistributor")
+if (if_name == "redistributor" || if_name == "core_reset")
 return cluster->getEvs()->gem5_getPort(if_name, num);
 else
 return Base::getPort(if_name, idx);
@@ -199,7 +199,8 @@
 Port &
 CortexA76Cluster::getPort(const std::string _name, PortID idx)
 {
-if (if_name == "amba") {
+if (if_name == "amba" || if_name == "top_reset" ||
+if_name == "dbg_reset") {
 return evs->gem5_getPort(if_name, idx);
 } else {
 return SimObject::getPort(if_name, idx);
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc  
b/src/arch/arm/fastmodel/CortexA76/evs.cc

index 935d139..d54ad78 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -73,7 +73,10 @@
 template 
 ScxEvsCortexA76::ScxEvsCortexA76(
 const sc_core::sc_module_name _name, const Params ) :
-Base(mod_name), amba(Base::amba, p.name + ".amba", -1),
+Base(mod_name),
+amba(Base::amba, p.name + ".amba", -1),
+top_reset(p.name + ".top_reset", 0),
+dbg_reset(p.name + ".dbg_reset", 0),
 params(p)
 {
 for (int i = 0; i < CoreCount; i++) {
@@ -93,6 +96,10 @@
 new SignalReceiver(csprintf("cntpnsirq[%d]", i)));
 rvbaraddr.emplace_back(new SignalInitiator(
 csprintf("rvbaraddr[%d]", i).c_str()));
+core_reset.emplace_back(
+new SignalSender(csprintf("core_reset[%d]", i), 0));
+poweron_reset.emplace_back(
+new SignalSender(csprintf("poweron_reset[%d]", i), 0));

 Base::cnthpirq[i].bind(cnthpirq[i]->signal_in);
 Base::cnthvirq[i].bind(cnthvirq[i]->signal_in);
@@ -104,8 +111,13 @@
 Base::vcpumntirq[i].bind(vcpumntirq[i]->signal_in);
 Base::cntpnsirq[i].bind(cntpnsirq[i]->signal_in);
 rvbaraddr[i]->bind(Base::rvbaraddr[i]);
+core_reset[i]->signal_out.bind(Base::core_reset[i]);
+poweron_reset[i]->signal_out.bind(Base::poweron_reset[i]);
 }

+top_reset.signal_out.bind(Base::top_reset);
+dbg_reset.signal_out.bind(Base::dbg_reset);
+
 clockRateControl.bind(this->clock_rate_s);

[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: Add CortexR52 artifact reset port

2022-04-11 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58813 )



Change subject: fastmodel: Add CortexR52 artifact reset port
..

fastmodel: Add CortexR52 artifact reset port

The artifact reset is an aggregated logic to reset the whole model. The
port helps us to simulate the reboot process.

Change-Id: I15101bfe11dee40b63cc29c2befb610beb3d32aa
---
M src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
4 files changed, 35 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py  
b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py

index 615935e..151ed11 100644
--- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
+++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
@@ -30,6 +30,7 @@
 from m5.objects.ArmInterrupts import ArmInterrupts
 from m5.objects.ArmISA import ArmISA
 from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
+from m5.objects.FastModelResetPort import FastModelResetResponsePort
 from m5.objects.IntPin import IntSinkPin, VectorIntSinkPin
 from m5.objects.Iris import IrisBaseCPU
 from m5.objects.SystemC import SystemC_ScModule
@@ -116,6 +117,8 @@
 top_reset = IntSinkPin('This signal resets timer and interrupt  
controller.')
 dbg_reset = IntSinkPin('Initialize the shared debug APB, Cross  
Trigger ' \

 'Interface (CTI), and Cross Trigger Matrix (CTM) logic.')
+artifact_reset = FastModelResetResponsePort(
+'An artifact reset port to reset the whole cluster.')

 CLUSTER_ID = Param.UInt16(0, "CLUSTER_ID[15:8] equivalent to " \
 "CFGMPIDRAFF2, CLUSTER_ID[7:0] equivalent to CFGMPIDRAFF1")
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc  
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc

index 2b92b2a..d4d7c87 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -159,7 +159,7 @@
 if (if_name == "spi") {
 return evs->gem5_getPort(if_name, idx);
 } else if (if_name == "ext_slave" || if_name == "top_reset" ||
-   if_name == "dbg_reset") {
+   if_name == "dbg_reset" || if_name == "artifact_reset") {
 assert(idx == InvalidPortID);
 return evs->gem5_getPort(if_name, idx);
 } else {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc  
b/src/arch/arm/fastmodel/CortexR52/evs.cc

index f9f1583..3dfc0af 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -99,6 +99,7 @@
 ext_slave(Base::ext_slave, p.name + ".ext_slave", -1),
 top_reset(p.name + ".top_reset", 0),
 dbg_reset(p.name + ".dbg_reset", 0),
+artifact_reset(p.name + ".artifact_reset", -1, this),
 params(p)
 {
 for (int i = 0; i < CoreCount; i++)
@@ -148,6 +149,8 @@
 return this->top_reset;
 } else if (if_name == "dbg_reset") {
 return this->dbg_reset;
+} else if (if_name == "artifact_reset") {
+return this->artifact_reset;
 } else if (if_name == "spi") {
 return *this->spis.at(idx);
 } else if (if_name.substr(0, 3) == "ppi") {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh  
b/src/arch/arm/fastmodel/CortexR52/evs.hh

index eee44c7..50c0d18 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -31,6 +31,7 @@
 #include 

 #include "arch/arm/fastmodel/amba_ports.hh"
+#include "arch/arm/fastmodel/common/reset_port.hh"
 #include "arch/arm/fastmodel/common/signal_receiver.hh"
 #include "arch/arm/fastmodel/common/signal_sender.hh"
 #include "arch/arm/fastmodel/iris/cpu.hh"
@@ -125,6 +126,8 @@

 SignalSender dbg_reset;

+ResetResponsePort artifact_reset;
+
 CortexR52Cluster *gem5CpuCluster;

 const Params 
@@ -145,6 +148,19 @@
 this->signalInterrupt->spi(num, false);
 }

+void
+requestReset()
+{
+// Reset all cores.
+for (auto _pin : corePins) {
+core_pin->poweron_reset.signal_out.set_state(0, true);
+}
+// Reset L2 system.
+this->top_reset.signal_out.set_state(0, true);
+// Reset debug APB.
+this->dbg_reset.signal_out.set_state(0, true);
+}
+
 Port _getPort(const std::string _name, int idx) override;

 void

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I15101bfe11dee40b63cc29c2befb610beb3d32aa
Gerrit-Change-Number: 58813
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang 
Gerrit-MessageType: newchange
___

[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Fix script failed when default files not found

2022-04-11 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58809 )



Change subject: scons: Fix script failed when default files not found
..

scons: Fix script failed when default files not found

Change-Id: Ic673783cb5050159a141a869ca17b1ac09a924ef
---
M SConstruct
1 file changed, 10 insertions(+), 1 deletion(-)



diff --git a/SConstruct b/SConstruct
index cf130c1..95ebff1 100755
--- a/SConstruct
+++ b/SConstruct
@@ -633,7 +633,7 @@
 (' or '.join(current_vars_files), default_vars_file))
 else:
 error("Cannot find variables file(s) %s or default  
file(s) %s" %

-(' or '.join(current_vars_file),
+(' or '.join(current_vars_files),
  ' or '.join(default_vars_files)))
 Exit(1)


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic673783cb5050159a141a869ca17b1ac09a924ef
Gerrit-Change-Number: 58809
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: base: change bitunion default constructor to default

2022-03-22 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57730 )


Change subject: base: change bitunion default constructor to default
..

base: change bitunion default constructor to default

Current implementation prevents customers from performing zero
initialize on BitUnion class. Customers would get unexpected results
when writing `BitUnion{}`. Changing the default constructor to default
can solve this issue.

After changing the default constructor, the test failed with unused
variable. I also change one with zero initializer and make the other
with maybe_unused label.
```
tests/build/ARM/base/bitunion.test.cc:133:14: error: 'emptySixteen' defined  
but not used [-Werror=unused-variable]

  133 | EmptySixteen emptySixteen;
  |  ^~~~
tests/build/ARM/base/bitunion.test.cc:132:16: error: 'emptyThirtyTwo'  
defined but not used [-Werror=unused-variable]

  132 | EmptyThirtyTwo emptyThirtyTwo;
  |^~
```

Change-Id: Icbed36b3fa6751cbda63e84443eaab6d865d9bd6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57730
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/base/bitunion.hh
M src/base/bitunion.test.cc
2 files changed, 33 insertions(+), 3 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/base/bitunion.hh b/src/base/bitunion.hh
index 92d747c..c8bb659 100644
--- a/src/base/bitunion.hh
+++ b/src/base/bitunion.hh
@@ -261,7 +261,7 @@

 BitUnionOperators(const BitUnionOperators &) = default;

-BitUnionOperators() {}
+BitUnionOperators() = default;

 //Conversion operators.
 operator const typename Base::__StorageType () const
diff --git a/src/base/bitunion.test.cc b/src/base/bitunion.test.cc
index 7300efe..06c7a61 100644
--- a/src/base/bitunion.test.cc
+++ b/src/base/bitunion.test.cc
@@ -129,8 +129,8 @@
 // Declare these as global so g++ doesn't ignore them. Initialize them in
 // various ways.
 EmptySixtyFour emptySixtyFour = 0;
-EmptyThirtyTwo emptyThirtyTwo;
-EmptySixteen emptySixteen;
+EmptyThirtyTwo emptyThirtyTwo{};
+[[maybe_unused]] EmptySixteen emptySixteen;
 EmptyEight emptyEight(0);

 class BitUnionData : public testing::Test

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icbed36b3fa6751cbda63e84443eaab6d865d9bd6
Gerrit-Change-Number: 57730
Gerrit-PatchSet: 6
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jui-min Lee 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Ahbong Chang 
Gerrit-CC: Earl Ou 
Gerrit-CC: Gabe Black 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Upgrade to FastModel 11.17

2022-03-17 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57549 )


Change subject: fastmodel: Upgrade to FastModel 11.17
..

fastmodel: Upgrade to FastModel 11.17

The first big change is gcc-6.4 is no longer supported in FastModel
11.17. We switch to gcc-7.3. Next, TARGET_MAXVIEW is
replaced by TARGET_SYSTEMC_MAXVIEW. The default value of
TARGET_SYSTEMC_MAXVIEW is zero. So we can simply remove TARGET_MAXVIEW.
Finally, I fixed an undefined exception in the build script.

Change-Id: I5ec70112056513c253e6127ed5f8abacf191431f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57549
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/CortexA76/x1/x1.sgproj
M src/arch/arm/fastmodel/CortexA76/x2/x2.sgproj
M src/arch/arm/fastmodel/CortexA76/x3/x3.sgproj
M src/arch/arm/fastmodel/CortexA76/x4/x4.sgproj
M src/arch/arm/fastmodel/CortexR52/x1/x1.sgproj
M src/arch/arm/fastmodel/CortexR52/x2/x2.sgproj
M src/arch/arm/fastmodel/CortexR52/x3/x3.sgproj
M src/arch/arm/fastmodel/CortexR52/x4/x4.sgproj
M src/arch/arm/fastmodel/GIC/GIC.sgproj
M src/arch/arm/fastmodel/PL330_DMAC/PL330.sgproj
M src/arch/arm/fastmodel/SConscript
M src/arch/arm/fastmodel/SConsopts
12 files changed, 31 insertions(+), 22 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/CortexA76/x1/x1.sgproj  
b/src/arch/arm/fastmodel/CortexA76/x1/x1.sgproj

index ff839685..f3fd0db 100644
--- a/src/arch/arm/fastmodel/CortexA76/x1/x1.sgproj
+++ b/src/arch/arm/fastmodel/CortexA76/x1/x1.sgproj
@@ -8,13 +8,12 @@
 ADDITIONAL_COMPILER_SETTINGS = "-O3 -Wall -std=c++14 -Wno-deprecated  
-Wno-unused-function";

 ADDITIONAL_LINKER_SETTINGS = "-Wl,--no-undefined";
 BUILD_DIR = "./gcc";
-COMPILER = "gcc-6.4";
+COMPILER = "gcc-7.3";
 CONFIG_DESCRIPTION = "";
 CONFIG_NAME = "gcc";
 PLATFORM = "Linux64";
 PREPROCESSOR_DEFINES = "NDEBUG";
 SIMGEN_COMMAND_LINE = "--num-comps-file 50";
-TARGET_MAXVIEW = "0";
 TARGET_SYSTEMC = "1";
 TARGET_SYSTEMC_AUTO = "1";

diff --git a/src/arch/arm/fastmodel/CortexA76/x2/x2.sgproj  
b/src/arch/arm/fastmodel/CortexA76/x2/x2.sgproj

index 8ecb76f..abec8ad 100644
--- a/src/arch/arm/fastmodel/CortexA76/x2/x2.sgproj
+++ b/src/arch/arm/fastmodel/CortexA76/x2/x2.sgproj
@@ -8,13 +8,12 @@
 ADDITIONAL_COMPILER_SETTINGS = "-march=core2 -O3 -Wall -std=c++14  
-Wno-deprecated -Wno-unused-function";

 ADDITIONAL_LINKER_SETTINGS = "-Wl,--no-undefined";
 BUILD_DIR = "./gcc";
-COMPILER = "gcc-6.4";
+COMPILER = "gcc-7.3";
 CONFIG_DESCRIPTION = "";
 CONFIG_NAME = "gcc";
 PLATFORM = "Linux64";
 PREPROCESSOR_DEFINES = "NDEBUG";
 SIMGEN_COMMAND_LINE = "--num-comps-file 50";
-TARGET_MAXVIEW = "0";
 TARGET_SYSTEMC = "1";
 TARGET_SYSTEMC_AUTO = "1";

diff --git a/src/arch/arm/fastmodel/CortexA76/x3/x3.sgproj  
b/src/arch/arm/fastmodel/CortexA76/x3/x3.sgproj

index 36cfec7..666b1dc 100644
--- a/src/arch/arm/fastmodel/CortexA76/x3/x3.sgproj
+++ b/src/arch/arm/fastmodel/CortexA76/x3/x3.sgproj
@@ -8,13 +8,12 @@
 ADDITIONAL_COMPILER_SETTINGS = "-march=core2 -O3 -Wall -std=c++14  
-Wno-deprecated -Wno-unused-function";

 ADDITIONAL_LINKER_SETTINGS = "-Wl,--no-undefined";
 BUILD_DIR = "./gcc";
-COMPILER = "gcc-6.4";
+COMPILER = "gcc-7.3";
 CONFIG_DESCRIPTION = "";
 CONFIG_NAME = "gcc";
 PLATFORM = "Linux64";
 PREPROCESSOR_DEFINES = "NDEBUG";
 SIMGEN_COMMAND_LINE = "--num-comps-file 50";
-TARGET_MAXVIEW = "0";
 TARGET_SYSTEMC = "1";
 TARGET_SYSTEMC_AUTO = "1";

diff --git a/src/arch/arm/fastmodel/CortexA76/x4/x4.sgproj  
b/src/arch/arm/fastmodel/CortexA76/x4/x4.sgproj

index 291256b..e3c9063 100644
--- a/src/arch/arm/fastmodel/CortexA76/x4/x4.sgproj
+++ b/src/arch/arm/fastmodel/CortexA76/x4/x4.sgproj
@@ -8,13 +8,12 @@
 ADDITIONAL_COMPILER_SETTINGS = "-march=core2 -O3 -Wall -std=c++14  
-Wno-deprecated -Wno-unused-function";

 ADDITIONAL_LINKER_SETTINGS = "-Wl,--no-undefined";
 BUILD_DIR = "./gcc";
-COMPILER = "gcc-6.4";
+COMPILER = "gcc-7.3";
 CONFIG_DESCRIPTION = "";
 CONFIG_NAME = "gcc";
 PLATFORM = "Linux64";
 PREPROCESSOR_DEFINES = "NDEBUG";
 SIMGEN_COMMAND_LINE = "--num-comps-file 50";
-TARGET_MAXVIEW = "0";
 TARGET_SYSTEMC = "1";
 TARGET_SYSTEMC_AUTO = "1";

diff --git a/src/arch/arm/fastmodel/CortexR52/x1/x1.sgproj  
b/src/arch/arm/fastmodel/CortexR52/x1/x1.sgproj

index 4e8d35f..9d2a574 100644
--- a/src/arch/arm/fastmodel/CortexR52/x1/x1.sgproj
+++ b/src/arch/arm/fastmodel/CortexR52/x1/x1.sgproj
@@ -8,13 +8,12 @@
 ADDITIONAL_COMPILER_SETTINGS = "-O3 -Wall -std=c++14 -Wno-deprecated  
-Wno-unused-function";

 ADDITIONAL_LINKER_SETTINGS = "-Wl,--no-undefined";
 BUILD_DIR = "./gcc";
-

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: CortexA76 fix missing registers for FastModel 11.16

2022-03-17 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52543 )


Change subject: fastmodel: CortexA76 fix missing registers for FastModel  
11.16

..

fastmodel: CortexA76 fix missing registers for FastModel 11.16

Change-Id: Id6bfa1c374e9c9e65f2c234654f87567d2b29c09
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52543
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/CortexA76/thread_context.cc
1 file changed, 64 insertions(+), 51 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc  
b/src/arch/arm/fastmodel/CortexA76/thread_context.cc

index 735e06d..ff82bbe 100644
--- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
@@ -310,67 +310,67 @@
 { ArmISA::MISCREG_CSSELR, "CSSELR_EL1" }, //XXX verify
 // ArmISA::MISCREG_CSSELR_NS?
 // ArmISA::MISCREG_CSSELR_S?
-{ ArmISA::MISCREG_VPIDR, "VPIDR" },
-{ ArmISA::MISCREG_VMPIDR, "VMPIDR" },
+// ArmISA::MISCREG_VPIDR?
+// ArmISA::MISCREG_VMPIDR?,
 // ArmISA::MISCREG_SCTLR?
 // ArmISA::MISCREG_SCTLR_NS?
 // ArmISA::MISCREG_SCTLR_S?
 // ArmISA::MISCREG_ACTLR?
 // ArmISA::MISCREG_ACTLR_NS?
 // ArmISA::MISCREG_ACTLR_S?
-{ ArmISA::MISCREG_CPACR, "CPACR" },
+// ArmISA::MISCREG_CPACR?
 { ArmISA::MISCREG_SCR, "SCR" },
 { ArmISA::MISCREG_SDER, "SDER" },
-{ ArmISA::MISCREG_NSACR, "NSACR" },
-{ ArmISA::MISCREG_HSCTLR, "HSCTLR" },
-{ ArmISA::MISCREG_HACTLR, "HACTLR" },
-{ ArmISA::MISCREG_HCR, "HCR" },
-{ ArmISA::MISCREG_HDCR, "HDCR" },
-{ ArmISA::MISCREG_HCPTR, "HCPTR" },
+// ArmISA::MISCREG_NSACR?
+// ArmISA::MISCREG_HSCTLR?
+// ArmISA::MISCREG_HACTLR?
+// ArmISA::MISCREG_HCR?
+// ArmISA::MISCREG_HDCR?
+// ArmISA::MISCREG_HCPTR?
 { ArmISA::MISCREG_HSTR, "HSTR_EL2" }, //XXX verify
-{ ArmISA::MISCREG_HACR, "HACR" },
+// ArmISA::MISCREG_HACR?
 // ArmISA::MISCREG_TTBR0?
-{ ArmISA::MISCREG_TTBR0_NS, "NS_TTBR0" }, //XXX verify
+// ArmISA::MISCREG_TTBR0_NS?
 // ArmISA::MISCREG_TTBR0_S?
 // ArmISA::MISCREG_TTBR1?
-{ ArmISA::MISCREG_TTBR1_NS, "NS_TTBR1" }, //XXX verify
+// ArmISA::MISCREG_TTBR1_NS?
 // ArmISA::MISCREG_TTBR1_S?
 // ArmISA::MISCREG_TTBCR?
-{ ArmISA::MISCREG_TTBCR_NS, "NS_TTBCR" }, //XXX verify
+// ArmISA::MISCREG_TTBCR_NS?
 // ArmISA::MISCREG_TTBCR_S?
 // ArmISA::MISCREG_HTCR?
 // ArmISA::MISCREG_VTCR?
 // ArmISA::MISCREG_DACR?
-{ ArmISA::MISCREG_DACR_NS, "NS_DACR" }, //XXX verify
+// ArmISA::MISCREG_DACR_NS?
 // ArmISA::MISCREG_DACR_S?
 // ArmISA::MISCREG_DFSR?
-{ ArmISA::MISCREG_DFSR_NS, "NS_DFSR" }, //XXX verify
+// ArmISA::MISCREG_DFSR_NS?
 // ArmISA::MISCREG_DFSR_S?
 // ArmISA::MISCREG_IFSR?
-{ ArmISA::MISCREG_IFSR_NS, "NS_IFSR" },
+// ArmISA::MISCREG_IFSR_NS?
 // ArmISA::MISCREG_IFSR_S?
-{ ArmISA::MISCREG_ADFSR, "ADFSR" },
+// { ArmISA::MISCREG_ADFSR, "ADFSR" },
 // ArmISA::MISCREG_ADFSR_NS?
 // ArmISA::MISCREG_ADFSR_S?
-{ ArmISA::MISCREG_AIFSR, "AIFSR" },
+// ArmISA::MISCREG_AIFSR?
 // ArmISA::MISCREG_AIFSR_NS?
 // ArmISA::MISCREG_AIFSR_S?
 // ArmISA::MISCREG_HADFSR?
 // ArmISA::MISCREG_HAIFSR?
-{ ArmISA::MISCREG_HSR, "HSR" },
+// ArmISA::MISCREG_HSR?
 // ArmISA::MISCREG_DFAR?
-{ ArmISA::MISCREG_DFAR_NS, "NS_DFAR" }, //XXX verify
+// ArmISA::MISCREG_DFAR_NS?
 // ArmISA::MISCREG_DFAR_S?
 // ArmISA::MISCREG_IFAR?
-{ ArmISA::MISCREG_IFAR_NS, "NS_IFAR" }, //XXX verify
+// ArmISA::MISCREG_IFAR_NS?
 // ArmISA::MISCREG_IFAR_S?
-{ ArmISA::MISCREG_HDFAR, "HDFAR" },
-{ ArmISA::MISCREG_HIFAR, "HIFAR" },
-{ ArmISA::MISCREG_HPFAR, "HPFAR" },
+// ArmISA::MISCREG_HDFAR?
+// ArmISA::MISCREG_HIFAR?
+// ArmISA::MISCREG_HPFAR?
 { ArmISA::MISCREG_ICIALLUIS, "ICIALLUIS" },
 // ArmISA::MISCREG_BPIALLIS?
 // ArmISA::MISCREG_PAR?
-{ ArmISA::MISCREG_PAR_NS, "NS_PAR" }, //XXX verify
+// ArmISA::MISCREG_PAR_NS?
 // ArmISA::MISCREG_PAR_S?
 { ArmISA::MISCREG_ICIALLU, "ICIALLU" },
 { ArmISA::MISCREG_ICIMVAU, "ICIMVAU" },
@@ -445,50 +445,50 @@
 // ArmISA::MISCREG_L2CTLR?
 // ArmISA::MISCREG_L2ECTLR?
 // ArmISA::MISCREG_PRRR?
-{ ArmISA::MISCREG_PRRR_NS, "NS_PRRR" }, //XXX

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: CortexA76 fix missing registers for FastModel 11.17

2022-03-17 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57629 )


Change subject: fastmodel: CortexA76 fix missing registers for FastModel  
11.17

..

fastmodel: CortexA76 fix missing registers for FastModel 11.17

Change-Id: I1f6e2e92b91d0fe361a5ea88542a1e095a9f357b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57629
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/CortexA76/thread_context.cc
1 file changed, 64 insertions(+), 51 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc  
b/src/arch/arm/fastmodel/CortexA76/thread_context.cc

index ff82bbe..36c6458 100644
--- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
@@ -267,7 +267,7 @@
 { ArmISA::MISCREG_DBGOSLAR, "DBGOSLAR" },
 // ArmISA::MISCREG_DBGOSLSR?
 // ArmISA::MISCREG_DBGOSDLR?
-{ ArmISA::MISCREG_DBGPRCR, "DBGPRCR_EL1" }, //XXX verify
+// ArmISA::MISCREG_DBGPRCR?
 // ArmISA::MISCREG_DBGDSAR?
 { ArmISA::MISCREG_DBGCLAIMSET, "DBGCLAIMSET" },
 { ArmISA::MISCREG_DBGCLAIMCLR, "DBGCLAIMCLR" },
@@ -283,31 +283,31 @@

 // AArch32 CP15 registers (system control)
 { ArmISA::MISCREG_MIDR, "MIDR" },
-{ ArmISA::MISCREG_CTR, "CTR" },
-{ ArmISA::MISCREG_TCMTR, "TCMTR" },
-{ ArmISA::MISCREG_TLBTR, "TLBTR" },
-{ ArmISA::MISCREG_MPIDR, "MPIDR" },
-{ ArmISA::MISCREG_REVIDR, "REVIDR" },
-{ ArmISA::MISCREG_ID_PFR0, "ID_PFR0" },
-{ ArmISA::MISCREG_ID_PFR1, "ID_PFR1" },
-{ ArmISA::MISCREG_ID_DFR0, "ID_DFR0" },
-{ ArmISA::MISCREG_ID_AFR0, "ID_AFR0" },
-{ ArmISA::MISCREG_ID_MMFR0, "ID_MMFR0" },
-{ ArmISA::MISCREG_ID_MMFR1, "ID_MMFR1" },
-{ ArmISA::MISCREG_ID_MMFR2, "ID_MMFR2" },
-{ ArmISA::MISCREG_ID_MMFR3, "ID_MMFR3" },
-{ ArmISA::MISCREG_ID_MMFR4, "ID_MMFR4" },
-{ ArmISA::MISCREG_ID_ISAR0, "ID_ISAR0" },
-{ ArmISA::MISCREG_ID_ISAR1, "ID_ISAR1" },
-{ ArmISA::MISCREG_ID_ISAR2, "ID_ISAR2" },
-{ ArmISA::MISCREG_ID_ISAR3, "ID_ISAR3" },
-{ ArmISA::MISCREG_ID_ISAR4, "ID_ISAR4" },
-{ ArmISA::MISCREG_ID_ISAR5, "ID_ISAR5" },
-{ ArmISA::MISCREG_ID_ISAR6, "ID_ISAR6" },
-{ ArmISA::MISCREG_CCSIDR, "CCSIDR" },
-{ ArmISA::MISCREG_CLIDR, "CLIDR" },
-{ ArmISA::MISCREG_AIDR, "AIDR" },
-{ ArmISA::MISCREG_CSSELR, "CSSELR_EL1" }, //XXX verify
+// ArmISA::MISCREG_CTR?
+// ArmISA::MISCREG_TCMTR?
+// ArmISA::MISCREG_TLBTR?
+// ArmISA::MISCREG_MPIDR?
+// ArmISA::MISCREG_REVIDR?
+// ArmISA::MISCREG_ID_PFR0?
+// ArmISA::MISCREG_ID_PFR1?
+// ArmISA::MISCREG_ID_DFR0?
+// ArmISA::MISCREG_ID_AFR0?
+// ArmISA::MISCREG_ID_MMFR0?
+// ArmISA::MISCREG_ID_MMFR1?
+// ArmISA::MISCREG_ID_MMFR2?
+// ArmISA::MISCREG_ID_MMFR3?
+// ArmISA::MISCREG_ID_MMFR4?
+// ArmISA::MISCREG_ID_ISAR0?
+// ArmISA::MISCREG_ID_ISAR1?
+// ArmISA::MISCREG_ID_ISAR2?
+// ArmISA::MISCREG_ID_ISAR3?
+// ArmISA::MISCREG_ID_ISAR4?
+// ArmISA::MISCREG_ID_ISAR5?
+// ArmISA::MISCREG_ID_ISAR6?
+// ArmISA::MISCREG_CCSIDR?
+// ArmISA::MISCREG_CLIDR?
+// ArmISA::MISCREG_AIDR?
+// ArmISA::MISCREG_CSSELR?
 // ArmISA::MISCREG_CSSELR_NS?
 // ArmISA::MISCREG_CSSELR_S?
 // ArmISA::MISCREG_VPIDR?
@@ -327,7 +327,7 @@
 // ArmISA::MISCREG_HCR?
 // ArmISA::MISCREG_HDCR?
 // ArmISA::MISCREG_HCPTR?
-{ ArmISA::MISCREG_HSTR, "HSTR_EL2" }, //XXX verify
+// ArmISA::MISCREG_HSTR?
 // ArmISA::MISCREG_HACR?
 // ArmISA::MISCREG_TTBR0?
 // ArmISA::MISCREG_TTBR0_NS?
@@ -349,7 +349,7 @@
 // ArmISA::MISCREG_IFSR?
 // ArmISA::MISCREG_IFSR_NS?
 // ArmISA::MISCREG_IFSR_S?
-// { ArmISA::MISCREG_ADFSR, "ADFSR" },
+// ArmISA::MISCREG_ADFSR?
 // ArmISA::MISCREG_ADFSR_NS?
 // ArmISA::MISCREG_ADFSR_S?
 // ArmISA::MISCREG_AIFSR?
@@ -367,35 +367,35 @@
 // ArmISA::MISCREG_HDFAR?
 // ArmISA::MISCREG_HIFAR?
 // ArmISA::MISCREG_HPFAR?
-{ ArmISA::MISCREG_ICIALLUIS, "ICIALLUIS" },
+// ArmISA::MISCREG_ICIALLUIS?
 // ArmISA::MISCREG_BPIALLIS?
 // ArmISA::MISCREG_PAR?
 // ArmISA::MISCREG_PAR_NS?
 // ArmISA::MISCREG_PAR_S?
-{ ArmISA::MISCREG_ICIALLU, "ICIALLU" },
-{ ArmISA::MISCREG_ICIMVAU, "ICIMVAU" },
+// ArmISA::MISCREG_ICIALLU?
+// ArmISA::MISCREG_ICIMVAU?
 // ArmISA::MISCREG_CP15ISB?

[gem5-dev] Change in gem5/gem5[develop]: base: zero initialize the underlying storage of bitunion

2022-03-15 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57730 )



Change subject: base: zero initialize the underlying storage of bitunion
..

base: zero initialize the underlying storage of bitunion

To make the simulation result deterministic, we should make sure
everything is initiaized in a good state. In addition, this change
wouldn't break anything, since the original initial value is a random
value.

Change-Id: Icbed36b3fa6751cbda63e84443eaab6d865d9bd6
---
M src/base/bitunion.hh
1 file changed, 18 insertions(+), 1 deletion(-)



diff --git a/src/base/bitunion.hh b/src/base/bitunion.hh
index 92d747c..1fc0a94 100644
--- a/src/base/bitunion.hh
+++ b/src/base/bitunion.hh
@@ -261,7 +261,10 @@

 BitUnionOperators(const BitUnionOperators &) = default;

-BitUnionOperators() {}
+BitUnionOperators()
+{
+Base::__storage = {};
+}

 //Conversion operators.
 operator const typename Base::__StorageType () const

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icbed36b3fa6751cbda63e84443eaab6d865d9bd6
Gerrit-Change-Number: 57730
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: CortexA76 fix missing registers for FastModel 11.17

2022-03-14 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57629 )



Change subject: fastmodel: CortexA76 fix missing registers for FastModel  
11.17

..

fastmodel: CortexA76 fix missing registers for FastModel 11.17

Change-Id: I1f6e2e92b91d0fe361a5ea88542a1e095a9f357b
---
M src/arch/arm/fastmodel/CortexA76/thread_context.cc
1 file changed, 60 insertions(+), 51 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc  
b/src/arch/arm/fastmodel/CortexA76/thread_context.cc

index ff82bbe..36c6458 100644
--- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
@@ -267,7 +267,7 @@
 { ArmISA::MISCREG_DBGOSLAR, "DBGOSLAR" },
 // ArmISA::MISCREG_DBGOSLSR?
 // ArmISA::MISCREG_DBGOSDLR?
-{ ArmISA::MISCREG_DBGPRCR, "DBGPRCR_EL1" }, //XXX verify
+// ArmISA::MISCREG_DBGPRCR?
 // ArmISA::MISCREG_DBGDSAR?
 { ArmISA::MISCREG_DBGCLAIMSET, "DBGCLAIMSET" },
 { ArmISA::MISCREG_DBGCLAIMCLR, "DBGCLAIMCLR" },
@@ -283,31 +283,31 @@

 // AArch32 CP15 registers (system control)
 { ArmISA::MISCREG_MIDR, "MIDR" },
-{ ArmISA::MISCREG_CTR, "CTR" },
-{ ArmISA::MISCREG_TCMTR, "TCMTR" },
-{ ArmISA::MISCREG_TLBTR, "TLBTR" },
-{ ArmISA::MISCREG_MPIDR, "MPIDR" },
-{ ArmISA::MISCREG_REVIDR, "REVIDR" },
-{ ArmISA::MISCREG_ID_PFR0, "ID_PFR0" },
-{ ArmISA::MISCREG_ID_PFR1, "ID_PFR1" },
-{ ArmISA::MISCREG_ID_DFR0, "ID_DFR0" },
-{ ArmISA::MISCREG_ID_AFR0, "ID_AFR0" },
-{ ArmISA::MISCREG_ID_MMFR0, "ID_MMFR0" },
-{ ArmISA::MISCREG_ID_MMFR1, "ID_MMFR1" },
-{ ArmISA::MISCREG_ID_MMFR2, "ID_MMFR2" },
-{ ArmISA::MISCREG_ID_MMFR3, "ID_MMFR3" },
-{ ArmISA::MISCREG_ID_MMFR4, "ID_MMFR4" },
-{ ArmISA::MISCREG_ID_ISAR0, "ID_ISAR0" },
-{ ArmISA::MISCREG_ID_ISAR1, "ID_ISAR1" },
-{ ArmISA::MISCREG_ID_ISAR2, "ID_ISAR2" },
-{ ArmISA::MISCREG_ID_ISAR3, "ID_ISAR3" },
-{ ArmISA::MISCREG_ID_ISAR4, "ID_ISAR4" },
-{ ArmISA::MISCREG_ID_ISAR5, "ID_ISAR5" },
-{ ArmISA::MISCREG_ID_ISAR6, "ID_ISAR6" },
-{ ArmISA::MISCREG_CCSIDR, "CCSIDR" },
-{ ArmISA::MISCREG_CLIDR, "CLIDR" },
-{ ArmISA::MISCREG_AIDR, "AIDR" },
-{ ArmISA::MISCREG_CSSELR, "CSSELR_EL1" }, //XXX verify
+// ArmISA::MISCREG_CTR?
+// ArmISA::MISCREG_TCMTR?
+// ArmISA::MISCREG_TLBTR?
+// ArmISA::MISCREG_MPIDR?
+// ArmISA::MISCREG_REVIDR?
+// ArmISA::MISCREG_ID_PFR0?
+// ArmISA::MISCREG_ID_PFR1?
+// ArmISA::MISCREG_ID_DFR0?
+// ArmISA::MISCREG_ID_AFR0?
+// ArmISA::MISCREG_ID_MMFR0?
+// ArmISA::MISCREG_ID_MMFR1?
+// ArmISA::MISCREG_ID_MMFR2?
+// ArmISA::MISCREG_ID_MMFR3?
+// ArmISA::MISCREG_ID_MMFR4?
+// ArmISA::MISCREG_ID_ISAR0?
+// ArmISA::MISCREG_ID_ISAR1?
+// ArmISA::MISCREG_ID_ISAR2?
+// ArmISA::MISCREG_ID_ISAR3?
+// ArmISA::MISCREG_ID_ISAR4?
+// ArmISA::MISCREG_ID_ISAR5?
+// ArmISA::MISCREG_ID_ISAR6?
+// ArmISA::MISCREG_CCSIDR?
+// ArmISA::MISCREG_CLIDR?
+// ArmISA::MISCREG_AIDR?
+// ArmISA::MISCREG_CSSELR?
 // ArmISA::MISCREG_CSSELR_NS?
 // ArmISA::MISCREG_CSSELR_S?
 // ArmISA::MISCREG_VPIDR?
@@ -327,7 +327,7 @@
 // ArmISA::MISCREG_HCR?
 // ArmISA::MISCREG_HDCR?
 // ArmISA::MISCREG_HCPTR?
-{ ArmISA::MISCREG_HSTR, "HSTR_EL2" }, //XXX verify
+// ArmISA::MISCREG_HSTR?
 // ArmISA::MISCREG_HACR?
 // ArmISA::MISCREG_TTBR0?
 // ArmISA::MISCREG_TTBR0_NS?
@@ -349,7 +349,7 @@
 // ArmISA::MISCREG_IFSR?
 // ArmISA::MISCREG_IFSR_NS?
 // ArmISA::MISCREG_IFSR_S?
-// { ArmISA::MISCREG_ADFSR, "ADFSR" },
+// ArmISA::MISCREG_ADFSR?
 // ArmISA::MISCREG_ADFSR_NS?
 // ArmISA::MISCREG_ADFSR_S?
 // ArmISA::MISCREG_AIFSR?
@@ -367,35 +367,35 @@
 // ArmISA::MISCREG_HDFAR?
 // ArmISA::MISCREG_HIFAR?
 // ArmISA::MISCREG_HPFAR?
-{ ArmISA::MISCREG_ICIALLUIS, "ICIALLUIS" },
+// ArmISA::MISCREG_ICIALLUIS?
 // ArmISA::MISCREG_BPIALLIS?
 // ArmISA::MISCREG_PAR?
 // ArmISA::MISCREG_PAR_NS?
 // ArmISA::MISCREG_PAR_S?
-{ ArmISA::MISCREG_ICIALLU, "ICIALLU" },
-{ ArmISA::MISCREG_ICIMVAU, "ICIMVAU" },
+// ArmISA::MISCREG_ICIALLU?
+// ArmISA::MISCREG_ICIMVAU?
 // ArmISA::MISCREG_CP15ISB?
 // ArmISA::MISCREG_BPIALL?
 // ArmISA::MISCREG_BPIMVA?
-{ ArmISA::MISCREG_DCIMVAC, "DCIMVAC" },
-{ ArmISA::MISCREG_DCISW, "DCISW" },
-{ ArmISA::MISCREG_ATS1CPR, "ATS1CPR" },
-{

[gem5-dev] Change in gem5/gem5[develop]: cpu: System should skip invalid thread when iterating

2022-02-08 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56549 )



Change subject: cpu: System should skip invalid thread when iterating
..

cpu: System should skip invalid thread when iterating

In System structure, we use a vector to implement map for mapping id and
ThreadContext. Once the id is not assigned in order, it would create
some invalid ThreadContexts within the vector. We should skip those
invalid ThreadContexts when doing iterating.

Change-Id: If016d563c9cbd933e6e4791595e987808dff6d6a
---
M src/sim/system.cc
1 file changed, 36 insertions(+), 2 deletions(-)



diff --git a/src/sim/system.cc b/src/sim/system.cc
index db8f44c..29411dc 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -141,6 +141,9 @@
 System::Threads::findFree()
 {
 for (auto : threads) {
+if (thread.context == nullptr) {
+continue;
+}
 if (thread.context->status() == ThreadContext::Halted)
 return thread.context;
 }
@@ -152,6 +155,9 @@
 {
 int count = 0;
 for (auto : threads) {
+if (thread.context == nullptr) {
+continue;
+}
 auto status = thread.context->status();
 if (status != ThreadContext::Halted &&
 status != ThreadContext::Halting) {
@@ -273,8 +279,12 @@
 {
 bool all = true;
 liveEvents.push_back(event);
-for (auto *tc: threads)
+for (auto *tc: threads) {
+if (tc == nullptr) {
+continue;
+}
 all = tc->schedule(event) && all;
+}
 return all;
 }

@@ -283,8 +293,12 @@
 {
 bool all = true;
 liveEvents.remove(event);
-for (auto *tc: threads)
+for (auto *tc: threads) {
+if (tc == nullptr) {
+continue;
+}
 all = tc->remove(event) && all;
+}
 return all;
 }

@@ -352,6 +366,9 @@
 System::serialize(CheckpointOut ) const
 {
 for (auto : threads.threads) {
+if (t.context == nullptr) {
+continue;
+}
 Tick when = 0;
 if (t.resumeEvent && t.resumeEvent->scheduled())
 when = t.resumeEvent->when();
@@ -368,6 +385,9 @@
 System::unserialize(CheckpointIn )
 {
 for (auto : threads.threads) {
+if (t.context == nullptr) {
+continue;
+}
 Tick when = 0;
 ContextID id = t.context->contextId();
 if (!optParamIn(cp, csprintf("quiesceEndTick_%d", id), when) ||

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If016d563c9cbd933e6e4791595e987808dff6d6a
Gerrit-Change-Number: 56549
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Set simulation pause when breakpoint hit

2022-01-19 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55484 )


Change subject: fastmodel: Set simulation pause when breakpoint hit
..

fastmodel: Set simulation pause when breakpoint hit

The 7th parameter of breakpoint_set_code is dontStop. It seems the
fastmodel would prefetch something or do some evaluation ahead with the
flag set. This behavior prevents the instruction stepping feature of
gdb. The implementation of the feature is creating a breakpoint on the
next instruction and contining the simulation. Without stopping on the
breakpoint, it wouldn't invoke the breakpoint callback, since it may
evaulate the code we just want it to stop already. We should set the
dontStop to false to fix this issue.

Change-Id: Iaf8acd3235fa9625c1423ef34606e1fa5d0c531a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55484
Reviewed-by: Earl Ou 
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/iris/thread_context.cc
1 file changed, 24 insertions(+), 1 deletion(-)

Approvals:
  Earl Ou: Looks good to me, but someone else must approve
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc  
b/src/arch/arm/fastmodel/iris/thread_context.cc

index 16c8250..4a9c2db 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -181,7 +181,7 @@
 const auto _ids = getBpSpaceIds();
 for (auto sid: space_ids) {
 BpId id;
-call().breakpoint_set_code(_instId, id, pc, sid, 0, true);
+call().breakpoint_set_code(_instId, id, pc, sid, 0);
 it->second->ids.push_back(id);
 }
 }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iaf8acd3235fa9625c1423ef34606e1fa5d0c531a
Gerrit-Change-Number: 55484
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: ext: upgrade to googletest 1.11.x

2022-01-19 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55384 )


Change subject: ext: upgrade to googletest 1.11.x
..

ext: upgrade to googletest 1.11.x

Upgrade googletest to 1.11.x
upstream commit: 8306020a3e9eceafec65508868d7ab5c63bb41f7

sha1sum df8cdd26ee7cdf2a3d9c05a92d3630a96f406422 generated by command:
find . -type f ! -name SConscript ! -path "./.*" -print0 \
| sort -z | xargs -0 sha1sum | sha1sum

This upgrade is mainly for providing ConditionalMatcher support.

Change-Id: I27d971c02c59a3ad42c3002f1b4e1a8b18269c56
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55384
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Giacomo Travaglini 
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
---
M ext/googletest/googlemock/src/gmock-spec-builders.cc
M ext/googletest/googlemock/scripts/generator/cpp/tokenize.py
A ext/googletest/docs/quickstart-cmake.md
M ext/googletest/googlemock/test/gmock-matchers_test.cc
M ext/googletest/CONTRIBUTING.md
M ext/googletest/googletest/include/gtest/internal/custom/gtest.h
A ext/googletest/ci/linux-presubmit.sh
M ext/googletest/googletest/test/production.h
R ext/googletest/docs/gmock_cook_book.md
M ext/googletest/googletest/include/gtest/gtest_pred_impl.h
M ext/googletest/googletest/test/googletest-json-output-unittest.py
D ext/googletest/googlemock/test/gmock-generated-matchers_test.cc
R ext/googletest/docs/gmock_for_dummies.md
C ext/googletest/googletest/test/gtest_skip_check_output_test.py
M ext/googletest/googletest/test/gtest_xml_outfiles_test.py
D ext/googletest/googlemock/scripts/gmock_doctor.py
M ext/googletest/googletest/test/gtest-typed-test_test.cc
M ext/googletest/googletest/include/gtest/gtest.h
D ext/googletest/googletest/test/googletest-test2_test.cc
R ext/googletest/docs/faq.md
M ext/googletest/googletest/include/gtest/internal/gtest-internal.h
M ext/googletest/googlemock/test/gmock-nice-strict_test.cc
D ext/googletest/googlemock/include/gmock/gmock-generated-actions.h
M ext/googletest/googletest/test/googletest-death-test_ex_test.cc
M ext/googletest/googletest/test/googletest-param-test-test.cc
M ext/googletest/googlemock/include/gmock/internal/custom/gmock-port.h
A ext/googletest/docs/reference/testing.md
D ext/googletest/googlemock/include/gmock/gmock-generated-matchers.h.pump
M ext/googletest/googletest/cmake/internal_utils.cmake
D ext/googletest/library.json
M ext/googletest/googlemock/scripts/generator/cpp/ast.py
A ext/googletest/ci/macos-presubmit.sh
M ext/googletest/googlemock/src/gmock-matchers.cc
M ext/googletest/WORKSPACE
A ext/googletest/docs/index.md
M ext/googletest/googlemock/include/gmock/gmock-matchers.h
D ext/googletest/ci/travis.sh
M ext/googletest/googletest/include/gtest/gtest-spi.h
A ext/googletest/docs/_config.yml
A ext/googletest/docs/reference/actions.md
D ext/googletest/googlemock/docs/cheat_sheet.md
M ext/googletest/googlemock/include/gmock/gmock-cardinalities.h
M ext/googletest/googlemock/test/gmock-more-actions_test.cc
M ext/googletest/googletest/src/gtest-filepath.cc
A ext/googletest/docs/_data/navigation.yml
M ext/googletest/googletest/src/gtest-matchers.cc
D ext/googletest/googlemock/scripts/upload_gmock.py
M ext/googletest/googletest/test/gtest-unittest-api_test.cc
M ext/googletest/googletest/CMakeLists.txt
M ext/googletest/googletest/test/gtest_xml_output_unittest_.cc
M ext/googletest/googletest/samples/sample2.h
M ext/googletest/googletest/src/gtest-port.cc
M ext/googletest/googletest/test/gtest_xml_output_unittest.py
D ext/googletest/googletest/scripts/pump.py
M ext/googletest/googlemock/cmake/gmock.pc.in
A ext/googletest/googletest/scripts/README.md
M ext/googletest/README.md
D ext/googletest/googlemock/include/gmock/gmock-generated-actions.h.pump
M ext/googletest/googlemock/scripts/generator/cpp/gmock_class_test.py
M ext/googletest/googletest/test/gtest_throw_on_failure_ex_test.cc
M ext/googletest/googletest/test/googletest-listener-test.cc
M ext/googletest/BUILD.bazel
M ext/googletest/googlemock/test/gmock_link_test.h
M ext/googletest/googlemock/test/gmock_output_test_golden.txt
M ext/googletest/googlemock/scripts/fuse_gmock_files.py
A ext/googletest/docs/gmock_cheat_sheet.md
A ext/googletest/docs/_layouts/default.html
M ext/googletest/CMakeLists.txt
M ext/googletest/googletest/include/gtest/internal/gtest-param-util.h
M ext/googletest/googletest/src/gtest_main.cc
D ext/googletest/googlemock/CONTRIBUTORS
M ext/googletest/googletest/test/gtest_skip_test.cc
M ext/googletest/googletest/test/googletest-shuffle-test_.cc
A ext/googletest/googletest/test/googletest-setuptestsuite-test_.cc
D ext/googletest/googlemock/test/gmock-function-mocker_nc.cc
A ext/googletest/googlemock/scripts/README.md
M ext/googletest/googletest/test/googletest-param-test-test.h
M ext/googletest/googletest/test/gtest_xml_test_utils.py
M

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Correct the status of ThreadContext

2022-01-13 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55485 )



Change subject: fastmodel: Correct the status of ThreadContext
..

fastmodel: Correct the status of ThreadContext

Change-Id: I356fbd2c924ea95d78265cee4ff8881120585efd
---
M src/arch/arm/fastmodel/iris/thread_context.cc
1 file changed, 15 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc  
b/src/arch/arm/fastmodel/iris/thread_context.cc

index 4a9c2db..93f67c2 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -264,10 +264,15 @@
 uint64_t sInstId, bool syncEc, std::string _message_out)
 {
 if (fields.at("RUNNING").getAsBool()) {
-// If this is just simulation time starting up, don't do anything.
+// If this is just simulation time starting up, don't do anything  
except

+// status update.
+activate();
 return iris::E_ok;
 }

+// Update ThreadContext status.
+suspend();
+
 // If simulation time has stopped for any reason, IRIS helpfully clears
 // all stepping counters and we need to set them back. We might also  
need
 // to service events based on the current number of executed  
instructions.


--
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Gerrit-Branch: develop
Gerrit-Change-Id: I356fbd2c924ea95d78265cee4ff8881120585efd
Gerrit-Change-Number: 55485
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Set simulation pause when breakpoint hit

2022-01-13 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55484 )



Change subject: fastmodel: Set simulation pause when breakpoint hit
..

fastmodel: Set simulation pause when breakpoint hit

The 7th parameter of breakpoint_set_code is dontStop. It seems the
fastmodel would prefetch something or do some evaluation ahead with the
flag set. This behavior prevents the instruction stepping feature of
gdb. The implementation of the feature is creating a breakpoint on the
next instruction and contining the simulation. Without stopping on the
breakpoint, it wouldn't invoke the breakpoint callback, since it may
evaulate the code we just want it to stop already. We should set the
dontStop to false to fix this issue.

Change-Id: Iaf8acd3235fa9625c1423ef34606e1fa5d0c531a
---
M src/arch/arm/fastmodel/iris/thread_context.cc
1 file changed, 19 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc  
b/src/arch/arm/fastmodel/iris/thread_context.cc

index 16c8250..4a9c2db 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -181,7 +181,7 @@
 const auto _ids = getBpSpaceIds();
 for (auto sid: space_ids) {
 BpId id;
-call().breakpoint_set_code(_instId, id, pc, sid, 0, true);
+call().breakpoint_set_code(_instId, id, pc, sid, 0);
 it->second->ids.push_back(id);
 }
 }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iaf8acd3235fa9625c1423ef34606e1fa5d0c531a
Gerrit-Change-Number: 55484
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Mask el2_watchdog in VExpressFastmodel platform

2022-01-12 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55306 )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: dev-arm: Mask el2_watchdog in VExpressFastmodel platform
..

dev-arm: Mask el2_watchdog in VExpressFastmodel platform

el2_watchdog depends on SystemCounter. However, we have mask
system_counter in the platform. We should also mask the el2_watchdog
accordingly.

Change-Id: I2ed774549272438d654e0573ffe9f482a6659d37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55306
Reviewed-by: Gabe Black 
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/dev/arm/VExpressFastmodel.py
1 file changed, 19 insertions(+), 0 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, but someone else must approve
  kokoro: Regressions pass




diff --git a/src/dev/arm/VExpressFastmodel.py  
b/src/dev/arm/VExpressFastmodel.py

index 6f9a731..6e5ade4 100644
--- a/src/dev/arm/VExpressFastmodel.py
+++ b/src/dev/arm/VExpressFastmodel.py
@@ -45,6 +45,7 @@
 generic_timer = SubSystem()
 generic_timer_mem = SubSystem()
 sys_counter = SubSystem()
+el2_watchdog = SubSystem()

 def _on_chip_devices(self):
 return [

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2ed774549272438d654e0573ffe9f482a6659d37
Gerrit-Change-Number: 55306
Gerrit-PatchSet: 3
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Bobby Bruce 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Fix cluster build failed

2022-01-12 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55305 )


 (

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: fastmodel: Fix cluster build failed
..

fastmodel: Fix cluster build failed

FastModelCortexCluster subclasses don't have `type` property. They don't
need to be specified in sim_objects for generating *Params class.

Change-Id: Ic09e494042e05d68c890f9603b8b78a4a8d815a9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55305
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/CortexA76/SConscript
M src/arch/arm/fastmodel/CortexR52/SConscript
2 files changed, 18 insertions(+), 4 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/CortexA76/SConscript  
b/src/arch/arm/fastmodel/CortexA76/SConscript

index ce51268..016f613 100644
--- a/src/arch/arm/fastmodel/CortexA76/SConscript
+++ b/src/arch/arm/fastmodel/CortexA76/SConscript
@@ -39,8 +39,7 @@

 SimObject('FastModelCortexA76.py', sim_objects=[
 'FastModelCortexA76', 'FastModelCortexA76Cluster'] +
-[f'FastModelScxEvsCortexA76x{num}' for num in (1, 2, 3, 4)] +
-[f'FastModelCortexA76x{num}' for num in (1, 2, 3, 4)])
+[f'FastModelScxEvsCortexA76x{num}' for num in (1, 2, 3, 4)])
 Source('cortex_a76.cc')
 Source('evs.cc')
 Source('thread_context.cc')
diff --git a/src/arch/arm/fastmodel/CortexR52/SConscript  
b/src/arch/arm/fastmodel/CortexR52/SConscript

index 4e5e147..c1dc1fe 100644
--- a/src/arch/arm/fastmodel/CortexR52/SConscript
+++ b/src/arch/arm/fastmodel/CortexR52/SConscript
@@ -40,8 +40,7 @@

 SimObject('FastModelCortexR52.py', sim_objects=[
 'FastModelCortexR52', 'FastModelCortexR52Cluster'] +
-[f'FastModelScxEvsCortexR52x{num}' for num in (1, 2, 3, 4)] +
-[f'FastModelCortexR52x{num}' for num in (1, 2, 3, 4)])
+[f'FastModelScxEvsCortexR52x{num}' for num in (1, 2, 3, 4)])
 Source('cortex_r52.cc')
 Source('evs.cc')
 Source('thread_context.cc')

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic09e494042e05d68c890f9603b8b78a4a8d815a9
Gerrit-Change-Number: 55305
Gerrit-PatchSet: 4
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Add missing sim_objects of VExpressFastmodel

2022-01-11 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55304 )


Change subject: dev-arm: Add missing sim_objects of VExpressFastmodel
..

dev-arm: Add missing sim_objects of VExpressFastmodel

Change-Id: Ic6a9e5f1381c6c6412faa6d19f1448ca0e08b1e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55304
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/SConscript
1 file changed, 16 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/arm/SConscript b/src/dev/arm/SConscript
index e74b190..e59dc94 100644
--- a/src/dev/arm/SConscript
+++ b/src/dev/arm/SConscript
@@ -64,7 +64,7 @@
 enums=['NoMaliGpuType'], tags='arm isa')
 SimObject('VirtIOMMIO.py', sim_objects=['MmioVirtIO'], tags='arm isa')
 if env['USE_ARM_FASTMODEL']:
-SimObject('VExpressFastmodel.py', tags='arm isa')
+SimObject('VExpressFastmodel.py', sim_objects=[], tags='arm isa')

 Source('a9scu.cc', tags='arm isa')
 Source('amba_device.cc', tags='arm isa')

--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ic6a9e5f1381c6c6412faa6d19f1448ca0e08b1e7
Gerrit-Change-Number: 55304
Gerrit-PatchSet: 3
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: ext: googletest: upgrade to googletest 1.11

2022-01-11 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55384 )



Change subject: ext: googletest: upgrade to googletest 1.11
..

ext: googletest: upgrade to googletest 1.11

Upgrade googletest to 1.11
upstream commit: e2239ee6043f73722e7aa812a459f54a28552929
tag: release-1.11.0

sha1sum ce8186cedbc1d0da6d2fd9213c36a75b35f3d776 generated by command:
find . -type f ! -name SConscript ! -path "./.*" -print0 \
| sort -z | xargs -0 sha1sum | sha1sum

Change-Id: I27d971c02c59a3ad42c3002f1b4e1a8b18269c56
---
M ext/googletest/googlemock/src/gmock-spec-builders.cc
M ext/googletest/googlemock/scripts/generator/cpp/tokenize.py
A ext/googletest/docs/quickstart-cmake.md
M ext/googletest/googlemock/test/gmock-matchers_test.cc
M ext/googletest/CONTRIBUTING.md
M ext/googletest/googletest/include/gtest/internal/custom/gtest.h
A ext/googletest/ci/linux-presubmit.sh
M ext/googletest/googletest/test/production.h
R ext/googletest/docs/gmock_cook_book.md
M ext/googletest/googletest/include/gtest/gtest_pred_impl.h
M ext/googletest/googletest/test/googletest-json-output-unittest.py
D ext/googletest/googlemock/test/gmock-generated-matchers_test.cc
R ext/googletest/docs/gmock_for_dummies.md
C ext/googletest/googletest/test/gtest_skip_check_output_test.py
M ext/googletest/googletest/test/gtest_xml_outfiles_test.py
D ext/googletest/googlemock/scripts/gmock_doctor.py
M ext/googletest/googletest/test/gtest-typed-test_test.cc
M ext/googletest/googletest/include/gtest/gtest.h
D ext/googletest/googletest/test/googletest-test2_test.cc
R ext/googletest/docs/faq.md
M ext/googletest/googletest/include/gtest/internal/gtest-internal.h
M ext/googletest/googlemock/test/gmock-nice-strict_test.cc
D ext/googletest/googlemock/include/gmock/gmock-generated-actions.h
M ext/googletest/googletest/test/googletest-death-test_ex_test.cc
M ext/googletest/googletest/test/googletest-param-test-test.cc
M ext/googletest/googlemock/include/gmock/internal/custom/gmock-port.h
A ext/googletest/docs/reference/testing.md
D ext/googletest/googlemock/include/gmock/gmock-generated-matchers.h.pump
M ext/googletest/googletest/cmake/internal_utils.cmake
M ext/googletest/library.json
M ext/googletest/googlemock/scripts/generator/cpp/ast.py
A ext/googletest/ci/macos-presubmit.sh
M ext/googletest/googlemock/src/gmock-matchers.cc
M ext/googletest/WORKSPACE
A ext/googletest/docs/index.md
M ext/googletest/googlemock/include/gmock/gmock-matchers.h
D ext/googletest/ci/travis.sh
M ext/googletest/googletest/include/gtest/gtest-spi.h
A ext/googletest/docs/_config.yml
A ext/googletest/docs/reference/actions.md
D ext/googletest/googlemock/docs/cheat_sheet.md
M ext/googletest/googlemock/include/gmock/gmock-cardinalities.h
M ext/googletest/googlemock/test/gmock-more-actions_test.cc
M ext/googletest/googletest/src/gtest-filepath.cc
A ext/googletest/docs/_data/navigation.yml
M ext/googletest/googletest/src/gtest-matchers.cc
D ext/googletest/googlemock/scripts/upload_gmock.py
M ext/googletest/googletest/test/gtest-unittest-api_test.cc
M ext/googletest/googletest/CMakeLists.txt
M ext/googletest/googletest/test/gtest_xml_output_unittest_.cc
M ext/googletest/googletest/samples/sample2.h
M ext/googletest/googletest/src/gtest-port.cc
M ext/googletest/googletest/test/gtest_xml_output_unittest.py
D ext/googletest/googletest/scripts/pump.py
M ext/googletest/googlemock/cmake/gmock.pc.in
A ext/googletest/googletest/scripts/README.md
M ext/googletest/README.md
D ext/googletest/googlemock/include/gmock/gmock-generated-actions.h.pump
M ext/googletest/googlemock/scripts/generator/cpp/gmock_class_test.py
M ext/googletest/BUILD.bazel
M ext/googletest/googlemock/test/gmock_link_test.h
M ext/googletest/googlemock/test/gmock_output_test_golden.txt
M ext/googletest/googlemock/scripts/fuse_gmock_files.py
A ext/googletest/docs/gmock_cheat_sheet.md
A ext/googletest/docs/_layouts/default.html
M ext/googletest/CMakeLists.txt
M ext/googletest/googletest/include/gtest/internal/gtest-param-util.h
M ext/googletest/googletest/src/gtest_main.cc
D ext/googletest/googlemock/CONTRIBUTORS
M ext/googletest/googletest/test/gtest_skip_test.cc
M ext/googletest/googletest/test/googletest-shuffle-test_.cc
A ext/googletest/googletest/test/googletest-setuptestsuite-test_.cc
D ext/googletest/googlemock/test/gmock-function-mocker_nc.cc
A ext/googletest/googlemock/scripts/README.md
M ext/googletest/googletest/test/googletest-param-test-test.h
M ext/googletest/googletest/test/gtest_xml_test_utils.py
M ext/googletest/googlemock/scripts/generator/cpp/utils.py
M ext/googletest/googletest/test/googletest-output-test-golden-lin.txt
M ext/googletest/googlemock/include/gmock/gmock-actions.h
M ext/googletest/googletest/samples/sample6_unittest.cc
M ext/googletest/googletest/cmake/gtest.pc.in
R ext/googletest/CONTRIBUTORS
A ext/googletest/googletest/test/googletest-failfast-unittest.py
A ext/googletest/docs/pkgconfig.md
D

[gem5-dev] Change in gem5/gem5[develop]: configs: Fix parameters change when WalkCache is removed

2022-01-10 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55303 )


Change subject: configs: Fix parameters change when WalkCache is removed
..

configs: Fix parameters change when WalkCache is removed

Change-Id: I3e8d2ae60e64d18462f6782484be500c5c514003
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55303
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M configs/example/arm/devices.py
1 file changed, 15 insertions(+), 2 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 9122e7c..a488ab3 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -176,7 +176,7 @@
 class AtomicCluster(CpuCluster):
 def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
 cpu_config = [ ObjectList.cpu_list.get("AtomicSimpleCPU"), None,
-   None, None, None ]
+   None, None ]
 super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock,
 cpu_voltage, *cpu_config)
 def addL1(self):
@@ -185,7 +185,7 @@
 class KvmCluster(CpuCluster):
 def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
 cpu_config = [ ObjectList.cpu_list.get("ArmV8KvmCPU"), None, None,
-None, None ]
+None ]
 super(KvmCluster, self).__init__(system, num_cpus, cpu_clock,
  cpu_voltage, *cpu_config)
 def addL1(self):

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3e8d2ae60e64d18462f6782484be500c5c514003
Gerrit-Change-Number: 55303
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Gabe Black 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Add an example reset controller for IrisCpu

2022-01-10 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/54065 )


Change subject: fastmodel: Add an example reset controller for IrisCpu
..

fastmodel: Add an example reset controller for IrisCpu

The example reset controller provides a register interface to config
RVBAR and ability to reset the core.

Change-Id: I088ddde6f44ff9cc5914afb834ec07a8f7f269fa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54065
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
A src/arch/arm/fastmodel/reset_controller/SConscript
A src/arch/arm/fastmodel/reset_controller/FastModelResetControllerExample.py
A src/arch/arm/fastmodel/reset_controller/example.cc
A src/arch/arm/fastmodel/reset_controller/example.hh
4 files changed, 314 insertions(+), 0 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git  
a/src/arch/arm/fastmodel/reset_controller/FastModelResetControllerExample.py  
b/src/arch/arm/fastmodel/reset_controller/FastModelResetControllerExample.py

new file mode 100644
index 000..b9327f4
--- /dev/null
+++  
b/src/arch/arm/fastmodel/reset_controller/FastModelResetControllerExample.py

@@ -0,0 +1,40 @@
+# Copyright 2021 Google, Inc.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.params import *
+from m5.proxy import *
+
+from m5.objects.Device import BasicPioDevice
+from m5.objects.IntPin import IntSourcePin
+from m5.objects.Iris import IrisBaseCPU
+
+class FastModelResetControllerExample(BasicPioDevice):
+type = 'FastModelResetControllerExample'
+cxx_class = 'gem5::fastmodel::ResetControllerExample'
+cxx_header = 'arch/arm/fastmodel/reset_controller/example.hh'
+
+cpu = Param.IrisBaseCPU('target cpu')
+reset = IntSourcePin('reset pin')
+halt = IntSourcePin('halt pin')
diff --git a/src/arch/arm/fastmodel/reset_controller/SConscript  
b/src/arch/arm/fastmodel/reset_controller/SConscript

new file mode 100644
index 000..3230e5d
--- /dev/null
+++ b/src/arch/arm/fastmodel/reset_controller/SConscript
@@ -0,0 +1,34 @@
+# Copyright 2021 Google, Inc.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Mask el2_watchdog in VExpressFastmodel platform

2022-01-10 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55306 )



Change subject: dev-arm: Mask el2_watchdog in VExpressFastmodel platform
..

dev-arm: Mask el2_watchdog in VExpressFastmodel platform

el2_watchdog depends on SystemCounter. However, we have mask
system_counter in the platform. We should also mask the el2_watchdog
accordingly.

Change-Id: I2ed774549272438d654e0573ffe9f482a6659d37
---
M src/dev/arm/VExpressFastmodel.py
1 file changed, 14 insertions(+), 0 deletions(-)



diff --git a/src/dev/arm/VExpressFastmodel.py  
b/src/dev/arm/VExpressFastmodel.py

index 6f9a731..6e5ade4 100644
--- a/src/dev/arm/VExpressFastmodel.py
+++ b/src/dev/arm/VExpressFastmodel.py
@@ -45,6 +45,7 @@
 generic_timer = SubSystem()
 generic_timer_mem = SubSystem()
 sys_counter = SubSystem()
+el2_watchdog = SubSystem()

 def _on_chip_devices(self):
 return [

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Gerrit-Branch: develop
Gerrit-Change-Id: I2ed774549272438d654e0573ffe9f482a6659d37
Gerrit-Change-Number: 55306
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang 
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[gem5-dev] Change in gem5/gem5[develop]: configs: Fix parameters change when WalkCache is removed

2022-01-10 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55303 )



Change subject: configs: Fix parameters change when WalkCache is removed
..

configs: Fix parameters change when WalkCache is removed

Change-Id: I3e8d2ae60e64d18462f6782484be500c5c514003
---
M configs/example/arm/devices.py
1 file changed, 11 insertions(+), 2 deletions(-)



diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 9122e7c..a488ab3 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -176,7 +176,7 @@
 class AtomicCluster(CpuCluster):
 def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
 cpu_config = [ ObjectList.cpu_list.get("AtomicSimpleCPU"), None,
-   None, None, None ]
+   None, None ]
 super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock,
 cpu_voltage, *cpu_config)
 def addL1(self):
@@ -185,7 +185,7 @@
 class KvmCluster(CpuCluster):
 def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
 cpu_config = [ ObjectList.cpu_list.get("ArmV8KvmCPU"), None, None,
-None, None ]
+None ]
 super(KvmCluster, self).__init__(system, num_cpus, cpu_clock,
  cpu_voltage, *cpu_config)
 def addL1(self):

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Gerrit-Branch: develop
Gerrit-Change-Id: I3e8d2ae60e64d18462f6782484be500c5c514003
Gerrit-Change-Number: 55303
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang 
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Add missing sim_objects of VExpressFastmodel

2022-01-10 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55304 )



Change subject: dev-arm: Add missing sim_objects of VExpressFastmodel
..

dev-arm: Add missing sim_objects of VExpressFastmodel

Change-Id: Ic6a9e5f1381c6c6412faa6d19f1448ca0e08b1e7
---
M src/dev/arm/SConscript
1 file changed, 10 insertions(+), 1 deletion(-)



diff --git a/src/dev/arm/SConscript b/src/dev/arm/SConscript
index e74b190..8d2d9a9 100644
--- a/src/dev/arm/SConscript
+++ b/src/dev/arm/SConscript
@@ -64,7 +64,7 @@
 enums=['NoMaliGpuType'], tags='arm isa')
 SimObject('VirtIOMMIO.py', sim_objects=['MmioVirtIO'], tags='arm isa')
 if env['USE_ARM_FASTMODEL']:
-SimObject('VExpressFastmodel.py', tags='arm isa')
+SimObject('VExpressFastmodel.py', tags='arm isa', sim_objects=[])

 Source('a9scu.cc', tags='arm isa')
 Source('amba_device.cc', tags='arm isa')

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Gerrit-Change-Id: Ic6a9e5f1381c6c6412faa6d19f1448ca0e08b1e7
Gerrit-Change-Number: 55304
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Gerrit-Owner: Yu-hsin Wang 
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Fix cluster build failed

2022-01-10 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55305 )



Change subject: fastmodel: Fix cluster build failed
..

fastmodel: Fix cluster build failed

FastModelCortexCluster subclasses doesn't inherit from SimObject
directly. We don't need to specify them in the SConscript.

Change-Id: Ic09e494042e05d68c890f9603b8b78a4a8d815a9
---
M src/arch/arm/fastmodel/CortexA76/SConscript
M src/arch/arm/fastmodel/CortexR52/SConscript
2 files changed, 14 insertions(+), 4 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexA76/SConscript  
b/src/arch/arm/fastmodel/CortexA76/SConscript

index ce51268..016f613 100644
--- a/src/arch/arm/fastmodel/CortexA76/SConscript
+++ b/src/arch/arm/fastmodel/CortexA76/SConscript
@@ -39,8 +39,7 @@

 SimObject('FastModelCortexA76.py', sim_objects=[
 'FastModelCortexA76', 'FastModelCortexA76Cluster'] +
-[f'FastModelScxEvsCortexA76x{num}' for num in (1, 2, 3, 4)] +
-[f'FastModelCortexA76x{num}' for num in (1, 2, 3, 4)])
+[f'FastModelScxEvsCortexA76x{num}' for num in (1, 2, 3, 4)])
 Source('cortex_a76.cc')
 Source('evs.cc')
 Source('thread_context.cc')
diff --git a/src/arch/arm/fastmodel/CortexR52/SConscript  
b/src/arch/arm/fastmodel/CortexR52/SConscript

index 4e5e147..c1dc1fe 100644
--- a/src/arch/arm/fastmodel/CortexR52/SConscript
+++ b/src/arch/arm/fastmodel/CortexR52/SConscript
@@ -40,8 +40,7 @@

 SimObject('FastModelCortexR52.py', sim_objects=[
 'FastModelCortexR52', 'FastModelCortexR52Cluster'] +
-[f'FastModelScxEvsCortexR52x{num}' for num in (1, 2, 3, 4)] +
-[f'FastModelCortexR52x{num}' for num in (1, 2, 3, 4)])
+[f'FastModelScxEvsCortexR52x{num}' for num in (1, 2, 3, 4)])
 Source('cortex_r52.cc')
 Source('evs.cc')
 Source('thread_context.cc')

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Gerrit-Owner: Yu-hsin Wang 
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: gdb support Thumb-2 ISA

2021-12-16 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/54124 )


Change subject: arch-arm: gdb support Thumb-2 ISA
..

arch-arm: gdb support Thumb-2 ISA

From the document*1, we should allow 2,3,4 in kind check function for
supporting all kinds of ARM breakpoint.

1.  
https://sourceware.org/gdb/current/onlinedocs/gdb/ARM-Breakpoint-Kinds.html


Change-Id: I82bcb88cfe6e80e7f17cd6bb68a26a45ace7b174
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54124
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/remote_gdb.cc
1 file changed, 40 insertions(+), 2 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index 215c532..6e8923e 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -168,6 +168,20 @@

 using namespace ArmISA;

+namespace
+{
+
+//  
https://sourceware.org/gdb/current/onlinedocs/gdb/ARM-Breakpoint-Kinds.html

+enum class ArmBpKind
+{
+THUMB = 2,
+THUMB_2 = 3,
+ARM = 4,
+};
+
+} // namespace
+
+
 static bool
 tryTranslate(ThreadContext *tc, Addr addr)
 {
@@ -364,8 +378,14 @@
 bool
 RemoteGDB::checkBpKind(size_t kind)
 {
-// 2 for Thumb ISA, 4 for ARM ISA.
-return kind == 2 || kind == 4;
+switch (ArmBpKind(kind)) {
+  case ArmBpKind::THUMB:
+  case ArmBpKind::THUMB_2:
+  case ArmBpKind::ARM:
+return true;
+  default:
+return false;
+}
 }

 } // namespace gem5

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I82bcb88cfe6e80e7f17cd6bb68a26a45ace7b174
Gerrit-Change-Number: 54124
Gerrit-PatchSet: 5
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Philip Metzler 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Correct checkBpLen naming with checkBpKind

2021-12-16 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/54123 )


Change subject: base: Correct checkBpLen naming with checkBpKind
..

base: Correct checkBpLen naming with checkBpKind

In gdb document*1, the second parameter of checkpoint command(Z0, Z1) is
named after kind. Although underlying implementation probably considers
it as length*2, it's still good to follow the name described in gdb
document for avoiding any confusion.

Refs:
1. https://sourceware.org/gdb/onlinedocs/gdb/Packets.html
2. https://github.com/bminor/binutils-gdb/blob/master/gdb/arch-utils.h#L41

Change-Id: Ib4b585613b8018970b16355f96cdff2ce9d5bae6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54123
Reviewed-by: Daniel Carvalho 
Maintainer: Daniel Carvalho 
Tested-by: kokoro 
Reviewed-by: Giacomo Travaglini 
---
M src/arch/riscv/remote_gdb.hh
M src/arch/arm/remote_gdb.cc
M src/arch/arm/remote_gdb.hh
M src/arch/x86/remote_gdb.hh
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
6 files changed, 61 insertions(+), 36 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved
  Daniel Carvalho: Looks good to me, but someone else must approve; Looks  
good to me, approved

  kokoro: Regressions pass




diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index 2efa82f..215c532 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -362,10 +362,10 @@
 }

 bool
-RemoteGDB::checkBpLen(size_t len)
+RemoteGDB::checkBpKind(size_t kind)
 {
 // 2 for Thumb ISA, 4 for ARM ISA.
-return len == 2 || len == 4;
+return kind == 2 || kind == 4;
 }

 } // namespace gem5
diff --git a/src/arch/arm/remote_gdb.hh b/src/arch/arm/remote_gdb.hh
index cff6d4a..8e512a4 100644
--- a/src/arch/arm/remote_gdb.hh
+++ b/src/arch/arm/remote_gdb.hh
@@ -120,7 +120,7 @@
   public:
 RemoteGDB(System *_system, int _port);
 BaseGdbRegCache *gdbRegs() override;
-bool checkBpLen(size_t len) override;
+bool checkBpKind(size_t kind) override;
 std::vector
 availableFeatures() const override
 {
diff --git a/src/arch/riscv/remote_gdb.hh b/src/arch/riscv/remote_gdb.hh
index 40fe821..753859f 100644
--- a/src/arch/riscv/remote_gdb.hh
+++ b/src/arch/riscv/remote_gdb.hh
@@ -56,7 +56,7 @@

 bool acc(Addr addr, size_t len) override;
 // A breakpoint will be 2 bytes if it is compressed and 4 if not
-bool checkBpLen(size_t len) override { return len == 2 || len == 4; }
+bool checkBpKind(size_t kind) override { return kind == 2 || kind ==  
4; }


 class RiscvGdbRegCache : public BaseGdbRegCache
 {
diff --git a/src/arch/x86/remote_gdb.hh b/src/arch/x86/remote_gdb.hh
index 62176a5..dfa9177 100644
--- a/src/arch/x86/remote_gdb.hh
+++ b/src/arch/x86/remote_gdb.hh
@@ -58,7 +58,7 @@
 {
   protected:
 bool acc(Addr addr, size_t len);
-bool checkBpLen(size_t len) { return len == 1; }
+bool checkBpKind(size_t kind) { return kind == 1; }
 class X86GdbRegCache : public BaseGdbRegCache
 {
   using BaseGdbRegCache::BaseGdbRegCache;
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index 1437b75..798d09f 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -784,28 +784,28 @@
 }

 void
-BaseRemoteGDB::insertSoftBreak(Addr addr, size_t len)
+BaseRemoteGDB::insertSoftBreak(Addr addr, size_t kind)
 {
-if (!checkBpLen(len))
-throw BadClient("Invalid breakpoint length\n");
+if (!checkBpKind(kind))
+throw BadClient("Invalid breakpoint kind.\n");

-return insertHardBreak(addr, len);
+return insertHardBreak(addr, kind);
 }

 void
-BaseRemoteGDB::removeSoftBreak(Addr addr, size_t len)
+BaseRemoteGDB::removeSoftBreak(Addr addr, size_t kind)
 {
-if (!checkBpLen(len))
-throw BadClient("Invalid breakpoint length.\n");
+if (!checkBpKind(kind))
+throw BadClient("Invalid breakpoint kind.\n");

-return removeHardBreak(addr, len);
+return removeHardBreak(addr, kind);
 }

 void
-BaseRemoteGDB::insertHardBreak(Addr addr, size_t len)
+BaseRemoteGDB::insertHardBreak(Addr addr, size_t kind)
 {
-if (!checkBpLen(len))
-throw BadClient("Invalid breakpoint length\n");
+if (!checkBpKind(kind))
+throw BadClient("Invalid breakpoint kind.\n");

 DPRINTF(GDBMisc, "Inserting hardware breakpoint at %#x\n", addr);

@@ -817,10 +817,10 @@
 }

 void
-BaseRemoteGDB::removeHardBreak(Addr addr, size_t len)
+BaseRemoteGDB::removeHardBreak(Addr addr, size_t kind)
 {
-if (!checkBpLen(len))
-throw BadClient("Invalid breakpoint length\n");
+if (!checkBpKind(kind))
+throw BadClient("Invalid breakpoint kind.\n");

 DPRINTF(GDBMisc, "Removing hardware breakpoint at %#x\n", addr);

@@ -917,7 +917,7 @@
 };

 bool
-BaseRemoteGDB::checkBpLen(size_t len)
+BaseRemoteGDB::checkBpKind(size_t kind)
 {
 return true;
 }
@@ -1302,17 +1302,17 @@

[gem5-dev] Change in gem5/gem5[develop]: base: Correct checkBpLen naming with checkBpKind

2021-12-13 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/54123 )



Change subject: base: Correct checkBpLen naming with checkBpKind
..

base: Correct checkBpLen naming with checkBpKind

In gdb document*1, the second parameter of checkpoint command(Z0, Z1) is
named after kind. Although underlying implementation probably considers
it as length*2, it's still good to follow the name described in gdb
document for avoiding any confusion.

Refs:
1. https://sourceware.org/gdb/onlinedocs/gdb/Packets.html
2. https://github.com/bminor/binutils-gdb/blob/master/gdb/arch-utils.h#L41

Change-Id: Ib4b585613b8018970b16355f96cdff2ce9d5bae6
---
M src/arch/riscv/remote_gdb.hh
M src/arch/arm/remote_gdb.cc
M src/arch/arm/remote_gdb.hh
M src/arch/x86/remote_gdb.hh
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
6 files changed, 43 insertions(+), 25 deletions(-)



diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index 2efa82f..215c532 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -362,10 +362,10 @@
 }

 bool
-RemoteGDB::checkBpLen(size_t len)
+RemoteGDB::checkBpKind(size_t kind)
 {
 // 2 for Thumb ISA, 4 for ARM ISA.
-return len == 2 || len == 4;
+return kind == 2 || kind == 4;
 }

 } // namespace gem5
diff --git a/src/arch/arm/remote_gdb.hh b/src/arch/arm/remote_gdb.hh
index cff6d4a..8e512a4 100644
--- a/src/arch/arm/remote_gdb.hh
+++ b/src/arch/arm/remote_gdb.hh
@@ -120,7 +120,7 @@
   public:
 RemoteGDB(System *_system, int _port);
 BaseGdbRegCache *gdbRegs() override;
-bool checkBpLen(size_t len) override;
+bool checkBpKind(size_t kind) override;
 std::vector
 availableFeatures() const override
 {
diff --git a/src/arch/riscv/remote_gdb.hh b/src/arch/riscv/remote_gdb.hh
index 40fe821..753859f 100644
--- a/src/arch/riscv/remote_gdb.hh
+++ b/src/arch/riscv/remote_gdb.hh
@@ -56,7 +56,7 @@

 bool acc(Addr addr, size_t len) override;
 // A breakpoint will be 2 bytes if it is compressed and 4 if not
-bool checkBpLen(size_t len) override { return len == 2 || len == 4; }
+bool checkBpKind(size_t kind) override { return kind == 2 || kind ==  
4; }


 class RiscvGdbRegCache : public BaseGdbRegCache
 {
diff --git a/src/arch/x86/remote_gdb.hh b/src/arch/x86/remote_gdb.hh
index 62176a5..dfa9177 100644
--- a/src/arch/x86/remote_gdb.hh
+++ b/src/arch/x86/remote_gdb.hh
@@ -58,7 +58,7 @@
 {
   protected:
 bool acc(Addr addr, size_t len);
-bool checkBpLen(size_t len) { return len == 1; }
+bool checkBpKind(size_t kind) { return kind == 1; }
 class X86GdbRegCache : public BaseGdbRegCache
 {
   using BaseGdbRegCache::BaseGdbRegCache;
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index 1437b75..64e5e74 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -784,28 +784,28 @@
 }

 void
-BaseRemoteGDB::insertSoftBreak(Addr addr, size_t len)
+BaseRemoteGDB::insertSoftBreak(Addr addr, size_t kind)
 {
-if (!checkBpLen(len))
-throw BadClient("Invalid breakpoint length\n");
+if (!checkBpKind(kind))
+throw BadClient("Invalid breakpoint kind.\n");

-return insertHardBreak(addr, len);
+return insertHardBreak(addr, kind);
 }

 void
-BaseRemoteGDB::removeSoftBreak(Addr addr, size_t len)
+BaseRemoteGDB::removeSoftBreak(Addr addr, size_t kind)
 {
-if (!checkBpLen(len))
-throw BadClient("Invalid breakpoint length.\n");
+if (!checkBpKind(kind))
+throw BadClient("Invalid breakpoint kind.\n");

-return removeHardBreak(addr, len);
+return removeHardBreak(addr, kind);
 }

 void
-BaseRemoteGDB::insertHardBreak(Addr addr, size_t len)
+BaseRemoteGDB::insertHardBreak(Addr addr, size_t kind)
 {
-if (!checkBpLen(len))
-throw BadClient("Invalid breakpoint length\n");
+if (!checkBpKind(kind))
+throw BadClient("Invalid breakpoint kind.\n");

 DPRINTF(GDBMisc, "Inserting hardware breakpoint at %#x\n", addr);

@@ -817,10 +817,10 @@
 }

 void
-BaseRemoteGDB::removeHardBreak(Addr addr, size_t len)
+BaseRemoteGDB::removeHardBreak(Addr addr, size_t kind)
 {
-if (!checkBpLen(len))
-throw BadClient("Invalid breakpoint length\n");
+if (!checkBpKind(kind))
+throw BadClient("Invalid breakpoint kind.\n");

 DPRINTF(GDBMisc, "Removing hardware breakpoint at %#x\n", addr);

@@ -917,7 +917,7 @@
 };

 bool
-BaseRemoteGDB::checkBpLen(size_t len)
+BaseRemoteGDB::checkBpKind(size_t kind)
 {
 return true;
 }
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index 59bccc5..30800d6 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -313,10 +313,10 @@
 void descheduleInstCommitEvent(Event *ev);

 // Breakpoints.
-void insertSoftBreak(Addr addr, size_t len);
-void removeSoftBreak(Addr addr, size_t len);
-void insertHardBreak(Addr addr, size_t len);

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: gdb support Thumb-2 ISA

2021-12-13 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/54124 )



Change subject: arch-arm: gdb support Thumb-2 ISA
..

arch-arm: gdb support Thumb-2 ISA

From the document*1, we should allow 2,3,4 in kind check function for
supporting all kinds of ARM breakpoint.

1.  
https://sourceware.org/gdb/current/onlinedocs/gdb/ARM-Breakpoint-Kinds.html


Change-Id: I82bcb88cfe6e80e7f17cd6bb68a26a45ace7b174
---
M src/arch/arm/remote_gdb.cc
1 file changed, 16 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index 215c532..605a5ff 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -364,8 +364,8 @@
 bool
 RemoteGDB::checkBpKind(size_t kind)
 {
-// 2 for Thumb ISA, 4 for ARM ISA.
-return kind == 2 || kind == 4;
+//  
https://sourceware.org/gdb/current/onlinedocs/gdb/ARM-Breakpoint-Kinds.html

+return kind >= 2 && kind <= 4;
 }

 } // namespace gem5

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Gerrit-Change-Id: I82bcb88cfe6e80e7f17cd6bb68a26a45ace7b174
Gerrit-Change-Number: 54124
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Gerrit-Owner: Yu-hsin Wang 
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[gem5-dev] Change in gem5/gem5[develop]: systemc: Add -Wno-free-nonheap-object for building scheduler.cc

2021-12-13 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/54064 )


Change subject: systemc: Add -Wno-free-nonheap-object for building  
scheduler.cc

..

systemc: Add -Wno-free-nonheap-object for building scheduler.cc

GCC11 introduces a new warning, free-nonheap-object, which would check
if the code potentially calls delete with a nonheap object. The
scheduler is a global object, and its events members fall to this case.

Here's a simplified example.
https://godbolt.org/z/q6GqEfETa

We think this is a false positive warning, since we set auto delete to
false in the event constructor. To avoid performance penalty, we want to
keep current implementation. As the result, we disable the warning in
the SConscript.

Change-Id: I606ebfdec0af7c78d7bbb336faa1f587caa62855
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54064
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/systemc/core/SConscript
1 file changed, 33 insertions(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/systemc/core/SConscript b/src/systemc/core/SConscript
index 8805e9b..45bad4f 100644
--- a/src/systemc/core/SConscript
+++ b/src/systemc/core/SConscript
@@ -39,7 +39,6 @@
 Source('object.cc')
 Source('port.cc')
 Source('process.cc')
-Source('scheduler.cc')
 Source('sched_event.cc')
 Source('sensitivity.cc')
 Source('time.cc')
@@ -72,3 +71,11 @@
 append['CCFLAGS'] = [flag]
 break
 Source('sc_time_python.cc', append=append)
+
+# Disable the false positive warning for the event members of the  
scheduler.

+with gem5_scons.Configure(main) as conf:
+flag = '-Wno-free-nonheap-object'
+append = {}
+if conf.CheckCxxFlag(flag, autoadd=False):
+append['CCFLAGS'] = [flag]
+Source('scheduler.cc', append=append)

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I606ebfdec0af7c78d7bbb336faa1f587caa62855
Gerrit-Change-Number: 54064
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jui-min Lee 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Add a common reset controller for IrisCpu

2021-12-13 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/54065 )



Change subject: fastmodel: Add a common reset controller for IrisCpu
..

fastmodel: Add a common reset controller for IrisCpu

The reset controller provides a register interface to config RVBAR and
ability to reset the core.

Change-Id: I088ddde6f44ff9cc5914afb834ec07a8f7f269fa
---
M src/arch/arm/fastmodel/iris/Iris.py
A src/arch/arm/fastmodel/iris/reset_controller.cc
A src/arch/arm/fastmodel/iris/reset_controller.hh
M src/arch/arm/fastmodel/iris/SConscript
4 files changed, 240 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/fastmodel/iris/Iris.py  
b/src/arch/arm/fastmodel/iris/Iris.py

index 4979715..bcdfecb 100644
--- a/src/arch/arm/fastmodel/iris/Iris.py
+++ b/src/arch/arm/fastmodel/iris/Iris.py
@@ -43,6 +43,8 @@
 from m5.objects.BaseISA import BaseISA
 from m5.objects.BaseTLB import BaseTLB
 from m5.objects.BaseMMU import BaseMMU
+from m5.objects.Device import BasicPioDevice
+from m5.objects.IntPin import IntSourcePin

 class IrisTLB(BaseTLB):
 type = 'IrisTLB'
@@ -100,3 +102,12 @@

 def createInterruptController(self):
 self.interrupts = [ IrisInterrupts() for i in  
range(self.numThreads) ]

+
+class IrisResetController(BasicPioDevice):
+type = 'IrisResetController'
+cxx_class = 'gem5::Iris::ResetController'
+cxx_header = 'arch/arm/fastmodel/iris/reset_controller.hh'
+
+cpu = Param.IrisBaseCPU('target cpu')
+reset = IntSourcePin('reset pin')
+halt = IntSourcePin('halt pin')
diff --git a/src/arch/arm/fastmodel/iris/SConscript  
b/src/arch/arm/fastmodel/iris/SConscript

index 6635ca0..f611e1a 100644
--- a/src/arch/arm/fastmodel/iris/SConscript
+++ b/src/arch/arm/fastmodel/iris/SConscript
@@ -36,3 +36,5 @@
 Source('tlb.cc')

 Source('thread_context.cc')
+
+Source('reset_controller.cc')
diff --git a/src/arch/arm/fastmodel/iris/reset_controller.cc  
b/src/arch/arm/fastmodel/iris/reset_controller.cc

new file mode 100644
index 000..8decf39
--- /dev/null
+++ b/src/arch/arm/fastmodel/iris/reset_controller.cc
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2021 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/arm/fastmodel/iris/reset_controller.hh"
+
+#include "base/logging.hh"
+
+namespace gem5
+{
+namespace Iris
+{
+
+ResetController::CorePins::CorePins(const std::string _name)
+: reset(module_name + ".reset", 0, this),
+  halt(module_name + ".halt", 0, this)
+{}
+
+ResetController::Registers::Registers(
+const std::string _name, BaseCPU *c, CorePins *p)
+: RegisterBankLE(module_name, 0), cpu(c), pins(p),
+  nsrvbar(module_name + ".nsrvbar"),
+  rvbar(module_name + ".rvbar"),
+  reset(module_name + ".reset"),
+  halt(module_name + ".halt")
+{
+  panic_if(cpu == nullptr, "ResetController needs a target cpu.");
+  nsrvbar.writer(
+  [this] (auto , auto val)
+  {
+  cpu->setResetAddr(val, false);
+  });
+  rvbar.writer(
+  [this] (auto , auto val)
+  {
+  cpu->setResetAddr(val, true);
+  });
+  reset.writer(
+  [this] (auto , auto val)
+  {
+  if (!pins->reset.isConnected()) {
+  warn_once("%s is not connected.", pins->reset.name());
+  return;
+  }
+
+  if (val) pins->reset.raise();
+  else

[gem5-dev] Change in gem5/gem5[develop]: systemc: Add -Wno-free-nonheap-object for building scheduler.cc

2021-12-12 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/54064 )



Change subject: systemc: Add -Wno-free-nonheap-object for building  
scheduler.cc

..

systemc: Add -Wno-free-nonheap-object for building scheduler.cc

GCC11 introduces a new warning, free-nonheap-object, which would check
if the code potentially calls delete with a nonheap object. The
scheduler is a global object, and its events members fall to this case.

Here's a simplified example.
https://godbolt.org/z/q6GqEfETa

We think this is a false positive warning, since we set auto delete to
false in the event constructor. To avoid performance penalty, we want to
keep current implementation. As the result, we disable the warning in
the SConscript.

Change-Id: I606ebfdec0af7c78d7bbb336faa1f587caa62855
---
M src/systemc/core/SConscript
1 file changed, 29 insertions(+), 1 deletion(-)



diff --git a/src/systemc/core/SConscript b/src/systemc/core/SConscript
index 8805e9b..45bad4f 100644
--- a/src/systemc/core/SConscript
+++ b/src/systemc/core/SConscript
@@ -39,7 +39,6 @@
 Source('object.cc')
 Source('port.cc')
 Source('process.cc')
-Source('scheduler.cc')
 Source('sched_event.cc')
 Source('sensitivity.cc')
 Source('time.cc')
@@ -72,3 +71,11 @@
 append['CCFLAGS'] = [flag]
 break
 Source('sc_time_python.cc', append=append)
+
+# Disable the false positive warning for the event members of the  
scheduler.

+with gem5_scons.Configure(main) as conf:
+flag = '-Wno-free-nonheap-object'
+append = {}
+if conf.CheckCxxFlag(flag, autoadd=False):
+append['CCFLAGS'] = [flag]
+Source('scheduler.cc', append=append)

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I606ebfdec0af7c78d7bbb336faa1f587caa62855
Gerrit-Change-Number: 54064
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: systemc: Allocate event members of scheduler on heap

2021-12-12 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/54063 )



Change subject: systemc: Allocate event members of scheduler on heap
..

systemc: Allocate event members of scheduler on heap

GCC11 introduces a new warning, free-nonheap-object, which would check
if the code potentially calls delete with a nonheap object. The
scheduler is a global object, and its events member full to this case.

Here's a simplified example.
https://godbolt.org/z/q6GqEfETa

There are two ways to fix it. One is allocate the global scheduler on
heap. The other is allocate the event members on heap. Here we choose
the second way. The reason is even we move the scheduler to heap. The
code is still potentially calls delete to a member of a class which
doesn't make sense.

This cl fixes the problem.

Change-Id: I6c5fca36b63fa416197a0a54d1425ff96540a9f6
---
M src/systemc/core/scheduler.cc
M src/systemc/core/scheduler.hh
2 files changed, 87 insertions(+), 47 deletions(-)



diff --git a/src/systemc/core/scheduler.cc b/src/systemc/core/scheduler.cc
index 42a2ca4..1398fa04 100644
--- a/src/systemc/core/scheduler.cc
+++ b/src/systemc/core/scheduler.cc
@@ -27,6 +27,8 @@

 #include "systemc/core/scheduler.hh"

+#include 
+
 #include "base/fiber.hh"
 #include "base/logging.hh"
 #include "sim/eventq.hh"
@@ -44,14 +46,20 @@
 {

 Scheduler::Scheduler() :
-eq(nullptr), readyEvent(this, false, ReadyPriority),
-pauseEvent(this, false, PausePriority),
-stopEvent(this, false, StopPriority), _throwUp(nullptr),
-starvationEvent(this, false, StarvationPriority),
+eq(nullptr),
+readyEvent(std::make_unique(this, false, ReadyPriority)),
+pauseEvent(std::make_unique(this, false, PausePriority)),
+stopEvent(std::make_unique(this, false, StopPriority)),
+_throwUp(nullptr),
+starvationEvent(std::make_unique(
+this, false, StarvationPriority)),
 _elaborationDone(false), _started(false), _stopNow(false),
 _status(StatusOther), maxTick(gem5::MaxTick),
-maxTickEvent(this, false, MaxTickPriority),
-timeAdvancesEvent(this, false, TimeAdvancesPriority), _numCycles(0),
+maxTickEvent(std::make_unique(
+this, false, MaxTickPriority)),
+timeAdvancesEvent(std::make_unique(
+this, false, TimeAdvancesPriority)),
+_numCycles(0),
 _changeStamp(0), _current(nullptr), initDone(false), runToTime(true),
 runOnce(false)
 {}
@@ -79,18 +87,18 @@
 timeSlots.clear();

 // gem5 events.
-if (readyEvent.scheduled())
-deschedule();
-if (pauseEvent.scheduled())
-deschedule();
-if (stopEvent.scheduled())
-deschedule();
-if (starvationEvent.scheduled())
-deschedule();
-if (maxTickEvent.scheduled())
-deschedule();
-if (timeAdvancesEvent.scheduled())
-deschedule();
+if (readyEvent->scheduled())
+deschedule(readyEvent.get());
+if (pauseEvent->scheduled())
+deschedule(pauseEvent.get());
+if (stopEvent->scheduled())
+deschedule(stopEvent.get());
+if (starvationEvent->scheduled())
+deschedule(starvationEvent.get());
+if (maxTickEvent->scheduled())
+deschedule(maxTickEvent.get());
+if (timeAdvancesEvent->scheduled())
+deschedule(timeAdvancesEvent.get());

 Process *p;
 while ((p = initList.getNext()))
@@ -266,20 +274,20 @@
 Scheduler::scheduleReadyEvent()
 {
 // Schedule the evaluate and update phases.
-if (!readyEvent.scheduled()) {
-schedule();
-if (starvationEvent.scheduled())
-deschedule();
+if (!readyEvent->scheduled()) {
+schedule(readyEvent.get());
+if (starvationEvent->scheduled())
+deschedule(starvationEvent.get());
 }
 }

 void
 Scheduler::scheduleStarvationEvent()
 {
-if (!starvationEvent.scheduled()) {
-schedule();
-if (readyEvent.scheduled())
-deschedule();
+if (!starvationEvent->scheduled()) {
+schedule(starvationEvent.get());
+if (readyEvent->scheduled())
+deschedule(readyEvent.get());
 }
 }

@@ -416,20 +424,20 @@
 kernel->status(::sc_core::SC_RUNNING);
 }

-schedule(, maxTick);
+schedule(maxTickEvent.get(), maxTick);
 scheduleTimeAdvancesEvent();

 // Return to gem5 to let it run events, etc.
 gem5::Fiber::primaryFiber()->run();

-if (pauseEvent.scheduled())
-deschedule();
-if (stopEvent.scheduled())
-deschedule();
-if (maxTickEvent.scheduled())
-deschedule();
-if (starvationEvent.scheduled())
-deschedule();
+if (pauseEvent->scheduled())
+deschedule(pauseEvent.get());
+if (stopEvent->scheduled())
+deschedule(stopEvent.get());
+if (maxTickEvent->scheduled())
+deschedule(maxTickEvent.get());
+if (starvationEvent->scheduled())
+

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: CortexR52 implements setResetAddr interface

2021-12-07 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53328 )


Change subject: fastmodel: CortexR52 implements setResetAddr interface
..

fastmodel: CortexR52 implements setResetAddr interface

Change-Id: I45da1c1538430061cc89f666cb02aa5fe77abcba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53328
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Earl Ou 
---
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
M src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
M src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
M src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
8 files changed, 45 insertions(+), 2 deletions(-)

Approvals:
  Earl Ou: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc  
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc

index f5817f9..85a4c2a 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -79,6 +79,12 @@
 set_evs_param("vfp-enable_at_reset", params().vfp_enable_at_reset);
 }

+void
+CortexR52::setResetAddr(Addr addr, bool secure)
+{
+evs_base_cpu->setResetAddr(num, addr, secure);
+}
+
 Port &
 CortexR52::getPort(const std::string _name, PortID idx)
 {
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh  
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh

index c43052b..76c7d33 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
@@ -72,6 +72,8 @@

 void setCluster(CortexR52Cluster *_cluster, int _num);

+void setResetAddr(Addr addr, bool secure = false) override;
+
 Port (const std::string _name,
 PortID idx=InvalidPortID) override;
 };
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc  
b/src/arch/arm/fastmodel/CortexR52/evs.cc

index 5dcda4e..720f1cc 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -66,7 +66,7 @@
 void
 ScxEvsCortexR52::setResetAddr(int core, Addr addr, bool secure)
 {
-panic("Not implemented for R52.");
+this->corePins[core]->cfgvectable.set_state(0, addr);
 }

 template 
@@ -78,7 +78,8 @@
 amba(evs->amba[cpu], name + ".amba", -1),
 core_reset(name + ".core_reset", 0),
 poweron_reset(name + ".poweron_reset", 0),
-halt(name + ".halt", 0)
+halt(name + ".halt", 0),
+cfgvectable((name + "cfgvectable").c_str())
 {
 for (int i = 0; i < Evs::PpiCount; i++) {
 ppis.emplace_back(
@@ -87,6 +88,7 @@
 core_reset.signal_out.bind(evs->core_reset[cpu]);
 poweron_reset.signal_out.bind(evs->poweron_reset[cpu]);
 halt.signal_out.bind(evs->halt[cpu]);
+cfgvectable.bind(evs->cfgvectable[cpu]);
 }


diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh  
b/src/arch/arm/fastmodel/CortexR52/evs.hh

index a616a4d..fa9d7fe 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -79,6 +79,8 @@
 struct CorePins
 {
 using CoreInt = IntSinkPin;
+template 
+using SignalInitiator = amba_pv::signal_master_port;

 std::string name;
 Evs *evs;
@@ -107,6 +109,8 @@
 SignalSender core_reset;
 SignalSender poweron_reset;
 SignalSender halt;
+
+SignalInitiator cfgvectable;
 };

 std::vector> corePins;
diff --git a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa  
b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa

index a15fe74..36f3279 100644
--- a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
@@ -59,6 +59,9 @@
 self.ppi_0 => core.extppi_in_0;

 self.spi => core.spi_in;
+
+// Core reset addrs.
+self.cfgvectable => core.cfgvectable;
 }

 properties
@@ -74,6 +77,7 @@
 slave port poweron_reset[1];
 slave port halt[1];
 slave port top_reset;
+slave port cfgvectable[1];

 slave port clock_rate_s
 {
diff --git a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa  
b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa

index 9b992a4..492d289 100644
--- a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
@@ -60,6 +60,9 @@
 self.ppi_1 => core.extppi_in_1;

 self.spi => core.spi_in;
+
+// Core reset addrs.
+self.cfgvectable => core.cfgvectable;
 }

 properties
@@ -75,6 +78,7 @@
 slave port poweron_reset[2];
 slave port halt[2];
 slave port top_reset;
+slave port cfgvectable[2];

 slave port clock_rate_s
 {
diff --git a/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa  
b/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa

index

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: CortexA76 implements setResetAddr interface

2021-12-07 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53327 )


Change subject: fastmodel: CortexA76 implements setResetAddr interface
..

fastmodel: CortexA76 implements setResetAddr interface

Change-Id: I3612a62e2145d3442f01a69b21954fc00dd5ade9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53327
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Earl Ou 
---
M src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
M src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
M src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
M src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
8 files changed, 47 insertions(+), 3 deletions(-)

Approvals:
  Earl Ou: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc

index e9b468d..e77e734 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -95,6 +95,12 @@
 set_evs_param("vfp-enable_at_reset", params().vfp_enable_at_reset);
 }

+void
+CortexA76::setResetAddr(Addr addr, bool secure)
+{
+evs_base_cpu->setResetAddr(num, addr, secure);
+}
+
 Port &
 CortexA76::getPort(const std::string _name, PortID idx)
 {
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh

index 79d9eee..39f916e 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
@@ -74,6 +74,8 @@

 void setCluster(CortexA76Cluster *_cluster, int _num);

+void setResetAddr(Addr addr, bool secure = false) override;
+
 Port (const std::string _name,
 PortID idx=InvalidPortID) override;
 };
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc  
b/src/arch/arm/fastmodel/CortexA76/evs.cc

index 4b25014..935d139 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -67,7 +67,7 @@
 void
 ScxEvsCortexA76::setResetAddr(int core, Addr addr, bool secure)
 {
-panic("Not implemented for A76.");
+this->rvbaraddr[core]->set_state(0, addr);
 }

 template 
@@ -91,6 +91,8 @@
 new SignalReceiver(csprintf("vcpumntirq[%d]", i)));
 cntpnsirq.emplace_back(
 new SignalReceiver(csprintf("cntpnsirq[%d]", i)));
+rvbaraddr.emplace_back(new SignalInitiator(
+csprintf("rvbaraddr[%d]", i).c_str()));

 Base::cnthpirq[i].bind(cnthpirq[i]->signal_in);
 Base::cnthvirq[i].bind(cnthvirq[i]->signal_in);
@@ -101,6 +103,7 @@
 Base::pmuirq[i].bind(pmuirq[i]->signal_in);
 Base::vcpumntirq[i].bind(vcpumntirq[i]->signal_in);
 Base::cntpnsirq[i].bind(cntpnsirq[i]->signal_in);
+rvbaraddr[i]->bind(Base::rvbaraddr[i]);
 }

 clockRateControl.bind(this->clock_rate_s);
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh  
b/src/arch/arm/fastmodel/CortexA76/evs.hh

index 37f8363..7c834d0 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -69,10 +69,13 @@
 ClockRateControlInitiatorSocket clockRateControl;
 ClockRateControlInitiatorSocket periphClockRateControl;

-typedef sc_gem5::TlmTargetBaseWrapper<
+using TlmGicTarget = sc_gem5::TlmTargetBaseWrapper<
 64, svp_gicv3_comms::gicv3_comms_fw_if,
 svp_gicv3_comms::gicv3_comms_bw_if, 1,
-sc_core::SC_ONE_OR_MORE_BOUND> TlmGicTarget;
+sc_core::SC_ONE_OR_MORE_BOUND>;
+
+template 
+using SignalInitiator = amba_pv::signal_master_port;

 AmbaInitiator amba;
 std::vector> redist;
@@ -86,6 +89,7 @@
 std::vector> pmuirq;
 std::vector> vcpumntirq;
 std::vector> cntpnsirq;
+std::vector>> rvbaraddr;

 CortexA76Cluster *gem5CpuCluster;

diff --git a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa  
b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa

index 04dae41..b83efc6 100644
--- a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
@@ -57,6 +57,9 @@
 core.pmuirq => self.pmuirq;
 core.vcpumntirq => self.vcpumntirq;

+// Core reset addrs.
+self.rvbaraddr => core.rvbaraddr;
+
 // Clocks.
 clock1Hz.clk_out => clockDiv.clk_in;
 clock1Hz.clk_out => clockDivPeriph.clk_in;
@@ -96,4 +99,5 @@
 master port pmuirq[1];
 master port vcpumntirq[1];
 master port cntpnsirq[1];
+slave port rvbaraddr[1];
 }
diff --git a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa  
b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa

index 0279140..4ab0b07 100644
--- a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
+++

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: add setResetAddr interface

2021-12-07 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53326 )


Change subject: fastmodel: add setResetAddr interface
..

fastmodel: add setResetAddr interface

setResetAddr interface allows us to change the reset addr of fastmodel
cores. This will enable us to simulate hard reset or even complicated
boot sequence.

Change-Id: I0de828a4cd693119c0b44c74866efc1fffa81ace
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53326
Reviewed-by: Earl Ou 
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/iris/cpu.hh
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
5 files changed, 43 insertions(+), 0 deletions(-)

Approvals:
  Earl Ou: Looks good to me, but someone else must approve
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc  
b/src/arch/arm/fastmodel/CortexA76/evs.cc

index 4e0add6..4b25014 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -64,6 +64,13 @@
 }

 template 
+void
+ScxEvsCortexA76::setResetAddr(int core, Addr addr, bool secure)
+{
+panic("Not implemented for A76.");
+}
+
+template 
 ScxEvsCortexA76::ScxEvsCortexA76(
 const sc_core::sc_module_name _name, const Params ) :
 Base(mod_name), amba(Base::amba, p.name + ".amba", -1),
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh  
b/src/arch/arm/fastmodel/CortexA76/evs.hh

index f0e2ef5..37f8363 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -113,6 +113,8 @@
 void setSysCounterFrq(uint64_t sys_counter_frq) override;

 void setCluster(SimObject *cluster) override;
+
+void setResetAddr(int core, Addr addr, bool secure) override;
 };

 struct ScxEvsCortexA76x1Types
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc  
b/src/arch/arm/fastmodel/CortexR52/evs.cc

index 7f992f2..5dcda4e 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -63,6 +63,13 @@
 }

 template 
+void
+ScxEvsCortexR52::setResetAddr(int core, Addr addr, bool secure)
+{
+panic("Not implemented for R52.");
+}
+
+template 
 ScxEvsCortexR52::CorePins::CorePins(Evs *_evs, int _cpu) :
 name(csprintf("%s.cpu%s", _evs->name(), _cpu)),
 evs(_evs), cpu(_cpu),
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh  
b/src/arch/arm/fastmodel/CortexR52/evs.hh

index 20870df..a616a4d 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -156,6 +156,8 @@
 void setSysCounterFrq(uint64_t sys_counter_frq) override;

 void setCluster(SimObject *cluster) override;
+
+void setResetAddr(int core, Addr addr, bool secure) override;
 };

 struct ScxEvsCortexR52x1Types
diff --git a/src/arch/arm/fastmodel/iris/cpu.hh  
b/src/arch/arm/fastmodel/iris/cpu.hh

index 5cb8820..b43eb8e 100644
--- a/src/arch/arm/fastmodel/iris/cpu.hh
+++ b/src/arch/arm/fastmodel/iris/cpu.hh
@@ -51,6 +51,7 @@
 virtual void setClkPeriod(Tick clk_period) = 0;
 virtual void setSysCounterFrq(uint64_t sys_counter_frq) = 0;
 virtual void setCluster(SimObject *cluster) = 0;
+virtual void setResetAddr(int core, Addr addr, bool secure) = 0;
 };

 // This CPU class adds some mechanisms which help attach the gem5 and fast
@@ -86,6 +87,12 @@
 Counter totalInsts() const override;
 Counter totalOps() const override { return totalInsts(); }

+virtual void
+setResetAddr(Addr addr, bool secure = false)
+{
+panic("%s not implemented.", __FUNCTION__);
+}
+
   protected:
 sc_core::sc_module *evs;
 // Hold casted pointer to *evs.

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/53326
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0de828a4cd693119c0b44c74866efc1fffa81ace
Gerrit-Change-Number: 53326
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Philip Metzler 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: CortexA76 implements setResetAddr interface

2021-11-29 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53327 )



Change subject: fastmodel: CortexA76 implements setResetAddr interface
..

fastmodel: CortexA76 implements setResetAddr interface

Change-Id: I3612a62e2145d3442f01a69b21954fc00dd5ade9
---
M src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
M src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
M src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
M src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
8 files changed, 43 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc

index e9b468d..e77e734 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -95,6 +95,12 @@
 set_evs_param("vfp-enable_at_reset", params().vfp_enable_at_reset);
 }

+void
+CortexA76::setResetAddr(Addr addr, bool secure)
+{
+evs_base_cpu->setResetAddr(num, addr, secure);
+}
+
 Port &
 CortexA76::getPort(const std::string _name, PortID idx)
 {
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh

index 79d9eee..39f916e 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
@@ -74,6 +74,8 @@

 void setCluster(CortexA76Cluster *_cluster, int _num);

+void setResetAddr(Addr addr, bool secure = false) override;
+
 Port (const std::string _name,
 PortID idx=InvalidPortID) override;
 };
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc  
b/src/arch/arm/fastmodel/CortexA76/evs.cc

index 4b25014..935d139 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -67,7 +67,7 @@
 void
 ScxEvsCortexA76::setResetAddr(int core, Addr addr, bool secure)
 {
-panic("Not implemented for A76.");
+this->rvbaraddr[core]->set_state(0, addr);
 }

 template 
@@ -91,6 +91,8 @@
 new SignalReceiver(csprintf("vcpumntirq[%d]", i)));
 cntpnsirq.emplace_back(
 new SignalReceiver(csprintf("cntpnsirq[%d]", i)));
+rvbaraddr.emplace_back(new SignalInitiator(
+csprintf("rvbaraddr[%d]", i).c_str()));

 Base::cnthpirq[i].bind(cnthpirq[i]->signal_in);
 Base::cnthvirq[i].bind(cnthvirq[i]->signal_in);
@@ -101,6 +103,7 @@
 Base::pmuirq[i].bind(pmuirq[i]->signal_in);
 Base::vcpumntirq[i].bind(vcpumntirq[i]->signal_in);
 Base::cntpnsirq[i].bind(cntpnsirq[i]->signal_in);
+rvbaraddr[i]->bind(Base::rvbaraddr[i]);
 }

 clockRateControl.bind(this->clock_rate_s);
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh  
b/src/arch/arm/fastmodel/CortexA76/evs.hh

index 37f8363..7c834d0 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -69,10 +69,13 @@
 ClockRateControlInitiatorSocket clockRateControl;
 ClockRateControlInitiatorSocket periphClockRateControl;

-typedef sc_gem5::TlmTargetBaseWrapper<
+using TlmGicTarget = sc_gem5::TlmTargetBaseWrapper<
 64, svp_gicv3_comms::gicv3_comms_fw_if,
 svp_gicv3_comms::gicv3_comms_bw_if, 1,
-sc_core::SC_ONE_OR_MORE_BOUND> TlmGicTarget;
+sc_core::SC_ONE_OR_MORE_BOUND>;
+
+template 
+using SignalInitiator = amba_pv::signal_master_port;

 AmbaInitiator amba;
 std::vector> redist;
@@ -86,6 +89,7 @@
 std::vector> pmuirq;
 std::vector> vcpumntirq;
 std::vector> cntpnsirq;
+std::vector>> rvbaraddr;

 CortexA76Cluster *gem5CpuCluster;

diff --git a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa  
b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa

index 04dae41..b83efc6 100644
--- a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
@@ -57,6 +57,9 @@
 core.pmuirq => self.pmuirq;
 core.vcpumntirq => self.vcpumntirq;

+// Core reset addrs.
+self.rvbaraddr => core.rvbaraddr;
+
 // Clocks.
 clock1Hz.clk_out => clockDiv.clk_in;
 clock1Hz.clk_out => clockDivPeriph.clk_in;
@@ -96,4 +99,5 @@
 master port pmuirq[1];
 master port vcpumntirq[1];
 master port cntpnsirq[1];
+slave port rvbaraddr[1];
 }
diff --git a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa  
b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa

index 0279140..4ab0b07 100644
--- a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
@@ -57,6 +57,9 @@
 core.pmuirq => self.pmuirq;
 core.vcpumntirq => self.vcpumntirq;

+// Core reset addrs.
+self.rvbaraddr => core.rvbaraddr;
+
 // Clocks.

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: CortexR52 implements setResetAddr interface

2021-11-29 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53328 )



Change subject: fastmodel: CortexR52 implements setResetAddr interface
..

fastmodel: CortexR52 implements setResetAddr interface

Change-Id: I45da1c1538430061cc89f666cb02aa5fe77abcba
---
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
M src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
M src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
M src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
8 files changed, 41 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc  
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc

index f5817f9..85a4c2a 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -79,6 +79,12 @@
 set_evs_param("vfp-enable_at_reset", params().vfp_enable_at_reset);
 }

+void
+CortexR52::setResetAddr(Addr addr, bool secure)
+{
+evs_base_cpu->setResetAddr(num, addr, secure);
+}
+
 Port &
 CortexR52::getPort(const std::string _name, PortID idx)
 {
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh  
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh

index c43052b..76c7d33 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
@@ -72,6 +72,8 @@

 void setCluster(CortexR52Cluster *_cluster, int _num);

+void setResetAddr(Addr addr, bool secure = false) override;
+
 Port (const std::string _name,
 PortID idx=InvalidPortID) override;
 };
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc  
b/src/arch/arm/fastmodel/CortexR52/evs.cc

index 5dcda4e..720f1cc 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -66,7 +66,7 @@
 void
 ScxEvsCortexR52::setResetAddr(int core, Addr addr, bool secure)
 {
-panic("Not implemented for R52.");
+this->corePins[core]->cfgvectable.set_state(0, addr);
 }

 template 
@@ -78,7 +78,8 @@
 amba(evs->amba[cpu], name + ".amba", -1),
 core_reset(name + ".core_reset", 0),
 poweron_reset(name + ".poweron_reset", 0),
-halt(name + ".halt", 0)
+halt(name + ".halt", 0),
+cfgvectable((name + "cfgvectable").c_str())
 {
 for (int i = 0; i < Evs::PpiCount; i++) {
 ppis.emplace_back(
@@ -87,6 +88,7 @@
 core_reset.signal_out.bind(evs->core_reset[cpu]);
 poweron_reset.signal_out.bind(evs->poweron_reset[cpu]);
 halt.signal_out.bind(evs->halt[cpu]);
+cfgvectable.bind(evs->cfgvectable[cpu]);
 }


diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh  
b/src/arch/arm/fastmodel/CortexR52/evs.hh

index a616a4d..fa9d7fe 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -79,6 +79,8 @@
 struct CorePins
 {
 using CoreInt = IntSinkPin;
+template 
+using SignalInitiator = amba_pv::signal_master_port;

 std::string name;
 Evs *evs;
@@ -107,6 +109,8 @@
 SignalSender core_reset;
 SignalSender poweron_reset;
 SignalSender halt;
+
+SignalInitiator cfgvectable;
 };

 std::vector> corePins;
diff --git a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa  
b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa

index a15fe74..36f3279 100644
--- a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
@@ -59,6 +59,9 @@
 self.ppi_0 => core.extppi_in_0;

 self.spi => core.spi_in;
+
+// Core reset addrs.
+self.cfgvectable => core.cfgvectable;
 }

 properties
@@ -74,6 +77,7 @@
 slave port poweron_reset[1];
 slave port halt[1];
 slave port top_reset;
+slave port cfgvectable[1];

 slave port clock_rate_s
 {
diff --git a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa  
b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa

index 9b992a4..492d289 100644
--- a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
@@ -60,6 +60,9 @@
 self.ppi_1 => core.extppi_in_1;

 self.spi => core.spi_in;
+
+// Core reset addrs.
+self.cfgvectable => core.cfgvectable;
 }

 properties
@@ -75,6 +78,7 @@
 slave port poweron_reset[2];
 slave port halt[2];
 slave port top_reset;
+slave port cfgvectable[2];

 slave port clock_rate_s
 {
diff --git a/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa  
b/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa

index 18619b9..ed4837c 100644
--- a/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
@@ -61,6 +61,9 @@
 self.ppi_2 => core.extppi_in_2;

 self.spi => core.spi_in;
+
+// Core reset

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: add setResetAddr interface

2021-11-29 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53326 )



Change subject: fastmodel: add setResetAddr interface
..

fastmodel: add setResetAddr interface

setResetAddr interface allows us to change the reset addr of fastmodel
cores. This will enable us to simulate hard reset or even complicated
boot sequence.

Change-Id: I0de828a4cd693119c0b44c74866efc1fffa81ace
---
M src/arch/arm/fastmodel/iris/cpu.hh
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
5 files changed, 38 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc  
b/src/arch/arm/fastmodel/CortexA76/evs.cc

index 4e0add6..4b25014 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -64,6 +64,13 @@
 }

 template 
+void
+ScxEvsCortexA76::setResetAddr(int core, Addr addr, bool secure)
+{
+panic("Not implemented for A76.");
+}
+
+template 
 ScxEvsCortexA76::ScxEvsCortexA76(
 const sc_core::sc_module_name _name, const Params ) :
 Base(mod_name), amba(Base::amba, p.name + ".amba", -1),
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh  
b/src/arch/arm/fastmodel/CortexA76/evs.hh

index f0e2ef5..37f8363 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -113,6 +113,8 @@
 void setSysCounterFrq(uint64_t sys_counter_frq) override;

 void setCluster(SimObject *cluster) override;
+
+void setResetAddr(int core, Addr addr, bool secure) override;
 };

 struct ScxEvsCortexA76x1Types
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc  
b/src/arch/arm/fastmodel/CortexR52/evs.cc

index 7f992f2..5dcda4e 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -63,6 +63,13 @@
 }

 template 
+void
+ScxEvsCortexR52::setResetAddr(int core, Addr addr, bool secure)
+{
+panic("Not implemented for R52.");
+}
+
+template 
 ScxEvsCortexR52::CorePins::CorePins(Evs *_evs, int _cpu) :
 name(csprintf("%s.cpu%s", _evs->name(), _cpu)),
 evs(_evs), cpu(_cpu),
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh  
b/src/arch/arm/fastmodel/CortexR52/evs.hh

index 20870df..a616a4d 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -156,6 +156,8 @@
 void setSysCounterFrq(uint64_t sys_counter_frq) override;

 void setCluster(SimObject *cluster) override;
+
+void setResetAddr(int core, Addr addr, bool secure) override;
 };

 struct ScxEvsCortexR52x1Types
diff --git a/src/arch/arm/fastmodel/iris/cpu.hh  
b/src/arch/arm/fastmodel/iris/cpu.hh

index 5cb8820..b43eb8e 100644
--- a/src/arch/arm/fastmodel/iris/cpu.hh
+++ b/src/arch/arm/fastmodel/iris/cpu.hh
@@ -51,6 +51,7 @@
 virtual void setClkPeriod(Tick clk_period) = 0;
 virtual void setSysCounterFrq(uint64_t sys_counter_frq) = 0;
 virtual void setCluster(SimObject *cluster) = 0;
+virtual void setResetAddr(int core, Addr addr, bool secure) = 0;
 };

 // This CPU class adds some mechanisms which help attach the gem5 and fast
@@ -86,6 +87,12 @@
 Counter totalInsts() const override;
 Counter totalOps() const override { return totalInsts(); }

+virtual void
+setResetAddr(Addr addr, bool secure = false)
+{
+panic("%s not implemented.", __FUNCTION__);
+}
+
   protected:
 sc_core::sc_module *evs;
 // Hold casted pointer to *evs.

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Gerrit-Change-Number: 53326
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Gerrit-Owner: Yu-hsin Wang 
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[gem5-dev] Change in gem5/gem5[develop]: systemc: move tracefile registration into constructor

2021-11-21 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52923 )


Change subject: systemc: move tracefile registration into constructor
..

systemc: move tracefile registration into constructor

The TraceFile object needs to be registered into the scheduler for
triggering its trace function. For now only the TraceFile created by
sc_create_vcd_trace_file is registered automatically. This design is not
good for users to implement their own TraceFile class.

In addition, some libraries, ex Verilator, implement thier own trace file.
To bridge them into gem5, we also need the ability to create customized
TraceFile class.

Change-Id: I38fe510048655c6a2cd848a0a1263a66a1778eee
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52923
Reviewed-by: Earl Ou 
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/systemc/utils/sc_trace_file.cc
M src/systemc/utils/tracefile.cc
2 files changed, 29 insertions(+), 7 deletions(-)

Approvals:
  Earl Ou: Looks good to me, but someone else must approve
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/systemc/utils/sc_trace_file.cc  
b/src/systemc/utils/sc_trace_file.cc

index 38161ba..8eb 100644
--- a/src/systemc/utils/sc_trace_file.cc
+++ b/src/systemc/utils/sc_trace_file.cc
@@ -27,7 +27,6 @@

 #include 

-#include "systemc/core/scheduler.hh"
 #include "systemc/ext/channel/sc_signal_in_if.hh"
 #include "systemc/ext/core/sc_event.hh"
 #include "systemc/ext/core/sc_time.hh"
@@ -52,16 +51,12 @@
 sc_trace_file *
 sc_create_vcd_trace_file(const char *name)
 {
-auto tf = new ::sc_gem5::VcdTraceFile(name);
-::sc_gem5::scheduler.registerTraceFile(tf);
-return tf;
+return new ::sc_gem5::VcdTraceFile(name);
 }

 void
 sc_close_vcd_trace_file(sc_trace_file *tf)
 {
-::sc_gem5::scheduler.unregisterTraceFile(
-static_cast<::sc_gem5::TraceFile *>(tf));
 delete tf;
 }

diff --git a/src/systemc/utils/tracefile.cc b/src/systemc/utils/tracefile.cc
index a6cf952..0c54052 100644
--- a/src/systemc/utils/tracefile.cc
+++ b/src/systemc/utils/tracefile.cc
@@ -30,6 +30,7 @@
 #include 
 #include 

+#include "systemc/core/scheduler.hh"
 #include "systemc/core/time.hh"
 #include "systemc/ext/core/sc_main.hh"
 #include "systemc/ext/core/sc_time.hh"
@@ -41,10 +42,13 @@
 TraceFile::TraceFile(const std::string ) :
 _os(gem5::simout.create(name, true, true)), timeUnitTicks(0),
 timeUnitValue(0.0), timeUnitUnit(::sc_core::SC_PS), _traceDeltas(false)
-{}
+{
+::sc_gem5::scheduler.registerTraceFile(this);
+}

 TraceFile::~TraceFile()
 {
+::sc_gem5::scheduler.unregisterTraceFile(this);
 gem5::simout.close(_os);
 }


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I38fe510048655c6a2cd848a0a1263a66a1778eee
Gerrit-Change-Number: 52923
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jui-min Lee 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: systemc: move tracefile registration into constructor

2021-11-17 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52923 )



Change subject: systemc: move tracefile registration into constructor
..

systemc: move tracefile registration into constructor

The TraceFile object needs to be registered into the scheduler for
triggering its trace function. For now only the TraceFile created by
sc_create_vcd_trace_file is registered automatically. This design is not
good for users to implement their own TraceFile class.

In addition, some libraries, ex Verilator, implement thier own trace file.
To bridge them into gem5, we also need the ability to create customized
TraceFile class.

Change-Id: I38fe510048655c6a2cd848a0a1263a66a1778eee
---
M src/systemc/utils/sc_trace_file.cc
M src/systemc/utils/tracefile.cc
2 files changed, 24 insertions(+), 7 deletions(-)



diff --git a/src/systemc/utils/sc_trace_file.cc  
b/src/systemc/utils/sc_trace_file.cc

index 38161ba..8eb 100644
--- a/src/systemc/utils/sc_trace_file.cc
+++ b/src/systemc/utils/sc_trace_file.cc
@@ -27,7 +27,6 @@

 #include 

-#include "systemc/core/scheduler.hh"
 #include "systemc/ext/channel/sc_signal_in_if.hh"
 #include "systemc/ext/core/sc_event.hh"
 #include "systemc/ext/core/sc_time.hh"
@@ -52,16 +51,12 @@
 sc_trace_file *
 sc_create_vcd_trace_file(const char *name)
 {
-auto tf = new ::sc_gem5::VcdTraceFile(name);
-::sc_gem5::scheduler.registerTraceFile(tf);
-return tf;
+return new ::sc_gem5::VcdTraceFile(name);
 }

 void
 sc_close_vcd_trace_file(sc_trace_file *tf)
 {
-::sc_gem5::scheduler.unregisterTraceFile(
-static_cast<::sc_gem5::TraceFile *>(tf));
 delete tf;
 }

diff --git a/src/systemc/utils/tracefile.cc b/src/systemc/utils/tracefile.cc
index a6cf952..0c54052 100644
--- a/src/systemc/utils/tracefile.cc
+++ b/src/systemc/utils/tracefile.cc
@@ -30,6 +30,7 @@
 #include 
 #include 

+#include "systemc/core/scheduler.hh"
 #include "systemc/core/time.hh"
 #include "systemc/ext/core/sc_main.hh"
 #include "systemc/ext/core/sc_time.hh"
@@ -41,10 +42,13 @@
 TraceFile::TraceFile(const std::string ) :
 _os(gem5::simout.create(name, true, true)), timeUnitTicks(0),
 timeUnitValue(0.0), timeUnitUnit(::sc_core::SC_PS), _traceDeltas(false)
-{}
+{
+::sc_gem5::scheduler.registerTraceFile(this);
+}

 TraceFile::~TraceFile()
 {
+::sc_gem5::scheduler.unregisterTraceFile(this);
 gem5::simout.close(_os);
 }


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Gerrit-Owner: Yu-hsin Wang 
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: gdb support Thumb ISA

2021-11-11 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52624 )


 (

3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: gdb support Thumb ISA
..

arch-arm: gdb support Thumb ISA

BaseRemoteGDB only checks if the breakpoint size equals to MachInst size.
However, there are two kinds of instruction size in ARM. We should allow
the 16-bits breakpoint for Thumb ISA.

Change-Id: I79c0e1503092ecf233c719f2e354739edb8e6b25
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52624
Reviewed-by: Gabe Black 
Reviewed-by: Giacomo Travaglini 
Maintainer: Gabe Black 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/remote_gdb.cc
M src/arch/arm/remote_gdb.hh
2 files changed, 27 insertions(+), 0 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index d14e1c1..5382d51 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -361,4 +361,11 @@
 return 
 }

+bool
+RemoteGDB::checkBpLen(size_t len)
+{
+// 2 for Thumb ISA, 4 for ARM ISA.
+return len == 2 || len == 4;
+}
+
 } // namespace gem5
diff --git a/src/arch/arm/remote_gdb.hh b/src/arch/arm/remote_gdb.hh
index 5c5a37d..cff6d4a 100644
--- a/src/arch/arm/remote_gdb.hh
+++ b/src/arch/arm/remote_gdb.hh
@@ -120,6 +120,7 @@
   public:
 RemoteGDB(System *_system, int _port);
 BaseGdbRegCache *gdbRegs() override;
+bool checkBpLen(size_t len) override;
 std::vector
 availableFeatures() const override
 {

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Gerrit-Branch: develop
Gerrit-Change-Id: I79c0e1503092ecf233c719f2e354739edb8e6b25
Gerrit-Change-Number: 52624
Gerrit-PatchSet: 5
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: add missing override for remote_gdb

2021-11-11 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52685 )


Change subject: arch-arm: add missing override for remote_gdb
..

arch-arm: add missing override for remote_gdb

Change-Id: Iecbf56d97784367e416f950658515343734f3bec
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52685
Reviewed-by: Earl Ou 
Reviewed-by: Gabe Black 
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/remote_gdb.hh
1 file changed, 20 insertions(+), 4 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  Earl Ou: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/remote_gdb.hh b/src/arch/arm/remote_gdb.hh
index 847dee7..5c5a37d 100644
--- a/src/arch/arm/remote_gdb.hh
+++ b/src/arch/arm/remote_gdb.hh
@@ -63,7 +63,7 @@
 class RemoteGDB : public BaseRemoteGDB
 {
   protected:
-bool acc(Addr addr, size_t len);
+bool acc(Addr addr, size_t len) override;

 class AArch32GdbRegCache : public BaseGdbRegCache
 {
@@ -119,13 +119,14 @@

   public:
 RemoteGDB(System *_system, int _port);
-BaseGdbRegCache *gdbRegs();
+BaseGdbRegCache *gdbRegs() override;
 std::vector
-availableFeatures() const
+availableFeatures() const override
 {
 return {"qXfer:features:read+"};
 };
-bool getXferFeaturesRead(const std::string , std::string  
);

+bool getXferFeaturesRead(const std::string ,
+ std::string ) override;
 };

 } // namespace ArmISA

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Gerrit-Branch: develop
Gerrit-Change-Id: Iecbf56d97784367e416f950658515343734f3bec
Gerrit-Change-Number: 52685
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: add missing override for remote_gdb

2021-11-10 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52685 )



Change subject: arch-arm: add missing override for remote_gdb
..

arch-arm: add missing override for remote_gdb

Change-Id: Iecbf56d97784367e416f950658515343734f3bec
---
M src/arch/arm/remote_gdb.hh
1 file changed, 14 insertions(+), 4 deletions(-)



diff --git a/src/arch/arm/remote_gdb.hh b/src/arch/arm/remote_gdb.hh
index 847dee7..5c5a37d 100644
--- a/src/arch/arm/remote_gdb.hh
+++ b/src/arch/arm/remote_gdb.hh
@@ -63,7 +63,7 @@
 class RemoteGDB : public BaseRemoteGDB
 {
   protected:
-bool acc(Addr addr, size_t len);
+bool acc(Addr addr, size_t len) override;

 class AArch32GdbRegCache : public BaseGdbRegCache
 {
@@ -119,13 +119,14 @@

   public:
 RemoteGDB(System *_system, int _port);
-BaseGdbRegCache *gdbRegs();
+BaseGdbRegCache *gdbRegs() override;
 std::vector
-availableFeatures() const
+availableFeatures() const override
 {
 return {"qXfer:features:read+"};
 };
-bool getXferFeaturesRead(const std::string , std::string  
);

+bool getXferFeaturesRead(const std::string ,
+ std::string ) override;
 };

 } // namespace ArmISA

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Gerrit-Change-Id: Iecbf56d97784367e416f950658515343734f3bec
Gerrit-Change-Number: 52685
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Gerrit-Owner: Yu-hsin Wang 
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: CortexR52 support gdb

2021-11-10 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52623 )


Change subject: fastmodel: CortexR52 support gdb
..

fastmodel: CortexR52 support gdb

We change several things to support basic gdb.

1. Correct the memory translation.
memory_getUsefulAddressTranslations returns an empty list. So there's no
memory translation in R52.

2. Implement FPSCR for gdb collecting status.

3. Correct the breakpoint memory space.

Change-Id: Icc824502faec5ac228003f0de7e9dbe26babe7ef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52623
Reviewed-by: Gabe Black 
Reviewed-by: Earl Ou 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/CortexR52/thread_context.cc
M src/arch/arm/fastmodel/CortexR52/thread_context.hh
2 files changed, 47 insertions(+), 29 deletions(-)

Approvals:
  Earl Ou: Looks good to me, but someone else must approve
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/CortexR52/thread_context.cc  
b/src/arch/arm/fastmodel/CortexR52/thread_context.cc

index 0f2dfa0..269baf5 100644
--- a/src/arch/arm/fastmodel/CortexR52/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexR52/thread_context.cc
@@ -49,31 +49,9 @@
 bool
 CortexR52TC::translateAddress(Addr , Addr vaddr)
 {
-// Determine what memory spaces are currently active.
-Iris::CanonicalMsn in_msn;
-switch (ArmISA::currEL(this)) {
-  case ArmISA::EL3:
-in_msn = Iris::SecureMonitorMsn;
-break;
-  case ArmISA::EL2:
-in_msn = Iris::NsHypMsn;
-break;
-  default:
-in_msn = Iris::GuestMsn;
-break;
-}
-
-Iris::CanonicalMsn out_msn = ArmISA::isSecure(this) ?
-Iris::PhysicalMemorySecureMsn : Iris::PhysicalMemoryNonSecureMsn;
-
-// Figure out what memory spaces match the canonical numbers we need.
-iris::MemorySpaceId in = getMemorySpaceId(in_msn);
-iris::MemorySpaceId out = getMemorySpaceId(out_msn);
-
-panic_if(in == iris::IRIS_UINT64_MAX || out == iris::IRIS_UINT64_MAX,
-"Canonical IRIS memory space numbers not found.");
-
-return ThreadContext::translateAddress(paddr, out, vaddr, in);
+// No MMU here.
+paddr = vaddr;
+return true;
 }

 void
@@ -89,6 +67,23 @@
 extractResourceMap(ccRegIds, resources, ccRegIdxNameMap);
 }

+void
+CortexR52TC::sendFunctional(PacketPtr pkt)
+{
+  auto msn = Iris::PhysicalMemoryMsn;
+  auto id = getMemorySpaceId(msn);
+
+  auto addr = pkt->getAddr();
+  auto size = pkt->getSize();
+  auto data = pkt->getPtr();
+
+  pkt->makeResponse();
+  if (pkt->isRead())
+  readMem(id, addr, data, size);
+  else
+  writeMem(id, addr, data, size);
+}
+
 RegVal
 CortexR52TC::readIntReg(RegIndex reg_idx) const
 {
@@ -148,9 +143,7 @@
 CortexR52TC::getBpSpaceIds() const
 {
 if (bpSpaceIds.empty()) {
-std::vector msns{
-Iris::SecureMonitorMsn, Iris::GuestMsn, Iris::NsHypMsn,
-Iris::HypAppMsn};
+std::vector msns{Iris::GuestMsn,  
Iris::NsHypMsn};

 for (auto  : msns) {
 auto id = getMemorySpaceId(msn);
 if (id != iris::IRIS_UINT64_MAX)
@@ -609,7 +602,7 @@
 // ArmISA::MISCREG_NZCV?
 // ArmISA::MISCREG_DAIF?
 // ArmISA::MISCREG_FPCR?
-// ArmISA::MISCREG_FPSR?
+{ ArmISA::MISCREG_FPSCR, "FPSCR" },
 // ArmISA::MISCREG_DSPSR_EL0?
 // ArmISA::MISCREG_DLR_EL0?
 // ArmISA::MISCREG_SPSR_EL2?
diff --git a/src/arch/arm/fastmodel/CortexR52/thread_context.hh  
b/src/arch/arm/fastmodel/CortexR52/thread_context.hh

index eb12fee..7126a37 100644
--- a/src/arch/arm/fastmodel/CortexR52/thread_context.hh
+++ b/src/arch/arm/fastmodel/CortexR52/thread_context.hh
@@ -56,6 +56,7 @@
 bool translateAddress(Addr , Addr vaddr) override;

 void initFromIrisInstance(const ResourceMap ) override;
+void sendFunctional(PacketPtr pkt) override;

 // Since this CPU doesn't support aarch64, we override these two  
methods

 // and always assume we're 32 bit. More than likely we could be more

--
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Gerrit-Change-Id: Icc824502faec5ac228003f0de7e9dbe26babe7ef
Gerrit-Change-Number: 52623
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: CortexR52 support gdb

2021-11-09 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52623 )



Change subject: fastmodel: CortexR52 support gdb
..

fastmodel: CortexR52 support gdb

We change several things to support basic gdb.

1. Correct the memory translation.
memory_getUsefulAddressTranslations returns an empty list. So there's no
memory translation in R52.

2. Implement FPSCR for gdb collecting status.

3. Correct the breakpoint memory space.

Change-Id: Icc824502faec5ac228003f0de7e9dbe26babe7ef
---
M src/arch/arm/fastmodel/CortexR52/thread_context.cc
M src/arch/arm/fastmodel/CortexR52/thread_context.hh
2 files changed, 42 insertions(+), 29 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexR52/thread_context.cc  
b/src/arch/arm/fastmodel/CortexR52/thread_context.cc

index 0f2dfa0..269baf5 100644
--- a/src/arch/arm/fastmodel/CortexR52/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexR52/thread_context.cc
@@ -49,31 +49,9 @@
 bool
 CortexR52TC::translateAddress(Addr , Addr vaddr)
 {
-// Determine what memory spaces are currently active.
-Iris::CanonicalMsn in_msn;
-switch (ArmISA::currEL(this)) {
-  case ArmISA::EL3:
-in_msn = Iris::SecureMonitorMsn;
-break;
-  case ArmISA::EL2:
-in_msn = Iris::NsHypMsn;
-break;
-  default:
-in_msn = Iris::GuestMsn;
-break;
-}
-
-Iris::CanonicalMsn out_msn = ArmISA::isSecure(this) ?
-Iris::PhysicalMemorySecureMsn : Iris::PhysicalMemoryNonSecureMsn;
-
-// Figure out what memory spaces match the canonical numbers we need.
-iris::MemorySpaceId in = getMemorySpaceId(in_msn);
-iris::MemorySpaceId out = getMemorySpaceId(out_msn);
-
-panic_if(in == iris::IRIS_UINT64_MAX || out == iris::IRIS_UINT64_MAX,
-"Canonical IRIS memory space numbers not found.");
-
-return ThreadContext::translateAddress(paddr, out, vaddr, in);
+// No MMU here.
+paddr = vaddr;
+return true;
 }

 void
@@ -89,6 +67,23 @@
 extractResourceMap(ccRegIds, resources, ccRegIdxNameMap);
 }

+void
+CortexR52TC::sendFunctional(PacketPtr pkt)
+{
+  auto msn = Iris::PhysicalMemoryMsn;
+  auto id = getMemorySpaceId(msn);
+
+  auto addr = pkt->getAddr();
+  auto size = pkt->getSize();
+  auto data = pkt->getPtr();
+
+  pkt->makeResponse();
+  if (pkt->isRead())
+  readMem(id, addr, data, size);
+  else
+  writeMem(id, addr, data, size);
+}
+
 RegVal
 CortexR52TC::readIntReg(RegIndex reg_idx) const
 {
@@ -148,9 +143,7 @@
 CortexR52TC::getBpSpaceIds() const
 {
 if (bpSpaceIds.empty()) {
-std::vector msns{
-Iris::SecureMonitorMsn, Iris::GuestMsn, Iris::NsHypMsn,
-Iris::HypAppMsn};
+std::vector msns{Iris::GuestMsn,  
Iris::NsHypMsn};

 for (auto  : msns) {
 auto id = getMemorySpaceId(msn);
 if (id != iris::IRIS_UINT64_MAX)
@@ -609,7 +602,7 @@
 // ArmISA::MISCREG_NZCV?
 // ArmISA::MISCREG_DAIF?
 // ArmISA::MISCREG_FPCR?
-// ArmISA::MISCREG_FPSR?
+{ ArmISA::MISCREG_FPSCR, "FPSCR" },
 // ArmISA::MISCREG_DSPSR_EL0?
 // ArmISA::MISCREG_DLR_EL0?
 // ArmISA::MISCREG_SPSR_EL2?
diff --git a/src/arch/arm/fastmodel/CortexR52/thread_context.hh  
b/src/arch/arm/fastmodel/CortexR52/thread_context.hh

index eb12fee..7126a37 100644
--- a/src/arch/arm/fastmodel/CortexR52/thread_context.hh
+++ b/src/arch/arm/fastmodel/CortexR52/thread_context.hh
@@ -56,6 +56,7 @@
 bool translateAddress(Addr , Addr vaddr) override;

 void initFromIrisInstance(const ResourceMap ) override;
+void sendFunctional(PacketPtr pkt) override;

 // Since this CPU doesn't support aarch64, we override these two  
methods

 // and always assume we're 32 bit. More than likely we could be more

--
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: gdb support Thumb ISA

2021-11-09 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52624 )



Change subject: arch-arm: gdb support Thumb ISA
..

arch-arm: gdb support Thumb ISA

BaseRemoteGDB only checks if the breakpoint size equals to MachInst size.
However, there are two kinds of instruction size in ARM. We should allow
the 16-bits breakpoint for Thumb ISA.

Change-Id: I79c0e1503092ecf233c719f2e354739edb8e6b25
---
M src/arch/arm/remote_gdb.cc
M src/arch/arm/remote_gdb.hh
2 files changed, 21 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index d14e1c1..5382d51 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -361,4 +361,11 @@
 return 
 }

+bool
+RemoteGDB::checkBpLen(size_t len)
+{
+// 2 for Thumb ISA, 4 for ARM ISA.
+return len == 2 || len == 4;
+}
+
 } // namespace gem5
diff --git a/src/arch/arm/remote_gdb.hh b/src/arch/arm/remote_gdb.hh
index 847dee7..b8f224a 100644
--- a/src/arch/arm/remote_gdb.hh
+++ b/src/arch/arm/remote_gdb.hh
@@ -120,6 +120,7 @@
   public:
 RemoteGDB(System *_system, int _port);
 BaseGdbRegCache *gdbRegs();
+bool checkBpLen(size_t len) override;
 std::vector
 availableFeatures() const
 {

--
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[gem5-dev] Change in gem5/gem5[develop]: base: fix name setter doesn't pass correct stat style

2021-11-02 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52323 )


Change subject: base: fix name setter doesn't pass correct stat style
..

base: fix name setter doesn't pass correct stat style

There are two kinds of stats in the system. The old one requires an
unique name, while the new one requires an local name. The setName
function has a flag to specify the difference. In the constructor of
InfoAccess, it sets correct flag to the setName function. However, if
you set the name later with the setter, it wouldn't set the flag for
you. This leads the name conflict in new style stats with same local
name. We should also pass the correct flag in the name setter.

Change-Id: I0fcaad3cca65d0f2859c5f6cb28a00813a026a0c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52323
Reviewed-by: Andreas Sandberg 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Daniel Carvalho 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/base/statistics.cc
M src/base/statistics.hh
2 files changed, 36 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Andreas Sandberg: Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/base/statistics.cc b/src/base/statistics.cc
index 39e76b6..c380143 100644
--- a/src/base/statistics.cc
+++ b/src/base/statistics.cc
@@ -111,7 +111,7 @@
 Info *
 InfoAccess::info()
 {
-if (_info) {
+if (newStyleStats()) {
 // New-style stats
 return _info;
 } else {
@@ -125,7 +125,7 @@
 const Info *
 InfoAccess::info() const
 {
-if (_info) {
+if (newStyleStats()) {
 // New-style stats
 return _info;
 } else {
@@ -136,6 +136,12 @@
 }
 }

+bool
+InfoAccess::newStyleStats() const
+{
+return _info != nullptr;
+}
+
 Formula::Formula(Group *parent, const char *name, const char *desc)
 : DataWrapVec(
 parent, name, units::Unspecified::get(), desc)
diff --git a/src/base/statistics.hh b/src/base/statistics.hh
index 5079443..24cbf71 100644
--- a/src/base/statistics.hh
+++ b/src/base/statistics.hh
@@ -198,6 +198,9 @@
 /** Grab the information class for this statistic */
 const Info *info() const;

+/** Check if the info is new style stats */
+bool newStyleStats() const;
+
   public:
 InfoAccess()
 : _info(nullptr) {};
@@ -259,7 +262,7 @@
 parent->addStat(info);

 if (name) {
-info->setName(name, parent == nullptr);
+info->setName(name, !newStyleStats());
 info->flags.set(display);
 }

@@ -286,7 +289,7 @@
 name(const std::string )
 {
 Info *info = this->info();
-info->setName(name);
+info->setName(name, !newStyleStats());
 info->flags.set(display);
 return this->self();
 }

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Gerrit-Change-Id: I0fcaad3cca65d0f2859c5f6cb28a00813a026a0c
Gerrit-Change-Number: 52323
Gerrit-PatchSet: 4
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Gabe Black 
Gerrit-CC: Han-sheng Liu 
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[gem5-dev] Change in gem5/gem5[develop]: base: fix name setter doesn't pass correct stat style

2021-11-02 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52323 )



Change subject: base: fix name setter doesn't pass correct stat style
..

base: fix name setter doesn't pass correct stat style

There are two kinds of stats in the system. The old one requires an
unique name, while the new one requires an local name. The setName
function has a flag to specify the difference. In the constructor of
InfoAccess, it sets correct flag to the setName function. However, if
you set the name later with the setter, it wouldn't set the flag for
you. This leads the name conflict in new style stats with same local
name. We should also pass the correct flag in the name setter.

Change-Id: I0fcaad3cca65d0f2859c5f6cb28a00813a026a0c
---
M src/base/statistics.cc
M src/base/statistics.hh
2 files changed, 30 insertions(+), 4 deletions(-)



diff --git a/src/base/statistics.cc b/src/base/statistics.cc
index 39e76b6..65d7799 100644
--- a/src/base/statistics.cc
+++ b/src/base/statistics.cc
@@ -111,7 +111,7 @@
 Info *
 InfoAccess::info()
 {
-if (_info) {
+if (newStyleState()) {
 // New-style stats
 return _info;
 } else {
@@ -125,7 +125,7 @@
 const Info *
 InfoAccess::info() const
 {
-if (_info) {
+if (newStyleState()) {
 // New-style stats
 return _info;
 } else {
@@ -136,6 +136,12 @@
 }
 }

+bool
+InfoAccess::newStyleState() const
+{
+return _info != nullptr;
+}
+
 Formula::Formula(Group *parent, const char *name, const char *desc)
 : DataWrapVec(
 parent, name, units::Unspecified::get(), desc)
diff --git a/src/base/statistics.hh b/src/base/statistics.hh
index 5079443..02e7dac 100644
--- a/src/base/statistics.hh
+++ b/src/base/statistics.hh
@@ -198,6 +198,9 @@
 /** Grab the information class for this statistic */
 const Info *info() const;

+/** Check if the info is new style stats */
+bool newStyleState() const;
+
   public:
 InfoAccess()
 : _info(nullptr) {};
@@ -259,7 +262,7 @@
 parent->addStat(info);

 if (name) {
-info->setName(name, parent == nullptr);
+info->setName(name, !newStyleState());
 info->flags.set(display);
 }

@@ -286,7 +289,7 @@
 name(const std::string )
 {
 Info *info = this->info();
-info->setName(name);
+info->setName(name, !newStyleState());
 info->flags.set(display);
 return this->self();
 }

--
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Adopt the gem5 namespace

2021-11-01 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52263 )


Change subject: fastmodel: Adopt the gem5 namespace
..

fastmodel: Adopt the gem5 namespace

Change-Id: I2317a2593fafcce26a30d8d7b900e844daa64714
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52263
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/common/signal_sender.hh
1 file changed, 20 insertions(+), 2 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/common/signal_sender.hh  
b/src/arch/arm/fastmodel/common/signal_sender.hh

index dbd4526..f4772cf 100644
--- a/src/arch/arm/fastmodel/common/signal_sender.hh
+++ b/src/arch/arm/fastmodel/common/signal_sender.hh
@@ -35,7 +35,11 @@

 #include "dev/intpin.hh"

-namespace FastModel
+namespace gem5
+{
+
+GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
+namespace fastmodel
 {

 class SignalSender : public IntSinkPinBase
@@ -53,6 +57,7 @@
 void lowerOnDevice() override { signal_out.set_state(id, false); }
 };

-} // namespace FastModel
+} // namespace fastmodel
+} // namespace gem5

 #endif  // __ARCH_ARM_FASTMODEL_COMMON_SIGNAL_SENDER_HH__

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Gerrit-Change-Id: I2317a2593fafcce26a30d8d7b900e844daa64714
Gerrit-Change-Number: 52263
Gerrit-PatchSet: 3
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: misc: Adopt the gem5 namespace

2021-11-01 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52263 )



Change subject: misc: Adopt the gem5 namespace
..

misc: Adopt the gem5 namespace

Change-Id: I2317a2593fafcce26a30d8d7b900e844daa64714
---
M src/arch/arm/fastmodel/common/signal_sender.hh
1 file changed, 16 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/fastmodel/common/signal_sender.hh  
b/src/arch/arm/fastmodel/common/signal_sender.hh

index dbd4526..f4772cf 100644
--- a/src/arch/arm/fastmodel/common/signal_sender.hh
+++ b/src/arch/arm/fastmodel/common/signal_sender.hh
@@ -35,7 +35,11 @@

 #include "dev/intpin.hh"

-namespace FastModel
+namespace gem5
+{
+
+GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
+namespace fastmodel
 {

 class SignalSender : public IntSinkPinBase
@@ -53,6 +57,7 @@
 void lowerOnDevice() override { signal_out.set_state(id, false); }
 };

-} // namespace FastModel
+} // namespace fastmodel
+} // namespace gem5

 #endif  // __ARCH_ARM_FASTMODEL_COMMON_SIGNAL_SENDER_HH__

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[gem5-dev] Change in gem5/gem5[develop]: mem: Fix offset when loading a memory image

2021-09-02 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49907 )



Change subject: mem: Fix offset when loading a memory image
..

mem: Fix offset when loading a memory image

Change-Id: I5e98979fe3105771c0ba27ba32d9edcbcb72aadd
---
M src/mem/abstract_mem.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index 03f2557..8e24ab2 100644
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -89,7 +89,7 @@
 if (!range.contains(image_range.start())) {
 warn("%s: Moving image from %s to memory address range %s.",
 name(), image_range.to_string(), range.to_string());
-image = image.offset(range.start());
+image = image.offset(range.start() - image_range.start());
 image_range = AddrRange(image.minAddr(), image.maxAddr());
 }
 panic_if(!image_range.isSubset(range), "%s: memory image %s doesn't  
fit.",


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5e98979fe3105771c0ba27ba32d9edcbcb72aadd
Gerrit-Change-Number: 49907
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: add size check for AdvSIMD copy

2021-09-01 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49827 )


Change subject: arch-arm: add size check for AdvSIMD copy
..

arch-arm: add size check for AdvSIMD copy

imm5_pos and size are the output of findLsbSet. When imm5 is zero,
imm5_pos and size are 64 which will cause assert fail in the following
bits calls. We detect this case and return an Unknown instruction.

Change-Id: I4ed2513267fff5b5bdb81723617ff74fb9f82482
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49827
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/isa/formats/neon64.isa
1 file changed, 12 insertions(+), 0 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/isa/formats/neon64.isa  
b/src/arch/arm/isa/formats/neon64.isa

index 1948a34..660d118 100644
--- a/src/arch/arm/isa/formats/neon64.isa
+++ b/src/arch/arm/isa/formats/neon64.isa
@@ -1205,6 +1205,9 @@
 if (!q || (imm4 & mask(imm5_pos)))
 return new Unknown64(machInst);

+if (imm5_pos > 3)
+return new Unknown64(machInst);
+
 index1 = bits(imm5, 4, imm5_pos + 1);  // dst
 index2 = bits(imm4, 3, imm5_pos);  // src

@@ -1224,6 +1227,9 @@

 switch (imm4) {
   case 0x0:
+if (imm5_pos > 3)
+return new Unknown64(machInst);
+
 index1 = bits(imm5, 4, imm5_pos + 1);
 switch (imm5_pos) {
   case 0:
@@ -1289,6 +1295,9 @@
 return new Unknown64(machInst);
 }
   case 0x5:
+if (imm5_pos > 3)
+return new Unknown64(machInst);
+
 index1 = bits(imm5, 4, imm5_pos + 1);
 switch (imm5_pos) {
   case 0:
@@ -2431,6 +2440,9 @@
 IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);

 uint8_t size = findLsbSet(imm5);
+if (size > 3)
+return new Unknown64(machInst);
+
 uint8_t index = bits(imm5, 4, size + 1);

 return decodeNeonUTwoShiftUReg(

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4ed2513267fff5b5bdb81723617ff74fb9f82482
Gerrit-Change-Number: 49827
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: add size check for AdvSIMD copy

2021-09-01 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49827 )



Change subject: arch-arm: add size check for AdvSIMD copy
..

arch-arm: add size check for AdvSIMD copy

imm5_pos and size are the output of findLsbSet. When imm5 is zero,
imm5_pos and size are 64 which will cause assert fail in the following
bits calls. We detect this case and return an Unknown instruction.

Change-Id: I4ed2513267fff5b5bdb81723617ff74fb9f82482
---
M src/arch/arm/isa/formats/neon64.isa
1 file changed, 12 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/isa/formats/neon64.isa  
b/src/arch/arm/isa/formats/neon64.isa

index 1948a34..660d118 100644
--- a/src/arch/arm/isa/formats/neon64.isa
+++ b/src/arch/arm/isa/formats/neon64.isa
@@ -1205,6 +1205,9 @@
 if (!q || (imm4 & mask(imm5_pos)))
 return new Unknown64(machInst);

+if (imm5_pos > 3)
+return new Unknown64(machInst);
+
 index1 = bits(imm5, 4, imm5_pos + 1);  // dst
 index2 = bits(imm4, 3, imm5_pos);  // src

@@ -1224,6 +1227,9 @@

 switch (imm4) {
   case 0x0:
+if (imm5_pos > 3)
+return new Unknown64(machInst);
+
 index1 = bits(imm5, 4, imm5_pos + 1);
 switch (imm5_pos) {
   case 0:
@@ -1289,6 +1295,9 @@
 return new Unknown64(machInst);
 }
   case 0x5:
+if (imm5_pos > 3)
+return new Unknown64(machInst);
+
 index1 = bits(imm5, 4, imm5_pos + 1);
 switch (imm5_pos) {
   case 0:
@@ -2431,6 +2440,9 @@
 IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);

 uint8_t size = findLsbSet(imm5);
+if (size > 3)
+return new Unknown64(machInst);
+
 uint8_t index = bits(imm5, 4, size + 1);

 return decodeNeonUTwoShiftUReg(

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4ed2513267fff5b5bdb81723617ff74fb9f82482
Gerrit-Change-Number: 49827
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: export CortexR52 ext_slave port

2021-08-31 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49650 )


Change subject: fastmodel: export CortexR52 ext_slave port
..

fastmodel: export CortexR52 ext_slave port

Change-Id: I38788d934424cf264152fc689a3e48b84733f068
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49650
Reviewed-by: Earl Ou 
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
M src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
M src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
M src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
8 files changed, 20 insertions(+), 2 deletions(-)

Approvals:
  Earl Ou: Looks good to me, approved
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py  
b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py

index 9404edf..6530854 100644
--- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
+++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
@@ -29,7 +29,7 @@

 from m5.objects.ArmInterrupts import ArmInterrupts
 from m5.objects.ArmISA import ArmISA
-from m5.objects.FastModel import AmbaInitiatorSocket
+from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
 from m5.objects.IntPin import VectorIntSinkPin
 from m5.objects.Iris import IrisBaseCPU
 from m5.objects.SystemC import SystemC_ScModule
@@ -107,6 +107,8 @@

 spi = VectorIntSinkPin('SPI inputs (0-959)')

+ext_slave = AmbaTargetSocket(64, 'AMBA target socket')
+
 CLUSTER_ID = Param.UInt16(0, "CLUSTER_ID[15:8] equivalent to " \
 "CFGMPIDRAFF2, CLUSTER_ID[7:0] equivalent to CFGMPIDRAFF1")
 DBGROMADDR = Param.UInt32(0, "Equivalent to CFGDBGROMADDR")
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc  
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc

index 4f14e7e..35e4e07 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -150,6 +150,9 @@
 {
 if (if_name == "spi") {
 return evs->gem5_getPort(if_name, idx);
+} else if (if_name == "ext_slave") {
+assert(idx == InvalidPortID);
+return evs->gem5_getPort(if_name, idx);
 } else {
 return SimObject::getPort(if_name, idx);
 }
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc  
b/src/arch/arm/fastmodel/CortexR52/evs.cc

index 90612ae..f4e091e 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -81,7 +81,8 @@
 ScxEvsCortexR52::ScxEvsCortexR52(
 const sc_core::sc_module_name _name, const Params ) :
 Base(mod_name),
-params(p)
+params(p),
+ext_slave(Base::ext_slave, p.name + ".ext_slave", -1)
 {
 for (int i = 0; i < CoreCount; i++)
 corePins.emplace_back(new CorePins(this, i));
@@ -115,6 +116,8 @@
 return this->corePins.at(idx)->flash;
 } else if (if_name == "amba") {
 return this->corePins.at(idx)->amba;
+} else if (if_name == "ext_slave") {
+return this->ext_slave;
 } else if (if_name == "spi") {
 return *this->spis.at(idx);
 } else if (if_name.substr(0, 3) == "ppi") {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh  
b/src/arch/arm/fastmodel/CortexR52/evs.hh

index b27e7e2..d0c1253 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -114,6 +114,8 @@

 const Params 

+AmbaTarget ext_slave;
+
   public:
 ScxEvsCortexR52(const Params ) : ScxEvsCortexR52(p.name.c_str(), p)  
{}
 ScxEvsCortexR52(const sc_core::sc_module_name _name, const Params  
);
diff --git a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa  
b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa

index 9ed73a6..720d66f 100644
--- a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
@@ -44,6 +44,7 @@
 core.llpp_m => self.llpp;
 core.flash_m => self.flash;
 core.pvbus_core_m => self.amba;
+self.ext_slave => core.ext_slave_s;

 // Clocks.
 clock1Hz.clk_out => clockDiv.clk_in;
@@ -64,6 +65,7 @@
 master port llpp[1];
 master port flash[1];
 master port amba[1];
+slave port ext_slave;

 slave port clock_rate_s
 {
diff --git a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa  
b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa

index 147d2e9..bcbf1f4 100644
--- a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
@@ -44,6 +44,7 @@
 core.llpp_m => self.llpp;
 core.flash_m => self.flash;
 core.pvbus_core_m => self.amba;
+self.ext_slave

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: export CortexR52 reset and halt signals

2021-08-31 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49651 )


Change subject: fastmodel: export CortexR52 reset and halt signals
..

fastmodel: export CortexR52 reset and halt signals

Change-Id: I44a26bad1a91009dbef586ab5d860352d51e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49651
Reviewed-by: Earl Ou 
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
M src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
M src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
M src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
8 files changed, 69 insertions(+), 5 deletions(-)

Approvals:
  Earl Ou: Looks good to me, approved
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py  
b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py

index 6530854..710584d 100644
--- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
+++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
@@ -30,7 +30,7 @@
 from m5.objects.ArmInterrupts import ArmInterrupts
 from m5.objects.ArmISA import ArmISA
 from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
-from m5.objects.IntPin import VectorIntSinkPin
+from m5.objects.IntPin import IntSinkPin, VectorIntSinkPin
 from m5.objects.Iris import IrisBaseCPU
 from m5.objects.SystemC import SystemC_ScModule

@@ -46,6 +46,11 @@
 llpp = AmbaInitiatorSocket(64, 'Low Latency Peripheral Port')
 flash = AmbaInitiatorSocket(64, 'Flash')
 amba = AmbaInitiatorSocket(64, 'AMBA initiator socket')
+core_reset = IntSinkPin('Raising this signal will put the core into ' \
+'reset mode.')
+poweron_reset = IntSinkPin('Power on reset. Initializes all the ' \
+   'processor logic, including debug logic.')
+halt = IntSinkPin('Raising this signal will put the core into halt  
mode.')


 CFGEND = Param.Bool(False, "Endianness configuration at reset.  0, " \
 "little endian. 1, big endian.")
@@ -108,6 +113,7 @@
 spi = VectorIntSinkPin('SPI inputs (0-959)')

 ext_slave = AmbaTargetSocket(64, 'AMBA target socket')
+top_reset = IntSinkPin('This signal resets timer and interrupt  
controller.')


 CLUSTER_ID = Param.UInt16(0, "CLUSTER_ID[15:8] equivalent to " \
 "CFGMPIDRAFF2, CLUSTER_ID[7:0] equivalent to CFGMPIDRAFF1")
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc  
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc

index 35e4e07..f5817f9 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -86,7 +86,9 @@
 // Since PPIs are indexed both by core and by number, modify the  
name

 // to hold the core number.
 return evs->gem5_getPort(csprintf("%s_%d", if_name, num), idx);
-} else if (if_name == "amba" || if_name == "llpp" || if_name  
== "flash") {
+} else if (if_name == "amba" || if_name == "llpp" || if_name  
== "flash" ||

+   if_name == "core_reset" || if_name == "poweron_reset" ||
+   if_name == "halt") {
 // Since these ports are scalar per core, use the core number as  
the

 // index. Also verify that that index is not being used.
 assert(idx == InvalidPortID);
@@ -150,7 +152,7 @@
 {
 if (if_name == "spi") {
 return evs->gem5_getPort(if_name, idx);
-} else if (if_name == "ext_slave") {
+} else if (if_name == "ext_slave" || if_name == "top_reset") {
 assert(idx == InvalidPortID);
 return evs->gem5_getPort(if_name, idx);
 } else {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc  
b/src/arch/arm/fastmodel/CortexR52/evs.cc

index f4e091e..7f992f2 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -68,12 +68,18 @@
 evs(_evs), cpu(_cpu),
 llpp(evs->llpp[cpu], name + ".llpp", -1),
 flash(evs->flash[cpu], name + ".flash", -1),
-amba(evs->amba[cpu], name + ".amba", -1)
+amba(evs->amba[cpu], name + ".amba", -1),
+core_reset(name + ".core_reset", 0),
+poweron_reset(name + ".poweron_reset", 0),
+halt(name + ".halt", 0)
 {
 for (int i = 0; i < Evs::PpiCount; i++) {
 ppis.emplace_back(
 new CoreInt(csprintf("%s.ppi[%d]", name, i), i, this));
 }
+core_reset.signal_out.bind(evs->core_reset[cpu]);
+poweron_reset.signal_out.bind(evs->poweron_reset[cpu]);
+halt.signal_out.bind(evs->halt[cpu]);
 }


@@ -82,7 +88,8 @@
 const sc_core::sc_module_name _name, const Params ) :

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: add helper class for exporting amba_pv signal

2021-08-31 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48943 )


Change subject: fastmodel: add helper class for exporting amba_pv signal
..

fastmodel: add helper class for exporting amba_pv signal

To bridge amba_pv::signal_master_port with IntPins, we made a
helper class for the purpose. The SignalSender class can be exported as
a gem5 Port, receive the signal, and transfer to fastmodel.

Here's an example showing how it works

*.lisa
```
component
{
  slave port reset;
}
```

evs.hh
```
class
{
  SignalSender reset;
}
```

evs.cc
```
constructor(Params ) : reset(p.name + ".reset", 0)
{
  reset.signal_out.bind(Base::reset);
}

getPort
{
  return reset;
}
```

Change-Id: I0936f9ebb2cd60e975661ae78e590285da697771
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48943
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
A src/arch/arm/fastmodel/common/signal_sender.hh
1 file changed, 58 insertions(+), 0 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/common/signal_sender.hh  
b/src/arch/arm/fastmodel/common/signal_sender.hh

new file mode 100644
index 000..dbd4526
--- /dev/null
+++ b/src/arch/arm/fastmodel/common/signal_sender.hh
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2021 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_ARM_FASTMODEL_COMMON_SIGNAL_SENDER_HH__
+#define __ARCH_ARM_FASTMODEL_COMMON_SIGNAL_SENDER_HH__
+
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Woverloaded-virtual"
+#include 
+#pragma GCC diagnostic pop
+
+#include "dev/intpin.hh"
+
+namespace FastModel
+{
+
+class SignalSender : public IntSinkPinBase
+{
+  public:
+amba_pv::signal_master_port signal_out;
+
+SignalSender(const std::string &_name, PortID _id) :
+IntSinkPinBase(_name, _id, 0),
+signal_out((_name + ".sig").c_str())
+{}
+
+  private:
+void raiseOnDevice() override { signal_out.set_state(id, true); }
+void lowerOnDevice() override { signal_out.set_state(id, false); }
+};
+
+} // namespace FastModel
+
+#endif  // __ARCH_ARM_FASTMODEL_COMMON_SIGNAL_SENDER_HH__

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0936f9ebb2cd60e975661ae78e590285da697771
Gerrit-Change-Number: 48943
Gerrit-PatchSet: 3
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jui-min Lee 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Han-sheng Liu 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: export CortexR52 reset and halt signals

2021-08-30 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49651 )



Change subject: fastmodel: export CortexR52 reset and halt signals
..

fastmodel: export CortexR52 reset and halt signals

Change-Id: I44a26bad1a91009dbef586ab5d860352d51e
---
M src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
M src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
M src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
M src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
8 files changed, 69 insertions(+), 5 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py  
b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py

index 6530854..710584d 100644
--- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
+++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
@@ -30,7 +30,7 @@
 from m5.objects.ArmInterrupts import ArmInterrupts
 from m5.objects.ArmISA import ArmISA
 from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
-from m5.objects.IntPin import VectorIntSinkPin
+from m5.objects.IntPin import IntSinkPin, VectorIntSinkPin
 from m5.objects.Iris import IrisBaseCPU
 from m5.objects.SystemC import SystemC_ScModule

@@ -46,6 +46,11 @@
 llpp = AmbaInitiatorSocket(64, 'Low Latency Peripheral Port')
 flash = AmbaInitiatorSocket(64, 'Flash')
 amba = AmbaInitiatorSocket(64, 'AMBA initiator socket')
+core_reset = IntSinkPin('Raising this signal will put the core into ' \
+'reset mode.')
+poweron_reset = IntSinkPin('Power on reset. Initializes all the ' \
+   'processor logic, including debug logic.')
+halt = IntSinkPin('Raising this signal will put the core into halt  
mode.')


 CFGEND = Param.Bool(False, "Endianness configuration at reset.  0, " \
 "little endian. 1, big endian.")
@@ -108,6 +113,7 @@
 spi = VectorIntSinkPin('SPI inputs (0-959)')

 ext_slave = AmbaTargetSocket(64, 'AMBA target socket')
+top_reset = IntSinkPin('This signal resets timer and interrupt  
controller.')


 CLUSTER_ID = Param.UInt16(0, "CLUSTER_ID[15:8] equivalent to " \
 "CFGMPIDRAFF2, CLUSTER_ID[7:0] equivalent to CFGMPIDRAFF1")
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc  
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc

index 35e4e07..f5817f9 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -86,7 +86,9 @@
 // Since PPIs are indexed both by core and by number, modify the  
name

 // to hold the core number.
 return evs->gem5_getPort(csprintf("%s_%d", if_name, num), idx);
-} else if (if_name == "amba" || if_name == "llpp" || if_name  
== "flash") {
+} else if (if_name == "amba" || if_name == "llpp" || if_name  
== "flash" ||

+   if_name == "core_reset" || if_name == "poweron_reset" ||
+   if_name == "halt") {
 // Since these ports are scalar per core, use the core number as  
the

 // index. Also verify that that index is not being used.
 assert(idx == InvalidPortID);
@@ -150,7 +152,7 @@
 {
 if (if_name == "spi") {
 return evs->gem5_getPort(if_name, idx);
-} else if (if_name == "ext_slave") {
+} else if (if_name == "ext_slave" || if_name == "top_reset") {
 assert(idx == InvalidPortID);
 return evs->gem5_getPort(if_name, idx);
 } else {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc  
b/src/arch/arm/fastmodel/CortexR52/evs.cc

index f4e091e..7f992f2 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -68,12 +68,18 @@
 evs(_evs), cpu(_cpu),
 llpp(evs->llpp[cpu], name + ".llpp", -1),
 flash(evs->flash[cpu], name + ".flash", -1),
-amba(evs->amba[cpu], name + ".amba", -1)
+amba(evs->amba[cpu], name + ".amba", -1),
+core_reset(name + ".core_reset", 0),
+poweron_reset(name + ".poweron_reset", 0),
+halt(name + ".halt", 0)
 {
 for (int i = 0; i < Evs::PpiCount; i++) {
 ppis.emplace_back(
 new CoreInt(csprintf("%s.ppi[%d]", name, i), i, this));
 }
+core_reset.signal_out.bind(evs->core_reset[cpu]);
+poweron_reset.signal_out.bind(evs->poweron_reset[cpu]);
+halt.signal_out.bind(evs->halt[cpu]);
 }


@@ -82,7 +88,8 @@
 const sc_core::sc_module_name _name, const Params ) :
 Base(mod_name),
 params(p),
-ext_slave(Base::ext_slave, p.name + ".ext_slave", -1)
+ext_slave(Base::ext_slave, p.name + ".ext_slave", -1),
+top_reset(p.name + ".top_reset", 0)
 {
 for (int i = 0; i < CoreCount; i++)
 corePins.emplace_back(new CorePins(this, i));
@@ -92,6

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