date:20200909

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix ArmISA namespace requirement for TME instructions

2020-09-09 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34235 )



Change subject: arch-arm: Fix ArmISA namespace requirement for TME  
instructions

..

arch-arm: Fix ArmISA namespace requirement for TME instructions

This is needed after:

https://gem5-review.googlesource.com/c/public/gem5/+/34155

Change-Id: I8ef0b5ce9cd5ae5224331e1c9347fdd9e884a536
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/insts/misc64.hh
M src/arch/arm/insts/tme64.cc
M src/arch/arm/insts/tme64.hh
M src/arch/arm/insts/tme64classic.cc
M src/arch/arm/insts/tme64ruby.cc
5 files changed, 36 insertions(+), 29 deletions(-)



diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index 7aedd55..a077882 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -234,14 +234,14 @@
 Addr pc, const Loader::SymbolTable *symtab) const override;
 };

-class RegNone : public ArmStaticInst
+class RegNone : public ArmISA::ArmStaticInst
 {
   protected:
-IntRegIndex dest;
+ArmISA::IntRegIndex dest;

-RegNone(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest) :
-ArmStaticInst(mnem, _machInst, __opClass),
+RegNone(const char *mnem, ArmISA::ExtMachInst _machInst,
+OpClass __opClass, ArmISA::IntRegIndex _dest) :
+ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
 dest(_dest)
 {}

diff --git a/src/arch/arm/insts/tme64.cc b/src/arch/arm/insts/tme64.cc
index da228c4..30aff20 100644
--- a/src/arch/arm/insts/tme64.cc
+++ b/src/arch/arm/insts/tme64.cc
@@ -40,6 +40,8 @@

  #include 

+using namespace ArmISA;
+
 namespace ArmISAInst {

 std::string
diff --git a/src/arch/arm/insts/tme64.hh b/src/arch/arm/insts/tme64.hh
index dada664..b75adc1 100644
--- a/src/arch/arm/insts/tme64.hh
+++ b/src/arch/arm/insts/tme64.hh
@@ -44,18 +44,19 @@

 namespace ArmISAInst {

-class MicroTmeOp : public MicroOp
+class MicroTmeOp : public ArmISA::MicroOp
 {
   protected:
-MicroTmeOp(const char *mnem, ExtMachInst machInst, OpClass __opClass) :
-   MicroOp(mnem, machInst, __opClass)
+MicroTmeOp(const char *mnem, ArmISA::ExtMachInst machInst,
+   OpClass __opClass)
+  : ArmISA::MicroOp(mnem, machInst, __opClass)
 {}
 };

 class MicroTmeBasic64 : public MicroTmeOp
 {
   protected:
-MicroTmeBasic64(const char *mnem, ExtMachInst machInst,
+MicroTmeBasic64(const char *mnem, ArmISA::ExtMachInst machInst,
 OpClass __opClass) :
 MicroTmeOp(mnem, machInst, __opClass)
 {}
@@ -64,30 +65,30 @@
 const Loader::SymbolTable *symtab)  
const;

 };

-class TmeImmOp64 : public ArmStaticInst
+class TmeImmOp64 : public ArmISA::ArmStaticInst
 {
   protected:
 uint64_t imm;

-TmeImmOp64(const char *mnem, ExtMachInst machInst,
-   OpClass __opClass, uint64_t _imm) :
- ArmStaticInst(mnem, machInst, __opClass),
- imm(_imm)
+TmeImmOp64(const char *mnem, ArmISA::ExtMachInst machInst,
+   OpClass __opClass, uint64_t _imm)
+  : ArmISA::ArmStaticInst(mnem, machInst, __opClass),
+imm(_imm)
 {}

 std::string generateDisassembly(Addr pc,
 const Loader::SymbolTable *symtab)  
const;

 };

-class TmeRegNone64 : public ArmStaticInst
+class TmeRegNone64 : public ArmISA::ArmStaticInst
 {
   protected:
-IntRegIndex dest;
+ArmISA::IntRegIndex dest;

-TmeRegNone64(const char *mnem, ExtMachInst machInst,
- OpClass __opClass, IntRegIndex _dest) :
-   ArmStaticInst(mnem, machInst, __opClass),
-   dest(_dest)
+TmeRegNone64(const char *mnem, ArmISA::ExtMachInst machInst,
+ OpClass __opClass, ArmISA::IntRegIndex _dest)
+  : ArmISA::ArmStaticInst(mnem, machInst, __opClass),
+dest(_dest)
 {}

 std::string generateDisassembly(Addr pc,
@@ -97,7 +98,7 @@
 class Tstart64 : public TmeRegNone64
 {
   public:
-Tstart64(ExtMachInst, IntRegIndex);
+Tstart64(ArmISA::ExtMachInst, ArmISA::IntRegIndex);

 Fault execute(ExecContext *, Trace::InstRecord *) const;
 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
@@ -107,7 +108,7 @@
 class Ttest64 : public TmeRegNone64
 {
   public:
-Ttest64(ExtMachInst, IntRegIndex);
+Ttest64(ArmISA::ExtMachInst, ArmISA::IntRegIndex);

 Fault execute(ExecContext *, Trace::InstRecord *) const;
 };
@@ -115,7 +116,7 @@
 class Tcancel64 : public TmeImmOp64
 {
   public:
-Tcancel64(ExtMachInst, uint64_t);
+Tcancel64(ArmISA::ExtMachInst, uint64_t);

 Fault execute(ExecContext *, Trace::InstRecord *) const;
 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
@@ -125,7 +126,7 @@
 class MicroTfence64 : public

[gem5-dev] Change in gem5/gem5[develop]: sim: Expose the system's byte order as a param

2020-09-09 Thread Andreas Sandberg (Gerrit) via gem5-dev

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33175 )


Change subject: sim: Expose the system's byte order as a param
..

sim: Expose the system's byte order as a param

There are cases where a system's byte order isn't well-defined from an
ISA. For example, Arm implementations can be either big or little
endian, sometimes depending on a boot parameter. Decouple the CPU byte
order from the System's default byte order by exposing the System's
byte order as a parameter that defaults to big endian for SPARC and
POWER and little endian for everything else.

Change-Id: I24f87ea3a61b05042ede20dea6bb056af071d2c0
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33175
Tested-by: kokoro 
Reviewed-by: Gabe Black 
---
M src/sim/System.py
M src/sim/system.hh
2 files changed, 9 insertions(+), 5 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/System.py b/src/sim/System.py
index dcef74b..caf32fb 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -48,6 +48,11 @@
 class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing',
 'atomic_noncaching']

+if buildEnv['TARGET_ISA'] in ('sparc', 'power'):
+default_byte_order = 'big'
+else:
+default_byte_order = 'little'
+
 class System(SimObject):
 type = 'System'
 cxx_header = "sim/system.hh"
@@ -84,6 +89,9 @@

 cache_line_size = Param.Unsigned(64, "Cache line size in bytes")

+byte_order = Param.ByteOrder(default_byte_order,
+ "Default byte order of system components")
+
 redirect_paths = VectorParam.RedirectPath([], "Path redirections")

 exit_on_work_items = Param.Bool(False, "Exit from the simulation loop  
when "

diff --git a/src/sim/system.hh b/src/sim/system.hh
index 8e2c472..8b31b2f 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -386,11 +386,7 @@
 ByteOrder
 getGuestByteOrder() const
 {
-#if THE_ISA != NULL_ISA
-return TheISA::GuestByteOrder;
-#else
-panic("The NULL ISA has no endianness.");
-#endif
+return _params->byte_order;
 }

  /**

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/33175
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I24f87ea3a61b05042ede20dea6bb056af071d2c0
Gerrit-Change-Number: 33175
Gerrit-PatchSet: 5
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base, sim, mem, arch: Remove the dummy CPU in NULL

2020-09-09 Thread Andreas Sandberg (Gerrit) via gem5-dev

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34236 )



Change subject: base, sim, mem, arch: Remove the dummy CPU in NULL
..

base, sim, mem, arch: Remove the dummy CPU in NULL

The NULL ISA target has a dummy BaseCPU class that doesn't seem to be
needed anymore. Remove this class and the some unnecessary includes.

Change-Id: I031c999b3c0bb8dec036ad087a3edb2c1c723501
Signed-off-by: Andreas Sandberg 
---
M src/arch/null/SConscript
D src/arch/null/cpu_dummy.cc
D src/arch/null/cpu_dummy.hh
M src/cpu/base.hh
M src/mem/abstract_mem.cc
M src/mem/cache/prefetch/base.cc
M src/sim/stat_control.cc
M src/sim/system.cc
M src/sim/system.hh
9 files changed, 9 insertions(+), 100 deletions(-)



diff --git a/src/arch/null/SConscript b/src/arch/null/SConscript
index 41457e2..3f0b053 100644
--- a/src/arch/null/SConscript
+++ b/src/arch/null/SConscript
@@ -36,6 +36,3 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 Import('*')
-
-if env['TARGET_ISA'] == 'null':
-Source('cpu_dummy.cc')
diff --git a/src/arch/null/cpu_dummy.cc b/src/arch/null/cpu_dummy.cc
deleted file mode 100644
index df30b81..000
--- a/src/arch/null/cpu_dummy.cc
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2013 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder.  You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * Provide the actual storage for maxThreadsPerCPU which is declared
- * extern and normally provided by src/cpu/base.cc
- */
-int maxThreadsPerCPU = 1;
diff --git a/src/arch/null/cpu_dummy.hh b/src/arch/null/cpu_dummy.hh
deleted file mode 100644
index 7e183eb..000
--- a/src/arch/null/cpu_dummy.hh
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2013 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder.  You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: convert commit to new style stats

2020-09-09 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33315 )


Change subject: cpu-o3: convert commit to new style stats
..

cpu-o3: convert commit to new style stats

Change-Id: I859fe753d1a2ec2da8a4209d1db122f1014af5d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33315
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.cc
3 files changed, 117 insertions(+), 155 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 85d00a9..01a0b7f 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -143,9 +143,6 @@
 /** Returns the name of the DefaultCommit. */
 std::string name() const;

-/** Registers statistics. */
-void regStats();
-
 /** Registers probes. */
 void regProbePoints();

@@ -479,52 +476,55 @@
 /** Updates commit stats based on this instruction. */
 void updateComInstStats(const DynInstPtr );

-
 // HTM
 int htmStarts[Impl::MaxThreads];
 int htmStops[Impl::MaxThreads];

-/** Stat for the total number of squashed instructions discarded by  
commit.

- */
-Stats::Scalar commitSquashedInsts;
-/** Stat for the total number of times commit has had to stall due to  
a non-

- * speculative instruction reaching the head of the ROB.
- */
-Stats::Scalar commitNonSpecStalls;
-/** Stat for the total number of branch mispredicts that caused a  
squash. */

-Stats::Scalar branchMispredicts;
-/** Distribution of the number of committed instructions each cycle. */
-Stats::Distribution numCommittedDist;
+struct CommitStats : public Stats::Group {
+CommitStats(O3CPU *cpu, DefaultCommit *commit);
+/** Stat for the total number of squashed instructions discarded by
+ * commit.
+ */
+Stats::Scalar commitSquashedInsts;
+/** Stat for the total number of times commit has had to stall due
+ * to a non-speculative instruction reaching the head of the ROB.
+ */
+Stats::Scalar commitNonSpecStalls;
+/** Stat for the total number of branch mispredicts that caused a
+ * squash.
+ */
+Stats::Scalar branchMispredicts;
+/** Distribution of the number of committed instructions each  
cycle. */

+Stats::Distribution numCommittedDist;

-/** Total number of instructions committed. */
-Stats::Vector instsCommitted;
-/** Total number of ops (including micro ops) committed. */
-Stats::Vector opsCommitted;
-/** Total number of software prefetches committed. */
-Stats::Vector statComSwp;
-/** Stat for the total number of committed memory references. */
-Stats::Vector statComRefs;
-/** Stat for the total number of committed loads. */
-Stats::Vector statComLoads;
-/** Stat for the total number of committed atomics. */
-Stats::Vector statComAmos;
-/** Total number of committed memory barriers. */
-Stats::Vector statComMembars;
-/** Total number of committed branches. */
-Stats::Vector statComBranches;
-/** Total number of vector instructions */
-Stats::Vector statComVector;
-/** Total number of floating point instructions */
-Stats::Vector statComFloating;
-/** Total number of integer instructions */
-Stats::Vector statComInteger;
-/** Total number of function calls */
-Stats::Vector statComFunctionCalls;
-/** Committed instructions by instruction type (OpClass) */
-Stats::Vector2d statCommittedInstType;
+/** Total number of instructions committed. */
+Stats::Vector instsCommitted;
+/** Total number of ops (including micro ops) committed. */
+Stats::Vector opsCommitted;
+/** Stat for the total number of committed memory references. */
+Stats::Vector memRefs;
+/** Stat for the total number of committed loads. */
+Stats::Vector loads;
+/** Stat for the total number of committed atomics. */
+Stats::Vector amos;
+/** Total number of committed memory barriers. */
+Stats::Vector membars;
+/** Total number of committed branches. */
+Stats::Vector branches;
+/** Total number of vector instructions */
+Stats::Vector vector;
+/** Total number of floating point instructions */
+Stats::Vector floating;
+/** Total number of integer instructions */
+Stats::Vector integer;
+/** Total number of function calls */
+Stats::Vector functionCalls;
+/** Committed instructions by instruction type (OpClass) */
+Stats::Vector2d committedInstType;

-/** Number of cycles where the commit

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: convert lsq_unit to new style stats

2020-09-09 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33394 )


Change subject: cpu-o3: convert lsq_unit to new style stats
..

cpu-o3: convert lsq_unit to new style stats

Removes unused stats: invAddrLoads, invAddrSwpfs, lsqBlockedLoads

Change-Id: Icd7fc6d8a040f4a1f9b190409b7cdb0a57fd68cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33394
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
5 files changed, 49 insertions(+), 93 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 9a04fe6..497c532 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -146,7 +146,6 @@
 using namespace Stats;

 instQueue.regStats();
-ldstQueue.regStats();

 iewIdleCycles
 .name(name() + ".iewIdleCycles")
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 35c2873..bc5e154 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -856,9 +856,6 @@
 /** Returns the name of the LSQ. */
 std::string name() const;

-/** Registers statistics of each LSQ unit. */
-void regStats();
-
 /** Sets the pointer to the list of active threads. */
 void setActiveThreads(std::list *at_ptr);

diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index a535dcc..7657b23 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -118,16 +118,6 @@

 template
 void
-LSQ::regStats()
-{
-//Initialize LSQs
-for (ThreadID tid = 0; tid < numThreads; tid++) {
-thread[tid].regStats();
-}
-}
-
-template
-void
 LSQ::setActiveThreads(list *at_ptr)
 {
 activeThreads = at_ptr;
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 70995d6..3d6e3f0 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -45,6 +45,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 

 #include "arch/generic/debugfaults.hh"
@@ -225,7 +226,10 @@
  * contructor is deleted explicitly. However, STL vector requires
  * a valid copy constructor for the base type at compile time.
  */
-LSQUnit(const LSQUnit ) { panic("LSQUnit is not copy-able"); }
+LSQUnit(const LSQUnit ): stats(nullptr)
+{
+panic("LSQUnit is not copy-able");
+}

 /** Initializes the LSQ unit with the specified number of entries. */
 void init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
@@ -234,9 +238,6 @@
 /** Returns the name of the LSQ unit. */
 std::string name() const;

-/** Registers statistics. */
-void regStats();
-
 /** Sets the pointer to the dcache port. */
 void setDcachePort(RequestPort *dcache_port);

@@ -561,39 +562,35 @@
 /** Flag for memory model. */
 bool needsTSO;

+  protected:
 // Will also need how many read/write ports the Dcache has.  Or keep  
track
 // of that in stage that is one level up, and only call  
executeLoad/Store

 // the appropriate number of times.
-/** Total number of loads forwaded from LSQ stores. */
-Stats::Scalar lsqForwLoads;
+struct LSQUnitStats : public Stats::Group{
+LSQUnitStats(Stats::Group *parent);

-/** Total number of loads ignored due to invalid addresses. */
-Stats::Scalar invAddrLoads;
+/** Total number of loads forwaded from LSQ stores. */
+Stats::Scalar forwLoads;

-/** Total number of squashed loads. */
-Stats::Scalar lsqSquashedLoads;
+/** Total number of squashed loads. */
+Stats::Scalar squashedLoads;

-/** Total number of responses from the memory system that are
- * ignored due to the instruction already being squashed. */
-Stats::Scalar lsqIgnoredResponses;
+/** Total number of responses from the memory system that are
+ * ignored due to the instruction already being squashed. */
+Stats::Scalar ignoredResponses;

-/** Tota number of memory ordering violations. */
-Stats::Scalar lsqMemOrderViolation;
+/** Tota number of memory ordering violations. */
+Stats::Scalar memOrderViolation;

-/** Total number of squashed stores. */
-Stats::Scalar lsqSquashedStores;
+/** Total number of squashed stores. */
+Stats::Scalar squashedStores;

-/** Total number of software prefetches ignored due to invalid  
addresses. */

-Stats::Scalar invAddrSwpfs;
+/** Number of loads that were rescheduled. */
+Stats::Scalar rescheduledLoads;

-/** Ready loads blocked due to partial store-forwarding. */
-Stats::Scalar lsqBlockedLoads;
-
-/** Number of loads that were rescheduled. */
-Stats::Scalar lsqRescheduledLoads;
-
-/**

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: convert rename to new style stats

2020-09-09 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33397 )


Change subject: cpu-o3: convert rename to new style stats
..

cpu-o3: convert rename to new style stats

Change-Id: Id34a85e40ad7e83d5805a034df6e0c5ad9b9af82
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33397
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/o3/cpu.cc
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
3 files changed, 150 insertions(+), 176 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index bbc6b82..414913d 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -441,7 +441,6 @@
 .precision(6);
 totalIpc =  sum(committedInsts) / numCycles;

-this->rename.regStats();
 this->iew.regStats();

 intRegfileReads
diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh
index e3dc3e9..5b45218 100644
--- a/src/cpu/o3/rename.hh
+++ b/src/cpu/o3/rename.hh
@@ -133,9 +133,6 @@
 /** Returns the name of rename. */
 std::string name() const;

-/** Registers statistics. */
-void regStats();
-
 /** Registers probes. */
 void regProbePoints();

@@ -481,51 +478,62 @@
  */
 inline void incrFullStat(const FullSource );

-/** Stat for total number of cycles spent squashing. */
-Stats::Scalar renameSquashCycles;
-/** Stat for total number of cycles spent idle. */
-Stats::Scalar renameIdleCycles;
-/** Stat for total number of cycles spent blocking. */
-Stats::Scalar renameBlockCycles;
-/** Stat for total number of cycles spent stalling for a serializing  
inst. */

-Stats::Scalar renameSerializeStallCycles;
-/** Stat for total number of cycles spent running normally. */
-Stats::Scalar renameRunCycles;
-/** Stat for total number of cycles spent unblocking. */
-Stats::Scalar renameUnblockCycles;
-/** Stat for total number of renamed instructions. */
-Stats::Scalar renameRenamedInsts;
-/** Stat for total number of squashed instructions that rename  
discards. */

-Stats::Scalar renameSquashedInsts;
-/** Stat for total number of times that the ROB starts a stall in  
rename. */

-Stats::Scalar renameROBFullEvents;
-/** Stat for total number of times that the IQ starts a stall in  
rename. */

-Stats::Scalar renameIQFullEvents;
-/** Stat for total number of times that the LQ starts a stall in  
rename. */

-Stats::Scalar renameLQFullEvents;
-/** Stat for total number of times that the SQ starts a stall in  
rename. */

-Stats::Scalar renameSQFullEvents;
-/** Stat for total number of times that rename runs out of free  
registers

- * to use to rename. */
-Stats::Scalar renameFullRegistersEvents;
-/** Stat for total number of renamed destination registers. */
-Stats::Scalar renameRenamedOperands;
-/** Stat for total number of source register rename lookups. */
-Stats::Scalar renameRenameLookups;
-Stats::Scalar intRenameLookups;
-Stats::Scalar fpRenameLookups;
-Stats::Scalar vecRenameLookups;
-Stats::Scalar vecPredRenameLookups;
-/** Stat for total number of committed renaming mappings. */
-Stats::Scalar renameCommittedMaps;
-/** Stat for total number of mappings that were undone due to a  
squash. */

-Stats::Scalar renameUndoneMaps;
-/** Number of serialize instructions handled. */
-Stats::Scalar renamedSerializing;
-/** Number of instructions marked as temporarily serializing. */
-Stats::Scalar renamedTempSerializing;
-/** Number of instructions inserted into skid buffers. */
-Stats::Scalar renameSkidInsts;
+struct RenameStats : public Stats::Group {
+RenameStats(Stats::Group *parent);
+
+/** Stat for total number of cycles spent squashing. */
+Stats::Scalar squashCycles;
+/** Stat for total number of cycles spent idle. */
+Stats::Scalar idleCycles;
+/** Stat for total number of cycles spent blocking. */
+Stats::Scalar blockCycles;
+/** Stat for total number of cycles spent stalling for a  
serializing

+ *  inst. */
+Stats::Scalar serializeStallCycles;
+/** Stat for total number of cycles spent running normally. */
+Stats::Scalar runCycles;
+/** Stat for total number of cycles spent unblocking. */
+Stats::Scalar unblockCycles;
+/** Stat for total number of renamed instructions. */
+Stats::Scalar renamedInsts;
+/** Stat for total number of squashed instructions that rename
+ * discards. */
+Stats::Scalar squashedInsts;
+/** Stat for total number of times that the ROB starts a stall in
+ * rename. */
+Stats::Scalar ROBFullEvents;
+

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: convert rob to new style stats

2020-09-09 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33398 )


Change subject: cpu-o3: convert rob to new style stats
..

cpu-o3: convert rob to new style stats

Change-Id: I84430d50c49742cd536dd75ce25184c2316dce51
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33398
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/cpu/o3/cpu.cc
M src/cpu/o3/rob.hh
M src/cpu/o3/rob_impl.hh
3 files changed, 19 insertions(+), 23 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index c5b4a82..bbc6b82 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -443,7 +443,6 @@

 this->rename.regStats();
 this->iew.regStats();
-this->rob.regStats();

 intRegfileReads
 .name(name() + ".int_regfile_reads")
diff --git a/src/cpu/o3/rob.hh b/src/cpu/o3/rob.hh
index eb8d1d6..4b87dc4 100644
--- a/src/cpu/o3/rob.hh
+++ b/src/cpu/o3/rob.hh
@@ -257,9 +257,6 @@
  */
 size_t countInsts(ThreadID tid);

-/** Registers statistics. */
-void regStats();
-
   private:
 /** Reset the ROB state */
 void resetState();
@@ -323,10 +320,15 @@
 /** Number of active threads. */
 ThreadID numThreads;

-// The number of rob_reads
-Stats::Scalar robReads;
-// The number of rob_writes
-Stats::Scalar robWrites;
+
+struct ROBStats : public Stats::Group {
+ROBStats(Stats::Group *parent);
+
+// The number of rob_reads
+Stats::Scalar reads;
+// The number of rob_writes
+Stats::Scalar writes;
+} stats;
 };

 #endif //__CPU_O3_ROB_HH__
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index 80ea1e6..bfc368b 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -58,7 +58,8 @@
   numEntries(params->numROBEntries),
   squashWidth(params->squashWidth),
   numInstsInROB(0),
-  numThreads(params->numThreads)
+  numThreads(params->numThreads),
+  stats(_cpu)
 {
 //Figure out rob policy
 if (robPolicy == SMTQueuePolicy::Dynamic) {
@@ -204,7 +205,7 @@
 {
 assert(inst);

-robWrites++;
+stats.writes++;

 DPRINTF(ROB, "Adding inst PC %s to the ROB.\n", inst->pcState());

@@ -239,7 +240,7 @@
 void
 ROB::retireHead(ThreadID tid)
 {
-robWrites++;
+stats.writes++;

 assert(numInstsInROB > 0);

@@ -274,7 +275,7 @@
 bool
 ROB::isHeadReady(ThreadID tid)
 {
-robReads++;
+stats.reads++;
 if (threadEntries[tid] != 0) {
 return instList[tid].front()->readyToCommit();
 }
@@ -319,7 +320,7 @@
 void
 ROB::doSquash(ThreadID tid)
 {
-robWrites++;
+stats.writes++;
 DPRINTF(ROB, "[tid:%i] Squashing instructions until [sn:%llu].\n",
 tid, squashedSeqNum[tid]);

@@ -528,17 +529,11 @@
 }

 template 
-void
-ROB::regStats()
+ROB::ROBStats::ROBStats(Stats::Group *parent)
+: Stats::Group(parent, "rob"),
+  ADD_STAT(reads, "The number of ROB reads"),
+  ADD_STAT(writes, "The number of ROB writes")
 {
-using namespace Stats;
-robReads
-.name(name() + ".rob_reads")
-.desc("The number of ROB reads");
-
-robWrites
-.name(name() + ".rob_writes")
-.desc("The number of ROB writes");
 }

 template 

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/33398
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I84430d50c49742cd536dd75ce25184c2316dce51
Gerrit-Change-Number: 33398
Gerrit-PatchSet: 4
Gerrit-Owner: Emily Brickey 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: convert decode to new style stats

2020-09-09 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33316 )


Change subject: cpu-o3: convert decode to new style stats
..

cpu-o3: convert decode to new style stats

Change-Id: Ia67a51f3b2c2d40d8bf09f1636c721550f5e9a23
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33316
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/o3/cpu.cc
M src/cpu/o3/decode.hh
M src/cpu/o3/decode_impl.hh
3 files changed, 63 insertions(+), 80 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index c705801..c5b4a82 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -441,7 +441,6 @@
 .precision(6);
 totalIpc =  sum(committedInsts) / numCycles;

-this->decode.regStats();
 this->rename.regStats();
 this->iew.regStats();
 this->rob.regStats();
diff --git a/src/cpu/o3/decode.hh b/src/cpu/o3/decode.hh
index 9e26bae..c0c0b81 100644
--- a/src/cpu/o3/decode.hh
+++ b/src/cpu/o3/decode.hh
@@ -109,9 +109,6 @@
 /** Returns the name of decode. */
 std::string name() const;

-/** Registers statistics. */
-void regStats();
-
 /** Sets the main backwards communication time buffer pointer. */
 void setTimeBuffer(TimeBuffer *tb_ptr);

@@ -295,29 +292,32 @@
  */
 bool squashAfterDelaySlot[Impl::MaxThreads];

+struct DecodeStats : public Stats::Group {
+DecodeStats(O3CPU *cpu);

-/** Stat for total number of idle cycles. */
-Stats::Scalar decodeIdleCycles;
-/** Stat for total number of blocked cycles. */
-Stats::Scalar decodeBlockedCycles;
-/** Stat for total number of normal running cycles. */
-Stats::Scalar decodeRunCycles;
-/** Stat for total number of unblocking cycles. */
-Stats::Scalar decodeUnblockCycles;
-/** Stat for total number of squashing cycles. */
-Stats::Scalar decodeSquashCycles;
-/** Stat for number of times a branch is resolved at decode. */
-Stats::Scalar decodeBranchResolved;
-/** Stat for number of times a branch mispredict is detected. */
-Stats::Scalar decodeBranchMispred;
-/** Stat for number of times decode detected a non-control instruction
- * incorrectly predicted as a branch.
- */
-Stats::Scalar decodeControlMispred;
-/** Stat for total number of decoded instructions. */
-Stats::Scalar decodeDecodedInsts;
-/** Stat for total number of squashed instructions. */
-Stats::Scalar decodeSquashedInsts;
+/** Stat for total number of idle cycles. */
+Stats::Scalar idleCycles;
+/** Stat for total number of blocked cycles. */
+Stats::Scalar blockedCycles;
+/** Stat for total number of normal running cycles. */
+Stats::Scalar runCycles;
+/** Stat for total number of unblocking cycles. */
+Stats::Scalar unblockCycles;
+/** Stat for total number of squashing cycles. */
+Stats::Scalar squashCycles;
+/** Stat for number of times a branch is resolved at decode. */
+Stats::Scalar branchResolved;
+/** Stat for number of times a branch mispredict is detected. */
+Stats::Scalar branchMispred;
+/** Stat for number of times decode detected a non-control  
instruction

+ * incorrectly predicted as a branch.
+ */
+Stats::Scalar controlMispred;
+/** Stat for total number of decoded instructions. */
+Stats::Scalar decodedInsts;
+/** Stat for total number of squashed instructions. */
+Stats::Scalar squashedInsts;
+} stats;
 };

 #endif // __CPU_O3_DECODE_HH__
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index cf3d601..24640f6 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -64,7 +64,8 @@
   commitToDecodeDelay(params->commitToDecodeDelay),
   fetchToDecodeDelay(params->fetchToDecodeDelay),
   decodeWidth(params->decodeWidth),
-  numThreads(params->numThreads)
+  numThreads(params->numThreads),
+  stats(_cpu)
 {
 if (decodeWidth > Impl::MaxWidth)
 fatal("decodeWidth (%d) is larger than compiled limit (%d),\n"
@@ -119,50 +120,33 @@
 }

 template 
-void
-DefaultDecode::regStats()
+DefaultDecode::DecodeStats::DecodeStats(O3CPU *cpu)
+: Stats::Group(cpu, "decode"),
+  ADD_STAT(idleCycles, "Number of cycles decode is idle"),
+  ADD_STAT(blockedCycles, "Number of cycles decode is blocked"),
+  ADD_STAT(runCycles, "Number of cycles decode is running"),
+  ADD_STAT(unblockCycles, "Number of cycles decode is unblocking"),
+  ADD_STAT(squashCycles, "Number of cycles decode is squashing"),
+  ADD_STAT(branchResolved, "Number of

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix ArmISA namespace requirement for TME instructions

2020-09-09 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34235 )


Change subject: arch-arm: Fix ArmISA namespace requirement for TME  
instructions

..

arch-arm: Fix ArmISA namespace requirement for TME instructions

This is needed after:

https://gem5-review.googlesource.com/c/public/gem5/+/34155

Change-Id: I8ef0b5ce9cd5ae5224331e1c9347fdd9e884a536
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34235
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/arm/insts/misc64.hh
M src/arch/arm/insts/tme64.cc
M src/arch/arm/insts/tme64.hh
M src/arch/arm/insts/tme64classic.cc
M src/arch/arm/insts/tme64ruby.cc
5 files changed, 36 insertions(+), 29 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index 7aedd55..a077882 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -234,14 +234,14 @@
 Addr pc, const Loader::SymbolTable *symtab) const override;
 };

-class RegNone : public ArmStaticInst
+class RegNone : public ArmISA::ArmStaticInst
 {
   protected:
-IntRegIndex dest;
+ArmISA::IntRegIndex dest;

-RegNone(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest) :
-ArmStaticInst(mnem, _machInst, __opClass),
+RegNone(const char *mnem, ArmISA::ExtMachInst _machInst,
+OpClass __opClass, ArmISA::IntRegIndex _dest) :
+ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
 dest(_dest)
 {}

diff --git a/src/arch/arm/insts/tme64.cc b/src/arch/arm/insts/tme64.cc
index da228c4..30aff20 100644
--- a/src/arch/arm/insts/tme64.cc
+++ b/src/arch/arm/insts/tme64.cc
@@ -40,6 +40,8 @@

  #include 

+using namespace ArmISA;
+
 namespace ArmISAInst {

 std::string
diff --git a/src/arch/arm/insts/tme64.hh b/src/arch/arm/insts/tme64.hh
index dada664..b75adc1 100644
--- a/src/arch/arm/insts/tme64.hh
+++ b/src/arch/arm/insts/tme64.hh
@@ -44,18 +44,19 @@

 namespace ArmISAInst {

-class MicroTmeOp : public MicroOp
+class MicroTmeOp : public ArmISA::MicroOp
 {
   protected:
-MicroTmeOp(const char *mnem, ExtMachInst machInst, OpClass __opClass) :
-   MicroOp(mnem, machInst, __opClass)
+MicroTmeOp(const char *mnem, ArmISA::ExtMachInst machInst,
+   OpClass __opClass)
+  : ArmISA::MicroOp(mnem, machInst, __opClass)
 {}
 };

 class MicroTmeBasic64 : public MicroTmeOp
 {
   protected:
-MicroTmeBasic64(const char *mnem, ExtMachInst machInst,
+MicroTmeBasic64(const char *mnem, ArmISA::ExtMachInst machInst,
 OpClass __opClass) :
 MicroTmeOp(mnem, machInst, __opClass)
 {}
@@ -64,30 +65,30 @@
 const Loader::SymbolTable *symtab)  
const;

 };

-class TmeImmOp64 : public ArmStaticInst
+class TmeImmOp64 : public ArmISA::ArmStaticInst
 {
   protected:
 uint64_t imm;

-TmeImmOp64(const char *mnem, ExtMachInst machInst,
-   OpClass __opClass, uint64_t _imm) :
- ArmStaticInst(mnem, machInst, __opClass),
- imm(_imm)
+TmeImmOp64(const char *mnem, ArmISA::ExtMachInst machInst,
+   OpClass __opClass, uint64_t _imm)
+  : ArmISA::ArmStaticInst(mnem, machInst, __opClass),
+imm(_imm)
 {}

 std::string generateDisassembly(Addr pc,
 const Loader::SymbolTable *symtab)  
const;

 };

-class TmeRegNone64 : public ArmStaticInst
+class TmeRegNone64 : public ArmISA::ArmStaticInst
 {
   protected:
-IntRegIndex dest;
+ArmISA::IntRegIndex dest;

-TmeRegNone64(const char *mnem, ExtMachInst machInst,
- OpClass __opClass, IntRegIndex _dest) :
-   ArmStaticInst(mnem, machInst, __opClass),
-   dest(_dest)
+TmeRegNone64(const char *mnem, ArmISA::ExtMachInst machInst,
+ OpClass __opClass, ArmISA::IntRegIndex _dest)
+  : ArmISA::ArmStaticInst(mnem, machInst, __opClass),
+dest(_dest)
 {}

 std::string generateDisassembly(Addr pc,
@@ -97,7 +98,7 @@
 class Tstart64 : public TmeRegNone64
 {
   public:
-Tstart64(ExtMachInst, IntRegIndex);
+Tstart64(ArmISA::ExtMachInst, ArmISA::IntRegIndex);

 Fault execute(ExecContext *, Trace::InstRecord *) const;
 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
@@ -107,7 +108,7 @@
 class Ttest64 : public TmeRegNone64
 {
   public:
-Ttest64(ExtMachInst, IntRegIndex);
+Ttest64(ArmISA::ExtMachInst, ArmISA::IntRegIndex);

 Fault execute(ExecContext *, Trace::InstRecord *) const;
 };
@@ -115,7 +116,7 @@
 class Tcancel64 : public TmeImmOp64
 {
   public:
-

[gem5-dev] Build failed in Jenkins: Nightly #63

2020-09-09 Thread jenkins-no-reply--- via gem5-dev

See 

Changes:

[gabeblack] arch: Add a virtual destructor to BaseHTMCheckpoint.

[gabeblack] cpu: Fix style and add overrides to bas_dyn_inst.hh.

[gabeblack] mem: Remove the unused nvm private member from NVMInterface::Rank.

[Andreas.Sandberg] sim: Expose the system's byte order as a param

[Jason Lowe-Power] cpu-o3: convert commit to new style stats

[Jason Lowe-Power] cpu-o3: convert decode to new style stats

[Jason Lowe-Power] cpu-o3: convert lsq_unit to new style stats

[Jason Lowe-Power] cpu-o3: convert rob to new style stats

[Jason Lowe-Power] cpu-o3: convert rename to new style stats

[giacomo.travaglini] arch-arm: Fix ArmISA namespace requirement for TME 
instructions


--
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 [ TRACING]  -> MIPS/debug/SimpleTrace.hh
 [ CXX] MIPS/cpu/o3/probe/simple_trace.cc -> .o
 [ TRACING]  -> MIPS/debug/ElasticTrace.hh
 [ CXX] MIPS/cpu/o3/probe/elastic_trace.cc -> .o
 [ TRACING]  -> MIPS/debug/RubyTest.hh
 [ CXX] MIPS/cpu/testers/rubytest/RubyTester.cc -> .o
 [ CXX] MIPS/cpu/testers/rubytest/Check.cc -> .o
 [ CXX] MIPS/cpu/testers/rubytest/CheckTable.cc -> .o
 [LINK]  -> MIPS/cpu/o3/probe/lib.o.partial
 [ TRACING]  -> MIPS/debug/RubyStats.hh
 [ CXX] MIPS/mem/ruby/structures/DirectoryMemory.cc -> .o
 [ TRACING]  -> MIPS/debug/HtmMem.hh
 [ TRACING]  -> MIPS/debug/RubyCacheTrace.hh
 [ TRACING]  -> MIPS/debug/RubyResourceStalls.hh
 [ CXX] MIPS/mem/ruby/structures/CacheMemory.cc -> .o
 [LINK]  ->

[gem5-dev] Change in gem5/gem5[develop]: cpu: Fixed unused var error when with fast builds

2020-09-09 Thread Bobby R. Bruce (Gerrit) via gem5-dev

Bobby R. Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34256 )



Change subject: cpu: Fixed unused var error when with fast builds
..

cpu: Fixed unused var error when with fast builds

As `is_htm_speculative` is only used in assert statements, it is
considered unused during the `.fast` compilation. This commit adds the
`M5_USED_VAR` macro.

This caused our compiler tests to fail:
https://www.mail-archive.com/gem5-dev@gem5.org/msg35913.html

Change-Id: I00d187d1a31d065c236ac29a657bd479ad4b03bc
---
M src/cpu/simple/timing.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index f22c58d..820bede 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -947,7 +947,7 @@
 // hardware transactional memory

 SimpleExecContext *t_info = threadInfo[curThread];
-const bool is_htm_speculative =
+const bool is_htm_speculative M5_VAR_USED =
 t_info->inHtmTransactionalState();

 // received a response from the dcache: complete the load or store

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34256
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I00d187d1a31d065c236ac29a657bd479ad4b03bc
Gerrit-Change-Number: 34256
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce 
Gerrit-MessageType: newchange
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[gem5-dev] Re: Build failed in Jenkins: Nightly #63

2020-09-09 Thread Bobby Bruce via gem5-dev

This failure is fixed by
https://gem5-review.googlesource.com/c/public/gem5/+/34255

--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Wed, Sep 9, 2020 at 12:58 PM jenkins-no-reply--- via gem5-dev <
gem5-dev@gem5.org> wrote:

> See  >
>
> Changes:
>
> [gabeblack] arch: Add a virtual destructor to BaseHTMCheckpoint.
>
> [gabeblack] cpu: Fix style and add overrides to bas_dyn_inst.hh.
>
> [gabeblack] mem: Remove the unused nvm private member from
> NVMInterface::Rank.
>
> [Andreas.Sandberg] sim: Expose the system's byte order as a param
>
> [Jason Lowe-Power] cpu-o3: convert commit to new style stats
>
> [Jason Lowe-Power] cpu-o3: convert decode to new style stats
>
> [Jason Lowe-Power] cpu-o3: convert lsq_unit to new style stats
>
> [Jason Lowe-Power] cpu-o3: convert rob to new style stats
>
> [Jason Lowe-Power] cpu-o3: convert rename to new style stats
>
> [giacomo.travaglini] arch-arm: Fix ArmISA namespace requirement for TME
> instructions
>
>
> --
> [...truncated 279.99 KB...]
>  [  CC] MIPS/base/fenv.c -> .o
>  [CONFIG H] HAVE_VALGRIND, 0 -> MIPS/config/have_valgrind.hh
>  [ CXX] MIPS/base/fiber.cc -> .o
>  [ CXX] MIPS/base/framebuffer.cc -> .o
>  [LINK]  -> MIPS/dev/pci/lib.o.partial
>  [ CXX] MIPS/base/hostinfo.cc -> .o
>  [ CXX] MIPS/base/inet.cc -> .o
>  [ CXX] MIPS/base/inifile.cc -> .o
>  [ CXX] MIPS/base/logging.cc -> .o
>  [ CXX] MIPS/base/match.cc -> .o
>  [ CXX] MIPS/base/output.cc -> .o
>  [ CXX] MIPS/base/pixel.cc -> .o
>  [ CXX] MIPS/base/pollevent.cc -> .o
>  [ CXX] MIPS/base/random.cc -> .o
>  [ TRACING]  -> MIPS/debug/GDBAll.hh
>  [ CXX] MIPS/base/remote_gdb.cc -> .o
>  [ CXX] MIPS/base/socket.cc -> .o
>  [ CXX] MIPS/base/statistics.cc -> .o
>  [ CXX] MIPS/base/str.cc -> .o
>  [CONFIG H] USE_POSIX_CLOCK, 1 -> MIPS/config/use_posix_clock.hh
>  [ CXX] MIPS/base/time.cc -> .o
>  [ CXX] MIPS/base/version.cc -> .o
>  [ TRACING]  -> MIPS/debug/FmtFlag.hh
>  [ TRACING]  -> MIPS/debug/FmtStackTrace.hh
>  [ TRACING]  -> MIPS/debug/FmtTicksOff.hh
>  [ CXX] MIPS/base/trace.cc -> .o
>  [ CXX] MIPS/base/types.cc -> .o
>  [ CXX] MIPS/base/loader/dtb_file.cc -> .o
>  [ CXX] MIPS/base/loader/elf_object.cc -> .o
>  [ CXX] MIPS/base/loader/image_file_data.cc -> .o
>  [ CXX] MIPS/base/loader/memory_image.cc -> .o
>  [ CXX] MIPS/base/loader/object_file.cc -> .o
>  [ CXX] MIPS/base/loader/symtab.cc -> .o
>  [ TRACING]  -> MIPS/debug/Stats.hh
>  [ CXX] MIPS/base/stats/group.cc -> .o
>  [ CXX] MIPS/base/stats/text.cc -> .o
>  [ CXX] MIPS/mem/cache/replacement_policies/bip_rp.cc -> .o
>  [ CXX] MIPS/mem/cache/replacement_policies/brrip_rp.cc -> .o
>  [ CXX] MIPS/mem/cache/replacement_policies/fifo_rp.cc -> .o
>  [ CXX] MIPS/mem/cache/replacement_policies/lfu_rp.cc -> .o
>  [ CXX] MIPS/mem/cache/replacement_policies/lru_rp.cc -> .o
>  [ CXX] MIPS/mem/cache/replacement_policies/mru_rp.cc -> .o
>  [ CXX] MIPS/mem/cache/replacement_policies/random_rp.cc -> .o
>  [ CXX] MIPS/mem/cache/replacement_policies/second_chance_rp.cc -> .o
>  [ CXX] MIPS/mem/cache/replacement_policies/tree_plru_rp.cc -> .o
>  [ CXX] MIPS/mem/cache/replacement_policies/weighted_lru_rp.cc -> .o
>  [ CXX] MIPS/mem/protocol/atomic.cc -> .o
>  [ CXX] MIPS/mem/protocol/functional.cc -> .o
>  [LINK]  -> MIPS/base/lib.o.partial
>  [LINK]  -> MIPS/mem/cache/replacement_policies/lib.o.partial
>  [ CXX] MIPS/mem/protocol/timing.cc -> .o
>  [ CXX] MIPS/systemc/channel/messages.cc -> .o
>  [ CXX] MIPS/systemc/channel/sc_clock.cc -> .o
>  [ CXX] MIPS/systemc/channel/sc_event_queue.cc -> .o
>  [ CXX] MIPS/systemc/channel/sc_in_resolved.cc -> .o
>  [LINK]  -> MIPS/mem/protocol/lib.o.partial
>  [ CXX] MIPS/systemc/channel/sc_inout_resolved.cc -> .o
>  [ CXX] MIPS/systemc/channel/sc_out_resolved.cc -> .o
>  [ CXX] MIPS/systemc/channel/sc_mutex.cc -> .o
>  [ CXX] MIPS/systemc/channel/sc_semaphore.cc -> .o
>  [ CXX] MIPS/systemc/channel/sc_signal.cc -> .o
>  [ CXX] MIPS/systemc/channel/sc_signal_resolved.cc -> .o
>  [ CXX] MIPS/python/pybind11/core.cc -> .o
>  [ CXX] MIPS/python/pybind11/debug.cc -> .o
>  [ CXX] MIPS/python/pybind11/event.cc -> .o
>  [LINK]  -> MIPS/systemc/channel/lib.o.partial
>  [CONFIG H] USE_HDF5, 0 -> MIPS/config/use_hdf5.hh
>  [ CXX] MIPS/python/pybind11/stats.cc -> .o
>  [ CXX] MIPS/dev/i2c/bus.cc -> .o
>  [LINK]  -> MIPS/dev/i2c/lib.o.partial
>  [ TRACING]  -> MIPS/debug/SimpleTrace.hh
>  [ CXX] MIPS/cpu/o3/probe/simple_trace.cc -> .o
>  [ TRACING]  -> MIPS/debug/ElasticTrace.hh
>  [ CXX] MIPS/cpu/o3/probe/elastic_trace.cc -> .o
>  [ TRACING]  -> MIPS/debug/RubyTest.hh
>  [ CXX]

[gem5-dev] Re: Build failed in Jenkins: Compiler-Checks #22

2020-09-09 Thread Bobby Bruce via gem5-dev

We're running into a lot of errors today :). I've fixed all the compilation
errors. These are currently under review here:

https://gem5-review.googlesource.com/c/public/gem5/+/34256
https://gem5-review.googlesource.com/c/public/gem5/+/34255

--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Wed, Sep 9, 2020 at 6:18 PM jenkins-no-reply--- via gem5-dev <
gem5-dev@gem5.org> wrote:

> See <
> https://jenkins.gem5.org/job/Compiler-Checks/22/display/redirect?page=changes
> >
>
> Changes:
>
> [gabeblack] misc: Remove the "fault" parameter from syscall functions.
>
> [giacomo.travaglini] arch, mem: Initial Hardware Transactional Memory
> implementation
>
> [giacomo.travaglini] arch: Add uReset helper to UPCState
>
> [giacomo.travaglini] mem: Relax packet limit in packet queue
>
> [msamani] mem,ext: Fixed DRAMSim2 Integration
>
> [msamani] mem,ext: Integrating DRAMSim3 with gem5
>
> [hoanguyen] ext: Revert "ext: remove libelf"
>
> [hoanguyen] ext: Revert "base: Use system libelf instead of ext"
>
> [hoanguyen] ext: Link gem5 libelf to ext/libelf/libelf.a
>
> [eavivi] cpu-o3: convert fetch to new style stats
>
> [eavivi] cpu-kvm: convert kvm base to new style stats
>
> [gabeblack] arch: Use a fault to trigger system calls in SE mode.
>
> [esbrickey] cpu: convert bpred_unit to new style stats
>
> [esbrickey] cpu: convert loop_predictor to new style stats
>
> [esbrickey] cpu: convert statistical_corrector to new style stats
>
> [esbrickey] cpu: convert tage_base to new style stats
>
> [eavivi] cpu: convert thread_state to new style stats
>
> [kyleroarty1716] util: Install scons 3.1 from pip in gcn-gpu dockerfile
>
> [Jason Lowe-Power] cpu: Set ContextId on request from trace CPU
>
> [mattdsinclair] util: add dev-hsa commit message tag
>
> [Bobby R. Bruce] tests: Removed realview tests from .testignore
>
> [Bobby R. Bruce] tests: Removed `tests/halt.sh`
>
> [Bobby R. Bruce] tests: Removed tests/configs/tgen files
>
> [Bobby R. Bruce] tests: Removed SPARC Insttests from .testignore
>
> [Bobby R. Bruce] tests: Removed the ignoring of tests
>
> [Bobby R. Bruce] tests: Removed test-progs/pthread
>
> [Bobby R. Bruce] tests: Removed test-progs/asmtest
>
> [Bobby R. Bruce] tests: Moved realview config files
>
> [Bobby R. Bruce] tests: Removed learning-gem5 tests/configs
>
> [Bobby R. Bruce] tests: Standardized test resources download dir
>
> [Bobby R. Bruce] tests,arch-arm: Pass gem5_root as an arg in run.py
>
> [Bobby R. Bruce] tests: Removed author info from insttest test.py
>
> [danguria] cpu: Failure to restore RAS during squash
>
> [srikant.bharadwaj] mem-garnet: Integration of HeteroGarnet
>
> [srikant.bharadwaj] mem-garnet: Initialize unused Credit members
>
> [srikant.bharadwaj] mem-garnet: Flexible VCs per Vnet for each router
>
> [srikant.bharadwaj] mem-garnet: Add a check to see if router is already
> scheduled
>
> [srikant.bharadwaj] mem-garnet: Separable allocator in Garnet not fair
> enough.
>
> [eavivi] learning-gem5: convert simple cache to new style stats
>
> [Bobby R. Bruce] misc,scons,util: Drop support for GCC 4
>
> [Andreas.Sandberg] base: Cleanup Debug::CompoundFlag
>
> [Andreas.Sandberg] scons: Simplify arch enum generation
>
> [Andreas.Sandberg] base: Remove unused Debug::All flag
>
> [Andreas.Sandberg] base: Cleanup debug flags API
>
> [Andreas.Sandberg] python: Add the ability to check if a debug flag has
> been enabled
>
> [Andreas.Sandberg] python: Remove unused debug APIs
>
> [giacomo.travaglini] cpu: Add HtmCpu DebugFlag
>
> [giacomo.travaglini] cpu: Add HTM Instruction Flags
>
> [giacomo.travaglini] cpu: Add HTM CPU API
>
> [giacomo.travaglini] mem: Add HTM fields to Request
>
> [gabeblack] mem: Re-remove the arch/isa_traits.hh include in the base
> prefetcher.
>
> [giacomo.travaglini] cpu: Add HTM ExecContext API
>
> [giacomo.travaglini] cpu: Add HTM ThreadContext API
>
> [giacomo.travaglini] sim: Add HTM Generic Fault
>
> [giacomo.travaglini] cpu: Base dyn inst HTM flags getter
>
> [giacomo.travaglini] mem: Add HTM fields to the Packet object
>
> [giacomo.travaglini] mem-ruby: HTM mem implementation
>
> [giacomo.travaglini] cpu: HTM Implementation for TimingCPU
>
> [giacomo.travaglini] cpu: HTM Implementation for O3CPU
>
> [Bobby R. Bruce] tests,arch-sparc: Move SPARC insttests to long
>
> [hoanguyen] base: Tag API methods and variables in bitfield.hh
>
> [hoanguyen] base: Tag API methods in coroutine.hh
>
> [hoanguyen] base: Tag API methods and variables in fiber.hh
>
> [hoanguyen] base: Tag API methods and macros in logger.hh
>
> [hoanguyen] base: Tag API methods and variables in chunk_generator.hh
>
> [hoanguyen] base: Tag API methods and variables to circular_queue.hh
>
> [Andreas.Sandberg] base, sim: Make ByteOrder into a ScopedEnum accessible
> to Python
>
> [hoanguyen] base: Tag API methods and variables in random.hh
>
> [hoanguyen] base: Tag API methods in amo.hh
>
> [hoanguyen] base: Tag API methods and variables in

[gem5-dev] Change in gem5/gem5[develop]: arch-mips: Replaced `BigEndianByteOrder` in MIPS

2020-09-09 Thread Bobby R. Bruce (Gerrit) via gem5-dev

Bobby R. Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34255 )



Change subject: arch-mips: Replaced `BigEndianByteOrder` in MIPS
..

arch-mips: Replaced `BigEndianByteOrder` in MIPS

The following change removed the `BigEndianByteOrder` enum and replaced
it with `ByteOrder:big`:
https://gem5-review.googlesource.com/c/public/gem5/+/33174

This change was not propogated to `src/arch/mips/isa/decoder.isa` and
`src/arch/mips/isa/formats/mem.isa`, and therefore caused compilation
errors. This commit fixes this error.

Change-Id: I3967eb9e9236a7a95318c17ca410b613b8473eed
---
M src/arch/mips/isa/decoder.isa
M src/arch/mips/isa/formats/mem.isa
2 files changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index d35fc18..f62000e 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -1532,7 +1532,7 @@
 if (Rs<2:0> == 0) {
 Fd_ud = Fs_ud;
 } else if (Rs<2:0> == 4) {
-if (GuestByteOrder == BigEndianByteOrder)
+if (GuestByteOrder == ByteOrder::big)
 Fd_ud = Fs_ud<31:0> << 32 | Ft_ud<63:32>;
 else
 Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>;
diff --git a/src/arch/mips/isa/formats/mem.isa  
b/src/arch/mips/isa/formats/mem.isa

index 4f6f2ee..491dd0c 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -497,7 +497,7 @@
 uint32_t mem_word = Mem_uw;
 uint32_t unalign_addr = Rs + disp;
 uint32_t byte_offset = unalign_addr & 3;
-if (GuestByteOrder == BigEndianByteOrder)
+if (GuestByteOrder == ByteOrder::big)
 byte_offset ^= 3;
 '''

@@ -515,7 +515,7 @@
 uint32_t mem_word = 0;
 uint32_t unaligned_addr = Rs + disp;
 uint32_t byte_offset = unaligned_addr & 3;
-if (GuestByteOrder == BigEndianByteOrder)
+if (GuestByteOrder == ByteOrder::big)
 byte_offset ^= 3;
 fault = readMemAtomicLE(xc, traceData, EA, mem_word,  
memAccessFlags);

 '''

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34255
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3967eb9e9236a7a95318c17ca410b613b8473eed
Gerrit-Change-Number: 34255
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-mips: Replaced `BigEndianByteOrder` in MIPS

2020-09-09 Thread Bobby R. Bruce (Gerrit) via gem5-dev

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34255 )


Change subject: arch-mips: Replaced `BigEndianByteOrder` in MIPS
..

arch-mips: Replaced `BigEndianByteOrder` in MIPS

The following change removed the `BigEndianByteOrder` enum and replaced
it with `ByteOrder:big`:
https://gem5-review.googlesource.com/c/public/gem5/+/33174

This change was not propogated to `src/arch/mips/isa/decoder.isa` and
`src/arch/mips/isa/formats/mem.isa`, and therefore caused compilation
errors. This caused the Nightly Build to fail:
https://www.mail-archive.com/gem5-dev@gem5.org/msg35900.html

This commit fixes this error.

Change-Id: I3967eb9e9236a7a95318c17ca410b613b8473eed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34255
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/mips/isa/decoder.isa
M src/arch/mips/isa/formats/mem.isa
2 files changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index d35fc18..f62000e 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -1532,7 +1532,7 @@
 if (Rs<2:0> == 0) {
 Fd_ud = Fs_ud;
 } else if (Rs<2:0> == 4) {
-if (GuestByteOrder == BigEndianByteOrder)
+if (GuestByteOrder == ByteOrder::big)
 Fd_ud = Fs_ud<31:0> << 32 | Ft_ud<63:32>;
 else
 Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>;
diff --git a/src/arch/mips/isa/formats/mem.isa  
b/src/arch/mips/isa/formats/mem.isa

index 4f6f2ee..491dd0c 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -497,7 +497,7 @@
 uint32_t mem_word = Mem_uw;
 uint32_t unalign_addr = Rs + disp;
 uint32_t byte_offset = unalign_addr & 3;
-if (GuestByteOrder == BigEndianByteOrder)
+if (GuestByteOrder == ByteOrder::big)
 byte_offset ^= 3;
 '''

@@ -515,7 +515,7 @@
 uint32_t mem_word = 0;
 uint32_t unaligned_addr = Rs + disp;
 uint32_t byte_offset = unaligned_addr & 3;
-if (GuestByteOrder == BigEndianByteOrder)
+if (GuestByteOrder == ByteOrder::big)
 byte_offset ^= 3;
 fault = readMemAtomicLE(xc, traceData, EA, mem_word,  
memAccessFlags);

 '''

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34255
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3967eb9e9236a7a95318c17ca410b613b8473eed
Gerrit-Change-Number: 34255
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Build failed in Jenkins: Compiler-Checks #22

2020-09-09 Thread jenkins-no-reply--- via gem5-dev

See 


Changes:

[gabeblack] misc: Remove the "fault" parameter from syscall functions.

[giacomo.travaglini] arch, mem: Initial Hardware Transactional Memory 
implementation

[giacomo.travaglini] arch: Add uReset helper to UPCState

[giacomo.travaglini] mem: Relax packet limit in packet queue

[msamani] mem,ext: Fixed DRAMSim2 Integration

[msamani] mem,ext: Integrating DRAMSim3 with gem5

[hoanguyen] ext: Revert "ext: remove libelf"

[hoanguyen] ext: Revert "base: Use system libelf instead of ext"

[hoanguyen] ext: Link gem5 libelf to ext/libelf/libelf.a

[eavivi] cpu-o3: convert fetch to new style stats

[eavivi] cpu-kvm: convert kvm base to new style stats

[gabeblack] arch: Use a fault to trigger system calls in SE mode.

[esbrickey] cpu: convert bpred_unit to new style stats

[esbrickey] cpu: convert loop_predictor to new style stats

[esbrickey] cpu: convert statistical_corrector to new style stats

[esbrickey] cpu: convert tage_base to new style stats

[eavivi] cpu: convert thread_state to new style stats

[kyleroarty1716] util: Install scons 3.1 from pip in gcn-gpu dockerfile

[Jason Lowe-Power] cpu: Set ContextId on request from trace CPU

[mattdsinclair] util: add dev-hsa commit message tag

[Bobby R. Bruce] tests: Removed realview tests from .testignore

[Bobby R. Bruce] tests: Removed `tests/halt.sh`

[Bobby R. Bruce] tests: Removed tests/configs/tgen files

[Bobby R. Bruce] tests: Removed SPARC Insttests from .testignore

[Bobby R. Bruce] tests: Removed the ignoring of tests

[Bobby R. Bruce] tests: Removed test-progs/pthread

[Bobby R. Bruce] tests: Removed test-progs/asmtest

[Bobby R. Bruce] tests: Moved realview config files

[Bobby R. Bruce] tests: Removed learning-gem5 tests/configs

[Bobby R. Bruce] tests: Standardized test resources download dir

[Bobby R. Bruce] tests,arch-arm: Pass gem5_root as an arg in run.py

[Bobby R. Bruce] tests: Removed author info from insttest test.py

[danguria] cpu: Failure to restore RAS during squash

[srikant.bharadwaj] mem-garnet: Integration of HeteroGarnet

[srikant.bharadwaj] mem-garnet: Initialize unused Credit members

[srikant.bharadwaj] mem-garnet: Flexible VCs per Vnet for each router

[srikant.bharadwaj] mem-garnet: Add a check to see if router is already 
scheduled

[srikant.bharadwaj] mem-garnet: Separable allocator in Garnet not fair enough.

[eavivi] learning-gem5: convert simple cache to new style stats

[Bobby R. Bruce] misc,scons,util: Drop support for GCC 4

[Andreas.Sandberg] base: Cleanup Debug::CompoundFlag

[Andreas.Sandberg] scons: Simplify arch enum generation

[Andreas.Sandberg] base: Remove unused Debug::All flag

[Andreas.Sandberg] base: Cleanup debug flags API

[Andreas.Sandberg] python: Add the ability to check if a debug flag has been 
enabled

[Andreas.Sandberg] python: Remove unused debug APIs

[giacomo.travaglini] cpu: Add HtmCpu DebugFlag

[giacomo.travaglini] cpu: Add HTM Instruction Flags

[giacomo.travaglini] cpu: Add HTM CPU API

[giacomo.travaglini] mem: Add HTM fields to Request

[gabeblack] mem: Re-remove the arch/isa_traits.hh include in the base 
prefetcher.

[giacomo.travaglini] cpu: Add HTM ExecContext API

[giacomo.travaglini] cpu: Add HTM ThreadContext API

[giacomo.travaglini] sim: Add HTM Generic Fault

[giacomo.travaglini] cpu: Base dyn inst HTM flags getter

[giacomo.travaglini] mem: Add HTM fields to the Packet object

[giacomo.travaglini] mem-ruby: HTM mem implementation

[giacomo.travaglini] cpu: HTM Implementation for TimingCPU

[giacomo.travaglini] cpu: HTM Implementation for O3CPU

[Bobby R. Bruce] tests,arch-sparc: Move SPARC insttests to long

[hoanguyen] base: Tag API methods and variables in bitfield.hh

[hoanguyen] base: Tag API methods in coroutine.hh

[hoanguyen] base: Tag API methods and variables in fiber.hh

[hoanguyen] base: Tag API methods and macros in logger.hh

[hoanguyen] base: Tag API methods and variables in chunk_generator.hh

[hoanguyen] base: Tag API methods and variables to circular_queue.hh

[Andreas.Sandberg] base, sim: Make ByteOrder into a ScopedEnum accessible to 
Python

[hoanguyen] base: Tag API methods and variables in random.hh

[hoanguyen] base: Tag API methods in amo.hh

[hoanguyen] base: Tag API methods and variables in addr_range_map.hh

[hoanguyen] base: Tag API methods and variables in channel_addr.hh

[hoanguyen] base: Tag API methods in socket.hh

[hoanguyen] base: Tag API methods and variables in trie.hh

[hoanguyen] base: Tag API methods and variables in bitunion.hh

[hoanguyen] base: Tag API methods and variables in callback.hh

[hoanguyen] base: Tag API methods and variables in addr_range.hh

[hoanguyen] base: Tag API methods in pollevent.hh

[hoanguyen] base: Tag API methods in stl_helpers.hh

[hoanguyen] base: Tag API methods in remote_gdb.hh

[hoanguyen] base: Tag API methods to trace.hh

[hoanguyen] base: Tag API methods in condcodes.hh

[hoanguyen] base: Tag API methods

[gem5-dev] Change in gem5/gem5[develop]: cpu: Fix style and add overrides to bas_dyn_inst.hh.

2020-09-09 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34216 )


Change subject: cpu: Fix style and add overrides to bas_dyn_inst.hh.
..

cpu: Fix style and add overrides to bas_dyn_inst.hh.

Either return types, brackets and the function body should all be on
their own line, or the entire function should be on a single line.

Consistently place the * or & up against the variable name and not the
type name. There isn't an official rule for which to use, but the
majority of existing uses were this way.

Add overrides for overridden virtual methods.

These fixes get rid of compiler warnings which are breaking the build
for me.

Change-Id: Ifc6ace4794a66ffd031ee686f6b6ef888004d786
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34216
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/base_dyn_inst.hh
1 file changed, 133 insertions(+), 75 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index b0e9ef2..56b9114 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -291,30 +291,34 @@
 //
 

-void demapPage(Addr vaddr, uint64_t asn)
+void
+demapPage(Addr vaddr, uint64_t asn) override
 {
 cpu->demapPage(vaddr, asn);
 }
-void demapInstPage(Addr vaddr, uint64_t asn)
+void
+demapInstPage(Addr vaddr, uint64_t asn)
 {
 cpu->demapPage(vaddr, asn);
 }
-void demapDataPage(Addr vaddr, uint64_t asn)
+void
+demapDataPage(Addr vaddr, uint64_t asn)
 {
 cpu->demapPage(vaddr, asn);
 }

 Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags,
-const std::vector& byte_enable = std::vector());
+const std::vector _enable=std::vector())  
override;


 Fault initiateHtmCmd(Request::Flags flags) override;

 Fault writeMem(uint8_t *data, unsigned size, Addr addr,
Request::Flags flags, uint64_t *res,
-   const std::vector& byte_enable =  
std::vector());
+   const std::vector  
_enable=std::vector())

+   override;

 Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
- AtomicOpFunctorPtr amo_op);
+ AtomicOpFunctorPtr amo_op) override;

 /** True if the DTB address translation has started. */
 bool translationStarted() const { return  
instFlags[TranslationStarted]; }

@@ -329,8 +333,16 @@
  * snoop invalidate modifies the line, in which case we need to squash.
  * If nothing modified the line the order doesn't matter.
  */
-bool possibleLoadViolation() const { return  
instFlags[PossibleLoadViolation]; }
-void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation]  
= f; }

+bool
+possibleLoadViolation() const
+{
+return instFlags[PossibleLoadViolation];
+}
+void
+possibleLoadViolation(bool f)
+{
+instFlags[PossibleLoadViolation] = f;
+}

 /** True if the address hit a external snoop while sitting in the LSQ.
  * If this is true and a older instruction sees it, this instruction  
must

@@ -343,7 +355,8 @@
  * Returns true if the DTB address translation is being delayed due to  
a hw

  * page table walk.
  */
-bool isTranslationDelayed() const
+bool
+isTranslationDelayed() const
 {
 return (translationStarted() && !translationCompleted());
 }
@@ -356,13 +369,15 @@
 /** Returns the physical register index of the i'th destination
  *  register.
  */
-PhysRegIdPtr renamedDestRegIdx(int idx) const
+PhysRegIdPtr
+renamedDestRegIdx(int idx) const
 {
 return _destRegIdx[idx];
 }

 /** Returns the physical register index of the i'th source register. */
-PhysRegIdPtr renamedSrcRegIdx(int idx) const
+PhysRegIdPtr
+renamedSrcRegIdx(int idx) const
 {
 assert(TheISA::MaxInstSrcRegs > idx);
 return _srcRegIdx[idx];
@@ -371,7 +386,8 @@
 /** Returns the flattened register index of the i'th destination
  *  register.
  */
-const RegId& flattenedDestRegIdx(int idx) const
+const RegId &
+flattenedDestRegIdx(int idx) const
 {
 return _flatDestRegIdx[idx];
 }
@@ -379,7 +395,8 @@
 /** Returns the physical register index of the previous physical  
register

  *  that remapped to the same logical register index.
  */
-PhysRegIdPtr prevDestRegIdx(int idx) const
+PhysRegIdPtr
+prevDestRegIdx(int idx) const
 {
 return _prevDestRegIdx[idx];
 }
@@ -387,9 +404,9 @@
 /** Renames a destination register to a physical register.  Also

[gem5-dev] Change in gem5/gem5[develop]: arch: Add a virtual destructor to BaseHTMCheckpoint.

2020-09-09 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34215 )


Change subject: arch: Add a virtual destructor to BaseHTMCheckpoint.
..

arch: Add a virtual destructor to BaseHTMCheckpoint.

Since it has virtual methods, it should also have a virtual destructor.
My compiler complains otherwise, which breaks my build.

Change-Id: I44bba97b76931bab6e3511fcdee79831080c12d4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34215
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/generic/htm.hh
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/generic/htm.hh b/src/arch/generic/htm.hh
index 74e2d44..5f45f5d 100644
--- a/src/arch/generic/htm.hh
+++ b/src/arch/generic/htm.hh
@@ -137,6 +137,7 @@
 {
 reset();
 }
+virtual ~BaseHTMCheckpoint() {}

 /**
  * Every ISA implementing HTM support should override the

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I44bba97b76931bab6e3511fcdee79831080c12d4
Gerrit-Change-Number: 34215
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem: Remove the unused nvm private member from NVMInterface::Rank.

2020-09-09 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34217 )


Change subject: mem: Remove the unused nvm private member from  
NVMInterface::Rank.

..

mem: Remove the unused nvm private member from NVMInterface::Rank.

This unused (and otherwise unusable) member caused a compiler warning
and broke the build for me. It can be reintroduced if used in the
future.

Change-Id: I48181f6bca60c059e74727290950adfb9a194680
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34217
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/mem_interface.cc
M src/mem/mem_interface.hh
2 files changed, 1 insertion(+), 9 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/mem_interface.cc b/src/mem/mem_interface.cc
index 7817c4a..307cf92 100644
--- a/src/mem/mem_interface.cc
+++ b/src/mem/mem_interface.cc
@@ -2043,8 +2043,7 @@

 NVMInterface::Rank::Rank(const NVMInterfaceParams* _p,
  int _rank, NVMInterface& _nvm)
-: EventManager(&_nvm), nvm(_nvm), rank(_rank),
-  banks(_p->banks_per_rank)
+: EventManager(&_nvm), rank(_rank), banks(_p->banks_per_rank)
 {
 for (int b = 0; b < _p->banks_per_rank; b++) {
 banks[b].bank = b;
diff --git a/src/mem/mem_interface.hh b/src/mem/mem_interface.hh
index 9844002..b67cdb0 100644
--- a/src/mem/mem_interface.hh
+++ b/src/mem/mem_interface.hh
@@ -1026,13 +1026,6 @@
  */
 class Rank : public EventManager
 {
-  private:
-
-/**
- * A reference to the parent NVMInterface instance
- */
-NVMInterface& nvm;
-
   public:

 /**

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34217
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I48181f6bca60c059e74727290950adfb9a194680
Gerrit-Change-Number: 34217
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Wendy Elsasser 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Build failed in Jenkins: Nightly #62

2020-09-09 Thread jenkins-no-reply--- via gem5-dev

See 

Changes:

[giacomo.travaglini] cpu: Add HTM ExecContext API

[giacomo.travaglini] cpu: Add HTM ThreadContext API

[giacomo.travaglini] sim: Add HTM Generic Fault

[giacomo.travaglini] cpu: Base dyn inst HTM flags getter

[giacomo.travaglini] mem: Add HTM fields to the Packet object

[giacomo.travaglini] mem-ruby: HTM mem implementation

[giacomo.travaglini] cpu: HTM Implementation for TimingCPU

[giacomo.travaglini] cpu: HTM Implementation for O3CPU

[Bobby R. Bruce] tests,arch-sparc: Move SPARC insttests to long

[hoanguyen] base: Tag API methods and variables in bitfield.hh

[hoanguyen] base: Tag API methods in coroutine.hh

[hoanguyen] base: Tag API methods and variables in fiber.hh

[hoanguyen] base: Tag API methods and macros in logger.hh

[hoanguyen] base: Tag API methods and variables in chunk_generator.hh

[hoanguyen] base: Tag API methods and variables to circular_queue.hh

[Andreas.Sandberg] base, sim: Make ByteOrder into a ScopedEnum accessible to 
Python

[hoanguyen] base: Tag API methods and variables in random.hh

[hoanguyen] base: Tag API methods in amo.hh

[hoanguyen] base: Tag API methods and variables in addr_range_map.hh

[hoanguyen] base: Tag API methods and variables in channel_addr.hh

[hoanguyen] base: Tag API methods in socket.hh

[hoanguyen] base: Tag API methods and variables in trie.hh

[hoanguyen] base: Tag API methods and variables in bitunion.hh

[hoanguyen] base: Tag API methods and variables in callback.hh

[hoanguyen] base: Tag API methods and variables in addr_range.hh

[hoanguyen] base: Tag API methods in pollevent.hh

[hoanguyen] base: Tag API methods in stl_helpers.hh

[hoanguyen] base: Tag API methods in remote_gdb.hh

[hoanguyen] base: Tag API methods to trace.hh

[hoanguyen] base: Tag API methods in condcodes.hh

[hoanguyen] base: Tag API methods in sat_counter.hh

[hoanguyen] base: Tag API methods in intmath.hh

[hoanguyen] base: Tag API variables in version.cc

[hoanguyen] base: Tag API methods in flags.hh

[hoanguyen] base: Tag API variables in date.cc

[hoanguyen] base: Tag API methods in inet.hh

[hoanguyen] base: Tag API methods to debug.hh

[hoanguyen] base: Tag API methods in crc.hh

[hoanguyen] ext: Make the testing-results folder visible

[Jason Lowe-Power] mem: Factor out DRAM interface

[Jason Lowe-Power] mem: Make MemCtrl a ClockedObject

[Jason Lowe-Power] mem: Add NVM interface

[Jason Lowe-Power] mem: Clean up Memory Controller

[Jason Lowe-Power] cpu: convert memtest to new style stats

[hoanguyen] ext: Force testlib to only create one Log object

[hoanguyen] ext: Add post_test_procedure to testlib runner

[hoanguyen] ext,tests: Copy test's output files from /tmp to testing-results

[Jason Lowe-Power] cpu-o3: convert elastic trace to new style stats

[Jason Lowe-Power] cpu: convert trace cpu to new style stats

[gabeblack] arm: Replicate the PageBytes constant in the ArmSystem class.

[gabeblack] dev,arm: Use the ArmSystem::PageBytes constant in the generic timer.

[srikant.bharadwaj] mem-ruby: Check number of vnets when creating links

[hoanguyen] base,misc: Add group definitions for newly tagged API in src/base

[Bobby R. Bruce] arch-arm: Transactional Memory Extension (TME)

[gabeblack] arm: Remove "using namespace ArmISA" from arch/arm/isa_traits.hh.

[Jason Lowe-Power] cpu-minor: convert fetch2 to new style stats


--
[...truncated 243.79 KB...]
 [ CXX] ARM/sim/tags.cc -> .o
 [ CXX] ARM/sim/cxx_config.cc -> .o
 [ TRACING]  -> ARM/debug/CxxConfig.hh
 [ CXX] ARM/sim/cxx_manager.cc -> .o
 [ CXX] ARM/sim/cxx_config_ini.cc -> .o
 [ CXX] ARM/sim/debug.cc -> .o
 [LINK]  -> ARM/mem/ruby/structures/lib.o.partial
 [ CXX] ARM/sim/py_interact.cc -> .o
 [ CXX] ARM/sim/eventq.cc -> .o
 [ CXX] ARM/sim/futex_map.cc -> .o
 [ CXX] ARM/sim/global_event.cc -> .o
 [ CXX] ARM/sim/init.cc -> .o
 [ CXX] ARM/sim/init_signals.cc -> .o
 [ TRACING]  -> ARM/debug/Loader.hh
 [ CXX] ARM/sim/kernel_workload.cc -> .o
 [ CXX] ARM/sim/port.cc -> .o
 [ CXX] ARM/sim/python.cc -> .o
 [ CXX] ARM/sim/redirect_path.cc -> .o
 [ TRACING]  -> ARM/debug/TimeSync.hh
 [ CXX] ARM/sim/root.cc -> .o
 [ CXX] ARM/sim/serialize.cc -> .o
 [ CXX] ARM/sim/drain.cc -> .o
 [ CXX] ARM/sim/sim_events.cc -> .o
 [ CXX] ARM/sim/sim_object.cc -> .o
 [ CXX] ARM/sim/sub_system.cc -> .o
 [ CXX] ARM/sim/ticked_object.cc -> .o
 [ CXX] ARM/sim/simulate.cc -> .o
 [ CXX] ARM/sim/stat_control.cc -> .o
 [ CXX] ARM/sim/stat_register.cc -> .o
 [ TRACING]  -> ARM/debug/ClockDomain.hh
 [ CXX] ARM/sim/clock_domain.cc -> .o
 [ TRACING]  -> ARM/debug/VoltageDomain.hh
 [ CXX] ARM/sim/voltage_domain.cc -> .o
 [ CXX] ARM/sim/se_signal.cc -> .o
 [ CXX] ARM/sim/linear_solver.cc -> .o
 [GENERATE] arm -> ARM/arch/remote_gdb.hh
 [CONFIG H] USE_KVM, 0 -> ARM/config/use_kvm.hh
 [ TRACING]  ->

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix ArmISA namespace requirement for TME instructions

[gem5-dev] Change in gem5/gem5[develop]: sim: Expose the system's byte order as a param

[gem5-dev] Change in gem5/gem5[develop]: base, sim, mem, arch: Remove the dummy CPU in NULL

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: convert commit to new style stats

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: convert lsq_unit to new style stats

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: convert rename to new style stats

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: convert rob to new style stats

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: convert decode to new style stats

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix ArmISA namespace requirement for TME instructions

[gem5-dev] Build failed in Jenkins: Nightly #63

[gem5-dev] Change in gem5/gem5[develop]: cpu: Fixed unused var error when with fast builds

[gem5-dev] Re: Build failed in Jenkins: Nightly #63

[gem5-dev] Re: Build failed in Jenkins: Compiler-Checks #22

[gem5-dev] Change in gem5/gem5[develop]: arch-mips: Replaced `BigEndianByteOrder` in MIPS

[gem5-dev] Change in gem5/gem5[develop]: arch-mips: Replaced `BigEndianByteOrder` in MIPS

[gem5-dev] Build failed in Jenkins: Compiler-Checks #22

[gem5-dev] Change in gem5/gem5[develop]: cpu: Fix style and add overrides to bas_dyn_inst.hh.

[gem5-dev] Change in gem5/gem5[develop]: arch: Add a virtual destructor to BaseHTMCheckpoint.

[gem5-dev] Change in gem5/gem5[develop]: mem: Remove the unused nvm private member from NVMInterface::Rank.

[gem5-dev] Build failed in Jenkins: Nightly #62

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