Re: [gem5-users] Error Simulating Simple Config. file with DerivO3CPU

[Jason Lowe-Power]

Hi Yasir,

Honestly, I'm not exactly sure why. Here's a dump of what's going on:
7319000: system.membus.reqLayer2: The crossbar layer is now busy from tick
7319000 to 7319000
7319000: system.cpu.iew.lsq.thread0: Executing load PC
(0x409d9a=>0x409d9f).(0=>1), [sn:1627]

7319000: system.cpu.iew.lsq.thread0: Read called, load idx: 27, store idx:
2, storeHead: 31 addr: 0x94bc0
7319000: system.cpu.iew.lsq.thread0: Doing memory access for inst [sn:1627]
PC (0x409d9a=>0x409d9f).(0=>1)
7319000: system.membus: recvTimingReq: src system.membus.slave[1] packet
ReadReq [94bc0:94bc7]
7319000: system.membus.snoop_filter: lookupRequest: src
system.membus.slave[1] packet ReadReq [94bc0:94bc7]

7319000: system.membus: recvTimingReq: src system.membus.slave[1] packet
ReadReq [94bc0:94bc7] SF size: 0 lat: 1
7319000: system.membus: forwardTiming for ReadReq [94bc0:94bc7]
7319000: system.membus.reqLayer2: The crossbar layer is now busy from tick
7319000 to 732
7319000: system.cpu.iew.lsq.thread0: Executing load PC
(0x409d9f=>0x409da4).(0=>1), [sn:1628]

7319000: system.cpu.iew.lsq.thread0: Read called, load idx: 28, store idx:
2, storeHead: 31 addr: 0x94bc8
7319000: system.cpu.iew.lsq.thread0: Doing memory access for inst [sn:1628]
PC (0x409d9f=>0x409da4).(0=>1)
7319000: system.membus: recvTimingReq: src system.membus.slave[1] packet
ReadReq [94bc8:94bcf] BUSY
7319000: system.cpu.iew.lsq.thread0: Executing load PC
(0x409da4=>0x409da9).(0=>1), [sn:1629]

7319000: system.cpu.iew.lsq.thread0: Read called, load idx: 29, store idx:
2, storeHead: 31 addr: 0x94bd0
7319000: system.cpu.iew.lsq.thread0: Doing memory access for inst [sn:1629]
PC (0x409da4=>0x409da9).(0=>1)
gem5.opt: build/X86/mem/xbar.cc:190: bool BaseXBar::Layer<SrcType,
DstType>::tryTiming(SrcType*) [with SrcType = SlavePort; DstType =
MasterPort]: Assertion `std::find(waitingForLayer.begin(),
waitingForLayer.end(), src_port) == waitingForLayer.end()' failed.
Program aborted at tick 7319000

My guess is that the O3CPU is trying to issue more than one ld in a single
cycle and the crossbar can't handle that. But I haven't really dug into it
enough to know for sure.

Cheers,
Jason

On Tue, Dec 5, 2017 at 7:39 AM Qureshi Yasir Mahmood <yasir.qure...@epfl.ch>
wrote:

> Hi Jason,
>
>
>
> Is there as specific reason as to why you can’t connect O3 ports directly
> to the crossbar ? I have added Scratchpad memories at the same level as L1.
> I used NonCoherent Xbar to connect the scratch pad and L1 and them
> connected the Xbar to the CPU ports.
>
>
>
> The system worked fine for all CPU models, except for O3, and returned the
> same error as reported in this thread.
>
>
>
> Thanks
>
> Yasir
>
>
>
> *From:* gem5-users [mailto:gem5-users-boun...@gem5.org] *On Behalf Of *Jason
> Lowe-Power
> *Sent:* 14 March 2017 14:19
> *To:* gem5 users mailing list <gem5-users@gem5.org>
> *Subject:* Re: [gem5-users] Error Simulating Simple Config. file with
> DerivO3CPU
>
>
>
> This is because the O3 ports cannot be directly connected to a crossbar.
> You need to use a cache between the ports and the membus. See the two_level
> script.
>
> Jason
>
>
>
> On Mon, Mar 13, 2017, 5:00 PM Muzamil Rafique <muzamil.ravian...@gmail.com>
> wrote:
>
> Hi All,
>
> I tried to simulate simple.py with DerivO3 CPU and got the following error:
>
> command line: build/X86/gem5.opt configs/tutorial/simple.py
>
> Beginning simulation!
> info: Entering event queue @ 0.  Starting simulation...
> gem5.opt: build/X86/mem/xbar.cc:190: bool BaseXBar::Layer<SrcType,
> DstType>::tryTiming(SrcType*) [with SrcType = SlavePort; DstType =
> MasterPort]: Assertion `std::find(waitingForLayer.begin(),
> waitingForLayer.end(), src_port) == waitingForLayer.end()' failed.
>
> Program aborted at tick 5734000
>
> It works fine with TimingSimpleCPU but giving error with DerivO3CPU. Any
> ideas why this error pops up, which was not the case previously?
>
> Thanks
>
> Muzamil
>
>
>
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Re: [gem5-users] Error Simulating Simple Config. file with DerivO3CPU

[Qureshi Yasir Mahmood]

Hi Jason,

Is there as specific reason as to why you can’t connect O3 ports directly to 
the crossbar ? I have added Scratchpad memories at the same level as L1. I used 
NonCoherent Xbar to connect the scratch pad and L1 and them connected the Xbar 
to the CPU ports.

The system worked fine for all CPU models, except for O3, and returned the same 
error as reported in this thread.

Thanks
Yasir

From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of Jason 
Lowe-Power
Sent: 14 March 2017 14:19
To: gem5 users mailing list <gem5-users@gem5.org>
Subject: Re: [gem5-users] Error Simulating Simple Config. file with DerivO3CPU


This is because the O3 ports cannot be directly connected to a crossbar. You 
need to use a cache between the ports and the membus. See the two_level script.

Jason

On Mon, Mar 13, 2017, 5:00 PM Muzamil Rafique 
<muzamil.ravian...@gmail.com<mailto:muzamil.ravian...@gmail.com>> wrote:
Hi All,
I tried to simulate simple.py with DerivO3 CPU and got the following error:

command line: build/X86/gem5.opt configs/tutorial/simple.py

Beginning simulation!
info: Entering event queue @ 0.  Starting simulation...
gem5.opt: build/X86/mem/xbar.cc:190: bool BaseXBar::Layer<SrcType, 
DstType>::tryTiming(SrcType*) [with SrcType = SlavePort; DstType = MasterPort]: 
Assertion `std::find(waitingForLayer.begin(), waitingForLayer.end(), src_port) 
== waitingForLayer.end()' failed.

Program aborted at tick 5734000
It works fine with TimingSimpleCPU but giving error with DerivO3CPU. Any ideas 
why this error pops up, which was not the case previously?
Thanks
Muzamil


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Re: [gem5-users] Error Simulating Simple Config. file with DerivO3CPU

[Jason Lowe-Power]

This is because the O3 ports cannot be directly connected to a crossbar.
You need to use a cache between the ports and the membus. See the two_level
script.

Jason

On Mon, Mar 13, 2017, 5:00 PM Muzamil Rafique 
wrote:

> Hi All,
>
> I tried to simulate simple.py with DerivO3 CPU and got the following error:
>
> command line: build/X86/gem5.opt configs/tutorial/simple.py
>
> Beginning simulation!
> info: Entering event queue @ 0.  Starting simulation...
> gem5.opt: build/X86/mem/xbar.cc:190: bool BaseXBar::Layer DstType>::tryTiming(SrcType*) [with SrcType = SlavePort; DstType =
> MasterPort]: Assertion `std::find(waitingForLayer.begin(),
> waitingForLayer.end(), src_port) == waitingForLayer.end()' failed.
>
> Program aborted at tick 5734000
>
> It works fine with TimingSimpleCPU but giving error with DerivO3CPU. Any
> ideas why this error pops up, which was not the case previously?
>
> Thanks
> Muzamil
>
>
>
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[gem5-users] Error Simulating Simple Config. file with DerivO3CPU

[Muzamil Rafique]

Hi All,

I tried to simulate simple.py with DerivO3 CPU and got the following error:

command line: build/X86/gem5.opt configs/tutorial/simple.py

Beginning simulation!
info: Entering event queue @ 0.  Starting simulation...
gem5.opt: build/X86/mem/xbar.cc:190: bool BaseXBar::Layer::tryTiming(SrcType*) [with SrcType = SlavePort; DstType =
MasterPort]: Assertion `std::find(waitingForLayer.begin(),
waitingForLayer.end(), src_port) == waitingForLayer.end()' failed.

Program aborted at tick 5734000

It works fine with TimingSimpleCPU but giving error with DerivO3CPU. Any
ideas why this error pops up, which was not the case previously?

Thanks
Muzamil
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