Re: [gem5-users] Requests to Main Memory

[Poremba, Matthew]

Hi Reza,


Memory controllers (including NVMain) are behind a slave port and are generally 
not aware of what the cache is doing – In other words, you want to look in the 
gem5 source if you want to do something special for LLC misses. This will be 
different for Ruby and classic caches:

If you are using ruby, you want to look in the SLICC files at your protocol for 
where queueMemoryRead and queueMemoryWrite are called from the LLC/directory 
and see which transitions use them. For example, in MESI_Three_Level this is in 
MESI_Two_Level-dir.sm under the I->IM transition. The sending and receiving of 
memory requests is handled in AbstractController.cc.

I’m not an expert on classic caches, but I believe you could start with the 
call to memSidePort->sendTimingReq and follow the control flow through cache.cc 
to find out where requests are sent and responses are received.


-Matt

From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of Mohammad 
Reza Jokar
Sent: Wednesday, February 08, 2017 7:13 AM
To: gem5 users mailing list <gem5-users@gem5.org>
Subject: Re: [gem5-users] Requests to Main Memory

Hi Jason,

Thank you for your response and reference to your book. I will read that.
I'm using NVmain as memory type. In this case, should I look into gem5 source 
files or NVmain source files? I'm looking for a file/function that checks if 
the access to last level cache is a miss, then sends the request to main memory.


Thank you.
Reza

On Wed, Feb 8, 2017 at 9:04 AM, Jason Lowe-Power 
<ja...@lowepower.com<mailto:ja...@lowepower.com>> wrote:
Hi Reza,

This is handled by the port interface between the cache and the main memory. 
For instance, at the DRAM controller, every request calls recvTimingReq(). You 
may learn something from this chapter of my book: 
http://learning.gem5.org/book/part2/memoryobject.html. The caches and the 
memory controllers are just MemObj's.

Cheers,
Jason

On Wed, Feb 8, 2017 at 8:57 AM Mohammad Reza Jokar 
<jokar@gmail.com<mailto:jokar@gmail.com>> wrote:
Dear all,

When we experience a cache miss at last level cache, we should send a request 
to main memory and ask for the missed block. I was wondering if you could help 
me find a file or function that does send requests to main memory (and receive 
responses from that.)


Thank you.
Reza
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Re: [gem5-users] Requests to Main Memory

[Mohammad Reza Jokar]

Hi Jason,

Thank you for your response and reference to your book. I will read that.
I'm using NVmain as memory type. In this case, should I look into gem5
source files or NVmain source files? I'm looking for a file/function that
checks if the access to last level cache is a miss, then sends the request
to main memory.


Thank you.
Reza

On Wed, Feb 8, 2017 at 9:04 AM, Jason Lowe-Power 
wrote:

> Hi Reza,
>
> This is handled by the port interface between the cache and the main
> memory. For instance, at the DRAM controller, every request calls
> recvTimingReq(). You may learn something from this chapter of my book:
> http://learning.gem5.org/book/part2/memoryobject.html. The caches and the
> memory controllers are just MemObj's.
>
> Cheers,
> Jason
>
> On Wed, Feb 8, 2017 at 8:57 AM Mohammad Reza Jokar 
> wrote:
>
>> Dear all,
>>
>> When we experience a cache miss at last level cache, we should send a
>> request to main memory and ask for the missed block. I was wondering if you
>> could help me find a file or function that does send requests to main
>> memory (and receive responses from that.)
>>
>>
>> Thank you.
>> Reza
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
>
> ___
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> gem5-users@gem5.org
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>
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Re: [gem5-users] Requests to Main Memory

[Jason Lowe-Power]

Hi Reza,

This is handled by the port interface between the cache and the main
memory. For instance, at the DRAM controller, every request calls
recvTimingReq(). You may learn something from this chapter of my book:
http://learning.gem5.org/book/part2/memoryobject.html. The caches and the
memory controllers are just MemObj's.

Cheers,
Jason

On Wed, Feb 8, 2017 at 8:57 AM Mohammad Reza Jokar 
wrote:

> Dear all,
>
> When we experience a cache miss at last level cache, we should send a
> request to main memory and ask for the missed block. I was wondering if you
> could help me find a file or function that does send requests to main
> memory (and receive responses from that.)
>
>
> Thank you.
> Reza
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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[gem5-users] Requests to Main Memory

[Mohammad Reza Jokar]

Dear all,

When we experience a cache miss at last level cache, we should send a
request to main memory and ask for the missed block. I was wondering if you
could help me find a file or function that does send requests to main
memory (and receive responses from that.)


Thank you.
Reza
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