Re: [gem5-users] Response for WritebackDirty packets (learning.gem5)

[Jason Lowe-Power]

Hi Muhammad,

Generally, if sendTimingReq fails, you have to save the packet so you can
resend it. In my Learning gem5 code, I *try* to simplify the retry logic so
that this is hidden. Instead of saving the packet in the cache code, the
packet is saved in the port code. Also, the code in Learning gem5 was
significantly simplified because it was a blocking cache with only a single
request outstanding at a time.

Jason

On Fri, May 25, 2018 at 11:50 AM Muhammad Ali Akhtar <
muhammadali...@gmail.com> wrote:

> Dear Jason,
>
> Thkns for the response. Just another quick question.
>
> What if memory was busy when u call the "sendTiimingReq" for
> WritebackDirty packet.  In insert() function, when you call
> memport.sendTimingReq for WritebackDirty blocks, you don't save them in
> blocked Packet, in case Memory is blocked and called 'sendReqRetry()" later.
>
>
>
> Muhammad Ali Akhtar
> Principal Design Engineer
> http://www.linkedin.com/in/muhammadakhtar
>
> On Tue, May 22, 2018 at 3:40 AM, Jason Lowe-Power 
> wrote:
>
>> Hello,
>>
>> No. You should not have a response for WritebackDirty. In fact, most
>> (all?) writes do not have responses. See src/mem/packet.cc. (
>> https://gem5.googlesource.com/public/gem5/+/master/src/mem/packet.cc#80)
>> Some commands have the "NeedsResponse" flag set. If so, this request will
>> be turned into a response by whatever memory object fulfills the request
>> (by calling pkt.makeResponse()).
>>
>> I hope this answers your question.
>>
>> Jason
>>
>> On Sat, May 19, 2018 at 11:38 PM Muhammad Ali Akhtar <
>> muhammadali...@gmail.com> wrote:
>>
>>> Hello All,
>>>
>>> Following jason's website, created my own cache.
>>>
>>> On Cache miss, I send the TimingReq to memory, and get the response,
>>> which I handle in "handleResponse".
>>>
>>> during HandleResponse, in case the insertion causes eviction (cache was
>>> full), the insert function generates another memPort.sendTimingReq(). This
>>> time, the pkt is WritebackDirty. However, For this TimingReq() to memory
>>> (WritebackDirty), we don't get any response from memory Write?
>>>
>>> My question is:
>>>
>>> Do we ever get a response from memory for packets of type
>>> "WritebackDirty". When I examine the simulator output, it seems that it
>>> moves on to next instrutions without waiting for response from memory for
>>> this particular request.
>>>
>>>
>>> Muhammad Ali Akhtar
>>> Principal Design Engineer
>>> http://www.linkedin.com/in/muhammadakhtar
>>> ___
>>> gem5-users mailing list
>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>>
>> ___
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>>
>
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Re: [gem5-users] Response for WritebackDirty packets (learning.gem5)

[Muhammad Ali Akhtar]

Dear Jason,

Thkns for the response. Just another quick question.

What if memory was busy when u call the "sendTiimingReq" for WritebackDirty
packet.  In insert() function, when you call memport.sendTimingReq for
WritebackDirty blocks, you don't save them in blocked Packet, in case
Memory is blocked and called 'sendReqRetry()" later.



Muhammad Ali Akhtar
Principal Design Engineer
http://www.linkedin.com/in/muhammadakhtar

On Tue, May 22, 2018 at 3:40 AM, Jason Lowe-Power 
wrote:

> Hello,
>
> No. You should not have a response for WritebackDirty. In fact, most
> (all?) writes do not have responses. See src/mem/packet.cc. (
> https://gem5.googlesource.com/public/gem5/+/master/src/mem/packet.cc#80)
> Some commands have the "NeedsResponse" flag set. If so, this request will
> be turned into a response by whatever memory object fulfills the request
> (by calling pkt.makeResponse()).
>
> I hope this answers your question.
>
> Jason
>
> On Sat, May 19, 2018 at 11:38 PM Muhammad Ali Akhtar <
> muhammadali...@gmail.com> wrote:
>
>> Hello All,
>>
>> Following jason's website, created my own cache.
>>
>> On Cache miss, I send the TimingReq to memory, and get the response,
>> which I handle in "handleResponse".
>>
>> during HandleResponse, in case the insertion causes eviction (cache was
>> full), the insert function generates another memPort.sendTimingReq(). This
>> time, the pkt is WritebackDirty. However, For this TimingReq() to memory
>> (WritebackDirty), we don't get any response from memory Write?
>>
>> My question is:
>>
>> Do we ever get a response from memory for packets of type
>> "WritebackDirty". When I examine the simulator output, it seems that it
>> moves on to next instrutions without waiting for response from memory for
>> this particular request.
>>
>>
>> Muhammad Ali Akhtar
>> Principal Design Engineer
>> http://www.linkedin.com/in/muhammadakhtar
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
___
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Re: [gem5-users] Response for WritebackDirty packets (learning.gem5)

[Jason Lowe-Power]

Hello,

No. You should not have a response for WritebackDirty. In fact, most (all?)
writes do not have responses. See src/mem/packet.cc. (
https://gem5.googlesource.com/public/gem5/+/master/src/mem/packet.cc#80)
Some commands have the "NeedsResponse" flag set. If so, this request will
be turned into a response by whatever memory object fulfills the request
(by calling pkt.makeResponse()).

I hope this answers your question.

Jason

On Sat, May 19, 2018 at 11:38 PM Muhammad Ali Akhtar <
muhammadali...@gmail.com> wrote:

> Hello All,
>
> Following jason's website, created my own cache.
>
> On Cache miss, I send the TimingReq to memory, and get the response, which
> I handle in "handleResponse".
>
> during HandleResponse, in case the insertion causes eviction (cache was
> full), the insert function generates another memPort.sendTimingReq(). This
> time, the pkt is WritebackDirty. However, For this TimingReq() to memory
> (WritebackDirty), we don't get any response from memory Write?
>
> My question is:
>
> Do we ever get a response from memory for packets of type
> "WritebackDirty". When I examine the simulator output, it seems that it
> moves on to next instrutions without waiting for response from memory for
> this particular request.
>
>
> Muhammad Ali Akhtar
> Principal Design Engineer
> http://www.linkedin.com/in/muhammadakhtar
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
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[gem5-users] Response for WritebackDirty packets (learning.gem5)

[Muhammad Ali Akhtar]

Hello All,

Following jason's website, created my own cache.

On Cache miss, I send the TimingReq to memory, and get the response, which
I handle in "handleResponse".

during HandleResponse, in case the insertion causes eviction (cache was
full), the insert function generates another memPort.sendTimingReq(). This
time, the pkt is WritebackDirty. However, For this TimingReq() to memory
(WritebackDirty), we don't get any response from memory Write?

My question is:

Do we ever get a response from memory for packets of type "WritebackDirty".
When I examine the simulator output, it seems that it moves on to next
instrutions without waiting for response from memory for this particular
request.


Muhammad Ali Akhtar
Principal Design Engineer
http://www.linkedin.com/in/muhammadakhtar
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