Re: What's the intent of the "LOAD AND ZERO RIGHTMOST BYTE" instruction?

2019-07-26 Thread Tony Harminc
On Fri, 26 Jul 2019 at 08:52, Mike Schwab  wrote:

> Well, the hardware does move a 256 byte area aligned on a 256 bytes
> boundary very efficiently.  And would allow you to load the register
> with an address without storing the last byte.  So a storage pool with
> allocation of multiples of 256 bytes would greatly helped.
>

I thought of that... But then for generality maybe the instruction should
be something like Load and Zero Rightmost
Sufficient-to-address-a-cache-line Bits.

Tony H.

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Re: What's the intent of the "LOAD AND ZERO RIGHTMOST BYTE" instruction?

2019-07-26 Thread Charles Mills
Take some (any) big C or COBOL program and run it through the relevant
compiler with the pseudo-assembler output option turned on, OPT and ARCH(9
or 10). Then do an ISPF FIND for the op code. No guarantees of course.

Charles


-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
Behalf Of Peter Relson
Sent: Thursday, July 25, 2019 5:04 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: What's the intent of the "LOAD AND ZERO RIGHTMOST BYTE"
instruction?

I don't know the answer, but the usual answer is:
because either the Java team or the compiler team found something 
beneficial to having it.

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Re: What's the intent of the "LOAD AND ZERO RIGHTMOST BYTE" instruction?

2019-07-26 Thread Mike Schwab
Well, the hardware does move a 256 byte area aligned on a 256 bytes
boundary very efficiently.  And would allow you to load the register
with an address without storing the last byte.  So a storage pool with
allocation of multiples of 256 bytes would greatly helped.

On Thu, Jul 25, 2019 at 10:53 PM Phil Smith III  wrote:
>
> Peter Relson wrote:
>
> >I don't know the answer, but the usual answer is:
>
> >because either the Java team or the compiler team found something
>
> >beneficial to having it.
>
>
>
> Which leads one to wonder.at what point does the C in CISC make this a losing 
> proposition? Are we there yet?
>
>
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-- 
Mike A Schwab, Springfield IL USA
Where do Forest Rangers go to get away from it all?

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Re: What's the intent of the "LOAD AND ZERO RIGHTMOST BYTE" instruction?

2019-07-25 Thread Phil Smith III
Peter Relson wrote: 

>I don't know the answer, but the usual answer is:

>because either the Java team or the compiler team found something 

>beneficial to having it.

 

Which leads one to wonder.at what point does the C in CISC make this a losing 
proposition? Are we there yet?


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Re: What's the intent of the "LOAD AND ZERO RIGHTMOST BYTE" instruction?

2019-07-25 Thread Peter Relson
I don't know the answer, but the usual answer is:
because either the Java team or the compiler team found something 
beneficial to having it.

Peter Relson
z/OS Core Technology Design


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Re: What's the intent of the "LOAD AND ZERO RIGHTMOST BYTE" instruction?

2019-07-24 Thread Steve Smith
Argh.  A "LOAD LOGICAL 24 BITS" would actually still be useful. Of course,
we need the other 24 bits :-).

LAN (and LAA) are weird instructions.  The and part (AND or OR) (does this
read like "Alice in Wonderland" yet?) is performed on the *second* operand
-- the field in storage.  They have some fairly obvious uses (similar to
CS), but the names seem misleading to me.

As for LZRF... maybe somebody finally got an Easter egg into the
architecture.  You'd think that a L / NILL sequence wouldn't likely be the
worst bottleneck they needed to solve last year.

sas



On Wed, Jul 24, 2019 at 6:00 PM zMan  wrote:

> Obviously it's for little-Endian 24-bit addressing mode!
>
> On Wed, Jul 24, 2019 at 3:18 PM Tony Harminc  wrote:
>
> > On Wed, 24 Jul 2019 at 08:35, Vernooij, Kees (ITOP NM) - KLM <
> > kees.verno...@klm.com> wrote:
> >
> > > I cannot answer your question, it is probably depending on how the
> > > hardware works on different machines.
> > >
> > > Another question: what is the purpose of this instruction?
> >
> >
> > I think that's what the OP was asking.
> >
> > Is it executed that often that it is worthwhile to make an instruction to
> > > replace 2 instructions (Load+AND, MOVE+AND) or is there another reason?
> > >
> >
> > In fact there is an earlier Load and AND instruction LAN/LANG that can do
> > just the same thing in one instruction, though it also sets the condition
> > code based on the result, and requires full or double word alignment,
> which
> > LZRF/LZRG do not.
> >
> > Paging Dan Greiner...
> >
> > Tony H.
> >
> > --
> > For IBM-MAIN subscribe / signoff / archive access instructions,
> > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
> >
>
>
> --
> zMan -- "I've got a mainframe and I'm not afraid to use it"
>
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-- 
sas

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Re: What's the intent of the "LOAD AND ZERO RIGHTMOST BYTE" instruction?

2019-07-24 Thread zMan
Obviously it's for little-Endian 24-bit addressing mode!

On Wed, Jul 24, 2019 at 3:18 PM Tony Harminc  wrote:

> On Wed, 24 Jul 2019 at 08:35, Vernooij, Kees (ITOP NM) - KLM <
> kees.verno...@klm.com> wrote:
>
> > I cannot answer your question, it is probably depending on how the
> > hardware works on different machines.
> >
> > Another question: what is the purpose of this instruction?
>
>
> I think that's what the OP was asking.
>
> Is it executed that often that it is worthwhile to make an instruction to
> > replace 2 instructions (Load+AND, MOVE+AND) or is there another reason?
> >
>
> In fact there is an earlier Load and AND instruction LAN/LANG that can do
> just the same thing in one instruction, though it also sets the condition
> code based on the result, and requires full or double word alignment, which
> LZRF/LZRG do not.
>
> Paging Dan Greiner...
>
> Tony H.
>
> --
> For IBM-MAIN subscribe / signoff / archive access instructions,
> send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
>


-- 
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Re: What's the intent of the "LOAD AND ZERO RIGHTMOST BYTE" instruction?

2019-07-24 Thread Tony Harminc
On Wed, 24 Jul 2019 at 08:35, Vernooij, Kees (ITOP NM) - KLM <
kees.verno...@klm.com> wrote:

> I cannot answer your question, it is probably depending on how the
> hardware works on different machines.
>
> Another question: what is the purpose of this instruction?


I think that's what the OP was asking.

Is it executed that often that it is worthwhile to make an instruction to
> replace 2 instructions (Load+AND, MOVE+AND) or is there another reason?
>

In fact there is an earlier Load and AND instruction LAN/LANG that can do
just the same thing in one instruction, though it also sets the condition
code based on the result, and requires full or double word alignment, which
LZRF/LZRG do not.

Paging Dan Greiner...

Tony H.

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Re: What's the intent of the "LOAD AND ZERO RIGHTMOST BYTE" instruction?

2019-07-24 Thread Vernooij, Kees (ITOP NM) - KLM
I cannot answer your question, it is probably depending on how the hardware 
works on different machines.

Another question: what is the purpose of this instruction? Is it executed that 
often that it is worthwhile to make an instruction to replace 2 instructions 
(Load+AND, MOVE+AND) or is there another reason?

Kees.


> -Original Message-
> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
> Behalf Of Jerry Callen
> Sent: 24 July, 2019 14:22
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: What's the intent of the "LOAD AND ZERO RIGHTMOST BYTE"
> instruction?
> 
> Is it Friday yet?
> 
> The z13 (I think) added this puppy:
> 
> =
> 
> LOAD AND ZERO RIGHTMOST BYTE
> 
> The second operand, with the rightmost byte set to zero, is placed at the
> first-operand location. For LZRF, the first and second operands are 32
> bits, and for LZRG, the first and second operands are 64 bits.
> 
> The displacement is treated as a 20-bit signed binary integer.
> 
> It is unpredictable whether an access exception is recognized for the
> rightmost byte of the second operand.
> 
> =
> 
> Why?
> 
> -- Jerry
> 
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What's the intent of the "LOAD AND ZERO RIGHTMOST BYTE" instruction?

2019-07-24 Thread Jerry Callen
Is it Friday yet?

The z13 (I think) added this puppy:

=

LOAD AND ZERO RIGHTMOST BYTE

The second operand, with the rightmost byte set to zero, is placed at the 
first-operand location. For LZRF, the first and second operands are 32 bits, 
and for LZRG, the first and second operands are 64 bits.

The displacement is treated as a 20-bit signed binary integer.

It is unpredictable whether an access exception is recognized for the rightmost 
byte of the second operand.

=

Why?

-- Jerry

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