Re: [Intel-gfx] [PATCH 1/9] x86/early-quirks: Extend Intel graphics stolen memory placement to 64bit

[Thomas Gleixner]

On Fri, 24 Nov 2017, Matthew Auld wrote:

> From: Joonas Lahtinen 

Please CC the linux kernel mailinglist on patches related to x86. The
MAINTAINERS file says:

X86 ARCHITECTURE (32-BIT AND 64-BIT)
M:  Thomas Gleixner 
M:  Ingo Molnar 
M:  "H. Peter Anvin" 
M:  x...@kernel.org
L:  linux-ker...@vger.kernel.org<===

See also Documentation/process/submitting-patches.rst, chapter:

5) Select the recipients for your patch

> In preparation for upcoming SKUs, allow more freedom in placement
> of the Intel graphics stolen memory by BIOS to full 64bit range.

This is not really informative for people not familiar with the issue you
want to solve.

Thanks,

tglx
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[Intel-gfx] ✗ Fi.CI.IGT: warning for make stolen resource centric (rev3)

[Patchwork]

== Series Details ==

Series: make stolen resource centric (rev3)
URL   : https://patchwork.freedesktop.org/series/34256/
State : warning

== Summary ==

Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-cur-indfb-draw-render:
skip   -> PASS   (shard-hsw)
Subgroup fbc-rgb101010-draw-pwrite:
skip   -> PASS   (shard-hsw)
Subgroup fbc-suspend:
pass   -> DMESG-WARN (shard-snb) fdo#101623 +1
Test kms_rmfb:
Subgroup close-fd:
skip   -> PASS   (shard-hsw)
Test kms_plane_multiple:
Subgroup atomic-pipe-a-tiling-x:
skip   -> PASS   (shard-hsw)
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_plane:
Subgroup plane-position-covered-pipe-a-planes:
pass   -> SKIP   (shard-hsw)
Subgroup plane-position-hole-pipe-a-planes:
pass   -> SKIP   (shard-hsw)

fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2667 pass:1533 dwarn:1   dfail:0   fail:14  skip:1119 
time:9452s
shard-snbtotal:2649 pass:1288 dwarn:2   dfail:0   fail:15  skip:1343 
time:7933s
Blacklisted hosts:
shard-apltotal:2667 pass:1688 dwarn:3   dfail:0   fail:26  skip:950 
time:13389s
shard-kbltotal:2667 pass:1802 dwarn:2   dfail:0   fail:29  skip:834 
time:10910s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7286/shards.html
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Re: [Intel-gfx] [PATCH 9/9] drm/i915: prefer resource_size_t for everything stolen

[Chris Wilson]

Quoting Matthew Auld (2017-11-24 21:29:30)
> Keeps things consistent now that we make use of struct resource. This
> should keep us covered in case we ever get huge amounts of stolen
> memory.
> 
> v2: bunch of missing conversions (Chris)
> 
> Signed-off-by: Matthew Auld 
> Cc: Joonas Lahtinen 
> Cc: Chris Wilson 
> Cc: Paulo Zanoni 
> ---
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c 
> b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index 2b7af60dfce0..fca56ec9913d 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -76,10 +76,10 @@ void i915_gem_stolen_remove_node(struct drm_i915_private 
> *dev_priv,
> mutex_unlock(_priv->mm.stolen_lock);
>  }
>  
> -static dma_addr_t i915_stolen_to_dma(struct drm_i915_private *dev_priv)
> +static resource_size_t i915_stolen_to_dma(struct drm_i915_private *dev_priv)
>  {
> struct i915_ggtt *ggtt = _priv->ggtt;
> -   dma_addr_t base = intel_graphics_stolen_res.start;
> +   resource_size_t base = intel_graphics_stolen_res.start;
> struct resource *r;
>  
> if (base == 0 || add_overflows(base, ggtt->stolen_size))

It's no longer to_dma anymore. The point of the function was to pretend
phys_addr_t was magically transformed into dma_addr_t.

We should now be at the point where this is just
return intel_graphics_stolen_res;
-Chris
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Re: [Intel-gfx] [PATCH 8/9] drm/i915: make mappable struct resource centric

[Chris Wilson]

Quoting Matthew Auld (2017-11-24 21:29:29)
> Signed-off-by: Matthew Auld 
> Cc: Joonas Lahtinen 
> Cc: Chris Wilson 
> Cc: Paulo Zanoni 
> ---
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h 
> b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index 6eb34fd2c4ba..a91281a55b91 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -368,9 +368,9 @@ i915_vm_has_scratch_64K(struct i915_address_space *vm)
>   */
>  struct i915_ggtt {
> struct i915_address_space base;
> -   struct io_mapping mappable; /* Mapping to our CPU mappable region 
> */
>  
> -   phys_addr_t mappable_base;  /* PA of our GMADR */
> +   struct io_mapping mappable_io;  /* Mapping to our CPU mappable region 
> */
> +   struct resource mappable;   /* GMADR resource */

How about

struct io_mapping iomap;
struct resource gmadr;

?

ggtt->iomap I think is going to be less confusing than ggtt->mappable
going forwards.
-Chris
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Re: [Intel-gfx] [PATCH 7/9] drm/i915: make reserved struct resource centric

[Chris Wilson]

Quoting Matthew Auld (2017-11-24 21:29:28)

Always have a small explanation here.

"Now that we are using struct resource to track the stolen region, it is
more convenient if we track the reserved portion of that region in a
resource as well."

> v2: s/<= end + 1/< end/ (Chris)
> 
> Signed-off-by: Matthew Auld 
> Cc: Joonas Lahtinen 
> Cc: Chris Wilson 
> Cc: Paulo Zanoni 
> ---
> @@ -400,17 +401,16 @@ int i915_gem_init_stolen(struct drm_i915_private 
> *dev_priv)
> reserved_base = stolen_top;
> }
>  
> -   if (reserved_base < dev_priv->dsm.start ||
> -   reserved_base + reserved_size > stolen_top) {
> -   dma_addr_t reserved_top = reserved_base + reserved_size;
> -   DRM_ERROR("Stolen reserved area [%pad - %pad] outside stolen 
> memory [%pad - %pad]\n",
> - _base, _top,
> - _priv->dsm.start, _top);
> +   reserved.start = reserved_base;
> +   reserved.end = reserved_base + reserved_size - 1;

Not just

dev_priv->dsm_reserved = DEFINE_RES_MEM(reserved_base, reserved_size);

?
-Chris
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Re: [Intel-gfx] [PATCH 6/9] drm/i915: make dsm struct resource centric

[Chris Wilson]

Quoting Matthew Auld (2017-11-24 21:29:27)
> v2: check range_overflow when writing to 32b registers (Chris)
> pepper in some comments (Chris)
> 
> Signed-off-by: Matthew Auld 
> Cc: Joonas Lahtinen 
> Cc: Chris Wilson 
> Cc: Paulo Zanoni 
> ---
> @@ -352,11 +352,14 @@ int i915_gem_init_stolen(struct drm_i915_private 
> *dev_priv)
> if (ggtt->stolen_size == 0)
> return 0;
>  
> -   dev_priv->mm.stolen_base = i915_stolen_to_dma(dev_priv);
> -   if (dev_priv->mm.stolen_base == 0)
> +   dev_priv->dsm.start = i915_stolen_to_dma(dev_priv);
> +   if (dev_priv->dsm.start == 0)
> return 0;
>  
> -   stolen_top = dev_priv->mm.stolen_base + ggtt->stolen_size;
> +   dev_priv->dsm.end = dev_priv->dsm.start + ggtt->stolen_size - 1;
> +   dev_priv->dsm.flags = IORESOURCE_MEM;

I'm confused. I thought we exported the stolen resource from x86/quirks
so that we could use it here? I wasn't expecting to keep a bunch of
intermediates.

> +
> +   stolen_top = dev_priv->dsm.end + 1;
> reserved_base = 0;
> reserved_size = 0;
>  

> @@ -460,7 +463,7 @@ i915_pages_create_for_stolen(struct drm_device *dev,
> sg->offset = 0;
> sg->length = size;

For safety sake we should have a GEM_BUG_ON(range_overflow(offset, size,
resource_size(dsm));
-Chris
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Re: [Intel-gfx] [PATCH 5/9] drm/i915: s/mappable_end/mappable_size/

[Chris Wilson]

Quoting Matthew Auld (2017-11-24 21:29:26)
> In a later patch we introduce 'struct resource mappable', which means we
> will have both mappable.end and mappable_end, both meaning different
> things. Therefore to avoid any confusion prefer mappable_size for
> mappable_end, since it is effectively the size of the resource.

Hmm, I still want to keep mappable_end.

Would ggtt->bar work better for the struct resource of the physical
address (or ggtt->gsm/gam whatever the acronym is)?
-Chris
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Re: [Intel-gfx] [PATCH 4/9] drm/i915: nuke the duplicated stolen discovery

[Chris Wilson]

Quoting Matthew Auld (2017-11-24 21:29:25)
> We duplicate the stolen discovery code in early-quirks and in i915,
> however now the stolen region is exported as a resource from
> early-quirks we can nuke the duplication.
> 
> Signed-off-by: Matthew Auld 
> Cc: Joonas Lahtinen 
> Cc: Chris Wilson 
> Cc: Paulo Zanoni 
> ---
>  static dma_addr_t i915_stolen_to_dma(struct drm_i915_private *dev_priv)
>  {
> -   struct pci_dev *pdev = dev_priv->drm.pdev;
> struct i915_ggtt *ggtt = _priv->ggtt;
> +   dma_addr_t base = intel_graphics_stolen_res.start;
> struct resource *r;
> -   dma_addr_t base;

GEM_BUG_ON(overflows_type(intel_graphics_stolen_res.start, base));

Reviewed-by: Chris Wilson 
-Chris
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Re: [Intel-gfx] [PATCH 1/9] x86/early-quirks: Extend Intel graphics stolen memory placement to 64bit

[Chris Wilson]

Quoting Matthew Auld (2017-11-24 21:29:22)
> From: Joonas Lahtinen 
> 
> In preparation for upcoming SKUs, allow more freedom in placement
> of the Intel graphics stolen memory by BIOS to full 64bit range.
> 
> v2: export the stolen region as a resource
> fix u16 << 16 (Chris)
> 
> Signed-off-by: Joonas Lahtinen 
> Signed-off-by: Matthew Auld 
> Cc: Joonas Lahtinen 
> Cc: Ville Syrjälä 
> Cc: Chris Wilson 
> Cc: Paulo Zanoni 
> Cc: Ingo Molnar 
> Cc: H. Peter Anvin 
> Cc: x...@kernel.org
> Reviewed-by: Chris Wilson  #v1
> ---
> -static phys_addr_t __init i865_stolen_base(int num, int slot, int func,
> -  size_t stolen_size)
> +static resource_size_t __init i865_stolen_base(int num, int slot, int func,
> +  resource_size_t stolen_size)
>  {
> u16 toud = 0;
>  
> toud = read_pci_config_16(0, 0, 0, I865_TOUD);
>  
> -   return (phys_addr_t)(toud << 16) + i845_tseg_size();
> +   return (resource_size_t)(toud << 16) + i845_tseg_size();

We need the cast on toud before the <<.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for make stolen resource centric (rev3)

[Patchwork]

== Series Details ==

Series: make stolen resource centric (rev3)
URL   : https://patchwork.freedesktop.org/series/34256/
State : success

== Summary ==

Series 34256v3 make stolen resource centric
https://patchwork.freedesktop.org/api/1.0/series/34256/revisions/3/mbox/

Test gem_exec_reloc:
Subgroup basic-cpu-active:
fail   -> PASS   (fi-gdg-551) fdo#102582 +5
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
pass   -> FAIL   (fi-gdg-551) fdo#102618

fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582
fdo#102618 https://bugs.freedesktop.org/show_bug.cgi?id=102618

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:447s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:446s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:381s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:524s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:277s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:509s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:508s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:491s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:485s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:423s
fi-gdg-551   total:289  pass:177  dwarn:1   dfail:0   fail:2   skip:109 
time:275s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:540s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:424s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:433s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:428s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:468s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:461s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:479s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:536s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:478s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:525s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:571s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:453s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:540s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:568s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:509s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:492s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:463s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:551s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:414s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:607s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:540s
fi-glk-dsi   total:289  pass:169  dwarn:0   dfail:10  fail:3   skip:107 
time:487s

65457f7595c164f6e527aebc8b8301ec6debf117 drm-tip: 2017y-11m-24d-20h-48m-11s UTC 
integration manifest
7c6b288c9a78 drm/i915: prefer resource_size_t for everything stolen
0d4acd627141 drm/i915: make mappable struct resource centric
cc8aed6966f0 drm/i915: make reserved struct resource centric
a62542f61e9e drm/i915: make dsm struct resource centric
8a5e13d15d9b drm/i915: s/mappable_end/mappable_size/
17c5f6868931 drm/i915: nuke the duplicated stolen discovery
2672aec08fe1 x86/early-quirks: reverse the if ladders
432ce20de217 x86/early-quirks: replace the magical increment start values
24dadf1a873a x86/early-quirks: Extend Intel graphics stolen memory placement to 
64bit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7286/
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Re: [Intel-gfx] [PATCH] drm/i915/pmu: Aggregate all RC6 states into one counter

[Chris Wilson]

Quoting Chris Wilson (2017-11-24 20:40:31)
> Quoting Tvrtko Ursulin (2017-11-24 17:13:31)
> > From: Tvrtko Ursulin 
> > 
> > Chris has discovered that RC6, RC6p and RC6pp counters are mutually
> > exclusive, and even that on some SNB SKUs you get RC6p increasing, and on
> > the others RC6.
> > 
> > Furthermore RC6p and RC6pp were only present starting from GEN6 until,
> > GEN7, not including Haswell.
> > 
> > All this combined makes it questionable whether we need to reserve new ABI
> > for these counters. One idea was to just combine them all under the RC6
> > counter to simplify things for userspace. So that is what this patch does.
> > 
> > Signed-off-by: Tvrtko Ursulin 
> > Suggested-by: Chris Wilson 
> Reviewed-by: Chris Wilson 

Oh merde. This patch was still in my tree when I picked up the guc tidy.
Sorry, I accidentally pushed it (without my even r-b).

Humble apologies, I better go pick up the igt catchup as well.
-Chris
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[Intel-gfx] [PATCH 6/9] drm/i915: make dsm struct resource centric

[Matthew Auld]

v2: check range_overflow when writing to 32b registers (Chris)
pepper in some comments (Chris)

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_drv.h| 13 ++---
 drivers/gpu/drm/i915/i915_gem_stolen.c | 19 +++
 drivers/gpu/drm/i915/intel_fbc.c   | 10 --
 drivers/gpu/drm/i915/intel_pm.c| 17 +
 4 files changed, 42 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d575a56fc100..313ab1e98fc7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1536,9 +1536,6 @@ struct i915_gem_mm {
 */
struct pagevec wc_stash;
 
-   /** Usable portion of the GTT for GEM */
-   dma_addr_t stolen_base; /* limited to low memory (32-bit) */
-
/**
 * tmpfs instance used for shmem backed objects
 */
@@ -2252,6 +2249,16 @@ struct drm_i915_private {
 
const struct intel_device_info info;
 
+   /**
+* Data Stolen Memory - aka "i915 stolen memory" gives us the start and
+* end of stolen which we can optionally use to create GEM objects
+* backed by stolen memory. Note that ggtt->stolen_usable_size tells us
+* exactly how much of this we are actually allowed to use, given that
+* some portion of it is in fact reserved for use by hardware functions,
+* while ggtt->stolen_size gives us the total size of the stolen region.
+*/
+   struct resource dsm;
+
void __iomem *regs;
 
struct intel_uncore uncore;
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c 
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index f1b8eeda0058..36c8ec04fd7a 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -185,7 +185,7 @@ static void g4x_get_stolen_reserved(struct drm_i915_private 
*dev_priv,
uint32_t reg_val = I915_READ(IS_GM45(dev_priv) ?
 CTG_STOLEN_RESERVED :
 ELK_STOLEN_RESERVED);
-   dma_addr_t stolen_top = dev_priv->mm.stolen_base + ggtt->stolen_size;
+   dma_addr_t stolen_top = dev_priv->dsm.start + ggtt->stolen_size;
 
if ((reg_val & G4X_STOLEN_RESERVED_ENABLE) == 0) {
*base = 0;
@@ -316,7 +316,7 @@ static void bdw_get_stolen_reserved(struct drm_i915_private 
*dev_priv,
return;
}
 
-   stolen_top = dev_priv->mm.stolen_base + ggtt->stolen_size;
+   stolen_top = dev_priv->dsm.start + ggtt->stolen_size;
 
*base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
 
@@ -352,11 +352,14 @@ int i915_gem_init_stolen(struct drm_i915_private 
*dev_priv)
if (ggtt->stolen_size == 0)
return 0;
 
-   dev_priv->mm.stolen_base = i915_stolen_to_dma(dev_priv);
-   if (dev_priv->mm.stolen_base == 0)
+   dev_priv->dsm.start = i915_stolen_to_dma(dev_priv);
+   if (dev_priv->dsm.start == 0)
return 0;
 
-   stolen_top = dev_priv->mm.stolen_base + ggtt->stolen_size;
+   dev_priv->dsm.end = dev_priv->dsm.start + ggtt->stolen_size - 1;
+   dev_priv->dsm.flags = IORESOURCE_MEM;
+
+   stolen_top = dev_priv->dsm.end + 1;
reserved_base = 0;
reserved_size = 0;
 
@@ -397,12 +400,12 @@ int i915_gem_init_stolen(struct drm_i915_private 
*dev_priv)
reserved_base = stolen_top;
}
 
-   if (reserved_base < dev_priv->mm.stolen_base ||
+   if (reserved_base < dev_priv->dsm.start ||
reserved_base + reserved_size > stolen_top) {
dma_addr_t reserved_top = reserved_base + reserved_size;
DRM_ERROR("Stolen reserved area [%pad - %pad] outside stolen 
memory [%pad - %pad]\n",
  _base, _top,
- _priv->mm.stolen_base, _top);
+ _priv->dsm.start, _top);
return 0;
}
 
@@ -460,7 +463,7 @@ i915_pages_create_for_stolen(struct drm_device *dev,
sg->offset = 0;
sg->length = size;
 
-   sg_dma_address(sg) = (dma_addr_t)dev_priv->mm.stolen_base + offset;
+   sg_dma_address(sg) = (dma_addr_t)dev_priv->dsm.start + offset;
sg_dma_len(sg) = size;
 
return st;
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 4aefc658a5cf..a291bb965e2e 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -615,10 +615,16 @@ static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
 
fbc->compressed_llb = compressed_llb;
 
+   GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start,
+fbc->compressed_fb.start,
+   

[Intel-gfx] [PATCH 7/9] drm/i915: make reserved struct resource centric

[Matthew Auld]

v2: s/<= end + 1/< end/ (Chris)

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_drv.h|  4 
 drivers/gpu/drm/i915/i915_gem_gtt.h|  2 --
 drivers/gpu/drm/i915/i915_gem_stolen.c | 16 
 drivers/gpu/drm/i915/intel_pm.c|  6 ++
 4 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 313ab1e98fc7..e30a8a7812ba 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2258,6 +2258,10 @@ struct drm_i915_private {
 * while ggtt->stolen_size gives us the total size of the stolen region.
 */
struct resource dsm;
+   /**
+* Reseved portion of Data Stolen Memory
+*/
+   struct resource dsm_reserved;
 
void __iomem *regs;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h 
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 922d796983d5..6eb34fd2c4ba 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -383,8 +383,6 @@ struct i915_ggtt {
 */
u32 stolen_size;/* Total size of stolen memory */
u32 stolen_usable_size; /* Total size minus reserved ranges */
-   u32 stolen_reserved_base;
-   u32 stolen_reserved_size;
 
/** "Graphics Stolen Memory" holds the global PTEs */
void __iomem *gsm;
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c 
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 36c8ec04fd7a..2b7af60dfce0 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -333,6 +333,7 @@ static void bdw_get_stolen_reserved(struct drm_i915_private 
*dev_priv,
 int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
 {
struct i915_ggtt *ggtt = _priv->ggtt;
+   struct resource reserved = DEFINE_RES_MEM(0, 0);
dma_addr_t reserved_base, stolen_top;
u32 reserved_total, reserved_size;
u32 stolen_usable_start;
@@ -400,17 +401,16 @@ int i915_gem_init_stolen(struct drm_i915_private 
*dev_priv)
reserved_base = stolen_top;
}
 
-   if (reserved_base < dev_priv->dsm.start ||
-   reserved_base + reserved_size > stolen_top) {
-   dma_addr_t reserved_top = reserved_base + reserved_size;
-   DRM_ERROR("Stolen reserved area [%pad - %pad] outside stolen 
memory [%pad - %pad]\n",
- _base, _top,
- _priv->dsm.start, _top);
+   reserved.start = reserved_base;
+   reserved.end = reserved_base + reserved_size - 1;
+
+   if (!resource_contains(_priv->dsm, )) {
+   DRM_ERROR("Stolen reserved area %pR outside stolen memory 
%pR\n",
+ , _priv->dsm);
return 0;
}
 
-   ggtt->stolen_reserved_base = reserved_base;
-   ggtt->stolen_reserved_size = reserved_size;
+   dev_priv->dsm_reserved = reserved;
 
/* It is possible for the reserved area to end before the end of stolen
 * memory, so just consider the start. */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6a7a28e889bf..504021adcae6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6439,7 +6439,6 @@ static void intel_print_rc6_info(struct drm_i915_private 
*dev_priv, u32 mode)
 
 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
 {
-   struct i915_ggtt *ggtt = _priv->ggtt;
bool enable_rc6 = true;
unsigned long rc6_ctx_base;
u32 rc_ctl;
@@ -6464,9 +6463,8 @@ static bool bxt_check_bios_rc6_setup(struct 
drm_i915_private *dev_priv)
 * for this check.
 */
rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
-   if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
- (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
-   ggtt->stolen_reserved_size))) {
+   if (!((rc6_ctx_base >= dev_priv->dsm_reserved.start) &&
+ (rc6_ctx_base + PAGE_SIZE < dev_priv->dsm_reserved.end))) {
DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
enable_rc6 = false;
}
-- 
2.14.3

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 8/9] drm/i915: make mappable struct resource centric

[Matthew Auld]

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Paulo Zanoni 
---
 drivers/gpu/drm/i915/gvt/gvt.h|  2 +-
 drivers/gpu/drm/i915/i915_drv.c   |  2 +-
 drivers/gpu/drm/i915/i915_gem.c   |  8 
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c   | 28 ---
 drivers/gpu/drm/i915/i915_gem_gtt.h   |  4 ++--
 drivers/gpu/drm/i915/i915_gpu_error.c |  2 +-
 drivers/gpu/drm/i915/i915_vma.c   |  2 +-
 drivers/gpu/drm/i915/intel_display.c  |  2 +-
 drivers/gpu/drm/i915/intel_overlay.c  |  4 ++--
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  4 ++--
 drivers/gpu/drm/i915/selftests/mock_gtt.c |  3 ++-
 12 files changed, 35 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 028d00e61bad..601e5fee8957 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -336,7 +336,7 @@ int intel_gvt_load_firmware(struct intel_gvt *gvt);
 
 /* Aperture/GM space definitions for GVT device */
 #define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_size)
-#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base)
+#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable.start)
 
 #define gvt_ggtt_gm_sz(gvt)  (gvt->dev_priv->ggtt.base.total)
 #define gvt_ggtt_sz(gvt) \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e1bb0c8822aa..be29895a56f6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -728,7 +728,7 @@ static int i915_kick_out_firmware_fb(struct 
drm_i915_private *dev_priv)
if (!ap)
return -ENOMEM;
 
-   ap->ranges[0].base = ggtt->mappable_base;
+   ap->ranges[0].base = ggtt->mappable.start;
ap->ranges[0].size = ggtt->mappable_size;
 
primary =
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 05cc4f2df1bf..48c5a005a4b6 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1106,7 +1106,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
page_base += offset & PAGE_MASK;
}
 
-   if (gtt_user_read(>mappable, page_base, page_offset,
+   if (gtt_user_read(>mappable_io, page_base, page_offset,
  user_data, page_length)) {
ret = -EFAULT;
break;
@@ -1314,7 +1314,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
 * If the object is non-shmem backed, we retry again with the
 * path that handles page fault.
 */
-   if (ggtt_write(>mappable, page_base, page_offset,
+   if (ggtt_write(>mappable_io, page_base, page_offset,
   user_data, page_length)) {
ret = -EFAULT;
break;
@@ -1960,9 +1960,9 @@ int i915_gem_fault(struct vm_fault *vmf)
/* Finally, remap it using the new GTT offset */
ret = remap_io_mapping(area,
   area->vm_start + (vma->ggtt_view.partial.offset 
<< PAGE_SHIFT),
-  (ggtt->mappable_base + vma->node.start) >> 
PAGE_SHIFT,
+  (ggtt->mappable.start + vma->node.start) >> 
PAGE_SHIFT,
   min_t(u64, vma->size, area->vm_end - 
area->vm_start),
-  >mappable);
+  >mappable_io);
if (ret)
goto err_fence;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 8224abbb0f2d..da4db769e1e2 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1012,7 +1012,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj,
offset += page << PAGE_SHIFT;
}
 
-   vaddr = (void __force *)io_mapping_map_atomic_wc(>mappable,
+   vaddr = (void __force *)io_mapping_map_atomic_wc(>mappable_io,
 offset);
cache->page = page;
cache->vaddr = (unsigned long)vaddr;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 94faeaebf0d0..35d91cf07123 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2912,7 +2912,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private 
*dev_priv)
mutex_unlock(_priv->drm.struct_mutex);
 
arch_phys_wc_del(ggtt->mtrr);
-   io_mapping_fini(>mappable);
+   io_mapping_fini(>mappable_io);
 }
 
 static unsigned int 

[Intel-gfx] [PATCH 4/9] drm/i915: nuke the duplicated stolen discovery

[Matthew Auld]

We duplicate the stolen discovery code in early-quirks and in i915,
however now the stolen region is exported as a resource from
early-quirks we can nuke the duplication.

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c|  51 +--
 drivers/gpu/drm/i915/i915_gem_stolen.c | 109 +
 2 files changed, 4 insertions(+), 156 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 41a203e0c160..6b567bab2363 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2949,50 +2949,6 @@ static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
return 0;
 }
 
-static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
-{
-   snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
-   snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
-   return (size_t)snb_gmch_ctl << 25; /* 32 MB units */
-}
-
-static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
-{
-   bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
-   bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
-   return (size_t)bdw_gmch_ctl << 25; /* 32 MB units */
-}
-
-static size_t chv_get_stolen_size(u16 gmch_ctrl)
-{
-   gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
-   gmch_ctrl &= SNB_GMCH_GMS_MASK;
-
-   /*
-* 0x0  to 0x10: 32MB increments starting at 0MB
-* 0x11 to 0x16: 4MB increments starting at 8MB
-* 0x17 to 0x1d: 4MB increments start at 36MB
-*/
-   if (gmch_ctrl < 0x11)
-   return (size_t)gmch_ctrl << 25;
-   else if (gmch_ctrl < 0x17)
-   return (size_t)(gmch_ctrl - 0x11 + 2) << 22;
-   else
-   return (size_t)(gmch_ctrl - 0x17 + 9) << 22;
-}
-
-static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
-{
-   gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
-   gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
-
-   if (gen9_gmch_ctl < 0xf0)
-   return (size_t)gen9_gmch_ctl << 25; /* 32 MB units */
-   else
-   /* 4MB increments starting at 0xf0 for 4MB */
-   return (size_t)(gen9_gmch_ctl - 0xf0 + 1) << 22;
-}
-
 static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
 {
struct drm_i915_private *dev_priv = ggtt->base.i915;
@@ -3343,14 +3299,13 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 
pci_read_config_word(pdev, SNB_GMCH_CTRL, _gmch_ctl);
 
+   ggtt->stolen_size = resource_size(_graphics_stolen_res);
+
if (INTEL_GEN(dev_priv) >= 9) {
-   ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl);
size = gen8_get_total_gtt_size(snb_gmch_ctl);
} else if (IS_CHERRYVIEW(dev_priv)) {
-   ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl);
size = chv_get_total_gtt_size(snb_gmch_ctl);
} else {
-   ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl);
size = gen8_get_total_gtt_size(snb_gmch_ctl);
}
 
@@ -3408,7 +3363,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err);
pci_read_config_word(pdev, SNB_GMCH_CTRL, _gmch_ctl);
 
-   ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
+   ggtt->stolen_size = resource_size(_graphics_stolen_res);
 
size = gen6_get_total_gtt_size(snb_gmch_ctl);
ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c 
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 1877ae9a1d9b..f1b8eeda0058 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -30,9 +30,6 @@
 #include 
 #include "i915_drv.h"
 
-#define KB(x) ((x) * 1024)
-#define MB(x) (KB(x) * 1024)
-
 /*
  * The BIOS typically reserves some of the system's memory for the exclusive
  * use of the integrated graphics. This memory is no longer available for
@@ -81,113 +78,9 @@ void i915_gem_stolen_remove_node(struct drm_i915_private 
*dev_priv,
 
 static dma_addr_t i915_stolen_to_dma(struct drm_i915_private *dev_priv)
 {
-   struct pci_dev *pdev = dev_priv->drm.pdev;
struct i915_ggtt *ggtt = _priv->ggtt;
+   dma_addr_t base = intel_graphics_stolen_res.start;
struct resource *r;
-   dma_addr_t base;
-
-   /* Almost universally we can find the Graphics Base of Stolen Memory
-* at register BSM (0x5c) in the igfx configuration space. On a few
-* (desktop) machines this is also mirrored in the bridge device at
-* different locations, or in the MCHBAR.
-*
-* On 865 we just check the TOUD register.
-*
-* On 830/845/85x the stolen memory base isn't available in any
-* register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
-*
-*/

[Intel-gfx] [PATCH 5/9] drm/i915: s/mappable_end/mappable_size/

[Matthew Auld]

In a later patch we introduce 'struct resource mappable', which means we
will have both mappable.end and mappable_end, both meaning different
things. Therefore to avoid any confusion prefer mappable_size for
mappable_end, since it is effectively the size of the resource.

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Paulo Zanoni 
---
 drivers/char/agp/intel-gtt.c  |  4 ++--
 drivers/gpu/drm/i915/gvt/gvt.h|  2 +-
 drivers/gpu/drm/i915/i915_debugfs.c   |  2 +-
 drivers/gpu/drm/i915/i915_drv.c   |  2 +-
 drivers/gpu/drm/i915/i915_gem.c   |  8 +++
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c   | 30 +--
 drivers/gpu/drm/i915/i915_gem_gtt.h   |  2 +-
 drivers/gpu/drm/i915/i915_vgpu.c  | 12 +--
 drivers/gpu/drm/i915/i915_vma.c   |  4 ++--
 drivers/gpu/drm/i915/intel_fbdev.c|  2 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  2 +-
 drivers/gpu/drm/i915/selftests/i915_vma.c | 22 ++--
 drivers/gpu/drm/i915/selftests/mock_gtt.c |  2 +-
 include/drm/intel-gtt.h   |  2 +-
 15 files changed, 49 insertions(+), 49 deletions(-)

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 9b6b6023193b..2a321ee2943a 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1424,12 +1424,12 @@ EXPORT_SYMBOL(intel_gmch_probe);
 void intel_gtt_get(u64 *gtt_total,
   u32 *stolen_size,
   phys_addr_t *mappable_base,
-  u64 *mappable_end)
+  u64 *mappable_size)
 {
*gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT;
*stolen_size = intel_private.stolen_size;
*mappable_base = intel_private.gma_bus_addr;
-   *mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT;
+   *mappable_size = intel_private.gtt_mappable_entries << PAGE_SHIFT;
 }
 EXPORT_SYMBOL(intel_gtt_get);
 
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 393066726993..028d00e61bad 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -335,7 +335,7 @@ int intel_gvt_load_firmware(struct intel_gvt *gvt);
 #define HOST_FENCE 4
 
 /* Aperture/GM space definitions for GVT device */
-#define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end)
+#define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_size)
 #define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base)
 
 #define gvt_ggtt_gm_sz(gvt)  (gvt->dev_priv->ggtt.base.total)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 28294470ae31..a05e2b92c02c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -523,7 +523,7 @@ static int i915_gem_object_info(struct seq_file *m, void 
*data)
   dpy_count, dpy_size);
 
seq_printf(m, "%llu [%llu] gtt total\n",
-  ggtt->base.total, ggtt->mappable_end);
+  ggtt->base.total, ggtt->mappable_size);
seq_printf(m, "Supported page sizes: %s\n",
   stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes,
buf, sizeof(buf)));
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0793a27e2b95..e1bb0c8822aa 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -729,7 +729,7 @@ static int i915_kick_out_firmware_fb(struct 
drm_i915_private *dev_priv)
return -ENOMEM;
 
ap->ranges[0].base = ggtt->mappable_base;
-   ap->ranges[0].size = ggtt->mappable_end;
+   ap->ranges[0].size = ggtt->mappable_size;
 
primary =
pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e03d6c2554e2..05cc4f2df1bf 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -66,7 +66,7 @@ insert_mappable_node(struct i915_ggtt *ggtt,
memset(node, 0, sizeof(*node));
return drm_mm_insert_node_in_range(>base.mm, node,
   size, 0, I915_COLOR_UNEVICTABLE,
-  0, ggtt->mappable_end,
+  0, ggtt->mappable_size,
   DRM_MM_INSERT_LOW);
 }
 
@@ -4158,7 +4158,7 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
 * the object in and out of the Global GTT and
 * waste a lot of cycles under the mutex.
 */
-   if (obj->base.size > 

[Intel-gfx] [PATCH 9/9] drm/i915: prefer resource_size_t for everything stolen

[Matthew Auld]

Keeps things consistent now that we make use of struct resource. This
should keep us covered in case we ever get huge amounts of stolen
memory.

v2: bunch of missing conversions (Chris)

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Paulo Zanoni 
---
 drivers/char/agp/intel-gtt.c   | 14 +-
 drivers/gpu/drm/i915/i915_debugfs.c|  4 +--
 drivers/gpu/drm/i915/i915_drv.h|  9 +++---
 drivers/gpu/drm/i915/i915_gem_gtt.c| 10 +++
 drivers/gpu/drm/i915/i915_gem_gtt.h|  6 ++--
 drivers/gpu/drm/i915/i915_gem_stolen.c | 51 +-
 drivers/gpu/drm/i915/intel_pm.c| 10 +++
 include/drm/intel-gtt.h|  4 +--
 8 files changed, 55 insertions(+), 53 deletions(-)

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 2a321ee2943a..312c4cc440bc 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -80,7 +80,7 @@ static struct _intel_private {
unsigned int needs_dmar : 1;
phys_addr_t gma_bus_addr;
/*  Size of memory reserved for graphics by the BIOS */
-   unsigned int stolen_size;
+   resource_size_t stolen_size;
/* Total number of gtt entries. */
unsigned int gtt_total_entries;
/* Part of the gtt that is mappable by the cpu, for those chips where
@@ -333,13 +333,13 @@ static void i810_write_entry(dma_addr_t addr, unsigned 
int entry,
writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
 }
 
-static unsigned int intel_gtt_stolen_size(void)
+static resource_size_t intel_gtt_stolen_size(void)
 {
u16 gmch_ctrl;
u8 rdct;
int local = 0;
static const int ddt[4] = { 0, 16, 32, 64 };
-   unsigned int stolen_size = 0;
+   resource_size_t stolen_size = 0;
 
if (INTEL_GTT_GEN == 1)
return 0; /* no stolen mem on i81x */
@@ -417,8 +417,8 @@ static unsigned int intel_gtt_stolen_size(void)
}
 
if (stolen_size > 0) {
-   dev_info(_private.bridge_dev->dev, "detected %dK %s 
memory\n",
-  stolen_size / KB(1), local ? "local" : "stolen");
+   dev_info(_private.bridge_dev->dev, "detected %lluK %s 
memory\n",
+  (u64)stolen_size / KB(1), local ? "local" : "stolen");
} else {
dev_info(_private.bridge_dev->dev,
   "no pre-allocated video memory detected\n");
@@ -1422,9 +1422,9 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev, struct 
pci_dev *gpu_pdev,
 EXPORT_SYMBOL(intel_gmch_probe);
 
 void intel_gtt_get(u64 *gtt_total,
-  u32 *stolen_size,
+  resource_size_t *stolen_size,
   phys_addr_t *mappable_base,
-  u64 *mappable_size)
+  resource_size_t *mappable_size)
 {
*gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT;
*stolen_size = intel_private.stolen_size;
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index a05e2b92c02c..58cb81fe8727 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -522,8 +522,8 @@ static int i915_gem_object_info(struct seq_file *m, void 
*data)
seq_printf(m, "%u display objects (globally pinned), %llu bytes\n",
   dpy_count, dpy_size);
 
-   seq_printf(m, "%llu [%llu] gtt total\n",
-  ggtt->base.total, ggtt->mappable_size);
+   seq_printf(m, "%llu [%pa] gtt total\n",
+  ggtt->base.total, >mappable_size);
seq_printf(m, "Supported page sizes: %s\n",
   stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes,
buf, sizeof(buf)));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e30a8a7812ba..eedffb941f9d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3908,12 +3908,13 @@ void i915_gem_stolen_remove_node(struct 
drm_i915_private *dev_priv,
 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
 void i915_gem_cleanup_stolen(struct drm_device *dev);
 struct drm_i915_gem_object *
-i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
+i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
+ resource_size_t size);
 struct drm_i915_gem_object *
 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private 
*dev_priv,
-  u32 stolen_offset,
-  u32 gtt_offset,
-  u32 size);
+  resource_size_t stolen_offset,
+  resource_size_t 

[Intel-gfx] [PATCH 3/9] x86/early-quirks: reverse the if ladders

[Matthew Auld]

Makes things much easier to follow.

Suggested-by: Ville Syrjälä 
Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Ville Syrjälä 
Cc: Chris Wilson 
Cc: Paulo Zanoni 
Cc: Ingo Molnar 
Cc: H. Peter Anvin 
Cc: x...@kernel.org
---
 arch/x86/kernel/early-quirks.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 3bc1e49d6c41..347951dab769 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -425,12 +425,12 @@ static resource_size_t __init chv_stolen_size(int num, 
int slot, int func)
 * 0x11 to 0x16: 4MB increments starting at 8MB
 * 0x17 to 0x1d: 4MB increments start at 36MB
 */
-   if (gms < 0x11)
-   return gms * MB(32);
-   else if (gms < 0x17)
+   if (gms >= 0x17)
+   return (gms - 0x17) * MB(4) + MB(36);
+   else if (gms >= 0x11)
return (gms - 0x11) * MB(4) + MB(8);
else
-   return (gms - 0x17) * MB(4) + MB(36);
+   return gms * MB(32);
 }
 
 static resource_size_t __init gen9_stolen_size(int num, int slot, int func)
@@ -443,10 +443,10 @@ static resource_size_t __init gen9_stolen_size(int num, 
int slot, int func)
 
/* 0x0  to 0xef: 32MB increments starting at 0MB */
/* 0xf0 to 0xfe: 4MB increments starting at 4MB */
-   if (gms < 0xf0)
-   return gms * MB(32);
-   else
+   if (gms >= 0xf0)
return (gms - 0xf0) * MB(4) + MB(4);
+   else
+   return gms * MB(32);
 }
 
 struct intel_early_ops {
-- 
2.14.3

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[Intel-gfx] [PATCH 1/9] x86/early-quirks: Extend Intel graphics stolen memory placement to 64bit

[Matthew Auld]

From: Joonas Lahtinen 

In preparation for upcoming SKUs, allow more freedom in placement
of the Intel graphics stolen memory by BIOS to full 64bit range.

v2: export the stolen region as a resource
fix u16 << 16 (Chris)

Signed-off-by: Joonas Lahtinen 
Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Ville Syrjälä 
Cc: Chris Wilson 
Cc: Paulo Zanoni 
Cc: Ingo Molnar 
Cc: H. Peter Anvin 
Cc: x...@kernel.org
Reviewed-by: Chris Wilson  #v1
---
 arch/x86/kernel/early-quirks.c | 86 +++---
 include/drm/i915_drm.h |  3 ++
 2 files changed, 50 insertions(+), 39 deletions(-)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 1e82f787c160..3116f579841a 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -243,7 +243,7 @@ static void __init intel_remapping_check(int num, int slot, 
int func)
 #define KB(x)  ((x) * 1024UL)
 #define MB(x)  (KB (KB (x)))
 
-static size_t __init i830_tseg_size(void)
+static resource_size_t __init i830_tseg_size(void)
 {
u8 esmramc = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
 
@@ -256,7 +256,7 @@ static size_t __init i830_tseg_size(void)
return KB(512);
 }
 
-static size_t __init i845_tseg_size(void)
+static resource_size_t __init i845_tseg_size(void)
 {
u8 esmramc = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
u8 tseg_size = esmramc & I845_TSEG_SIZE_MASK;
@@ -273,7 +273,7 @@ static size_t __init i845_tseg_size(void)
return 0;
 }
 
-static size_t __init i85x_tseg_size(void)
+static resource_size_t __init i85x_tseg_size(void)
 {
u8 esmramc = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
 
@@ -283,12 +283,12 @@ static size_t __init i85x_tseg_size(void)
return MB(1);
 }
 
-static size_t __init i830_mem_size(void)
+static resource_size_t __init i830_mem_size(void)
 {
return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32);
 }
 
-static size_t __init i85x_mem_size(void)
+static resource_size_t __init i85x_mem_size(void)
 {
return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32);
 }
@@ -297,36 +297,36 @@ static size_t __init i85x_mem_size(void)
  * On 830/845/85x the stolen memory base isn't available in any
  * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
  */
-static phys_addr_t __init i830_stolen_base(int num, int slot, int func,
-  size_t stolen_size)
+static resource_size_t __init i830_stolen_base(int num, int slot, int func,
+  resource_size_t stolen_size)
 {
-   return (phys_addr_t)i830_mem_size() - i830_tseg_size() - stolen_size;
+   return i830_mem_size() - i830_tseg_size() - stolen_size;
 }
 
-static phys_addr_t __init i845_stolen_base(int num, int slot, int func,
-  size_t stolen_size)
+static resource_size_t __init i845_stolen_base(int num, int slot, int func,
+  resource_size_t stolen_size)
 {
-   return (phys_addr_t)i830_mem_size() - i845_tseg_size() - stolen_size;
+   return i830_mem_size() - i845_tseg_size() - stolen_size;
 }
 
-static phys_addr_t __init i85x_stolen_base(int num, int slot, int func,
-  size_t stolen_size)
+static resource_size_t __init i85x_stolen_base(int num, int slot, int func,
+  resource_size_t stolen_size)
 {
-   return (phys_addr_t)i85x_mem_size() - i85x_tseg_size() - stolen_size;
+   return i85x_mem_size() - i85x_tseg_size() - stolen_size;
 }
 
-static phys_addr_t __init i865_stolen_base(int num, int slot, int func,
-  size_t stolen_size)
+static resource_size_t __init i865_stolen_base(int num, int slot, int func,
+  resource_size_t stolen_size)
 {
u16 toud = 0;
 
toud = read_pci_config_16(0, 0, 0, I865_TOUD);
 
-   return (phys_addr_t)(toud << 16) + i845_tseg_size();
+   return (resource_size_t)(toud << 16) + i845_tseg_size();
 }
 
-static phys_addr_t __init gen3_stolen_base(int num, int slot, int func,
-  size_t stolen_size)
+static resource_size_t __init gen3_stolen_base(int num, int slot, int func,
+  resource_size_t stolen_size)
 {
u32 bsm;
 
@@ -337,10 +337,10 @@ static phys_addr_t __init gen3_stolen_base(int num, int 
slot, int func,
 */
bsm = read_pci_config(num, slot, func, INTEL_BSM);
 
-   return (phys_addr_t)bsm & INTEL_BSM_MASK;
+   return bsm & INTEL_BSM_MASK;
 }
 

[Intel-gfx] [PATCH 2/9] x86/early-quirks: replace the magical increment start values

[Matthew Auld]

Replace the magical +2, +9 etc. with +MB, which is far easier to read.

Suggested-by: Ville Syrjälä 
Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Ville Syrjälä 
Cc: Chris Wilson 
Cc: Paulo Zanoni 
Cc: Ingo Molnar 
Cc: H. Peter Anvin 
Cc: x...@kernel.org
Reviewed-by: Ville Syrjälä 
---
 arch/x86/kernel/early-quirks.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 3116f579841a..3bc1e49d6c41 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -428,9 +428,9 @@ static resource_size_t __init chv_stolen_size(int num, int 
slot, int func)
if (gms < 0x11)
return gms * MB(32);
else if (gms < 0x17)
-   return (gms - 0x11 + 2) * MB(4);
+   return (gms - 0x11) * MB(4) + MB(8);
else
-   return (gms - 0x17 + 9) * MB(4);
+   return (gms - 0x17) * MB(4) + MB(36);
 }
 
 static resource_size_t __init gen9_stolen_size(int num, int slot, int func)
@@ -446,7 +446,7 @@ static resource_size_t __init gen9_stolen_size(int num, int 
slot, int func)
if (gms < 0xf0)
return gms * MB(32);
else
-   return (gms - 0xf0 + 1) * MB(4);
+   return (gms - 0xf0) * MB(4) + MB(4);
 }
 
 struct intel_early_ops {
-- 
2.14.3

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[Intel-gfx] [PATCH 0/9] make stolen resource centric

[Matthew Auld]

Continuation of Paulo' stolen series[1], addressing the feedback from Joonas and
Chris.

[1] https://patchwork.freedesktop.org/series/30923/

Joonas Lahtinen (1):
  x86/early-quirks: Extend Intel graphics stolen memory placement to
64bit

Matthew Auld (8):
  x86/early-quirks: replace the magical increment start values
  x86/early-quirks: reverse the if ladders
  drm/i915: nuke the duplicated stolen discovery
  drm/i915: s/mappable_end/mappable_size/
  drm/i915: make dsm struct resource centric
  drm/i915: make reserved struct resource centric
  drm/i915: make mappable struct resource centric
  drm/i915: prefer resource_size_t for everything stolen

 arch/x86/kernel/early-quirks.c|  92 +++--
 drivers/char/agp/intel-gtt.c  |  16 +--
 drivers/gpu/drm/i915/gvt/gvt.h|   4 +-
 drivers/gpu/drm/i915/i915_debugfs.c   |   4 +-
 drivers/gpu/drm/i915/i915_drv.c   |   4 +-
 drivers/gpu/drm/i915/i915_drv.h   |  26 +++-
 drivers/gpu/drm/i915/i915_gem.c   |  16 +--
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|   4 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c   | 103 +-
 drivers/gpu/drm/i915/i915_gem_gtt.h   |  12 +-
 drivers/gpu/drm/i915/i915_gem_stolen.c| 187 ++
 drivers/gpu/drm/i915/i915_gpu_error.c |   2 +-
 drivers/gpu/drm/i915/i915_vgpu.c  |  12 +-
 drivers/gpu/drm/i915/i915_vma.c   |   6 +-
 drivers/gpu/drm/i915/intel_display.c  |   2 +-
 drivers/gpu/drm/i915/intel_fbc.c  |  10 +-
 drivers/gpu/drm/i915/intel_fbdev.c|   2 +-
 drivers/gpu/drm/i915/intel_overlay.c  |   4 +-
 drivers/gpu/drm/i915/intel_pm.c   |  33 +++--
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |   6 +-
 drivers/gpu/drm/i915/selftests/i915_vma.c |  22 +--
 drivers/gpu/drm/i915/selftests/mock_gtt.c |   5 +-
 include/drm/i915_drm.h|   3 +
 include/drm/intel-gtt.h   |   4 +-
 24 files changed, 236 insertions(+), 343 deletions(-)

-- 
2.14.3

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Re: [Intel-gfx] [PATCH] drm/i915/guc: Use consistent name for scratch register count

[Chris Wilson]

Quoting Michal Wajdeczko (2017-11-24 17:02:39)
> We should be consistent on naming of similar definitions.
> 
> Signed-off-by: Michal Wajdeczko 
> Cc: Chris Wilson 
> Cc: Joonas Lahtinen 
> Cc: Sagar Arun Kamble 

Indeed, SOFT_SCRATCH_COUNT being the nearby example
Reviewed-by: Chris Wilson 
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/pmu: Aggregate all RC6 states into one counter

[Chris Wilson]

Quoting Tvrtko Ursulin (2017-11-24 17:13:31)
> From: Tvrtko Ursulin 
> 
> Chris has discovered that RC6, RC6p and RC6pp counters are mutually
> exclusive, and even that on some SNB SKUs you get RC6p increasing, and on
> the others RC6.
> 
> Furthermore RC6p and RC6pp were only present starting from GEN6 until,
> GEN7, not including Haswell.
> 
> All this combined makes it questionable whether we need to reserve new ABI
> for these counters. One idea was to just combine them all under the RC6
> counter to simplify things for userspace. So that is what this patch does.
> 
> Signed-off-by: Tvrtko Ursulin 
> Suggested-by: Chris Wilson 
Reviewed-by: Chris Wilson 
-Chris
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Re: [Intel-gfx] [PATCH i-g-t] intel/pmu: Catch-up with i915 RC6 aggregation changes

[Chris Wilson]

Quoting Tvrtko Ursulin (2017-11-24 17:16:18)
> From: Tvrtko Ursulin 
> 
> Since i915 PMU is removing separate RC6 counters and now aggregates all
> under a single one, catch up the test and intel-gpu-overlay with those
> changes.
> 
> Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Chris Wilson 
-Chris
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[Intel-gfx] ✗ Fi.CI.IGT: warning for intel/pmu: Catch-up with i915 RC6 aggregation changes

[Patchwork]

== Series Details ==

Series: intel/pmu: Catch-up with i915 RC6 aggregation changes
URL   : https://patchwork.freedesktop.org/series/34371/
State : warning

== Summary ==

Test kms_frontbuffer_tracking:
Subgroup fbc-1p-pri-indfb-multidraw:
fail   -> SKIP   (shard-snb) fdo#103167
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
pass   -> FAIL   (shard-snb) fdo#101623 +1
Test kms_draw_crc:
Subgroup draw-method-xrgb2101010-pwrite-xtiled:
pass   -> SKIP   (shard-snb)
Test drv_module_reload:
Subgroup basic-reload:
pass   -> DMESG-WARN (shard-hsw) fdo#102707
Test gem_softpin:
Subgroup noreloc-s3:
pass   -> DMESG-WARN (shard-snb) fdo#102365
Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-c-planes:
skip   -> PASS   (shard-hsw) fdo#103375

fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375

shard-hswtotal:2662 pass:1532 dwarn:2   dfail:0   fail:10  skip:1118 
time:9469s
shard-snbtotal:2662 pass:1303 dwarn:2   dfail:0   fail:13  skip:1344 
time:8081s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_550/shards.html
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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/guc: Use consistent name for scratch register count

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Use consistent name for scratch register count
URL   : https://patchwork.freedesktop.org/series/34369/
State : warning

== Summary ==

Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
pass   -> FAIL   (shard-snb) fdo#101623 +1
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_chv_cursor_fail:
Subgroup pipe-c-256x256-top-edge:
pass   -> SKIP   (shard-hsw)

fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2667 pass:1534 dwarn:1   dfail:0   fail:10  skip:1122 
time:9489s
shard-snbtotal:2667 pass:1311 dwarn:1   dfail:0   fail:13  skip:1342 
time:8062s
Blacklisted hosts:
shard-apltotal:2667 pass:1689 dwarn:2   dfail:0   fail:22  skip:954 
time:13340s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7284/shards.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for make stolen resource centric (rev2)

[Patchwork]

== Series Details ==

Series: make stolen resource centric (rev2)
URL   : https://patchwork.freedesktop.org/series/34256/
State : failure

== Summary ==

Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
pass   -> FAIL   (shard-snb) fdo#101623 +1
Subgroup fbc-1p-primscrn-pri-shrfb-draw-render:
pass   -> FAIL   (shard-snb)
Subgroup fbc-rgb101010-draw-mmap-gtt:
pass   -> SKIP   (shard-hsw)
Subgroup fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
pass   -> SKIP   (shard-hsw) fdo#103167
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_cursor_legacy:
Subgroup cursora-vs-flipa-toggle:
pass   -> SKIP   (shard-hsw)
Test gem_busy:
Subgroup close-race:
pass   -> FAIL   (shard-snb) fdo#103829
Test drv_selftest:
Subgroup mock_sanitycheck:
pass   -> DMESG-WARN (shard-snb) fdo#103717

fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#103829 https://bugs.freedesktop.org/show_bug.cgi?id=103829
fdo#103717 https://bugs.freedesktop.org/show_bug.cgi?id=103717

shard-hswtotal:2667 pass:1532 dwarn:1   dfail:0   fail:10  skip:1124 
time:9415s
shard-snbtotal:2667 pass:1308 dwarn:2   dfail:0   fail:15  skip:1342 
time:8023s
Blacklisted hosts:
shard-kbltotal:2667 pass:1804 dwarn:2   dfail:0   fail:25  skip:836 
time:10861s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7283/shards.html
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Re: [Intel-gfx] [PATCH 8/8] drm/i915: prefer resource_size_t for everything stolen

[Chris Wilson]

Quoting Matthew Auld (2017-11-24 17:56:34)
> On 24 November 2017 at 16:54, Chris Wilson  wrote:
> > Quoting Matthew Auld (2017-11-24 16:42:57)
> >> Keeps things consistent now that we make use of struct resource. This
> >> should keep us covered in case we ever get huge amounts of stolen
> >> memory.
> >>
> >> v2: bunch of missing conversions (Chris)
> >>
> >> Signed-off-by: Matthew Auld 
> >> Cc: Joonas Lahtinen 
> >> Cc: Chris Wilson 
> >> Cc: Paulo Zanoni 
> >> ---
> >> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> >> b/drivers/gpu/drm/i915/i915_debugfs.c
> >> index a05e2b92c02c..248d18a255d8 100644
> >> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> >> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> >> @@ -523,7 +523,7 @@ static int i915_gem_object_info(struct seq_file *m, 
> >> void *data)
> >>dpy_count, dpy_size);
> >>
> >> seq_printf(m, "%llu [%llu] gtt total\n",
> >> -  ggtt->base.total, ggtt->mappable_size);
> >> +  ggtt->base.total, (u64)ggtt->mappable_size);
> >
> > resource_size_t uses %pa (same as phys_addr_t), which you used below.
> > Did it not work with seq_printf?
> 
> It does work, I just didn't fancy having a mix of decimal-integers
> with hexadecimal-integers when printing. Or don't we care?

Don't care that much, go hex.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/pmu: Aggregate all RC6 states into one counter

[Chris Wilson]

Quoting Chris Wilson (2017-11-24 18:19:03)
> Quoting Tvrtko Ursulin (2017-11-24 17:13:31)
> > From: Tvrtko Ursulin 
> > 
> > Chris has discovered that RC6, RC6p and RC6pp counters are mutually
> > exclusive, and even that on some SNB SKUs you get RC6p increasing, and on
> > the others RC6.
> > 
> > Furthermore RC6p and RC6pp were only present starting from GEN6 until,
> > GEN7, not including Haswell.
> > 
> > All this combined makes it questionable whether we need to reserve new ABI
> > for these counters. One idea was to just combine them all under the RC6
> > counter to simplify things for userspace. So that is what this patch does.
> > 
> > Signed-off-by: Tvrtko Ursulin 
> > Suggested-by: Chris Wilson 
> 
> (Wrong mail!)
> 
> First run failed: (perf_pmu:1928) CRITICAL: 'idle - prev' != 'slept'
> (1884715520.00 not within 5.00% tolerance of 2000133450.00)

Subsequent runs, ok. Shrug.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for intel/pmu: Catch-up with i915 RC6 aggregation changes

[Patchwork]

== Series Details ==

Series: intel/pmu: Catch-up with i915 RC6 aggregation changes
URL   : https://patchwork.freedesktop.org/series/34371/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
c6577473df7117b7a6e030605df1e28cd0e55708 lib/igt_core: Move write_stderr out of 
LIBUNWIND ifdef

with latest DRM-Tip kernel build CI_DRM_3385
c2ee9de5c13c drm-tip: 2017y-11m-24d-17h-10m-43s UTC integration manifest

Testlist changes:
-igt@perf_pmu@other-init-5
-igt@perf_pmu@other-init-6
-igt@perf_pmu@other-read-5
-igt@perf_pmu@other-read-6
-igt@perf_pmu@rc6p

Test gem_exec_reloc:
Subgroup basic-cpu-active:
pass   -> FAIL   (fi-gdg-551) fdo#102582 +5
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
pass   -> FAIL   (fi-gdg-551) fdo#102618

fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582
fdo#102618 https://bugs.freedesktop.org/show_bug.cgi?id=102618

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:444s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:388s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:539s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:278s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:511s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:503s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:493s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:490s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:427s
fi-gdg-551   total:289  pass:170  dwarn:1   dfail:0   fail:9   skip:109 
time:277s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:538s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:427s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:434s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:431s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:494s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:463s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:486s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:532s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:480s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:530s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:455s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:539s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:568s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:508s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:499s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:458s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:556s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:418s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:595s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:558s
fi-glk-dsi   total:91   pass:46   dwarn:0   dfail:1   fail:2   skip:41 

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_550/
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] igt: Remove Android support

[Patchwork]

== Series Details ==

Series: series starting with [1/2] igt: Remove Android support
URL   : https://patchwork.freedesktop.org/series/34365/
State : success

== Summary ==

Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
fail   -> PASS   (shard-snb) fdo#101623 +2
Test kms_flip:
Subgroup dpms-vs-vblank-race-interruptible:
pass   -> FAIL   (shard-hsw) fdo#103060
Test drv_module_reload:
Subgroup basic-reload:
pass   -> DMESG-WARN (shard-hsw) fdo#102707
Test gem_busy:
Subgroup close-race:
fail   -> PASS   (shard-snb) fdo#103829

fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707
fdo#103829 https://bugs.freedesktop.org/show_bug.cgi?id=103829

shard-hswtotal:2667 pass:1533 dwarn:2   dfail:0   fail:11  skip:1121 
time:9508s
shard-snbtotal:2667 pass:1312 dwarn:1   dfail:0   fail:12  skip:1342 
time:8125s
Blacklisted hosts:
shard-apltotal:2667 pass:1686 dwarn:1   dfail:0   fail:25  skip:954 
time:13703s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_549/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915/pmu: Aggregate all RC6 states into one counter

[Chris Wilson]

Quoting Tvrtko Ursulin (2017-11-24 17:13:31)
> From: Tvrtko Ursulin 
> 
> Chris has discovered that RC6, RC6p and RC6pp counters are mutually
> exclusive, and even that on some SNB SKUs you get RC6p increasing, and on
> the others RC6.
> 
> Furthermore RC6p and RC6pp were only present starting from GEN6 until,
> GEN7, not including Haswell.
> 
> All this combined makes it questionable whether we need to reserve new ABI
> for these counters. One idea was to just combine them all under the RC6
> counter to simplify things for userspace. So that is what this patch does.
> 
> Signed-off-by: Tvrtko Ursulin 
> Suggested-by: Chris Wilson 

(Wrong mail!)

First run failed: (perf_pmu:1928) CRITICAL: 'idle - prev' != 'slept'
(1884715520.00 not within 5.00% tolerance of 2000133450.00)
-Chris
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Re: [Intel-gfx] [PATCH i-g-t] intel/pmu: Catch-up with i915 RC6 aggregation changes

[Chris Wilson]

Quoting Tvrtko Ursulin (2017-11-24 17:16:18)
> From: Tvrtko Ursulin 
> 
> Since i915 PMU is removing separate RC6 counters and now aggregates all
> under a single one, catch up the test and intel-gpu-overlay with those
> changes.

First run failed
(perf_pmu:1928) CRITICAL: 'idle - prev' != 'slept' (1884715520.00
not within 5.00% tolerance of 2000133450.00)

Weird. Be back later,
-Chris
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/pmu: Aggregate all RC6 states into one counter

[Patchwork]

== Series Details ==

Series: drm/i915/pmu: Aggregate all RC6 states into one counter
URL   : https://patchwork.freedesktop.org/series/34370/
State : failure

== Summary ==

Series 34370v1 drm/i915/pmu: Aggregate all RC6 states into one counter
https://patchwork.freedesktop.org/api/1.0/series/34370/revisions/1/mbox/

Test gem_exec_reloc:
Subgroup basic-cpu-read-active:
fail   -> PASS   (fi-gdg-551) fdo#102582 +2
Test drv_module_reload:
Subgroup basic-reload-inject:
pass   -> INCOMPLETE (fi-bwr-2160)

fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:441s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:448s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:384s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:526s
fi-bwr-2160  total:288  pass:182  dwarn:0   dfail:0   fail:0   skip:105
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:510s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:512s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:487s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:483s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:431s
fi-gdg-551   total:289  pass:176  dwarn:1   dfail:0   fail:3   skip:109 
time:265s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:539s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:423s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:432s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:431s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:473s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:454s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:470s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:530s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:469s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:534s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:449s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:542s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:568s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:508s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:494s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:454s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:553s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:415s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:594s
fi-cnl-y total:220  pass:199  dwarn:0   dfail:0   fail:0   skip:20 
fi-glk-dsi   total:289  pass:258  dwarn:0   dfail:0   fail:1   skip:30  
time:491s
fi-pnv-d510 failed to collect. IGT log at Patchwork_7285/fi-pnv-d510/igt.log

c2ee9de5c13c27c716dd45b78b9f24826cdcd118 drm-tip: 2017y-11m-24d-17h-10m-43s UTC 
integration manifest
7a12baf3824a drm/i915/pmu: Aggregate all RC6 states into one counter

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7285/
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Re: [Intel-gfx] [PATCH 8/8] drm/i915: prefer resource_size_t for everything stolen

[Matthew Auld]

On 24 November 2017 at 16:54, Chris Wilson  wrote:
> Quoting Matthew Auld (2017-11-24 16:42:57)
>> Keeps things consistent now that we make use of struct resource. This
>> should keep us covered in case we ever get huge amounts of stolen
>> memory.
>>
>> v2: bunch of missing conversions (Chris)
>>
>> Signed-off-by: Matthew Auld 
>> Cc: Joonas Lahtinen 
>> Cc: Chris Wilson 
>> Cc: Paulo Zanoni 
>> ---
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
>> b/drivers/gpu/drm/i915/i915_debugfs.c
>> index a05e2b92c02c..248d18a255d8 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -523,7 +523,7 @@ static int i915_gem_object_info(struct seq_file *m, void 
>> *data)
>>dpy_count, dpy_size);
>>
>> seq_printf(m, "%llu [%llu] gtt total\n",
>> -  ggtt->base.total, ggtt->mappable_size);
>> +  ggtt->base.total, (u64)ggtt->mappable_size);
>
> resource_size_t uses %pa (same as phys_addr_t), which you used below.
> Did it not work with seq_printf?

It does work, I just didn't fancy having a mix of decimal-integers
with hexadecimal-integers when printing. Or don't we care?
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Expose the busyspin durations for i915_wait_request

[Patchwork]

== Series Details ==

Series: drm/i915: Expose the busyspin durations for i915_wait_request
URL   : https://patchwork.freedesktop.org/series/34364/
State : success

== Summary ==

Test gem_busy:
Subgroup close-race:
fail   -> PASS   (shard-snb) fdo#103829
Test kms_frontbuffer_tracking:
Subgroup fbc-rgb565-draw-blt:
fail   -> PASS   (shard-snb) fdo#101623 +1
Test kms_flip:
Subgroup plain-flip-ts-check-interruptible:
pass   -> FAIL   (shard-hsw) fdo#100368

fdo#103829 https://bugs.freedesktop.org/show_bug.cgi?id=103829
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368

shard-hswtotal:2592 pass:1493 dwarn:1   dfail:0   fail:10  skip:1088 
time:9239s
shard-snbtotal:2667 pass:1311 dwarn:1   dfail:0   fail:13  skip:1342 
time:8078s
Blacklisted hosts:
shard-apltotal:2645 pass:1666 dwarn:1   dfail:0   fail:23  skip:954 
time:13183s
shard-kbltotal:2667 pass:1802 dwarn:1   dfail:0   fail:26  skip:838 
time:10767s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7282/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Use consistent name for scratch register count

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Use consistent name for scratch register count
URL   : https://patchwork.freedesktop.org/series/34369/
State : success

== Summary ==

Series 34369v1 drm/i915/guc: Use consistent name for scratch register count
https://patchwork.freedesktop.org/api/1.0/series/34369/revisions/1/mbox/

Test kms_busy:
Subgroup basic-flip-a:
pass   -> FAIL   (fi-gdg-551) fdo#102654

fdo#102654 https://bugs.freedesktop.org/show_bug.cgi?id=102654

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:445s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:453s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:380s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:543s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:276s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:502s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:509s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:498s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:498s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:425s
fi-gdg-551   total:289  pass:177  dwarn:1   dfail:0   fail:2   skip:109 
time:266s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:538s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:429s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:438s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:425s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:484s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:461s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:483s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:531s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:474s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:533s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:576s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:456s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:537s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:567s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:516s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:500s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:463s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:566s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:423s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:608s
fi-glk-dsi   total:289  pass:169  dwarn:0   dfail:10  fail:2   skip:108 
time:438s
fi-cnl-y failed to connect after reboot

2cc63d7f56b7d8c9287a431773b3fec01b53e5cb drm-tip: 2017y-11m-24d-16h-04m-11s UTC 
integration manifest
a3469c641b6c drm/i915/guc: Use consistent name for scratch register count

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7284/
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[Intel-gfx] [PATCH i-g-t] intel/pmu: Catch-up with i915 RC6 aggregation changes

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Since i915 PMU is removing separate RC6 counters and now aggregates all
under a single one, catch up the test and intel-gpu-overlay with those
changes.

Signed-off-by: Tvrtko Ursulin 
---
 lib/igt_perf.h   |  4 +---
 overlay/rc6.c| 45 +++--
 tests/perf_pmu.c | 53 -
 3 files changed, 8 insertions(+), 94 deletions(-)

diff --git a/lib/igt_perf.h b/lib/igt_perf.h
index 5428feb0c746..7b66fc582b88 100644
--- a/lib/igt_perf.h
+++ b/lib/igt_perf.h
@@ -64,10 +64,8 @@ enum drm_i915_pmu_engine_sample {
 #define I915_PMU_REQUESTED_FREQUENCY   __I915_PMU_OTHER(1)
 #define I915_PMU_INTERRUPTS__I915_PMU_OTHER(2)
 #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
-#define I915_PMU_RC6p_RESIDENCY__I915_PMU_OTHER(4)
-#define I915_PMU_RC6pp_RESIDENCY   __I915_PMU_OTHER(5)
 
-#define I915_PMU_LAST I915_PMU_RC6pp_RESIDENCY
+#define I915_PMU_LAST I915_PMU_RC6_RESIDENCY
 
 static inline int
 perf_event_open(struct perf_event_attr *attr,
diff --git a/overlay/rc6.c b/overlay/rc6.c
index 8977f0993095..b5286f0cf8c6 100644
--- a/overlay/rc6.c
+++ b/overlay/rc6.c
@@ -35,34 +35,12 @@
 
 #include "rc6.h"
 
-#define RC6(1<<0)
-#define RC6p   (1<<1)
-#define RC6pp  (1<<2)
-
-static int perf_open(unsigned *flags)
-{
-   int fd;
-
-   fd = perf_i915_open_group(I915_PMU_RC6_RESIDENCY, -1);
-   if (fd < 0)
-   return -1;
-
-   *flags |= RC6;
-   if (perf_i915_open_group(I915_PMU_RC6p_RESIDENCY, fd) >= 0)
-   *flags |= RC6p;
-
-   if (perf_i915_open_group(I915_PMU_RC6pp_RESIDENCY, fd) >= 0)
-   *flags |= RC6pp;
-
-   return fd;
-}
-
 int rc6_init(struct rc6 *rc6)
 {
memset(rc6, 0, sizeof(*rc6));
 
-   rc6->fd = perf_open(>flags);
-   if (rc6->fd == -1) {
+   rc6->fd = perf_i915_open(I915_PMU_RC6_RESIDENCY);
+   if (rc6->fd < 0) {
struct stat st;
if (stat("/sys/class/drm/card0/power", ) < 0)
return rc6->error = errno;
@@ -110,7 +88,7 @@ int rc6_update(struct rc6 *rc6)
if (rc6->error)
return rc6->error;
 
-   if (rc6->fd == -1) {
+   if (rc6->fd < 0) {
struct stat st;
 
if (stat("/sys/class/drm/card0/power/rc6_residency_ms", ) < 
0)
@@ -121,22 +99,13 @@ int rc6_update(struct rc6 *rc6)
s->rc6pp_residency = 
file_to_u64("/sys/class/drm/card0/power/rc6pp_residency_ms");
s->timestamp = clock_ms_to_u64();
} else {
-   uint64_t data[5];
-   int len;
+   uint64_t data[2];
 
-   len = read(rc6->fd, data, sizeof(data));
-   if (len < 0)
+   if (read(rc6->fd, data, sizeof(data)) < sizeof(data))
return rc6->error = errno;
 
-   s->timestamp = data[1] / (1000*1000);
-
-   len = 2;
-   if (rc6->flags & RC6)
-   s->rc6_residency = data[len++] / 1e6;
-   if (rc6->flags & RC6p)
-   s->rc6p_residency = data[len++] / 1e6;
-   if (rc6->flags & RC6pp)
-   s->rc6pp_residency = data[len++] / 1e6;
+   s->timestamp = data[1] / 1e6;
+   s->rc6_residency = data[0] / 1e6;
}
 
if (rc6->count == 1)
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index a19fd2ac45a2..8d58ecea3528 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -1019,53 +1019,6 @@ test_rc6(int gem_fd)
assert_within_epsilon(busy - prev, 0.0, tolerance);
 }
 
-static void
-test_rc6p(int gem_fd)
-{
-   int64_t duration_ns = 2e9;
-   unsigned int num_pmu = 1;
-   uint64_t idle[3], busy[3], prev[3];
-   unsigned int slept, i;
-   int fd, ret, fw;
-
-   fd = open_group(I915_PMU_RC6_RESIDENCY, -1);
-   ret = perf_i915_open_group(I915_PMU_RC6p_RESIDENCY, fd);
-   if (ret > 0) {
-   num_pmu++;
-   ret = perf_i915_open_group(I915_PMU_RC6pp_RESIDENCY, fd);
-   if (ret > 0)
-   num_pmu++;
-   }
-
-   igt_require(num_pmu == 3);
-
-   gem_quiescent_gpu(gem_fd);
-   usleep(100e3); /* wait for the rc6 cycle counter to kick in */
-
-   /* Go idle and check full RC6. */
-   pmu_read_multi(fd, num_pmu, prev);
-   slept = measured_usleep(duration_ns / 1000);
-   pmu_read_multi(fd, num_pmu, idle);
-
-   for (i = 0; i < num_pmu; i++)
-   assert_within_epsilon(idle[i] - prev[i], slept, tolerance);
-
-   /* Wake up device and check no RC6. */
-   fw = igt_open_forcewake_handle(gem_fd);
-   igt_assert(fw >= 0);
-   usleep(1e3); /* wait for the rc6 cycle counter to stop ticking */
-
-   pmu_read_multi(fd, num_pmu, prev);
-   usleep(duration_ns / 1000);
- 

[Intel-gfx] [PATCH] drm/i915/pmu: Aggregate all RC6 states into one counter

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Chris has discovered that RC6, RC6p and RC6pp counters are mutually
exclusive, and even that on some SNB SKUs you get RC6p increasing, and on
the others RC6.

Furthermore RC6p and RC6pp were only present starting from GEN6 until,
GEN7, not including Haswell.

All this combined makes it questionable whether we need to reserve new ABI
for these counters. One idea was to just combine them all under the RC6
counter to simplify things for userspace. So that is what this patch does.

Signed-off-by: Tvrtko Ursulin 
Suggested-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_pmu.c | 23 ++-
 include/uapi/drm/i915_drm.h |  6 +-
 2 files changed, 7 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 39310cf13c3a..3357b690ce90 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -359,11 +359,6 @@ static int i915_pmu_event_init(struct perf_event *event)
if (!HAS_RC6(i915))
ret = -ENODEV;
break;
-   case I915_PMU_RC6p_RESIDENCY:
-   case I915_PMU_RC6pp_RESIDENCY:
-   if (!HAS_RC6p(i915))
-   ret = -ENODEV;
-   break;
default:
ret = -ENOENT;
break;
@@ -421,16 +416,12 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
 IS_VALLEYVIEW(i915) ?
 VLV_GT_RENDER_RC6 :
 GEN6_GT_GFX_RC6);
-   intel_runtime_pm_put(i915);
-   break;
-   case I915_PMU_RC6p_RESIDENCY:
-   intel_runtime_pm_get(i915);
-   val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
-   intel_runtime_pm_put(i915);
-   break;
-   case I915_PMU_RC6pp_RESIDENCY:
-   intel_runtime_pm_get(i915);
-   val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
+   if (HAS_RC6p(i915)) {
+   val += intel_rc6_residency_ns(i915,
+ GEN6_GT_GFX_RC6p);
+   val += intel_rc6_residency_ns(i915,
+ 
GEN6_GT_GFX_RC6pp);
+   }
intel_runtime_pm_put(i915);
break;
}
@@ -708,8 +699,6 @@ static struct attribute *i915_pmu_events_attrs[] = {
I915_EVENT_ATTR(interrupts, I915_PMU_INTERRUPTS),
 
I915_EVENT(rc6-residency,   I915_PMU_RC6_RESIDENCY,   "ns"),
-   I915_EVENT(rc6p-residency,  I915_PMU_RC6p_RESIDENCY,  "ns"),
-   I915_EVENT(rc6pp-residency, I915_PMU_RC6pp_RESIDENCY, "ns"),
 
NULL,
 };
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 239e8633edc9..536ee4febd74 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -137,14 +137,10 @@ enum drm_i915_pmu_engine_sample {
 
 #define I915_PMU_ACTUAL_FREQUENCY  __I915_PMU_OTHER(0)
 #define I915_PMU_REQUESTED_FREQUENCY   __I915_PMU_OTHER(1)
-
 #define I915_PMU_INTERRUPTS__I915_PMU_OTHER(2)
-
 #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
-#define I915_PMU_RC6p_RESIDENCY__I915_PMU_OTHER(4)
-#define I915_PMU_RC6pp_RESIDENCY   __I915_PMU_OTHER(5)
 
-#define I915_PMU_LAST I915_PMU_RC6pp_RESIDENCY
+#define I915_PMU_LAST I915_PMU_RC6_RESIDENCY
 
 /* Each region is a minimum of 16k, and there are at most 255 of them.
  */
-- 
2.14.1

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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/guc: Advance over port[0] if set and not preempting

[Chris Wilson]

Quoting Patchwork (2017-11-24 17:02:54)
> == Series Details ==
> 
> Series: series starting with [1/2] drm/i915/guc: Advance over port[0] if set 
> and not preempting
> URL   : https://patchwork.freedesktop.org/series/34361/
> State : success
> 
> == Summary ==
> 
> Test kms_frontbuffer_tracking:
> Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
> fail   -> PASS   (shard-snb) fdo#101623 +1
> Test gem_busy:
> Subgroup close-race:
> fail   -> PASS   (shard-snb) fdo#103829
> 
> fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
> fdo#103829 https://bugs.freedesktop.org/show_bug.cgi?id=103829
> 
> shard-hswtotal:2667 pass:1535 dwarn:1   dfail:0   fail:10  skip:1121 
> time:9535s
> shard-snbtotal:2667 pass:1311 dwarn:1   dfail:0   fail:13  skip:1342 
> time:8031s
> Blacklisted hosts:
> shard-apltotal:2667 pass:1660 dwarn:6   dfail:3   fail:43  skip:955 
> time:12343s
> 
> == Logs ==
> 
> For more details see: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7281/shards.html

All looks clear (if you squint over the pmu sore spot), pushed along
with the guc tidy.

Thanks for spotting the mistake and review,
-Chris
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Re: [Intel-gfx] [PATCH 2/8] x86/early-quirks: replace the magical increment start values

[Ville Syrjälä]

On Fri, Nov 24, 2017 at 04:42:51PM +, Matthew Auld wrote:
> Replace the magical +2, +9 etc. with +MB, which is far easier to read.
> 
> Suggested-by: Ville Syrjälä 
> Signed-off-by: Matthew Auld 
> Cc: Joonas Lahtinen 
> Cc: Ville Syrjälä 
> Cc: Chris Wilson 
> Cc: Paulo Zanoni 
> Cc: Ingo Molnar 
> Cc: H. Peter Anvin 
> Cc: x...@kernel.org
> ---
>  arch/x86/kernel/early-quirks.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index 3116f579841a..3bc1e49d6c41 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -428,9 +428,9 @@ static resource_size_t __init chv_stolen_size(int num, 
> int slot, int func)
>   if (gms < 0x11)
>   return gms * MB(32);
>   else if (gms < 0x17)
> - return (gms - 0x11 + 2) * MB(4);
> + return (gms - 0x11) * MB(4) + MB(8);
>   else
> - return (gms - 0x17 + 9) * MB(4);
> + return (gms - 0x17) * MB(4) + MB(36);

Reviewed-by: Ville Syrjälä 

But now I'm thinking we should also reverse the if ladders...

if (gms >= 0x17)
return (gms - 0x17) * ...;
else if (gms >= 0x11)
return (gms - 0x11) * ...;
else
return gms * ...;

Better? I think so.

>  }
>  
>  static resource_size_t __init gen9_stolen_size(int num, int slot, int func)
> @@ -446,7 +446,7 @@ static resource_size_t __init gen9_stolen_size(int num, 
> int slot, int func)
>   if (gms < 0xf0)
>   return gms * MB(32);
>   else
> - return (gms - 0xf0 + 1) * MB(4);
> + return (gms - 0xf0) * MB(4) + MB(4);
>  }
>  
>  struct intel_early_ops {
> -- 
> 2.14.3

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] ✗ Fi.CI.IGT: warning for lib/igt_core: Move write_stderr out of LIBUNWIND ifdef

[Patchwork]

== Series Details ==

Series: lib/igt_core: Move write_stderr out of LIBUNWIND ifdef
URL   : https://patchwork.freedesktop.org/series/34349/
State : warning

== Summary ==

Test kms_flip:
Subgroup wf_vblank-vs-modeset-interruptible:
pass   -> SKIP   (shard-hsw) fdo#102614
Subgroup vblank-vs-suspend-interruptible:
pass   -> SKIP   (shard-hsw) fdo#100368
Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-b-planes:
pass   -> SKIP   (shard-hsw)
Subgroup plane-panning-bottom-right-suspend-pipe-a-planes:
pass   -> SKIP   (shard-snb) fdo#103667
Test drv_selftest:
Subgroup mock_sanitycheck:
pass   -> DMESG-WARN (shard-snb) fdo#103717
Test gem_busy:
Subgroup close-race:
fail   -> PASS   (shard-snb) fdo#103829
Test kms_frontbuffer_tracking:
Subgroup fbc-rgb565-draw-blt:
fail   -> PASS   (shard-snb) fdo#101623
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912

fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103667 https://bugs.freedesktop.org/show_bug.cgi?id=103667
fdo#103717 https://bugs.freedesktop.org/show_bug.cgi?id=103717
fdo#103829 https://bugs.freedesktop.org/show_bug.cgi?id=103829
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2667 pass:1533 dwarn:1   dfail:0   fail:9   skip:1124 
time:9396s
shard-snbtotal:2667 pass:1308 dwarn:2   dfail:0   fail:14  skip:1343 
time:8047s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_548/shards.html
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Re: [Intel-gfx] [PATCH 01/15] drm/i915: Reject odd pipe source width with double wide/dual link

[Daniel Vetter]

On Thu, Nov 23, 2017 at 09:04:48PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> In order to guarantee that pipe_src_w/h matches the user mode h/vdisplay
> we must not adjust pipe_src_w to accommodate double wide/dual link.
> Instead just reject the mode outright.
> 
> This will allows us to rely on crtc_state->mode for plane clipping.
> 
> Cc: Laurent Pinchart 
> Signed-off-by: Ville Syrjälä 

Might be real good if we have some igt that injects all these kinds of
funny modes, just to check for bugs and stuff (i.e. not encoding any
expectations that any of them work). Or maybe we need a smart fuzzer for
the atomic ioctl for that.

Musings aside, on patches 1&2:

Reviewed-by: Daniel Vetter 

> ---
>  drivers/gpu/drm/i915/intel_display.c | 15 ---
>  1 file changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index d67c7c498b34..959d21157328 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6332,9 +6332,18 @@ static int intel_crtc_compute_config(struct intel_crtc 
> *crtc,
>* - LVDS dual channel mode
>* - Double wide pipe
>*/
> - if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
> -  intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
> - pipe_config->pipe_src_w &= ~1;
> + if (pipe_config->pipe_src_w & 1) {
> + if (pipe_config->double_wide) {
> + DRM_DEBUG_KMS("Odd pipe source width not supported with 
> double wide pipe\n");
> + return -EINVAL;
> + }
> +
> + if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
> + intel_is_dual_link_lvds(dev)) {
> + DRM_DEBUG_KMS("Odd pipe source width not supported with 
> dual link LVDS\n");
> + return -EINVAL;
> + }
> + }
>  
>   /* Cantiga+ cannot handle modes with a hsync front porch of 0.
>* WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
> -- 
> 2.13.6
> 
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/guc: Advance over port[0] if set and not preempting

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/guc: Advance over port[0] if set 
and not preempting
URL   : https://patchwork.freedesktop.org/series/34361/
State : success

== Summary ==

Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
fail   -> PASS   (shard-snb) fdo#101623 +1
Test gem_busy:
Subgroup close-race:
fail   -> PASS   (shard-snb) fdo#103829

fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103829 https://bugs.freedesktop.org/show_bug.cgi?id=103829

shard-hswtotal:2667 pass:1535 dwarn:1   dfail:0   fail:10  skip:1121 
time:9535s
shard-snbtotal:2667 pass:1311 dwarn:1   dfail:0   fail:13  skip:1342 
time:8031s
Blacklisted hosts:
shard-apltotal:2667 pass:1660 dwarn:6   dfail:3   fail:43  skip:955 
time:12343s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7281/shards.html
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[Intel-gfx] [PATCH] drm/i915/guc: Use consistent name for scratch register count

[Michal Wajdeczko]

We should be consistent on naming of similar definitions.

Signed-off-by: Michal Wajdeczko 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_guc_fw.c  | 4 ++--
 drivers/gpu/drm/i915/intel_guc_reg.h | 3 ++-
 drivers/gpu/drm/i915/intel_uc_fw.c   | 2 +-
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c 
b/drivers/gpu/drm/i915/intel_guc_fw.c
index 69ba015..bbab4e1 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -130,14 +130,14 @@ static int guc_xfer_rsa(struct intel_guc *guc, struct 
i915_vma *vma)
struct drm_i915_private *dev_priv = guc_to_i915(guc);
struct intel_uc_fw *guc_fw = >fw;
struct sg_table *sg = vma->pages;
-   u32 rsa[UOS_RSA_SCRATCH_MAX_COUNT];
+   u32 rsa[UOS_RSA_SCRATCH_COUNT];
int i;
 
if (sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa),
   guc_fw->rsa_offset) != sizeof(rsa))
return -EINVAL;
 
-   for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++)
+   for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
 
return 0;
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h 
b/drivers/gpu/drm/i915/intel_guc_reg.h
index 0a8ff03..19a9247 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -52,7 +52,8 @@
 #define SOFT_SCRATCH_COUNT 16
 
 #define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)
-#define   UOS_RSA_SCRATCH_MAX_COUNT  64
+#define UOS_RSA_SCRATCH_COUNT  64
+
 #define DMA_ADDR_0_LOW _MMIO(0xc300)
 #define DMA_ADDR_0_HIGH_MMIO(0xc304)
 #define DMA_ADDR_1_LOW _MMIO(0xc308)
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c 
b/drivers/gpu/drm/i915/intel_uc_fw.c
index 4bc82d3..b376dd3 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/intel_uc_fw.c
@@ -105,7 +105,7 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
}
 
/* now RSA */
-   if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
+   if (css->key_size_dw != UOS_RSA_SCRATCH_COUNT) {
DRM_WARN("%s: Mismatched firmware RSA key size (%u)\n",
 intel_uc_fw_type_repr(uc_fw->type), css->key_size_dw);
err = -ENOEXEC;
-- 
2.7.4

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[Intel-gfx] ✓ Fi.CI.BAT: success for make stolen resource centric (rev2)

[Patchwork]

== Series Details ==

Series: make stolen resource centric (rev2)
URL   : https://patchwork.freedesktop.org/series/34256/
State : success

== Summary ==

Series 34256v2 make stolen resource centric
https://patchwork.freedesktop.org/api/1.0/series/34256/revisions/2/mbox/

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time:419s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:605s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
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time:496s

2cc63d7f56b7d8c9287a431773b3fec01b53e5cb drm-tip: 2017y-11m-24d-16h-04m-11s UTC 
integration manifest
cb677cdb2272 drm/i915: prefer resource_size_t for everything stolen
a7238c8fd709 drm/i915: make mappable struct resource centric
27e73fbf543f drm/i915: make reserved struct resource centric
1f90b9ab4ed0 drm/i915: make dsm struct resource centric
1dc9173fac06 drm/i915: s/mappable_end/mappable_size/
1b4a59faddbd drm/i915: nuke the duplicated stolen discovery
32992386a7dc x86/early-quirks: replace the magical increment start values
ef8723396370 x86/early-quirks: Extend Intel graphics stolen memory placement to 
64bit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7283/
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Re: [Intel-gfx] [PATCH 15/15] drm: Don't pass clip to drm_atomic_helper_check_plane_state()

[Daniel Vetter]

On Thu, Nov 23, 2017 at 09:05:02PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Move the plane clip rectangle handling into
> drm_atomic_helper_check_plane_state(). Drivers no longer
> have to worry about such mundane details.
> 
> Cc: Laurent Pinchart 
> Cc: Daniel Vetter 
> Suggested-by: Daniel Vetter 
> Signed-off-by: Ville Syrjälä 

I guess the longer-term next step would be that we expose can_scale and
can_position (and maybe the scaling limits?) as read-only properties, as
hints to the compositor. And then move all the calls into the overall
helpers (i.e. drm_atomic_helper_check_planes).

But this here is real sweet already I think.

Reviewed-by: Daniel Vetter 

> ---
>  drivers/gpu/drm/arm/hdlcd_crtc.c|  7 +--
>  drivers/gpu/drm/arm/malidp_planes.c |  7 +--
>  drivers/gpu/drm/armada/armada_overlay.c |  6 +-
>  drivers/gpu/drm/drm_atomic_helper.c | 12 +++-
>  drivers/gpu/drm/drm_plane_helper.c  | 11 +++
>  drivers/gpu/drm/drm_simple_kms_helper.c |  6 --
>  drivers/gpu/drm/i915/intel_display.c| 12 
>  drivers/gpu/drm/imx/ipuv3-plane.c   |  7 +--
>  drivers/gpu/drm/mediatek/mtk_drm_plane.c|  7 +--
>  drivers/gpu/drm/meson/meson_plane.c |  7 +--
>  drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c   | 14 ++
>  drivers/gpu/drm/nouveau/nv50_display.c  | 12 
>  drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  7 +--
>  drivers/gpu/drm/tegra/dc.c  |  7 +--
>  drivers/gpu/drm/vmwgfx/vmwgfx_kms.c |  7 +--
>  drivers/gpu/drm/zte/zx_plane.c  | 13 +
>  include/drm/drm_atomic_helper.h |  1 -
>  include/drm/drm_plane_helper.h  |  1 -
>  18 files changed, 22 insertions(+), 122 deletions(-)
> 
> diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c 
> b/drivers/gpu/drm/arm/hdlcd_crtc.c
> index fa852fc1c9e6..93c503b754ba 100644
> --- a/drivers/gpu/drm/arm/hdlcd_crtc.c
> +++ b/drivers/gpu/drm/arm/hdlcd_crtc.c
> @@ -229,7 +229,6 @@ static const struct drm_crtc_helper_funcs 
> hdlcd_crtc_helper_funcs = {
>  static int hdlcd_plane_atomic_check(struct drm_plane *plane,
>   struct drm_plane_state *state)
>  {
> - struct drm_rect clip = { 0 };
>   struct drm_crtc_state *crtc_state;
>   u32 src_h = state->src_h >> 16;
>  
> @@ -249,11 +248,7 @@ static int hdlcd_plane_atomic_check(struct drm_plane 
> *plane,
>   return -EINVAL;
>   }
>  
> - if (crtc_state->enable)
> - drm_mode_get_hv_timing(_state->mode,
> -, );
> -
> - return drm_atomic_helper_check_plane_state(state, crtc_state, ,
> + return drm_atomic_helper_check_plane_state(state, crtc_state,
>  DRM_PLANE_HELPER_NO_SCALING,
>  DRM_PLANE_HELPER_NO_SCALING,
>  false, true);
> diff --git a/drivers/gpu/drm/arm/malidp_planes.c 
> b/drivers/gpu/drm/arm/malidp_planes.c
> index 2f6d608d6eaf..e630c0218aaf 100644
> --- a/drivers/gpu/drm/arm/malidp_planes.c
> +++ b/drivers/gpu/drm/arm/malidp_planes.c
> @@ -141,18 +141,13 @@ static int malidp_se_check_scaling(struct malidp_plane 
> *mp,
>   struct drm_crtc_state *crtc_state =
>   drm_atomic_get_existing_crtc_state(state->state, state->crtc);
>   struct malidp_crtc_state *mc;
> - struct drm_rect clip = { 0 };
>   u32 src_w, src_h;
>   int ret;
>  
>   if (!crtc_state)
>   return -EINVAL;
>  
> - if (crtc_state->enable)
> - drm_mode_get_hv_timing(_state->mode,
> -, );
> -
> - ret = drm_atomic_helper_check_plane_state(state, crtc_state, ,
> + ret = drm_atomic_helper_check_plane_state(state, crtc_state,
> 0, INT_MAX, true, true);
>   if (ret)
>   return ret;
> diff --git a/drivers/gpu/drm/armada/armada_overlay.c 
> b/drivers/gpu/drm/armada/armada_overlay.c
> index b411b608821a..564bd63a5f6a 100644
> --- a/drivers/gpu/drm/armada/armada_overlay.c
> +++ b/drivers/gpu/drm/armada/armada_overlay.c
> @@ -111,10 +111,6 @@ armada_ovl_plane_update(struct drm_plane *plane, struct 
> drm_crtc *crtc,
>   .x2 = crtc_x + crtc_w,
>   .y2 = crtc_y + crtc_h,
>   };
> - const struct drm_rect clip = {
> - .x2 = crtc->mode.hdisplay,
> - .y2 = crtc->mode.vdisplay,
> - };
>   uint32_t val, ctrl0;
>   unsigned idx = 0;
>   bool visible;
> @@ -124,7 +120,7 @@ armada_ovl_plane_update(struct drm_plane *plane, struct 
> drm_crtc *crtc,
>crtc_x, crtc_y, 

Re: [Intel-gfx] [PATCH] drm/i915: Disable THP until we have a read BW W/A

[Matthew Auld]

On 24 November 2017 at 11:27, Joonas Lahtinen
 wrote:
> We seem to be missing some W/A for 2M pages and are getting
> a hit on raw read bandwidths (even 30%) even though the write
> bandwidths improve (even 10%).
>
> For now, disable THP, which is our only practical source of
> 2M pages until we have a W/A for the issue.
>
> Reported-by: Valtteri Rantala 
> Fixes: b901bb89324a ("drm/i915/gemfs: enable THP")
> Signed-off-by: Joonas Lahtinen 
> Cc: Matthew Auld 
> Cc: Chris Wilson 
> Cc: Jani Nikula 
> Cc: Rodrigo Vivi 
> Cc: Valtteri Rantala 
> Cc: Eero Tamminen 

With s/deny/never/:
Reviewed-by: Matthew Auld 
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Re: [Intel-gfx] [PATCH] drm/i915: Expose the busyspin durations for i915_wait_request

[Chris Wilson]

Quoting Tvrtko Ursulin (2017-11-24 16:44:21)
> 
> On 24/11/2017 14:54, Chris Wilson wrote:
> > An interesting discussion regarding "hybrid interrupt polling" for NVMe
> > came to the conclusion that the ideal busyspin before sleeping was half
> > of the expected request latency (and better if it was already halfway
> > through that request). This suggested that we too should look again at
> > our tradeoff between spinning and waiting. Currently, our spin simply
> > tries to hide the cost of enabling the interrupt, which is good to avoid
> > penalising nop requests (i.e. test throughput) and not much else.
> > Studying real world workloads suggests that a spin of upto 500us can
> > dramatically boost performance, but the suggestion is that this is not
> > from avoiding interrupt latency per-se, but from secondary effects of
> > sleeping such as allowing the CPU reduce cstate and context switch away.
> > 
> > v2: Expose the spin setting via Kconfig options for easier adjustment
> > and testing.
> > 
> > Suggested-by: Sagar Kamble 
> > Signed-off-by: Chris Wilson 
> > Cc: Sagar Kamble 
> > Cc: Eero Tamminen 
> > Cc: Tvrtko Ursulin 
> > Cc: Ben Widawsky 
> > Cc: Joonas Lahtinen 
> > Cc: Michał Winiarski 
> > ---
> >   drivers/gpu/drm/i915/Kconfig|  6 ++
> >   drivers/gpu/drm/i915/Kconfig.profile| 23 +++
> >   drivers/gpu/drm/i915/i915_gem_request.c | 28 
> >   3 files changed, 53 insertions(+), 4 deletions(-)
> >   create mode 100644 drivers/gpu/drm/i915/Kconfig.profile
> > 
> > diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
> > index dfd95889f4b7..0553c3176109 100644
> > --- a/drivers/gpu/drm/i915/Kconfig
> > +++ b/drivers/gpu/drm/i915/Kconfig
> > @@ -131,3 +131,9 @@ depends on DRM_I915
> >   depends on EXPERT
> >   source drivers/gpu/drm/i915/Kconfig.debug
> >   endmenu
> > +
> > +menu "drm/i915 Profile Guided Optimisation"
> > +depends on DRM_I915
> > +depends on EXPERT
> > +source drivers/gpu/drm/i915/Kconfig.profile
> > +endmenu
> > diff --git a/drivers/gpu/drm/i915/Kconfig.profile 
> > b/drivers/gpu/drm/i915/Kconfig.profile
> > new file mode 100644
> > index ..c8fe5754466c
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/Kconfig.profile
> > @@ -0,0 +1,23 @@
> > +config DRM_I915_SPIN_REQUEST_IRQ
> > + int
> > + default 5 # microseconds
> > + help
> > +   Before sleeping waiting for a request (GPU operation) to complete,
> > +   we may spend some time polling for its completion. As the IRQ may
> > +   take a non-negligible time to setup, we do a short spin first to
> > +   check if the request will complete quickly.
> > +
> > +   May be 0 to disable the initial spin.
> > +
> > +config DRM_I915_SPIN_REQUEST_CS
> > + int
> > + default 20 # microseconds
> > + help
> > +   After sleeping for a request (GPU operation) to complete, we will
> > +   be woken up on the completion of every request prior to the one
> > +   being waited on. For very short requests, going back to sleep and
> > +   be woken up again may add considerably to the wakeup latency. To
> > +   avoid incurring extra latency from the scheduler, we may choose to
> > +   spin prior to sleeping again.
> > +
> > +   May be 0 to disable spinning after being woken.
> > diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
> > b/drivers/gpu/drm/i915/i915_gem_request.c
> > index a90bdd26571f..7ac72a0a949c 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_request.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_request.c
> > @@ -1198,8 +1198,21 @@ long i915_wait_request(struct drm_i915_gem_request 
> > *req,
> >   GEM_BUG_ON(!intel_wait_has_seqno());
> >   GEM_BUG_ON(!i915_sw_fence_signaled(>submit));
> >   
> > - /* Optimistic short spin before touching IRQs */
> > - if (__i915_spin_request(req, wait.seqno, state, 5))
> > + /* Optimistic spin before touching IRQs.
> > +  *
> > +  * We may use a rather large value here to offset the penalty of
> > +  * switching away from the active task. Frequently, the client will
> > +  * wait upon an old swapbuffer to throttle itself to remain within a
> > +  * frame of the gpu. If the client is running in lockstep with the 
> > gpu,
> > +  * then it should not be waiting long at all, and a sleep now will 
> > incur
> > +  * extra scheduler latency in producing the next frame. So we sleep
> > +  * for longer to try and keep the client running.
> > +  *
> > +  * We need ~5us to enable the irq, ~20us to hide a context switch.
> > +  */
> > + if (CONFIG_DRM_I915_SPIN_REQUEST_IRQ &&
> > + __i915_spin_request(req, wait.seqno, state,
> > + 

Re: [Intel-gfx] [PATCH 8/8] drm/i915: prefer resource_size_t for everything stolen

[Chris Wilson]

Quoting Matthew Auld (2017-11-24 16:42:57)
> Keeps things consistent now that we make use of struct resource. This
> should keep us covered in case we ever get huge amounts of stolen
> memory.
> 
> v2: bunch of missing conversions (Chris)
> 
> Signed-off-by: Matthew Auld 
> Cc: Joonas Lahtinen 
> Cc: Chris Wilson 
> Cc: Paulo Zanoni 
> ---
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index a05e2b92c02c..248d18a255d8 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -523,7 +523,7 @@ static int i915_gem_object_info(struct seq_file *m, void 
> *data)
>dpy_count, dpy_size);
>  
> seq_printf(m, "%llu [%llu] gtt total\n",
> -  ggtt->base.total, ggtt->mappable_size);
> +  ggtt->base.total, (u64)ggtt->mappable_size);

resource_size_t uses %pa (same as phys_addr_t), which you used below.
Did it not work with seq_printf?
-Chris

> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 35d91cf07123..390de1c74329 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -3354,7 +3354,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
>  * a coarse sanity check.
>  */
> if (ggtt->mappable_size < (64<<20) || ggtt->mappable_size > 
> (512<<20)) {
> -   DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_size);
> +   DRM_ERROR("Unknown GMADR size (%pa)\n", >mappable_size);
> return -ENXIO;
> }
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Re: [Intel-gfx] [PATCH] drm/i915: Expose the busyspin durations for i915_wait_request

[Tvrtko Ursulin]

On 24/11/2017 14:54, Chris Wilson wrote:

An interesting discussion regarding "hybrid interrupt polling" for NVMe
came to the conclusion that the ideal busyspin before sleeping was half
of the expected request latency (and better if it was already halfway
through that request). This suggested that we too should look again at
our tradeoff between spinning and waiting. Currently, our spin simply
tries to hide the cost of enabling the interrupt, which is good to avoid
penalising nop requests (i.e. test throughput) and not much else.
Studying real world workloads suggests that a spin of upto 500us can
dramatically boost performance, but the suggestion is that this is not
from avoiding interrupt latency per-se, but from secondary effects of
sleeping such as allowing the CPU reduce cstate and context switch away.

v2: Expose the spin setting via Kconfig options for easier adjustment
and testing.

Suggested-by: Sagar Kamble 
Signed-off-by: Chris Wilson 
Cc: Sagar Kamble 
Cc: Eero Tamminen 
Cc: Tvrtko Ursulin 
Cc: Ben Widawsky 
Cc: Joonas Lahtinen 
Cc: Michał Winiarski 
---
  drivers/gpu/drm/i915/Kconfig|  6 ++
  drivers/gpu/drm/i915/Kconfig.profile| 23 +++
  drivers/gpu/drm/i915/i915_gem_request.c | 28 
  3 files changed, 53 insertions(+), 4 deletions(-)
  create mode 100644 drivers/gpu/drm/i915/Kconfig.profile

diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index dfd95889f4b7..0553c3176109 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -131,3 +131,9 @@ depends on DRM_I915
  depends on EXPERT
  source drivers/gpu/drm/i915/Kconfig.debug
  endmenu
+
+menu "drm/i915 Profile Guided Optimisation"
+depends on DRM_I915
+depends on EXPERT
+source drivers/gpu/drm/i915/Kconfig.profile
+endmenu
diff --git a/drivers/gpu/drm/i915/Kconfig.profile 
b/drivers/gpu/drm/i915/Kconfig.profile
new file mode 100644
index ..c8fe5754466c
--- /dev/null
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -0,0 +1,23 @@
+config DRM_I915_SPIN_REQUEST_IRQ
+   int
+   default 5 # microseconds
+   help
+ Before sleeping waiting for a request (GPU operation) to complete,
+ we may spend some time polling for its completion. As the IRQ may
+ take a non-negligible time to setup, we do a short spin first to
+ check if the request will complete quickly.
+
+ May be 0 to disable the initial spin.
+
+config DRM_I915_SPIN_REQUEST_CS
+   int
+   default 20 # microseconds
+   help
+ After sleeping for a request (GPU operation) to complete, we will
+ be woken up on the completion of every request prior to the one
+ being waited on. For very short requests, going back to sleep and
+ be woken up again may add considerably to the wakeup latency. To
+ avoid incurring extra latency from the scheduler, we may choose to
+ spin prior to sleeping again.
+
+ May be 0 to disable spinning after being woken.
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index a90bdd26571f..7ac72a0a949c 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -1198,8 +1198,21 @@ long i915_wait_request(struct drm_i915_gem_request *req,
GEM_BUG_ON(!intel_wait_has_seqno());
GEM_BUG_ON(!i915_sw_fence_signaled(>submit));
  
-	/* Optimistic short spin before touching IRQs */

-   if (__i915_spin_request(req, wait.seqno, state, 5))
+   /* Optimistic spin before touching IRQs.
+*
+* We may use a rather large value here to offset the penalty of
+* switching away from the active task. Frequently, the client will
+* wait upon an old swapbuffer to throttle itself to remain within a
+* frame of the gpu. If the client is running in lockstep with the gpu,
+* then it should not be waiting long at all, and a sleep now will incur
+* extra scheduler latency in producing the next frame. So we sleep
+* for longer to try and keep the client running.
+*
+* We need ~5us to enable the irq, ~20us to hide a context switch.
+*/
+   if (CONFIG_DRM_I915_SPIN_REQUEST_IRQ &&
+   __i915_spin_request(req, wait.seqno, state,
+   CONFIG_DRM_I915_SPIN_REQUEST_IRQ))
goto complete;
  
  	set_current_state(state);

@@ -1255,8 +1268,15 @@ long i915_wait_request(struct drm_i915_gem_request *req,
__i915_wait_request_check_and_reset(req))
continue;
  
-		/* Only spin if we know the GPU is processing this request */

-   if (__i915_spin_request(req, wait.seqno, 

[Intel-gfx] [PATCH 6/8] drm/i915: make reserved struct resource centric

[Matthew Auld]

v2: s/<= end + 1/< end/ (Chris)

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_drv.h|  4 
 drivers/gpu/drm/i915/i915_gem_gtt.h|  2 --
 drivers/gpu/drm/i915/i915_gem_stolen.c | 16 
 drivers/gpu/drm/i915/intel_pm.c|  6 ++
 4 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 313ab1e98fc7..e30a8a7812ba 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2258,6 +2258,10 @@ struct drm_i915_private {
 * while ggtt->stolen_size gives us the total size of the stolen region.
 */
struct resource dsm;
+   /**
+* Reseved portion of Data Stolen Memory
+*/
+   struct resource dsm_reserved;
 
void __iomem *regs;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h 
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 922d796983d5..6eb34fd2c4ba 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -383,8 +383,6 @@ struct i915_ggtt {
 */
u32 stolen_size;/* Total size of stolen memory */
u32 stolen_usable_size; /* Total size minus reserved ranges */
-   u32 stolen_reserved_base;
-   u32 stolen_reserved_size;
 
/** "Graphics Stolen Memory" holds the global PTEs */
void __iomem *gsm;
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c 
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 36c8ec04fd7a..2b7af60dfce0 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -333,6 +333,7 @@ static void bdw_get_stolen_reserved(struct drm_i915_private 
*dev_priv,
 int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
 {
struct i915_ggtt *ggtt = _priv->ggtt;
+   struct resource reserved = DEFINE_RES_MEM(0, 0);
dma_addr_t reserved_base, stolen_top;
u32 reserved_total, reserved_size;
u32 stolen_usable_start;
@@ -400,17 +401,16 @@ int i915_gem_init_stolen(struct drm_i915_private 
*dev_priv)
reserved_base = stolen_top;
}
 
-   if (reserved_base < dev_priv->dsm.start ||
-   reserved_base + reserved_size > stolen_top) {
-   dma_addr_t reserved_top = reserved_base + reserved_size;
-   DRM_ERROR("Stolen reserved area [%pad - %pad] outside stolen 
memory [%pad - %pad]\n",
- _base, _top,
- _priv->dsm.start, _top);
+   reserved.start = reserved_base;
+   reserved.end = reserved_base + reserved_size - 1;
+
+   if (!resource_contains(_priv->dsm, )) {
+   DRM_ERROR("Stolen reserved area %pR outside stolen memory 
%pR\n",
+ , _priv->dsm);
return 0;
}
 
-   ggtt->stolen_reserved_base = reserved_base;
-   ggtt->stolen_reserved_size = reserved_size;
+   dev_priv->dsm_reserved = reserved;
 
/* It is possible for the reserved area to end before the end of stolen
 * memory, so just consider the start. */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 872d15f599d1..a07b7b456b50 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6439,7 +6439,6 @@ static void intel_print_rc6_info(struct drm_i915_private 
*dev_priv, u32 mode)
 
 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
 {
-   struct i915_ggtt *ggtt = _priv->ggtt;
bool enable_rc6 = true;
unsigned long rc6_ctx_base;
u32 rc_ctl;
@@ -6464,9 +6463,8 @@ static bool bxt_check_bios_rc6_setup(struct 
drm_i915_private *dev_priv)
 * for this check.
 */
rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
-   if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
- (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
-   ggtt->stolen_reserved_size))) {
+   if (!((rc6_ctx_base >= dev_priv->dsm_reserved.start) &&
+ (rc6_ctx_base + PAGE_SIZE < dev_priv->dsm_reserved.end))) {
DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
enable_rc6 = false;
}
-- 
2.14.3

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[Intel-gfx] [PATCH 2/8] x86/early-quirks: replace the magical increment start values

[Matthew Auld]

Replace the magical +2, +9 etc. with +MB, which is far easier to read.

Suggested-by: Ville Syrjälä 
Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Ville Syrjälä 
Cc: Chris Wilson 
Cc: Paulo Zanoni 
Cc: Ingo Molnar 
Cc: H. Peter Anvin 
Cc: x...@kernel.org
---
 arch/x86/kernel/early-quirks.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 3116f579841a..3bc1e49d6c41 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -428,9 +428,9 @@ static resource_size_t __init chv_stolen_size(int num, int 
slot, int func)
if (gms < 0x11)
return gms * MB(32);
else if (gms < 0x17)
-   return (gms - 0x11 + 2) * MB(4);
+   return (gms - 0x11) * MB(4) + MB(8);
else
-   return (gms - 0x17 + 9) * MB(4);
+   return (gms - 0x17) * MB(4) + MB(36);
 }
 
 static resource_size_t __init gen9_stolen_size(int num, int slot, int func)
@@ -446,7 +446,7 @@ static resource_size_t __init gen9_stolen_size(int num, int 
slot, int func)
if (gms < 0xf0)
return gms * MB(32);
else
-   return (gms - 0xf0 + 1) * MB(4);
+   return (gms - 0xf0) * MB(4) + MB(4);
 }
 
 struct intel_early_ops {
-- 
2.14.3

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[Intel-gfx] [PATCH 8/8] drm/i915: prefer resource_size_t for everything stolen

[Matthew Auld]

Keeps things consistent now that we make use of struct resource. This
should keep us covered in case we ever get huge amounts of stolen
memory.

v2: bunch of missing conversions (Chris)

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Paulo Zanoni 
---
 drivers/char/agp/intel-gtt.c   | 14 +-
 drivers/gpu/drm/i915/i915_debugfs.c|  2 +-
 drivers/gpu/drm/i915/i915_drv.h|  9 +++---
 drivers/gpu/drm/i915/i915_gem_gtt.c| 10 +++
 drivers/gpu/drm/i915/i915_gem_gtt.h|  6 ++--
 drivers/gpu/drm/i915/i915_gem_stolen.c | 51 +-
 drivers/gpu/drm/i915/intel_pm.c| 10 +++
 include/drm/intel-gtt.h|  4 +--
 8 files changed, 54 insertions(+), 52 deletions(-)

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 2a321ee2943a..312c4cc440bc 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -80,7 +80,7 @@ static struct _intel_private {
unsigned int needs_dmar : 1;
phys_addr_t gma_bus_addr;
/*  Size of memory reserved for graphics by the BIOS */
-   unsigned int stolen_size;
+   resource_size_t stolen_size;
/* Total number of gtt entries. */
unsigned int gtt_total_entries;
/* Part of the gtt that is mappable by the cpu, for those chips where
@@ -333,13 +333,13 @@ static void i810_write_entry(dma_addr_t addr, unsigned 
int entry,
writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
 }
 
-static unsigned int intel_gtt_stolen_size(void)
+static resource_size_t intel_gtt_stolen_size(void)
 {
u16 gmch_ctrl;
u8 rdct;
int local = 0;
static const int ddt[4] = { 0, 16, 32, 64 };
-   unsigned int stolen_size = 0;
+   resource_size_t stolen_size = 0;
 
if (INTEL_GTT_GEN == 1)
return 0; /* no stolen mem on i81x */
@@ -417,8 +417,8 @@ static unsigned int intel_gtt_stolen_size(void)
}
 
if (stolen_size > 0) {
-   dev_info(_private.bridge_dev->dev, "detected %dK %s 
memory\n",
-  stolen_size / KB(1), local ? "local" : "stolen");
+   dev_info(_private.bridge_dev->dev, "detected %lluK %s 
memory\n",
+  (u64)stolen_size / KB(1), local ? "local" : "stolen");
} else {
dev_info(_private.bridge_dev->dev,
   "no pre-allocated video memory detected\n");
@@ -1422,9 +1422,9 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev, struct 
pci_dev *gpu_pdev,
 EXPORT_SYMBOL(intel_gmch_probe);
 
 void intel_gtt_get(u64 *gtt_total,
-  u32 *stolen_size,
+  resource_size_t *stolen_size,
   phys_addr_t *mappable_base,
-  u64 *mappable_size)
+  resource_size_t *mappable_size)
 {
*gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT;
*stolen_size = intel_private.stolen_size;
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index a05e2b92c02c..248d18a255d8 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -523,7 +523,7 @@ static int i915_gem_object_info(struct seq_file *m, void 
*data)
   dpy_count, dpy_size);
 
seq_printf(m, "%llu [%llu] gtt total\n",
-  ggtt->base.total, ggtt->mappable_size);
+  ggtt->base.total, (u64)ggtt->mappable_size);
seq_printf(m, "Supported page sizes: %s\n",
   stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes,
buf, sizeof(buf)));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e30a8a7812ba..eedffb941f9d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3908,12 +3908,13 @@ void i915_gem_stolen_remove_node(struct 
drm_i915_private *dev_priv,
 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
 void i915_gem_cleanup_stolen(struct drm_device *dev);
 struct drm_i915_gem_object *
-i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
+i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
+ resource_size_t size);
 struct drm_i915_gem_object *
 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private 
*dev_priv,
-  u32 stolen_offset,
-  u32 gtt_offset,
-  u32 size);
+  resource_size_t stolen_offset,
+  resource_size_t gtt_offset,
+  resource_size_t size);
 
 /* i915_gem_internal.c */
 struct 

[Intel-gfx] [PATCH 5/8] drm/i915: make dsm struct resource centric

[Matthew Auld]

v2: check range_overflow when writing to 32b registers (Chris)
pepper in some comments (Chris)

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_drv.h| 13 ++---
 drivers/gpu/drm/i915/i915_gem_stolen.c | 19 +++
 drivers/gpu/drm/i915/intel_fbc.c   | 10 --
 drivers/gpu/drm/i915/intel_pm.c| 17 +
 4 files changed, 42 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d575a56fc100..313ab1e98fc7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1536,9 +1536,6 @@ struct i915_gem_mm {
 */
struct pagevec wc_stash;
 
-   /** Usable portion of the GTT for GEM */
-   dma_addr_t stolen_base; /* limited to low memory (32-bit) */
-
/**
 * tmpfs instance used for shmem backed objects
 */
@@ -2252,6 +2249,16 @@ struct drm_i915_private {
 
const struct intel_device_info info;
 
+   /**
+* Data Stolen Memory - aka "i915 stolen memory" gives us the start and
+* end of stolen which we can optionally use to create GEM objects
+* backed by stolen memory. Note that ggtt->stolen_usable_size tells us
+* exactly how much of this we are actually allowed to use, given that
+* some portion of it is in fact reserved for use by hardware functions,
+* while ggtt->stolen_size gives us the total size of the stolen region.
+*/
+   struct resource dsm;
+
void __iomem *regs;
 
struct intel_uncore uncore;
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c 
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index f1b8eeda0058..36c8ec04fd7a 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -185,7 +185,7 @@ static void g4x_get_stolen_reserved(struct drm_i915_private 
*dev_priv,
uint32_t reg_val = I915_READ(IS_GM45(dev_priv) ?
 CTG_STOLEN_RESERVED :
 ELK_STOLEN_RESERVED);
-   dma_addr_t stolen_top = dev_priv->mm.stolen_base + ggtt->stolen_size;
+   dma_addr_t stolen_top = dev_priv->dsm.start + ggtt->stolen_size;
 
if ((reg_val & G4X_STOLEN_RESERVED_ENABLE) == 0) {
*base = 0;
@@ -316,7 +316,7 @@ static void bdw_get_stolen_reserved(struct drm_i915_private 
*dev_priv,
return;
}
 
-   stolen_top = dev_priv->mm.stolen_base + ggtt->stolen_size;
+   stolen_top = dev_priv->dsm.start + ggtt->stolen_size;
 
*base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
 
@@ -352,11 +352,14 @@ int i915_gem_init_stolen(struct drm_i915_private 
*dev_priv)
if (ggtt->stolen_size == 0)
return 0;
 
-   dev_priv->mm.stolen_base = i915_stolen_to_dma(dev_priv);
-   if (dev_priv->mm.stolen_base == 0)
+   dev_priv->dsm.start = i915_stolen_to_dma(dev_priv);
+   if (dev_priv->dsm.start == 0)
return 0;
 
-   stolen_top = dev_priv->mm.stolen_base + ggtt->stolen_size;
+   dev_priv->dsm.end = dev_priv->dsm.start + ggtt->stolen_size - 1;
+   dev_priv->dsm.flags = IORESOURCE_MEM;
+
+   stolen_top = dev_priv->dsm.end + 1;
reserved_base = 0;
reserved_size = 0;
 
@@ -397,12 +400,12 @@ int i915_gem_init_stolen(struct drm_i915_private 
*dev_priv)
reserved_base = stolen_top;
}
 
-   if (reserved_base < dev_priv->mm.stolen_base ||
+   if (reserved_base < dev_priv->dsm.start ||
reserved_base + reserved_size > stolen_top) {
dma_addr_t reserved_top = reserved_base + reserved_size;
DRM_ERROR("Stolen reserved area [%pad - %pad] outside stolen 
memory [%pad - %pad]\n",
  _base, _top,
- _priv->mm.stolen_base, _top);
+ _priv->dsm.start, _top);
return 0;
}
 
@@ -460,7 +463,7 @@ i915_pages_create_for_stolen(struct drm_device *dev,
sg->offset = 0;
sg->length = size;
 
-   sg_dma_address(sg) = (dma_addr_t)dev_priv->mm.stolen_base + offset;
+   sg_dma_address(sg) = (dma_addr_t)dev_priv->dsm.start + offset;
sg_dma_len(sg) = size;
 
return st;
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 4aefc658a5cf..a291bb965e2e 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -615,10 +615,16 @@ static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
 
fbc->compressed_llb = compressed_llb;
 
+   GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start,
+fbc->compressed_fb.start,
+   

[Intel-gfx] [PATCH 3/8] drm/i915: nuke the duplicated stolen discovery

[Matthew Auld]

We duplicate the stolen discovery code in early-quirks and in i915,
however now the stolen region is exported as a resource from
early-quirks we can nuke the duplication.

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c|  51 +--
 drivers/gpu/drm/i915/i915_gem_stolen.c | 109 +
 2 files changed, 4 insertions(+), 156 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 41a203e0c160..6b567bab2363 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2949,50 +2949,6 @@ static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
return 0;
 }
 
-static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
-{
-   snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
-   snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
-   return (size_t)snb_gmch_ctl << 25; /* 32 MB units */
-}
-
-static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
-{
-   bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
-   bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
-   return (size_t)bdw_gmch_ctl << 25; /* 32 MB units */
-}
-
-static size_t chv_get_stolen_size(u16 gmch_ctrl)
-{
-   gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
-   gmch_ctrl &= SNB_GMCH_GMS_MASK;
-
-   /*
-* 0x0  to 0x10: 32MB increments starting at 0MB
-* 0x11 to 0x16: 4MB increments starting at 8MB
-* 0x17 to 0x1d: 4MB increments start at 36MB
-*/
-   if (gmch_ctrl < 0x11)
-   return (size_t)gmch_ctrl << 25;
-   else if (gmch_ctrl < 0x17)
-   return (size_t)(gmch_ctrl - 0x11 + 2) << 22;
-   else
-   return (size_t)(gmch_ctrl - 0x17 + 9) << 22;
-}
-
-static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
-{
-   gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
-   gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
-
-   if (gen9_gmch_ctl < 0xf0)
-   return (size_t)gen9_gmch_ctl << 25; /* 32 MB units */
-   else
-   /* 4MB increments starting at 0xf0 for 4MB */
-   return (size_t)(gen9_gmch_ctl - 0xf0 + 1) << 22;
-}
-
 static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
 {
struct drm_i915_private *dev_priv = ggtt->base.i915;
@@ -3343,14 +3299,13 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 
pci_read_config_word(pdev, SNB_GMCH_CTRL, _gmch_ctl);
 
+   ggtt->stolen_size = resource_size(_graphics_stolen_res);
+
if (INTEL_GEN(dev_priv) >= 9) {
-   ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl);
size = gen8_get_total_gtt_size(snb_gmch_ctl);
} else if (IS_CHERRYVIEW(dev_priv)) {
-   ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl);
size = chv_get_total_gtt_size(snb_gmch_ctl);
} else {
-   ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl);
size = gen8_get_total_gtt_size(snb_gmch_ctl);
}
 
@@ -3408,7 +3363,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err);
pci_read_config_word(pdev, SNB_GMCH_CTRL, _gmch_ctl);
 
-   ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
+   ggtt->stolen_size = resource_size(_graphics_stolen_res);
 
size = gen6_get_total_gtt_size(snb_gmch_ctl);
ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c 
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 1877ae9a1d9b..f1b8eeda0058 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -30,9 +30,6 @@
 #include 
 #include "i915_drv.h"
 
-#define KB(x) ((x) * 1024)
-#define MB(x) (KB(x) * 1024)
-
 /*
  * The BIOS typically reserves some of the system's memory for the exclusive
  * use of the integrated graphics. This memory is no longer available for
@@ -81,113 +78,9 @@ void i915_gem_stolen_remove_node(struct drm_i915_private 
*dev_priv,
 
 static dma_addr_t i915_stolen_to_dma(struct drm_i915_private *dev_priv)
 {
-   struct pci_dev *pdev = dev_priv->drm.pdev;
struct i915_ggtt *ggtt = _priv->ggtt;
+   dma_addr_t base = intel_graphics_stolen_res.start;
struct resource *r;
-   dma_addr_t base;
-
-   /* Almost universally we can find the Graphics Base of Stolen Memory
-* at register BSM (0x5c) in the igfx configuration space. On a few
-* (desktop) machines this is also mirrored in the bridge device at
-* different locations, or in the MCHBAR.
-*
-* On 865 we just check the TOUD register.
-*
-* On 830/845/85x the stolen memory base isn't available in any
-* register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
-*
-*/

[Intel-gfx] [PATCH 1/8] x86/early-quirks: Extend Intel graphics stolen memory placement to 64bit

[Matthew Auld]

From: Joonas Lahtinen 

In preparation for upcoming SKUs, allow more freedom in placement
of the Intel graphics stolen memory by BIOS to full 64bit range.

v2: export the stolen region as a resource
fix u16 << 16 (Chris)

Signed-off-by: Joonas Lahtinen 
Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Ville Syrjälä 
Cc: Chris Wilson 
Cc: Paulo Zanoni 
Cc: Ingo Molnar 
Cc: H. Peter Anvin 
Cc: x...@kernel.org
Reviewed-by: Chris Wilson  #v1
---
 arch/x86/kernel/early-quirks.c | 86 +++---
 include/drm/i915_drm.h |  3 ++
 2 files changed, 50 insertions(+), 39 deletions(-)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 1e82f787c160..3116f579841a 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -243,7 +243,7 @@ static void __init intel_remapping_check(int num, int slot, 
int func)
 #define KB(x)  ((x) * 1024UL)
 #define MB(x)  (KB (KB (x)))
 
-static size_t __init i830_tseg_size(void)
+static resource_size_t __init i830_tseg_size(void)
 {
u8 esmramc = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
 
@@ -256,7 +256,7 @@ static size_t __init i830_tseg_size(void)
return KB(512);
 }
 
-static size_t __init i845_tseg_size(void)
+static resource_size_t __init i845_tseg_size(void)
 {
u8 esmramc = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
u8 tseg_size = esmramc & I845_TSEG_SIZE_MASK;
@@ -273,7 +273,7 @@ static size_t __init i845_tseg_size(void)
return 0;
 }
 
-static size_t __init i85x_tseg_size(void)
+static resource_size_t __init i85x_tseg_size(void)
 {
u8 esmramc = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
 
@@ -283,12 +283,12 @@ static size_t __init i85x_tseg_size(void)
return MB(1);
 }
 
-static size_t __init i830_mem_size(void)
+static resource_size_t __init i830_mem_size(void)
 {
return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32);
 }
 
-static size_t __init i85x_mem_size(void)
+static resource_size_t __init i85x_mem_size(void)
 {
return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32);
 }
@@ -297,36 +297,36 @@ static size_t __init i85x_mem_size(void)
  * On 830/845/85x the stolen memory base isn't available in any
  * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
  */
-static phys_addr_t __init i830_stolen_base(int num, int slot, int func,
-  size_t stolen_size)
+static resource_size_t __init i830_stolen_base(int num, int slot, int func,
+  resource_size_t stolen_size)
 {
-   return (phys_addr_t)i830_mem_size() - i830_tseg_size() - stolen_size;
+   return i830_mem_size() - i830_tseg_size() - stolen_size;
 }
 
-static phys_addr_t __init i845_stolen_base(int num, int slot, int func,
-  size_t stolen_size)
+static resource_size_t __init i845_stolen_base(int num, int slot, int func,
+  resource_size_t stolen_size)
 {
-   return (phys_addr_t)i830_mem_size() - i845_tseg_size() - stolen_size;
+   return i830_mem_size() - i845_tseg_size() - stolen_size;
 }
 
-static phys_addr_t __init i85x_stolen_base(int num, int slot, int func,
-  size_t stolen_size)
+static resource_size_t __init i85x_stolen_base(int num, int slot, int func,
+  resource_size_t stolen_size)
 {
-   return (phys_addr_t)i85x_mem_size() - i85x_tseg_size() - stolen_size;
+   return i85x_mem_size() - i85x_tseg_size() - stolen_size;
 }
 
-static phys_addr_t __init i865_stolen_base(int num, int slot, int func,
-  size_t stolen_size)
+static resource_size_t __init i865_stolen_base(int num, int slot, int func,
+  resource_size_t stolen_size)
 {
u16 toud = 0;
 
toud = read_pci_config_16(0, 0, 0, I865_TOUD);
 
-   return (phys_addr_t)(toud << 16) + i845_tseg_size();
+   return (resource_size_t)(toud << 16) + i845_tseg_size();
 }
 
-static phys_addr_t __init gen3_stolen_base(int num, int slot, int func,
-  size_t stolen_size)
+static resource_size_t __init gen3_stolen_base(int num, int slot, int func,
+  resource_size_t stolen_size)
 {
u32 bsm;
 
@@ -337,10 +337,10 @@ static phys_addr_t __init gen3_stolen_base(int num, int 
slot, int func,
 */
bsm = read_pci_config(num, slot, func, INTEL_BSM);
 
-   return (phys_addr_t)bsm & INTEL_BSM_MASK;
+   return bsm & INTEL_BSM_MASK;
 }
 

[Intel-gfx] [PATCH 7/8] drm/i915: make mappable struct resource centric

[Matthew Auld]

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Paulo Zanoni 
---
 drivers/gpu/drm/i915/gvt/gvt.h|  2 +-
 drivers/gpu/drm/i915/i915_drv.c   |  2 +-
 drivers/gpu/drm/i915/i915_gem.c   |  8 
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c   | 28 ---
 drivers/gpu/drm/i915/i915_gem_gtt.h   |  4 ++--
 drivers/gpu/drm/i915/i915_gpu_error.c |  2 +-
 drivers/gpu/drm/i915/i915_vma.c   |  2 +-
 drivers/gpu/drm/i915/intel_display.c  |  2 +-
 drivers/gpu/drm/i915/intel_overlay.c  |  4 ++--
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  4 ++--
 drivers/gpu/drm/i915/selftests/mock_gtt.c |  3 ++-
 12 files changed, 35 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 028d00e61bad..601e5fee8957 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -336,7 +336,7 @@ int intel_gvt_load_firmware(struct intel_gvt *gvt);
 
 /* Aperture/GM space definitions for GVT device */
 #define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_size)
-#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base)
+#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable.start)
 
 #define gvt_ggtt_gm_sz(gvt)  (gvt->dev_priv->ggtt.base.total)
 #define gvt_ggtt_sz(gvt) \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e1bb0c8822aa..be29895a56f6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -728,7 +728,7 @@ static int i915_kick_out_firmware_fb(struct 
drm_i915_private *dev_priv)
if (!ap)
return -ENOMEM;
 
-   ap->ranges[0].base = ggtt->mappable_base;
+   ap->ranges[0].base = ggtt->mappable.start;
ap->ranges[0].size = ggtt->mappable_size;
 
primary =
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 05cc4f2df1bf..48c5a005a4b6 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1106,7 +1106,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
page_base += offset & PAGE_MASK;
}
 
-   if (gtt_user_read(>mappable, page_base, page_offset,
+   if (gtt_user_read(>mappable_io, page_base, page_offset,
  user_data, page_length)) {
ret = -EFAULT;
break;
@@ -1314,7 +1314,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
 * If the object is non-shmem backed, we retry again with the
 * path that handles page fault.
 */
-   if (ggtt_write(>mappable, page_base, page_offset,
+   if (ggtt_write(>mappable_io, page_base, page_offset,
   user_data, page_length)) {
ret = -EFAULT;
break;
@@ -1960,9 +1960,9 @@ int i915_gem_fault(struct vm_fault *vmf)
/* Finally, remap it using the new GTT offset */
ret = remap_io_mapping(area,
   area->vm_start + (vma->ggtt_view.partial.offset 
<< PAGE_SHIFT),
-  (ggtt->mappable_base + vma->node.start) >> 
PAGE_SHIFT,
+  (ggtt->mappable.start + vma->node.start) >> 
PAGE_SHIFT,
   min_t(u64, vma->size, area->vm_end - 
area->vm_start),
-  >mappable);
+  >mappable_io);
if (ret)
goto err_fence;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 8224abbb0f2d..da4db769e1e2 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1012,7 +1012,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj,
offset += page << PAGE_SHIFT;
}
 
-   vaddr = (void __force *)io_mapping_map_atomic_wc(>mappable,
+   vaddr = (void __force *)io_mapping_map_atomic_wc(>mappable_io,
 offset);
cache->page = page;
cache->vaddr = (unsigned long)vaddr;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 94faeaebf0d0..35d91cf07123 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2912,7 +2912,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private 
*dev_priv)
mutex_unlock(_priv->drm.struct_mutex);
 
arch_phys_wc_del(ggtt->mtrr);
-   io_mapping_fini(>mappable);
+   io_mapping_fini(>mappable_io);
 }
 
 static unsigned int 

[Intel-gfx] [PATCH 4/8] drm/i915: s/mappable_end/mappable_size/

[Matthew Auld]

In a later patch we introduce 'struct resource mappable', which means we
will have both mappable.end and mappable_end, both meaning different
things. Therefore to avoid any confusion prefer mappable_size for
mappable_end, since it is effectively the size of the resource.

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Paulo Zanoni 
---
 drivers/char/agp/intel-gtt.c  |  4 ++--
 drivers/gpu/drm/i915/gvt/gvt.h|  2 +-
 drivers/gpu/drm/i915/i915_debugfs.c   |  2 +-
 drivers/gpu/drm/i915/i915_drv.c   |  2 +-
 drivers/gpu/drm/i915/i915_gem.c   |  8 +++
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c   | 30 +--
 drivers/gpu/drm/i915/i915_gem_gtt.h   |  2 +-
 drivers/gpu/drm/i915/i915_vgpu.c  | 12 +--
 drivers/gpu/drm/i915/i915_vma.c   |  4 ++--
 drivers/gpu/drm/i915/intel_fbdev.c|  2 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  2 +-
 drivers/gpu/drm/i915/selftests/i915_vma.c | 22 ++--
 drivers/gpu/drm/i915/selftests/mock_gtt.c |  2 +-
 include/drm/intel-gtt.h   |  2 +-
 15 files changed, 49 insertions(+), 49 deletions(-)

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 9b6b6023193b..2a321ee2943a 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1424,12 +1424,12 @@ EXPORT_SYMBOL(intel_gmch_probe);
 void intel_gtt_get(u64 *gtt_total,
   u32 *stolen_size,
   phys_addr_t *mappable_base,
-  u64 *mappable_end)
+  u64 *mappable_size)
 {
*gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT;
*stolen_size = intel_private.stolen_size;
*mappable_base = intel_private.gma_bus_addr;
-   *mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT;
+   *mappable_size = intel_private.gtt_mappable_entries << PAGE_SHIFT;
 }
 EXPORT_SYMBOL(intel_gtt_get);
 
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 393066726993..028d00e61bad 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -335,7 +335,7 @@ int intel_gvt_load_firmware(struct intel_gvt *gvt);
 #define HOST_FENCE 4
 
 /* Aperture/GM space definitions for GVT device */
-#define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end)
+#define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_size)
 #define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base)
 
 #define gvt_ggtt_gm_sz(gvt)  (gvt->dev_priv->ggtt.base.total)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 28294470ae31..a05e2b92c02c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -523,7 +523,7 @@ static int i915_gem_object_info(struct seq_file *m, void 
*data)
   dpy_count, dpy_size);
 
seq_printf(m, "%llu [%llu] gtt total\n",
-  ggtt->base.total, ggtt->mappable_end);
+  ggtt->base.total, ggtt->mappable_size);
seq_printf(m, "Supported page sizes: %s\n",
   stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes,
buf, sizeof(buf)));
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0793a27e2b95..e1bb0c8822aa 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -729,7 +729,7 @@ static int i915_kick_out_firmware_fb(struct 
drm_i915_private *dev_priv)
return -ENOMEM;
 
ap->ranges[0].base = ggtt->mappable_base;
-   ap->ranges[0].size = ggtt->mappable_end;
+   ap->ranges[0].size = ggtt->mappable_size;
 
primary =
pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e03d6c2554e2..05cc4f2df1bf 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -66,7 +66,7 @@ insert_mappable_node(struct i915_ggtt *ggtt,
memset(node, 0, sizeof(*node));
return drm_mm_insert_node_in_range(>base.mm, node,
   size, 0, I915_COLOR_UNEVICTABLE,
-  0, ggtt->mappable_end,
+  0, ggtt->mappable_size,
   DRM_MM_INSERT_LOW);
 }
 
@@ -4158,7 +4158,7 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
 * the object in and out of the Global GTT and
 * waste a lot of cycles under the mutex.
 */
-   if (obj->base.size > 

[Intel-gfx] [PATCH 0/8] make stolen resource centric

[Matthew Auld]

Continuation of Paulo' stolen series[1], addressing the feedback from Joonas and
Chris.

[1] https://patchwork.freedesktop.org/series/30923/

Joonas Lahtinen (1):
  x86/early-quirks: Extend Intel graphics stolen memory placement to
64bit

Matthew Auld (7):
  x86/early-quirks: replace the magical increment start values
  drm/i915: nuke the duplicated stolen discovery
  drm/i915: s/mappable_end/mappable_size/
  drm/i915: make dsm struct resource centric
  drm/i915: make reserved struct resource centric
  drm/i915: make mappable struct resource centric
  drm/i915: prefer resource_size_t for everything stolen

 arch/x86/kernel/early-quirks.c|  86 ++--
 drivers/char/agp/intel-gtt.c  |  16 +--
 drivers/gpu/drm/i915/gvt/gvt.h|   4 +-
 drivers/gpu/drm/i915/i915_debugfs.c   |   2 +-
 drivers/gpu/drm/i915/i915_drv.c   |   4 +-
 drivers/gpu/drm/i915/i915_drv.h   |  26 +++-
 drivers/gpu/drm/i915/i915_gem.c   |  16 +--
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|   4 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c   | 103 +-
 drivers/gpu/drm/i915/i915_gem_gtt.h   |  12 +-
 drivers/gpu/drm/i915/i915_gem_stolen.c| 187 ++
 drivers/gpu/drm/i915/i915_gpu_error.c |   2 +-
 drivers/gpu/drm/i915/i915_vgpu.c  |  12 +-
 drivers/gpu/drm/i915/i915_vma.c   |   6 +-
 drivers/gpu/drm/i915/intel_display.c  |   2 +-
 drivers/gpu/drm/i915/intel_fbc.c  |  10 +-
 drivers/gpu/drm/i915/intel_fbdev.c|   2 +-
 drivers/gpu/drm/i915/intel_overlay.c  |   4 +-
 drivers/gpu/drm/i915/intel_pm.c   |  33 +++--
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |   6 +-
 drivers/gpu/drm/i915/selftests/i915_vma.c |  22 +--
 drivers/gpu/drm/i915/selftests/mock_gtt.c |   5 +-
 include/drm/i915_drm.h|   3 +
 include/drm/intel-gtt.h   |   4 +-
 24 files changed, 232 insertions(+), 339 deletions(-)

-- 
2.14.3

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Tidy ELSP port assignment

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Tidy ELSP port assignment
URL   : https://patchwork.freedesktop.org/series/34358/
State : success

== Summary ==

Test kms_flip:
Subgroup modeset-vs-vblank-race-interruptible:
fail   -> PASS   (shard-hsw) fdo#103060
Test gem_softpin:
Subgroup noreloc-s3:
pass   -> DMESG-WARN (shard-snb) fdo#102365
Test drv_selftest:
Subgroup mock_sanitycheck:
pass   -> DMESG-WARN (shard-snb) fdo#103717
Test drv_module_reload:
Subgroup basic-reload:
dmesg-warn -> PASS   (shard-snb) fdo#102848

fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#103717 https://bugs.freedesktop.org/show_bug.cgi?id=103717
fdo#102848 https://bugs.freedesktop.org/show_bug.cgi?id=102848

shard-hswtotal:2667 pass:1535 dwarn:1   dfail:0   fail:10  skip:1121 
time:9537s
shard-snbtotal:2667 pass:1309 dwarn:3   dfail:0   fail:13  skip:1342 
time:8059s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7279/shards.html
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[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [CI,1/3] drm/i915/guc: Tidy ELSP port assignment

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/3] drm/i915/guc: Tidy ELSP port assignment
URL   : https://patchwork.freedesktop.org/series/34360/
State : warning

== Summary ==

Test gem_busy:
Subgroup close-race:
pass   -> FAIL   (shard-snb) fdo#103829
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
pass   -> FAIL   (shard-snb) fdo#101623 +1
Test kms_flip:
Subgroup modeset-vs-vblank-race-interruptible:
fail   -> PASS   (shard-hsw) fdo#103060
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-a:
pass   -> SKIP   (shard-hsw)
Test drv_module_reload:
Subgroup basic-reload:
dmesg-warn -> PASS   (shard-snb) fdo#102848

fdo#103829 https://bugs.freedesktop.org/show_bug.cgi?id=103829
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#102848 https://bugs.freedesktop.org/show_bug.cgi?id=102848

shard-hswtotal:2667 pass:1534 dwarn:1   dfail:0   fail:10  skip:1122 
time:9547s
shard-snbtotal:2667 pass:1310 dwarn:1   dfail:0   fail:14  skip:1342 
time:8121s
Blacklisted hosts:
shard-apltotal:2667 pass:1661 dwarn:6   dfail:3   fail:42  skip:955 
time:12403s
shard-kbltotal:2549 pass:1633 dwarn:16  dfail:12  fail:37  skip:849 
time:10037s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7280/shards.html
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: Pass the correct msgs to gmbus_is_index_read()

[Ville Syrjälä]

On Fri, Nov 24, 2017 at 02:55:28PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 23, 2017 at 08:50:41PM +, Chris Wilson wrote:
> > Quoting Ville Syrjala (2017-11-23 19:41:55)
> > > From: Ville Syrjälä 
> > > 
> > > We're supposed to examine msgs[i] and msgs[i+1] to see if they
> > > form a pair suitable for an indexed transfer. But in reality
> > > we're examining msgs[0] and msgs[1]. Fix this.
> > > 
> > > Cc: sta...@vger.kernel.org
> > > Cc: Daniel Kurtz 
> > > Cc: Chris Wilson 
> > > Cc: Daniel Vetter 
> > > Cc: Sean Paul 
> > > Fixes: 56f9eac05489 ("drm/i915/intel_i2c: use INDEX cycles for i2c read 
> > > transactions")
> > > Signed-off-by: Ville Syrjälä 
> > > ---
> > >  drivers/gpu/drm/i915/intel_i2c.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_i2c.c 
> > > b/drivers/gpu/drm/i915/intel_i2c.c
> > > index eb5827110d8f..165375cbef2f 100644
> > > --- a/drivers/gpu/drm/i915/intel_i2c.c
> > > +++ b/drivers/gpu/drm/i915/intel_i2c.c
> > > @@ -484,7 +484,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct 
> > > i2c_msg *msgs, int num)
> > >  
> > > for (; i < num; i += inc) {
> > > inc = 1;
> > > -   if (gmbus_is_index_read(msgs, i, num)) {
> > > +   if (gmbus_is_index_read([i], i, num)) {
> > 
> > i is passed to gmbus_is_index_read() and used as an index into msgs. So
> > this should be accounted for right?
> 
> Doh. Yep, this patch is nonsense.

The two other patches pushed to dinq. Thanks catching my mistake with
this one.

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] igt: Remove Android support

[Patchwork]

== Series Details ==

Series: series starting with [1/2] igt: Remove Android support
URL   : https://patchwork.freedesktop.org/series/34365/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
c6577473df7117b7a6e030605df1e28cd0e55708 lib/igt_core: Move write_stderr out of 
LIBUNWIND ifdef

with latest DRM-Tip kernel build CI_DRM_3383
99e3e01d35c9 drm-tip: 2017y-11m-24d-13h-20m-57s UTC integration manifest

No testlist changes.

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:445s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:457s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:383s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:539s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:279s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:504s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:509s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:507s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:492s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:434s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:267s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:545s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:439s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:441s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:429s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:462s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:484s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:531s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:481s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:531s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:572s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:462s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:548s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:566s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:516s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:499s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:463s
fi-snb-2520m total:246  pass:212  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:430s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:603s
fi-cnl-y total:236  pass:211  dwarn:0   dfail:0   fail:0   skip:24 
fi-glk-dsi   total:289  pass:258  dwarn:0   dfail:0   fail:1   skip:30  
time:503s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_549/
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Re: [Intel-gfx] [PATCH i-g-t] tests/kms_vblank: Add test to ensure DRM_CAP_CRTC_IN_VBLANK_EVENT works correctly

[Daniel Vetter]

On Fri, Nov 24, 2017 at 04:35:10PM +0100, Maarten Lankhorst wrote:
> Op 24-11-17 om 16:03 schreef Daniel Vetter:
> > On Thu, Nov 23, 2017 at 01:26:14PM +0100, Maarten Lankhorst wrote:
> >> This was implemented correctly only on the atomic ioctl before, but
> >> it should really be working on all 3 ioctl's involved, so ensure we
> >> always set crtc_id correctly with a testcase.
> >>
> >> Signed-off-by: Maarten Lankhorst 
> > We seemt to completely lack these checks for the vblank ioctl and the
> > atomic ioctl too. Can you pls fill these gaps (probably best in kms_flip.c
> > and kms_atomic.c), too?
> Summary is a bit out of date, but I did add them in here. :)

Oh was blind.

> >> ---
> >>  tests/kms_vblank.c | 60 
> >> ++
> >>  1 file changed, 56 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/tests/kms_vblank.c b/tests/kms_vblank.c
> >> index 47fd10fb9078..004f0e6104ee 100644
> >> --- a/tests/kms_vblank.c
> >> +++ b/tests/kms_vblank.c
> >> @@ -121,7 +121,6 @@ static void run_test(data_t *data, int fd, void 
> >> (*testfunc)(data_t *, int, int))
> >>igt_display_t *display = >display;
> >>igt_output_t *output;
> >>enum pipe p;
> >> -  unsigned int valid_tests = 0;
> >>  
> >>for_each_pipe_with_valid_output(display, p, output) {
> >>igt_hang_t hang;
> >> @@ -170,11 +169,60 @@ static void run_test(data_t *data, int fd, void 
> >> (*testfunc)(data_t *, int, int))
> >>  
> >>/* cleanup what prepare_crtc() has done */
> >>cleanup_crtc(data, fd, output);
> >> -  valid_tests++;
> >>}
> >> +}
> >> +
> >> +static void crtc_id_subtest(data_t *data, int fd)
> >> +{
> >> +  igt_display_t *display = >display;
> >> +  igt_output_t *output;
> >> +  enum pipe p;
> >> +
> >> +  for_each_pipe_with_valid_output(display, p, output) {
> >> +  struct drm_event_vblank buf;
> >> +  const uint32_t pipe_id_flag = kmstest_get_vbl_flag(p);
> >> +  unsigned crtc_id, expected_crtc_id;
> >> +  uint64_t val;
> >> +  union drm_wait_vblank vbl;
> >> +
> >> +  crtc_id = display->pipes[p].crtc_id;
> >> +  if (drmGetCap(display->drm_fd, DRM_CAP_CRTC_IN_VBLANK_EVENT, 
> >> ) == 0)
> >> +  expected_crtc_id = crtc_id;
> >> +  else
> >> +  expected_crtc_id = 0;
> >> +
> >> +  data->pipe = p;
> >> +  prepare_crtc(data, fd, output);
> >> +
> >> +  memset(, 0, sizeof(vbl));
> >> +  vbl.request.type = DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT;
> >> +  vbl.request.type |= pipe_id_flag;
> >> +  vbl.request.sequence = 1;
> >> +  igt_assert_eq(wait_vblank(fd, ), 0);
> >> +
> >> +  igt_assert_eq(read(fd, , sizeof(buf)), sizeof(buf));
> >> +  igt_assert_eq(buf.crtc_id, expected_crtc_id);
> >> +
> >> +  do_or_die(drmModePageFlip(fd, crtc_id,
> >> +data->primary_fb.fb_id,
> >> +DRM_MODE_PAGE_FLIP_EVENT, NULL));
> >> +
> >> +  igt_assert_eq(read(fd, , sizeof(buf)), sizeof(buf));
> >> +  igt_assert_eq(buf.crtc_id, expected_crtc_id);
> >> +
> >> +  if (display->is_atomic) {
> >> +  igt_plane_t *primary = igt_output_get_plane(output, 0);
> >> +
> >> +  igt_plane_set_fb(primary, >primary_fb);
> >> +  igt_display_commit_atomic(display, 
> >> DRM_MODE_PAGE_FLIP_EVENT, NULL);
> >>  
> >> -  igt_require_f(valid_tests,
> >> -"no valid crtc/connector combinations found\n");
> >> +  igt_assert_eq(read(fd, , sizeof(buf)), sizeof(buf));
> >> +  igt_assert_eq(buf.crtc_id, expected_crtc_id);
> >> +  }
> >> +
> >> +  cleanup_crtc(data, fd, output);
> >> +  return;
> >> +  }
> >>  }
> >>  
> >>  static void accuracy(data_t *data, int fd, int nchildren)
> >> @@ -307,8 +355,12 @@ igt_main
> >>fd = drm_open_driver(DRIVER_ANY);
> >>kmstest_set_vt_graphics_mode();
> >>igt_display_init(, fd);
> >> +  igt_display_require_output();
> >>}
> >>  
> >> +  igt_subtest("crtc-id")
> >> +  crtc_id_subtest(, fd);
> > Either I'm stupid, or this doesn't apply on top of latest igt master.
> >
> > Either way I think taking the expensive modesets out of individual tests
> > would be good, so that when we run entire binaries in CI, we'll benefit
> > from some good speedup. Which is the plan, now that machines are a bit
> > more stable ...
> This is my intention of speeding up IGT as well, tests that don't care can use
> the inherited pipe/connector. It will speed up testing a lot by preventing 
> even
> performing a modeset.
> 
> I also plan to add a function to read the current state through 
> igt_display_read_hw_state(),
> then find an active pipe/connector, or just the first combination if nothing 
> 

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_vblank: Add test to ensure DRM_CAP_CRTC_IN_VBLANK_EVENT works correctly

[Maarten Lankhorst]

Op 24-11-17 om 16:03 schreef Daniel Vetter:
> On Thu, Nov 23, 2017 at 01:26:14PM +0100, Maarten Lankhorst wrote:
>> This was implemented correctly only on the atomic ioctl before, but
>> it should really be working on all 3 ioctl's involved, so ensure we
>> always set crtc_id correctly with a testcase.
>>
>> Signed-off-by: Maarten Lankhorst 
> We seemt to completely lack these checks for the vblank ioctl and the
> atomic ioctl too. Can you pls fill these gaps (probably best in kms_flip.c
> and kms_atomic.c), too?
Summary is a bit out of date, but I did add them in here. :)
>> ---
>>  tests/kms_vblank.c | 60 
>> ++
>>  1 file changed, 56 insertions(+), 4 deletions(-)
>>
>> diff --git a/tests/kms_vblank.c b/tests/kms_vblank.c
>> index 47fd10fb9078..004f0e6104ee 100644
>> --- a/tests/kms_vblank.c
>> +++ b/tests/kms_vblank.c
>> @@ -121,7 +121,6 @@ static void run_test(data_t *data, int fd, void 
>> (*testfunc)(data_t *, int, int))
>>  igt_display_t *display = >display;
>>  igt_output_t *output;
>>  enum pipe p;
>> -unsigned int valid_tests = 0;
>>  
>>  for_each_pipe_with_valid_output(display, p, output) {
>>  igt_hang_t hang;
>> @@ -170,11 +169,60 @@ static void run_test(data_t *data, int fd, void 
>> (*testfunc)(data_t *, int, int))
>>  
>>  /* cleanup what prepare_crtc() has done */
>>  cleanup_crtc(data, fd, output);
>> -valid_tests++;
>>  }
>> +}
>> +
>> +static void crtc_id_subtest(data_t *data, int fd)
>> +{
>> +igt_display_t *display = >display;
>> +igt_output_t *output;
>> +enum pipe p;
>> +
>> +for_each_pipe_with_valid_output(display, p, output) {
>> +struct drm_event_vblank buf;
>> +const uint32_t pipe_id_flag = kmstest_get_vbl_flag(p);
>> +unsigned crtc_id, expected_crtc_id;
>> +uint64_t val;
>> +union drm_wait_vblank vbl;
>> +
>> +crtc_id = display->pipes[p].crtc_id;
>> +if (drmGetCap(display->drm_fd, DRM_CAP_CRTC_IN_VBLANK_EVENT, 
>> ) == 0)
>> +expected_crtc_id = crtc_id;
>> +else
>> +expected_crtc_id = 0;
>> +
>> +data->pipe = p;
>> +prepare_crtc(data, fd, output);
>> +
>> +memset(, 0, sizeof(vbl));
>> +vbl.request.type = DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT;
>> +vbl.request.type |= pipe_id_flag;
>> +vbl.request.sequence = 1;
>> +igt_assert_eq(wait_vblank(fd, ), 0);
>> +
>> +igt_assert_eq(read(fd, , sizeof(buf)), sizeof(buf));
>> +igt_assert_eq(buf.crtc_id, expected_crtc_id);
>> +
>> +do_or_die(drmModePageFlip(fd, crtc_id,
>> +  data->primary_fb.fb_id,
>> +  DRM_MODE_PAGE_FLIP_EVENT, NULL));
>> +
>> +igt_assert_eq(read(fd, , sizeof(buf)), sizeof(buf));
>> +igt_assert_eq(buf.crtc_id, expected_crtc_id);
>> +
>> +if (display->is_atomic) {
>> +igt_plane_t *primary = igt_output_get_plane(output, 0);
>> +
>> +igt_plane_set_fb(primary, >primary_fb);
>> +igt_display_commit_atomic(display, 
>> DRM_MODE_PAGE_FLIP_EVENT, NULL);
>>  
>> -igt_require_f(valid_tests,
>> -  "no valid crtc/connector combinations found\n");
>> +igt_assert_eq(read(fd, , sizeof(buf)), sizeof(buf));
>> +igt_assert_eq(buf.crtc_id, expected_crtc_id);
>> +}
>> +
>> +cleanup_crtc(data, fd, output);
>> +return;
>> +}
>>  }
>>  
>>  static void accuracy(data_t *data, int fd, int nchildren)
>> @@ -307,8 +355,12 @@ igt_main
>>  fd = drm_open_driver(DRIVER_ANY);
>>  kmstest_set_vt_graphics_mode();
>>  igt_display_init(, fd);
>> +igt_display_require_output();
>>  }
>>  
>> +igt_subtest("crtc-id")
>> +crtc_id_subtest(, fd);
> Either I'm stupid, or this doesn't apply on top of latest igt master.
>
> Either way I think taking the expensive modesets out of individual tests
> would be good, so that when we run entire binaries in CI, we'll benefit
> from some good speedup. Which is the plan, now that machines are a bit
> more stable ...
This is my intention of speeding up IGT as well, tests that don't care can use
the inherited pipe/connector. It will speed up testing a lot by preventing even
performing a modeset.

I also plan to add a function to read the current state through 
igt_display_read_hw_state(),
then find an active pipe/connector, or just the first combination if nothing 
matches.
And after the end of the test keep it alive without disabling the crtc's, only 
removing framebuffers,
which no longer disables the crtc's on i915. :-)

~Maarten

Re: [Intel-gfx] [PATCH 15/15] drm: Don't pass clip to drm_atomic_helper_check_plane_state()

[Liviu Dudau]

On Fri, Nov 24, 2017 at 04:08:28PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 24, 2017 at 11:59:45AM +, Liviu Dudau wrote:
> > On Thu, Nov 23, 2017 at 09:05:02PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä 
> > 
> > Hi Ville,
> > 
> > > 
> > > Move the plane clip rectangle handling into
> > > drm_atomic_helper_check_plane_state(). Drivers no longer
> > > have to worry about such mundane details.
> > 
> > This is quite an important patch and I dare say the essence of your
> > series, right? Yet very few people got Cc-ed on it (1 AFAICT) and it
> > touches quite a few drivers.
> 
> It has no functional changes, so forgetting to plaster it with Ccs
> doesn't seem all that dangerous. All the (potentially) functional
> changes were in the prep patches which had Ccs, as did the cover
> letter. And maintainers should read the ml anyway ;)

Maintainers don't maintain the functionality, they maintain the source
code. They fix conflicts and order patches. On that line, not Cc-ing
maintainers when you change the code of the drivers they maintain makes
their lives all more ... "entertaining".

And I would argue that the patch does introduce functional changes, as
it removes the clip rectangle from drm_atomic_helper_check_plane_state()'s
list of parameters. It does change all the users of it, too, I agree, but
not for people that have drivers not yet upstreamed (and they start to wonder
how one driver compiles and other fails when they were supposed to have the
same code inside :) )

Regards,
Liviu

> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 

| I would like to |
| fix the world,  |
| but they're not |
| giving me the   |
 \ source code!  /
  ---
¯\_(ツ)_/¯
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Expose the busyspin durations for i915_wait_request

[Patchwork]

== Series Details ==

Series: drm/i915: Expose the busyspin durations for i915_wait_request
URL   : https://patchwork.freedesktop.org/series/34364/
State : success

== Summary ==

Series 34364v1 drm/i915: Expose the busyspin durations for i915_wait_request
https://patchwork.freedesktop.org/api/1.0/series/34364/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:445s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:461s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:380s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:540s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:276s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:505s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:507s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:499s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:493s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:427s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:267s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:539s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:430s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:435s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:428s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:463s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:480s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:529s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:478s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:531s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:563s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:462s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:545s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:560s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:523s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:505s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:459s
fi-snb-2520m total:246  pass:212  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:420s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:592s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:551s
fi-glk-dsi   total:289  pass:132  dwarn:0   dfail:10  fail:2   skip:145 
time:309s

99e3e01d35c95de2392d7f5796f3086cb13b441a drm-tip: 2017y-11m-24d-13h-20m-57s UTC 
integration manifest
45896519b9fe drm/i915: Expose the busyspin durations for i915_wait_request

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7282/
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[Intel-gfx] [PATCH i-g-t 2/2] Revert "lib/igt_aux: Make procps optional"

[Arkadiusz Hiler]

This reverts commit d7d3f4e87b827152f00bdf89a67871736672b492
and gets rid of the config option from the meson.build.

It was needed only for the Android support.

Signed-off-by: Arkadiusz Hiler 
---
 configure.ac  |  6 +-
 lib/igt_aux.c | 35 +++
 meson.build   |  5 +
 3 files changed, 5 insertions(+), 41 deletions(-)

diff --git a/configure.ac b/configure.ac
index 1ac2e8e8..84c6e646 100644
--- a/configure.ac
+++ b/configure.ac
@@ -123,11 +123,7 @@ AC_SUBST(ASSEMBLER_WARN_CFLAGS)
 PKG_CHECK_MODULES(DRM, [libdrm >= 2.4.82])
 PKG_CHECK_MODULES(PCIACCESS, [pciaccess >= 0.10])
 PKG_CHECK_MODULES(KMOD, [libkmod])
-PKG_CHECK_MODULES(PROCPS, [libprocps], [procps=yes], [procps=no])
-AM_CONDITIONAL(HAVE_PROCPS, [test "x$procps" = xyes])
-if test x"$procps" = xyes; then
-   AC_DEFINE(HAVE_PROCPS,1,[Enable process managment without shelling out])
-fi
+PKG_CHECK_MODULES(PROCPS, [libprocps])
 PKG_CHECK_MODULES(VALGRIND, [valgrind], [have_valgrind=yes], 
[have_valgrind=no])
 
 if test x$have_valgrind = xyes; then
diff --git a/lib/igt_aux.c b/lib/igt_aux.c
index a41ae2f1..e2424109 100644
--- a/lib/igt_aux.c
+++ b/lib/igt_aux.c
@@ -48,7 +48,9 @@
 #include 
 #include 
 #include 
-#include 
+
+#include 
+
 #include "drmtest.h"
 #include "i915_drm.h"
 #include "intel_chipset.h"
@@ -68,10 +70,6 @@
 #include/* for dirname() */
 #endif
 
-#ifdef HAVE_PROCPS
-#include 
-#endif
-
 /**
  * SECTION:igt_aux
  * @short_description: Auxiliary libraries and support functions
@@ -1296,7 +1294,6 @@ void igt_set_module_param_int(const char *name, int val)
  * This function sends the signal @sig for a process found in process table
  * with name @comm.
  */
-#ifdef HAVE_PROCPS
 int igt_terminate_process(int sig, const char *comm)
 {
PROCTAB *proc;
@@ -1321,19 +1318,7 @@ int igt_terminate_process(int sig, const char *comm)
closeproc(proc);
return err;
 }
-#else
-#warning "No procps, using naive implementation of igt_terminate_process"
 
-int igt_terminate_process(int sig, const char *comm)
-{
-   char pkill_cmd[NAME_MAX];
-
-   snprintf(pkill_cmd, sizeof(pkill_cmd), "pkill -x -%d %s", sig, comm);
-   return system(pkill_cmd);
-}
-#endif
-
-#ifdef HAVE_PROCPS
 struct pinfo {
pid_t pid;
const char *comm;
@@ -1515,7 +1500,6 @@ __igt_lsof(const char *dir)
 
closeproc(proc);
 }
-#endif
 
 /**
  * igt_lsof: Lists information about files opened by processes.
@@ -1524,7 +1508,6 @@ __igt_lsof(const char *dir)
  * This function mimics (a restrictive form of) lsof(8), but also shows
  * information about opened fds.
  */
-#ifdef HAVE_PROCPS
 void
 igt_lsof(const char *dpath)
 {
@@ -1549,18 +1532,6 @@ igt_lsof(const char *dpath)
 
free(sanitized);
 }
-#else
-#warning "No procps, using naive implementation of igt_lsof"
-
-void
-igt_lsof(const char *dpath)
-{
-   char lsof_cmd[NAME_MAX];
-
-   snprintf(lsof_cmd, sizeof(lsof_cmd), "lsof +d %s", dpath);
-   system(lsof_cmd);
-}
-#endif
 
 static struct igt_siglatency {
timer_t timer;
diff --git a/meson.build b/meson.build
index 2361866b..8e01b05d 100644
--- a/meson.build
+++ b/meson.build
@@ -37,10 +37,7 @@ libdrm_amdgpu = dependency('libdrm_amdgpu', required : false)
 
 pciaccess = dependency('pciaccess', version : '>=0.10')
 libkmod = dependency('libkmod')
-libprocps = dependency('libprocps', required : false)
-if libprocps.found()
-   config.set('HAVE_PROCPS', 1)
-endif
+libprocps = dependency('libprocps', required : true)
 
 valgrind = dependency('valgrind', required : false)
 if valgrind.found()
-- 
2.13.6

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[Intel-gfx] [PATCH i-g-t 1/2] igt: Remove Android support

[Arkadiusz Hiler]

This patch gets rid of the Android support, deleting all the hacks and
moving code around to the places it belongs.

Android build is not really maintained properly and rots rather fast.
With recent push for Meson here and Android going for Soong it will only
accelerate.

It's a good time to drop the illusion of providing any support.

Cc: Daniel Vetter 
Cc: Kalyan Kondapally 
Cc: Petri Latvala 
Cc: Radoslaw Szwichtenberg 
Signed-off-by: Arkadiusz Hiler 
---
 Android.mk   |  4 --
 assembler/ralloc.c   |  5 ---
 benchmarks/Android.mk| 46 -
 benchmarks/gem_syslatency.c  |  2 -
 lib/Android.mk   | 53 
 lib/drmtest.h| 16 
 lib/igt_aux.c| 95 
 lib/igt_aux.h|  5 ---
 lib/igt_core.c   | 68 ---
 lib/igt_debugfs.c| 25 +---
 lib/igt_fb.h |  7 
 lib/igt_kmod.h   |  4 --
 lib/igt_kms.c| 89 +
 lib/tests/Android.mk | 41 ---
 tests/Android.mk | 83 --
 tests/core_get_client_auth.c |  4 +-
 tests/gem_exec_nop.c |  4 --
 tools/Android.mk | 82 --
 18 files changed, 91 insertions(+), 542 deletions(-)
 delete mode 100644 Android.mk
 delete mode 100644 benchmarks/Android.mk
 delete mode 100644 lib/Android.mk
 delete mode 100644 lib/tests/Android.mk
 delete mode 100644 tests/Android.mk
 delete mode 100644 tools/Android.mk

diff --git a/Android.mk b/Android.mk
deleted file mode 100644
index 3690fc5a..
--- a/Android.mk
+++ /dev/null
@@ -1,4 +0,0 @@
-HAVE_LIBDRM_INTEL := true
-
-include $(call all-named-subdir-makefiles, lib tests tools benchmarks)
-
diff --git a/assembler/ralloc.c b/assembler/ralloc.c
index 59e71c48..69c1da4d 100644
--- a/assembler/ralloc.c
+++ b/assembler/ralloc.c
@@ -28,11 +28,6 @@
 #include 
 #include 
 
-/* Android defines SIZE_MAX in limits.h, instead of the standard stdint.h */
-#ifdef ANDROID
-#include 
-#endif
-
 /* Some versions of MinGW are missing _vscprintf's declaration, although they
  * still provide the symbol in the import library. */
 #ifdef __MINGW32__
diff --git a/benchmarks/Android.mk b/benchmarks/Android.mk
deleted file mode 100644
index 4ea275c4..
--- a/benchmarks/Android.mk
+++ /dev/null
@@ -1,46 +0,0 @@
-LOCAL_PATH := $(call my-dir)
-
-include $(LOCAL_PATH)/Makefile.sources
-IGT_LOCAL_C_INCLUDES = $(LOCAL_PATH)/../lib
-
-##
-
-define add_benchmark
-include $(CLEAR_VARS)
-
-LOCAL_SRC_FILES := $1.c
-
-LOCAL_C_INCLUDES = ${IGT_LOCAL_C_INCLUDES} \
-   $(LOCAL_PATH)/../lib/stubs/drm/
-LOCAL_CFLAGS += -DHAVE_STRUCT_SYSINFO_TOTALRAM
-LOCAL_CFLAGS += -DANDROID -UNDEBUG -include "check-ndebug.h"
-LOCAL_CFLAGS += -std=gnu99
-# FIXME: drop once Bionic correctly annotates "noreturn" on pthread_exit
-LOCAL_CFLAGS += -Wno-error=return-type
-# Excessive complaining for established cases. Rely on the Linux version 
warnings.
-LOCAL_CFLAGS += -Wno-sign-compare
-LOCAL_LDFLAGS += -lkmod
-
-LOCAL_MODULE := $1_benchmark
-LOCAL_MODULE_TAGS := optional
-LOCAL_MODULE_PATH := 
$(TARGET_OUT_VENDOR)/intel/validation/core/igt/benchmarks
-
-LOCAL_STATIC_LIBRARIES := libintel_gpu_tools
-
-LOCAL_SHARED_LIBRARIES := libpciaccess  \
-  libkmod   \
-  libdrm\
-  libdrm_intel
-
-include $(BUILD_EXECUTABLE)
-endef
-
-##
-
-benchmark_list := $(benchmarks_prog_list)
-
-ifeq ($(HAVE_LIBDRM_INTEL),true)
-benchmark_list += $(LIBDRM_INTEL_BENCHMARKS)
-endif
-
-$(foreach item,$(benchmark_list),$(eval $(call add_benchmark,$(item
diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c
index 580edc5f..de59eaf8 100644
--- a/benchmarks/gem_syslatency.c
+++ b/benchmarks/gem_syslatency.c
@@ -219,7 +219,6 @@ static void *sys_thp_alloc(void *arg)
 static void bind_cpu(pthread_attr_t *attr, int cpu)
 {
 #ifdef __USE_GNU
-#ifndef ANDROID
cpu_set_t mask;
 
if (cpu == -1)
@@ -230,7 +229,6 @@ static void bind_cpu(pthread_attr_t *attr, int cpu)
 
pthread_attr_setaffinity_np(attr, sizeof(mask), );
 #endif
-#endif
 }
 
 static void rtprio(pthread_attr_t *attr, int prio)
diff --git a/lib/Android.mk b/lib/Android.mk
deleted file mode 100644
index 31f88be7..
--- a/lib/Android.mk
+++ /dev/null
@@ -1,53 +0,0 @@
-LOCAL_PATH := $(call my-dir)
-
-GPU_TOOLS_PATH := $(LOCAL_PATH)/..
-IGT_LIB_PATH := $(LOCAL_PATH)
-
-# FIXME: autogenerate this info #
-$(GPU_TOOLS_PATH)/config.h:
- 

Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Advance over port[0] if set and not preempting

[Michał Winiarski]

On Fri, Nov 24, 2017 at 01:37:44PM +, Chris Wilson wrote:
> Our execlist emulation is intended to only use a maximum of 2 ports per
> engine, so as to not overflow the wq. (By knowing the limits, we can
> avoid having to handle the wq exhaustion.) However, upon adding
> preemption, we lost the skip over the first port if set for the
> non-preemption path. Restore it.
> 
> Reported-by: Mika Kuoppala 
> Fixes: c41937fd994a ("drm/i915/guc: Preemption! With GuC")
> Signed-off-by: Chris Wilson 
> Cc: Michał Winiarski 
> Cc: Mika Kuoppala 

Reviewed-by: Michał Winiarski 

-Michał

> ---
>  drivers/gpu/drm/i915/intel_guc_submission.c | 29 
> -
>  1 file changed, 16 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c 
> b/drivers/gpu/drm/i915/intel_guc_submission.c
> index cbf5a96f5806..70e64bdb73dd 100644
> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> @@ -743,23 +743,26 @@ static void guc_dequeue(struct intel_engine_cs *engine)
>   if (!rb)
>   goto unlock;
>  
> - if (HAS_LOGICAL_RING_PREEMPTION(engine->i915) && port_isset(port)) {
> - struct guc_preempt_work *preempt_work =
> - >i915->guc.preempt_work[engine->id];
> -
> - if (rb_entry(rb, struct i915_priolist, node)->priority >
> - max(port_request(port)->priotree.priority, 0)) {
> - execlists_set_active(execlists,
> -  EXECLISTS_ACTIVE_PREEMPT);
> - queue_work(engine->i915->guc.preempt_wq,
> -_work->work);
> - goto unlock;
> - } else if (port_isset(last_port)) {
> - goto unlock;
> + if (port_isset(port)) {
> + if (HAS_LOGICAL_RING_PREEMPTION(engine->i915)) {
> + struct guc_preempt_work *preempt_work =
> + >i915->guc.preempt_work[engine->id];
> +
> + if (rb_entry(rb, struct i915_priolist, node)->priority >
> + max(port_request(port)->priotree.priority, 0)) {
> + execlists_set_active(execlists,
> +  EXECLISTS_ACTIVE_PREEMPT);
> + queue_work(engine->i915->guc.preempt_wq,
> +_work->work);
> + goto unlock;
> + }
>   }
>  
>   port++;
> + if (port_isset(port))
> + goto unlock;
>   }
> + GEM_BUG_ON(port_isset(port));
>  
>   do {
>   struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
> -- 
> 2.15.0
> 
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Re: [Intel-gfx] [PATCH] MAINTAINERS: Remove Jani as drm-misc co-maintainer

[Daniel Vetter]

On Thu, Nov 23, 2017 at 02:13:08PM +0200, Jani Nikula wrote:
> I'm juggling too many things, and drm-misc maintenance is one that I
> keep dropping on the floor. Admit reality and remove myself as
> maintainer. This still leaves us with a nice team of three who are
> actually doing the drm-misc work, while I focus on drm-intel.

Thanks a lot for the work done!

> Cc: Daniel Vetter 
> Cc: Gustavo Padovan 
> Cc: Sean Paul 
> Cc: Dave Airlie 
> Signed-off-by: Jani Nikula 

Acked-by: Daniel Vetter 

Sean is getting stuffed with turkey and Gustova is on vacation, so will
probably take until next week for those acks to roll in.

Thanks, Daniel

> ---
>  MAINTAINERS | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 9a9d3fdc55ef..fb8820458a7f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -4490,7 +4490,6 @@ F:  include/linux/vga*
>  
>  DRM DRIVERS AND MISC GPU PATCHES
>  M:   Daniel Vetter 
> -M:   Jani Nikula 
>  M:   Gustavo Padovan 
>  M:   Sean Paul 
>  W:   https://01.org/linuxgraphics/gfx-docs/maintainer-tools/drm-misc.html
> -- 
> 2.11.0
> 
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH] drm/i915: Disable THP until we have a read BW W/A

[Chris Wilson]

Quoting Chris Wilson (2017-11-24 12:12:33)
> Quoting Joonas Lahtinen (2017-11-24 11:27:50)
> > We seem to be missing some W/A for 2M pages and are getting
> > a hit on raw read bandwidths (even 30%) even though the write
> > bandwidths improve (even 10%).
> > 
> > For now, disable THP, which is our only practical source of
> > 2M pages until we have a W/A for the issue.
> > 
> > Reported-by: Valtteri Rantala 
> > Fixes: b901bb89324a ("drm/i915/gemfs: enable THP")
> > Signed-off-by: Joonas Lahtinen 
> > Cc: Matthew Auld 
> > Cc: Chris Wilson 
> > Cc: Jani Nikula 
> > Cc: Rodrigo Vivi 
> > Cc: Valtteri Rantala 
> > Cc: Eero Tamminen 
> 
> I don't have much to say, a lot of unknowns and you've already concisely
> summed up everything that is known.
> Reviewed-by: Chris Wilson 

Bah, what works on the cmdline isn't allowed as an option!
Apparently, s/deny/never/
-Chris
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Re: [Intel-gfx] [PATCH i-g-t] tests/kms_vblank: Add test to ensure DRM_CAP_CRTC_IN_VBLANK_EVENT works correctly

[Daniel Vetter]

On Thu, Nov 23, 2017 at 01:26:14PM +0100, Maarten Lankhorst wrote:
> This was implemented correctly only on the atomic ioctl before, but
> it should really be working on all 3 ioctl's involved, so ensure we
> always set crtc_id correctly with a testcase.
> 
> Signed-off-by: Maarten Lankhorst 

We seemt to completely lack these checks for the vblank ioctl and the
atomic ioctl too. Can you pls fill these gaps (probably best in kms_flip.c
and kms_atomic.c), too?

> ---
>  tests/kms_vblank.c | 60 
> ++
>  1 file changed, 56 insertions(+), 4 deletions(-)
> 
> diff --git a/tests/kms_vblank.c b/tests/kms_vblank.c
> index 47fd10fb9078..004f0e6104ee 100644
> --- a/tests/kms_vblank.c
> +++ b/tests/kms_vblank.c
> @@ -121,7 +121,6 @@ static void run_test(data_t *data, int fd, void 
> (*testfunc)(data_t *, int, int))
>   igt_display_t *display = >display;
>   igt_output_t *output;
>   enum pipe p;
> - unsigned int valid_tests = 0;
>  
>   for_each_pipe_with_valid_output(display, p, output) {
>   igt_hang_t hang;
> @@ -170,11 +169,60 @@ static void run_test(data_t *data, int fd, void 
> (*testfunc)(data_t *, int, int))
>  
>   /* cleanup what prepare_crtc() has done */
>   cleanup_crtc(data, fd, output);
> - valid_tests++;
>   }
> +}
> +
> +static void crtc_id_subtest(data_t *data, int fd)
> +{
> + igt_display_t *display = >display;
> + igt_output_t *output;
> + enum pipe p;
> +
> + for_each_pipe_with_valid_output(display, p, output) {
> + struct drm_event_vblank buf;
> + const uint32_t pipe_id_flag = kmstest_get_vbl_flag(p);
> + unsigned crtc_id, expected_crtc_id;
> + uint64_t val;
> + union drm_wait_vblank vbl;
> +
> + crtc_id = display->pipes[p].crtc_id;
> + if (drmGetCap(display->drm_fd, DRM_CAP_CRTC_IN_VBLANK_EVENT, 
> ) == 0)
> + expected_crtc_id = crtc_id;
> + else
> + expected_crtc_id = 0;
> +
> + data->pipe = p;
> + prepare_crtc(data, fd, output);
> +
> + memset(, 0, sizeof(vbl));
> + vbl.request.type = DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT;
> + vbl.request.type |= pipe_id_flag;
> + vbl.request.sequence = 1;
> + igt_assert_eq(wait_vblank(fd, ), 0);
> +
> + igt_assert_eq(read(fd, , sizeof(buf)), sizeof(buf));
> + igt_assert_eq(buf.crtc_id, expected_crtc_id);
> +
> + do_or_die(drmModePageFlip(fd, crtc_id,
> +   data->primary_fb.fb_id,
> +   DRM_MODE_PAGE_FLIP_EVENT, NULL));
> +
> + igt_assert_eq(read(fd, , sizeof(buf)), sizeof(buf));
> + igt_assert_eq(buf.crtc_id, expected_crtc_id);
> +
> + if (display->is_atomic) {
> + igt_plane_t *primary = igt_output_get_plane(output, 0);
> +
> + igt_plane_set_fb(primary, >primary_fb);
> + igt_display_commit_atomic(display, 
> DRM_MODE_PAGE_FLIP_EVENT, NULL);
>  
> - igt_require_f(valid_tests,
> -   "no valid crtc/connector combinations found\n");
> + igt_assert_eq(read(fd, , sizeof(buf)), sizeof(buf));
> + igt_assert_eq(buf.crtc_id, expected_crtc_id);
> + }
> +
> + cleanup_crtc(data, fd, output);
> + return;
> + }
>  }
>  
>  static void accuracy(data_t *data, int fd, int nchildren)
> @@ -307,8 +355,12 @@ igt_main
>   fd = drm_open_driver(DRIVER_ANY);
>   kmstest_set_vt_graphics_mode();
>   igt_display_init(, fd);
> + igt_display_require_output();
>   }
>  
> + igt_subtest("crtc-id")
> + crtc_id_subtest(, fd);

Either I'm stupid, or this doesn't apply on top of latest igt master.

Either way I think taking the expensive modesets out of individual tests
would be good, so that when we run entire binaries in CI, we'll benefit
from some good speedup. Which is the plan, now that machines are a bit
more stable ...
-Daniel
> +
>   for (f = funcs; f->name; f++) {
>   for (m = modes; m->name; m++) {
>   if (m->flags & ~f->valid)
> -- 
> 2.15.0
> 
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Disable THP until we have a read BW W/A

[Patchwork]

== Series Details ==

Series: drm/i915: Disable THP until we have a read BW W/A
URL   : https://patchwork.freedesktop.org/series/34355/
State : warning

== Summary ==

Warning: bzip CI_DRM_3381/shard-glkb6/results8.json.bz2 wasn't in correct JSON 
format
Test perf:
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
pass   -> FAIL   (shard-snb) fdo#101623
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test drv_selftest:
Subgroup mock_sanitycheck:
pass   -> DMESG-WARN (shard-snb) fdo#103717
Subgroup mock_breadcrumbs:
pass   -> DMESG-WARN (shard-snb)
pass   -> DMESG-WARN (shard-hsw)
Subgroup mock_requests:
pass   -> DMESG-WARN (shard-snb)
pass   -> DMESG-WARN (shard-hsw)
Subgroup mock_objects:
pass   -> DMESG-WARN (shard-snb)
pass   -> DMESG-WARN (shard-hsw)
Subgroup mock_dmabuf:
pass   -> DMESG-WARN (shard-snb)
pass   -> DMESG-WARN (shard-hsw)
Subgroup mock_vma:
pass   -> DMESG-WARN (shard-snb)
pass   -> DMESG-WARN (shard-hsw)
Subgroup mock_evict:
pass   -> DMESG-WARN (shard-snb)
pass   -> DMESG-WARN (shard-hsw)
Subgroup mock_gtt:
pass   -> DMESG-WARN (shard-snb)
pass   -> DMESG-WARN (shard-hsw)
Subgroup mock_hugepages:
pass   -> DMESG-WARN (shard-snb)
pass   -> DMESG-WARN (shard-hsw)
Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
fail   -> PASS   (shard-hsw) fdo#100368

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#103717 https://bugs.freedesktop.org/show_bug.cgi?id=103717
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368

shard-hswtotal:2667 pass:1527 dwarn:9   dfail:0   fail:10  skip:1121 
time:9590s
shard-snbtotal:2667 pass:1301 dwarn:10  dfail:0   fail:14  skip:1342 
time:8123s
Blacklisted hosts:
shard-apltotal:2667 pass:1680 dwarn:9   dfail:0   fail:23  skip:955 
time:13587s
shard-kbltotal:2667 pass:1685 dwarn:116 dfail:6   fail:22  skip:838 
time:10901s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7278/shards.html
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[Intel-gfx] [PATCH] drm/i915: Expose the busyspin durations for i915_wait_request

[Chris Wilson]

An interesting discussion regarding "hybrid interrupt polling" for NVMe
came to the conclusion that the ideal busyspin before sleeping was half
of the expected request latency (and better if it was already halfway
through that request). This suggested that we too should look again at
our tradeoff between spinning and waiting. Currently, our spin simply
tries to hide the cost of enabling the interrupt, which is good to avoid
penalising nop requests (i.e. test throughput) and not much else.
Studying real world workloads suggests that a spin of upto 500us can
dramatically boost performance, but the suggestion is that this is not
from avoiding interrupt latency per-se, but from secondary effects of
sleeping such as allowing the CPU reduce cstate and context switch away.

v2: Expose the spin setting via Kconfig options for easier adjustment
and testing.

Suggested-by: Sagar Kamble 
Signed-off-by: Chris Wilson 
Cc: Sagar Kamble 
Cc: Eero Tamminen 
Cc: Tvrtko Ursulin 
Cc: Ben Widawsky 
Cc: Joonas Lahtinen 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/Kconfig|  6 ++
 drivers/gpu/drm/i915/Kconfig.profile| 23 +++
 drivers/gpu/drm/i915/i915_gem_request.c | 28 
 3 files changed, 53 insertions(+), 4 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/Kconfig.profile

diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index dfd95889f4b7..0553c3176109 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -131,3 +131,9 @@ depends on DRM_I915
 depends on EXPERT
 source drivers/gpu/drm/i915/Kconfig.debug
 endmenu
+
+menu "drm/i915 Profile Guided Optimisation"
+depends on DRM_I915
+depends on EXPERT
+source drivers/gpu/drm/i915/Kconfig.profile
+endmenu
diff --git a/drivers/gpu/drm/i915/Kconfig.profile 
b/drivers/gpu/drm/i915/Kconfig.profile
new file mode 100644
index ..c8fe5754466c
--- /dev/null
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -0,0 +1,23 @@
+config DRM_I915_SPIN_REQUEST_IRQ
+   int
+   default 5 # microseconds
+   help
+ Before sleeping waiting for a request (GPU operation) to complete,
+ we may spend some time polling for its completion. As the IRQ may
+ take a non-negligible time to setup, we do a short spin first to
+ check if the request will complete quickly.
+
+ May be 0 to disable the initial spin.
+
+config DRM_I915_SPIN_REQUEST_CS
+   int
+   default 20 # microseconds
+   help
+ After sleeping for a request (GPU operation) to complete, we will
+ be woken up on the completion of every request prior to the one
+ being waited on. For very short requests, going back to sleep and
+ be woken up again may add considerably to the wakeup latency. To
+ avoid incurring extra latency from the scheduler, we may choose to
+ spin prior to sleeping again.
+
+ May be 0 to disable spinning after being woken.
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index a90bdd26571f..7ac72a0a949c 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -1198,8 +1198,21 @@ long i915_wait_request(struct drm_i915_gem_request *req,
GEM_BUG_ON(!intel_wait_has_seqno());
GEM_BUG_ON(!i915_sw_fence_signaled(>submit));
 
-   /* Optimistic short spin before touching IRQs */
-   if (__i915_spin_request(req, wait.seqno, state, 5))
+   /* Optimistic spin before touching IRQs.
+*
+* We may use a rather large value here to offset the penalty of
+* switching away from the active task. Frequently, the client will
+* wait upon an old swapbuffer to throttle itself to remain within a
+* frame of the gpu. If the client is running in lockstep with the gpu,
+* then it should not be waiting long at all, and a sleep now will incur
+* extra scheduler latency in producing the next frame. So we sleep
+* for longer to try and keep the client running.
+*
+* We need ~5us to enable the irq, ~20us to hide a context switch.
+*/
+   if (CONFIG_DRM_I915_SPIN_REQUEST_IRQ &&
+   __i915_spin_request(req, wait.seqno, state,
+   CONFIG_DRM_I915_SPIN_REQUEST_IRQ))
goto complete;
 
set_current_state(state);
@@ -1255,8 +1268,15 @@ long i915_wait_request(struct drm_i915_gem_request *req,
__i915_wait_request_check_and_reset(req))
continue;
 
-   /* Only spin if we know the GPU is processing this request */
-   if (__i915_spin_request(req, wait.seqno, state, 2))
+   /*
+

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Move engine->needs_cmd_parser to engine->flags

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Move engine->needs_cmd_parser to 
engine->flags
URL   : https://patchwork.freedesktop.org/series/34354/
State : success

== Summary ==

Warning: bzip CI_DRM_3381/shard-glkb6/results8.json.bz2 wasn't in correct JSON 
format
Test kms_flip:
Subgroup dpms-vs-vblank-race:
pass   -> FAIL   (shard-hsw) fdo#103060
Subgroup plain-flip-fb-recreate-interruptible:
fail   -> PASS   (shard-hsw) fdo#100368
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
fail   -> PASS   (shard-snb) fdo#101623

fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623

shard-hswtotal:2667 pass:1534 dwarn:1   dfail:0   fail:11  skip:1121 
time:9510s
shard-snbtotal:2667 pass:1312 dwarn:1   dfail:0   fail:12  skip:1342 
time:8135s
Blacklisted hosts:
shard-apltotal:2667 pass:1690 dwarn:2   dfail:1   fail:20  skip:954 
time:13477s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7277/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for lib/igt_core: Move write_stderr out of LIBUNWIND ifdef

[Patchwork]

== Series Details ==

Series: lib/igt_core: Move write_stderr out of LIBUNWIND ifdef
URL   : https://patchwork.freedesktop.org/series/34349/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
2a1c1c099113022f091f9e9585be88c6c9cefec5 igt/perf_pmu: Recalibrate interrupt 
loop.

with latest DRM-Tip kernel build CI_DRM_3383
99e3e01d35c9 drm-tip: 2017y-11m-24d-13h-20m-57s UTC integration manifest

No testlist changes.

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:444s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:455s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:387s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:545s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:280s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:508s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:512s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:505s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:492s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:427s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:543s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:431s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:442s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:434s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:484s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:468s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:480s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:533s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:475s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:540s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:570s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:457s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:546s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:568s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:498s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:469s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:567s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:423s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:605s
fi-cnl-y total:289  pass:261  dwarn:1   dfail:0   fail:0   skip:27  
time:557s
fi-glk-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:492s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_548/
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Rename i915_guc_reg.h to intel_guc_reg.h (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Rename i915_guc_reg.h to intel_guc_reg.h (rev2)
URL   : https://patchwork.freedesktop.org/series/34319/
State : success

== Summary ==

Warning: bzip CI_DRM_3381/shard-glkb6/results8.json.bz2 wasn't in correct JSON 
format
Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
fail   -> PASS   (shard-hsw) fdo#100368
Subgroup modeset-vs-vblank-race:
pass   -> FAIL   (shard-hsw) fdo#103060
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
fail   -> PASS   (shard-snb) fdo#101623

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623

shard-hswtotal:2667 pass:1534 dwarn:1   dfail:0   fail:11  skip:1121 
time:9514s
shard-snbtotal:2667 pass:1312 dwarn:1   dfail:0   fail:12  skip:1342 
time:8096s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7276/shards.html
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Re: [Intel-gfx] [PATCH 07/15] drm/mediatek: Use drm_mode_get_hv_timing() to populate plane clip rectangle

[Ville Syrjälä]

On Fri, Nov 24, 2017 at 03:32:22PM +0100, Philipp Zabel wrote:
> On Thu, 2017-11-23 at 21:04 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä 
> > 
> > Use drm_mode_get_hv_timing() to fill out the plane clip rectangle.
> > 
> > No functional changes as the code already uses crtc_state->mode
> > to populate the clip, which is also what drm_mode_get_hv_timing()
> > uses.
> 
> I don't understand this explanation, drm_mode_get_hv_timing uses
> whichever mode is passed to it?

Hmm. I worded that badly it seems. The point is that we pass the user
mode everywhere else where we want to know the dimensions of the
crtc coordinate space.

> 
> > Once everyone agrees on this we can move the clip handling into
> > drm_atomic_helper_check_plane_state().
> 
> I can see that there are no functional changes though,
> 
> Acked-by: Philipp Zabel 
> 
> regards
> Philipp

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 07/15] drm/mediatek: Use drm_mode_get_hv_timing() to populate plane clip rectangle

[Philipp Zabel]

On Thu, 2017-11-23 at 21:04 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Use drm_mode_get_hv_timing() to fill out the plane clip rectangle.
> 
> No functional changes as the code already uses crtc_state->mode
> to populate the clip, which is also what drm_mode_get_hv_timing()
> uses.

I don't understand this explanation, drm_mode_get_hv_timing uses
whichever mode is passed to it?

> Once everyone agrees on this we can move the clip handling into
> drm_atomic_helper_check_plane_state().

I can see that there are no functional changes though,

Acked-by: Philipp Zabel 

regards
Philipp
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Re: [Intel-gfx] [PATCH 06/15] drm/imx: Use drm_mode_get_hv_timing() to populate plane clip rectangle

[Philipp Zabel]

On Thu, 2017-11-23 at 21:04 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Use drm_mode_get_hv_timing() to fill out the plane clip rectangle.
> 
> Note that this replaces crtc_state->adjusted_mode usage with
> crtc_state->mode. The latter is the correct choice since that's the
> mode the user provided and it matches the plane crtc coordinates
> the user also provided.

I am not aware of any adjustments that change hdisplay/vdisplay anyway,

Acked-by: Philipp Zabel 

regards
Philipp
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/guc: Advance over port[0] if set and not preempting

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/guc: Advance over port[0] if set 
and not preempting
URL   : https://patchwork.freedesktop.org/series/34361/
State : success

== Summary ==

Series 34361v1 series starting with [1/2] drm/i915/guc: Advance over port[0] if 
set and not preempting
https://patchwork.freedesktop.org/api/1.0/series/34361/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:445s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:455s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:382s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:541s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:277s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:504s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:510s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:502s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:491s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:428s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:265s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:543s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:428s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:438s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:425s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:473s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:462s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:481s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:520s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:478s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:527s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:576s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:456s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:539s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:563s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:524s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:494s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:457s
fi-snb-2520m total:246  pass:212  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:422s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:610s
fi-glk-dsi   total:289  pass:156  dwarn:0   dfail:10  fail:2   skip:121 
time:373s
fi-cnl-y failed to connect after reboot

99e3e01d35c95de2392d7f5796f3086cb13b441a drm-tip: 2017y-11m-24d-13h-20m-57s UTC 
integration manifest
b9f468eb29d4 HAX Enable GuC Submission for CI
927a4b8c8c74 drm/i915/guc: Advance over port[0] if set and not preempting

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7281/
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Re: [Intel-gfx] [PATCH v3] drm/i915: Use exponential backoff for wait_for()

[Chris Wilson]

Quoting Michał Winiarski (2017-11-24 12:37:56)
> Since we see the effects for GuC preeption, let's gather some evidence.
> 
> (SKL)
> intel_guc_send_mmio latency: 100 rounds of gem_exec_latency --r '*-preemption'
> 
> drm-tip:
>  usecs   : count distribution
>  0 -> 1  : 0||
>  2 -> 3  : 0||
>  4 -> 7  : 0||
>  8 -> 15 : 44   ||
> 16 -> 31 : 1088 ||
> 32 -> 63 : 832  ||
> 64 -> 127: 0||
>128 -> 255: 0||
>256 -> 511: 12   ||
>512 -> 1023   : 0||
>   1024 -> 2047   : 29899|*   |
>   2048 -> 4095   : 131033   ||

Such pretty graphs. Reminds me of the bpf hist output, I wonder if we
could create a tracepoint/kprobe that would output a histogram for each
waiter (filterable ofc). Benefit? Just thinking of tuning the
spin/sleep, in which case overall metrics are best
(intel_eait_for_register needs to be optimised for the typical case). I
am wondering if we could tune the spin period down to 5us, 2us? And then
have the 10us sleep.

We would also need a typical workload to run, it's profile-guided
optimisation after all. Hmm.
-Chris
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Re: [Intel-gfx] [PATCH 15/15] drm: Don't pass clip to drm_atomic_helper_check_plane_state()

[Ville Syrjälä]

On Fri, Nov 24, 2017 at 11:59:45AM +, Liviu Dudau wrote:
> On Thu, Nov 23, 2017 at 09:05:02PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä 
> 
> Hi Ville,
> 
> > 
> > Move the plane clip rectangle handling into
> > drm_atomic_helper_check_plane_state(). Drivers no longer
> > have to worry about such mundane details.
> 
> This is quite an important patch and I dare say the essence of your
> series, right? Yet very few people got Cc-ed on it (1 AFAICT) and it
> touches quite a few drivers.

It has no functional changes, so forgetting to plaster it with Ccs
doesn't seem all that dangerous. All the (potentially) functional
changes were in the prep patches which had Ccs, as did the cover
letter. And maintainers should read the ml anyway ;)

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH v2] drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too

[Rantala, Valtteri]

> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Friday, November 24, 2017 3:50 PM
> To: Rantala, Valtteri 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/glk: Apply
> WaProgramL3SqcReg1DefaultForPerf for GLK too
> 
> On Fri, Nov 24, 2017 at 10:37:12AM +0200, Valtteri Rantala wrote:
> > Testing the texture read performance shows that the same tuning for
> > the SQ credits is needed on GLK as on BXT/APL. This has been also
> > confirmed by Altug from the HW team.
> >
> > V2: Rebase
> >
> > Signed-off-by: Valtteri Rantala 
> > ---
> >  drivers/gpu/drm/i915/intel_engine_cs.c | 8 
> >  1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> > b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index fede62d..e1dcc91 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1067,6 +1067,15 @@ static int gen9_init_workarounds(struct
> intel_engine_cs *engine)
> > /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
> > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
> >
> > +   /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
> > +   if (IS_GEN9_LP(dev_priv)) {
> > +   u32 val = I915_READ(GEN8_L3SQCREG1);
> > +
> > +   val &= ~L3_PRIO_CREDITS_MASK;
> > +   val |= L3_GENERAL_PRIO_CREDITS(62) |
> L3_HIGH_PRIO_CREDITS(2);
> > +   I915_WRITE(GEN8_L3SQCREG1, val);
> > +   }
> 
> We're now doing this twice on bxt aren't we? So pls either remove the same
> code from the bxt function, or just add this to the glk function instead of 
> here.
> 
> We might want to actually split gen9_init_workarounds() into big core and lp
> variants. IMO there are too many conditional branches in the current function,
> which sort of defeats the purpose of having platform specific 
> init_workarounds()
> functions in the first place.
Until that split is done I'll remove duplicate code from bxt. Since it is 
needed for both.

> 
> > +
> > /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
> > I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
> > GEN8_LQSC_FLUSH_COHERENT_LINES));
> > --
> > 2.7.4
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Ville Syrjälä
> Intel OTC
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Re: [Intel-gfx] [PATCH] x86/early-quirks: Extend Intel graphics stolen memory placement to 64bit

[Ville Syrjälä]

On Fri, Nov 24, 2017 at 09:30:17AM +0200, Joonas Lahtinen wrote:
> @@ -426,14 +426,14 @@ static size_t __init chv_stolen_size(int num, int slot, 
> int func)
>* 0x17 to 0x1d: 4MB increments start at 36MB
>*/
>   if (gms < 0x11)
> - return (size_t)gms * MB(32);
> + return gms * MB(32);
>   else if (gms < 0x17)
> - return (size_t)(gms - 0x11 + 2) * MB(4);
> + return (gms - 0x11 + 2) * MB(4);
>   else
> - return (size_t)(gms - 0x17 + 9) * MB(4);
> + return (gms - 0x17 + 9) * MB(4);

Unrelated random idea: Maybe someone could replace the
semi-magic looking +2,+9 etc. with just +MB(whatever)?

-- 
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Intel OTC
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Advance over port[0] if set and not preempting

[Mika Kuoppala]

Chris Wilson  writes:

> Quoting Chris Wilson (2017-11-24 13:37:44)
>> Our execlist emulation is intended to only use a maximum of 2 ports per
>> engine, so as to not overflow the wq. (By knowing the limits, we can
>> avoid having to handle the wq exhaustion.) However, upon adding
>> preemption, we lost the skip over the first port if set for the
>> non-preemption path. Restore it.
>> 
>> Reported-by: Mika Kuoppala 
>> Fixes: c41937fd994a ("drm/i915/guc: Preemption! With GuC")
>> Signed-off-by: Chris Wilson 
>> Cc: Michał Winiarski 
>> Cc: Mika Kuoppala 
>> ---
>>  drivers/gpu/drm/i915/intel_guc_submission.c | 29 
>> -
>>  1 file changed, 16 insertions(+), 13 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c 
>> b/drivers/gpu/drm/i915/intel_guc_submission.c
>> index cbf5a96f5806..70e64bdb73dd 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
>> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
>> @@ -743,23 +743,26 @@ static void guc_dequeue(struct intel_engine_cs *engine)
>> if (!rb)
>> goto unlock;
>>  
>> -   if (HAS_LOGICAL_RING_PREEMPTION(engine->i915) && port_isset(port)) {
>> -   struct guc_preempt_work *preempt_work =
>> -   >i915->guc.preempt_work[engine->id];
>> -
>> -   if (rb_entry(rb, struct i915_priolist, node)->priority >
>> -   max(port_request(port)->priotree.priority, 0)) {
>> -   execlists_set_active(execlists,
>> -EXECLISTS_ACTIVE_PREEMPT);
>> -   queue_work(engine->i915->guc.preempt_wq,
>> -  _work->work);
>> -   goto unlock;
>> -   } else if (port_isset(last_port)) {
>> -   goto unlock;
>> +   if (port_isset(port)) {
>> +   if (HAS_LOGICAL_RING_PREEMPTION(engine->i915)) {
>> +   struct guc_preempt_work *preempt_work =
>> +   >i915->guc.preempt_work[engine->id];
>> +
>> +   if (rb_entry(rb, struct i915_priolist, 
>> node)->priority >
>> +   max(port_request(port)->priotree.priority, 0)) {
>> +   execlists_set_active(execlists,
>> +
>> EXECLISTS_ACTIVE_PREEMPT);
>> +   queue_work(engine->i915->guc.preempt_wq,
>> +  _work->work);
>> +   goto unlock;
>> +   }
>> }
>>  
>> port++;
>> +   if (port_isset(port))
>
> You probably want to stick with last_port, or at least Mika will want to
> make it last_port again after he expands ELSP[] and propagates all the
> changes.

This looks cleaner this way. We can always bring it back if it truely
helps readability. There has been too much last_port == port[1]
assumptions to tackle with.

-Mika
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Re: [Intel-gfx] [PATCH v2] drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too

[Ville Syrjälä]

On Fri, Nov 24, 2017 at 10:37:12AM +0200, Valtteri Rantala wrote:
> Testing the texture read performance shows that the same tuning for
> the SQ credits is needed on GLK as on BXT/APL. This has been also
> confirmed by Altug from the HW team.
> 
> V2: Rebase
> 
> Signed-off-by: Valtteri Rantala 
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index fede62d..e1dcc91 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1067,6 +1067,15 @@ static int gen9_init_workarounds(struct 
> intel_engine_cs *engine)
>   /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
>   WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
>  
> + /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
> + if (IS_GEN9_LP(dev_priv)) {
> + u32 val = I915_READ(GEN8_L3SQCREG1);
> +
> + val &= ~L3_PRIO_CREDITS_MASK;
> + val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);
> + I915_WRITE(GEN8_L3SQCREG1, val);
> + }

We're now doing this twice on bxt aren't we? So pls either remove the
same code from the bxt function, or just add this to the glk function
instead of here.

We might want to actually split gen9_init_workarounds() into big core
and lp variants. IMO there are too many conditional branches in the
current function, which sort of defeats the purpose of having platform
specific init_workarounds() functions in the first place.

> +
>   /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
>   I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
>   GEN8_LQSC_FLUSH_COHERENT_LINES));
> -- 
> 2.7.4
> 
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Advance over port[0] if set and not preempting

[Mika Kuoppala]

Chris Wilson  writes:

> Our execlist emulation is intended to only use a maximum of 2 ports per
> engine, so as to not overflow the wq. (By knowing the limits, we can
> avoid having to handle the wq exhaustion.) However, upon adding
> preemption, we lost the skip over the first port if set for the
> non-preemption path. Restore it.
>
> Reported-by: Mika Kuoppala 
> Fixes: c41937fd994a ("drm/i915/guc: Preemption! With GuC")
> Signed-off-by: Chris Wilson 
> Cc: Michał Winiarski 
> Cc: Mika Kuoppala 

Now it makes sense to me. You might want a stamp from Michał too.

Reviewed-by: Mika Kuoppala 

> ---
>  drivers/gpu/drm/i915/intel_guc_submission.c | 29 
> -
>  1 file changed, 16 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c 
> b/drivers/gpu/drm/i915/intel_guc_submission.c
> index cbf5a96f5806..70e64bdb73dd 100644
> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> @@ -743,23 +743,26 @@ static void guc_dequeue(struct intel_engine_cs *engine)
>   if (!rb)
>   goto unlock;
>  
> - if (HAS_LOGICAL_RING_PREEMPTION(engine->i915) && port_isset(port)) {
> - struct guc_preempt_work *preempt_work =
> - >i915->guc.preempt_work[engine->id];
> -
> - if (rb_entry(rb, struct i915_priolist, node)->priority >
> - max(port_request(port)->priotree.priority, 0)) {
> - execlists_set_active(execlists,
> -  EXECLISTS_ACTIVE_PREEMPT);
> - queue_work(engine->i915->guc.preempt_wq,
> -_work->work);
> - goto unlock;
> - } else if (port_isset(last_port)) {
> - goto unlock;
> + if (port_isset(port)) {
> + if (HAS_LOGICAL_RING_PREEMPTION(engine->i915)) {
> + struct guc_preempt_work *preempt_work =
> + >i915->guc.preempt_work[engine->id];
> +
> + if (rb_entry(rb, struct i915_priolist, node)->priority >
> + max(port_request(port)->priotree.priority, 0)) {
> + execlists_set_active(execlists,
> +  EXECLISTS_ACTIVE_PREEMPT);
> + queue_work(engine->i915->guc.preempt_wq,
> +_work->work);
> + goto unlock;
> + }
>   }
>  
>   port++;
> + if (port_isset(port))
> + goto unlock;
>   }
> + GEM_BUG_ON(port_isset(port));
>  
>   do {
>   struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
> -- 
> 2.15.0
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Advance over port[0] if set and not preempting

[Chris Wilson]

Quoting Chris Wilson (2017-11-24 13:37:44)
> Our execlist emulation is intended to only use a maximum of 2 ports per
> engine, so as to not overflow the wq. (By knowing the limits, we can
> avoid having to handle the wq exhaustion.) However, upon adding
> preemption, we lost the skip over the first port if set for the
> non-preemption path. Restore it.
> 
> Reported-by: Mika Kuoppala 
> Fixes: c41937fd994a ("drm/i915/guc: Preemption! With GuC")
> Signed-off-by: Chris Wilson 
> Cc: Michał Winiarski 
> Cc: Mika Kuoppala 
> ---
>  drivers/gpu/drm/i915/intel_guc_submission.c | 29 
> -
>  1 file changed, 16 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c 
> b/drivers/gpu/drm/i915/intel_guc_submission.c
> index cbf5a96f5806..70e64bdb73dd 100644
> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> @@ -743,23 +743,26 @@ static void guc_dequeue(struct intel_engine_cs *engine)
> if (!rb)
> goto unlock;
>  
> -   if (HAS_LOGICAL_RING_PREEMPTION(engine->i915) && port_isset(port)) {
> -   struct guc_preempt_work *preempt_work =
> -   >i915->guc.preempt_work[engine->id];
> -
> -   if (rb_entry(rb, struct i915_priolist, node)->priority >
> -   max(port_request(port)->priotree.priority, 0)) {
> -   execlists_set_active(execlists,
> -EXECLISTS_ACTIVE_PREEMPT);
> -   queue_work(engine->i915->guc.preempt_wq,
> -  _work->work);
> -   goto unlock;
> -   } else if (port_isset(last_port)) {
> -   goto unlock;
> +   if (port_isset(port)) {
> +   if (HAS_LOGICAL_RING_PREEMPTION(engine->i915)) {
> +   struct guc_preempt_work *preempt_work =
> +   >i915->guc.preempt_work[engine->id];
> +
> +   if (rb_entry(rb, struct i915_priolist, 
> node)->priority >
> +   max(port_request(port)->priotree.priority, 0)) {
> +   execlists_set_active(execlists,
> +
> EXECLISTS_ACTIVE_PREEMPT);
> +   queue_work(engine->i915->guc.preempt_wq,
> +  _work->work);
> +   goto unlock;
> +   }
> }
>  
> port++;
> +   if (port_isset(port))

You probably want to stick with last_port, or at least Mika will want to
make it last_port again after he expands ELSP[] and propagates all the
changes.
-Chris
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Re: [Intel-gfx] [PATCH v2] drm/i915: Enable render context support for Ironlake (gen5)

[Ville Syrjälä]

On Thu, Nov 23, 2017 at 08:47:45PM +, Chris Wilson wrote:
> Ironlake does support being able to saving and reloading context specific
> registers between contexts, providing isolation of the basic GPU state
> (as programmable by userspace). This allows userspace to assume that the
> GPU retains their state from one batch to the next, minimising the
> amount of state it needs to reload.
> 
> v2: Fix off-by-one in reading CXT_SIZE, and add a comment that the
> CXT_SIZE and context-layout do not match in bspec, but the difference is
> irrelevant as we overallocate the full page anyway (Ville).
> 
> Signed-off-by: Chris Wilson 
> Cc: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c  | 16 
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +
>  2 files changed, 29 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index fede62daf3e1..5b99125a179b 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -175,6 +175,22 @@ __intel_engine_context_size(struct drm_i915_private 
> *dev_priv, u8 class)
>   return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
>   PAGE_SIZE);
>   case 5:
> + /*
> +  * There is a discrepancy here between the size reported
> +  * by the register and the size of the context layout
> +  * in the docs. Both are described as authorative!
> +  *
> +  * The discrepancy is on the order of a few cachelines,
> +  * but the total is under one page (4k), which is our
> +  * minimum allocation anyway so it should all come
> +  * out in the wash.
> +  */
> + cxt_size = I915_READ(CXT_SIZE) + 1;
> + DRM_DEBUG_DRIVER("gen%d CXT_SIZE = %d bytes [0x%08x]\n",
> +  INTEL_GEN(dev_priv),
> +  cxt_size * 64,
> +  cxt_size - 1);
> + return round_up(cxt_size * 64, PAGE_SIZE);
>   case 4:
>   case 3:
>   case 2:
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index e2085820b586..2074749b27a5 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1403,11 +1403,14 @@ static inline int mi_set_context(struct 
> drm_i915_gem_request *rq, u32 flags)
>   /* These flags are for resource streamer on HSW+ */
>   flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
>   else
> + /* We need to save the extended state for powersaving modes */
>   flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
>  
>   len = 4;
>   if (IS_GEN7(i915))
>   len += 2 + (num_rings ? 4*num_rings + 6 : 0);
> + if (IS_GEN5(i915))
> + len += 2;
>  
>   cs = intel_ring_begin(rq, len);
>   if (IS_ERR(cs))
> @@ -1430,6 +1433,14 @@ static inline int mi_set_context(struct 
> drm_i915_gem_request *rq, u32 flags)
>   GEN6_PSMI_SLEEP_MSG_DISABLE);
>   }
>   }
> + } else if (IS_GEN5(i915)) {
> + /*
> +  * This w/a is only listed for pre-production ilk a/b steppings,
> +  * but is also mentioned for programming the powerctx. To be
> +  * safe, just apply the workaround; we do not use SyncFlush so
> +  * this should never take effect and so be a no-op!
> +  */
> + *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN;

Maybe also toss in the name from the w/a db?

Reviewed-by: Ville Syrjälä 

>   }
>  
>   *cs++ = MI_NOOP;
> @@ -1464,6 +1475,8 @@ static inline int mi_set_context(struct 
> drm_i915_gem_request *rq, u32 flags)
>   *cs++ = MI_NOOP;
>   }
>   *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
> + } else if (IS_GEN5(i915)) {
> + *cs++ = MI_SUSPEND_FLUSH;
>   }
>  
>   intel_ring_advance(rq, cs);
> -- 
> 2.15.0

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 12/15] drm/tegra/dc: Use drm_mode_get_hv_timing() to populate plane clip rectangle

[Thierry Reding]

On Thu, Nov 23, 2017 at 09:04:59PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Use drm_mode_get_hv_timing() to fill out the plane clip rectangle.
> 
> No functional changes as the code already uses crtc_state->mode
> to populate the clip, which is also what drm_mode_get_hv_timing()
> uses.
> 
> Once everyone agrees on this we can move the clip handling into
> drm_atomic_helper_check_plane_state().
> 
> Cc: Laurent Pinchart 
> Cc: Thierry Reding 
> Cc: linux-te...@vger.kernel.org
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/tegra/dc.c | 9 -
>  1 file changed, 4 insertions(+), 5 deletions(-)

I assume you want to take this through drm-misc, so:

Acked-by: Thierry Reding 


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Re: [Intel-gfx] [PATCH 00/15] drm: More plane clipping polish

[Thierry Reding]

On Thu, Nov 23, 2017 at 09:04:47PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> This series first unifies all users of drm_atomic_helper_check_plane_state()
> to populate the clip rectangle with drm_mode_get_hv_timing(), and once
> everything is unified the clip rectangle handling is sucked into
> drm_atomic_helper_check_plane_state() away from driver code.
> 
> Entire series available here:
> git://github.com/vsyrjala/linux.git atomic_plane_helper_clip
> 
> Cc: Archit Taneja 
> Cc: Ben Skeggs 
> Cc: Brian Starkey 
> Cc: CK Hu 
> Cc: Daniel Vetter 
> Cc: freedr...@lists.freedesktop.org
> Cc: Laurent Pinchart 
> Cc: linux-amlo...@lists.infradead.org
> Cc: linux-arm-...@vger.kernel.org
> Cc: linux-te...@vger.kernel.org
> Cc: Liviu Dudau 
> Cc: Mali DP Maintainers 
> Cc: Mark Yao 
> Cc: Neil Armstrong 
> Cc: Noralf Trønnes 
> Cc: nouv...@lists.freedesktop.org
> Cc: Philipp Zabel 
> Cc: Rob Clark 
> Cc: Shawn Guo 
> Cc: Sinclair Yeh 
> Cc: Thierry Reding 
> Cc: Thomas Hellstrom 
> Cc: VMware Graphics 
> 
> Ville Syrjälä (15):
>   drm/i915: Reject odd pipe source width with double wide/dual link
>   drm/i915: Use drm_mode_get_hv_timing() to populate plane clip
> rectangle
>   drm/arm/hdlcd: Use drm_mode_get_hv_timing() to populate plane clip
> rectangle
>   drm/arm/mali-dp: Use drm_mode_get_hv_timing() to populate plane clip
> rectangle
>   drm/simple_kms_helper: Use drm_mode_get_hv_timing() to populate plane
> clip rectangle
>   drm/imx: Use drm_mode_get_hv_timing() to populate plane clip rectangle
>   drm/mediatek: Use drm_mode_get_hv_timing() to populate plane clip
> rectangle
>   drm/meson: Use drm_mode_get_hv_timing() to populate plane clip
> rectangle
>   drm/msm/mdp5: Use drm_mode_get_hv_timing() to populate plane clip
> rectangle
>   drm/nouveau/kms/nv50: Use drm_mode_get_hv_timing() to populate plane
> clip rectangle
>   drm/rockchip: Use drm_mode_get_hv_timing() to populate plane clip
> rectangle
>   drm/tegra/dc: Use drm_mode_get_hv_timing() to populate plane clip
> rectangle
>   drm/vmwgfx: Use drm_mode_get_hv_timing() to populate plane clip
> rectangle
>   drm/zte: Use drm_mode_get_hv_timing() to populate plane clip rectangle
>   drm: Don't pass clip to drm_atomic_helper_check_plane_state()
> 
>  drivers/gpu/drm/arm/hdlcd_crtc.c|  6 +-
>  drivers/gpu/drm/arm/malidp_planes.c |  5 +
>  drivers/gpu/drm/armada/armada_overlay.c |  2 +-
>  drivers/gpu/drm/drm_atomic_helper.c | 12 +++-
>  drivers/gpu/drm/drm_plane_helper.c  | 11 +++
>  drivers/gpu/drm/drm_simple_kms_helper.c |  5 -
>  drivers/gpu/drm/i915/intel_atomic_plane.c   |  8 
>  drivers/gpu/drm/i915/intel_display.c| 12 +++-
>  drivers/gpu/drm/i915/intel_drv.h|  1 -
>  drivers/gpu/drm/i915/intel_sprite.c |  8 ++--
>  drivers/gpu/drm/imx/ipuv3-plane.c   |  7 +--
>  drivers/gpu/drm/mediatek/mtk_drm_plane.c|  6 +-
>  drivers/gpu/drm/meson/meson_plane.c |  6 +-
>  drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c   | 14 ++
>  drivers/gpu/drm/nouveau/nv50_display.c  |  8 
>  drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  8 +---
>  drivers/gpu/drm/tegra/dc.c  |  8 +---
>  drivers/gpu/drm/vmwgfx/vmwgfx_kms.c |  8 +---
>  drivers/gpu/drm/zte/zx_plane.c  | 15 +--
>  include/drm/drm_atomic_helper.h |  1 -
>  include/drm/drm_plane_helper.h  |  1 -
>  21 files changed, 35 insertions(+), 117 deletions(-)

The series:

Reviewed-by: Thierry Reding 


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[Intel-gfx] [PATCH 1/2] drm/i915/guc: Advance over port[0] if set and not preempting

[Chris Wilson]

Our execlist emulation is intended to only use a maximum of 2 ports per
engine, so as to not overflow the wq. (By knowing the limits, we can
avoid having to handle the wq exhaustion.) However, upon adding
preemption, we lost the skip over the first port if set for the
non-preemption path. Restore it.

Reported-by: Mika Kuoppala 
Fixes: c41937fd994a ("drm/i915/guc: Preemption! With GuC")
Signed-off-by: Chris Wilson 
Cc: Michał Winiarski 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_guc_submission.c | 29 -
 1 file changed, 16 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c 
b/drivers/gpu/drm/i915/intel_guc_submission.c
index cbf5a96f5806..70e64bdb73dd 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -743,23 +743,26 @@ static void guc_dequeue(struct intel_engine_cs *engine)
if (!rb)
goto unlock;
 
-   if (HAS_LOGICAL_RING_PREEMPTION(engine->i915) && port_isset(port)) {
-   struct guc_preempt_work *preempt_work =
-   >i915->guc.preempt_work[engine->id];
-
-   if (rb_entry(rb, struct i915_priolist, node)->priority >
-   max(port_request(port)->priotree.priority, 0)) {
-   execlists_set_active(execlists,
-EXECLISTS_ACTIVE_PREEMPT);
-   queue_work(engine->i915->guc.preempt_wq,
-  _work->work);
-   goto unlock;
-   } else if (port_isset(last_port)) {
-   goto unlock;
+   if (port_isset(port)) {
+   if (HAS_LOGICAL_RING_PREEMPTION(engine->i915)) {
+   struct guc_preempt_work *preempt_work =
+   >i915->guc.preempt_work[engine->id];
+
+   if (rb_entry(rb, struct i915_priolist, node)->priority >
+   max(port_request(port)->priotree.priority, 0)) {
+   execlists_set_active(execlists,
+EXECLISTS_ACTIVE_PREEMPT);
+   queue_work(engine->i915->guc.preempt_wq,
+  _work->work);
+   goto unlock;
+   }
}
 
port++;
+   if (port_isset(port))
+   goto unlock;
}
+   GEM_BUG_ON(port_isset(port));
 
do {
struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
-- 
2.15.0

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[Intel-gfx] [PATCH 2/2] HAX Enable GuC Submission for CI

[Chris Wilson]

From: Michał Winiarski 

Also:
Revert "drm/i915/guc: Assert that we switch between known ggtt->invalidate 
functions"

This reverts commit 04f7b24eccdfae680a36e9825fe0d61dcd5ed528.
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++--
 drivers/gpu/drm/i915/i915_params.h  | 4 ++--
 2 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 41a203e0c160..5e8614fd390b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3590,17 +3590,13 @@ int i915_ggtt_enable_hw(struct drm_i915_private 
*dev_priv)
 
 void i915_ggtt_enable_guc(struct drm_i915_private *i915)
 {
-   GEM_BUG_ON(i915->ggtt.invalidate != gen6_ggtt_invalidate);
-
i915->ggtt.invalidate = guc_ggtt_invalidate;
 }
 
 void i915_ggtt_disable_guc(struct drm_i915_private *i915)
 {
-   /* We should only be called after i915_ggtt_enable_guc() */
-   GEM_BUG_ON(i915->ggtt.invalidate != guc_ggtt_invalidate);
-
-   i915->ggtt.invalidate = gen6_ggtt_invalidate;
+   if (i915->ggtt.invalidate == guc_ggtt_invalidate)
+   i915->ggtt.invalidate = gen6_ggtt_invalidate;
 }
 
 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 8321bd86cba5..69ee2484c6bb 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -42,8 +42,8 @@
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
-   param(int, enable_guc_loading, 0) \
-   param(int, enable_guc_submission, 0) \
+   param(int, enable_guc_loading, 1) \
+   param(int, enable_guc_submission, 1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
-- 
2.15.0

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915/guc: Tidy ELSP port assignment

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/3] drm/i915/guc: Tidy ELSP port assignment
URL   : https://patchwork.freedesktop.org/series/34360/
State : success

== Summary ==

Series 34360v1 series starting with [CI,1/3] drm/i915/guc: Tidy ELSP port 
assignment
https://patchwork.freedesktop.org/api/1.0/series/34360/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:443s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:450s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:381s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:531s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:276s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:507s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:512s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:487s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:484s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:421s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:267s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:538s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:427s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:432s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:427s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:482s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:457s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:476s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:527s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:464s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:535s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:568s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:459s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:536s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:560s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:507s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:499s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:456s
fi-snb-2520m total:246  pass:212  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:415s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:618s
fi-glk-dsi   total:218  pass:118  dwarn:0   dfail:1   fail:1   skip:97 

79ca54cbfbc7aae4090d6ded6af6348f8654322d drm-tip: 2017y-11m-24d-12h-19m-52s UTC 
integration manifest
e4c0cc4304f5 HAX Enable GuC Submission for CI
78cd90672985 drm/i915: Use exponential backoff for wait_for()
d5b388e94d4f drm/i915/guc: Tidy ELSP port assignment

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7280/
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Re: [Intel-gfx] [PATCH 06/10] drm/edid: Fix cea mode aspect ratio handling

[Ville Syrjälä]

On Fri, Nov 24, 2017 at 02:26:09PM +0530, Sharma, Shashank wrote:
> Regards
> 
> Shashank
> 
> 
> On 11/17/2017 6:19 PM, Ville Syrjälä wrote:
> > On Fri, Nov 17, 2017 at 05:50:11PM +0530, Sharma, Shashank wrote:
> >> Regards
> >>
> >> Shashank
> >>
> >>
> >> On 11/17/2017 5:05 PM, Ville Syrjälä wrote:
> >>> On Fri, Nov 17, 2017 at 08:49:49AM +0530, Sharma, Shashank wrote:
>  Regards
> 
>  Shashank
> 
> 
>  On 11/16/2017 9:53 PM, Ville Syrjälä wrote:
> > On Thu, Nov 16, 2017 at 08:21:44PM +0530, Sharma, Shashank wrote:
> >> Regards
> >>
> >> Shashank
> >>
> >>
> >> On 11/13/2017 10:34 PM, Ville Syrjala wrote:
> >>> From: Ville Syrjälä 
> >>>
> >>> commit 6dffd431e229 ("drm: Add aspect ratio parsing in DRM layer")
> >>> cause us to not send out any VICs in the AVI infoframes. That commit
> >>> was since reverted, but if and when we add aspect ratio handing back
> >>> we need to be more careful.
> >>>
> >>> Let's handle this by considering the aspect ratio as a requirement
> >>> for cea mode matching only if the passed in mode actually has a
> >>> non-zero aspect ratio field. This will keep userspace that doesn't
> >>> provide an aspect ratio working as before by matching it to the
> >>> first otherwise equal cea mode. And once userspace starts to
> >>> provide the aspect ratio it will be considerd a hard requirement
> >>> for the match.
> >>>
> >>> Also change the hdmi mode matching to use drm_mode_match() for
> >>> consistency, but we don't match on aspect ratio there since the
> >>> spec doesn't list a specific aspect ratio for those modes.
> >>>
> >>> Cc: Shashank Sharma 
> >>> Cc: "Lin, Jia" 
> >>> Cc: Akashdeep Sharma 
> >>> Cc: Jim Bride 
> >>> Cc: Jose Abreu 
> >>> Cc: Daniel Vetter 
> >>> Cc: Emil Velikov 
> >>> Signed-off-by: Ville Syrjälä 
> >>> ---
> >>>  drivers/gpu/drm/drm_edid.c | 18 ++
> >>>  1 file changed, 14 insertions(+), 4 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> >>> index 7220b8f9a7e8..00aa98f3e55d 100644
> >>> --- a/drivers/gpu/drm/drm_edid.c
> >>> +++ b/drivers/gpu/drm/drm_edid.c
> >>> @@ -2903,11 +2903,15 @@ cea_mode_alternate_timings(u8 vic, struct 
> >>> drm_display_mode *mode)
> >>>  static u8 drm_match_cea_mode_clock_tolerance(const struct 
> >>> drm_display_mode *to_match,
> >>>unsigned int 
> >>> clock_tolerance)
> >>>  {
> >>> + unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | 
> >>> DRM_MODE_MATCH_FLAGS;
> >>>   u8 vic;
> >>>  
> >>>   if (!to_match->clock)
> >>>   return 0;
> >>>  
> >>> + if (to_match->picture_aspect_ratio)
> >>> + match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
> >> This doesn't look right. This means we are expecting a CEA mode without
> >> a pic aspect ratio field,
> >> which is invalid.
> > No, it's perfectly valid. It's what we currently get from userspace.
>  Yep, but that's due to missing Aspect ratio handling in the DRM layer.
>  If that's fixed, as per the list of CEA modes,
>  each CEA VIC contains an aspect ratio, which is a part of its unique
>  identity.
> 
>  I guess once we have the aspect ratio handling in DRM layer, it
>  would/should look like this:
>  - EDID gives you all supported modes, including CEA modes with Aspect 
>  ratio
>  - Userspcae gets the mode information, with aspect ratio (for CEA modes)
>  If ( Userspace picks one of the CEA modes)
> - sends a modeset
> - we find a matching CEA VIC, found one from modedb
> - we load this VIC = nonzero information in AVI IF VIC field,
>  else
> - sends a modeset
> - we could not find a matching CEA VIC, as aspect ratio is 0
> - we make VIC field in AVI IF as 0
> >>> No. That would break current userspace.
> >> I guess I forgot to make it clear, that userspace will set the cap, only
> >> then we will provide aspect ratio information.
> >> So this should not break userspace, isn't it ?
>  This is important, as HDMI compliance test 7-27 inspects if the VIC
>  field in the AVI IF is accurate.
> >>> Complicance is secondary to not breaking things that work. Also I find
> >>> it hard to see what purpose there is in having a complicance test that
> >>> sets a CEA modes w/o aspect ratio and then expects the infoframe to have
> >>> VIC 0.
> >> Again, typically this is how these analyzers force 

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Stop averaging with the previous sample

[Tvrtko Ursulin]

On 24/11/2017 10:38, Patchwork wrote:

== Series Details ==

Series: drm/i915/pmu: Stop averaging with the previous sample
URL   : https://patchwork.freedesktop.org/series/34346/
State : success

== Summary ==

Series 34346v1 drm/i915/pmu: Stop averaging with the previous sample
https://patchwork.freedesktop.org/api/1.0/series/34346/revisions/1/mbox/

Test gem_busy:
 Subgroup basic-hang-default:
 incomplete -> PASS   (fi-cfl-s2)
Test gem_exec_reloc:
 Subgroup basic-gtt-cpu-active:
 fail   -> PASS   (fi-gdg-551) fdo#102582 +2

fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:443s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:464s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:381s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:537s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:278s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:508s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:513s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:497s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:492s
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:612s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:432s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:269s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:540s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:428s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:442s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:428s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:471s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:468s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:489s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:527s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:476s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:533s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:578s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:454s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:545s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:566s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:518s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:498s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:459s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:559s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:431s

a5d8a220645ed25df2088568070cfdfb1bbf59c4 drm-tip: 2017y-11m-24d-09h-54m-57s UTC 
integration manifest
bc84de5a37ce drm/i915/pmu: Stop averaging with the previous sample


Pushed after seeing that shards were also happy.

Regards,

Tvrtko

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Re: [Intel-gfx] [PATCH] drm/i915/guc: Tidy ELSP port assignment

[Chris Wilson]

Quoting Chris Wilson (2017-11-24 12:29:16)
> Since we know that the port is empty, we do not need to extract the
> count from the old request it and copy it over to the new request, or
> attempt to unref the NULL old request pointer.
> 
> Signed-off-by: Chris Wilson 
> Cc: Mika Kuoppala 
> Cc: Michał Winiarski 

Oooh, Mika noticed that we no longer skip port[0] if set, as that is no
behind the if (preempt). Oops. As I recall, the intention is that we
only use a maximum of two ports per engine to avoid overflow. If we let
ourselves coalesce onto port[0], we lose track of how many wq are in
flight.

Patch incoming.
-Chris
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