[Intel-gfx] [PATCH] drm/i915/psr : Add psr1 live status

[vathsala nagaraju]

From: Vathsala Nagaraju 

Prints live state of psr1.Extending the existing
PSR2 live state function to cover psr1.

Tested on KBL with psr2 and psr1 panel.

v2: rebase
v3: DK
Rename psr2_live_status to psr_source_status.
v4: DK
Move EDP_PSR_STATUS_STATE_SHIFT below EDP_PSR_STATUS_STATE_MASK.
Pass seq to psr_source_status, handle source status prints in
psr_source_status.

Cc: Rodrigo Vivi 
Cc: Dhinakaran Pandiyan 

Signed-off-by: Vathsala Nagaraju 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 71 -
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 2 files changed, 48 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5251544..9e6594c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2596,27 +2596,54 @@ static int i915_guc_log_relay_release(struct inode 
*inode, struct file *file)
.release = i915_guc_log_relay_release,
 };
 
-static const char *psr2_live_status(u32 val)
-{
-   static const char * const live_status[] = {
-   "IDLE",
-   "CAPTURE",
-   "CAPTURE_FS",
-   "SLEEP",
-   "BUFON_FW",
-   "ML_UP",
-   "SU_STANDBY",
-   "FAST_SLEEP",
-   "DEEP_SLEEP",
-   "BUF_ON",
-   "TG_ON"
-   };
+void psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
+{
+   u32 val, psr_status = 0;
 
-   val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT;
-   if (val < ARRAY_SIZE(live_status))
-   return live_status[val];
+   if (dev_priv->psr.psr2_enabled) {
+   static const char * const live_status[] = {
+   "IDLE",
+   "CAPTURE",
+   "CAPTURE_FS",
+   "SLEEP",
+   "BUFON_FW",
+   "ML_UP",
+   "SU_STANDBY",
+   "FAST_SLEEP",
+   "DEEP_SLEEP",
+   "BUF_ON",
+   "TG_ON"
+   };
+   psr_status = I915_READ(EDP_PSR2_STATUS);
+   val =  (psr_status & EDP_PSR2_STATUS_STATE_MASK) >>
+   EDP_PSR2_STATUS_STATE_SHIFT;
+   if (val < ARRAY_SIZE(live_status)) {
+   seq_printf(m, "Source PSR status: %x[%s]\n", psr_status,
+   live_status[val]);
+   return;
+   }
+   } else {
+   static const char * const live_status[] = {
+   "IDLE",
+   "SRDONACK",
+   "SRDENT",
+   "BUFOFF",
+   "BUFON",
+   "AUXACK",
+   "SRDOFFACK",
+   "SRDENT_ON",
+   };
+   psr_status = I915_READ(EDP_PSR_STATUS);
+   val = (psr_status & EDP_PSR_STATUS_STATE_MASK) >>
+   EDP_PSR_STATUS_STATE_SHIFT;
+   if (val < ARRAY_SIZE(live_status)) {
+   seq_printf(m, "Source PSR status: %x[%s]\n", psr_status,
+   live_status[val]);
+   return;
+   }
+   }
 
-   return "unknown";
+   seq_printf(m, "Source psr status: %x[%s]\n", psr_status, "unknown");
 }
 
 static const char *psr_sink_status(u8 val)
@@ -2714,12 +2741,8 @@ static int i915_edp_psr_status(struct seq_file *m, void 
*data)
 
seq_printf(m, "Performance_Counter: %u\n", psrperf);
}
-   if (dev_priv->psr.psr2_enabled) {
-   u32 psr2 = I915_READ(EDP_PSR2_STATUS);
 
-   seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
-  psr2, psr2_live_status(psr2));
-   }
+   psr_source_status(dev_priv, m);
 
if (dev_priv->psr.enabled) {
struct drm_dp_aux *aux = _priv->psr.enabled->aux;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 513b4a4..0ac25d9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4048,6 +4048,7 @@ enum {
 
 #define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 
0x40)
 #define   EDP_PSR_STATUS_STATE_MASK(7<<29)
+#define   EDP_PSR_STATUS_STATE_SHIFT29
 #define   EDP_PSR_STATUS_STATE_IDLE(0<<29)
 #define   EDP_PSR_STATUS_STATE_SRDONACK(1<<29)
 #define   EDP_PSR_STATUS_STATE_SRDENT  (2<<29)
-- 
1.9.1

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Set idle frame count based on sink synchronization latency

[Patchwork]

== Series Details ==

Series: drm/i915/psr: Set idle frame count based on sink synchronization latency
URL   : https://patchwork.freedesktop.org/series/43742/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4236 -> Patchwork_9113 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9113 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9113, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43742/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9113:

  === IGT changes ===

 Warnings 

igt@gem_exec_gttfill@basic:
  fi-pnv-d510:PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_9113 that come from known issues:

  === IGT changes ===

 Possible fixes 

igt@gem_mmap_gtt@basic-small-bo-tiledx:
  fi-gdg-551: FAIL (fdo#102575) -> PASS

igt@kms_frontbuffer_tracking@basic:
  fi-hsw-4200u:   DMESG-FAIL (fdo#106103, fdo#102614) -> PASS

igt@prime_vgem@basic-fence-flip:
  fi-ilk-650: FAIL (fdo#104008) -> PASS


  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
  fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103


== Participating hosts (43 -> 39) ==

  Additional (1): fi-snb-2520m 
  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4236 -> Patchwork_9113

  CI_DRM_4236: 39b54b1e366012ce58e6a0cc175612577480992f @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4498: f9ecb79ad8b02278cfdb5b82495df47061c04f8f @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9113: 9601f363642d91c8ff0fa582fd2c6198e00feb46 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

9601f363642d drm/i915/psr: Set idle frame count based on sink synchronization 
latency

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9113/issues.html
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/psr: Set idle frame count based on sink synchronization latency

[Patchwork]

== Series Details ==

Series: drm/i915/psr: Set idle frame count based on sink synchronization latency
URL   : https://patchwork.freedesktop.org/series/43742/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/psr: Set idle frame count based on sink synchronization latency
-O:drivers/gpu/drm/i915/intel_psr.c:382:32: warning: expression using 
sizeof(void)
-O:drivers/gpu/drm/i915/intel_psr.c:434:32: warning: expression using 
sizeof(void)
+drivers/gpu/drm/i915/intel_psr.c:379:27: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_psr.c:384:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_psr.c:384:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_psr.c:432:27: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_psr.c:434:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_psr.c:434:23: warning: expression using sizeof(void)

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[Intel-gfx] [PATCH] drm/i915/psr: Set idle frame count based on sink synchronization latency

[Dhinakaran Pandiyan]

DPCD 2009h "Synchronization latency in sink" has bits that tell us the
maximum number of frames sink can take to resynchronize to source timing
when exiting PSR. More importantly, as per eDP 1.4b, this is the "Minimum
number of frames following PSR exit that the Source device needs to
wait for PSR entry."

We currently use this value only to setup the number frames to wait before
PSR2 selective update. But, based on the above description it makes more
sense to use this to configure idle frames for both PSR1 and and PSR2. This
will ensure we wait the required number of frames before
activation whether it is PSR1 or PSR2.

The minimum number of idle frames remains 6, while allowing sink
synchronization latency and VBT to increase this value.

This also solves the flip-flop between sink and source frames that I
noticed on my Thinkpad X260 during PSR exit. This specific panel has a
value of 8h, which according to the spec means the "Source device must
wait for more than eight active frames after PSR exit before initiating PSR
entry. (In this case, should be provided by the panel supplier.)" VBT
however has a value of 0.

Cc: Jani Nikula 
Cc: Jose Roberto de Souza 
Cc: Rodrigo Vivi 
Signed-off-by: Dhinakaran Pandiyan 
---
 drivers/gpu/drm/i915/intel_psr.c | 40 
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index ebc483f06c6f..71dfe541740f 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -247,6 +247,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
return;
}
dev_priv->psr.sink_support = true;
+   dev_priv->psr.sink_sync_latency =
+   intel_dp_get_sink_sync_latency(intel_dp);
 
if (INTEL_GEN(dev_priv) >= 9 &&
(intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
@@ -272,8 +274,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
if (dev_priv->psr.sink_psr2_support) {
dev_priv->psr.colorimetry_support =
intel_dp_get_colorimetry_status(intel_dp);
-   dev_priv->psr.sink_sync_latency =
-   intel_dp_get_sink_sync_latency(intel_dp);
}
}
 }
@@ -370,21 +370,21 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
+   u32 max_sleep_time = 0x1f;
+   u32 val = EDP_PSR_ENABLE;
 
-   uint32_t max_sleep_time = 0x1f;
-   /*
-* Let's respect VBT in case VBT asks a higher idle_frame value.
-* Let's use 6 as the minimum to cover all known cases including
-* the off-by-one issue that HW has in some cases. Also there are
-* cases where sink should be able to train
-* with the 5 or 6 idle patterns.
+   /* Let's use 6 as the minimum to cover all known cases including the
+* off-by-one issue that HW has in some cases.
 */
-   uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
-   uint32_t val = EDP_PSR_ENABLE;
+   int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
 
-   val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
+   /* sink_sync_latency of 8 means source has to wait for more than 8
+* frames, we'll go with 9 frames for now
+*/
+   idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 
+   val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
if (IS_HASWELL(dev_priv))
val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
@@ -424,15 +424,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
-   /*
-* Let's respect VBT in case VBT asks a higher idle_frame value.
-* Let's use 6 as the minimum to cover all known cases including
-* the off-by-one issue that HW has in some cases. Also there are
-* cases where sink should be able to train
-* with the 5 or 6 idle patterns.
+   u32 val;
+
+   /* Let's use 6 as the minimum to cover all known cases including the
+* off-by-one issue that HW has in some cases.
 */
-   uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
-   u32 val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
+   int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
+
+   idle_frames = max(idle_frames, 

[Intel-gfx] ✓ Fi.CI.IGT: success for gpu: Consistently use octal not symbolic permissions

[Patchwork]

== Series Details ==

Series: gpu: Consistently use octal not symbolic permissions
URL   : https://patchwork.freedesktop.org/series/43729/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4234_full -> Patchwork_9110_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9110_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9110_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43729/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9110_full:

  === IGT changes ===

 Warnings 

igt@gem_mocs_settings@mocs-rc6-bsd1:
  shard-kbl:  PASS -> SKIP +1

igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
  shard-snb:  SKIP -> PASS


== Known issues ==

  Here are the changes found in Patchwork_9110_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_selftest@live_gtt:
  shard-glk:  PASS -> INCOMPLETE (fdo#103359, k.org#198133)

igt@kms_flip@2x-plain-flip-fb-recreate:
  shard-hsw:  PASS -> FAIL (fdo#100368)

igt@kms_flip@plain-flip-fb-recreate:
  shard-glk:  PASS -> FAIL (fdo#100368) +1


 Possible fixes 

igt@drv_selftest@live_gtt:
  shard-kbl:  INCOMPLETE (fdo#103665) -> PASS

igt@gem_ppgtt@blt-vs-render-ctx0:
  shard-kbl:  INCOMPLETE (fdo#103665, fdo#106023) -> PASS

igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
  shard-glk:  FAIL (fdo#105703) -> PASS

igt@kms_flip@2x-flip-vs-expired-vblank:
  shard-glk:  FAIL (fdo#105363) -> PASS

igt@perf@blocking:
  shard-hsw:  FAIL (fdo#102252) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4234 -> Patchwork_9110

  CI_DRM_4234: 399e4206d849c5667d8553911e0035c53cd9c24e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4498: f9ecb79ad8b02278cfdb5b82495df47061c04f8f @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9110: ce883dbd4f90d0aeb63a64906872fc163367ae0d @ 
git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9110/shards.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/edid: Fix up edid_cea_modes[] formatting

[Patchwork]

== Series Details ==

Series: drm/edid: Fix up edid_cea_modes[] formatting
URL   : https://patchwork.freedesktop.org/series/43722/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4234_full -> Patchwork_9109_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9109_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9109_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43722/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9109_full:

  === IGT changes ===

 Warnings 

igt@gem_mocs_settings@mocs-rc6-bsd2:
  shard-kbl:  SKIP -> PASS

igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
  shard-snb:  SKIP -> PASS


== Known issues ==

  Here are the changes found in Patchwork_9109_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_selftest@live_hangcheck:
  shard-kbl:  NOTRUN -> DMESG-FAIL (fdo#106560)

igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
  shard-glk:  PASS -> FAIL (fdo#105703)

igt@kms_cursor_legacy@flip-vs-cursor-atomic:
  shard-hsw:  PASS -> FAIL (fdo#102670)

igt@kms_flip@dpms-vs-vblank-race-interruptible:
  shard-glk:  PASS -> FAIL (fdo#103060)

igt@kms_flip@flip-vs-expired-vblank:
  shard-glk:  PASS -> FAIL (fdo#105707)

igt@kms_flip@plain-flip-fb-recreate:
  shard-glk:  PASS -> FAIL (fdo#100368)

igt@kms_flip_tiling@flip-to-y-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724, fdo#103822)

igt@kms_rotation_crc@primary-rotation-180:
  shard-apl:  PASS -> FAIL (fdo#104724, fdo#103925)


 Possible fixes 

igt@drv_selftest@live_gtt:
  shard-kbl:  INCOMPLETE (fdo#103665) -> PASS

igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
  shard-glk:  FAIL (fdo#105703) -> PASS

igt@kms_flip@2x-flip-vs-expired-vblank:
  shard-glk:  FAIL (fdo#105363) -> PASS

igt@kms_flip_tiling@flip-x-tiled:
  shard-glk:  FAIL (fdo#104724, fdo#103822) -> PASS +1

igt@kms_setmode@basic:
  shard-apl:  FAIL (fdo#99912) -> PASS

igt@perf@blocking:
  shard-hsw:  FAIL (fdo#102252) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4234 -> Patchwork_9109

  CI_DRM_4234: 399e4206d849c5667d8553911e0035c53cd9c24e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4498: f9ecb79ad8b02278cfdb5b82495df47061c04f8f @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9109: 4258ca94a2a353d6af2c44dc7af8b055ef0bb990 @ 
git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9109/shards.html
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Try to suppress more spurious PCH underruns on ILK-IVB

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Try to suppress more spurious PCH 
underruns on ILK-IVB
URL   : https://patchwork.freedesktop.org/series/43721/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4234_full -> Patchwork_9108_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9108_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9108_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43721/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9108_full:

  === IGT changes ===

 Warnings 

igt@gem_exec_schedule@deep-blt:
  shard-kbl:  PASS -> SKIP

igt@gem_mocs_settings@mocs-rc6-bsd2:
  shard-kbl:  SKIP -> PASS

igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
  shard-snb:  SKIP -> PASS


== Known issues ==

  Here are the changes found in Patchwork_9108_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_selftest@live_gtt:
  shard-glk:  PASS -> INCOMPLETE (k.org#198133, fdo#103359)

igt@drv_selftest@live_hangcheck:
  shard-kbl:  NOTRUN -> DMESG-FAIL (fdo#106560)

igt@kms_flip@2x-plain-flip-fb-recreate:
  shard-glk:  PASS -> FAIL (fdo#100368)

igt@kms_flip@flip-vs-expired-vblank:
  shard-glk:  PASS -> FAIL (fdo#105707)

igt@kms_flip_tiling@flip-to-y-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724)

igt@pm_rps@waitboost:
  shard-apl:  PASS -> FAIL (fdo#102250)


 Possible fixes 

igt@drv_selftest@live_gtt:
  shard-kbl:  INCOMPLETE (fdo#103665) -> PASS

igt@gem_ppgtt@blt-vs-render-ctx0:
  shard-kbl:  INCOMPLETE (fdo#103665, fdo#106023) -> PASS

igt@kms_flip_tiling@flip-to-x-tiled:
  shard-glk:  FAIL (fdo#103822, fdo#104724) -> PASS

igt@perf@blocking:
  shard-hsw:  FAIL (fdo#102252) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102250 https://bugs.freedesktop.org/show_bug.cgi?id=102250
  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707
  fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4234 -> Patchwork_9108

  CI_DRM_4234: 399e4206d849c5667d8553911e0035c53cd9c24e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4498: f9ecb79ad8b02278cfdb5b82495df47061c04f8f @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9108: 2296f07c0461544811deb6f930299d72b1589bec @ 
git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9108/shards.html
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[Intel-gfx] ✗ Fi.CI.BAT: failure for More ICL display patches (rev8)

[Patchwork]

== Series Details ==

Series: More ICL display patches (rev8)
URL   : https://patchwork.freedesktop.org/series/43546/
State : failure

== Summary ==

Applying: drm/i915/icl: Extend AUX F interrupts to ICL
Applying: drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
Applying: drm/i915/icl: introduce tc_port
Applying: drm/i915/icl: Support for TC North Display interrupts
Applying: drm/i915/icp: Add Interrupt Support
Applying: drm/i915/ICL: Add register definition for DFLEXDPMLE
Applying: drm/i915/icl: Add DDI HDMI level selection for ICL
Applying: drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin
Applying: drm/i915/icl: Add Icelake PCH detection
Applying: drm/i915/icl: add icelake_get_ddi_pll()
Applying: drm/i915/icl: Get DDI clock for ICL based on PLLs.
Applying: drm/i915/icl: Calculate link clock using the new registers
Applying: drm/i915/icl: unconditionally init DDI for every port
Applying: drm/i915/icl: start adding the TBT pll
Applying: drm/i915/icl: compute the TBT PLL registers
Applying: drm/i915/icl: Handle hotplug interrupts for DP over TBT
Applying: drm/i915/icl: Add 10-bit support for hdmi
Applying: drm/i915/icl: implement icl_digital_port_connected()
Applying: drm/i915/icl: store the port type for TC ports
Applying: drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP
Applying: drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI
Applying: drm/i915/icl: Update FIA supported lane count for hpd.
Applying: drm/i915/icl: program MG_DP_MODE
Applying: drm/i915/icl: toggle PHY clock gating around link training
Applying: drm/i915/icl: fix gmbus gpio pin mapping
error: Failed to merge in the changes.
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/i915_reg.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_reg.h
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_reg.h
Patch failed at 0025 drm/i915/icl: fix gmbus gpio pin mapping
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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Re: [Intel-gfx] [PATCH 05/24] drm/i915/icp: Add Interrupt Support

[Lucas De Marchi]

On Thu, May 24, 2018 at 05:45:43PM -0700, Dhinakaran Pandiyan wrote:
> On Thu, 2018-05-24 at 16:53 -0700, Lucas De Marchi wrote:
> > On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote:
> > > 
> > > From: Anusha Srivatsa 
> > > 
> > > This patch addresses Interrupts from south display engine (SDE).
> > > 
> > > ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
> > > Introduce these registers and their intended values.
> > > 
> > > Introduce icp_irq_handler().
> > > 
> > > Cc: Paulo Zanoni 
> > > Cc: Dhinakaran Pandiyan 
> > > Cc: Ville Syrjala 
> > > Signed-off-by: Anusha Srivatsa 
> > > [Paulo: coding style bikesheds and rebases].
> > > Signed-off-by: Paulo Zanoni 
> > > ---
> > >  drivers/gpu/drm/i915/i915_irq.c | 134
> > > +++-
> > >  drivers/gpu/drm/i915/i915_reg.h |  40 
> > >  2 files changed, 172 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c
> > > index 9bcec5fdb9d0..6b109991786f 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -122,6 +122,15 @@ static const u32 hpd_tc_gen11[HPD_NUM_PINS] =
> > > {
> > >   [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> > >  };
> > >  
> > > +static const u32 hpd_icp[HPD_NUM_PINS] = {
> > > + [HPD_PORT_A] = ICP_DDIA_HOTPLUG,
> > > + [HPD_PORT_B] = ICP_DDIB_HOTPLUG,
> > > + [HPD_PORT_C] = ICP_TC1_HOTPLUG,
> > > + [HPD_PORT_D] = ICP_TC2_HOTPLUG,
> > > + [HPD_PORT_E] = ICP_TC3_HOTPLUG,
> > > + [HPD_PORT_F] = ICP_TC4_HOTPLUG
> > > +};
> > > +
> > >  /* IIR can theoretically queue up two events. Be paranoid. */
> > >  #define GEN8_IRQ_RESET_NDX(type, which) do { \
> > >   I915_WRITE(GEN8_##type##_IMR(which), 0x); \
> > > @@ -1586,6 +1595,34 @@ static bool
> > > bxt_port_hotplug_long_detect(enum port port, u32 val)
> > >   }
> > >  }
> > >  
> > > +static bool icp_ddi_port_hotplug_long_detect(enum port port, u32
> > > val)
> > > +{
> > > + switch (port) {
> > > + case PORT_A:
> > > + return val & ICP_DDIA_HPD_LONG_DETECT;
> > > + case PORT_B:
> > > + return val & ICP_DDIB_HPD_LONG_DETECT;
> > > + default:
> > > + return false;
> > > + }
> > > +}
> > > +
> > > +static bool icp_tc_port_hotplug_long_detect(enum port port, u32
> > > val)
> > > +{
> > > + switch (port) {
> > > + case PORT_C:
> > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> > > + case PORT_D:
> > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> > > + case PORT_E:
> > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> > > + case PORT_F:
> > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> > > + default:
> > > + return false;
> > > + }
> > > +}
> > > +
> > >  static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
> > >  {
> > >   switch (port) {
> > > @@ -2377,6 +2414,43 @@ static void cpt_irq_handler(struct
> > > drm_i915_private *dev_priv, u32 pch_iir)
> > >   cpt_serr_int_handler(dev_priv);
> > >  }
> > >  
> > > +static void icp_irq_handler(struct drm_i915_private *dev_priv, u32
> > > pch_iir)
> > > +{
> > > + u32 ddi_hotplug_trigger = pch_iir & ICP_SDE_DDI_MASK;
> > > + u32 tc_hotplug_trigger = pch_iir & ICP_SDE_TC_MASK;
> > > + u32 pin_mask = 0, long_mask = 0;
> > > +
> > > + if (ddi_hotplug_trigger) {
> > > + u32 dig_hotplug_reg;
> > > +
> > > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
> > > + I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
> > > +
> > > + intel_get_hpd_pins(dev_priv, _mask,
> > > _mask,
> > > +    ddi_hotplug_trigger,
> > > +    dig_hotplug_reg, hpd_icp,
> > > +    icp_ddi_port_hotplug_long_detec
> > > t);
> > > + }
> > > +
> > > + if (tc_hotplug_trigger) {
> > > + u32 dig_hotplug_reg;
> > > +
> > > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
> > > + I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
> > > +
> > > + intel_get_hpd_pins(dev_priv, _mask,
> > > _mask,
> > > +    tc_hotplug_trigger,
> > > +    dig_hotplug_reg, hpd_icp,
> > > +    icp_tc_port_hotplug_long_detect
> > > );
> > > + }
> > > +
> > > + if (pin_mask)
> > > + intel_hpd_irq_handler(dev_priv, pin_mask,
> > > long_mask);
> > > +
> > > + if (pch_iir & ICP_GMBUS)
> > > + gmbus_irq_handler(dev_priv);
> > > +}
> > > +
> > >  static void spt_irq_handler(struct drm_i915_private *dev_priv, u32
> > > pch_iir)
> > >  {
> > >   u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
> > > @@ -2779,8 +2853,11 @@ gen8_de_irq_handler(struct drm_i915_private
> > > *dev_priv, u32 master_ctl)
> > >   I915_WRITE(SDEIIR, iir);
> > >   

Re: [Intel-gfx] [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping

[Lucas De Marchi]

On Thu, May 24, 2018 at 04:42:36PM -0700, Paulo Zanoni wrote:
> From: Mahesh Kumar 
> 
> ICP has GPIO pin 1/2 mapped to combo-phy ports & GPIO pins 9/10/11/12
> mapped to tc ports[1-4].
> This patch defines GPIOCTL registers for GPIO pins 9-12 & uses them in GPIO
> pin mapping table.
> 
> Cc: Anusha Srivatsa 
> Cc: Madhav Chauhan 
> Cc: Lucas De Marchi 
> Signed-off-by: Mahesh Kumar 
> ---
>  drivers/gpu/drm/i915/i915_reg.h   |  4 
>  drivers/gpu/drm/i915/intel_hdmi.c |  2 +-
>  drivers/gpu/drm/i915/intel_i2c.c  | 12 ++--
>  3 files changed, 11 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 452356a4af07..e48b717769b2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3015,6 +3015,10 @@ enum i915_power_well_id {
>  #define GPIOF_MMIO(0x5024)
>  #define GPIOG_MMIO(0x5028)
>  #define GPIOH_MMIO(0x502c)
> +#define GPIOJ_MMIO(0x5034)
> +#define GPIOK_MMIO(0x5038)
> +#define GPIOL_MMIO(0x503C)
> +#define GPIOM_MMIO(0x5040)

I was reviewing again this and I think again I was puzzled why the spec
has them as 0xc5034, ...

Probably same conclusion as I had when I first reviewed this. Maybe it
would be nice to add a comment to PCH_GPIO* saying PCH_GPIOA is used
only for calculation the gpio base and remove the rest. I can send this
is a separate patch, what do you think?

---8<---
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6953419881c4..40b9aa57078b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7442,12 +7442,8 @@ enum {
 #define  PORTE_HOTPLUG_SHORT_DETECT(1 << 0)
 #define  PORTE_HOTPLUG_LONG_DETECT (2 << 0)
 
+/* Used just for calculating the gpio base for PCH */
 #define PCH_GPIOA   _MMIO(0xc5010)
-#define PCH_GPIOB   _MMIO(0xc5014)
-#define PCH_GPIOC   _MMIO(0xc5018)
-#define PCH_GPIOD   _MMIO(0xc501c)
-#define PCH_GPIOE   _MMIO(0xc5020)
-#define PCH_GPIOF   _MMIO(0xc5024)
 
 #define PCH_GMBUS0 _MMIO(0xc5100)
 #define PCH_GMBUS1 _MMIO(0xc5104)
---8<---


Other than that,

Reviewed-by: Lucas De Marchi 

>  # define GPIO_CLOCK_DIR_MASK (1 << 0)
>  # define GPIO_CLOCK_DIR_IN   (0 << 1)
>  # define GPIO_CLOCK_DIR_OUT  (1 << 1)
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index 75f02a0e7d39..3db2459c79b1 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -2276,7 +2276,7 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private 
> *dev_priv,
>   ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
>   else if (HAS_PCH_CNP(dev_priv))
>   ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
> - else if (IS_ICELAKE(dev_priv))
> + else if (HAS_PCH_ICP(dev_priv))
>   ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
>   else
>   ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c 
> b/drivers/gpu/drm/i915/intel_i2c.c
> index e6875509bcd9..b91e418028cb 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -77,12 +77,12 @@ static const struct gmbus_pin gmbus_pins_cnp[] = {
>  };
>  
>  static const struct gmbus_pin gmbus_pins_icp[] = {
> - [GMBUS_PIN_1_BXT] = { "dpa", GPIOA },
> - [GMBUS_PIN_2_BXT] = { "dpb", GPIOB },
> - [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOC },
> - [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOD },
> - [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOE },
> - [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOF },
> + [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> + [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> + [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
> + [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
> + [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
>  };
>  
>  /* pin is expected to be valid */
> -- 
> 2.14.3
> 
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Re: [Intel-gfx] [PATCH 12/24] drm/i915/icl: Calculate link clock using the new registers

[Paulo Zanoni]

Em Seg, 2018-05-21 às 17:25 -0700, Paulo Zanoni escreveu:
> From: Arkadiusz Hiler 
> 
> Start using the new registers for ICL and on.

I previously put this patch in a series that did not make use of
cnl_calc_wrpll_link() for ICL yet. This series makes ICL run
cnl_calc_wrpll_link(), so this patch makes sense now.

Reviewed-by: Paulo Zanoni 

> 
> Cc: Manasi Navare 
> Cc: Rodrigo Vivi 
> Cc: Paulo Zanoni 
> Signed-off-by: Arkadiusz Hiler 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 9 +++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 0d8bed8e2200..32e7482b64dd 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1381,8 +1381,13 @@ static int cnl_calc_wrpll_link(struct
> drm_i915_private *dev_priv,
>   uint32_t cfgcr0, cfgcr1;
>   uint32_t p0, p1, p2, dco_freq, ref_clock;
>  
> - cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
> - cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
> + if (INTEL_GEN(dev_priv) >= 11) {
> + cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
> + cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
> + } else {
> + cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
> + cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
> + }
>  
>   p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
>   p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
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Re: [Intel-gfx] [PATCH 09/24] drm/i915/icl: Add Icelake PCH detection

[Paulo Zanoni]

Em Seg, 2018-05-21 às 17:25 -0700, Paulo Zanoni escreveu:
> From: Anusha Srivatsa 
> 
> This patch adds the support to detect PCH_ICP.
> 
> Suggested-by: Paulo Zanoni 

Reviewed-by: Paulo Zanoni 

> Signed-off-by: Anusha Srivatsa 
> Signed-off-by: Michel Thierry 
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c
> index 9c449b8d8eab..7b6f64321f11 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -233,6 +233,8 @@ intel_virt_detect_pch(const struct
> drm_i915_private *dev_priv)
>   id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
>   else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
>   id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
> + else if (IS_ICELAKE(dev_priv))
> + id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
>  
>   if (id)
>   DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
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Re: [Intel-gfx] [PATCH 06/24] drm/i915/ICL: Add register definition for DFLEXDPMLE

[Paulo Zanoni]

Em Seg, 2018-05-21 às 17:25 -0700, Paulo Zanoni escreveu:
> From: Manasi Navare 
> 
> DFLEXDPMLE register is required to tell the FIA hardware which
> main links of DP are enabled on TCC Connectors. FIA uses this
> information to program PHY to Controller signal mapping.
> This register is applicable in both TC connector's Alternate mode
> as well as DP connector mode.
> 
> Cc: Jani Nikula 
> Cc: Animesh Manna 
> Cc: Madhav Chauhan 
> Cc: Anusha Srivatsa 
> Cc: Paulo Zanoni 
> Signed-off-by: Manasi Navare 
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 28ce96ce0484..7f27fe2e38c7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1990,6 +1990,11 @@ enum i915_power_well_id {
>  _ICL_PORT_COMP_DW
> 10_A, \
>  _ICL_PORT_COMP_DW
> 10_B)
>  
> +/* ICL PHY DFLEX registers */
> +#define ICL_PORT_TX_DFLEXDPMLE1  _MMIO(0x1638C0)

We can probably remove the ICL_ prefix since the register did not exist
before.

With or without that:
Reviewed-by: Paulo Zanoni 

Note: the patch that uses the register was removed from the series due
to some problems identified. Will be upstreamed as soon as it's fixed.

> +#define   DFLEXDPMLE1_DPMLETC_MASK(n)(0xf << (4 * (n)))
> +#define   DFLEXDPMLE1_DPMLETC(n, x)  ((x) << (4 * (n)))
> +
>  /* BXT PHY Ref registers */
>  #define _PORT_REF_DW3_A  0x16218C
>  #define _PORT_REF_DW3_BC 0x6C18C
___
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Re: [Intel-gfx] [PATCH 05/24] drm/i915/icp: Add Interrupt Support

[Dhinakaran Pandiyan]

On Thu, 2018-05-24 at 16:53 -0700, Lucas De Marchi wrote:
> On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote:
> > 
> > From: Anusha Srivatsa 
> > 
> > This patch addresses Interrupts from south display engine (SDE).
> > 
> > ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
> > Introduce these registers and their intended values.
> > 
> > Introduce icp_irq_handler().
> > 
> > Cc: Paulo Zanoni 
> > Cc: Dhinakaran Pandiyan 
> > Cc: Ville Syrjala 
> > Signed-off-by: Anusha Srivatsa 
> > [Paulo: coding style bikesheds and rebases].
> > Signed-off-by: Paulo Zanoni 
> > ---
> >  drivers/gpu/drm/i915/i915_irq.c | 134
> > +++-
> >  drivers/gpu/drm/i915/i915_reg.h |  40 
> >  2 files changed, 172 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 9bcec5fdb9d0..6b109991786f 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -122,6 +122,15 @@ static const u32 hpd_tc_gen11[HPD_NUM_PINS] =
> > {
> >     [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> >  };
> >  
> > +static const u32 hpd_icp[HPD_NUM_PINS] = {
> > +   [HPD_PORT_A] = ICP_DDIA_HOTPLUG,
> > +   [HPD_PORT_B] = ICP_DDIB_HOTPLUG,
> > +   [HPD_PORT_C] = ICP_TC1_HOTPLUG,
> > +   [HPD_PORT_D] = ICP_TC2_HOTPLUG,
> > +   [HPD_PORT_E] = ICP_TC3_HOTPLUG,
> > +   [HPD_PORT_F] = ICP_TC4_HOTPLUG
> > +};
> > +
> >  /* IIR can theoretically queue up two events. Be paranoid. */
> >  #define GEN8_IRQ_RESET_NDX(type, which) do { \
> >     I915_WRITE(GEN8_##type##_IMR(which), 0x); \
> > @@ -1586,6 +1595,34 @@ static bool
> > bxt_port_hotplug_long_detect(enum port port, u32 val)
> >     }
> >  }
> >  
> > +static bool icp_ddi_port_hotplug_long_detect(enum port port, u32
> > val)
> > +{
> > +   switch (port) {
> > +   case PORT_A:
> > +   return val & ICP_DDIA_HPD_LONG_DETECT;
> > +   case PORT_B:
> > +   return val & ICP_DDIB_HPD_LONG_DETECT;
> > +   default:
> > +   return false;
> > +   }
> > +}
> > +
> > +static bool icp_tc_port_hotplug_long_detect(enum port port, u32
> > val)
> > +{
> > +   switch (port) {
> > +   case PORT_C:
> > +   return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> > +   case PORT_D:
> > +   return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> > +   case PORT_E:
> > +   return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> > +   case PORT_F:
> > +   return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> > +   default:
> > +   return false;
> > +   }
> > +}
> > +
> >  static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
> >  {
> >     switch (port) {
> > @@ -2377,6 +2414,43 @@ static void cpt_irq_handler(struct
> > drm_i915_private *dev_priv, u32 pch_iir)
> >     cpt_serr_int_handler(dev_priv);
> >  }
> >  
> > +static void icp_irq_handler(struct drm_i915_private *dev_priv, u32
> > pch_iir)
> > +{
> > +   u32 ddi_hotplug_trigger = pch_iir & ICP_SDE_DDI_MASK;
> > +   u32 tc_hotplug_trigger = pch_iir & ICP_SDE_TC_MASK;
> > +   u32 pin_mask = 0, long_mask = 0;
> > +
> > +   if (ddi_hotplug_trigger) {
> > +   u32 dig_hotplug_reg;
> > +
> > +   dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
> > +   I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
> > +
> > +   intel_get_hpd_pins(dev_priv, _mask,
> > _mask,
> > +      ddi_hotplug_trigger,
> > +      dig_hotplug_reg, hpd_icp,
> > +      icp_ddi_port_hotplug_long_detec
> > t);
> > +   }
> > +
> > +   if (tc_hotplug_trigger) {
> > +   u32 dig_hotplug_reg;
> > +
> > +   dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
> > +   I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
> > +
> > +   intel_get_hpd_pins(dev_priv, _mask,
> > _mask,
> > +      tc_hotplug_trigger,
> > +      dig_hotplug_reg, hpd_icp,
> > +      icp_tc_port_hotplug_long_detect
> > );
> > +   }
> > +
> > +   if (pin_mask)
> > +   intel_hpd_irq_handler(dev_priv, pin_mask,
> > long_mask);
> > +
> > +   if (pch_iir & ICP_GMBUS)
> > +   gmbus_irq_handler(dev_priv);
> > +}
> > +
> >  static void spt_irq_handler(struct drm_i915_private *dev_priv, u32
> > pch_iir)
> >  {
> >     u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
> > @@ -2779,8 +2853,11 @@ gen8_de_irq_handler(struct drm_i915_private
> > *dev_priv, u32 master_ctl)
> >     I915_WRITE(SDEIIR, iir);
> >     ret = IRQ_HANDLED;
> >  
> > -   if (HAS_PCH_SPT(dev_priv) ||
> > HAS_PCH_KBP(dev_priv) ||
> > -   HAS_PCH_CNP(dev_priv))
> > +   if (HAS_PCH_ICP(dev_priv))
> > + 

[Intel-gfx] ✗ Fi.CI.BAT: failure for More ICL display patches (rev7)

[Patchwork]

== Series Details ==

Series: More ICL display patches (rev7)
URL   : https://patchwork.freedesktop.org/series/43546/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4234 -> Patchwork_9111 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9111 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9111, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43546/revisions/7/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9111:

  === IGT changes ===

 Possible regressions 

igt@drv_module_reload@basic-reload-inject:
  fi-ilk-650: PASS -> DMESG-WARN


== Known issues ==

  Here are the changes found in Patchwork_9111 that come from known issues:

  === IGT changes ===

 Possible fixes 

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
  fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS


  fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951


== Participating hosts (44 -> 39) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4234 -> Patchwork_9111

  CI_DRM_4234: 399e4206d849c5667d8553911e0035c53cd9c24e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4498: f9ecb79ad8b02278cfdb5b82495df47061c04f8f @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9111: 0e9dc804376bf800ffdb84a2ffde54c720c9f295 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

0e9dc804376b drm/i915/icl: update VBT's child_device_config flags2 field
2a7fade59ca8 drm/i915/icl: toggle PHY clock gating around link training
76747abf5771 drm/i915/icl: program MG_DP_MODE
30221f17596f drm/i915/icl: Update FIA supported lane count for hpd.
e86c6a8b3512 drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI
8e31a26476b9 drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for 
DP
6463e56dbfc4 drm/i915/icl: store the port type for TC ports
8a7fe1b43d10 drm/i915/icl: implement icl_digital_port_connected()
c7b5b502d19d drm/i915/icl: Add 10-bit support for hdmi
91188c6ba486 drm/i915/icl: Handle hotplug interrupts for DP over TBT
3292e78e766b drm/i915/icl: compute the TBT PLL registers
089d3d15c278 drm/i915/icl: start adding the TBT pll
87436cc87084 drm/i915/icl: unconditionally init DDI for every port
ea5e8efbb415 drm/i915/icl: Calculate link clock using the new registers
7aacef71bf5a drm/i915/icl: Get DDI clock for ICL based on PLLs.
914247ff4516 drm/i915/icl: add icelake_get_ddi_pll()
ff4263dd5056 drm/i915/icl: Add Icelake PCH detection
0452d69471d2 drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin
0aa9dd7d6752 drm/i915/icl: Add DDI HDMI level selection for ICL
23bec0ea27e5 drm/i915/ICL: Add register definition for DFLEXDPMLE
bb897d8be18f drm/i915/icp: Add Interrupt Support
dbbc1dcd8f1d drm/i915/icl: Support for TC North Display interrupts
8b1806b8b1e1 drm/i915/icl: introduce tc_port
7913b8e944f7 drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
d9841751b963 drm/i915/icl: Extend AUX F interrupts to ICL

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9111/issues.html
___
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Re: [Intel-gfx] [PATCH 29/24] drm/i915/icl: DP_AUX_E is valid on ICL+

[Paulo Zanoni]

Em Qui, 2018-05-24 às 16:42 -0700, Paulo Zanoni escreveu:
> From: James Ausmus 
> 
> Add support for DP_AUX_E. Here we also introduce the bits for the AUX
> power well E, however ICL power well support is still not enabled
> yet,
> so the power well is not used.
> 
> Cc: Paulo Zanoni 
> Cc: Rodrigo Vivi 
> Cc: Dhinakaran Pandiyan 
> Signed-off-by: James Ausmus 
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 1 +
>  drivers/gpu/drm/i915/i915_irq.c | 6 ++
>  drivers/gpu/drm/i915/i915_reg.h | 8 
>  drivers/gpu/drm/i915/intel_display.h| 3 ++-
>  drivers/gpu/drm/i915/intel_dp.c | 7 +++
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++
>  6 files changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index b86ed6401120..a85329f053dc 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1005,6 +1005,7 @@ enum modeset_restore {
>  #define DP_AUX_B 0x10
>  #define DP_AUX_C 0x20
>  #define DP_AUX_D 0x30
> +#define DP_AUX_E 0x50
>  #define DP_AUX_F 0x60
>  
>  #define DDC_PIN_B  0x05
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index 9f1b01ca4ed1..672bfaf2052a 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2783,6 +2783,9 @@ gen8_de_irq_handler(struct drm_i915_private
> *dev_priv, u32 master_ctl)
>   GEN9_AUX_CHANNEL_C |
>   GEN9_AUX_CHANNEL_D;
>  
> + if (INTEL_GEN(dev_priv) >= 11)
> + tmp_mask |= ICL_AUX_CHANNEL_E;
> +
>   if (IS_CNL_WITH_PORT_F(dev_priv) ||
>   INTEL_GEN(dev_priv) >= 11)
>   tmp_mask |= CNL_AUX_CHANNEL_F;
> @@ -4168,6 +4171,9 @@ static void gen8_de_irq_postinstall(struct
> drm_i915_private *dev_priv)
>   de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
>   }
>  
> + if (INTEL_GEN(dev_priv) >= 11)
> + de_port_masked |= ICL_AUX_CHANNEL_E;
> +
>   if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >=
> 11)
>   de_port_masked |= CNL_AUX_CHANNEL_F;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index ae7070c0806d..ba5285348534 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5342,6 +5342,13 @@ enum {
>  #define _DPD_AUX_CH_DATA4(dev_priv->info.display_mmio_offset 
> + 0x64320)
>  #define _DPD_AUX_CH_DATA5(dev_priv->info.display_mmio_offset 
> + 0x64324)
>  
> +#define _DPE_AUX_CH_CTL  (dev_priv-
> >info.display_mmio_offset + 0x64410)
> +#define _DPE_AUX_CH_DATA1(dev_priv->info.display_mmio_offset 
> + 0x64414)
> +#define _DPE_AUX_CH_DATA2(dev_priv->info.display_mmio_offset 
> + 0x64418)
> +#define _DPE_AUX_CH_DATA3(dev_priv->info.display_mmio_offset 
> + 0x6441c)
> +#define _DPE_AUX_CH_DATA4(dev_priv->info.display_mmio_offset 
> + 0x64420)
> +#define _DPE_AUX_CH_DATA5(dev_priv->info.display_mmio_offset 
> + 0x64424)
> +
>  #define _DPF_AUX_CH_CTL  (dev_priv-
> >info.display_mmio_offset + 0x64510)
>  #define _DPF_AUX_CH_DATA1(dev_priv->info.display_mmio_offset 
> + 0x64514)
>  #define _DPF_AUX_CH_DATA2(dev_priv->info.display_mmio_offset 
> + 0x64518)
> @@ -7040,6 +7047,7 @@ enum {
>  #define GEN8_DE_PORT_IMR _MMIO(0x4)
>  #define GEN8_DE_PORT_IIR _MMIO(0x8)
>  #define GEN8_DE_PORT_IER _MMIO(0xc)
> +#define  ICL_AUX_CHANNEL_E   (1 << 29)
>  #define  CNL_AUX_CHANNEL_F   (1 << 28)
>  #define  GEN9_AUX_CHANNEL_D  (1 << 27)
>  #define  GEN9_AUX_CHANNEL_C  (1 << 26)
> diff --git a/drivers/gpu/drm/i915/intel_display.h
> b/drivers/gpu/drm/i915/intel_display.h
> index fcedc600706b..653d85f8a374 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -162,7 +162,7 @@ enum aux_ch {
>   AUX_CH_B,
>   AUX_CH_C,
>   AUX_CH_D,
> - _AUX_CH_E, /* does not exist */
> + AUX_CH_E, /* ICL+ */
>   AUX_CH_F,
>  };
>  
> @@ -203,6 +203,7 @@ enum intel_display_power_domain {
>   POWER_DOMAIN_AUX_B,
>   POWER_DOMAIN_AUX_C,
>   POWER_DOMAIN_AUX_D,
> + POWER_DOMAIN_AUX_E,
>   POWER_DOMAIN_AUX_F,
>   POWER_DOMAIN_AUX_IO_A,
>   POWER_DOMAIN_GMBUS,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index bcc3f330b301..588a5de3a8ee 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1527,6 +1527,9 @@ static enum aux_ch intel_aux_ch(struct intel_dp
> *intel_dp)
>   case DP_AUX_D:
>   aux_ch = 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for More ICL display patches (rev7)

[Patchwork]

== Series Details ==

Series: More ICL display patches (rev7)
URL   : https://patchwork.freedesktop.org/series/43546/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/icl: Extend AUX F interrupts to ICL
Okay!

Commit: drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
Okay!

Commit: drm/i915/icl: introduce tc_port
Okay!

Commit: drm/i915/icl: Support for TC North Display interrupts
Okay!

Commit: drm/i915/icp: Add Interrupt Support
Okay!

Commit: drm/i915/ICL: Add register definition for DFLEXDPMLE
Okay!

Commit: drm/i915/icl: Add DDI HDMI level selection for ICL
Okay!

Commit: drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin
Okay!

Commit: drm/i915/icl: Add Icelake PCH detection
Okay!

Commit: drm/i915/icl: add icelake_get_ddi_pll()
Okay!

Commit: drm/i915/icl: Get DDI clock for ICL based on PLLs.
Okay!

Commit: drm/i915/icl: Calculate link clock using the new registers
Okay!

Commit: drm/i915/icl: unconditionally init DDI for every port
Okay!

Commit: drm/i915/icl: start adding the TBT pll
Okay!

Commit: drm/i915/icl: compute the TBT PLL registers
Okay!

Commit: drm/i915/icl: Handle hotplug interrupts for DP over TBT
Okay!

Commit: drm/i915/icl: Add 10-bit support for hdmi
Okay!

Commit: drm/i915/icl: implement icl_digital_port_connected()
Okay!

Commit: drm/i915/icl: store the port type for TC ports
Okay!

Commit: drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP
Okay!

Commit: drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI
Okay!

Commit: drm/i915/icl: Update FIA supported lane count for hpd.
-O:drivers/gpu/drm/i915/intel_dp.c:186:16: warning: expression using 
sizeof(void)
-O:drivers/gpu/drm/i915/intel_dp.c:186:16: warning: expression using 
sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:217:16: warning: expression using sizeof(void)

Commit: drm/i915/icl: program MG_DP_MODE
Okay!

Commit: drm/i915/icl: toggle PHY clock gating around link training
Okay!

Commit: drm/i915/icl: update VBT's child_device_config flags2 field
Okay!

___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for More ICL display patches (rev7)

[Patchwork]

== Series Details ==

Series: More ICL display patches (rev7)
URL   : https://patchwork.freedesktop.org/series/43546/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
d9841751b963 drm/i915/icl: Extend AUX F interrupts to ICL
7913b8e944f7 drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
8b1806b8b1e1 drm/i915/icl: introduce tc_port
dbbc1dcd8f1d drm/i915/icl: Support for TC North Display interrupts
bb897d8be18f drm/i915/icp: Add Interrupt Support
23bec0ea27e5 drm/i915/ICL: Add register definition for DFLEXDPMLE
0aa9dd7d6752 drm/i915/icl: Add DDI HDMI level selection for ICL
0452d69471d2 drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin
ff4263dd5056 drm/i915/icl: Add Icelake PCH detection
914247ff4516 drm/i915/icl: add icelake_get_ddi_pll()
7aacef71bf5a drm/i915/icl: Get DDI clock for ICL based on PLLs.
ea5e8efbb415 drm/i915/icl: Calculate link clock using the new registers
87436cc87084 drm/i915/icl: unconditionally init DDI for every port
089d3d15c278 drm/i915/icl: start adding the TBT pll
-:162: CHECK:LINE_SPACING: Please use a blank line after 
function/struct/union/enum declarations
#162: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.h:137:
 };
+#define I915_NUM_PLLS 7

total: 0 errors, 0 warnings, 1 checks, 129 lines checked
3292e78e766b drm/i915/icl: compute the TBT PLL registers
-:18: CHECK:CAMELCASE: Avoid CamelCase: 
#18: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2455:
+static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {

-:23: CHECK:CAMELCASE: Avoid CamelCase: 
#23: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2460:
+static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {

total: 0 errors, 0 warnings, 2 checks, 51 lines checked
91188c6ba486 drm/i915/icl: Handle hotplug interrupts for DP over TBT
c7b5b502d19d drm/i915/icl: Add 10-bit support for hdmi
8a7fe1b43d10 drm/i915/icl: implement icl_digital_port_connected()
6463e56dbfc4 drm/i915/icl: store the port type for TC ports
8e31a26476b9 drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for 
DP
e86c6a8b3512 drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI
30221f17596f drm/i915/icl: Update FIA supported lane count for hpd.
76747abf5771 drm/i915/icl: program MG_DP_MODE
2a7fade59ca8 drm/i915/icl: toggle PHY clock gating around link training
0e9dc804376b drm/i915/icl: update VBT's child_device_config flags2 field

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Re: [Intel-gfx] [PATCH 05/24] drm/i915/icp: Add Interrupt Support

[Lucas De Marchi]

On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote:
> From: Anusha Srivatsa 
> 
> This patch addresses Interrupts from south display engine (SDE).
> 
> ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
> Introduce these registers and their intended values.
> 
> Introduce icp_irq_handler().
> 
> Cc: Paulo Zanoni 
> Cc: Dhinakaran Pandiyan 
> Cc: Ville Syrjala 
> Signed-off-by: Anusha Srivatsa 
> [Paulo: coding style bikesheds and rebases].
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 134 
> +++-
>  drivers/gpu/drm/i915/i915_reg.h |  40 
>  2 files changed, 172 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 9bcec5fdb9d0..6b109991786f 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -122,6 +122,15 @@ static const u32 hpd_tc_gen11[HPD_NUM_PINS] = {
>   [HPD_PORT_F] = GEN11_TC4_HOTPLUG
>  };
>  
> +static const u32 hpd_icp[HPD_NUM_PINS] = {
> + [HPD_PORT_A] = ICP_DDIA_HOTPLUG,
> + [HPD_PORT_B] = ICP_DDIB_HOTPLUG,
> + [HPD_PORT_C] = ICP_TC1_HOTPLUG,
> + [HPD_PORT_D] = ICP_TC2_HOTPLUG,
> + [HPD_PORT_E] = ICP_TC3_HOTPLUG,
> + [HPD_PORT_F] = ICP_TC4_HOTPLUG
> +};
> +
>  /* IIR can theoretically queue up two events. Be paranoid. */
>  #define GEN8_IRQ_RESET_NDX(type, which) do { \
>   I915_WRITE(GEN8_##type##_IMR(which), 0x); \
> @@ -1586,6 +1595,34 @@ static bool bxt_port_hotplug_long_detect(enum port 
> port, u32 val)
>   }
>  }
>  
> +static bool icp_ddi_port_hotplug_long_detect(enum port port, u32 val)
> +{
> + switch (port) {
> + case PORT_A:
> + return val & ICP_DDIA_HPD_LONG_DETECT;
> + case PORT_B:
> + return val & ICP_DDIB_HPD_LONG_DETECT;
> + default:
> + return false;
> + }
> +}
> +
> +static bool icp_tc_port_hotplug_long_detect(enum port port, u32 val)
> +{
> + switch (port) {
> + case PORT_C:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> + case PORT_D:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> + case PORT_E:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> + case PORT_F:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> + default:
> + return false;
> + }
> +}
> +
>  static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
>  {
>   switch (port) {
> @@ -2377,6 +2414,43 @@ static void cpt_irq_handler(struct drm_i915_private 
> *dev_priv, u32 pch_iir)
>   cpt_serr_int_handler(dev_priv);
>  }
>  
> +static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> +{
> + u32 ddi_hotplug_trigger = pch_iir & ICP_SDE_DDI_MASK;
> + u32 tc_hotplug_trigger = pch_iir & ICP_SDE_TC_MASK;
> + u32 pin_mask = 0, long_mask = 0;
> +
> + if (ddi_hotplug_trigger) {
> + u32 dig_hotplug_reg;
> +
> + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
> + I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
> +
> + intel_get_hpd_pins(dev_priv, _mask, _mask,
> +ddi_hotplug_trigger,
> +dig_hotplug_reg, hpd_icp,
> +icp_ddi_port_hotplug_long_detect);
> + }
> +
> + if (tc_hotplug_trigger) {
> + u32 dig_hotplug_reg;
> +
> + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
> + I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
> +
> + intel_get_hpd_pins(dev_priv, _mask, _mask,
> +tc_hotplug_trigger,
> +dig_hotplug_reg, hpd_icp,
> +icp_tc_port_hotplug_long_detect);
> + }
> +
> + if (pin_mask)
> + intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> +
> + if (pch_iir & ICP_GMBUS)
> + gmbus_irq_handler(dev_priv);
> +}
> +
>  static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
>  {
>   u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
> @@ -2779,8 +2853,11 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, 
> u32 master_ctl)
>   I915_WRITE(SDEIIR, iir);
>   ret = IRQ_HANDLED;
>  
> - if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
> - HAS_PCH_CNP(dev_priv))
> + if (HAS_PCH_ICP(dev_priv))
> + icp_irq_handler(dev_priv, iir);
> + else if (HAS_PCH_SPT(dev_priv) ||
> +  HAS_PCH_KBP(dev_priv) ||
> +  HAS_PCH_CNP(dev_priv))
>

[Intel-gfx] [PATCH 29/24] drm/i915/icl: DP_AUX_E is valid on ICL+

[Paulo Zanoni]

From: James Ausmus 

Add support for DP_AUX_E. Here we also introduce the bits for the AUX
power well E, however ICL power well support is still not enabled yet,
so the power well is not used.

Cc: Paulo Zanoni 
Cc: Rodrigo Vivi 
Cc: Dhinakaran Pandiyan 
Signed-off-by: James Ausmus 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_drv.h | 1 +
 drivers/gpu/drm/i915/i915_irq.c | 6 ++
 drivers/gpu/drm/i915/i915_reg.h | 8 
 drivers/gpu/drm/i915/intel_display.h| 3 ++-
 drivers/gpu/drm/i915/intel_dp.c | 7 +++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++
 6 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b86ed6401120..a85329f053dc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1005,6 +1005,7 @@ enum modeset_restore {
 #define DP_AUX_B 0x10
 #define DP_AUX_C 0x20
 #define DP_AUX_D 0x30
+#define DP_AUX_E 0x50
 #define DP_AUX_F 0x60
 
 #define DDC_PIN_B  0x05
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9f1b01ca4ed1..672bfaf2052a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2783,6 +2783,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, 
u32 master_ctl)
GEN9_AUX_CHANNEL_C |
GEN9_AUX_CHANNEL_D;
 
+   if (INTEL_GEN(dev_priv) >= 11)
+   tmp_mask |= ICL_AUX_CHANNEL_E;
+
if (IS_CNL_WITH_PORT_F(dev_priv) ||
INTEL_GEN(dev_priv) >= 11)
tmp_mask |= CNL_AUX_CHANNEL_F;
@@ -4168,6 +4171,9 @@ static void gen8_de_irq_postinstall(struct 
drm_i915_private *dev_priv)
de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
}
 
+   if (INTEL_GEN(dev_priv) >= 11)
+   de_port_masked |= ICL_AUX_CHANNEL_E;
+
if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >= 11)
de_port_masked |= CNL_AUX_CHANNEL_F;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ae7070c0806d..ba5285348534 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5342,6 +5342,13 @@ enum {
 #define _DPD_AUX_CH_DATA4  (dev_priv->info.display_mmio_offset + 0x64320)
 #define _DPD_AUX_CH_DATA5  (dev_priv->info.display_mmio_offset + 0x64324)
 
+#define _DPE_AUX_CH_CTL(dev_priv->info.display_mmio_offset + 
0x64410)
+#define _DPE_AUX_CH_DATA1  (dev_priv->info.display_mmio_offset + 0x64414)
+#define _DPE_AUX_CH_DATA2  (dev_priv->info.display_mmio_offset + 0x64418)
+#define _DPE_AUX_CH_DATA3  (dev_priv->info.display_mmio_offset + 0x6441c)
+#define _DPE_AUX_CH_DATA4  (dev_priv->info.display_mmio_offset + 0x64420)
+#define _DPE_AUX_CH_DATA5  (dev_priv->info.display_mmio_offset + 0x64424)
+
 #define _DPF_AUX_CH_CTL(dev_priv->info.display_mmio_offset + 
0x64510)
 #define _DPF_AUX_CH_DATA1  (dev_priv->info.display_mmio_offset + 0x64514)
 #define _DPF_AUX_CH_DATA2  (dev_priv->info.display_mmio_offset + 0x64518)
@@ -7040,6 +7047,7 @@ enum {
 #define GEN8_DE_PORT_IMR _MMIO(0x4)
 #define GEN8_DE_PORT_IIR _MMIO(0x8)
 #define GEN8_DE_PORT_IER _MMIO(0xc)
+#define  ICL_AUX_CHANNEL_E (1 << 29)
 #define  CNL_AUX_CHANNEL_F (1 << 28)
 #define  GEN9_AUX_CHANNEL_D(1 << 27)
 #define  GEN9_AUX_CHANNEL_C(1 << 26)
diff --git a/drivers/gpu/drm/i915/intel_display.h 
b/drivers/gpu/drm/i915/intel_display.h
index fcedc600706b..653d85f8a374 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -162,7 +162,7 @@ enum aux_ch {
AUX_CH_B,
AUX_CH_C,
AUX_CH_D,
-   _AUX_CH_E, /* does not exist */
+   AUX_CH_E, /* ICL+ */
AUX_CH_F,
 };
 
@@ -203,6 +203,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_AUX_D,
+   POWER_DOMAIN_AUX_E,
POWER_DOMAIN_AUX_F,
POWER_DOMAIN_AUX_IO_A,
POWER_DOMAIN_GMBUS,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index bcc3f330b301..588a5de3a8ee 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1527,6 +1527,9 @@ static enum aux_ch intel_aux_ch(struct intel_dp *intel_dp)
case DP_AUX_D:
aux_ch = AUX_CH_D;
break;
+   case DP_AUX_E:
+   aux_ch = AUX_CH_E;
+   break;
case DP_AUX_F:
aux_ch = AUX_CH_F;
break;
@@ -1554,6 +1557,8 @@ 

[Intel-gfx] [PATCH 30/24] drm/i915/icl: update VBT's child_device_config flags2 field

[Paulo Zanoni]

Some bits from the flags2 field are going to be used in the next
patches, so replace the whole-byte definition with the actual bits and
document their versions.

This patch is based on a patch by Animesh Manna.

Cc: Animesh Manna 
Credits-to: Animesh Manna 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_vbt_defs.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/intel_vbt_defs.h
index 7c798c18600e..4dc907e47262 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -420,7 +420,9 @@ struct child_device_config {
u16 extended_type;
u8 dvo_function;
u8 dp_usb_type_c:1; /* 195 */
-   u8 flags2_reserved:7;   /* 195 */
+   u8 tbt:1;   /* 209 */
+   u8 flags2_reserved:2;   /* 195 */
+   u8 dp_port_trace_length:4;  /* 209 */
u8 dp_gpio_index;   /* 195 */
u16 dp_gpio_pin_num;/* 195 */
u8 dp_iboost_level:4;   /* 196 */
-- 
2.14.3

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[Intel-gfx] [PATCH 27/24] drm/i915/dp: Add support for HBR3 and TPS4 during link training

[Paulo Zanoni]

From: Manasi Navare 

DP spec 1.4 supports training pattern set 4 (TPS4) for HBR3 link
rate. This will be used in link training's channel equalization
phase if supported by both source and sink.
This patch adds the helpers to check if HBR3 is supported and uses
TPS4 in training pattern selection during link training.

Cc: James Ausmus 
Cc: Rodrigo Vivi 
Cc: Jani Nikula 
Signed-off-by: Manasi Navare 
---
 drivers/gpu/drm/i915/i915_reg.h   |  1 +
 drivers/gpu/drm/i915/intel_dp.c   | 17 +---
 drivers/gpu/drm/i915/intel_dp_link_training.c | 39 +++
 drivers/gpu/drm/i915/intel_drv.h  |  1 +
 4 files changed, 44 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e48b717769b2..ae7070c0806d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8791,6 +8791,7 @@ enum skl_power_gate {
 #define  DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
 #define  DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
 #define  DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
+#define  DP_TP_CTL_LINK_TRAIN_PAT4 (5<<8)
 #define  DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
 #define  DP_TP_CTL_LINK_TRAIN_NORMAL   (3<<8)
 #define  DP_TP_CTL_SCRAMBLE_DISABLE(1<<7)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3ee8e74cf2b8..bcc3f330b301 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1721,6 +1721,13 @@ bool intel_dp_source_supports_hbr2(struct intel_dp 
*intel_dp)
return max_rate >= 54;
 }
 
+bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
+{
+   int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
+
+   return max_rate >= 81;
+}
+
 static void
 intel_dp_set_clock(struct intel_encoder *encoder,
   struct intel_crtc_state *pipe_config)
@@ -3046,10 +3053,11 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
enum port port = intel_dig_port->base.port;
+   uint8_t train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
 
-   if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
+   if (dp_train_pat & train_pat_mask)
DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
- dp_train_pat & DP_TRAINING_PATTERN_MASK);
+ dp_train_pat & train_pat_mask);
 
if (HAS_DDI(dev_priv)) {
uint32_t temp = I915_READ(DP_TP_CTL(port));
@@ -3060,7 +3068,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
 
temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
-   switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
+   switch (dp_train_pat & train_pat_mask) {
case DP_TRAINING_PATTERN_DISABLE:
temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
 
@@ -3074,6 +3082,9 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
case DP_TRAINING_PATTERN_3:
temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
break;
+   case DP_TRAINING_PATTERN_4:
+   temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
+   break;
}
I915_WRITE(DP_TP_CTL(port), temp);
 
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
b/drivers/gpu/drm/i915/intel_dp_link_training.c
index 3fcaa98b9055..4da6e33c7fa1 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -219,14 +219,30 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
*intel_dp)
 }
 
 /*
- * Pick training pattern for channel equalization. Training Pattern 3 for HBR2
+ * Pick training pattern for channel equalization. Training pattern 4 for HBR3
+ * or for 1.4 devices that support it, training Pattern 3 for HBR2
  * or 1.2 devices that support it, Training Pattern 2 otherwise.
  */
 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
 {
-   u32 training_pattern = DP_TRAINING_PATTERN_2;
-   bool source_tps3, sink_tps3;
+   bool source_tps3, sink_tps3, source_tps4, sink_tps4;
 
+   /*
+* Intel platforms that support HBR3 also support TPS4. It is mandatory
+* for all downstream devices that support HBR3. There are no known eDP
+* panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1
+* specification.
+*/
+   source_tps4 = intel_dp_source_supports_hbr3(intel_dp);
+   sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
+   if (source_tps4 && 

[Intel-gfx] [PATCH 28/24] drm/i915/icl: implement DVFS for ICL

[Paulo Zanoni]

ICL DVFS is almost the same as CNL, except for the CDCLK/DDICLK
table. Implement it just like CNL does.

References: commit 48469eced282 ("drm/i915: Use cdclk_state->voltage
 on CNL")
References: commit 53e9bf5e8159 ("drm/i915: Adjust system agent
 voltage on CNL if required by DDI ports")
Cc: Ville Syrjälä 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_cdclk.c | 46 +++---
 drivers/gpu/drm/i915/intel_ddi.c   |  2 ++
 2 files changed, 45 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
b/drivers/gpu/drm/i915/intel_cdclk.c
index 704ddb4d3ca7..642f1e542a62 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1861,11 +1861,35 @@ static void icl_set_cdclk(struct drm_i915_private 
*dev_priv,
  skl_cdclk_decimal(cdclk));
 
mutex_lock(_priv->pcu_lock);
-   /* TODO: add proper DVFS support. */
-   sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 2);
+   sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+   cdclk_state->voltage_level);
mutex_unlock(_priv->pcu_lock);
 
intel_update_cdclk(dev_priv);
+
+   /*
+* Can't read out the voltage level :(
+* Let's just assume everything is as expected.
+*/
+   dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
+}
+
+static u8 icl_calc_voltage_level(int cdclk)
+{
+   switch (cdclk) {
+   case 5:
+   case 307200:
+   case 312000:
+   return 0;
+   case 556800:
+   case 552000:
+   return 1;
+   default:
+   MISSING_CASE(cdclk);
+   case 652800:
+   case 648000:
+   return 2;
+   }
 }
 
 static void icl_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1899,7 +1923,7 @@ static void icl_get_cdclk(struct drm_i915_private 
*dev_priv,
 */
cdclk_state->vco = 0;
cdclk_state->cdclk = cdclk_state->bypass;
-   return;
+   goto out;
}
 
cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
@@ -1908,6 +1932,14 @@ static void icl_get_cdclk(struct drm_i915_private 
*dev_priv,
WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
 
cdclk_state->cdclk = cdclk_state->vco / 2;
+
+out:
+   /*
+* Can't read this out :( Let's assume it's
+* at least what the CDCLK frequency requires.
+*/
+   cdclk_state->voltage_level =
+   icl_calc_voltage_level(cdclk_state->cdclk);
 }
 
 /**
@@ -1950,6 +1982,8 @@ void icl_init_cdclk(struct drm_i915_private *dev_priv)
sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
 sanitized_state.cdclk);
+   sanitized_state.voltage_level =
+   icl_calc_voltage_level(sanitized_state.cdclk);
 
icl_set_cdclk(dev_priv, _state);
 }
@@ -1967,6 +2001,7 @@ void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
 
cdclk_state.cdclk = cdclk_state.bypass;
cdclk_state.vco = 0;
+   cdclk_state.voltage_level = icl_calc_voltage_level(cdclk_state.cdclk);
 
icl_set_cdclk(dev_priv, _state);
 }
@@ -2470,6 +2505,9 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state 
*state)
 
intel_state->cdclk.logical.vco = vco;
intel_state->cdclk.logical.cdclk = cdclk;
+   intel_state->cdclk.logical.voltage_level =
+   max(icl_calc_voltage_level(cdclk),
+   cnl_compute_min_voltage_level(intel_state));
 
if (!intel_state->active_crtcs) {
cdclk = icl_calc_cdclk(0, ref);
@@ -2477,6 +2515,8 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state 
*state)
 
intel_state->cdclk.actual.vco = vco;
intel_state->cdclk.actual.cdclk = cdclk;
+   intel_state->cdclk.actual.voltage_level =
+   icl_calc_voltage_level(cdclk);
} else {
intel_state->cdclk.actual = intel_state->cdclk.logical;
}
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 610c2d7d499c..6cdcbf9bf098 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3073,6 +3073,8 @@ void intel_ddi_compute_min_voltage_level(struct 
drm_i915_private *dev_priv,
 {
if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
crtc_state->min_voltage_level = 2;
+   else if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)
+   crtc_state->min_voltage_level = 1;
 }
 
 void intel_ddi_get_config(struct intel_encoder *encoder,
-- 
2.14.3

___
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[Intel-gfx] [PATCH 26/24] drm/i915/icl: Add allowed DP rates for Icelake

[Paulo Zanoni]

From: Manasi Navare 

For ICL, on Combo PHY the allowed max rates are:
 - HBR3 8.1 eDP (DDIA)
 - HBR2 5.4 DisplayPort (DDIB)
and for MG PHY/TC DDI Ports allowed DP rates are:
 - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
 - DP on legacy connector - DDIC/D/E/F)

Cc: Rodrigo Vivi 
Cc: Jani Nikula 
Cc: James Ausmus 
Signed-off-by: Manasi Navare 
Signed-off-by: James Ausmus 
---
 drivers/gpu/drm/i915/intel_dp.c | 21 +++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5109023abe28..3ee8e74cf2b8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -419,6 +419,20 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
return 81;
 }
 
+static int icl_max_source_rate(struct intel_dp *intel_dp)
+{
+   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+   enum port port = dig_port->base.port;
+
+   /* On Combo PHY port A max speed is HBR3 for all Vccio voltages
+* and on Combo PHY Port B the maximum supported is HBR2.
+*/
+   if (port == PORT_B)
+   return 54;
+
+   return 81;
+}
+
 static void
 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 {
@@ -448,10 +462,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
/* This should only be done once */
WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 
-   if (IS_CANNONLAKE(dev_priv)) {
+   if (INTEL_GEN(dev_priv) >= 10) {
source_rates = cnl_rates;
size = ARRAY_SIZE(cnl_rates);
-   max_rate = cnl_max_source_rate(intel_dp);
+   if (IS_ICELAKE(dev_priv))
+   max_rate = icl_max_source_rate(intel_dp);
+   else
+   max_rate = cnl_max_source_rate(intel_dp);
} else if (IS_GEN9_LP(dev_priv)) {
source_rates = bxt_rates;
size = ARRAY_SIZE(bxt_rates);
-- 
2.14.3

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[Intel-gfx] [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping

[Paulo Zanoni]

From: Mahesh Kumar 

ICP has GPIO pin 1/2 mapped to combo-phy ports & GPIO pins 9/10/11/12
mapped to tc ports[1-4].
This patch defines GPIOCTL registers for GPIO pins 9-12 & uses them in GPIO
pin mapping table.

Cc: Anusha Srivatsa 
Cc: Madhav Chauhan 
Cc: Lucas De Marchi 
Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/i915_reg.h   |  4 
 drivers/gpu/drm/i915/intel_hdmi.c |  2 +-
 drivers/gpu/drm/i915/intel_i2c.c  | 12 ++--
 3 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 452356a4af07..e48b717769b2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3015,6 +3015,10 @@ enum i915_power_well_id {
 #define GPIOF  _MMIO(0x5024)
 #define GPIOG  _MMIO(0x5028)
 #define GPIOH  _MMIO(0x502c)
+#define GPIOJ  _MMIO(0x5034)
+#define GPIOK  _MMIO(0x5038)
+#define GPIOL  _MMIO(0x503C)
+#define GPIOM  _MMIO(0x5040)
 # define GPIO_CLOCK_DIR_MASK   (1 << 0)
 # define GPIO_CLOCK_DIR_IN (0 << 1)
 # define GPIO_CLOCK_DIR_OUT(1 << 1)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 75f02a0e7d39..3db2459c79b1 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2276,7 +2276,7 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private 
*dev_priv,
ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
else if (HAS_PCH_CNP(dev_priv))
ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
-   else if (IS_ICELAKE(dev_priv))
+   else if (HAS_PCH_ICP(dev_priv))
ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
else
ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index e6875509bcd9..b91e418028cb 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -77,12 +77,12 @@ static const struct gmbus_pin gmbus_pins_cnp[] = {
 };
 
 static const struct gmbus_pin gmbus_pins_icp[] = {
-   [GMBUS_PIN_1_BXT] = { "dpa", GPIOA },
-   [GMBUS_PIN_2_BXT] = { "dpb", GPIOB },
-   [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOC },
-   [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOD },
-   [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOE },
-   [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOF },
+   [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+   [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+   [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
+   [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
+   [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
+   [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
 };
 
 /* pin is expected to be valid */
-- 
2.14.3

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Re: [Intel-gfx] [PATCH 02/24] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC

[Dhinakaran Pandiyan]

On Thu, 2018-05-24 at 12:22 +0300, Mika Kuoppala wrote:
> Paulo Zanoni  writes:
> 
> > 
> > From: Dhinakaran Pandiyan 
> > 
> > The Graphics System Event(GSE) interrupt bit has a new location in
> > the
> > GU_MISC_INTERRUPT_{IIR, ISR, IMR, IER} registers. Since GSE was the
> > only
> > DE_MISC interrupt that was enabled, with this change we don't
> > enable/handle
> > any of DE_MISC interrupts for gen11. Credits to Paulo for pointing
> > out
> > the register change.
> > 
> > Signed-off-by: Dhinakaran Pandiyan 
> > [Paulo: bikesheds and rebases]
> > Signed-off-by: Paulo Zanoni 
> > ---
> >  drivers/gpu/drm/i915/i915_irq.c | 38
> > --
> >  drivers/gpu/drm/i915/i915_reg.h |  7 +++
> >  2 files changed, 43 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 2fd92a886789..dde938bbfb0a 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2605,7 +2605,8 @@ gen8_de_irq_handler(struct drm_i915_private
> > *dev_priv, u32 master_ctl)
> >     I915_WRITE(GEN8_DE_MISC_IIR, iir);
> >     ret = IRQ_HANDLED;
> >  
> > -   if (iir & GEN8_DE_MISC_GSE) {
> > +   if (INTEL_GEN(dev_priv) <= 10 &&
> > +   (iir & GEN8_DE_MISC_GSE)) {
> This bit should not be ever set with gen11 so no need to
> add extra guards?
The bit is reserved on gen-11, we can't be sure if some future platform
is not going to reuse it for something else.The guard also adds clarity
that the gen-11 handler is elsewhere.

> 
> > 
> >     intel_opregion_asle_intr(dev_priv)
> > ;
> >     found = true;
> >     }
> > @@ -2943,6 +2944,30 @@ gen11_gt_irq_handler(struct drm_i915_private
> > * const i915,
> >     spin_unlock(>irq_lock);
> >  }
> >  
> > +static irqreturn_t
> Return is never used for anything, just use void.
Looks like the caller was reworked upstream, I'll change this.

> 
> > 
> > +gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv, u32
> > master_ctl)
> > +{
> > +   irqreturn_t ret = IRQ_NONE;
> > +   u32 iir;
> > +
> > +   if (!(master_ctl & GEN11_GU_MISC_IRQ))
> > +   return ret;
> > +
> > +   iir = I915_READ(GEN11_GU_MISC_IIR);
> This reg seems to out of forcewake domain so
> just use raw_reg_read() in here.
How do you check that? And what exactly is the forcewake domain? Is it
similar to a power domain?

> 
> > 
> > +   if (iir) {
> just a note that likely(iir) if you want to add emphasis.
> 
> > 
> > +   I915_WRITE(GEN11_GU_MISC_IIR, iir);
> raw_reg_write()
> -Mika
> 
> > 
> > +   ret = IRQ_HANDLED;
> > +   if (iir & GEN11_GU_MISC_GSE)
> > +   intel_opregion_asle_intr(dev_priv);
> > +   else
> > +   DRM_ERROR("Unexpected GU Misc interrupt
> > 0x%08x\n", iir);
> > +   } else {
> > +   DRM_ERROR("The master control interrupt lied (GU
> > MISC)!\n");
> > +   }
> > +
> > +   return ret;
> > +}
> > +
> >  static irqreturn_t gen11_irq_handler(int irq, void *arg)
> >  {
> >     struct drm_i915_private * const i915 = to_i915(arg);
> > @@ -2976,6 +3001,8 @@ static irqreturn_t gen11_irq_handler(int irq,
> > void *arg)
> >     enable_rpm_wakeref_asserts(i915);
> >     }
> >  
> > +   gen11_gu_misc_irq_handler(i915, master_ctl);
> > +
> >     /* Acknowledge and enable interrupts. */
> >     raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ |
> > master_ctl);
> >  
> > @@ -3465,6 +3492,7 @@ static void gen11_irq_reset(struct drm_device
> > *dev)
> >  
> >     GEN3_IRQ_RESET(GEN8_DE_PORT_);
> >     GEN3_IRQ_RESET(GEN8_DE_MISC_);
> > +   GEN3_IRQ_RESET(GEN11_GU_MISC_);
> >     GEN3_IRQ_RESET(GEN8_PCU_);
> >  }
> >  
> > @@ -3908,9 +3936,12 @@ static void gen8_de_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> >     uint32_t de_pipe_enables;
> >     u32 de_port_masked = GEN8_AUX_CHANNEL_A;
> >     u32 de_port_enables;
> > -   u32 de_misc_masked = GEN8_DE_MISC_GSE | GEN8_DE_EDP_PSR;
> > +   u32 de_misc_masked = GEN8_DE_EDP_PSR;
> >     enum pipe pipe;
> >  
> > +   if (INTEL_GEN(dev_priv) <= 10)
> > +   de_misc_masked |= GEN8_DE_MISC_GSE;
> > +
> >     if (INTEL_GEN(dev_priv) >= 9) {
> >     de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
> >     de_port_masked |= GEN9_AUX_CHANNEL_B |
> > GEN9_AUX_CHANNEL_C |
> > @@ -4004,10 +4035,13 @@ static void gen11_gt_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> >  static int gen11_irq_postinstall(struct drm_device *dev)
> >  {
> >     struct drm_i915_private *dev_priv = dev->dev_private;
> > +   u32 gu_misc_masked = GEN11_GU_MISC_GSE;
> >  
> >     gen11_gt_irq_postinstall(dev_priv);
> >     gen8_de_irq_postinstall(dev_priv);
> >  
> > +   

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915: Include i915_scheduler.h from i915_gem_context.h

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/2] drm/i915: Include i915_scheduler.h from 
i915_gem_context.h
URL   : https://patchwork.freedesktop.org/series/43710/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4233_full -> Patchwork_9107_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9107_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9107_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43710/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9107_full:

  === IGT changes ===

 Warnings 

igt@gem_exec_schedule@deep-vebox:
  shard-kbl:  PASS -> SKIP +2

igt@gem_mocs_settings@mocs-rc6-vebox:
  shard-kbl:  SKIP -> PASS +3


== Known issues ==

  Here are the changes found in Patchwork_9107_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_selftest@live_gtt:
  shard-glk:  PASS -> INCOMPLETE (fdo#103359, k.org#198133)

igt@drv_selftest@live_hangcheck:
  shard-kbl:  NOTRUN -> DMESG-FAIL (fdo#106560)
  shard-apl:  NOTRUN -> DMESG-FAIL (fdo#106560)

igt@kms_cursor_crc@cursor-256x256-suspend:
  shard-apl:  PASS -> FAIL (fdo#103232, fdo#103191, fdo#104645, 
fdo#104724)

igt@kms_flip@flip-vs-expired-vblank:
  shard-glk:  PASS -> FAIL (fdo#105707)

igt@kms_flip_tiling@flip-x-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724)


 Possible fixes 

igt@drv_selftest@live_gtt:
  shard-kbl:  INCOMPLETE (fdo#103665) -> PASS
  shard-apl:  INCOMPLETE (fdo#103927) -> PASS

igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
  shard-glk:  FAIL (fdo#106509, fdo#105454) -> PASS

igt@kms_flip_tiling@flip-to-y-tiled:
  shard-glk:  FAIL (fdo#103822, fdo#104724) -> PASS


  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104645 https://bugs.freedesktop.org/show_bug.cgi?id=104645
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
  fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4233 -> Patchwork_9107

  CI_DRM_4233: 0b7643db57abff1223f77fb8cbb8dd8a00ca9938 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4498: f9ecb79ad8b02278cfdb5b82495df47061c04f8f @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9107: 9524989a00856810365d0c144ce99af8b511c10e @ 
git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9107/shards.html
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Try to suppress more spurious PCH underruns on ILK-IVB

[Chris Wilson]

Quoting Ville Syrjala (2018-05-24 20:04:05)
> From: Ville Syrjälä 
> 
> My ILK seems to generate a spurious PCH underrun with most interlaced
> HDMI modes. Add a second vblank wait to avoid it.

Fwiw, a second vblank because of interlacing is very believable.
 
> We have seen some spurious PCH underruns still in CI as well, some
> of which seem to be progressive DP. The logs also point towards some
> spurious underrins with progressive HDMI on SNB. While I don't have
> a solid explanation for those let's try to kill all the birds with one
> stone and always do the double wait.
> 
> Buzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106387
> Signed-off-by: Ville Syrjälä 
Acked-by: Chris Wilson 

No point waiting for a vblank worker? ;)
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for gpu: Consistently use octal not symbolic permissions

[Patchwork]

== Series Details ==

Series: gpu: Consistently use octal not symbolic permissions
URL   : https://patchwork.freedesktop.org/series/43729/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4234 -> Patchwork_9110 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43729/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9110 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@debugfs_test@read_all_entries:
  fi-snb-2520m:   PASS -> INCOMPLETE (fdo#103713)

igt@prime_vgem@basic-fence-flip:
  fi-glk-j4005:   PASS -> FAIL (fdo#104008)


 Possible fixes 

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
  fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS


  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
  fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951


== Participating hosts (44 -> 39) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4234 -> Patchwork_9110

  CI_DRM_4234: 399e4206d849c5667d8553911e0035c53cd9c24e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4498: f9ecb79ad8b02278cfdb5b82495df47061c04f8f @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9110: ce883dbd4f90d0aeb63a64906872fc163367ae0d @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ce883dbd4f90 gpu: Consistently use octal not symbolic permissions

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9110/issues.html
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Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] tests/drv_suspend: Suspend under memory pressure

[Chris Wilson]

Quoting Antonio Argenziano (2018-05-24 21:55:38)
> 
> 
> On 24/05/18 05:42, Chris Wilson wrote:
> > Recently we discovered that we have a race between swapping and
> > suspend in our resume path (we might be trying to page in an object
> > after disabling the block devices). Let's try to exercise that by
> > exhausting all of system memory before suspend.
> > 
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=106640
> > Signed-off-by: Chris Wilson 
> > Cc: Tomi Sarvela 
> 
> LGTM:
> Reviewed-by: Antonio Argenziano 
> 
> > ---
> >   lib/igt_core.c  | 34 --
> >   lib/igt_core.h  |  1 +
> >   tests/drv_suspend.c | 42 ++
> >   3 files changed, 63 insertions(+), 14 deletions(-)
> > 
> > diff --git a/lib/igt_core.c b/lib/igt_core.c
> > index e292ca24c..804ce4578 100644
> 
> > +static void
> > +test_shrink(int fd, unsigned int mode)
> > +{
> > + uint64_t *can_mlock;
> > + void *locked;
> > + uint64_t pin;
> > +
> > + gem_quiescent_gpu(fd);
> > + intel_purge_vm_caches(fd);
> > +
> > + can_mlock = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 
> > 0);
> > + igt_assert(can_mlock != MAP_FAILED);
> > +
> > + pin = intel_get_total_ram_mb() << 20;
> > +
> > + igt_debug("Locking %'"PRIu64" MiB\n", pin >> 20);
> > + locked = malloc(pin);
> > + igt_assert(locked);
> 
> Shouldn't this^ be a require as well?

It would be a weird system if it failed; overcommit turned off and
populate on allocation. igt_require is reasonable as we haven't begun
testing anything for real yet.

> > +
> > + /* Lock all the system memory, forcing the driver into swap and OOM */
> 
> > +
> >   static void
> >   test_forcewake(int fd, bool hibernate)
> >   {
> > @@ -199,6 +238,9 @@ igt_main
> >   igt_subtest("sysfs-reader")
> >   test_sysfs_reader(false);
> >   
> > + igt_subtest("shrink")
> > + test_shrink(fd, SUSPEND_STATE_MEM);
> 
> I am assuming you plan to have tests for other suspend modes.

Not as much as you might imagine ;)

Filling all of ram before hibernation is not as interesting. But using
the test modes might be.
-Chris
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Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for gpu: Consistently use octal not symbolic permissions

[Joe Perches]

On Thu, 2018-05-24 at 20:55 +, Patchwork wrote:
> == Series Details ==
> 
> Series: gpu: Consistently use octal not symbolic permissions
> URL   : https://patchwork.freedesktop.org/series/43729/
> State : warning

All of these are existing and expected.
Is there something else required?

> == Summary ==
> 
> $ dim checkpatch origin/drm-tip
> ce883dbd4f90 gpu: Consistently use octal not symbolic permissions
> -:18: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
> (prefer a maximum 75 chars per line)
> #18: 
> $ ./scripts/checkpatch.pl -f --types=SYMBOLIC_PERMS --fix-inplace 
> 
> -:53: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
> 'amdgpu_get_dpm_forced_performance_level' to 
> 'power_dpm_force_performance_level_show' 
> 'amdgpu_set_dpm_forced_performance_level' to 
> 'power_dpm_force_performance_level_store'
> #53: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:909:
> +static DEVICE_ATTR(power_dpm_force_performance_level, 0644,
> 
> -:85: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
> 'amdgpu_get_pp_num_states' to 'pp_num_states_show'
> #85: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:912:
> +static DEVICE_ATTR(pp_num_states, 0444, amdgpu_get_pp_num_states, NULL);
> 
> -:86: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
> 'amdgpu_get_pp_cur_state' to 'pp_cur_state_show'
> #86: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:913:
> +static DEVICE_ATTR(pp_cur_state, 0444, amdgpu_get_pp_cur_state, NULL);
> 
> -:87: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
> 'amdgpu_get_pp_force_state' to 'pp_force_state_show' 
> 'amdgpu_set_pp_force_state' to 'pp_force_state_store'
> #87: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:914:
> +static DEVICE_ATTR(pp_force_state, 0644,
> 
> -:90: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
> 'amdgpu_get_pp_table' to 'pp_table_show' 'amdgpu_set_pp_table' to 
> 'pp_table_store'
> #90: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:917:
> +static DEVICE_ATTR(pp_table, 0644,
> 
> -:93: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
> 'amdgpu_get_pp_dpm_sclk' to 'pp_dpm_sclk_show' 'amdgpu_set_pp_dpm_sclk' to 
> 'pp_dpm_sclk_store'
> #93: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:920:
> +static DEVICE_ATTR(pp_dpm_sclk, 0644,
> 
> -:96: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
> 'amdgpu_get_pp_dpm_mclk' to 'pp_dpm_mclk_show' 'amdgpu_set_pp_dpm_mclk' to 
> 'pp_dpm_mclk_store'
> #96: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:923:
> +static DEVICE_ATTR(pp_dpm_mclk, 0644,
> 
> -:99: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
> 'amdgpu_get_pp_dpm_pcie' to 'pp_dpm_pcie_show' 'amdgpu_set_pp_dpm_pcie' to 
> 'pp_dpm_pcie_store'
> #99: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:926:
> +static DEVICE_ATTR(pp_dpm_pcie, 0644,
> 
> -:102: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
> 'amdgpu_get_pp_sclk_od' to 'pp_sclk_od_show' 'amdgpu_set_pp_sclk_od' to 
> 'pp_sclk_od_store'
> #102: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:929:
> +static DEVICE_ATTR(pp_sclk_od, 0644,
> 
> -:105: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
> 'amdgpu_get_pp_mclk_od' to 'pp_mclk_od_show' 'amdgpu_set_pp_mclk_od' to 
> 'pp_mclk_od_store'
> #105: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:932:
> +static DEVICE_ATTR(pp_mclk_od, 0644,
> 
> -:108: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
> 'amdgpu_get_pp_power_profile_mode' to 'pp_power_profile_mode_show' 
> 'amdgpu_set_pp_power_profile_mode' to 'pp_power_profile_mode_store'
> #108: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:935:
> +static DEVICE_ATTR(pp_power_profile_mode, 0644,
> 
> -:111: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
> 'amdgpu_get_pp_od_clk_voltage' to 'pp_od_clk_voltage_show' 
> 'amdgpu_set_pp_od_clk_voltage' to 'pp_od_clk_voltage_store'
> #111: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:938:
> +static DEVICE_ATTR(pp_od_clk_voltage, 0644,
> 
> -:141: WARNING:LONG_LINE: line over 100 characters
> #141: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:1327:
> +static SENSOR_DEVICE_ATTR(pwm1_enable, 0644, amdgpu_hwmon_get_pwm1_enable, 
> amdgpu_hwmon_set_pwm1_enable, 0);
> 
> -:152: WARNING:LONG_LINE: line over 100 characters
> #152: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:1338:
> +static SENSOR_DEVICE_ATTR(power1_cap, 0644, amdgpu_hwmon_show_power_cap, 
> amdgpu_hwmon_set_power_cap, 0);
> 
> -:362: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
> 'show_rc6_ms' to 'rc6_residency_ms_show'
> #362: FILE: drivers/gpu/drm/i915/i915_sysfs.c:104:
> +static DEVICE_ATTR(rc6_residency_ms, 0444, show_rc6_ms, NULL);
> 
> -:363: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
> 'show_rc6p_ms' to 'rc6p_residency_ms_show'
> #363: FILE: drivers/gpu/drm/i915/i915_sysfs.c:105:
> +static DEVICE_ATTR(rc6p_residency_ms, 0444, show_rc6p_ms, NULL);
> 
> -:364: WARNING:DEVICE_ATTR_FUNCTIONS: Consider 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for gpu: Consistently use octal not symbolic permissions

[Patchwork]

== Series Details ==

Series: gpu: Consistently use octal not symbolic permissions
URL   : https://patchwork.freedesktop.org/series/43729/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
ce883dbd4f90 gpu: Consistently use octal not symbolic permissions
-:18: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#18: 
$ ./scripts/checkpatch.pl -f --types=SYMBOLIC_PERMS --fix-inplace 

-:53: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
'amdgpu_get_dpm_forced_performance_level' to 
'power_dpm_force_performance_level_show' 
'amdgpu_set_dpm_forced_performance_level' to 
'power_dpm_force_performance_level_store'
#53: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:909:
+static DEVICE_ATTR(power_dpm_force_performance_level, 0644,

-:85: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
'amdgpu_get_pp_num_states' to 'pp_num_states_show'
#85: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:912:
+static DEVICE_ATTR(pp_num_states, 0444, amdgpu_get_pp_num_states, NULL);

-:86: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
'amdgpu_get_pp_cur_state' to 'pp_cur_state_show'
#86: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:913:
+static DEVICE_ATTR(pp_cur_state, 0444, amdgpu_get_pp_cur_state, NULL);

-:87: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
'amdgpu_get_pp_force_state' to 'pp_force_state_show' 
'amdgpu_set_pp_force_state' to 'pp_force_state_store'
#87: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:914:
+static DEVICE_ATTR(pp_force_state, 0644,

-:90: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
'amdgpu_get_pp_table' to 'pp_table_show' 'amdgpu_set_pp_table' to 
'pp_table_store'
#90: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:917:
+static DEVICE_ATTR(pp_table, 0644,

-:93: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
'amdgpu_get_pp_dpm_sclk' to 'pp_dpm_sclk_show' 'amdgpu_set_pp_dpm_sclk' to 
'pp_dpm_sclk_store'
#93: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:920:
+static DEVICE_ATTR(pp_dpm_sclk, 0644,

-:96: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
'amdgpu_get_pp_dpm_mclk' to 'pp_dpm_mclk_show' 'amdgpu_set_pp_dpm_mclk' to 
'pp_dpm_mclk_store'
#96: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:923:
+static DEVICE_ATTR(pp_dpm_mclk, 0644,

-:99: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
'amdgpu_get_pp_dpm_pcie' to 'pp_dpm_pcie_show' 'amdgpu_set_pp_dpm_pcie' to 
'pp_dpm_pcie_store'
#99: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:926:
+static DEVICE_ATTR(pp_dpm_pcie, 0644,

-:102: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
'amdgpu_get_pp_sclk_od' to 'pp_sclk_od_show' 'amdgpu_set_pp_sclk_od' to 
'pp_sclk_od_store'
#102: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:929:
+static DEVICE_ATTR(pp_sclk_od, 0644,

-:105: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
'amdgpu_get_pp_mclk_od' to 'pp_mclk_od_show' 'amdgpu_set_pp_mclk_od' to 
'pp_mclk_od_store'
#105: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:932:
+static DEVICE_ATTR(pp_mclk_od, 0644,

-:108: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
'amdgpu_get_pp_power_profile_mode' to 'pp_power_profile_mode_show' 
'amdgpu_set_pp_power_profile_mode' to 'pp_power_profile_mode_store'
#108: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:935:
+static DEVICE_ATTR(pp_power_profile_mode, 0644,

-:111: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
'amdgpu_get_pp_od_clk_voltage' to 'pp_od_clk_voltage_show' 
'amdgpu_set_pp_od_clk_voltage' to 'pp_od_clk_voltage_store'
#111: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:938:
+static DEVICE_ATTR(pp_od_clk_voltage, 0644,

-:141: WARNING:LONG_LINE: line over 100 characters
#141: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:1327:
+static SENSOR_DEVICE_ATTR(pwm1_enable, 0644, amdgpu_hwmon_get_pwm1_enable, 
amdgpu_hwmon_set_pwm1_enable, 0);

-:152: WARNING:LONG_LINE: line over 100 characters
#152: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:1338:
+static SENSOR_DEVICE_ATTR(power1_cap, 0644, amdgpu_hwmon_show_power_cap, 
amdgpu_hwmon_set_power_cap, 0);

-:362: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
'show_rc6_ms' to 'rc6_residency_ms_show'
#362: FILE: drivers/gpu/drm/i915/i915_sysfs.c:104:
+static DEVICE_ATTR(rc6_residency_ms, 0444, show_rc6_ms, NULL);

-:363: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
'show_rc6p_ms' to 'rc6p_residency_ms_show'
#363: FILE: drivers/gpu/drm/i915/i915_sysfs.c:105:
+static DEVICE_ATTR(rc6p_residency_ms, 0444, show_rc6p_ms, NULL);

-:364: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
'show_rc6pp_ms' to 'rc6pp_residency_ms_show'
#364: FILE: drivers/gpu/drm/i915/i915_sysfs.c:106:
+static DEVICE_ATTR(rc6pp_residency_ms, 0444, show_rc6pp_ms, NULL);

-:365: WARNING:DEVICE_ATTR_FUNCTIONS: Consider renaming function(s) 
'show_media_rc6_ms' to 'media_rc6_residency_ms_show'
#365: FILE: 

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] tests/drv_suspend: Suspend under memory pressure

[Antonio Argenziano]

On 24/05/18 05:42, Chris Wilson wrote:

Recently we discovered that we have a race between swapping and
suspend in our resume path (we might be trying to page in an object
after disabling the block devices). Let's try to exercise that by
exhausting all of system memory before suspend.

References: https://bugs.freedesktop.org/show_bug.cgi?id=106640
Signed-off-by: Chris Wilson 
Cc: Tomi Sarvela 


LGTM:
Reviewed-by: Antonio Argenziano 


---
  lib/igt_core.c  | 34 --
  lib/igt_core.h  |  1 +
  tests/drv_suspend.c | 42 ++
  3 files changed, 63 insertions(+), 14 deletions(-)

diff --git a/lib/igt_core.c b/lib/igt_core.c
index e292ca24c..804ce4578 100644



+static void
+test_shrink(int fd, unsigned int mode)
+{
+   uint64_t *can_mlock;
+   void *locked;
+   uint64_t pin;
+
+   gem_quiescent_gpu(fd);
+   intel_purge_vm_caches(fd);
+
+   can_mlock = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
+   igt_assert(can_mlock != MAP_FAILED);
+
+   pin = intel_get_total_ram_mb() << 20;
+
+   igt_debug("Locking %'"PRIu64" MiB\n", pin >> 20);
+   locked = malloc(pin);
+   igt_assert(locked);


Shouldn't this^ be a require as well?


+
+   /* Lock all the system memory, forcing the driver into swap and OOM */



+
  static void
  test_forcewake(int fd, bool hibernate)
  {
@@ -199,6 +238,9 @@ igt_main
igt_subtest("sysfs-reader")
test_sysfs_reader(false);
  
+	igt_subtest("shrink")

+   test_shrink(fd, SUSPEND_STATE_MEM);


I am assuming you plan to have tests for other suspend modes.

Thanks,
Antonio


+
igt_subtest("forcewake")
test_forcewake(fd, false);
  


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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/trace: Describe engines as class:instance pairs

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/trace: Describe engines as 
class:instance pairs
URL   : https://patchwork.freedesktop.org/series/43709/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4233_full -> Patchwork_9106_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9106_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9106_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43709/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9106_full:

  === IGT changes ===

 Warnings 

igt@gem_mocs_settings@mocs-rc6-vebox:
  shard-kbl:  SKIP -> PASS


== Known issues ==

  Here are the changes found in Patchwork_9106_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_selftest@live_gtt:
  shard-glk:  PASS -> INCOMPLETE (k.org#198133, fdo#103359)

igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
  shard-glk:  PASS -> FAIL (fdo#105703)

igt@kms_flip_tiling@flip-y-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724)


 Possible fixes 

igt@drv_selftest@live_gtt:
  shard-kbl:  INCOMPLETE (fdo#103665) -> PASS
  shard-apl:  INCOMPLETE (fdo#103927) -> PASS

igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
  shard-glk:  FAIL (fdo#105703) -> PASS

igt@kms_flip@plain-flip-fb-recreate:
  shard-glk:  FAIL (fdo#100368) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4233 -> Patchwork_9106

  CI_DRM_4233: 0b7643db57abff1223f77fb8cbb8dd8a00ca9938 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4498: f9ecb79ad8b02278cfdb5b82495df47061c04f8f @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9106: 4f5293dac6122cdcb6456a96f29f8c69c73e0346 @ 
git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9106/shards.html
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Try to suppress more spurious PCH underruns on ILK-IVB

[Ville Syrjälä]

On Thu, May 24, 2018 at 09:15:37PM +0100, Chris Wilson wrote:
> Quoting Chris Wilson (2018-05-24 21:14:23)
> > Quoting Ville Syrjala (2018-05-24 20:04:05)
> > > From: Ville Syrjälä 
> > > 
> > > My ILK seems to generate a spurious PCH underrun with most interlaced
> > > HDMI modes. Add a second vblank wait to avoid it.
> > > 
> > > We have seen some spurious PCH underruns still in CI as well, some
> > > of which seem to be progressive DP. The logs also point towards some
> > > spurious underrins with progressive HDMI on SNB. While I don't have
> > > a solid explanation for those let's try to kill all the birds with one
> > > stone and always do the double wait.
> > > 
> > > Buzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106387
> > > Signed-off-by: Ville Syrjälä 
> > > ---
> > >  drivers/gpu/drm/i915/intel_display.c | 11 +--
> > >  1 file changed, 9 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index 7604fbda0607..b5fa4943372a 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -5528,9 +5528,16 @@ static void ironlake_crtc_enable(struct 
> > > intel_crtc_state *pipe_config,
> > > if (HAS_PCH_CPT(dev_priv))
> > > cpt_verify_modeset(dev, intel_crtc->pipe);
> > >  
> > > -   /* Must wait for vblank to avoid spurious PCH FIFO underruns */
> > > -   if (intel_crtc->config->has_pch_encoder)
> > > +   /*
> > > +* Must wait for vblank to avoid spurious PCH FIFO underruns.
> > > +* And a second vblank wait is needed at least on ILK with
> > > +* some interlaced HDMI modes. Let's do the double wait always
> > > +* in case there are more corner cases we don't know about.
> > > +*/
> > > +   if (intel_crtc->config->has_pch_encoder) {
> > > +   intel_wait_for_vblank(dev_priv, pipe);
> > > intel_wait_for_vblank(dev_priv, pipe);
> > 
> > The only purpose for the double wait here is for delaying the switching
> > on of underrun reporting, right? It doesn't accidentally fix anything
> > else?
> 
> E.g. in a multi-crtc setup, that's a big delay between switching on a
> pair of pipes.

I was testing with one pipe only. So at least it's not meant to do
anything else.

-- 
Ville Syrjälä
Intel
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[Intel-gfx] [PATCH] gpu: Consistently use octal not symbolic permissions

[Joe Perches]

There is currently a mixture of octal and symbolic permissions uses
in files in drivers/gpu/drm and one file in drivers/gpu.

There are ~270 existing octal uses and ~115 S_ uses.

Convert all the S_ symbolic permissions to their octal equivalents
as using octal and not symbolic permissions is preferred by many as more
readable.

see: https://lkml.org/lkml/2016/8/2/1945

Done with automated conversion via:
$ ./scripts/checkpatch.pl -f --types=SYMBOLIC_PERMS --fix-inplace 

Miscellanea:

o Wrapped modified multi-line calls to a single line where appropriate
o Realign modified multi-line calls to open parenthesis
o drivers/gpu/drm/msm/adreno/a5xx_debugfs.c has a world-writeable
  debug permission for "reset" - perhaps that should be modified

Signed-off-by: Joe Perches 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 98 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   |  3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  9 +-
 drivers/gpu/drm/armada/armada_debugfs.c|  4 +-
 drivers/gpu/drm/drm_debugfs.c  |  6 +-
 drivers/gpu/drm/drm_debugfs_crc.c  |  4 +-
 drivers/gpu/drm/drm_sysfs.c|  2 +-
 drivers/gpu/drm/i915/gvt/firmware.c|  2 +-
 drivers/gpu/drm/i915/i915_debugfs.c|  8 +-
 drivers/gpu/drm/i915/i915_perf.c   |  2 +-
 drivers/gpu/drm/i915/i915_sysfs.c  | 22 ++---
 drivers/gpu/drm/i915/intel_pipe_crc.c  |  2 +-
 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c  |  5 +-
 drivers/gpu/drm/msm/msm_perf.c |  4 +-
 drivers/gpu/drm/msm/msm_rd.c   |  4 +-
 drivers/gpu/drm/nouveau/nouveau_debugfs.c  |  2 +-
 drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c| 11 ++-
 .../drm/omapdrm/displays/panel-sony-acx565akm.c|  6 +-
 .../drm/omapdrm/displays/panel-tpo-td043mtea1.c| 10 +--
 drivers/gpu/drm/radeon/radeon_pm.c | 26 +++---
 drivers/gpu/drm/radeon/radeon_ttm.c|  4 +-
 drivers/gpu/drm/sti/sti_drv.c  |  2 +-
 drivers/gpu/drm/tinydrm/mipi-dbi.c |  4 +-
 drivers/gpu/drm/ttm/ttm_bo.c   |  2 +-
 drivers/gpu/drm/ttm/ttm_memory.c   | 12 +--
 drivers/gpu/drm/ttm/ttm_page_alloc.c   |  6 +-
 drivers/gpu/drm/ttm/ttm_page_alloc_dma.c   |  6 +-
 drivers/gpu/drm/udl/udl_fb.c   |  4 +-
 drivers/gpu/host1x/debug.c | 12 +--
 30 files changed, 138 insertions(+), 146 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index f5fb93795a69..7b29febff511 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -830,7 +830,7 @@ int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
 
for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
ent = debugfs_create_file(debugfs_regs_names[i],
- S_IFREG | S_IRUGO, root,
+ S_IFREG | 0444, root,
  adev, debugfs_regs[i]);
if (IS_ERR(ent)) {
for (j = 0; j < i; j++) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index b455da487782..fa55d7e9e784 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -905,39 +905,39 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct 
device *dev,
return -EINVAL;
 }
 
-static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, 
amdgpu_set_dpm_state);
-static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
+static DEVICE_ATTR(power_dpm_state, 0644, amdgpu_get_dpm_state, 
amdgpu_set_dpm_state);
+static DEVICE_ATTR(power_dpm_force_performance_level, 0644,
   amdgpu_get_dpm_forced_performance_level,
   amdgpu_set_dpm_forced_performance_level);
-static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
-static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
-static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
-   amdgpu_get_pp_force_state,
-   amdgpu_set_pp_force_state);
-static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
-   amdgpu_get_pp_table,
-   amdgpu_set_pp_table);
-static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
-   amdgpu_get_pp_dpm_sclk,
-   amdgpu_set_pp_dpm_sclk);
-static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
-   amdgpu_get_pp_dpm_mclk,
-   amdgpu_set_pp_dpm_mclk);
-static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
-   amdgpu_get_pp_dpm_pcie,
-   

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Try to suppress more spurious PCH underruns on ILK-IVB

[Chris Wilson]

Quoting Chris Wilson (2018-05-24 21:14:23)
> Quoting Ville Syrjala (2018-05-24 20:04:05)
> > From: Ville Syrjälä 
> > 
> > My ILK seems to generate a spurious PCH underrun with most interlaced
> > HDMI modes. Add a second vblank wait to avoid it.
> > 
> > We have seen some spurious PCH underruns still in CI as well, some
> > of which seem to be progressive DP. The logs also point towards some
> > spurious underrins with progressive HDMI on SNB. While I don't have
> > a solid explanation for those let's try to kill all the birds with one
> > stone and always do the double wait.
> > 
> > Buzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106387
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 11 +--
> >  1 file changed, 9 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 7604fbda0607..b5fa4943372a 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5528,9 +5528,16 @@ static void ironlake_crtc_enable(struct 
> > intel_crtc_state *pipe_config,
> > if (HAS_PCH_CPT(dev_priv))
> > cpt_verify_modeset(dev, intel_crtc->pipe);
> >  
> > -   /* Must wait for vblank to avoid spurious PCH FIFO underruns */
> > -   if (intel_crtc->config->has_pch_encoder)
> > +   /*
> > +* Must wait for vblank to avoid spurious PCH FIFO underruns.
> > +* And a second vblank wait is needed at least on ILK with
> > +* some interlaced HDMI modes. Let's do the double wait always
> > +* in case there are more corner cases we don't know about.
> > +*/
> > +   if (intel_crtc->config->has_pch_encoder) {
> > +   intel_wait_for_vblank(dev_priv, pipe);
> > intel_wait_for_vblank(dev_priv, pipe);
> 
> The only purpose for the double wait here is for delaying the switching
> on of underrun reporting, right? It doesn't accidentally fix anything
> else?

E.g. in a multi-crtc setup, that's a big delay between switching on a
pair of pipes.
-Chris
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Try to suppress more spurious PCH underruns on ILK-IVB

[Chris Wilson]

Quoting Ville Syrjala (2018-05-24 20:04:05)
> From: Ville Syrjälä 
> 
> My ILK seems to generate a spurious PCH underrun with most interlaced
> HDMI modes. Add a second vblank wait to avoid it.
> 
> We have seen some spurious PCH underruns still in CI as well, some
> of which seem to be progressive DP. The logs also point towards some
> spurious underrins with progressive HDMI on SNB. While I don't have
> a solid explanation for those let's try to kill all the birds with one
> stone and always do the double wait.
> 
> Buzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106387
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 11 +--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 7604fbda0607..b5fa4943372a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5528,9 +5528,16 @@ static void ironlake_crtc_enable(struct 
> intel_crtc_state *pipe_config,
> if (HAS_PCH_CPT(dev_priv))
> cpt_verify_modeset(dev, intel_crtc->pipe);
>  
> -   /* Must wait for vblank to avoid spurious PCH FIFO underruns */
> -   if (intel_crtc->config->has_pch_encoder)
> +   /*
> +* Must wait for vblank to avoid spurious PCH FIFO underruns.
> +* And a second vblank wait is needed at least on ILK with
> +* some interlaced HDMI modes. Let's do the double wait always
> +* in case there are more corner cases we don't know about.
> +*/
> +   if (intel_crtc->config->has_pch_encoder) {
> +   intel_wait_for_vblank(dev_priv, pipe);
> intel_wait_for_vblank(dev_priv, pipe);

The only purpose for the double wait here is for delaying the switching
on of underrun reporting, right? It doesn't accidentally fix anything
else?
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/edid: Fix up edid_cea_modes[] formatting

[Patchwork]

== Series Details ==

Series: drm/edid: Fix up edid_cea_modes[] formatting
URL   : https://patchwork.freedesktop.org/series/43722/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4234 -> Patchwork_9109 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9109 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9109, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43722/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9109:

  === IGT changes ===

 Warnings 

igt@gem_exec_gttfill@basic:
  fi-pnv-d510:SKIP -> PASS


== Known issues ==

  Here are the changes found in Patchwork_9109 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_chamelium@hdmi-hpd-fast:
  fi-kbl-7500u:   SKIP -> FAIL (fdo#102672, fdo#103841)

igt@prime_vgem@basic-fence-flip:
  fi-ilk-650: PASS -> FAIL (fdo#104008)


 Possible fixes 

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
  fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS


  fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672
  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
  fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951


== Participating hosts (44 -> 38) ==

  Missing(6): fi-ilk-m540 fi-bxt-dsi fi-byt-squawks fi-bsw-cyan 
fi-ctg-p8600 fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4234 -> Patchwork_9109

  CI_DRM_4234: 399e4206d849c5667d8553911e0035c53cd9c24e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4498: f9ecb79ad8b02278cfdb5b82495df47061c04f8f @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9109: 4258ca94a2a353d6af2c44dc7af8b055ef0bb990 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4258ca94a2a3 drm/edid: Fix up edid_cea_modes[] formatting

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9109/issues.html
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: per context slice/subslice powergating (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915: per context slice/subslice powergating (rev6)
URL   : https://patchwork.freedesktop.org/series/42285/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4233_full -> Patchwork_9105_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9105_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9105_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/42285/revisions/6/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9105_full:

  === IGT changes ===

 Possible regressions 

igt@gem_ctx_param@invalid-param-get:
  shard-apl:  PASS -> FAIL
  shard-glk:  PASS -> FAIL
  shard-snb:  PASS -> FAIL
  shard-hsw:  PASS -> FAIL
  shard-kbl:  PASS -> FAIL

igt@gem_ctx_param@invalid-param-set:
  shard-kbl:  PASS -> DMESG-FAIL
  shard-hsw:  PASS -> DMESG-FAIL
  shard-snb:  PASS -> DMESG-FAIL
  shard-glk:  PASS -> DMESG-FAIL
  shard-apl:  PASS -> DMESG-FAIL


 Warnings 

igt@drv_selftest@live_gtt:
  shard-kbl:  INCOMPLETE (fdo#103665) -> FAIL

igt@gem_mocs_settings@mocs-rc6-render:
  shard-kbl:  PASS -> SKIP +1

igt@gem_mocs_settings@mocs-rc6-vebox:
  shard-kbl:  SKIP -> PASS


== Known issues ==

  Here are the changes found in Patchwork_9105_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_selftest@live_hangcheck:
  shard-kbl:  NOTRUN -> DMESG-FAIL (fdo#106560)
  shard-glk:  PASS -> DMESG-FAIL (fdo#106560)

igt@kms_flip_tiling@flip-x-tiled:
  shard-glk:  PASS -> FAIL (fdo#103822, fdo#104724)


 Possible fixes 

igt@drv_selftest@live_gtt:
  shard-apl:  INCOMPLETE (fdo#103927) -> PASS

igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
  shard-glk:  FAIL (fdo#105703) -> PASS

igt@kms_flip@plain-flip-fb-recreate:
  shard-glk:  FAIL (fdo#100368) -> PASS

igt@kms_flip_tiling@flip-to-y-tiled:
  shard-glk:  FAIL (fdo#103822, fdo#104724) -> PASS

igt@kms_setmode@basic:
  shard-apl:  FAIL (fdo#99912) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4233 -> Patchwork_9105

  CI_DRM_4233: 0b7643db57abff1223f77fb8cbb8dd8a00ca9938 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4498: f9ecb79ad8b02278cfdb5b82495df47061c04f8f @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9105: 9873e890b9cd81024b6b5fb48aeb2377ed6fba8e @ 
git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9105/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Try to suppress more spurious PCH underruns on ILK-IVB

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Try to suppress more spurious PCH 
underruns on ILK-IVB
URL   : https://patchwork.freedesktop.org/series/43721/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4234 -> Patchwork_9108 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9108 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9108, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43721/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9108:

  === IGT changes ===

 Warnings 

igt@gem_exec_gttfill@basic:
  fi-pnv-d510:SKIP -> PASS


== Known issues ==

  Here are the changes found in Patchwork_9108 that come from known issues:

  === IGT changes ===

 Possible fixes 

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
  fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS


  fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951


== Participating hosts (44 -> 38) ==

  Missing(6): fi-ilk-m540 fi-cnl-y3 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 
fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4234 -> Patchwork_9108

  CI_DRM_4234: 399e4206d849c5667d8553911e0035c53cd9c24e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4498: f9ecb79ad8b02278cfdb5b82495df47061c04f8f @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9108: 2296f07c0461544811deb6f930299d72b1589bec @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

2296f07c0461 drm/i915: Simplify ilk-ivb underrun suppression
0e090bdd1211 drm/i915: Try to suppress more spurious PCH underruns on ILK-IVB

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9108/issues.html
___
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[Intel-gfx] [PATCH] drm/edid: Fix up edid_cea_modes[] formatting

[Ville Syrjala]

From: Ville Syrjälä 

Fix up a bunch of bad indentation and insconsistent comments
in edid_cea_modes[].

v2: Instead of stripping the aspect ratio comments let's
add them to all modes

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/drm_edid.c | 268 ++---
 1 file changed, 134 insertions(+), 134 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 82f1ab09169d..634a68a03b07 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -687,562 +687,562 @@ static const struct minimode extra_modes[] = {
 static const struct drm_display_mode edid_cea_modes[] = {
/* 0 - dummy, VICs start at 1 */
{ },
-   /* 1 - 640x480@60Hz */
+   /* 1 - 640x480@60Hz 4:3 */
{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
   752, 800, 0, 480, 490, 492, 525, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
-   /* 2 - 720x480@60Hz */
+   /* 2 - 720x480@60Hz 4:3 */
{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
   798, 858, 0, 480, 489, 495, 525, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
-   /* 3 - 720x480@60Hz */
+   /* 3 - 720x480@60Hz 16:9 */
{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
   798, 858, 0, 480, 489, 495, 525, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 4 - 1280x720@60Hz */
+   /* 4 - 1280x720@60Hz 16:9 */
{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
   1430, 1650, 0, 720, 725, 730, 750, 0,
   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 5 - 1920x1080i@60Hz */
+   /* 5 - 1920x1080i@60Hz 16:9 */
{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
   2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
-   DRM_MODE_FLAG_INTERLACE),
+  DRM_MODE_FLAG_INTERLACE),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 6 - 720(1440)x480i@60Hz */
+   /* 6 - 720(1440)x480i@60Hz 4:3 */
{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
   801, 858, 0, 480, 488, 494, 525, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
-   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+  DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
-   /* 7 - 720(1440)x480i@60Hz */
+   /* 7 - 720(1440)x480i@60Hz 16:9 */
{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
   801, 858, 0, 480, 488, 494, 525, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
-   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+  DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 8 - 720(1440)x240@60Hz */
+   /* 8 - 720(1440)x240@60Hz 4:3 */
{ DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
   801, 858, 0, 240, 244, 247, 262, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
-   DRM_MODE_FLAG_DBLCLK),
+  DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
-   /* 9 - 720(1440)x240@60Hz */
+   /* 9 - 720(1440)x240@60Hz 16:9 */
{ DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
   801, 858, 0, 240, 244, 247, 262, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
-   DRM_MODE_FLAG_DBLCLK),
+  DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 10 - 2880x480i@60Hz */
+   /* 10 - 2880x480i@60Hz 4:3 */
{ DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
   3204, 3432, 0, 480, 488, 494, 525, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
-   DRM_MODE_FLAG_INTERLACE),
+  DRM_MODE_FLAG_INTERLACE),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
-   /* 11 - 2880x480i@60Hz */
+   /* 11 - 2880x480i@60Hz 16:9 */
{ DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 

[Intel-gfx] [PATCH 2/2] drm/i915: Simplify ilk-ivb underrun suppression

[Ville Syrjala]

From: Ville Syrjälä 

Let's suppress the underruns around every modeset sequence instead
of trying to avoid it. Planes are disabled at this point anyway so
we don't really gain anything from keeping the underrun reporting
enabled. Also for PCH ports we already suppress all underruns here
anyway so trying avoid it for the CPU eDP doesn't seem all that
important.

Maybe this gets rid of some lingering spurious underruns?

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 12 
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index b5fa4943372a..dc7204d27a24 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5470,10 +5470,8 @@ static void ironlake_crtc_enable(struct intel_crtc_state 
*pipe_config,
 *
 * Spurious PCH underruns also occur during PCH enabling.
 */
-   if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
-   intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
-   if (intel_crtc->config->has_pch_encoder)
-   intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
+   intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
+   intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
 
if (intel_crtc->config->has_pch_encoder)
intel_prepare_shared_dpll(intel_crtc);
@@ -5717,10 +5715,8 @@ static void ironlake_crtc_disable(struct 
intel_crtc_state *old_crtc_state,
 * pipe is already disabled, but FDI RX/TX is still enabled.
 * Happens at least with VGA+HDMI cloning. Suppress them.
 */
-   if (intel_crtc->config->has_pch_encoder) {
-   intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
-   intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
-   }
+   intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
+   intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
 
intel_encoders_disable(crtc, old_crtc_state, old_state);
 
-- 
2.16.1

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[Intel-gfx] [PATCH 1/2] drm/i915: Try to suppress more spurious PCH underruns on ILK-IVB

[Ville Syrjala]

From: Ville Syrjälä 

My ILK seems to generate a spurious PCH underrun with most interlaced
HDMI modes. Add a second vblank wait to avoid it.

We have seen some spurious PCH underruns still in CI as well, some
of which seem to be progressive DP. The logs also point towards some
spurious underrins with progressive HDMI on SNB. While I don't have
a solid explanation for those let's try to kill all the birds with one
stone and always do the double wait.

Buzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106387
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 7604fbda0607..b5fa4943372a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5528,9 +5528,16 @@ static void ironlake_crtc_enable(struct intel_crtc_state 
*pipe_config,
if (HAS_PCH_CPT(dev_priv))
cpt_verify_modeset(dev, intel_crtc->pipe);
 
-   /* Must wait for vblank to avoid spurious PCH FIFO underruns */
-   if (intel_crtc->config->has_pch_encoder)
+   /*
+* Must wait for vblank to avoid spurious PCH FIFO underruns.
+* And a second vblank wait is needed at least on ILK with
+* some interlaced HDMI modes. Let's do the double wait always
+* in case there are more corner cases we don't know about.
+*/
+   if (intel_crtc->config->has_pch_encoder) {
+   intel_wait_for_vblank(dev_priv, pipe);
intel_wait_for_vblank(dev_priv, pipe);
+   }
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
 }
-- 
2.16.1

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Re: [Intel-gfx] [PATCH] drm/i915: Prepare GEM for suspend earlier

[kbuild test robot]

Hi Chris,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.17-rc6 next-20180517]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Prepare-GEM-for-suspend-earlier/20180524-231951
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x000-201820 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All errors (new ones prefixed by >>):

   drivers/gpu//drm/i915/i915_drv.c: In function 'i915_drm_suspend':
>> drivers/gpu//drm/i915/i915_drv.c:1624:1: error: label 'out' defined but not 
>> used [-Werror=unused-label]
out:
^~~
   Cyclomatic Complexity 5 include/linux/compiler.h:__read_once_size
   Cyclomatic Complexity 1 include/linux/kasan-checks.h:kasan_check_read
   Cyclomatic Complexity 1 include/linux/kasan-checks.h:kasan_check_write
   Cyclomatic Complexity 2 arch/x86/include/asm/bitops.h:clear_bit
   Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:constant_test_bit
   Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:fls
   Cyclomatic Complexity 1 arch/x86/include/asm/arch_hweight.h:__arch_hweight32
   Cyclomatic Complexity 1 arch/x86/include/asm/arch_hweight.h:__arch_hweight8
   Cyclomatic Complexity 1 include/linux/log2.h:__ilog2_u32
   Cyclomatic Complexity 1 include/linux/list.h:list_empty
   Cyclomatic Complexity 1 arch/x86/include/asm/mem_encrypt.h:sme_active
   Cyclomatic Complexity 1 include/linux/mem_encrypt.h:sme_get_me_mask
   Cyclomatic Complexity 1 include/asm-generic/getorder.h:__get_order
   Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:arch_atomic_read
   Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:arch_atomic_inc
   Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:arch_atomic_dec
   Cyclomatic Complexity 1 include/asm-generic/atomic-instrumented.h:atomic_read
   Cyclomatic Complexity 1 include/asm-generic/atomic-instrumented.h:atomic_inc
   Cyclomatic Complexity 1 include/asm-generic/atomic-instrumented.h:atomic_dec
   Cyclomatic Complexity 1 include/linux/err.h:ERR_PTR
   Cyclomatic Complexity 1 include/linux/err.h:PTR_ERR
   Cyclomatic Complexity 3 include/linux/err.h:IS_ERR_OR_NULL
   Cyclomatic Complexity 1 include/linux/lockdep.h:lock_is_held
   Cyclomatic Complexity 1 include/linux/spinlock.h:spinlock_check
   Cyclomatic Complexity 1 include/linux/spinlock.h:spin_lock_irq
   Cyclomatic Complexity 1 include/linux/spinlock.h:spin_unlock_irq
   Cyclomatic Complexity 1 include/linux/jiffies.h:_msecs_to_jiffies
   Cyclomatic Complexity 3 include/linux/jiffies.h:msecs_to_jiffies
   Cyclomatic Complexity 3 include/linux/ktime.h:ktime_compare
   Cyclomatic Complexity 1 include/linux/ktime.h:ktime_after
   Cyclomatic Complexity 1 include/linux/workqueue.h:queue_delayed_work
   Cyclomatic Complexity 67 include/linux/slab.h:kmalloc_large
   Cyclomatic Complexity 3 include/linux/slab.h:kmalloc
   Cyclomatic Complexity 1 include/linux/slab.h:kzalloc
   Cyclomatic Complexity 1 include/linux/device.h:dev_get_drvdata
   Cyclomatic Complexity 1 include/linux/device.h:dev_set_drvdata
   Cyclomatic Complexity 1 include/linux/device.h:dev_pm_set_driver_flags
   Cyclomatic Complexity 1 include/linux/pci.h:pci_disable_msi
   Cyclomatic Complexity 1 include/linux/pci.h:pci_enable_msi
   Cyclomatic Complexity 1 arch/x86/include/asm/pci.h:pci_domain_nr
   Cyclomatic Complexity 1 include/linux/pci.h:pci_get_drvdata
   Cyclomatic Complexity 1 include/linux/pci.h:pci_set_drvdata
   Cyclomatic Complexity 1 arch/x86/include/asm/dma-mapping.h:get_arch_dma_ops
   Cyclomatic Complexity 4 include/linux/dma-mapping.h:get_dma_ops
   Cyclomatic Complexity 3 include/linux/dma-mapping.h:dma_check_mask
   Cyclomatic Complexity 4 include/linux/dma-mapping.h:dma_supported
   Cyclomatic Complexity 2 include/linux/dma-mapping.h:dma_set_coherent_mask
   Cyclomatic Complexity 1 include/linux/vgaarb.h:vga_client_register
   Cyclomatic Complexity 2 include/linux/fb.h:alloc_apertures
   Cyclomatic Complexity 1 
include/linux/vga_switcheroo.h:vga_switcheroo_unregister_client
   Cyclomatic Complexity 1 
include/linux/vga_switcheroo.h:vga_switcheroo_register_client
   Cyclomatic Complexity 1 
include/linux/vga_switcheroo.h:vga_switcheroo_process_delayed_switch
   Cyclomatic Complexity 1 include/drm/drm_print.h:drm_debug_printer
   Cyclomatic Complexity 2 drivers/gpu//drm/i915/i915_utils.h:onoff
   Cyclomatic Complexity 3 
drivers/gpu//drm/i915/intel_device_info.h:sseu_subslice_total
   Cyclomatic Complexity 1 
drivers/gpu//drm/i915/intel_ringbuffer.h:intel_engine_flag
   Cyclomatic Complexity 1 
drivers/gpu//drm/i915/intel_uncore.h:intel_wait_for_register
   Cyclomatic Complexity 1 
drivers/gpu//drm/i915/i915_gpu_error.h:i915_reset_error_s

Re: [Intel-gfx] [PATCH 4/4] drm/i915: "Race-to-idle" on switching to the kernel context

[kbuild test robot]

Hi Chris,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on next-20180517]
[cannot apply to drm-intel/for-linux-next v4.17-rc6 v4.17-rc5 v4.17-rc4 
v4.17-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Prepare-GEM-for-suspend-earlier/20180524-224509
reproduce:
# apt-get install sparse
make ARCH=x86_64 allmodconfig
make C=1 CF=-D__CHECK_ENDIAN__


sparse warnings: (new ones prefixed by >>)

>> drivers/gpu/drm/i915/selftests/igt_flush_test.c:61:46: sparse: not enough 
>> arguments for function i915_gem_switch_to_kernel_context
   drivers/gpu/drm/i915/selftests/igt_flush_test.c: In function 
'igt_flush_test':
   drivers/gpu/drm/i915/selftests/igt_flush_test.c:61:6: error: too few 
arguments to function 'i915_gem_switch_to_kernel_context'
 i915_gem_switch_to_kernel_context(i915)) {
 ^
   In file included from drivers/gpu/drm/i915/selftests/../intel_lrc.h:28:0,
from drivers/gpu/drm/i915/selftests/../i915_drv.h:63,
from drivers/gpu/drm/i915/selftests/igt_flush_test.c:7:
   drivers/gpu/drm/i915/selftests/../i915_gem_context.h:297:5: note: declared 
here
int i915_gem_switch_to_kernel_context(struct drm_i915_private *i915,
^

vim +61 drivers/gpu/drm/i915/selftests/igt_flush_test.c

98dc0454 Chris Wilson 2018-05-05  48  
98dc0454 Chris Wilson 2018-05-05  49  #define wedge_on_timeout(W, DEV, TIMEOUT) 
\
98dc0454 Chris Wilson 2018-05-05  50for (__init_wedge((W), (DEV), 
(TIMEOUT), __builtin_return_address(0)); \
98dc0454 Chris Wilson 2018-05-05  51 (W)->i915; 
\
98dc0454 Chris Wilson 2018-05-05  52 __fini_wedge((W)))
98dc0454 Chris Wilson 2018-05-05  53  
98dc0454 Chris Wilson 2018-05-05  54  int igt_flush_test(struct 
drm_i915_private *i915, unsigned int flags)
98dc0454 Chris Wilson 2018-05-05  55  {
98dc0454 Chris Wilson 2018-05-05  56struct wedge_me w;
98dc0454 Chris Wilson 2018-05-05  57  
98dc0454 Chris Wilson 2018-05-05  58cond_resched();
98dc0454 Chris Wilson 2018-05-05  59  
b9777c6f Chris Wilson 2018-05-09  60if (flags & I915_WAIT_LOCKED &&
b9777c6f Chris Wilson 2018-05-09 @61
i915_gem_switch_to_kernel_context(i915)) {

:: The code at line 61 was first introduced by commit
:: b9777c6f86ac8c21f82211ab982ca48302042ede drm/i915/selftests: Only switch 
to kernel context when locked

:: TO: Chris Wilson <ch...@chris-wilson.co.uk>
:: CC: Chris Wilson <ch...@chris-wilson.co.uk>

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation
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Re: [Intel-gfx] [PATCH] drm/i915: Prepare GEM for suspend earlier

[kbuild test robot]

Hi Chris,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.17-rc6 next-20180517]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Prepare-GEM-for-suspend-earlier/20180524-231951
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x015-201820 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64 

All warnings (new ones prefixed by >>):

   drivers/gpu//drm/i915/i915_drv.c: In function 'i915_drm_suspend':
   drivers/gpu//drm/i915/i915_drv.c:1624:1: warning: label 'out' defined but 
not used [-Wunused-label]
out:
^~~
>> drivers/gpu//drm/i915/i915_drv.c:1627:9: warning: 'error' is used 
>> uninitialized in this function [-Wuninitialized]
 return error;
^

vim +/error +1627 drivers/gpu//drm/i915/i915_drv.c

156987f3e drivers/gpu/drm/i915/i915_drv.c Chris Wilson  2018-05-22  1574  
5e365c391 drivers/gpu/drm/i915/i915_drv.c Imre Deak 2014-10-23  1575  
static int i915_drm_suspend(struct drm_device *dev)
ba8bbcf6f drivers/char/drm/i915_drv.c Jesse Barnes  2007-11-22  1576  {
fac5e23e3 drivers/gpu/drm/i915/i915_drv.c Chris Wilson  2016-07-04  1577
struct drm_i915_private *dev_priv = to_i915(dev);
52a05c302 drivers/gpu/drm/i915/i915_drv.c David Weinehall   2016-08-22  1578
struct pci_dev *pdev = dev_priv->drm.pdev;
e5747e3ad drivers/gpu/drm/i915/i915_drv.c Jesse Barnes  2014-06-12  1579
pci_power_t opregion_target_state;
d58189385 drivers/gpu/drm/i915/i915_drv.c Daniel Vetter 2015-02-23  1580
int error;
61caf87cb drivers/gpu/drm/i915/i915_drv.c Rafael J. Wysocki 2010-02-18  1581  
b8efb17b3 drivers/gpu/drm/i915/i915_drv.c Zhang Rui 2013-02-05  1582
/* ignore lid events during suspend */
b8efb17b3 drivers/gpu/drm/i915/i915_drv.c Zhang Rui 2013-02-05  1583
mutex_lock(_priv->modeset_restore_lock);
b8efb17b3 drivers/gpu/drm/i915/i915_drv.c Zhang Rui 2013-02-05  1584
dev_priv->modeset_restore = MODESET_SUSPENDED;
b8efb17b3 drivers/gpu/drm/i915/i915_drv.c Zhang Rui 2013-02-05  1585
mutex_unlock(_priv->modeset_restore_lock);
b8efb17b3 drivers/gpu/drm/i915/i915_drv.c Zhang Rui 2013-02-05  1586  
1f814daca drivers/gpu/drm/i915/i915_drv.c Imre Deak 2015-12-16  1587
disable_rpm_wakeref_asserts(dev_priv);
1f814daca drivers/gpu/drm/i915/i915_drv.c Imre Deak 2015-12-16  1588  
c67a470b1 drivers/gpu/drm/i915/i915_drv.c Paulo Zanoni  2013-08-19  1589
/* We do a lot of poking in a lot of registers, make sure they work
c67a470b1 drivers/gpu/drm/i915/i915_drv.c Paulo Zanoni  2013-08-19  1590
 * properly. */
da7e29bd5 drivers/gpu/drm/i915/i915_drv.c Imre Deak 2014-02-18  1591
intel_display_set_init_power(dev_priv, true);
cb10799c1 drivers/gpu/drm/i915/i915_drv.c Paulo Zanoni  2013-01-25  1592  
5bcf719b7 drivers/gpu/drm/i915/i915_drv.c Dave Airlie   2010-12-07  1593
drm_kms_helper_poll_disable(dev);
5bcf719b7 drivers/gpu/drm/i915/i915_drv.c Dave Airlie   2010-12-07  1594  
52a05c302 drivers/gpu/drm/i915/i915_drv.c David Weinehall   2016-08-22  1595
pci_save_state(pdev);
ba8bbcf6f drivers/char/drm/i915_drv.c Jesse Barnes  2007-11-22  1596  
6b72d4862 drivers/gpu/drm/i915/i915_drv.c Maarten Lankhorst 2015-06-01  1597
intel_display_suspend(dev);
7d708ee40 drivers/gpu/drm/i915/i915_drv.c Imre Deak 2013-04-17  1598  
0e32b39ce drivers/gpu/drm/i915/i915_drv.c Dave Airlie   2014-05-02  1599
intel_dp_mst_suspend(dev);
09b64267c drivers/gpu/drm/i915/i915_drv.c Dave Airlie   2014-07-23  1600  
b963291cf drivers/gpu/drm/i915/i915_drv.c Daniel Vetter 2014-09-30  1601
intel_runtime_pm_disable_interrupts(dev_priv);
1d0d343ab drivers/gpu/drm/i915/i915_drv.c Imre Deak 2014-08-18  1602
intel_hpd_cancel_work(dev_priv);
0e32b39ce drivers/gpu/drm/i915/i915_drv.c Dave Airlie   2014-05-02  1603  
07f9cd0b3 drivers/gpu/drm/i915/i915_drv.c Imre Deak 2014-08-18  1604
intel_suspend_encoders(dev_priv);
07f9cd0b3 drivers/gpu/drm/i915/i915_drv.c Imre Deak 2014-08-18  1605  
712bf3644 drivers/gpu/drm/i915/i915_drv.c Ville Syrjälä 2016-10-31  1606
intel_suspend_hw(dev_priv);
5669fcacc drivers/gpu/drm/i915/i915_drv.c Jesse Barnes  2009-02-17  1607  
275a991c0 drivers/gpu/drm/i915/i915_drv.c Tvrtko Ursulin2016-11-16  1608
i915_gem_suspend_gtt_mappings(dev_priv);
828c79087 drivers/gpu/drm/i915/i915_drv.c Ben Widawsky  2013-10-16  1609  
af6dc7425 drivers/gpu/drm/i915/i915_drv.c Tvrtko Ursulin2016-12-01  1610
i915_save_state(dev_priv);
9e06dd39f drivers/gpu/drm/i915/i915_drv.c Jess

Re: [Intel-gfx] [PATCH 4/4] drm/i915: "Race-to-idle" on switching to the kernel context

[kbuild test robot]

Hi Chris,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on next-20180517]
[cannot apply to drm-intel/for-linux-next v4.17-rc6 v4.17-rc5 v4.17-rc4 
v4.17-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Prepare-GEM-for-suspend-earlier/20180524-224509
config: x86_64-randconfig-x015-201820 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/selftests/igt_flush_test.c: In function 
'igt_flush_test':
>> drivers/gpu/drm/i915/selftests/igt_flush_test.c:61:6: error: too few 
>> arguments to function 'i915_gem_switch_to_kernel_context'
 i915_gem_switch_to_kernel_context(i915)) {
 ^
   In file included from drivers/gpu/drm/i915/selftests/../intel_lrc.h:28:0,
from drivers/gpu/drm/i915/selftests/../i915_drv.h:63,
from drivers/gpu/drm/i915/selftests/igt_flush_test.c:7:
   drivers/gpu/drm/i915/selftests/../i915_gem_context.h:297:5: note: declared 
here
int i915_gem_switch_to_kernel_context(struct drm_i915_private *i915,
^

vim +/i915_gem_switch_to_kernel_context +61 
drivers/gpu/drm/i915/selftests/igt_flush_test.c

98dc0454 Chris Wilson 2018-05-05  48  
98dc0454 Chris Wilson 2018-05-05  49  #define wedge_on_timeout(W, DEV, TIMEOUT) 
\
98dc0454 Chris Wilson 2018-05-05  50for (__init_wedge((W), (DEV), 
(TIMEOUT), __builtin_return_address(0)); \
98dc0454 Chris Wilson 2018-05-05  51 (W)->i915; 
\
98dc0454 Chris Wilson 2018-05-05  52 __fini_wedge((W)))
98dc0454 Chris Wilson 2018-05-05  53  
98dc0454 Chris Wilson 2018-05-05  54  int igt_flush_test(struct 
drm_i915_private *i915, unsigned int flags)
98dc0454 Chris Wilson 2018-05-05  55  {
98dc0454 Chris Wilson 2018-05-05  56struct wedge_me w;
98dc0454 Chris Wilson 2018-05-05  57  
98dc0454 Chris Wilson 2018-05-05  58cond_resched();
98dc0454 Chris Wilson 2018-05-05  59  
b9777c6f Chris Wilson 2018-05-09  60if (flags & I915_WAIT_LOCKED &&
b9777c6f Chris Wilson 2018-05-09 @61
i915_gem_switch_to_kernel_context(i915)) {

:: The code at line 61 was first introduced by commit
:: b9777c6f86ac8c21f82211ab982ca48302042ede drm/i915/selftests: Only switch 
to kernel context when locked

:: TO: Chris Wilson <ch...@chris-wilson.co.uk>
:: CC: Chris Wilson <ch...@chris-wilson.co.uk>

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip
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Re: [Intel-gfx] [PATCH 4/9] drm: Begin an API for in-kernel clients

[Thomas Hellstrom]

On 05/24/2018 12:14 PM, Daniel Vetter wrote:

On Thu, May 24, 2018 at 11:25:04AM +0200, Thomas Hellstrom wrote:

On 05/24/2018 10:32 AM, Daniel Vetter wrote:

On Wed, May 23, 2018 at 11:45:00PM +0200, Thomas Hellstrom wrote:

Hi, Noralf.

A couple of issues below:

On 05/23/2018 04:34 PM, Noralf Trønnes wrote:

This the beginning of an API for in-kernel clients.
First out is a way to get a framebuffer backed by a dumb buffer.

Only GEM drivers are supported.
The original idea of using an exported dma-buf was dropped because it
also creates an anonomous file descriptor which doesn't work when the
buffer is created from a kernel thread. The easy way out is to use
drm_driver.gem_prime_vmap to get the virtual address, which requires a
GEM object. This excludes the vmwgfx driver which is the only non-GEM
driver apart from the legacy ones. A solution for vmwgfx will have to be
worked out later if it wants to support the client API which it probably
will when we have a bootsplash client.

Couldn't you add vmap() and  vunmap() to the dumb buffer API for in-kernel
use rather than using GEM directly?

But the main issue is pinning. It looks like the buffers are going to be
vmapped() for a long time, which requires pinning, and that doesn't work for
some drivers when they bind the framebuffer to a plane, since that might
require pinning in another memory region and the vmap would have to be torn
down. Besides, buffer pinning should really be avoided if possible:

Since we can't page-fault vmaps, and setting up / tearing down vmaps is
potentially an expensive operation, could we perhaps have a mapping api that
allows the driver to cache vmaps?

vmap()   // Indicates that we want to map a bo
begin_access() // Returns a virtual address which may vary between calls.
Allows access. A fast operation. Behind the lines pins / reserves the bo and
returns a cached vmap if the bo didn't move since last begin_access(), which
is the typical case.
end_access() // Disable access. Unpins / unreserves the bo.
vunmap_cached() //Indicates that the map is no longer needed. The driver can
release the cached map.

The idea is that the API client would wrap all bo map accesses with
begin_access() end_access(), allowing for the bo to be moved in between.

So originally my ideas for the cpu side dma-buf interfaces where all meant
to handle this. But then the first implementations bothered with none of
this, but instead expected that stuff is pinned, and vmap Just Works.

Which yeah doesn't work for vmwgfx and is a pain in a few other cases.

I agree it'd be nice to fix all this, but it's also not a problem that
this patch set here started. And since it's all optional (and vmwgfx isn't
even using the current fb helper code) I think it's reasonable to address
this post-merge (if someone gets around to it ever). What we'd need is is
a fallback for when vmap doesn't exist (for fbdev that probably means a
vmalloc'ed buffer + manual uploads, because fbdev), plus making sure
dma-buf implementations actually implement it.

My argument here is that, If I understand Noralf, this is intended to be an
API exported outside of drm. In that case we shouldn't replicate the assumed
behaviour of incomplete dma-buf implementations in a new API. Also the fact
that vmwgfx currently isn't using the fbdev helpers isn't a good argument to
design an API so that vmwgfx can _never_ use the fbdev helpers. The reason
we aren't using them is that the kms implementation was so old that we
didn't implement the necessary helper callbacks...

Also, I might be misunderstanding the code a bit, but I doubt that vmwgfx is
the only hardware with pinning restrictions on the framebuffer? I was under
the assumption that most discrete hardware required the framebuffer to be
pinned in VRAM?

So the important question is, Is this a set of helpers for shared-memory GEM
drivers to implement fbdev? Then I wouldn't bother, If it's intended to
become an API for clients outside of DRM, then I would have to insist on the
API being changed to reflect that.

This is definitely not an api for anything outside of drm. Just an attempt
to consolidate kernel-internal drm access like fbdev, a simple bootsplash
or an emergency console would need to do. Having some limitations in the
initial versions, as long as we have some idea how to handle them, seems
perfectly fine to me. This isn't meant to be a mandatory replacement for
anything - no intentions of exporting this to userspace.



OK, yeah my concern is really for generic code and that there in the end 
would be too much code to change if we wanted to support this, but at 
least the generic code would be somewhat contained.


But it seems like we're at least in agreement on the problematic areas, 
and as long as they are open for change I guess we can live with that.


/Thomas

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915: Include i915_scheduler.h from i915_gem_context.h

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/2] drm/i915: Include i915_scheduler.h from 
i915_gem_context.h
URL   : https://patchwork.freedesktop.org/series/43710/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4233 -> Patchwork_9107 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9107 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9107, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43710/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9107:

  === IGT changes ===

 Warnings 

igt@gem_exec_gttfill@basic:
  fi-pnv-d510:SKIP -> PASS


== Known issues ==

  Here are the changes found in Patchwork_9107 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@debugfs_test@read_all_entries:
  fi-snb-2520m:   PASS -> INCOMPLETE (fdo#103713)

igt@gem_mmap_gtt@basic-small-bo-tiledx:
  fi-gdg-551: PASS -> FAIL (fdo#102575)

igt@kms_flip@basic-flip-vs-wf_vblank:
  fi-skl-6770hq:  PASS -> FAIL (fdo#100368)

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
  fi-skl-6770hq:  PASS -> FAIL (fdo#103481) +1


 Possible fixes 

igt@kms_flip@basic-flip-vs-wf_vblank:
  fi-hsw-4200u:   FAIL (fdo#100368) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713


== Participating hosts (44 -> 39) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4233 -> Patchwork_9107

  CI_DRM_4233: 0b7643db57abff1223f77fb8cbb8dd8a00ca9938 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4498: f9ecb79ad8b02278cfdb5b82495df47061c04f8f @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9107: 9524989a00856810365d0c144ce99af8b511c10e @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

9524989a0085 drm/i915: Forward declare struct intel_context
aa0e999e0736 drm/i915: Include i915_scheduler.h from i915_gem_context.h

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9107/issues.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Allow DBLSCAN user modes with eDP/LVDS/DSI

[Patchwork]

== Series Details ==

Series: drm/i915: Allow DBLSCAN user modes with eDP/LVDS/DSI
URL   : https://patchwork.freedesktop.org/series/43698/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4230_full -> Patchwork_9104_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9104_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9104_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43698/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9104_full:

  === IGT changes ===

 Possible regressions 

igt@drv_selftest@live_gtt:
  shard-kbl:  PASS -> FAIL


 Warnings 

igt@gem_exec_schedule@deep-bsd1:
  shard-kbl:  SKIP -> PASS

igt@pm_rc6_residency@rc6-accuracy:
  shard-snb:  PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_9104_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_selftest@live_hugepages:
  shard-kbl:  PASS -> INCOMPLETE (fdo#103665)

igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
  shard-glk:  PASS -> FAIL (fdo#105703)

igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
  shard-hsw:  PASS -> FAIL (fdo#103060)

igt@kms_flip@plain-flip-fb-recreate:
  shard-glk:  PASS -> FAIL (fdo#100368)

igt@kms_setmode@basic:
  shard-apl:  PASS -> FAIL (fdo#99912)

igt@perf_pmu@busy-double-start-vcs0:
  shard-snb:  PASS -> FAIL (fdo#105106)


 Possible fixes 

igt@drv_selftest@live_gtt:
  shard-glk:  INCOMPLETE (fdo#103359, k.org#198133) -> PASS

igt@drv_selftest@live_hangcheck:
  shard-apl:  DMESG-FAIL (fdo#106560) -> PASS

igt@gem_ppgtt@blt-vs-render-ctx0:
  shard-kbl:  INCOMPLETE (fdo#106023, fdo#103665) -> PASS

igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
  shard-glk:  FAIL (fdo#105703) -> PASS

igt@kms_flip@2x-flip-vs-expired-vblank:
  shard-hsw:  FAIL (fdo#102887) -> PASS

igt@kms_flip@2x-plain-flip-fb-recreate:
  shard-glk:  FAIL (fdo#100368) -> PASS

igt@kms_flip@flip-vs-expired-vblank-interruptible:
  shard-glk:  FAIL (fdo#102887, fdo#105363) -> PASS

igt@kms_flip@modeset-vs-vblank-race-interruptible:
  shard-hsw:  FAIL (fdo#103060) -> PASS

igt@kms_flip_tiling@flip-x-tiled:
  shard-glk:  FAIL (fdo#104724) -> PASS

igt@pm_rpm@modeset-non-lpsp-stress:
  shard-hsw:  DMESG-WARN (fdo#102614) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105106 https://bugs.freedesktop.org/show_bug.cgi?id=105106
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4230 -> Patchwork_9104

  CI_DRM_4230: 097c5e2d7cf300d1f9855a550bfdd5150410ffc4 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4498: f9ecb79ad8b02278cfdb5b82495df47061c04f8f @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9104: 82368323f7e2a1fbe3822bd2da4e1860f8ca418d @ 
git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9104/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/trace: Describe engines as class:instance pairs

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/trace: Describe engines as 
class:instance pairs
URL   : https://patchwork.freedesktop.org/series/43709/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4233 -> Patchwork_9106 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9106 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9106, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43709/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9106:

  === IGT changes ===

 Warnings 

igt@gem_exec_gttfill@basic:
  fi-pnv-d510:SKIP -> PASS


== Known issues ==

  Here are the changes found in Patchwork_9106 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@debugfs_test@read_all_entries:
  fi-bsw-n3050:   PASS -> DMESG-WARN (fdo#106207)

igt@gem_mmap_gtt@basic-small-bo-tiledx:
  fi-gdg-551: PASS -> FAIL (fdo#102575)


 Possible fixes 

igt@kms_flip@basic-flip-vs-wf_vblank:
  fi-hsw-4200u:   FAIL (fdo#100368) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#106207 https://bugs.freedesktop.org/show_bug.cgi?id=106207


== Participating hosts (44 -> 39) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4233 -> Patchwork_9106

  CI_DRM_4233: 0b7643db57abff1223f77fb8cbb8dd8a00ca9938 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4498: f9ecb79ad8b02278cfdb5b82495df47061c04f8f @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9106: 4f5293dac6122cdcb6456a96f29f8c69c73e0346 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4f5293dac612 drm/i915/trace: Remove engine out of the context sandwich
29e13710369f drm/i915/trace: Describe engines as class:instance pairs

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9106/issues.html
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/trace: Describe engines as class:instance pairs

[Lionel Landwerlin]

On 24/05/18 17:07, Tvrtko Ursulin wrote:


On 24/05/2018 16:53, Lionel Landwerlin wrote:

On 24/05/18 16:04, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

Instead of using the engine->id, use uabi_class:instance pairs in 
trace-

points including engine info.

This will be more readable, more future proof and more stable for
userspace consumption.

Signed-off-by: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: svetlana.kukan...@intel.com

Don't you want engine->uabi_id instead of engine->instance ?


No, class:instance is the new engine identifier - why do you think we 
would need legacy engine->uabi_id?


Maybe I forgot about your engine listing series...
I would expect the tracepoint to match the engines listed through that uapi.

-
Lionel



Regards,

Tvrtko



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Re: [Intel-gfx] [PATCH v7 7/7] drm/i915: add a sysfs entry to let users set sseu configs

[Lionel Landwerlin]

On 24/05/18 16:35, Tvrtko Ursulin wrote:


On 24/05/2018 15:54, Lionel Landwerlin wrote:

There are concerns about denial of service around the per context sseu
configuration capability. In a previous commit introducing the
capability we allowed it only for capable users. This changes adds a
new debugfs entry to let any user configure its own context
powergating setup.

v2: Rename sysfs entry (Tvrtko)
 Lock interruptible the device in sysfs (Tvrtko)
 Fix dropped error code in getting dynamic sseu value (Tvrtko)
 s/dev_priv/i915/ (Tvrtko)

Signed-off-by: Lionel Landwerlin 
---
  drivers/gpu/drm/i915/i915_drv.h |  6 
  drivers/gpu/drm/i915/i915_gem_context.c | 47 -
  drivers/gpu/drm/i915/i915_sysfs.c   | 40 +
  3 files changed, 92 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h 
b/drivers/gpu/drm/i915/i915_drv.h

index 916a301d8c22..3db75c56a9f7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1842,6 +1842,8 @@ struct drm_i915_private {
  struct ida hw_ida;
  #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
  #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
+
+    bool dynamic_sseu;
  } contexts;
    u32 fdi_rx_config;
@@ -3275,6 +3277,10 @@ i915_gem_context_lookup(struct 
drm_i915_file_private *file_priv, u32 id)

  return ctx;
  }
  +int i915_gem_contexts_set_dynamic_sseu_locked(struct 
drm_i915_private *i915,

+  bool allowed);
+bool i915_gem_contexts_get_dynamic_sseu(struct drm_i915_private *i915);
+
  int i915_perf_open_ioctl(struct drm_device *dev, void *data,
   struct drm_file *file);
  int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c

index 30736efe0fcd..afb7db95aa3b 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -983,7 +983,8 @@ int i915_gem_context_setparam_ioctl(struct 
drm_device *dev, void *data,

  break;
  }
  -    if (!capable(CAP_SYS_ADMIN)) {
+    if (!i915->contexts.dynamic_sseu &&
+    !capable(CAP_SYS_ADMIN)) {
  ret = -EPERM;
  break;
  }
@@ -1065,6 +1066,50 @@ int i915_gem_context_reset_stats_ioctl(struct 
drm_device *dev,

  return ret;
  }
  +int i915_gem_contexts_set_dynamic_sseu_locked(struct 
drm_i915_private *i915,

+  bool allowed)


I think you can drop the _locked suffix since we normally only use it 
when there are two flavours of otherwise the same function name. And 
you have lockdep_assert_held so that makes it obvious.



Okay




+{
+    struct intel_engine_cs *engine = i915->engine[RCS];
+    int ret = 0;
+
+    lockdep_assert_held(>drm.struct_mutex);
+
+    if (!engine->emit_rpcs_config)
+    return -ENODEV;
+
+    /*
+ * When we allow each context to configure its powergating
+ * configuration, there is no need to put the configurations 
back to

+ * the default, it should already be the case.
+ */
+    if (!allowed) {


Do you want to optimize with "if (!allowed && 
i915->context.dynamic_sseu)"?


Yep!




+    struct intel_sseu default_sseu =
+ intel_sseu_from_device_sseu(_INFO(i915)->sseu);


Quick grep around patches tells me this function is always called with 
the same parameter.  Unless I missed something perhaps it would be 
more readable to rename it to something shorter. Like maybe:


default_sseu = intel_device_default_sseu(i915);

Just thinking if that would read nicer than _INFO(i915)->sseu 
everywhere?


Sure.



Regards,

Tvrtko


+    struct i915_gem_context *ctx;
+
+    list_for_each_entry(ctx, >contexts.list, link) {
+    ret = i915_gem_context_reconfigure_sseu(ctx, engine,
+    default_sseu);
+    if (ret)
+    break;
+    }
+    }
+
+    i915->contexts.dynamic_sseu = allowed;
+
+    return ret;
+}
+
+bool i915_gem_contexts_get_dynamic_sseu(struct drm_i915_private *i915)
+{
+    struct intel_engine_cs *engine = i915->engine[RCS];
+
+    if (!engine->emit_rpcs_config)
+    return false;
+
+    return i915->contexts.dynamic_sseu;
+}
+
  #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
  #include "selftests/mock_context.c"
  #include "selftests/i915_gem_context.c"
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c

index e5e6f6bb2b05..c323cab59ec7 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -483,6 +483,44 @@ static ssize_t gt_rp_mhz_show(struct device 
*kdev, struct device_attribute *attr

  return snprintf(buf, PAGE_SIZE, "%d\n", val);
  }
  +static ssize_t allow_dynamic_sseu_show(struct device *kdev,
+   struct device_attribute *attr,
+  

Re: [Intel-gfx] [PATCH 1/2] drm/i915/trace: Describe engines as class:instance pairs

[Tvrtko Ursulin]

On 24/05/2018 16:53, Lionel Landwerlin wrote:

On 24/05/18 16:04, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

Instead of using the engine->id, use uabi_class:instance pairs in trace-
points including engine info.

This will be more readable, more future proof and more stable for
userspace consumption.

Signed-off-by: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: svetlana.kukan...@intel.com

Don't you want engine->uabi_id instead of engine->instance ?


No, class:instance is the new engine identifier - why do you think we 
would need legacy engine->uabi_id?


Regards,

Tvrtko
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/trace: Remove engine out of the context sandwich

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-05-24 16:48:45)
> 
> On 24/05/2018 16:33, Chris Wilson wrote:
> > But what we call ctx here isn't really context, but timeline; how about
> > if we switch to the fence=%llx:%d representation we've mostly settled on
> > for the debug messages?
> 
> For the ctx and seqno pair? But here we have the additional issue of 
> hw_id. I think context is better than timeline at this level.
> 
> Or you mean keep explicit hw_id and join ctx and seqno into fence=%llx:%d?

Right. I think what we call ctx here is very confusing, as it's just the
fence.context (i.e timeline id) and not any of the ids we assign to the
context (neither hw_id or uabi_id), so I don't think ctx refers to
i915_gem_context/intel_context at all and so would rather stop using
'ctx'.

Pardon the rambling, 
-Chris
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/trace: Describe engines as class:instance pairs

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/trace: Describe engines as 
class:instance pairs
URL   : https://patchwork.freedesktop.org/series/43709/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
29e13710369f drm/i915/trace: Describe engines as class:instance pairs
4f5293dac612 drm/i915/trace: Remove engine out of the context sandwich
-:31: ERROR:CODE_INDENT: code indent should use tabs where possible
#31: FILE: drivers/gpu/drm/i915/i915_trace.h:643:
+^I  __entry->hw_id, __entry->ctx, __entry->seqno,$

total: 1 errors, 0 warnings, 0 checks, 60 lines checked

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: per context slice/subslice powergating (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915: per context slice/subslice powergating (rev6)
URL   : https://patchwork.freedesktop.org/series/42285/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4233 -> Patchwork_9105 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/42285/revisions/6/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9105 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_mmap_gtt@basic-small-bo-tiledx:
  fi-gdg-551: PASS -> FAIL (fdo#102575)

igt@kms_pipe_crc_basic@read-crc-pipe-b:
  fi-skl-guc: PASS -> FAIL (fdo#104724, fdo#103191)

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
  fi-cnl-psr: PASS -> DMESG-WARN (fdo#104951)

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
  fi-bsw-n3050:   PASS -> DMESG-WARN (fdo#106207) +5
  fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927)


 Possible fixes 

igt@kms_flip@basic-flip-vs-wf_vblank:
  fi-hsw-4200u:   FAIL (fdo#100368) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
  fdo#106207 https://bugs.freedesktop.org/show_bug.cgi?id=106207


== Participating hosts (44 -> 39) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4233 -> Patchwork_9105

  CI_DRM_4233: 0b7643db57abff1223f77fb8cbb8dd8a00ca9938 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4498: f9ecb79ad8b02278cfdb5b82495df47061c04f8f @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9105: 9873e890b9cd81024b6b5fb48aeb2377ed6fba8e @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

9873e890b9cd drm/i915: add a sysfs entry to let users set sseu configs
957b375e185c drm/i915: Expose RPCS (SSEU) configuration to userspace
d099dffee67c drm/i915/perf: lock powergating configuration to default when 
active
763f9dc06a15 drm/i915/perf: reuse intel_lrc ctx regs macro
16d9bb4e86fc drm/i915/perf: simplify configure all context function
eb3c2a521a10 drm/i915: Record the sseu configuration per-context & engine
966969f546ac drm/i915: Program RPCS for Broadwell

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9105/issues.html
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/trace: Describe engines as class:instance pairs

[Lionel Landwerlin]

On 24/05/18 16:04, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

Instead of using the engine->id, use uabi_class:instance pairs in trace-
points including engine info.

This will be more readable, more future proof and more stable for
userspace consumption.

Signed-off-by: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: svetlana.kukan...@intel.com

Don't you want engine->uabi_id instead of engine->instance ?

---
  drivers/gpu/drm/i915/i915_trace.h | 107 ++
  1 file changed, 65 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_trace.h 
b/drivers/gpu/drm/i915/i915_trace.h
index 5d4f78765083..3465cc1f9345 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -591,21 +591,26 @@ TRACE_EVENT(i915_gem_ring_sync_to,
  
  	TP_STRUCT__entry(

 __field(u32, dev)
-__field(u32, sync_from)
-__field(u32, sync_to)
+__field(u32, from_class)
+__field(u32, from_instance)
+__field(u32, to_class)
+__field(u32, to_instance)
 __field(u32, seqno)
 ),
  
  	TP_fast_assign(

   __entry->dev = from->i915->drm.primary->index;
-  __entry->sync_from = from->engine->id;
-  __entry->sync_to = to->engine->id;
+  __entry->from_class = from->engine->uabi_class;
+  __entry->from_instance = from->engine->instance;
+  __entry->to_class = to->engine->uabi_class;
+  __entry->to_instance = to->engine->instance;
   __entry->seqno = from->global_seqno;
   ),
  
-	TP_printk("dev=%u, sync-from=%u, sync-to=%u, seqno=%u",

+   TP_printk("dev=%u, sync-from=%u:%u, sync-to=%u:%u, seqno=%u",
  __entry->dev,
- __entry->sync_from, __entry->sync_to,
+ __entry->from_class, __entry->from_instance,
+ __entry->to_class, __entry->to_instance,
  __entry->seqno)
  );
  
@@ -616,7 +621,8 @@ TRACE_EVENT(i915_request_queue,

TP_STRUCT__entry(
 __field(u32, dev)
 __field(u32, hw_id)
-__field(u32, ring)
+__field(u32, class)
+__field(u32, instance)
 __field(u32, ctx)
 __field(u32, seqno)
 __field(u32, flags)
@@ -625,15 +631,17 @@ TRACE_EVENT(i915_request_queue,
TP_fast_assign(
   __entry->dev = rq->i915->drm.primary->index;
   __entry->hw_id = rq->gem_context->hw_id;
-  __entry->ring = rq->engine->id;
+  __entry->class = rq->engine->uabi_class;
+  __entry->instance = rq->engine->instance;
   __entry->ctx = rq->fence.context;
   __entry->seqno = rq->fence.seqno;
   __entry->flags = flags;
   ),
  
-	TP_printk("dev=%u, hw_id=%u, ring=%u, ctx=%u, seqno=%u, flags=0x%x",

- __entry->dev, __entry->hw_id, __entry->ring, __entry->ctx,
- __entry->seqno, __entry->flags)
+   TP_printk("dev=%u, hw_id=%u, engine=%u:%u, ctx=%u, seqno=%u, 
flags=0x%x",
+ __entry->dev, __entry->hw_id, __entry->class,
+ __entry->instance, __entry->ctx, __entry->seqno,
+ __entry->flags)
  );
  
  DECLARE_EVENT_CLASS(i915_request,

@@ -643,7 +651,8 @@ DECLARE_EVENT_CLASS(i915_request,
TP_STRUCT__entry(
 __field(u32, dev)
 __field(u32, hw_id)
-__field(u32, ring)
+__field(u32, class)
+__field(u32, instance)
 __field(u32, ctx)
 __field(u32, seqno)
 __field(u32, global)
@@ -652,15 +661,17 @@ DECLARE_EVENT_CLASS(i915_request,
TP_fast_assign(
   __entry->dev = rq->i915->drm.primary->index;
   __entry->hw_id = rq->gem_context->hw_id;
-  __entry->ring = rq->engine->id;
+  __entry->class = rq->engine->uabi_class;
+  __entry->instance = rq->engine->instance;
   __entry->ctx = rq->fence.context;
   __entry->seqno = 

Re: [Intel-gfx] [PATCH 2/2] drm/i915/trace: Remove engine out of the context sandwich

[Tvrtko Ursulin]

On 24/05/2018 16:48, Lionel Landwerlin wrote:

On 24/05/18 16:04, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

In the string tracepoint representation we ended up with the engine
sandwiched between context hardware id and context fence id.

Move the two pieces of context data together and consolidate for
redability using the format of ctx=hw_id:fence_context_id.


Arg! Will need to update the tracepoint parser in igt :(


I'll leave them separate then, was mostly aiming to remove engine out of 
the sandwich.


Regards,

Tvrtko



Binary records are left as is, that is both fields remaing under the
existing name and ordering.

Signed-off-by: Tvrtko Ursulin 
Cc: Lionel Landwerlin 
---
  drivers/gpu/drm/i915/i915_trace.h | 30 +++---
  1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_trace.h 
b/drivers/gpu/drm/i915/i915_trace.h

index 3465cc1f9345..ab67b1661de4 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -638,9 +638,9 @@ TRACE_EVENT(i915_request_queue,
 __entry->flags = flags;
 ),
-    TP_printk("dev=%u, hw_id=%u, engine=%u:%u, ctx=%u, seqno=%u, 
flags=0x%x",

-  __entry->dev, __entry->hw_id, __entry->class,
-  __entry->instance, __entry->ctx, __entry->seqno,
+    TP_printk("dev=%u, engine=%u:%u, ctx=%u:%u, seqno=%u, 
flags=0x%x",

+  __entry->dev, __entry->class, __entry->instance,
+  __entry->hw_id, __entry->ctx, __entry->seqno,
    __entry->flags)
  );
@@ -668,9 +668,9 @@ DECLARE_EVENT_CLASS(i915_request,
 __entry->global = rq->global_seqno;
 ),
-    TP_printk("dev=%u, hw_id=%u, engine=%u:%u, ctx=%u, seqno=%u, 
global=%u",

-  __entry->dev, __entry->hw_id, __entry->class,
-  __entry->instance, __entry->ctx, __entry->seqno,
+    TP_printk("dev=%u, engine=%u:%u, ctx=%u:%u, seqno=%u, 
global=%u",

+  __entry->dev, __entry->class, __entry->instance,
+  __entry->hw_id, __entry->ctx, __entry->seqno,
    __entry->global)
  );
@@ -718,9 +718,9 @@ TRACE_EVENT(i915_request_in,
 __entry->port = port;
 ),
-    TP_printk("dev=%u, hw_id=%u, engine=%u:%u, ctx=%u, seqno=%u, 
prio=%u, global=%u, port=%u",

-  __entry->dev, __entry->hw_id, __entry->class,
-  __entry->instance, __entry->ctx, __entry->seqno,
+    TP_printk("dev=%u, engine=%u:%u, ctx=%u:%u, seqno=%u, 
prio=%u, global=%u, port=%u",

+  __entry->dev, __entry->class, __entry->instance,
+  __entry->hw_id, __entry->ctx, __entry->seqno,
    __entry->prio, __entry->global_seqno, __entry->port)
  );
@@ -750,9 +750,9 @@ TRACE_EVENT(i915_request_out,
 __entry->completed = i915_request_completed(rq);
 ),
-    TP_printk("dev=%u, hw_id=%u, engine=%u:%u, ctx=%u, 
seqno=%u, global=%u, completed?=%u",

-  __entry->dev, __entry->hw_id, __entry->class,
-  __entry->instance, __entry->ctx, __entry->seqno,
+    TP_printk("dev=%u, engine=%u:%u, ctx=%u:%u, seqno=%u, 
global=%u, completed?=%u",

+  __entry->dev, __entry->class, __entry->instance,
+  __entry->hw_id, __entry->ctx, __entry->seqno,
    __entry->global_seqno, __entry->completed)
  );
@@ -842,9 +842,9 @@ TRACE_EVENT(i915_request_wait_begin,
 __entry->flags = flags;
 ),
-    TP_printk("dev=%u, hw_id=%u, engine=%u:%u, ctx=%u, seqno=%u, 
global=%u, blocking=%u, flags=0x%x",

-  __entry->dev, __entry->hw_id, __entry->class,
-  __entry->instance, __entry->ctx, __entry->seqno,
+    TP_printk("dev=%u, engine=%u:%u, ctx=%u:%u, seqno=%u, 
global=%u, blocking=%u, flags=0x%x",

+  __entry->dev, __entry->class, __entry->instance,
+  __entry->hw_id, __entry->ctx, __entry->seqno,
    __entry->global, !!(__entry->flags & I915_WAIT_LOCKED),
    __entry->flags)
  );



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Re: [Intel-gfx] [PATCH 2/2] drm/i915/trace: Remove engine out of the context sandwich

[Lionel Landwerlin]

On 24/05/18 16:04, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

In the string tracepoint representation we ended up with the engine
sandwiched between context hardware id and context fence id.

Move the two pieces of context data together and consolidate for
redability using the format of ctx=hw_id:fence_context_id.


Arg! Will need to update the tracepoint parser in igt :(



Binary records are left as is, that is both fields remaing under the
existing name and ordering.

Signed-off-by: Tvrtko Ursulin 
Cc: Lionel Landwerlin 
---
  drivers/gpu/drm/i915/i915_trace.h | 30 +++---
  1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_trace.h 
b/drivers/gpu/drm/i915/i915_trace.h
index 3465cc1f9345..ab67b1661de4 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -638,9 +638,9 @@ TRACE_EVENT(i915_request_queue,
   __entry->flags = flags;
   ),
  
-	TP_printk("dev=%u, hw_id=%u, engine=%u:%u, ctx=%u, seqno=%u, flags=0x%x",

- __entry->dev, __entry->hw_id, __entry->class,
- __entry->instance, __entry->ctx, __entry->seqno,
+   TP_printk("dev=%u, engine=%u:%u, ctx=%u:%u, seqno=%u, flags=0x%x",
+ __entry->dev, __entry->class, __entry->instance,
+ __entry->hw_id, __entry->ctx, __entry->seqno,
  __entry->flags)
  );
  
@@ -668,9 +668,9 @@ DECLARE_EVENT_CLASS(i915_request,

   __entry->global = rq->global_seqno;
   ),
  
-	TP_printk("dev=%u, hw_id=%u, engine=%u:%u, ctx=%u, seqno=%u, global=%u",

- __entry->dev, __entry->hw_id, __entry->class,
- __entry->instance, __entry->ctx, __entry->seqno,
+   TP_printk("dev=%u, engine=%u:%u, ctx=%u:%u, seqno=%u, global=%u",
+ __entry->dev, __entry->class, __entry->instance,
+ __entry->hw_id, __entry->ctx, __entry->seqno,
  __entry->global)
  );
  
@@ -718,9 +718,9 @@ TRACE_EVENT(i915_request_in,

   __entry->port = port;
   ),
  
-	TP_printk("dev=%u, hw_id=%u, engine=%u:%u, ctx=%u, seqno=%u, prio=%u, global=%u, port=%u",

- __entry->dev, __entry->hw_id, __entry->class,
- __entry->instance, __entry->ctx, __entry->seqno,
+   TP_printk("dev=%u, engine=%u:%u, ctx=%u:%u, seqno=%u, prio=%u, 
global=%u, port=%u",
+ __entry->dev, __entry->class, __entry->instance,
+ __entry->hw_id, __entry->ctx, __entry->seqno,
  __entry->prio, __entry->global_seqno, __entry->port)
  );
  
@@ -750,9 +750,9 @@ TRACE_EVENT(i915_request_out,

   __entry->completed = i915_request_completed(rq);
   ),
  
-		TP_printk("dev=%u, hw_id=%u, engine=%u:%u, ctx=%u, seqno=%u, global=%u, completed?=%u",

- __entry->dev, __entry->hw_id, __entry->class,
- __entry->instance, __entry->ctx, __entry->seqno,
+   TP_printk("dev=%u, engine=%u:%u, ctx=%u:%u, seqno=%u, global=%u, 
completed?=%u",
+ __entry->dev, __entry->class, __entry->instance,
+ __entry->hw_id, __entry->ctx, __entry->seqno,
  __entry->global_seqno, __entry->completed)
  );
  
@@ -842,9 +842,9 @@ TRACE_EVENT(i915_request_wait_begin,

   __entry->flags = flags;
   ),
  
-	TP_printk("dev=%u, hw_id=%u, engine=%u:%u, ctx=%u, seqno=%u, global=%u, blocking=%u, flags=0x%x",

- __entry->dev, __entry->hw_id, __entry->class,
- __entry->instance, __entry->ctx, __entry->seqno,
+   TP_printk("dev=%u, engine=%u:%u, ctx=%u:%u, seqno=%u, global=%u, 
blocking=%u, flags=0x%x",
+ __entry->dev, __entry->class, __entry->instance,
+ __entry->hw_id, __entry->ctx, __entry->seqno,
  __entry->global, !!(__entry->flags & I915_WAIT_LOCKED),
  __entry->flags)
  );



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Re: [Intel-gfx] [PATCH 2/2] drm/i915/trace: Remove engine out of the context sandwich

[Tvrtko Ursulin]

On 24/05/2018 16:33, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-05-24 16:04:47)

From: Tvrtko Ursulin 

In the string tracepoint representation we ended up with the engine
sandwiched between context hardware id and context fence id.

Move the two pieces of context data together and consolidate for
redability using the format of ctx=hw_id:fence_context_id.


Grr, bring backs my memory of ctx being the most important!


I knew it! :))


In order of segregation, I think of it as device+context as being the
outer container (a user isn't meant to escape their context). The
timelines and engines they use are all contained within their context.


If I move ctx before engine, then seqno is left to hang after the engine.

And honestly I forgot all my arguments in this topic. By the virtue of 
exhaustion I am prepared to give in. :))



But what we call ctx here isn't really context, but timeline; how about
if we switch to the fence=%llx:%d representation we've mostly settled on
for the debug messages?


For the ctx and seqno pair? But here we have the additional issue of 
hw_id. I think context is better than timeline at this level.


Or you mean keep explicit hw_id and join ctx and seqno into fence=%llx:%d?

Regards,

Tvrtko
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: per context slice/subslice powergating (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915: per context slice/subslice powergating (rev6)
URL   : https://patchwork.freedesktop.org/series/42285/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915: Program RPCS for Broadwell
Okay!

Commit: drm/i915: Record the sseu configuration per-context & engine
Okay!

Commit: drm/i915/perf: simplify configure all context function
Okay!

Commit: drm/i915/perf: reuse intel_lrc ctx regs macro
Okay!

Commit: drm/i915/perf: lock powergating configuration to default when active
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3664:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3680:16: warning: expression 
using sizeof(void)

Commit: drm/i915: Expose RPCS (SSEU) configuration to userspace
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3680:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3693:16: warning: expression 
using sizeof(void)

Commit: drm/i915: add a sysfs entry to let users set sseu configs
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3693:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3699:16: warning: expression 
using sizeof(void)

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Re: [Intel-gfx] [PATCH 1/2] drm/i915/trace: Describe engines as class:instance pairs

[Tvrtko Ursulin]

On 24/05/2018 16:29, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-05-24 16:04:46)

From: Tvrtko Ursulin 

Instead of using the engine->id, use uabi_class:instance pairs in trace-
points including engine info.


Should we not pack dev,hw_id,class,instance into u16s?


Can do.


This will be more readable, more future proof and more stable for
userspace consumption.

Signed-off-by: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: svetlana.kukan...@intel.com
---
@@ -616,7 +621,8 @@ TRACE_EVENT(i915_request_queue,
 TP_STRUCT__entry(
  __field(u32, dev)
  __field(u32, hw_id)
-__field(u32, ring)
+__field(u32, class)
+__field(u32, instance)
  __field(u32, ctx)


ctx needs u64 :(
I've no objection to switching to our hopefully futureproof uabi
nomenclature.

Reviewed-by: Chris Wilson 


Thanks, I'll grow the series with all of the above.

Regards,

Tvrtko
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: per context slice/subslice powergating (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915: per context slice/subslice powergating (rev6)
URL   : https://patchwork.freedesktop.org/series/42285/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
966969f546ac drm/i915: Program RPCS for Broadwell
eb3c2a521a10 drm/i915: Record the sseu configuration per-context & engine
16d9bb4e86fc drm/i915/perf: simplify configure all context function
763f9dc06a15 drm/i915/perf: reuse intel_lrc ctx regs macro
d099dffee67c drm/i915/perf: lock powergating configuration to default when 
active
957b375e185c drm/i915: Expose RPCS (SSEU) configuration to userspace
-:40: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#40: 
v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu() (Lionel)

total: 0 errors, 1 warnings, 0 checks, 456 lines checked
9873e890b9cd drm/i915: add a sysfs entry to let users set sseu configs

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Re: [Intel-gfx] [PATCH v7 7/7] drm/i915: add a sysfs entry to let users set sseu configs

[Tvrtko Ursulin]

On 24/05/2018 15:54, Lionel Landwerlin wrote:

There are concerns about denial of service around the per context sseu
configuration capability. In a previous commit introducing the
capability we allowed it only for capable users. This changes adds a
new debugfs entry to let any user configure its own context
powergating setup.

v2: Rename sysfs entry (Tvrtko)
 Lock interruptible the device in sysfs (Tvrtko)
 Fix dropped error code in getting dynamic sseu value (Tvrtko)
 s/dev_priv/i915/ (Tvrtko)

Signed-off-by: Lionel Landwerlin 
---
  drivers/gpu/drm/i915/i915_drv.h |  6 
  drivers/gpu/drm/i915/i915_gem_context.c | 47 -
  drivers/gpu/drm/i915/i915_sysfs.c   | 40 +
  3 files changed, 92 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 916a301d8c22..3db75c56a9f7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1842,6 +1842,8 @@ struct drm_i915_private {
struct ida hw_ida;
  #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
  #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
+
+   bool dynamic_sseu;
} contexts;
  
  	u32 fdi_rx_config;

@@ -3275,6 +3277,10 @@ i915_gem_context_lookup(struct drm_i915_file_private 
*file_priv, u32 id)
return ctx;
  }
  
+int i915_gem_contexts_set_dynamic_sseu_locked(struct drm_i915_private *i915,

+ bool allowed);
+bool i915_gem_contexts_get_dynamic_sseu(struct drm_i915_private *i915);
+
  int i915_perf_open_ioctl(struct drm_device *dev, void *data,
 struct drm_file *file);
  int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 30736efe0fcd..afb7db95aa3b 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -983,7 +983,8 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, 
void *data,
break;
}
  
-			if (!capable(CAP_SYS_ADMIN)) {

+   if (!i915->contexts.dynamic_sseu &&
+   !capable(CAP_SYS_ADMIN)) {
ret = -EPERM;
break;
}
@@ -1065,6 +1066,50 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device 
*dev,
return ret;
  }
  
+int i915_gem_contexts_set_dynamic_sseu_locked(struct drm_i915_private *i915,

+ bool allowed)


I think you can drop the _locked suffix since we normally only use it 
when there are two flavours of otherwise the same function name. And you 
have lockdep_assert_held so that makes it obvious.



+{
+   struct intel_engine_cs *engine = i915->engine[RCS];
+   int ret = 0;
+
+   lockdep_assert_held(>drm.struct_mutex);
+
+   if (!engine->emit_rpcs_config)
+   return -ENODEV;
+
+   /*
+* When we allow each context to configure its powergating
+* configuration, there is no need to put the configurations back to
+* the default, it should already be the case.
+*/
+   if (!allowed) {


Do you want to optimize with "if (!allowed && i915->context.dynamic_sseu)"?


+   struct intel_sseu default_sseu =
+   intel_sseu_from_device_sseu(_INFO(i915)->sseu);


Quick grep around patches tells me this function is always called with 
the same parameter.  Unless I missed something perhaps it would be more 
readable to rename it to something shorter. Like maybe:


default_sseu = intel_device_default_sseu(i915);

Just thinking if that would read nicer than _INFO(i915)->sseu 
everywhere?


Regards,

Tvrtko


+   struct i915_gem_context *ctx;
+
+   list_for_each_entry(ctx, >contexts.list, link) {
+   ret = i915_gem_context_reconfigure_sseu(ctx, engine,
+   default_sseu);
+   if (ret)
+   break;
+   }
+   }
+
+   i915->contexts.dynamic_sseu = allowed;
+
+   return ret;
+}
+
+bool i915_gem_contexts_get_dynamic_sseu(struct drm_i915_private *i915)
+{
+   struct intel_engine_cs *engine = i915->engine[RCS];
+
+   if (!engine->emit_rpcs_config)
+   return false;
+
+   return i915->contexts.dynamic_sseu;
+}
+
  #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
  #include "selftests/mock_context.c"
  #include "selftests/i915_gem_context.c"
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c
index e5e6f6bb2b05..c323cab59ec7 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -483,6 +483,44 @@ static ssize_t 

Re: [Intel-gfx] [PATCH 2/2] drm/i915/trace: Remove engine out of the context sandwich

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-05-24 16:04:47)
> From: Tvrtko Ursulin 
> 
> In the string tracepoint representation we ended up with the engine
> sandwiched between context hardware id and context fence id.
> 
> Move the two pieces of context data together and consolidate for
> redability using the format of ctx=hw_id:fence_context_id.

Grr, bring backs my memory of ctx being the most important!

In order of segregation, I think of it as device+context as being the
outer container (a user isn't meant to escape their context). The
timelines and engines they use are all contained within their context.

But what we call ctx here isn't really context, but timeline; how about
if we switch to the fence=%llx:%d representation we've mostly settled on
for the debug messages?
-Chris
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/trace: Describe engines as class:instance pairs

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-05-24 16:04:46)
> From: Tvrtko Ursulin 
> 
> Instead of using the engine->id, use uabi_class:instance pairs in trace-
> points including engine info.

Should we not pack dev,hw_id,class,instance into u16s?

> This will be more readable, more future proof and more stable for
> userspace consumption.
> 
> Signed-off-by: Tvrtko Ursulin 
> Cc: Chris Wilson 
> Cc: svetlana.kukan...@intel.com
> ---
> @@ -616,7 +621,8 @@ TRACE_EVENT(i915_request_queue,
> TP_STRUCT__entry(
>  __field(u32, dev)
>  __field(u32, hw_id)
> -__field(u32, ring)
> +__field(u32, class)
> +__field(u32, instance)
>  __field(u32, ctx)

ctx needs u64 :(

I've no objection to switching to our hopefully futureproof uabi
nomenclature.

Reviewed-by: Chris Wilson 
-Chris
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[Intel-gfx] [CI 2/2] drm/i915: Forward declare struct intel_context

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

This is to avoid an error with structure declared in parameter list if the
include ordering changes.

Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem_context.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.h 
b/drivers/gpu/drm/i915/i915_gem_context.h
index 84fef3b1e6e4..b116e4942c10 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -46,6 +46,8 @@ struct intel_ring;
 
 #define DEFAULT_CONTEXT_HANDLE 0
 
+struct intel_context;
+
 struct intel_context_ops {
void (*unpin)(struct intel_context *ce);
void (*destroy)(struct intel_context *ce);
-- 
2.17.0

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[Intel-gfx] [CI 1/2] drm/i915: Include i915_scheduler.h from i915_gem_context.h

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

struct i915_gem_context embeds structr i915_sched_attr so needs to include
the respective header.

Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem_context.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.h 
b/drivers/gpu/drm/i915/i915_gem_context.h
index c3262b4dd2ee..84fef3b1e6e4 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -30,6 +30,7 @@
 #include 
 
 #include "i915_gem.h"
+#include "i915_scheduler.h"
 
 struct pid;
 
-- 
2.17.0

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[Intel-gfx] [PATCH 2/2] drm/i915/trace: Remove engine out of the context sandwich

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

In the string tracepoint representation we ended up with the engine
sandwiched between context hardware id and context fence id.

Move the two pieces of context data together and consolidate for
redability using the format of ctx=hw_id:fence_context_id.

Binary records are left as is, that is both fields remaing under the
existing name and ordering.

Signed-off-by: Tvrtko Ursulin 
Cc: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_trace.h | 30 +++---
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_trace.h 
b/drivers/gpu/drm/i915/i915_trace.h
index 3465cc1f9345..ab67b1661de4 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -638,9 +638,9 @@ TRACE_EVENT(i915_request_queue,
   __entry->flags = flags;
   ),
 
-   TP_printk("dev=%u, hw_id=%u, engine=%u:%u, ctx=%u, seqno=%u, 
flags=0x%x",
- __entry->dev, __entry->hw_id, __entry->class,
- __entry->instance, __entry->ctx, __entry->seqno,
+   TP_printk("dev=%u, engine=%u:%u, ctx=%u:%u, seqno=%u, flags=0x%x",
+ __entry->dev, __entry->class, __entry->instance,
+ __entry->hw_id, __entry->ctx, __entry->seqno,
  __entry->flags)
 );
 
@@ -668,9 +668,9 @@ DECLARE_EVENT_CLASS(i915_request,
   __entry->global = rq->global_seqno;
   ),
 
-   TP_printk("dev=%u, hw_id=%u, engine=%u:%u, ctx=%u, seqno=%u, 
global=%u",
- __entry->dev, __entry->hw_id, __entry->class,
- __entry->instance, __entry->ctx, __entry->seqno,
+   TP_printk("dev=%u, engine=%u:%u, ctx=%u:%u, seqno=%u, global=%u",
+ __entry->dev, __entry->class, __entry->instance,
+ __entry->hw_id, __entry->ctx, __entry->seqno,
  __entry->global)
 );
 
@@ -718,9 +718,9 @@ TRACE_EVENT(i915_request_in,
   __entry->port = port;
   ),
 
-   TP_printk("dev=%u, hw_id=%u, engine=%u:%u, ctx=%u, seqno=%u, 
prio=%u, global=%u, port=%u",
- __entry->dev, __entry->hw_id, __entry->class,
- __entry->instance, __entry->ctx, __entry->seqno,
+   TP_printk("dev=%u, engine=%u:%u, ctx=%u:%u, seqno=%u, prio=%u, 
global=%u, port=%u",
+ __entry->dev, __entry->class, __entry->instance,
+ __entry->hw_id, __entry->ctx, __entry->seqno,
  __entry->prio, __entry->global_seqno, __entry->port)
 );
 
@@ -750,9 +750,9 @@ TRACE_EVENT(i915_request_out,
   __entry->completed = i915_request_completed(rq);
   ),
 
-   TP_printk("dev=%u, hw_id=%u, engine=%u:%u, ctx=%u, 
seqno=%u, global=%u, completed?=%u",
- __entry->dev, __entry->hw_id, __entry->class,
- __entry->instance, __entry->ctx, __entry->seqno,
+   TP_printk("dev=%u, engine=%u:%u, ctx=%u:%u, seqno=%u, 
global=%u, completed?=%u",
+ __entry->dev, __entry->class, __entry->instance,
+ __entry->hw_id, __entry->ctx, __entry->seqno,
  __entry->global_seqno, __entry->completed)
 );
 
@@ -842,9 +842,9 @@ TRACE_EVENT(i915_request_wait_begin,
   __entry->flags = flags;
   ),
 
-   TP_printk("dev=%u, hw_id=%u, engine=%u:%u, ctx=%u, seqno=%u, 
global=%u, blocking=%u, flags=0x%x",
- __entry->dev, __entry->hw_id, __entry->class,
- __entry->instance, __entry->ctx, __entry->seqno,
+   TP_printk("dev=%u, engine=%u:%u, ctx=%u:%u, seqno=%u, global=%u, 
blocking=%u, flags=0x%x",
+ __entry->dev, __entry->class, __entry->instance,
+ __entry->hw_id, __entry->ctx, __entry->seqno,
  __entry->global, !!(__entry->flags & I915_WAIT_LOCKED),
  __entry->flags)
 );
-- 
2.17.0

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[Intel-gfx] [PATCH 1/2] drm/i915/trace: Describe engines as class:instance pairs

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Instead of using the engine->id, use uabi_class:instance pairs in trace-
points including engine info.

This will be more readable, more future proof and more stable for
userspace consumption.

Signed-off-by: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: svetlana.kukan...@intel.com
---
 drivers/gpu/drm/i915/i915_trace.h | 107 ++
 1 file changed, 65 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_trace.h 
b/drivers/gpu/drm/i915/i915_trace.h
index 5d4f78765083..3465cc1f9345 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -591,21 +591,26 @@ TRACE_EVENT(i915_gem_ring_sync_to,
 
TP_STRUCT__entry(
 __field(u32, dev)
-__field(u32, sync_from)
-__field(u32, sync_to)
+__field(u32, from_class)
+__field(u32, from_instance)
+__field(u32, to_class)
+__field(u32, to_instance)
 __field(u32, seqno)
 ),
 
TP_fast_assign(
   __entry->dev = from->i915->drm.primary->index;
-  __entry->sync_from = from->engine->id;
-  __entry->sync_to = to->engine->id;
+  __entry->from_class = from->engine->uabi_class;
+  __entry->from_instance = from->engine->instance;
+  __entry->to_class = to->engine->uabi_class;
+  __entry->to_instance = to->engine->instance;
   __entry->seqno = from->global_seqno;
   ),
 
-   TP_printk("dev=%u, sync-from=%u, sync-to=%u, seqno=%u",
+   TP_printk("dev=%u, sync-from=%u:%u, sync-to=%u:%u, seqno=%u",
  __entry->dev,
- __entry->sync_from, __entry->sync_to,
+ __entry->from_class, __entry->from_instance,
+ __entry->to_class, __entry->to_instance,
  __entry->seqno)
 );
 
@@ -616,7 +621,8 @@ TRACE_EVENT(i915_request_queue,
TP_STRUCT__entry(
 __field(u32, dev)
 __field(u32, hw_id)
-__field(u32, ring)
+__field(u32, class)
+__field(u32, instance)
 __field(u32, ctx)
 __field(u32, seqno)
 __field(u32, flags)
@@ -625,15 +631,17 @@ TRACE_EVENT(i915_request_queue,
TP_fast_assign(
   __entry->dev = rq->i915->drm.primary->index;
   __entry->hw_id = rq->gem_context->hw_id;
-  __entry->ring = rq->engine->id;
+  __entry->class = rq->engine->uabi_class;
+  __entry->instance = rq->engine->instance;
   __entry->ctx = rq->fence.context;
   __entry->seqno = rq->fence.seqno;
   __entry->flags = flags;
   ),
 
-   TP_printk("dev=%u, hw_id=%u, ring=%u, ctx=%u, seqno=%u, flags=0x%x",
- __entry->dev, __entry->hw_id, __entry->ring, __entry->ctx,
- __entry->seqno, __entry->flags)
+   TP_printk("dev=%u, hw_id=%u, engine=%u:%u, ctx=%u, seqno=%u, 
flags=0x%x",
+ __entry->dev, __entry->hw_id, __entry->class,
+ __entry->instance, __entry->ctx, __entry->seqno,
+ __entry->flags)
 );
 
 DECLARE_EVENT_CLASS(i915_request,
@@ -643,7 +651,8 @@ DECLARE_EVENT_CLASS(i915_request,
TP_STRUCT__entry(
 __field(u32, dev)
 __field(u32, hw_id)
-__field(u32, ring)
+__field(u32, class)
+__field(u32, instance)
 __field(u32, ctx)
 __field(u32, seqno)
 __field(u32, global)
@@ -652,15 +661,17 @@ DECLARE_EVENT_CLASS(i915_request,
TP_fast_assign(
   __entry->dev = rq->i915->drm.primary->index;
   __entry->hw_id = rq->gem_context->hw_id;
-  __entry->ring = rq->engine->id;
+  __entry->class = rq->engine->uabi_class;
+  __entry->instance = rq->engine->instance;
   __entry->ctx = rq->fence.context;
   __entry->seqno = rq->fence.seqno;
   __entry->global = rq->global_seqno;
  

[Intel-gfx] [PATCH v7 6/7] drm/i915: Expose RPCS (SSEU) configuration to userspace

[Lionel Landwerlin]

From: Chris Wilson 

We want to allow userspace to reconfigure the subslice configuration for
its own use case. To do so, we expose a context parameter to allow
adjustment of the RPCS register stored within the context image (and
currently not accessible via LRI). If the context is adjusted before
first use, the adjustment is for "free"; otherwise if the context is
active we flush the context off the GPU (stalling all users) and forcing
the GPU to save the context to memory where we can modify it and so
ensure that the register is reloaded on next execution.

The overhead of managing additional EU subslices can be significant,
especially in multi-context workloads. Non-GPGPU contexts should
preferably disable the subslices it is not using, and others should
fine-tune the number to match their workload.

We expose complete control over the RPCS register, allowing
configuration of slice/subslice, via masks packed into a u64 for
simplicity. For example,

struct drm_i915_gem_context_param arg;
struct drm_i915_gem_context_param_sseu sseu = { .class = 0,
.instance = 0, };

memset(, 0, sizeof(arg));
arg.ctx_id = ctx;
arg.param = I915_CONTEXT_PARAM_SSEU;
arg.value = (uintptr_t) 
if (drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, ) == 0) {
sseu.packed.subslice_mask = 0;

drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, );
}

could be used to disable all subslices where supported.

v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu() (Lionel)

v3: Add ability to program this per engine (Chris)

v4: Move most get_sseu() into i915_gem_context.c (Lionel)

v5: Validate sseu configuration against the device's capabilities (Lionel)

v6: Change context powergating settings through MI_SDM on kernel context (Chris)

v7: Synchronize the requests following a powergating setting change using a 
global
dependency (Chris)
Iterate timelines through dev_priv.gt.active_rings (Tvrtko)
Disable RPCS configuration setting for non capable users (Lionel/Tvrtko)

v8: s/union intel_sseu/struct intel_sseu/ (Lionel)
s/dev_priv/i915/ (Tvrtko)
Change uapi class/instance fields to u16 (Tvrtko)
Bump mask fields to 64bits (Lionel)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100899
Signed-off-by: Chris Wilson 
Signed-off-by: Lionel Landwerlin 
c: Dmitry Rogozhkin 
CC: Tvrtko Ursulin 
CC: Zhipeng Gong 
CC: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.h |  13 ++
 drivers/gpu/drm/i915/i915_gem.c |   2 +
 drivers/gpu/drm/i915/i915_gem_context.c | 181 
 drivers/gpu/drm/i915/i915_request.c |  20 +++
 drivers/gpu/drm/i915/intel_lrc.c| 103 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c |   2 +
 drivers/gpu/drm/i915/intel_ringbuffer.h |   4 +
 include/uapi/drm/i915_drm.h |  43 ++
 8 files changed, 333 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f491784b2516..916a301d8c22 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2066,6 +2066,12 @@ struct drm_i915_private {
u32 active_requests;
u32 request_serial;
 
+   /**
+* Global barrier to ensuring ordering of sseu transitions
+* requests.
+*/
+   struct i915_gem_active global_barrier;
+
/**
 * Is the GPU currently considered idle, or busy executing
 * userspace requests? Whilst idle, we allow runtime power
@@ -3228,6 +3234,13 @@ i915_vm_to_ppgtt(struct i915_address_space *vm)
return container_of(vm, struct i915_hw_ppgtt, base);
 }
 
+static inline void i915_gem_set_global_barrier(struct drm_i915_private *i915,
+  struct i915_request *rq)
+{
+   lockdep_assert_held(>drm.struct_mutex);
+   i915_gem_active_set(>gt.global_barrier, rq);
+}
+
 /* i915_gem_fence_reg.c */
 struct drm_i915_fence_reg *
 i915_reserve_fence(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 03874b50ada9..9c2a0d04bd39 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5548,6 +5548,8 @@ int i915_gem_init_early(struct drm_i915_private *dev_priv)
if (!dev_priv->priorities)
goto err_dependencies;
 
+   init_request_active(_priv->gt.global_barrier, NULL);
+
INIT_LIST_HEAD(_priv->gt.timelines);
INIT_LIST_HEAD(_priv->gt.active_rings);
INIT_LIST_HEAD(_priv->gt.closed_vma);
diff --git 

[Intel-gfx] [PATCH v7 5/7] drm/i915/perf: lock powergating configuration to default when active

[Lionel Landwerlin]

If some of the contexts submitting workloads to the GPU have been
configured to shutdown slices/subslices, we might loose the NOA
configurations written in the NOA muxes.

One possible solution to this problem is to reprogram the NOA muxes
when we switch to a new context. We initially tried this in the
workaround batchbuffer but some concerns where raised about the cost
of reprogramming at every context switch. This solution is also not
without consequences from the userspace point of view. Reprogramming
of the muxes can only happen once the powergating configuration has
changed (which happens after context switch). This means for a window
of time during the recording, counters recorded by the OA unit might
be invalid. This requires userspace dealing with OA reports to discard
the invalid values.

Minimizing the reprogramming could be implemented by tracking of the
last programmed configuration somewhere in GGTT and use MI_PREDICATE
to discard some of the programming commands, but the command streamer
would still have to parse all the MI_LRI instructions in the
workaround batchbuffer.

Another solution, which this change implements, is to simply disregard
the user requested configuration for the period of time when i915/perf
is active. There is no known issue with this apart from a performance
penality for some media workloads that benefit from running on a
partially powergated GPU. We already prevent RC6 from affecting the
programming so it doesn't sound completely unreasonable to hold on
powergating for the same reason.

v2: Leave RPCS programming in intel_lrc.c (Lionel)

v3: Update for s/union intel_sseu/struct intel_sseu/ (Lionel)
More to_intel_context() (Tvrtko)
s/dev_priv/i915/ (Tvrtko)

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_drv.h  | 16 
 drivers/gpu/drm/i915/i915_perf.c | 24 +++-
 drivers/gpu/drm/i915/intel_lrc.c | 11 +++
 drivers/gpu/drm/i915/intel_lrc.h |  3 +++
 4 files changed, 45 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 487922f88b76..f491784b2516 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2744,6 +2744,22 @@ int intel_engines_init(struct drm_i915_private 
*dev_priv);
 
 u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);
 
+static inline struct intel_sseu
+intel_engine_prepare_sseu(struct intel_engine_cs *engine,
+ struct intel_sseu sseu)
+{
+   struct drm_i915_private *i915 = engine->i915;
+
+   /*
+* If i915/perf is active, we want a stable powergating configuration
+* on the system. The most natural configuration to take in that case
+* is the default (i.e maximum the hardware can do).
+*/
+   return i915->perf.oa.exclusive_stream ?
+   intel_sseu_from_device_sseu(_INFO(i915)->sseu) :
+   sseu;
+}
+
 /* intel_hotplug.c */
 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
   u32 pin_mask, u32 long_mask);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index a5d98bda5c2e..4750a6436737 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1574,7 +1574,8 @@ static void hsw_disable_metric_set(struct 
drm_i915_private *dev_priv)
  */
 static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx,
   u32 *reg_state,
-  const struct i915_oa_config 
*oa_config)
+  const struct i915_oa_config 
*oa_config,
+  struct intel_sseu sseu)
 {
struct drm_i915_private *dev_priv = ctx->i915;
u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset;
@@ -1620,6 +1621,9 @@ static void gen8_update_reg_state_unlocked(struct 
i915_gem_context *ctx,
 
CTX_REG(reg_state, state_offset, flex_regs[i], value);
}
+
+   CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
+   gen8_make_rpcs(_INFO(dev_priv)->sseu, sseu));
 }
 
 /*
@@ -1751,6 +1755,8 @@ static int gen8_configure_all_contexts(struct 
drm_i915_private *dev_priv,
   const struct i915_oa_config *oa_config)
 {
struct intel_engine_cs *engine = dev_priv->engine[RCS];
+   struct intel_sseu default_sseu =
+   intel_sseu_from_device_sseu(_INFO(dev_priv)->sseu);
struct i915_gem_context *ctx;
int ret;
unsigned int wait_flags = I915_WAIT_LOCKED;
@@ -1795,7 +1801,8 @@ static int gen8_configure_all_contexts(struct 
drm_i915_private *dev_priv,
ce->state->obj->mm.dirty = true;
regs += LRC_STATE_PN * PAGE_SIZE / sizeof(*regs);
 
-   gen8_update_reg_state_unlocked(ctx, regs, 

[Intel-gfx] [PATCH v7 1/7] drm/i915: Program RPCS for Broadwell

[Lionel Landwerlin]

From: Chris Wilson 

Currently we only configure the power gating for Skylake and above, but
the configuration should equally apply to Broadwell and Braswell. Even
though, there is not as much variation as for later generations, we want
to expose control over the configuration to userspace and may want to
opt out of the "always-enabled" setting.

Signed-off-by: Chris Wilson 
Signed-off-by: Lionel Landwerlin 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_lrc.c | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 857ab04452f0..c2500c209c63 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2486,13 +2486,6 @@ make_rpcs(struct drm_i915_private *dev_priv)
 {
u32 rpcs = 0;
 
-   /*
-* No explicit RPCS request is needed to ensure full
-* slice/subslice/EU enablement prior to Gen9.
-   */
-   if (INTEL_GEN(dev_priv) < 9)
-   return 0;
-
/*
 * Starting in Gen9, render power gating can leave
 * slice/subslice/EU in a partially enabled state. We
-- 
2.17.0

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[Intel-gfx] [PATCH v7 7/7] drm/i915: add a sysfs entry to let users set sseu configs

[Lionel Landwerlin]

There are concerns about denial of service around the per context sseu
configuration capability. In a previous commit introducing the
capability we allowed it only for capable users. This changes adds a
new debugfs entry to let any user configure its own context
powergating setup.

v2: Rename sysfs entry (Tvrtko)
Lock interruptible the device in sysfs (Tvrtko)
Fix dropped error code in getting dynamic sseu value (Tvrtko)
s/dev_priv/i915/ (Tvrtko)

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_drv.h |  6 
 drivers/gpu/drm/i915/i915_gem_context.c | 47 -
 drivers/gpu/drm/i915/i915_sysfs.c   | 40 +
 3 files changed, 92 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 916a301d8c22..3db75c56a9f7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1842,6 +1842,8 @@ struct drm_i915_private {
struct ida hw_ida;
 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
+
+   bool dynamic_sseu;
} contexts;
 
u32 fdi_rx_config;
@@ -3275,6 +3277,10 @@ i915_gem_context_lookup(struct drm_i915_file_private 
*file_priv, u32 id)
return ctx;
 }
 
+int i915_gem_contexts_set_dynamic_sseu_locked(struct drm_i915_private *i915,
+ bool allowed);
+bool i915_gem_contexts_get_dynamic_sseu(struct drm_i915_private *i915);
+
 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
 struct drm_file *file);
 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 30736efe0fcd..afb7db95aa3b 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -983,7 +983,8 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, 
void *data,
break;
}
 
-   if (!capable(CAP_SYS_ADMIN)) {
+   if (!i915->contexts.dynamic_sseu &&
+   !capable(CAP_SYS_ADMIN)) {
ret = -EPERM;
break;
}
@@ -1065,6 +1066,50 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device 
*dev,
return ret;
 }
 
+int i915_gem_contexts_set_dynamic_sseu_locked(struct drm_i915_private *i915,
+ bool allowed)
+{
+   struct intel_engine_cs *engine = i915->engine[RCS];
+   int ret = 0;
+
+   lockdep_assert_held(>drm.struct_mutex);
+
+   if (!engine->emit_rpcs_config)
+   return -ENODEV;
+
+   /*
+* When we allow each context to configure its powergating
+* configuration, there is no need to put the configurations back to
+* the default, it should already be the case.
+*/
+   if (!allowed) {
+   struct intel_sseu default_sseu =
+   intel_sseu_from_device_sseu(_INFO(i915)->sseu);
+   struct i915_gem_context *ctx;
+
+   list_for_each_entry(ctx, >contexts.list, link) {
+   ret = i915_gem_context_reconfigure_sseu(ctx, engine,
+   default_sseu);
+   if (ret)
+   break;
+   }
+   }
+
+   i915->contexts.dynamic_sseu = allowed;
+
+   return ret;
+}
+
+bool i915_gem_contexts_get_dynamic_sseu(struct drm_i915_private *i915)
+{
+   struct intel_engine_cs *engine = i915->engine[RCS];
+
+   if (!engine->emit_rpcs_config)
+   return false;
+
+   return i915->contexts.dynamic_sseu;
+}
+
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 #include "selftests/mock_context.c"
 #include "selftests/i915_gem_context.c"
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c
index e5e6f6bb2b05..c323cab59ec7 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -483,6 +483,44 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct 
device_attribute *attr
return snprintf(buf, PAGE_SIZE, "%d\n", val);
 }
 
+static ssize_t allow_dynamic_sseu_show(struct device *kdev,
+  struct device_attribute *attr,
+  char *buf)
+{
+   struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
+   bool value = i915_gem_contexts_get_dynamic_sseu(i915);
+
+   return snprintf(buf, PAGE_SIZE, "%d\n", value);
+}
+
+static ssize_t allow_dynamic_sseu_store(struct device *kdev,
+   struct device_attribute *attr,
+   

[Intel-gfx] [PATCH v7 2/7] drm/i915: Record the sseu configuration per-context & engine

[Lionel Landwerlin]

From: Chris Wilson 

We want to expose the ability to reconfigure the slices, subslice and
eu per context and per engine. To facilitate that, store the current
configuration on the context for each engine, which is initially set
to the device default upon creation.

v2: record sseu configuration per context & engine (Chris)

v3: introduce the i915_gem_context_sseu to store powergating
programming, sseu_dev_info has grown quite a bit (Lionel)

v4: rename i915_gem_sseu into intel_sseu (Chris)
use to_intel_context() (Chris)

v5: More to_intel_context() (Tvrtko)
Switch intel_sseu from union to struct (Tvrtko)
Move context default sseu in existing loop (Chris)

Signed-off-by: Chris Wilson 
Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_gem_context.c |  2 ++
 drivers/gpu/drm/i915/i915_gem_context.h | 17 +
 drivers/gpu/drm/i915/i915_request.h | 10 ++
 drivers/gpu/drm/i915/intel_lrc.c| 22 +++---
 4 files changed, 40 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index b69b18ef8120..c5ad468dae56 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -282,6 +282,8 @@ __create_hw_context(struct drm_i915_private *dev_priv,
struct intel_context *ce = >__engine[n];
 
ce->gem_context = ctx;
+   /* Use the whole device by default */
+   ce->sseu = 
intel_sseu_from_device_sseu(_INFO(dev_priv)->sseu);
}
 
INIT_RADIX_TREE(>handles_vma, GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h 
b/drivers/gpu/drm/i915/i915_gem_context.h
index c3262b4dd2ee..3389b5249342 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -30,6 +30,7 @@
 #include 
 
 #include "i915_gem.h"
+#include "intel_device_info.h"
 
 struct pid;
 
@@ -157,6 +158,9 @@ struct i915_gem_context {
int pin_count;
 
const struct intel_context_ops *ops;
+
+   /** sseu: Control eu/slice partitioning */
+   struct intel_sseu sseu;
} __engine[I915_NUM_ENGINES];
 
/** ring_size: size for allocating the per-engine ring buffer */
@@ -335,4 +339,17 @@ static inline void i915_gem_context_put(struct 
i915_gem_context *ctx)
kref_put(>ref, i915_gem_context_release);
 }
 
+static inline struct intel_sseu
+intel_sseu_from_device_sseu(const struct sseu_dev_info *sseu)
+{
+   struct intel_sseu value = {
+   .slice_mask = sseu->slice_mask,
+   .subslice_mask = sseu->subslice_mask[0],
+   .min_eus_per_subslice = sseu->max_eus_per_subslice,
+   .max_eus_per_subslice = sseu->max_eus_per_subslice,
+   };
+
+   return value;
+}
+
 #endif /* !__I915_GEM_CONTEXT_H__ */
diff --git a/drivers/gpu/drm/i915/i915_request.h 
b/drivers/gpu/drm/i915/i915_request.h
index 17a9fa03..82c5dd153bfd 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -39,6 +39,16 @@ struct drm_i915_gem_object;
 struct i915_request;
 struct i915_timeline;
 
+/*
+ * Powergating configuration for a particular (context,engine).
+ */
+struct intel_sseu {
+   u8 slice_mask;
+   u8 subslice_mask;
+   u8 min_eus_per_subslice;
+   u8 max_eus_per_subslice;
+};
+
 struct intel_wait {
struct rb_node node;
struct task_struct *tsk;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c2500c209c63..a8e139f7c337 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2481,8 +2481,8 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine)
return logical_ring_init(engine);
 }
 
-static u32
-make_rpcs(struct drm_i915_private *dev_priv)
+static u32 make_rpcs(const struct sseu_dev_info *sseu,
+struct intel_sseu ctx_sseu)
 {
u32 rpcs = 0;
 
@@ -2492,24 +2492,23 @@ make_rpcs(struct drm_i915_private *dev_priv)
 * must make an explicit request through RPCS for full
 * enablement.
*/
-   if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
+   if (sseu->has_slice_pg) {
rpcs |= GEN8_RPCS_S_CNT_ENABLE;
-   rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
-   GEN8_RPCS_S_CNT_SHIFT;
+   rpcs |= hweight8(ctx_sseu.slice_mask) << GEN8_RPCS_S_CNT_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
 
-   if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) {
+   if (sseu->has_subslice_pg) {
rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
-   rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]) <<
+   rpcs |= hweight8(ctx_sseu.subslice_mask) <<

[Intel-gfx] [PATCH v7 0/7] drm/i915: per context slice/subslice powergating

[Lionel Landwerlin]

Hi all,

This iteration addresses the last round of review. The last remaining
open is on how to deal contexts setting powergating configurations
while the sysfs entry disallow the setting. Tvrtko proposed to just
silently ignore it and just set it when the sysfs entry allow it. The
currently implementation return EPERM when not allowed.

Cheers,

Chris Wilson (3):
  drm/i915: Program RPCS for Broadwell
  drm/i915: Record the sseu configuration per-context & engine
  drm/i915: Expose RPCS (SSEU) configuration to userspace

Lionel Landwerlin (4):
  drm/i915/perf: simplify configure all context function
  drm/i915/perf: reuse intel_lrc ctx regs macro
  drm/i915/perf: lock powergating configuration to default when active
  drm/i915: add a sysfs entry to let users set sseu configs

 drivers/gpu/drm/i915/i915_drv.h |  35 
 drivers/gpu/drm/i915/i915_gem.c |   2 +
 drivers/gpu/drm/i915/i915_gem_context.c | 228 
 drivers/gpu/drm/i915/i915_gem_context.h |  17 ++
 drivers/gpu/drm/i915/i915_perf.c|  69 +++
 drivers/gpu/drm/i915/i915_request.c |  20 +++
 drivers/gpu/drm/i915/i915_request.h |  10 ++
 drivers/gpu/drm/i915/i915_sysfs.c   |  40 +
 drivers/gpu/drm/i915/intel_lrc.c| 117 +++-
 drivers/gpu/drm/i915/intel_lrc.h|   3 +
 drivers/gpu/drm/i915/intel_ringbuffer.c |   2 +
 drivers/gpu/drm/i915/intel_ringbuffer.h |   4 +
 include/uapi/drm/i915_drm.h |  43 +
 13 files changed, 516 insertions(+), 74 deletions(-)

--
2.17.0
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[Intel-gfx] [PATCH v7 4/7] drm/i915/perf: reuse intel_lrc ctx regs macro

[Lionel Landwerlin]

Abstract the context image access a bit.

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_perf.c | 34 +++-
 1 file changed, 16 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 805dfc732bba..a5d98bda5c2e 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -210,6 +210,7 @@
 #include "i915_oa_cflgt3.h"
 #include "i915_oa_cnl.h"
 #include "i915_oa_icl.h"
+#include "intel_lrc_reg.h"
 
 /* HW requires this to be a power of two, between 128k and 16M, though driver
  * is currently generally designed assuming the largest 16M size is used such
@@ -1579,27 +1580,25 @@ static void gen8_update_reg_state_unlocked(struct 
i915_gem_context *ctx,
u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset;
u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset;
/* The MMIO offsets for Flex EU registers aren't contiguous */
-   u32 flex_mmio[] = {
-   i915_mmio_reg_offset(EU_PERF_CNTL0),
-   i915_mmio_reg_offset(EU_PERF_CNTL1),
-   i915_mmio_reg_offset(EU_PERF_CNTL2),
-   i915_mmio_reg_offset(EU_PERF_CNTL3),
-   i915_mmio_reg_offset(EU_PERF_CNTL4),
-   i915_mmio_reg_offset(EU_PERF_CNTL5),
-   i915_mmio_reg_offset(EU_PERF_CNTL6),
+   i915_reg_t flex_regs[] = {
+   EU_PERF_CNTL0,
+   EU_PERF_CNTL1,
+   EU_PERF_CNTL2,
+   EU_PERF_CNTL3,
+   EU_PERF_CNTL4,
+   EU_PERF_CNTL5,
+   EU_PERF_CNTL6,
};
int i;
 
-   reg_state[ctx_oactxctrl] = i915_mmio_reg_offset(GEN8_OACTXCONTROL);
-   reg_state[ctx_oactxctrl+1] = (dev_priv->perf.oa.period_exponent <<
- GEN8_OA_TIMER_PERIOD_SHIFT) |
-(dev_priv->perf.oa.periodic ?
- GEN8_OA_TIMER_ENABLE : 0) |
-GEN8_OA_COUNTER_RESUME;
+   CTX_REG(reg_state, ctx_oactxctrl, GEN8_OACTXCONTROL,
+   (dev_priv->perf.oa.period_exponent << 
GEN8_OA_TIMER_PERIOD_SHIFT) |
+   (dev_priv->perf.oa.periodic ? GEN8_OA_TIMER_ENABLE : 0) |
+   GEN8_OA_COUNTER_RESUME);
 
-   for (i = 0; i < ARRAY_SIZE(flex_mmio); i++) {
+   for (i = 0; i < ARRAY_SIZE(flex_regs); i++) {
u32 state_offset = ctx_flexeu0 + i * 2;
-   u32 mmio = flex_mmio[i];
+   u32 mmio = i915_mmio_reg_offset(flex_regs[i]);
 
/*
 * This arbitrary default will select the 'EU FPU0 Pipeline
@@ -1619,8 +1618,7 @@ static void gen8_update_reg_state_unlocked(struct 
i915_gem_context *ctx,
}
}
 
-   reg_state[state_offset] = mmio;
-   reg_state[state_offset+1] = value;
+   CTX_REG(reg_state, state_offset, flex_regs[i], value);
}
 }
 
-- 
2.17.0

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[Intel-gfx] [PATCH v7 3/7] drm/i915/perf: simplify configure all context function

[Lionel Landwerlin]

We don't need any special treatment on error so just return as soon as
possible.

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_perf.c | 11 ---
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 4f0eb84b3c00..805dfc732bba 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1762,7 +1762,7 @@ static int gen8_configure_all_contexts(struct 
drm_i915_private *dev_priv,
/* Switch away from any user context. */
ret = gen8_switch_to_updated_kernel_context(dev_priv, oa_config);
if (ret)
-   goto out;
+   return ret;
 
/*
 * The OA register config is setup through the context image. This image
@@ -1779,7 +1779,7 @@ static int gen8_configure_all_contexts(struct 
drm_i915_private *dev_priv,
 */
ret = i915_gem_wait_for_idle(dev_priv, wait_flags);
if (ret)
-   goto out;
+   return ret;
 
/* Update all contexts now that we've stalled the submission. */
list_for_each_entry(ctx, _priv->contexts.list, link) {
@@ -1791,10 +1791,8 @@ static int gen8_configure_all_contexts(struct 
drm_i915_private *dev_priv,
continue;
 
regs = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
-   if (IS_ERR(regs)) {
-   ret = PTR_ERR(regs);
-   goto out;
-   }
+   if (IS_ERR(regs))
+   return PTR_ERR(regs);
 
ce->state->obj->mm.dirty = true;
regs += LRC_STATE_PN * PAGE_SIZE / sizeof(*regs);
@@ -1804,7 +1802,6 @@ static int gen8_configure_all_contexts(struct 
drm_i915_private *dev_priv,
i915_gem_object_unpin_map(ce->state->obj);
}
 
- out:
return ret;
 }
 
-- 
2.17.0

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Re: [Intel-gfx] [PATCH] drm/i915: Look for an active kernel context before switching

[Chris Wilson]

Quoting Mika Kuoppala (2018-05-24 15:40:47)
> Chris Wilson  writes:
> 
> > We were not very carefully checking to see if an older request on the
> > engine was an earlier switch-to-kernel-context before deciding to emit a
> > new switch. The end result would be that we could get into a permanent
> > loop of trying to emit a new request to perform the switch simply to
> > flush the existing switch.
> >
> > What we need is a means of tracking the completion of each timeline
> > versus the kernel context, that is to detect if a more recent request
> > has been submitted that would result in a switch away from the kernel
> > context. To realise this, we need only to look in our syncmap on the
> > kernel context and check that we have synchronized against all active
> > rings.
> >
> > v2: Since all ringbuffer clients currently share the same timeline, we do
> > have to use the gem_context to distinguish clients.
> >
> > As a bonus, include all the tracing used to debug the death inside
> > suspend.
> >
> > v3: Test, test, test. Construct a selftest to exercise and assert the
> > expected behaviour that multiple switch-to-contexts do not emit
> > redundant requests.
> >
> > Reported-by: Mika Kuoppala 
> > Fixes: a89d1f921c15 ("drm/i915: Split i915_gem_timeline into individual 
> > timelines")
> > Signed-off-by: Chris Wilson 
> > Cc: Mika Kuoppala 
> > ---
> >  drivers/gpu/drm/i915/i915_gem.c   |   7 +
> >  drivers/gpu/drm/i915/i915_gem.h   |   3 +
> >  drivers/gpu/drm/i915/i915_gem_context.c   |  86 +--
> >  drivers/gpu/drm/i915/i915_request.c   |   5 +-
> >  .../gpu/drm/i915/selftests/i915_gem_context.c | 144 ++
> >  .../drm/i915/selftests/i915_mock_selftests.h  |   1 +
> >  6 files changed, 231 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c 
> > b/drivers/gpu/drm/i915/i915_gem.c
> > index 03874b50ada9..05f44ca35a06 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -3703,6 +3703,9 @@ static int wait_for_engines(struct drm_i915_private 
> > *i915)
> >  
> >  int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int 
> > flags)
> >  {
> > + GEM_TRACE("flags=%x (%s)\n",
> > +   flags, flags & I915_WAIT_LOCKED ? "locked" : "unlocked");
> > +
> >   /* If the device is asleep, we have no requests outstanding */
> >   if (!READ_ONCE(i915->gt.awake))
> >   return 0;
> > @@ -3719,6 +3722,7 @@ int i915_gem_wait_for_idle(struct drm_i915_private 
> > *i915, unsigned int flags)
> >   return err;
> >   }
> >   i915_retire_requests(i915);
> > + GEM_BUG_ON(i915->gt.active_requests);
> >  
> >   return wait_for_engines(i915);
> >   } else {
> > @@ -4901,6 +4905,7 @@ static void assert_kernel_context_is_current(struct 
> > drm_i915_private *i915)
> >   struct intel_engine_cs *engine;
> >   enum intel_engine_id id;
> >  
> > + GEM_BUG_ON(i915->gt.active_requests);
> >   for_each_engine(engine, i915, id) {
> >   
> > GEM_BUG_ON(__i915_gem_active_peek(>timeline.last_request));
> >   GEM_BUG_ON(engine->last_retired_context->gem_context != kctx);
> > @@ -4932,6 +4937,8 @@ int i915_gem_suspend(struct drm_i915_private 
> > *dev_priv)
> >   struct drm_device *dev = _priv->drm;
> >   int ret;
> >  
> > + GEM_TRACE("\n");
> > +
> >   intel_runtime_pm_get(dev_priv);
> >   intel_suspend_gt_powersave(dev_priv);
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_gem.h 
> > b/drivers/gpu/drm/i915/i915_gem.h
> > index 5bf24cfc218c..62ee4e385365 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.h
> > +++ b/drivers/gpu/drm/i915/i915_gem.h
> > @@ -63,9 +63,12 @@ struct drm_i915_private;
> >  #if IS_ENABLED(CONFIG_DRM_I915_TRACE_GEM)
> >  #define GEM_TRACE(...) trace_printk(__VA_ARGS__)
> >  #define GEM_TRACE_DUMP() ftrace_dump(DUMP_ALL)
> > +#define GEM_TRACE_DUMP_ON(expr) \
> > + do { if (expr) ftrace_dump(DUMP_ALL); } while (0)
> >  #else
> >  #define GEM_TRACE(...) do { } while (0)
> >  #define GEM_TRACE_DUMP() do { } while (0)
> > +#define GEM_TRACE_DUMP_ON(expr) BUILD_BUG_ON_INVALID(expr)
> >  #endif
> >  
> >  #define I915_NUM_ENGINES 8
> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
> > b/drivers/gpu/drm/i915/i915_gem_context.c
> > index b69b18ef8120..45393f6e0208 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > @@ -576,30 +576,72 @@ last_request_on_engine(struct i915_timeline *timeline,
> >  {
> >   struct i915_request *rq;
> >  
> > - if (timeline == >timeline)
> > - return NULL;
> > + GEM_BUG_ON(timeline == >timeline);
> >  
> >   rq = i915_gem_active_raw(>last_request,
> >

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/4] drm/mm: Reject over-sized allocation requests early

[Chris Wilson]

Quoting Patchwork (2018-05-21 12:15:36)
> == Series Details ==
> 
> Series: series starting with [v2,1/4] drm/mm: Reject over-sized allocation 
> requests early
> URL   : https://patchwork.freedesktop.org/series/43497/
> State : success
> 
> == Summary ==
> 
> = CI Bug Log - changes from CI_DRM_4211_full -> Patchwork_9063_full =
> 
> == Summary - WARNING ==
> 
>   Minor unknown changes coming with Patchwork_9063_full need to be verified
>   manually.

Selftests (including the new subtests) passed and no impacts observed on
the driver.  I've applied these to the drm-misc-next branch, so
hopefully picking the right one.

Thanks for the review,
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Look for an active kernel context before switching

[Mika Kuoppala]

Chris Wilson  writes:

> We were not very carefully checking to see if an older request on the
> engine was an earlier switch-to-kernel-context before deciding to emit a
> new switch. The end result would be that we could get into a permanent
> loop of trying to emit a new request to perform the switch simply to
> flush the existing switch.
>
> What we need is a means of tracking the completion of each timeline
> versus the kernel context, that is to detect if a more recent request
> has been submitted that would result in a switch away from the kernel
> context. To realise this, we need only to look in our syncmap on the
> kernel context and check that we have synchronized against all active
> rings.
>
> v2: Since all ringbuffer clients currently share the same timeline, we do
> have to use the gem_context to distinguish clients.
>
> As a bonus, include all the tracing used to debug the death inside
> suspend.
>
> v3: Test, test, test. Construct a selftest to exercise and assert the
> expected behaviour that multiple switch-to-contexts do not emit
> redundant requests.
>
> Reported-by: Mika Kuoppala 
> Fixes: a89d1f921c15 ("drm/i915: Split i915_gem_timeline into individual 
> timelines")
> Signed-off-by: Chris Wilson 
> Cc: Mika Kuoppala 
> ---
>  drivers/gpu/drm/i915/i915_gem.c   |   7 +
>  drivers/gpu/drm/i915/i915_gem.h   |   3 +
>  drivers/gpu/drm/i915/i915_gem_context.c   |  86 +--
>  drivers/gpu/drm/i915/i915_request.c   |   5 +-
>  .../gpu/drm/i915/selftests/i915_gem_context.c | 144 ++
>  .../drm/i915/selftests/i915_mock_selftests.h  |   1 +
>  6 files changed, 231 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 03874b50ada9..05f44ca35a06 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3703,6 +3703,9 @@ static int wait_for_engines(struct drm_i915_private 
> *i915)
>  
>  int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags)
>  {
> + GEM_TRACE("flags=%x (%s)\n",
> +   flags, flags & I915_WAIT_LOCKED ? "locked" : "unlocked");
> +
>   /* If the device is asleep, we have no requests outstanding */
>   if (!READ_ONCE(i915->gt.awake))
>   return 0;
> @@ -3719,6 +3722,7 @@ int i915_gem_wait_for_idle(struct drm_i915_private 
> *i915, unsigned int flags)
>   return err;
>   }
>   i915_retire_requests(i915);
> + GEM_BUG_ON(i915->gt.active_requests);
>  
>   return wait_for_engines(i915);
>   } else {
> @@ -4901,6 +4905,7 @@ static void assert_kernel_context_is_current(struct 
> drm_i915_private *i915)
>   struct intel_engine_cs *engine;
>   enum intel_engine_id id;
>  
> + GEM_BUG_ON(i915->gt.active_requests);
>   for_each_engine(engine, i915, id) {
>   
> GEM_BUG_ON(__i915_gem_active_peek(>timeline.last_request));
>   GEM_BUG_ON(engine->last_retired_context->gem_context != kctx);
> @@ -4932,6 +4937,8 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
>   struct drm_device *dev = _priv->drm;
>   int ret;
>  
> + GEM_TRACE("\n");
> +
>   intel_runtime_pm_get(dev_priv);
>   intel_suspend_gt_powersave(dev_priv);
>  
> diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
> index 5bf24cfc218c..62ee4e385365 100644
> --- a/drivers/gpu/drm/i915/i915_gem.h
> +++ b/drivers/gpu/drm/i915/i915_gem.h
> @@ -63,9 +63,12 @@ struct drm_i915_private;
>  #if IS_ENABLED(CONFIG_DRM_I915_TRACE_GEM)
>  #define GEM_TRACE(...) trace_printk(__VA_ARGS__)
>  #define GEM_TRACE_DUMP() ftrace_dump(DUMP_ALL)
> +#define GEM_TRACE_DUMP_ON(expr) \
> + do { if (expr) ftrace_dump(DUMP_ALL); } while (0)
>  #else
>  #define GEM_TRACE(...) do { } while (0)
>  #define GEM_TRACE_DUMP() do { } while (0)
> +#define GEM_TRACE_DUMP_ON(expr) BUILD_BUG_ON_INVALID(expr)
>  #endif
>  
>  #define I915_NUM_ENGINES 8
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
> b/drivers/gpu/drm/i915/i915_gem_context.c
> index b69b18ef8120..45393f6e0208 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -576,30 +576,72 @@ last_request_on_engine(struct i915_timeline *timeline,
>  {
>   struct i915_request *rq;
>  
> - if (timeline == >timeline)
> - return NULL;
> + GEM_BUG_ON(timeline == >timeline);
>  
>   rq = i915_gem_active_raw(>last_request,
>>i915->drm.struct_mutex);
> - if (rq && rq->engine == engine)
> + if (rq && rq->engine == engine) {
> + GEM_TRACE("last request for %s on engine %s: %llx:%d\n",
> +   timeline->name, engine->name,
> +   rq->fence.context, rq->fence.seqno);

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Special case kernel_context switch request

[kbuild test robot]

Hi Mika,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on next-20180517]
[cannot apply to drm-intel/for-linux-next v4.17-rc6 v4.17-rc5 v4.17-rc4 
v4.17-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Prepare-GEM-for-suspend-earlier/20180524-214128
config: i386-randconfig-x071-201820 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All warnings (new ones prefixed by >>):

   In file included from arch/x86/include/asm/bitops.h:16:0,
from include/linux/bitops.h:38,
from include/linux/log2.h:16,
from drivers/gpu//drm/i915/i915_gem_context.c:88:
   drivers/gpu//drm/i915/i915_gem_context.c: In function 
'engine_has_idle_kernel_context':
   drivers/gpu//drm/i915/i915_gem_context.c:608:15: error: 'struct 
i915_request' has no member named 'gem_context'
  if (rq && rq->gem_context != engine->i915->kernel_context)
  ^
   include/linux/compiler.h:58:30: note: in definition of macro '__trace_if'
 if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
 ^~~~
>> drivers/gpu//drm/i915/i915_gem_context.c:608:3: note: in expansion of macro 
>> 'if'
  if (rq && rq->gem_context != engine->i915->kernel_context)
  ^~
   drivers/gpu//drm/i915/i915_gem_context.c:608:15: error: 'struct 
i915_request' has no member named 'gem_context'
  if (rq && rq->gem_context != engine->i915->kernel_context)
  ^
   include/linux/compiler.h:58:42: note: in definition of macro '__trace_if'
 if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
 ^~~~
>> drivers/gpu//drm/i915/i915_gem_context.c:608:3: note: in expansion of macro 
>> 'if'
  if (rq && rq->gem_context != engine->i915->kernel_context)
  ^~
   drivers/gpu//drm/i915/i915_gem_context.c:608:15: error: 'struct 
i915_request' has no member named 'gem_context'
  if (rq && rq->gem_context != engine->i915->kernel_context)
  ^
   include/linux/compiler.h:69:16: note: in definition of macro '__trace_if'
  __r = !!(cond); \
   ^~~~
>> drivers/gpu//drm/i915/i915_gem_context.c:608:3: note: in expansion of macro 
>> 'if'
  if (rq && rq->gem_context != engine->i915->kernel_context)
  ^~

vim +/if +608 drivers/gpu//drm/i915/i915_gem_context.c

   596  
   597  static bool engine_has_idle_kernel_context(struct intel_engine_cs 
*engine)
   598  {
   599  struct list_head * const active_rings = 
>i915->gt.active_rings;
   600  struct intel_ring *ring;
   601  
   602  lockdep_assert_held(>i915->drm.struct_mutex);
   603  
   604  list_for_each_entry(ring, active_rings, active_link) {
   605  struct i915_request *rq =
   606  last_request_on_engine(ring->timeline, engine);
   607  
 > 608  if (rq && rq->gem_context != 
 > engine->i915->kernel_context)
   609  return false;
   610  }
   611  
   612  return intel_engine_has_kernel_context(engine);
   613  }
   614  

---
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Re: [Intel-gfx] [PATCH 2/3] drm/i915: Special case kernel_context switch request

[kbuild test robot]

Hi Mika,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on next-20180517]
[cannot apply to drm-intel/for-linux-next v4.17-rc6 v4.17-rc5 v4.17-rc4 
v4.17-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Prepare-GEM-for-suspend-earlier/20180524-214128
config: x86_64-randconfig-x015-201820 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/gpu//drm/i915/i915_gem_context.c: In function 
'engine_has_idle_kernel_context':
>> drivers/gpu//drm/i915/i915_gem_context.c:608:15: error: 'struct 
>> i915_request' has no member named 'gem_context'
  if (rq && rq->gem_context != engine->i915->kernel_context)
  ^~

vim +608 drivers/gpu//drm/i915/i915_gem_context.c

   596  
   597  static bool engine_has_idle_kernel_context(struct intel_engine_cs 
*engine)
   598  {
   599  struct list_head * const active_rings = 
>i915->gt.active_rings;
   600  struct intel_ring *ring;
   601  
   602  lockdep_assert_held(>i915->drm.struct_mutex);
   603  
   604  list_for_each_entry(ring, active_rings, active_link) {
   605  struct i915_request *rq =
   606  last_request_on_engine(ring->timeline, engine);
   607  
 > 608  if (rq && rq->gem_context != 
 > engine->i915->kernel_context)
   609  return false;
   610  }
   611  
   612  return intel_engine_has_kernel_context(engine);
   613  }
   614  

---
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Allow DBLSCAN user modes with eDP/LVDS/DSI

[Patchwork]

== Series Details ==

Series: drm/i915: Allow DBLSCAN user modes with eDP/LVDS/DSI
URL   : https://patchwork.freedesktop.org/series/43698/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4230 -> Patchwork_9104 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43698/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9104 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
  fi-skl-6700k2:  PASS -> FAIL (fdo#103191, fdo#104724)


 Possible fixes 

igt@drv_module_reload@basic-reload-inject:
  fi-ilk-650: DMESG-WARN -> PASS

igt@kms_chamelium@dp-crc-fast:
  fi-kbl-7500u:   DMESG-FAIL (fdo#103841) -> PASS

igt@kms_pipe_crc_basic@read-crc-pipe-a:
  fi-skl-6700k2:  FAIL (fdo#103191, fdo#104724) -> PASS


  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724


== Participating hosts (44 -> 39) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4230 -> Patchwork_9104

  CI_DRM_4230: 097c5e2d7cf300d1f9855a550bfdd5150410ffc4 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4498: f9ecb79ad8b02278cfdb5b82495df47061c04f8f @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9104: 82368323f7e2a1fbe3822bd2da4e1860f8ca418d @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

82368323f7e2 drm/i915: Allow DBLSCAN user modes with eDP/LVDS/DSI

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9104/issues.html
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Re: [Intel-gfx] [PATCH 4/6] drm/i915/psr: Avoid unnecessary DPCD read of DP_PSR_CAPS

[Jani Nikula]

On Sun, 20 May 2018, Tarun Vyas  wrote:
> On Fri, May 11, 2018 at 12:51:43PM -0700, Dhinakaran Pandiyan wrote:
>> intel_dp->psr_dpcd already has the required values.
>> 
>> Cc: Jose Roberto de Souza 
>> Signed-off-by: Dhinakaran Pandiyan 
>> ---
>>  drivers/gpu/drm/i915/intel_psr.c | 11 +--
>>  1 file changed, 1 insertion(+), 10 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
>> b/drivers/gpu/drm/i915/intel_psr.c
>> index 61ade81576f5..381dbdbf30f4 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -201,15 +201,6 @@ void intel_psr_irq_handler(struct drm_i915_private 
>> *dev_priv, u32 psr_iir)
>>  }
>>  }
>>  
>> -static bool intel_dp_get_y_coord_required(struct intel_dp *intel_dp)
>> -{
>> -uint8_t psr_caps = 0;
>> -
>> -if (drm_dp_dpcd_readb(_dp->aux, DP_PSR_CAPS, _caps) != 1)
>> -return false;
>> -return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
>> -}
>> -
>>  static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
>>  {
>>  uint8_t dprx = 0;
>> @@ -275,7 +266,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>>   * GTC first.
>>   */
>>  dev_priv->psr.sink_psr2_support =
>> -intel_dp_get_y_coord_required(intel_dp);
>> +intel_dp->psr_dpcd[1] & 
>> DP_PSR2_SU_Y_COORDINATE_REQUIRED;
>>  DRM_DEBUG_KMS("PSR2 %ssupported\n",
>>dev_priv->psr.sink_psr2_support ? "" : "not ");
> The drm_dp_dpcd_read itself reads the first 2 PSR DPCD bytes which is what is 
> needed. Also, no other callers of intel_dp_get_y_coord_required exist. So,
>
> Reviewed-by: Tarun Vyas 

The rest of the patches in the series pushed to dinq as well, thanks for
the patches and review.

BR,
Jani.

>>  
>> -- 
>> 2.14.1
>> 
>> ___
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>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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-- 
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Re: [Intel-gfx] [PATCH 3/6] drm/psr: Fix missed entry in PSR setup time table.

[Jani Nikula]

On Fri, 11 May 2018, Dhinakaran Pandiyan  wrote:
> Entry corresponding to 220 us setup time was missing. I am not aware of
> any specific bug this fixes, but this could potentially result in enabling
> PSR on a panel with a higher setup time requirement than supported by the
> hardware.
>
> I verified the value is present in eDP spec versions 1.3, 1.4 and 1.4a.
>
> Fixes: 6608804b3d7f ("drm/dp: Add drm_dp_psr_setup_time()")
> Cc: sta...@vger.kernel.org
> Cc: Ville Syrjälä 
> Cc: Jose Roberto de Souza 
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Dhinakaran Pandiyan 

Pushed to drm-misc-fixes with reviews picked up from the earlier posting
[1]. Doesn't look like the function is used by anyone other than i915,
so I didn't bother with further acks from non-Intel devs. Should be a
straightforward fix anyway.

BR,
Jani.


[1] 
20180511005419.11199-1-dhinakaran.pandiyan@intel.com">http://mid.mail-archive.com/20180511005419.11199-1-dhinakaran.pandiyan@intel.com

> ---
>  drivers/gpu/drm/drm_dp_helper.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 36c7609a4bd5..a7ba602a43a8 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1159,6 +1159,7 @@ int drm_dp_psr_setup_time(const u8 
> psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
>   static const u16 psr_setup_time_us[] = {
>   PSR_SETUP_TIME(330),
>   PSR_SETUP_TIME(275),
> + PSR_SETUP_TIME(220),
>   PSR_SETUP_TIME(165),
>   PSR_SETUP_TIME(110),
>   PSR_SETUP_TIME(55),

-- 
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Add ChromeOS EC CEC Support (rev7)

[Patchwork]

== Series Details ==

Series: Add ChromeOS EC CEC Support (rev7)
URL   : https://patchwork.freedesktop.org/series/43162/
State : failure

== Summary ==

Applying: media: cec-notifier: Get notifier by device and connector name
Applying: drm/i915: hdmi: add CEC notifier to intel_hdmi
Applying: mfd: cros-ec: Increase maximum mkbp event size
Applying: mfd: cros-ec: Introduce CEC commands and events definitions.
Applying: mfd: cros_ec_dev: Add CEC sub-device registration
error: sha1 information is lacking or useless (drivers/mfd/cros_ec_dev.c).
error: could not build fake ancestor
Patch failed at 0005 mfd: cros_ec_dev: Add CEC sub-device registration
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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Re: [Intel-gfx] [PATCH v4] drm/i915: Flush the ring stop bit after clearing RING_HEAD in reset

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-05-24 14:34:41)
> 
> On 19/05/2018 10:04, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-05-18 15:42:00)
> >>
> >> On 18/05/2018 15:13, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2018-05-18 13:36:52)
> 
>  On 18/05/2018 13:28, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-05-18 12:50:41)
> >>
> >> On 18/05/2018 12:10, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2018-05-18 12:05:17)
> 
>  On 18/05/2018 11:09, Chris Wilson wrote:
> > Inside the live_hangcheck (reset) selftests, we occasionally see
> > failures like
> >
> > <7>[  239.094840] i915_gem_set_wedged rcs0
> > <7>[  239.094843] i915_gem_set_wedged current seqno 19a98, 
> > last 19a9a, hangcheck 0 [5158 ms]
> > <7>[  239.094846] i915_gem_set_wedged Reset count: 6239 
> > (global 1)
> > <7>[  239.094848] i915_gem_set_wedged Requests:
> > <7>[  239.095052] i915_gem_set_wedged first  19a99 
> > [e8c:5f] prio=1024 @ 5159ms: (null)
> > <7>[  239.095056] i915_gem_set_wedged last   19a9a 
> > [e81:1a] prio=139 @ 5159ms: igt/rcs0[5977]/1
> > <7>[  239.095059] i915_gem_set_wedged active 19a99 
> > [e8c:5f] prio=1024 @ 5159ms: (null)
> > <7>[  239.095062] i915_gem_set_wedged [head 0220, 
> > postfix 0280, tail 02a8, batch 0x_]
> > <7>[  239.100050] i915_gem_set_wedged ring->start:  
> > 0x00283000
> > <7>[  239.100053] i915_gem_set_wedged ring->head:   
> > 0x01f8
> > <7>[  239.100055] i915_gem_set_wedged ring->tail:   
> > 0x02a8
> > <7>[  239.100057] i915_gem_set_wedged ring->emit:   
> > 0x02a8
> > <7>[  239.100059] i915_gem_set_wedged ring->space:  
> > 0x0f10
> > <7>[  239.100085] i915_gem_set_wedged RING_START: 0x00283000
> > <7>[  239.100088] i915_gem_set_wedged RING_HEAD:  0x0260
> > <7>[  239.100091] i915_gem_set_wedged RING_TAIL:  0x02a8
> > <7>[  239.100094] i915_gem_set_wedged RING_CTL:   0x0001
> > <7>[  239.100097] i915_gem_set_wedged RING_MODE:  
> > 0x0300 [idle]
> > <7>[  239.100100] i915_gem_set_wedged RING_IMR: fefe
> > <7>[  239.100104] i915_gem_set_wedged ACTHD:  
> > 0x_609c
> > <7>[  239.100108] i915_gem_set_wedged BBADDR: 
> > 0x_609d
> > <7>[  239.100111] i915_gem_set_wedged DMA_FADDR: 
> > 0x_00283260
> > <7>[  239.100114] i915_gem_set_wedged IPEIR: 0x
> > <7>[  239.100117] i915_gem_set_wedged IPEHR: 0x0280
> > <7>[  239.100120] i915_gem_set_wedged Execlist status: 
> > 0x00044052 0002
> > <7>[  239.100124] i915_gem_set_wedged Execlist CSB read 5 
> > [5 cached], write 5 [5 from hws], interrupt posted? no, tasklet 
> > queued? no (enabled)
> > <7>[  239.100128] i915_gem_set_wedged ELSP[0] 
> > count=1, ring->start=00283000, rq: 19a99 [e8c:5f] prio=1024 @ 
> > 5164ms: (null)
> > <7>[  239.100132] i915_gem_set_wedged ELSP[1] 
> > count=1, ring->start=00257000, rq: 19a9a [e81:1a] prio=139 @ 
> > 5164ms: igt/rcs0[5977]/1
> > <7>[  239.100135] i915_gem_set_wedged HW active? 0x5
> > <7>[  239.100250] i915_gem_set_wedged E 19a99 
> > [e8c:5f] prio=1024 @ 5164ms: (null)
> > <7>[  239.100338] i915_gem_set_wedged E 19a9a 
> > [e81:1a] prio=139 @ 5164ms: igt/rcs0[5977]/1
> > <7>[  239.100340] i915_gem_set_wedged Queue 
> > priority: 139
> > <7>[  239.100343] i915_gem_set_wedged Q 0 [e98:19] 
> > prio=132 @ 5164ms: igt/rcs0[5977]/8
> > <7>[  239.100346] i915_gem_set_wedged Q 0 [e84:19] 
> > prio=121 @ 5165ms: igt/rcs0[5977]/2
> > <7>[  239.100349] i915_gem_set_wedged Q 0 [e87:19] 
> > prio=82 @ 5165ms: igt/rcs0[5977]/3
> > <7>[  239.100352] i915_gem_set_wedged Q 0 [e84:1a] 
> > prio=44 @ 5164ms: igt/rcs0[5977]/2
> > <7>[  239.100356] i915_gem_set_wedged Q 0 [e8b:19] 
> > prio=20 @ 5165ms: igt/rcs0[5977]/4
> > <7>[  239.100362] i915_gem_set_wedged drv_selftest [5894] 
> > waiting for 19a99
> >
> > where the GPU saw an arbitration point and idles; AND HAS NOT BEEN 
> > RESET!
> > The RING_MODE indicates that is 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Look for an active kernel context before switching (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Look for an active kernel context before switching (rev2)
URL   : https://patchwork.freedesktop.org/series/43609/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4228_full -> Patchwork_9102_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9102_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9102_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43609/revisions/2/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9102_full:

  === IGT changes ===

 Warnings 

igt@gem_exec_schedule@deep-blt:
  shard-kbl:  PASS -> SKIP +1

igt@gem_mocs_settings@mocs-rc6-blt:
  shard-kbl:  SKIP -> PASS


== Known issues ==

  Here are the changes found in Patchwork_9102_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_ctx_isolation@bcs0-s3:
  shard-kbl:  PASS -> INCOMPLETE (fdo#103665) +1

igt@kms_flip@modeset-vs-vblank-race-interruptible:
  shard-hsw:  PASS -> FAIL (fdo#103060)

igt@kms_flip_tiling@flip-to-y-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724)

igt@kms_setmode@basic:
  shard-kbl:  PASS -> FAIL (fdo#99912)


 Possible fixes 

igt@kms_flip@dpms-vs-vblank-race:
  shard-apl:  FAIL (fdo#103060) -> PASS

igt@kms_flip_tiling@flip-to-x-tiled:
  shard-glk:  FAIL (fdo#104724, fdo#103822) -> PASS

igt@kms_flip_tiling@flip-y-tiled:
  shard-glk:  FAIL (fdo#104724) -> PASS


  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4228 -> Patchwork_9102

  CI_DRM_4228: 8e3e5c1cc5de96c61ff995282ab952ff5d47a211 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4498: f9ecb79ad8b02278cfdb5b82495df47061c04f8f @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9102: 2fa6e902cd0d0a8680a4768a909d5808e23e7017 @ 
git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9102/shards.html
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Re: [Intel-gfx] [PATCH v4] drm/i915: Flush the ring stop bit after clearing RING_HEAD in reset

[Tvrtko Ursulin]

On 19/05/2018 10:04, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-05-18 15:42:00)


On 18/05/2018 15:13, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-05-18 13:36:52)


On 18/05/2018 13:28, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-05-18 12:50:41)


On 18/05/2018 12:10, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-05-18 12:05:17)


On 18/05/2018 11:09, Chris Wilson wrote:

Inside the live_hangcheck (reset) selftests, we occasionally see
failures like

<7>[  239.094840] i915_gem_set_wedged rcs0
<7>[  239.094843] i915_gem_set_wedged current seqno 19a98, last 19a9a, 
hangcheck 0 [5158 ms]
<7>[  239.094846] i915_gem_set_wedged Reset count: 6239 (global 1)
<7>[  239.094848] i915_gem_set_wedged Requests:
<7>[  239.095052] i915_gem_set_wedged first  19a99 [e8c:5f] 
prio=1024 @ 5159ms: (null)
<7>[  239.095056] i915_gem_set_wedged last   19a9a [e81:1a] 
prio=139 @ 5159ms: igt/rcs0[5977]/1
<7>[  239.095059] i915_gem_set_wedged active 19a99 [e8c:5f] 
prio=1024 @ 5159ms: (null)
<7>[  239.095062] i915_gem_set_wedged [head 0220, postfix 0280, 
tail 02a8, batch 0x_]
<7>[  239.100050] i915_gem_set_wedged ring->start:  0x00283000
<7>[  239.100053] i915_gem_set_wedged ring->head:   0x01f8
<7>[  239.100055] i915_gem_set_wedged ring->tail:   0x02a8
<7>[  239.100057] i915_gem_set_wedged ring->emit:   0x02a8
<7>[  239.100059] i915_gem_set_wedged ring->space:  0x0f10
<7>[  239.100085] i915_gem_set_wedged RING_START: 0x00283000
<7>[  239.100088] i915_gem_set_wedged RING_HEAD:  0x0260
<7>[  239.100091] i915_gem_set_wedged RING_TAIL:  0x02a8
<7>[  239.100094] i915_gem_set_wedged RING_CTL:   0x0001
<7>[  239.100097] i915_gem_set_wedged RING_MODE:  0x0300 [idle]
<7>[  239.100100] i915_gem_set_wedged RING_IMR: fefe
<7>[  239.100104] i915_gem_set_wedged ACTHD:  0x_609c
<7>[  239.100108] i915_gem_set_wedged BBADDR: 0x_609d
<7>[  239.100111] i915_gem_set_wedged DMA_FADDR: 0x_00283260
<7>[  239.100114] i915_gem_set_wedged IPEIR: 0x
<7>[  239.100117] i915_gem_set_wedged IPEHR: 0x0280
<7>[  239.100120] i915_gem_set_wedged Execlist status: 0x00044052 
0002
<7>[  239.100124] i915_gem_set_wedged Execlist CSB read 5 [5 cached], 
write 5 [5 from hws], interrupt posted? no, tasklet queued? no (enabled)
<7>[  239.100128] i915_gem_set_wedged ELSP[0] count=1, 
ring->start=00283000, rq: 19a99 [e8c:5f] prio=1024 @ 5164ms: (null)
<7>[  239.100132] i915_gem_set_wedged ELSP[1] count=1, 
ring->start=00257000, rq: 19a9a [e81:1a] prio=139 @ 5164ms: igt/rcs0[5977]/1
<7>[  239.100135] i915_gem_set_wedged HW active? 0x5
<7>[  239.100250] i915_gem_set_wedged E 19a99 [e8c:5f] 
prio=1024 @ 5164ms: (null)
<7>[  239.100338] i915_gem_set_wedged E 19a9a [e81:1a] prio=139 
@ 5164ms: igt/rcs0[5977]/1
<7>[  239.100340] i915_gem_set_wedged Queue priority: 139
<7>[  239.100343] i915_gem_set_wedged Q 0 [e98:19] prio=132 @ 
5164ms: igt/rcs0[5977]/8
<7>[  239.100346] i915_gem_set_wedged Q 0 [e84:19] prio=121 @ 
5165ms: igt/rcs0[5977]/2
<7>[  239.100349] i915_gem_set_wedged Q 0 [e87:19] prio=82 @ 
5165ms: igt/rcs0[5977]/3
<7>[  239.100352] i915_gem_set_wedged Q 0 [e84:1a] prio=44 @ 
5164ms: igt/rcs0[5977]/2
<7>[  239.100356] i915_gem_set_wedged Q 0 [e8b:19] prio=20 @ 
5165ms: igt/rcs0[5977]/4
<7>[  239.100362] i915_gem_set_wedged drv_selftest [5894] waiting for 
19a99

where the GPU saw an arbitration point and idles; AND HAS NOT BEEN RESET!
The RING_MODE indicates that is idle and has the STOP_RING bit set, so
try clearing it.

v2: Only clear the bit on restarting the ring, as we want to be sure the
STOP_RING bit is kept if reset fails on wedging.
v3: Spot when the ring state doesn't make sense when re-initialising the
engine and dump it to the logs so that we don't have to wait for an
error later and try to guess what happened earlier.
v4: Prepare to print all the unexpected state, not just the first.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
  drivers/gpu/drm/i915/intel_lrc.c | 22 ++
  1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3744f5750624..ba8411ba4abf 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1781,6 +1781,9 @@ static void enable_execlists(struct intel_engine_cs 
*engine)
  I915_WRITE(RING_MODE_GEN7(engine),
 

Re: [Intel-gfx] [PATCH 1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR

[Jani Nikula]

On Thu, 17 May 2018, Tarun Vyas  wrote:
> On Fri, May 11, 2018 at 12:51:40PM -0700, Dhinakaran Pandiyan wrote:
>> Ville noticed that we are unncessarily reading DPCD's after knowing
>> panel did not support PSR. Looks like this check that was present
>> earlier got removed unintentionally, let's put it back.
>> 
>> While we do this, add the PSR version number in the debug print.
>> 
>> Cc: Ville Syrjälä 
>> Signed-off-by: Dhinakaran Pandiyan 
>> ---
>>  drivers/gpu/drm/i915/intel_psr.c | 14 --
>>  1 file changed, 8 insertions(+), 6 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
>> b/drivers/gpu/drm/i915/intel_psr.c
>> index db27f2faa1de..8fe6d2f9ab2b 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -250,10 +250,12 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>>  drm_dp_dpcd_read(_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
>>   sizeof(intel_dp->psr_dpcd));
>>  
>> -if (intel_dp->psr_dpcd[0]) {
>> -dev_priv->psr.sink_support = true;
>> -DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
>> -}
>> +if (!intel_dp->psr_dpcd[0])
>> +return;
>> +
>> +DRM_DEBUG_KMS("eDP panel supports PSR version %x\n",
>> +  intel_dp->psr_dpcd[0]);
>> +dev_priv->psr.sink_support = true;
>>  
>>  if (INTEL_GEN(dev_priv) >= 9 &&
>>  (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
>> @@ -270,8 +272,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>>   */
>>  dev_priv->psr.sink_psr2_support =
>>  intel_dp_get_y_coord_required(intel_dp);
>> -DRM_DEBUG_KMS("PSR2 %s on sink", dev_priv->psr.sink_psr2_support
>> -  ? "supported" : "not supported");
>> +DRM_DEBUG_KMS("PSR2 %ssupported\n",
>> +  dev_priv->psr.sink_psr2_support ? "" : "not ");
> Would it make sense to make it clearer that PSR2 is not supported b/c of lack 
> of y-coordinate support on the sink ?
>
> Reviewed-by: Tarun Vyas 

Pushed to dinq, thanks for the patch and review.

BR,
Jani.


>>  
>>  if (dev_priv->psr.sink_psr2_support) {
>>  dev_priv->psr.colorimetry_support =
>> -- 
>> 2.14.1
>> 
>> ___
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>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 2/6] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.

[Jani Nikula]

On Fri, 11 May 2018, Dhinakaran Pandiyan  wrote:
> On Fri, 2018-05-11 at 12:51 -0700, Dhinakaran Pandiyan wrote:
>> By moving the check from psr_compute_config() to psr_init_dpcd(), we
>> get
>> to set the dev_priv->psr.sink_support flag only when the panel is
>> capable of changing power state. An additional benefit is that the
>> check
>> will be performed only at init time instead of every atomic_check.
>> 
>> This should change the psr_basic IGT failures on HSW to skips.
>> 
>> v2: Return early when SET_POWER_CAPABLE bit is 0 (Jose)
>> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106217
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106346

Pushed to dinq, thanks for the patch and review.

BR,
Jani.

>> Cc: José Roberto de Souza 
>> Cc: Ville Syrjälä 
>> Signed-off-by: Dhinakaran Pandiyan 
>> Reviewed-by: José Roberto de Souza 
>> ---
>>  drivers/gpu/drm/i915/intel_dp.c  |  8 ++--
>>  drivers/gpu/drm/i915/intel_psr.c | 11 +--
>>  2 files changed, 11 insertions(+), 8 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c
>> b/drivers/gpu/drm/i915/intel_dp.c
>> index dde92e4af5d3..cfd95eaa0d0d 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -3762,8 +3762,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
>>  dev_priv->no_aux_handshake = intel_dp-
>> >dpcd[DP_MAX_DOWNSPREAD] &
>>  DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
>>  
>> -intel_psr_init_dpcd(intel_dp);
>> -
>>  /*
>>   * Read the eDP display control registers.
>>   *
>> @@ -3779,6 +3777,12 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
>>  DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int)
>> sizeof(intel_dp->edp_dpcd),
>>    intel_dp->edp_dpcd);
>>  
>> +/*
>> + * This has to be called after intel_dp->edp_dpcd is filled,
>> PSR checks
>> + * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
>> + */
>> +intel_psr_init_dpcd(intel_dp);
>> +
>>  /* Read the eDP 1.4+ supported link rates. */
>>  if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
>>  __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c
>> b/drivers/gpu/drm/i915/intel_psr.c
>> index 8fe6d2f9ab2b..61ade81576f5 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -252,9 +252,13 @@ void intel_psr_init_dpcd(struct intel_dp
>> *intel_dp)
>>  
>>  if (!intel_dp->psr_dpcd[0])
>>  return;
>> -
>>  DRM_DEBUG_KMS("eDP panel supports PSR version %x\n",
>>    intel_dp->psr_dpcd[0]);
>> +
>> +if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
>> +DRM_DEBUG_KMS("Panel lacks power state control, PSR
>> cannot be enabled\n");
>> +return;
>> +}
>>  dev_priv->psr.sink_support = true;
>>  
>>  if (INTEL_GEN(dev_priv) >= 9 &&
>> @@ -642,11 +646,6 @@ void intel_psr_compute_config(struct intel_dp
>> *intel_dp,
>>  return;
>>  }
>>  
>> -if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
>> -DRM_DEBUG_KMS("PSR condition failed: panel lacks
>> power state control\n");
>> -return;
>> -}
>> -
>>  crtc_state->has_psr = true;
>>  crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp,
>> crtc_state);
>>  DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2"
>> : "");
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Re: [Intel-gfx] [PATCH v2 11/24] drm/i915/icl: Get DDI clock for ICL based on PLLs.

[Mika Kahola]

Patch look ok to me.

Reviewed-by: Mika Kahola 

On Wed, 2018-05-23 at 15:44 -0700, Paulo Zanoni wrote:
> From: Manasi Navare 
> 
> PLLs are the source clocks for the DDIs so in order
> to determine the ddi clock we need to check the PLL
> configuration.
> 
> This gets a little tricky for ICL since there is
> no register bit that maps directly to the link clock.
> So this patch creates a separate function in intel_dpll_mgr.c
> to obtain the write array PLL Params and compares the set
> pll_params with the table to get the corresponding link
> clock.
> 
> v2:
>   - Fix the encoder type check (DK).
>   - Improve our error checking, return a sane value (Mika, Paulo).
>   - Fix table entries (Paulo).
> 
> Cc: Rodrigo Vivi 
> Cc: Mika Kahola 
> Cc: Paulo Zanoni 
> Cc: Dhinakaran Pandiyan 
> Signed-off-by: Manasi Navare 
> Signed-off-by: Lucas De Marchi 
> [Paulo: implement v2]
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/i915_reg.h   |  3 ++
>  drivers/gpu/drm/i915/intel_ddi.c  | 26 +
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 70
> +++
>  drivers/gpu/drm/i915/intel_dpll_mgr.h |  2 +
>  4 files changed, 101 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index de6fcdb4948f..7c6346542a52 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9174,13 +9174,16 @@ enum skl_power_gate {
>  #define  DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
>  #define  DPLL_CFGCR1_QDIV_RATIO_SHIFT(10)
>  #define  DPLL_CFGCR1_QDIV_RATIO(x)   ((x) << 10)
> +#define  DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
>  #define  DPLL_CFGCR1_QDIV_MODE(x)((x) << 9)
>  #define  DPLL_CFGCR1_KDIV_MASK   (7 << 6)
> +#define  DPLL_CFGCR1_KDIV_SHIFT  (6)
>  #define  DPLL_CFGCR1_KDIV(x) ((x) << 6)
>  #define  DPLL_CFGCR1_KDIV_1  (1 << 6)
>  #define  DPLL_CFGCR1_KDIV_2  (2 << 6)
>  #define  DPLL_CFGCR1_KDIV_4  (4 << 6)
>  #define  DPLL_CFGCR1_PDIV_MASK   (0xf << 2)
> +#define  DPLL_CFGCR1_PDIV_SHIFT  (2)
>  #define  DPLL_CFGCR1_PDIV(x) ((x) << 2)
>  #define  DPLL_CFGCR1_PDIV_2  (1 << 2)
>  #define  DPLL_CFGCR1_PDIV_3  (2 << 2)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index f6b2c0ec4e97..0e0b726e3a49 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1429,6 +1429,30 @@ static void ddi_dotclock_get(struct
> intel_crtc_state *pipe_config)
>   pipe_config->base.adjusted_mode.crtc_clock = dotclock;
>  }
>  
> +static void icl_ddi_clock_get(struct intel_encoder *encoder,
> +   struct intel_crtc_state *pipe_config)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
> + enum port port = encoder->port;
> + int link_clock = 0;
> + uint32_t pll_id;
> +
> + pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config-
> >shared_dpll);
> + if (port == PORT_A || port == PORT_B) {
> + if (intel_crtc_has_type(pipe_config,
> INTEL_OUTPUT_HDMI))
> + link_clock = cnl_calc_wrpll_link(dev_priv,
> pll_id);
> + else
> + link_clock =
> icl_calc_dp_combo_pll_link(dev_priv,
> + pll_
> id);
> + } else {
> + /* FIXME - Add for MG PLL */
> + WARN(1, "MG PLL clock_get code not implemented
> yet\n");
> + }
> +
> + pipe_config->port_clock = link_clock;
> + ddi_dotclock_get(pipe_config);
> +}
> +
>  static void cnl_ddi_clock_get(struct intel_encoder *encoder,
>     struct intel_crtc_state *pipe_config)
>  {
> @@ -1622,6 +1646,8 @@ static void intel_ddi_clock_get(struct
> intel_encoder *encoder,
>   bxt_ddi_clock_get(encoder, pipe_config);
>   else if (IS_CANNONLAKE(dev_priv))
>   cnl_ddi_clock_get(encoder, pipe_config);
> + else if (IS_ICELAKE(dev_priv))
> + icl_ddi_clock_get(encoder, pipe_config);
>  }
>  
>  void intel_ddi_set_pipe_settings(const struct intel_crtc_state
> *crtc_state)
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 383fbc15113d..07bdbf2582ba 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2525,6 +2525,76 @@ static bool icl_calc_dpll_state(struct
> intel_crtc_state *crtc_state,
>   return true;
>  }
>  
> +int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> +    uint32_t pll_id)
> +{
> + uint32_t cfgcr0, cfgcr1;
> + uint32_t pdiv, 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Look for an active kernel context before switching (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Look for an active kernel context before switching (rev2)
URL   : https://patchwork.freedesktop.org/series/43609/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4228 -> Patchwork_9102 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43609/revisions/2/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9102 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_mmap_gtt@basic-small-bo-tiledx:
  fi-gdg-551: PASS -> FAIL (fdo#102575)


  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575


== Participating hosts (44 -> 39) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4228 -> Patchwork_9102

  CI_DRM_4228: 8e3e5c1cc5de96c61ff995282ab952ff5d47a211 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4498: f9ecb79ad8b02278cfdb5b82495df47061c04f8f @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9102: 2fa6e902cd0d0a8680a4768a909d5808e23e7017 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

2fa6e902cd0d drm/i915: Look for an active kernel context before switching

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9102/issues.html
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Re: [Intel-gfx] [PATCH] drm/i915/psr: Nuke PSR support for VLV and CHV

[Jani Nikula]

On Mon, 14 May 2018, Dhinakaran Pandiyan  wrote:
> On Mon, 2018-05-14 at 12:09 +0300, Jani Nikula wrote:
>> On Fri, 11 May 2018, Dhinakaran Pandiyan > om> wrote:
>> > 
>> > PSR hardware and hence the driver code for VLV and CHV deviates a
>> > lot from
>> > their DDI counterparts. While the feature has been disabled for a
>> > long time
>> > now, retaining support for these platforms is a maintenance burden.
>> > There
>> > have been multiple refactoring commits to just keep the existing
>> > code for
>> > these platforms in line with the rest. There are known issues that
>> > need to
>> > be fixed to enable PSR on these platforms, and there is no PSR
>> > capable
>> > platform in CI to ensure the code does not break again if we get
>> > around to
>> > fixing the existing issues. On account of all these reasons, let's
>> > nuke
>> > this code for now and bring it back if a need arises in the future.
>> > 
>> > Cc: Jani Nikula 
>> > Cc: Rodrigo Vivi 
>> > Cc: Ville Syrjälä 
>> > Signed-off-by: Dhinakaran Pandiyan 
>> Acked-by: Jani Nikula 
>> 
> Thank you. 
>
> Including Rodrigo's ack that was sent internally
> Acked-by: Rodrigo Vivi  


Pushed to dinq, thanks for the patch.

BR,
Jani.

>
>
>> > 
>> > ---
>> >  drivers/gpu/drm/i915/i915_debugfs.c  |  42 +-
>> >  drivers/gpu/drm/i915/i915_drv.h  |   1 -
>> >  drivers/gpu/drm/i915/i915_pci.c  |   2 -
>> >  drivers/gpu/drm/i915/intel_drv.h |   2 -
>> >  drivers/gpu/drm/i915/intel_frontbuffer.c |   2 -
>> >  drivers/gpu/drm/i915/intel_psr.c | 248 +++--
>> > --
>> >  6 files changed, 27 insertions(+), 270 deletions(-)
>> > 
>> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
>> > b/drivers/gpu/drm/i915/i915_debugfs.c
>> > index 13e7b9e4a6e6..0096e209fe04 100644
>> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> > @@ -2630,8 +2630,6 @@ static int i915_edp_psr_status(struct
>> > seq_file *m, void *data)
>> >  {
>> >    struct drm_i915_private *dev_priv = node_to_i915(m-
>> > >private);
>> >    u32 psrperf = 0;
>> > -  u32 stat[3];
>> > -  enum pipe pipe;
>> >    bool enabled = false;
>> >    bool sink_support;
>> >  
>> > @@ -2652,47 +2650,17 @@ static int i915_edp_psr_status(struct
>> > seq_file *m, void *data)
>> >    seq_printf(m, "Re-enable work scheduled: %s\n",
>> >       yesno(work_busy(_priv->psr.work.work)));
>> >  
>> > -  if (HAS_DDI(dev_priv)) {
>> > -  if (dev_priv->psr.psr2_enabled)
>> > -  enabled = I915_READ(EDP_PSR2_CTL) &
>> > EDP_PSR2_ENABLE;
>> > -  else
>> > -  enabled = I915_READ(EDP_PSR_CTL) &
>> > EDP_PSR_ENABLE;
>> > -  } else {
>> > -  for_each_pipe(dev_priv, pipe) {
>> > -  enum transcoder cpu_transcoder =
>> > -  intel_pipe_to_cpu_transcoder(dev_p
>> > riv, pipe);
>> > -  enum intel_display_power_domain
>> > power_domain;
>> > -
>> > -  power_domain =
>> > POWER_DOMAIN_TRANSCODER(cpu_transcoder);
>> > -  if
>> > (!intel_display_power_get_if_enabled(dev_priv,
>> > -  po
>> > wer_domain))
>> > -  continue;
>> > -
>> > -  stat[pipe] = I915_READ(VLV_PSRSTAT(pipe))
>> > &
>> > -  VLV_EDP_PSR_CURR_STATE_MASK;
>> > -  if ((stat[pipe] ==
>> > VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
>> > -  (stat[pipe] ==
>> > VLV_EDP_PSR_ACTIVE_SF_UPDATE))
>> > -  enabled = true;
>> > -
>> > -  intel_display_power_put(dev_priv,
>> > power_domain);
>> > -  }
>> > -  }
>> > +  if (dev_priv->psr.psr2_enabled)
>> > +  enabled = I915_READ(EDP_PSR2_CTL) &
>> > EDP_PSR2_ENABLE;
>> > +  else
>> > +  enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
>> >  
>> >    seq_printf(m, "Main link in standby mode: %s\n",
>> >       yesno(dev_priv->psr.link_standby));
>> >  
>> > -  seq_printf(m, "HW Enabled & Active bit: %s",
>> > yesno(enabled));
>> > -
>> > -  if (!HAS_DDI(dev_priv))
>> > -  for_each_pipe(dev_priv, pipe) {
>> > -  if ((stat[pipe] ==
>> > VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
>> > -  (stat[pipe] ==
>> > VLV_EDP_PSR_ACTIVE_SF_UPDATE))
>> > -  seq_printf(m, " pipe %c",
>> > pipe_name(pipe));
>> > -  }
>> > -  seq_puts(m, "\n");
>> > +  seq_printf(m, "HW Enabled & Active bit: %s\n",
>> > yesno(enabled));
>> >  
>> >    /*
>> > -   * VLV/CHV PSR has no kind of performance counter
>> >     * SKL+ Perf counter is reset to 0 everytime DC state is
>> > entered
>> >     */
>> >    if (IS_HASWELL(dev_priv) || 

Re: [Intel-gfx] [PATCH] drm/i915/psr: vbt change for psr

[Jani Nikula]

On Tue, 22 May 2018, Jani Nikula  wrote:
> On Tue, 22 May 2018, vathsala nagaraju  wrote:
>> From: Vathsala Nagaraju 
>>
>> For psr block #9, the vbt description has moved to options [0-3] for
>> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
>> structure. Since spec does not  mention from which VBT version this
>> change was added to vbt.bsf file, we cannot depend on bdb->version check
>> to change for all the platforms.
>>
>> There is RCR inplace for GOP team to  provide the version number
>> to make generic change. Since Kabylake with bdb version 209 is having this
>> change, limiting this change to gen9_bc and version 209+ to unblock google.
>>
>> Tested on skl(bdb version 203,without options) and
>> kabylake(bdb version 209,212) having new options.
>>
>> bspec 20131
>>
>> v2: (Jani and Rodrigo)
>> move the 165 version check to intel_bios.c
>> v3: Jani
>> Move the abstraction to intel_bios.
>> v4: Jani
>> Rename tp*_wakeup_time to have "us" suffix.
>> For values outside range[0-3],default to max 2500us.
>> Old decimal value was wake up time in multiples of 100us.
>> v5: Jani and Rodrigo
>> Handle option 2 in default condition.
>> Print oustide range value.
>> For negetive values default to 2500us.
>> v6: Jani
>> Handle default first and then fall through for case 2.
>> v7: Rodrigo
>> Apply this change for IS_GEN9_BC and vbt version > 209
>> v8: Puthik
>> Add new function vbt_psr_to_us.
>> v9: Jani
>> Change to v7 version as it's more readable.
>> DK
>> add comment /*fall through*/ after case2.
>>
>> Cc: Rodrigo Vivi 
>> Cc: Puthikorn Voravootivat 
>> Cc: Dhinakaran Pandiyan 
>> Cc: Jani Nikula 
>> Cc: José Roberto de Souza 
>>
>> Signed-off-by: Maulik V Vaghela 
>> Signed-off-by: Vathsala Nagaraju 
>
> Reviewed-by: Jani Nikula 

And pushed to dinq. Thanks for the patch.

BR,
Jani.

>
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>>  drivers/gpu/drm/i915/i915_reg.h   |  8 +++
>>  drivers/gpu/drm/i915/intel_bios.c | 48 
>> +--
>>  drivers/gpu/drm/i915/intel_psr.c  | 39 +++
>>  4 files changed, 72 insertions(+), 27 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h 
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index e33c380..dcfa791 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1078,8 +1078,8 @@ struct intel_vbt_data {
>>  bool require_aux_wakeup;
>>  int idle_frames;
>>  enum psr_lines_to_wait lines_to_wait;
>> -int tp1_wakeup_time;
>> -int tp2_tp3_wakeup_time;
>> +int tp1_wakeup_time_us;
>> +int tp2_tp3_wakeup_time_us;
>>  } psr;
>>  
>>  struct {
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 196a0eb..513b4a4 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -4088,10 +4088,10 @@ enum {
>>  #define   EDP_Y_COORDINATE_ENABLE   (1<<25) /* GLK and CNL+ */
>>  #define   EDP_MAX_SU_DISABLE_TIME(t)((t)<<20)
>>  #define   EDP_MAX_SU_DISABLE_TIME_MASK  (0x1f<<20)
>> -#define   EDP_PSR2_TP2_TIME_500 (0<<8)
>> -#define   EDP_PSR2_TP2_TIME_100 (1<<8)
>> -#define   EDP_PSR2_TP2_TIME_2500(2<<8)
>> -#define   EDP_PSR2_TP2_TIME_50  (3<<8)
>> +#define   EDP_PSR2_TP2_TIME_500us   (0<<8)
>> +#define   EDP_PSR2_TP2_TIME_100us   (1<<8)
>> +#define   EDP_PSR2_TP2_TIME_2500us  (2<<8)
>> +#define   EDP_PSR2_TP2_TIME_50us(3<<8)
>>  #define   EDP_PSR2_TP2_TIME_MASK(3<<8)
>>  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c 
>> b/drivers/gpu/drm/i915/intel_bios.c
>> index 54270bd..417f656 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -688,8 +688,52 @@ static int intel_bios_ssc_frequency(struct 
>> drm_i915_private *dev_priv,
>>  break;
>>  }
>>  
>> -dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
>> -dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
>> +/*
>> + * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
>> + * Old decimal value is wake up time in multiples of 100 us.
>> + */
>> +if (bdb->version >= 209 && IS_GEN9_BC(dev_priv)) {
>> +switch (psr_table->tp1_wakeup_time) {
>> +case 0:
>> +dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
>> +break;
>> +case 1:
>> +

[Intel-gfx] [PATCH] drm/i915: Allow DBLSCAN user modes with eDP/LVDS/DSI

[Ville Syrjala]

From: Ville Syrjälä 

When encountering a connector with the scaling mode property both
intel and modesetting ddxs sometimes add tons of DBLSCAN modes
to the output's mode list. The idea presumably being that since the
output will be going through the panel fitter anyway we can pretend
to use any kind of mode.

Sadly that means we can't reject user modes with the DBLSCAN flag
until we know whether we're going to be using the panel's native
mode or the user mode directly. Doing otherwise means X clients using
xf86vidmode/xrandr will get a protocol error (and often self
terminate as a result) when the kernel refuses to use the requested
mode with the DBLSCAN flag.

To undo the regression we'll move the DBLSCAN checks into the
connector->mode_valid() and encoder->compute_config() hooks.

Cc: Vito Caputo 
Reported-by: Vito Caputo 
Fixes: e995ca0b8139 ("drm/i915: Provide a device level .mode_valid() hook")
References: https://lkml.org/lkml/2018/5/21/715
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_crt.c | 20 
 drivers/gpu/drm/i915/intel_display.c | 16 +---
 drivers/gpu/drm/i915/intel_dp.c  |  6 ++
 drivers/gpu/drm/i915/intel_dp_mst.c  |  6 ++
 drivers/gpu/drm/i915/intel_dsi.c |  6 ++
 drivers/gpu/drm/i915/intel_dvo.c |  6 ++
 drivers/gpu/drm/i915/intel_hdmi.c|  6 ++
 drivers/gpu/drm/i915/intel_lvds.c|  5 +
 drivers/gpu/drm/i915/intel_sdvo.c|  6 ++
 drivers/gpu/drm/i915/intel_tv.c  | 12 ++--
 10 files changed, 84 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 211d601cd1b1..95aa29cf2d9c 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -304,6 +304,9 @@ intel_crt_mode_valid(struct drm_connector *connector,
int max_dotclk = dev_priv->max_dotclk_freq;
int max_clock;
 
+   if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
+   return MODE_NO_DBLESCAN;
+
if (mode->clock < 25000)
return MODE_CLOCK_LOW;
 
@@ -337,6 +340,12 @@ static bool intel_crt_compute_config(struct intel_encoder 
*encoder,
 struct intel_crtc_state *pipe_config,
 struct drm_connector_state *conn_state)
 {
+   struct drm_display_mode *adjusted_mode =
+   _config->base.adjusted_mode;
+
+   if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
+   return false;
+
return true;
 }
 
@@ -344,6 +353,12 @@ static bool pch_crt_compute_config(struct intel_encoder 
*encoder,
   struct intel_crtc_state *pipe_config,
   struct drm_connector_state *conn_state)
 {
+   struct drm_display_mode *adjusted_mode =
+   _config->base.adjusted_mode;
+
+   if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
+   return false;
+
pipe_config->has_pch_encoder = true;
 
return true;
@@ -354,6 +369,11 @@ static bool hsw_crt_compute_config(struct intel_encoder 
*encoder,
   struct drm_connector_state *conn_state)
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   struct drm_display_mode *adjusted_mode =
+   _config->base.adjusted_mode;
+
+   if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
+   return false;
 
pipe_config->has_pch_encoder = true;
 
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 8b385176ce3c..02651298a99b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14443,12 +14443,22 @@ static enum drm_mode_status
 intel_mode_valid(struct drm_device *dev,
 const struct drm_display_mode *mode)
 {
+   /*
+* Can't reject DBLSCAN here because Xorg ddxen can add piles
+* of DBLSCAN modes to the output's mode list when they detect
+* the scaling mode property on the connector. And they don't
+* ask the kernel to validate those modes in any way until
+* modeset time at which point the client gets a protocol error.
+* So in order to not upset those clients we silently ignore the
+* DBLSCAN flag on such connectors. For other connectors we will
+* reject modes with the DBLSCAN flag in encoder->compute_config().
+* And we always reject DBLSCAN modes in connector->mode_valid()
+* as we never want such modes on the connector's mode list.
+*/
+
if (mode->vscan > 1)
return MODE_NO_VSCAN;
 
-   if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
-   return MODE_NO_DBLESCAN;
-
if (mode->flags & DRM_MODE_FLAG_HSKEW)
return MODE_H_ILLEGAL;
 
diff --git 

[Intel-gfx] [PATCH i-g-t] tests/drv_suspend: Suspend under memory pressure

[Chris Wilson]

Recently we discovered that we have a race between swapping and
suspend in our resume path (we might be trying to page in an object
after disabling the block devices). Let's try to exercise that by
exhausting all of system memory before suspend.

References: https://bugs.freedesktop.org/show_bug.cgi?id=106640
Signed-off-by: Chris Wilson 
Cc: Tomi Sarvela 
---
 lib/igt_core.c  | 34 --
 lib/igt_core.h  |  1 +
 tests/drv_suspend.c | 42 ++
 3 files changed, 63 insertions(+), 14 deletions(-)

diff --git a/lib/igt_core.c b/lib/igt_core.c
index e292ca24c..804ce4578 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -1756,20 +1756,7 @@ void igt_child_done(pid_t pid)
test_children[i] = test_children[i + 1];
 }
 
-/**
- * igt_waitchildren:
- *
- * Wait for all children forked with igt_fork.
- *
- * The magic here is that exit codes from children will be correctly propagated
- * to the main thread, including the relevant exit code if a child thread 
failed.
- * Of course if multiple children failed with different exit codes the 
resulting
- * exit code will be non-deterministic.
- *
- * Note that igt_skip() will not be forwarded, feature tests need to be done
- * before spawning threads with igt_fork().
- */
-void igt_waitchildren(void)
+int __igt_waitchildren(void)
 {
int err = 0;
int count;
@@ -1815,6 +1802,25 @@ void igt_waitchildren(void)
}
 
num_test_children = 0;
+   return err;
+}
+
+/**
+ * igt_waitchildren:
+ *
+ * Wait for all children forked with igt_fork.
+ *
+ * The magic here is that exit codes from children will be correctly propagated
+ * to the main thread, including the relevant exit code if a child thread 
failed.
+ * Of course if multiple children failed with different exit codes the 
resulting
+ * exit code will be non-deterministic.
+ *
+ * Note that igt_skip() will not be forwarded, feature tests need to be done
+ * before spawning threads with igt_fork().
+ */
+void igt_waitchildren(void)
+{
+   int err = __igt_waitchildren();
if (err)
igt_fail(err);
 }
diff --git a/lib/igt_core.h b/lib/igt_core.h
index 3d7b787b2..6d4260403 100644
--- a/lib/igt_core.h
+++ b/lib/igt_core.h
@@ -742,6 +742,7 @@ bool __igt_fork(void);
for (int child = 0; child < (num_children); child++) \
for (; __igt_fork(); exit(0))
 void igt_child_done(pid_t pid);
+int __igt_waitchildren(void);
 void igt_waitchildren(void);
 void igt_waitchildren_timeout(int seconds, const char *reason);
 
diff --git a/tests/drv_suspend.c b/tests/drv_suspend.c
index 2e39f20ae..8f71a81d1 100644
--- a/tests/drv_suspend.c
+++ b/tests/drv_suspend.c
@@ -160,6 +160,45 @@ test_sysfs_reader(bool hibernate)
igt_stop_helper();
 }
 
+static void
+test_shrink(int fd, unsigned int mode)
+{
+   uint64_t *can_mlock;
+   void *locked;
+   uint64_t pin;
+
+   gem_quiescent_gpu(fd);
+   intel_purge_vm_caches(fd);
+
+   can_mlock = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
+   igt_assert(can_mlock != MAP_FAILED);
+
+   pin = intel_get_total_ram_mb() << 20;
+
+   igt_debug("Locking %'"PRIu64" MiB\n", pin >> 20);
+   locked = malloc(pin);
+   igt_assert(locked);
+
+   /* Lock all the system memory, forcing the driver into swap and OOM */
+   igt_fork(child, 1) {
+   for (uint64_t bytes = 64 << 20; bytes <= pin; bytes += 64 << 20)
+   if (!mlock(locked, bytes))
+   *can_mlock = bytes;
+   if (!mlock(locked, pin))
+   *can_mlock = pin;
+   }
+   __igt_waitchildren();
+   igt_require(*can_mlock);
+   mlock(locked, *can_mlock);
+   igt_info("Locked %'"PRIu64" MiB\n", *can_mlock >> 20);
+   munmap(can_mlock, 4096);
+
+   intel_purge_vm_caches(fd);
+   igt_system_suspend_autoresume(mode, SUSPEND_TEST_NONE);
+
+   free(locked);
+}
+
 static void
 test_forcewake(int fd, bool hibernate)
 {
@@ -199,6 +238,9 @@ igt_main
igt_subtest("sysfs-reader")
test_sysfs_reader(false);
 
+   igt_subtest("shrink")
+   test_shrink(fd, SUSPEND_STATE_MEM);
+
igt_subtest("forcewake")
test_forcewake(fd, false);
 
-- 
2.17.0

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