Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dp: Modeset only the tiled connectors with CRTC
On 28/01/2020 01:05, Navare, Manasi D wrote: > On Sat, Jan 25, 2020 at 01:31:06AM -0800, Saarinen, Jani wrote: >> + Martin to re-report. > > Could you re-report this so we get the full CI IGT results? Sorry, I had done the work but I re-reported the wrong run... Anyway, I queued the re-reporting. Sorry about this! Martin > > Manasi > >> >>> -Original Message- >>> From: Navare, Manasi D >>> Sent: lauantai 25. tammikuuta 2020 4.19 >>> To: intel-gfx@lists.freedesktop.org >>> Cc: Sarvela, Tomi P ; Saarinen, Jani >>> ; Nautiyal, Ankit K ; >>> Nikkanen, Kimmo >>> Subject: RE: ✗ Fi.CI.BAT: failure for drm/i915/dp: Modeset only the tiled >>> connectors >>> with CRTC >>> >>> This Gem related failure is not relevant to this patch, but because of this >>> it doesn’t >>> run full IGT, I want to make sure that the kms_flip tests are not getting >>> hung. >>> >>> Or can we confirm this with manual testing? >>> >>> Manasi >>> >>> -Original Message- >>> From: Patchwork >>> Sent: Friday, January 24, 2020 5:47 PM >>> To: Navare, Manasi D >>> Cc: intel-gfx@lists.freedesktop.org >>> Subject: ✗ Fi.CI.BAT: failure for drm/i915/dp: Modeset only the tiled >>> connectors >>> with CRTC >>> >>> == Series Details == >>> >>> Series: drm/i915/dp: Modeset only the tiled connectors with CRTC >>> URL : https://patchwork.freedesktop.org/series/72559/ >>> State : failure >>> >>> == Summary == >>> >>> CI Bug Log - changes from CI_DRM_7811 -> Patchwork_16267 >>> >>> >>> Summary >>> --- >>> >>> **FAILURE** >>> >>> Serious unknown changes coming with Patchwork_16267 absolutely need to be >>> verified manually. >>> >>> If you think the reported changes have nothing to do with the changes >>> introduced in Patchwork_16267, please notify your bug team to allow them >>> to document this new failure mode, which will reduce false positives in >>> CI. >>> >>> External URL: https://intel-gfx-ci.01.org/tree/drm- >>> tip/Patchwork_16267/index.html >>> >>> Possible new issues >>> --- >>> >>> Here are the unknown changes that may have been introduced in >>> Patchwork_16267: >>> >>> ### IGT changes ### >>> >>> Possible regressions >>> >>> * igt@gem_close_race@basic-threads: >>> - fi-hsw-peppy: [PASS][1] -> [INCOMPLETE][2] >>>[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-hsw- >>> peppy/igt@gem_close_r...@basic-threads.html >>>[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-hsw- >>> peppy/igt@gem_close_r...@basic-threads.html >>> >>> >>> Known issues >>> >>> >>> Here are the changes found in Patchwork_16267 that come from known issues: >>> >>> ### IGT changes ### >>> >>> Issues hit >>> >>> * igt@kms_chamelium@hdmi-hpd-fast: >>> - fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#111096] / [i915#323]) >>>[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-kbl- >>> 7500u/igt@kms_chamel...@hdmi-hpd-fast.html >>>[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-kbl- >>> 7500u/igt@kms_chamel...@hdmi-hpd-fast.html >>> >>> >>> Possible fixes >>> >>> * igt@gem_exec_parallel@fds: >>> - fi-byt-n2820: [TIMEOUT][5] ([fdo#112271]) -> [PASS][6] >>>[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-byt- >>> n2820/igt@gem_exec_paral...@fds.html >>>[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-byt- >>> n2820/igt@gem_exec_paral...@fds.html >>> >>> * igt@i915_module_load@reload-with-fault-injection: >>> - fi-cfl-8700k: [DMESG-WARN][7] ([i915#889]) -> [PASS][8] >>>[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-cfl- >>> 8700k/igt@i915_module_l...@reload-with-fault-injection.html >>>[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-cfl- >>> 8700k/igt@i915_module_l...@reload-with-fault-injection.html >>> >>> * igt@i915_selftest@live_blt: >>> - fi-hsw-4770:[DMESG-FAIL][9] ([i915#725]) -> [PASS][10] >>>[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-hsw- >>> 4770/igt@i915_selftest@live_blt.html >>>[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-hsw- >>> 4770/igt@i915_selftest@live_blt.html >>> >>> * igt@i915_selftest@live_gem_contexts: >>> - fi-byt-n2820: [DMESG-FAIL][11] ([i915#722]) -> [PASS][12] >>>[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-byt- >>> n2820/igt@i915_selftest@live_gem_contexts.html >>>[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-byt- >>> n2820/igt@i915_selftest@live_gem_contexts.html >>> >>> * igt@i915_selftest@live_gtt: >>> - fi-bdw-5557u: [TIMEOUT][13] ([fdo#112271]) -> [PASS][14] >>>[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-bdw- >>> 5557u/igt@i915_selftest@live_gtt.html >>>[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-bdw- >>> 5557u/igt@i915_sel
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: Modeset only the tiled connectors with CRTC
== Series Details == Series: drm/i915/dp: Modeset only the tiled connectors with CRTC URL : https://patchwork.freedesktop.org/series/72559/ State : success == Summary == CI Bug Log - changes from CI_DRM_7811 -> Patchwork_16267 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/index.html Known issues Here are the changes found in Patchwork_16267 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-hsw-peppy: [PASS][1] -> [INCOMPLETE][2] ([i915#816]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-hsw-peppy/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-hsw-peppy/igt@gem_close_r...@basic-threads.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#111096] / [i915#323]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@gem_exec_parallel@fds: - fi-byt-n2820: [TIMEOUT][5] ([fdo#112271]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-byt-n2820/igt@gem_exec_paral...@fds.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-byt-n2820/igt@gem_exec_paral...@fds.html * igt@i915_module_load@reload-with-fault-injection: - fi-cfl-8700k: [DMESG-WARN][7] ([i915#889]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-cfl-8700k/igt@i915_module_l...@reload-with-fault-injection.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-cfl-8700k/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][9] ([i915#725]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-hsw-4770/igt@i915_selftest@live_blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-byt-n2820: [DMESG-FAIL][11] ([i915#722]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_gtt: - fi-bdw-5557u: [TIMEOUT][13] ([fdo#112271]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-bdw-5557u/igt@i915_selftest@live_gtt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-bdw-5557u/igt@i915_selftest@live_gtt.html Warnings * igt@gem_exec_parallel@contexts: - fi-byt-n2820: [FAIL][15] ([i915#694]) -> [TIMEOUT][16] ([fdo#112271]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-byt-n2820/igt@gem_exec_paral...@contexts.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-byt-n2820/igt@gem_exec_paral...@contexts.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [FAIL][17] ([i915#217]) -> [DMESG-WARN][18] ([IGT#4] / [i915#263]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217 [i915#263]: https://gitlab.freedesktop.org/drm/intel/issues/263 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694 [i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 [i915#889]: https://gitlab.freedesktop.org/drm/intel/issues/889 Participating hosts (47 -> 42) -- Additional (1): fi-skl-6600u Missing(6): fi-hsw-4200u fi-bdw-gvtdvm fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7811 -> Patchwork_16267 CI-20190529: 20190529 CI_DRM_7811: f528982f5c837f075e82ca544df010ca5183064a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5384: fd6896567f7d612c76207970376d4f1e634ded55 @ git://anongit.freedesktop.org/xorg/app/intel-
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt conversion to new drm logging macros.
== Series Details == Series: drm/i915/gt conversion to new drm logging macros. URL : https://patchwork.freedesktop.org/series/72643/ State : success == Summary == CI Bug Log - changes from CI_DRM_7827 -> Patchwork_16290 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/index.html Known issues Here are the changes found in Patchwork_16290 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([i915#45]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_gem_contexts: - fi-cfl-guc: [PASS][3] -> [DMESG-FAIL][4] ([i915#623]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html Possible fixes * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][5] ([i915#553] / [i915#725]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-hsw-4770/igt@i915_selftest@live_blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_hangcheck: - fi-icl-u3: [INCOMPLETE][7] ([fdo#108569] / [i915#140]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140 [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#623]: https://gitlab.freedesktop.org/drm/intel/issues/623 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 Participating hosts (46 -> 39) -- Additional (5): fi-bsw-n3050 fi-gdg-551 fi-cfl-8109u fi-ivb-3770 fi-skl-6600u Missing(12): fi-ilk-m540 fi-bdw-samus fi-byt-squawks fi-bsw-cyan fi-ilk-650 fi-ctg-p8600 fi-whl-u fi-kbl-7560u fi-byt-n2820 fi-byt-clapper fi-skl-6700k2 fi-snb-2600 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7827 -> Patchwork_16290 CI-20190529: 20190529 CI_DRM_7827: c8969aeacfff681c83a800e82b0f18a6ab3e77ea @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5389: 966c58649dee31bb5bf2fad92f75ffd365968b81 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16290: 5b110e05162bff7e512f9a4f8133c5d3b1a315c5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5b110e05162b drm/i915/rps: move to new drm logging macros in gt/intel_rps.c 28139438c616 drm/i915/ring: convert to new logging macros in gt/intel_ring_submission.c d9d8777b20a6 drm/i915/gt: convert to new logging macros in gt/intel_gt.c 5ed3964d97b2 drm/i915/lrc: conversion to new drm logging macros in gt/intel_lrc.c cf7f41aa28b5 drm/i915/engine_cs: use new drm logging macros in gt/intel_engine_cs.c b7d1e0802827 drm/i915/reset: conversion to new drm logging macros in gt/intel_reset.c 52132978d32c drm/i915/ggtt: use new drm logging macros in gt/intel_ggtt.c 31cfe64d2d7f drm/i915/gt: conversion to struct drm_device macros when struct drm_i915_private is available. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Introduce CAP_PERFMON to secure system performance monitoring and observability (rev2)
== Series Details == Series: Introduce CAP_PERFMON to secure system performance monitoring and observability (rev2) URL : https://patchwork.freedesktop.org/series/72273/ State : success == Summary == CI Bug Log - changes from CI_DRM_7827 -> Patchwork_16289 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16289/index.html Known issues Here are the changes found in Patchwork_16289 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_gt_heartbeat: - fi-bsw-kefka: [PASS][1] -> [DMESG-FAIL][2] ([i915#541]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-bsw-kefka/igt@i915_selftest@live_gt_heartbeat.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16289/fi-bsw-kefka/igt@i915_selftest@live_gt_heartbeat.html * igt@kms_addfb_basic@bad-pitch-256: - fi-icl-dsi: [PASS][3] -> [DMESG-WARN][4] ([i915#109]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-icl-dsi/igt@kms_addfb_ba...@bad-pitch-256.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16289/fi-icl-dsi/igt@kms_addfb_ba...@bad-pitch-256.html Possible fixes * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][5] ([i915#553] / [i915#725]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-hsw-4770/igt@i915_selftest@live_blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16289/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_hangcheck: - fi-icl-u3: [INCOMPLETE][7] ([fdo#108569] / [i915#140]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16289/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109 [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140 [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 Participating hosts (46 -> 42) -- Additional (5): fi-bsw-n3050 fi-gdg-551 fi-cfl-8109u fi-ivb-3770 fi-skl-6600u Missing(9): fi-ilk-m540 fi-kbl-7560u fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-ctg-p8600 fi-blb-e6850 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7827 -> Patchwork_16289 CI-20190529: 20190529 CI_DRM_7827: c8969aeacfff681c83a800e82b0f18a6ab3e77ea @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5389: 966c58649dee31bb5bf2fad92f75ffd365968b81 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16289: e309daf4690565507b1fe7244ed41217b057ab0f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e309daf46905 drivers/oprofile: open access for CAP_PERFMON privileged process d4bca6e41e7d drivers/perf: open access for CAP_PERFMON privileged process 80510aa6fcc1 parisc/perf: open access for CAP_PERFMON privileged process 346f1feb325c powerpc/perf: open access for CAP_PERFMON privileged process 1ec452341389 trace/bpf_trace: open access for CAP_PERFMON privileged process 0ded358c0c9a drm/i915/perf: open access for CAP_PERFMON privileged process e16c0ae49641 perf tool: extend Perf tool with CAP_PERFMON capability support 67949e980fe0 perf/core: open access to probes for CAP_PERFMON privileged process 2b6eefdcee3f perf/core: open access to the core for CAP_PERFMON privileged process 00180af79ca9 capabilities: introduce CAP_PERFMON to kernel and user space == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16289/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/8] drm/i915/ggtt: use new drm logging macros in gt/intel_ggtt.c
Manual conversion of the printk based logging macros to the new struct
drm_based logging macros in drm/i915/gt/intel_ggtt.c.
Also includes extracting the struct drm_i915_private device from various
intel types to use in the new macros.
Signed-off-by: Wambui Karuga
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index d938cf8db460..09f4aa37bf2d 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -472,7 +472,8 @@ static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt)
GUC_GGTT_TOP, I915_COLOR_UNEVICTABLE,
PIN_NOEVICT);
if (ret)
- DRM_DEBUG_DRIVER("Failed to reserve top of GGTT for GuC\n");
+ drm_dbg(&ggtt->vm.i915->drm,
+ "Failed to reserve top of GGTT for GuC\n");
return ret;
}
@@ -544,8 +545,9 @@ static int init_ggtt(struct i915_ggtt *ggtt)
/* Clear any non-preallocated blocks */
drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
- DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
- hole_start, hole_end);
+ drm_dbg_kms(&ggtt->vm.i915->drm,
+ "clearing unused GTT space: [%lx, %lx]\n",
+ hole_start, hole_end);
ggtt->vm.clear_range(&ggtt->vm, hole_start,
hole_end - hole_start);
}
@@ -1273,6 +1275,7 @@ intel_rotate_pages(struct intel_rotation_info *rot_info,
struct drm_i915_gem_object *obj)
{
unsigned int size = intel_rotation_info_size(rot_info);
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
struct sg_table *st;
struct scatterlist *sg;
int ret = -ENOMEM;
@@ -1302,8 +1305,9 @@ intel_rotate_pages(struct intel_rotation_info *rot_info,
kfree(st);
err_st_alloc:
- DRM_DEBUG_DRIVER("Failed to create rotated mapping for object size %zu!
(%ux%u tiles, %u pages)\n",
-obj->base.size, rot_info->plane[0].width,
rot_info->plane[0].height, size);
+ drm_dbg(&i915->drm, "Failed to create rotated mapping for object size
%zu! (%ux%u tiles, %u pages)\n",
+ obj->base.size, rot_info->plane[0].width,
+ rot_info->plane[0].height, size);
return ERR_PTR(ret);
}
@@ -1355,6 +1359,7 @@ intel_remap_pages(struct intel_remapped_info *rem_info,
struct drm_i915_gem_object *obj)
{
unsigned int size = intel_remapped_info_size(rem_info);
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
struct sg_table *st;
struct scatterlist *sg;
int ret = -ENOMEM;
@@ -1386,8 +1391,9 @@ intel_remap_pages(struct intel_remapped_info *rem_info,
kfree(st);
err_st_alloc:
- DRM_DEBUG_DRIVER("Failed to create remapped mapping for object size
%zu! (%ux%u tiles, %u pages)\n",
-obj->base.size, rem_info->plane[0].width,
rem_info->plane[0].height, size);
+ drm_dbg(&i915->drm, "Failed to create remapped mapping for object size
%zu! (%ux%u tiles, %u pages)\n",
+ obj->base.size, rem_info->plane[0].width,
+ rem_info->plane[0].height, size);
return ERR_PTR(ret);
}
@@ -1485,8 +1491,9 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma)
if (IS_ERR(vma->pages)) {
ret = PTR_ERR(vma->pages);
vma->pages = NULL;
- DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
- vma->ggtt_view.type, ret);
+ drm_err(&vma->vm->i915->drm,
+ "Failed to get pages for VMA view type %u (%d)!\n",
+ vma->ggtt_view.type, ret);
}
return ret;
}
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 8/8] drm/i915/rps: move to new drm logging macros in gt/intel_rps.c
Convert various instances of the printk based drm logging macros to the
new struct drm_device based logging macros in i915/gt/intel_rps.c.
Signed-off-by: Wambui Karuga
---
drivers/gpu/drm/i915/gt/intel_rps.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 54e63435ccfe..9771d5f64b94 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -306,7 +306,7 @@ static bool gen5_rps_set(struct intel_rps *rps, u8 val)
rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
if (rgvswctl & MEMCTL_CMD_STS) {
- DRM_DEBUG("gpu busy, RCS change rejected\n");
+ drm_dbg(&uncore->i915->drm, "gpu busy, RCS change rejected\n");
return false; /* still busy with another command */
}
@@ -450,7 +450,8 @@ static bool gen5_rps_enable(struct intel_rps *rps)
if (wait_for_atomic((intel_uncore_read(uncore, MEMSWCTL) &
MEMCTL_CMD_STS) == 0, 10))
- DRM_ERROR("stuck trying to change perf mode\n");
+ drm_err(&uncore->i915->drm,
+ "stuck trying to change perf mode\n");
mdelay(1);
gen5_rps_set(rps, rps->cur_freq);
@@ -873,12 +874,13 @@ static void gen6_rps_init(struct intel_rps *rps)
static bool rps_reset(struct intel_rps *rps)
{
+ struct drm_i915_private *i915 = rps_to_i915(rps);
/* force a reset */
rps->power.mode = -1;
rps->last_freq = -1;
if (rps_set(rps, rps->min_freq, true)) {
- DRM_ERROR("Failed to reset RPS to initial values\n");
+ drm_err(&i915->drm, "Failed to reset RPS to initial values\n");
return false;
}
@@ -1441,6 +1443,7 @@ static void rps_work(struct work_struct *work)
{
struct intel_rps *rps = container_of(work, typeof(*rps), work);
struct intel_gt *gt = rps_to_gt(rps);
+ struct drm_i915_private *i915 = rps_to_i915(rps);
bool client_boost = false;
int new_freq, adj, min, max;
u32 pm_iir = 0;
@@ -1516,7 +1519,7 @@ static void rps_work(struct work_struct *work)
new_freq = clamp_t(int, new_freq, min, max);
if (intel_rps_set(rps, new_freq)) {
- DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n");
+ drm_dbg(&i915->drm, "Failed to set new GPU frequency\n");
rps->last_adj = 0;
}
@@ -1547,6 +1550,7 @@ void gen11_rps_irq_handler(struct intel_rps *rps, u32
pm_iir)
void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
{
struct intel_gt *gt = rps_to_gt(rps);
+ struct drm_i915_private *i915 = rps_to_i915(rps);
if (pm_iir & rps->pm_events) {
spin_lock(>->irq_lock);
@@ -1563,7 +1567,8 @@ void gen6_rps_irq_handler(struct intel_rps *rps, u32
pm_iir)
intel_engine_signal_breadcrumbs(gt->engine[VECS0]);
if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
- DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
+ drm_dbg(&i915->drm,
+ "Command parser error, pm_iir 0x%08x\n", pm_iir);
}
void gen5_rps_irq_handler(struct intel_rps *rps)
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/8] drm/i915/reset: conversion to new drm logging macros in gt/intel_reset.c
This converts most instances of the printk based drm logging macros in
i915/gt/intel_resect.c to the new struct drm_based logging macros.
Signed-off-by: Wambui Karuga
---
drivers/gpu/drm/i915/gt/intel_reset.c | 48 +++
1 file changed, 26 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index beee0cf89bce..df8240324714 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -72,9 +72,10 @@ static void client_mark_guilty(struct i915_gem_context *ctx,
bool banned)
if (score) {
atomic_add(score, &file_priv->ban_score);
- DRM_DEBUG_DRIVER("client %s: gained %u ban score, now %u\n",
-ctx->name, score,
-atomic_read(&file_priv->ban_score));
+ drm_dbg(&ctx->i915->drm,
+ "client %s: gained %u ban score, now %u\n",
+ ctx->name, score,
+ atomic_read(&file_priv->ban_score));
}
}
@@ -122,8 +123,8 @@ static bool mark_guilty(struct i915_request *rq)
if (time_before(jiffies, prev_hang + CONTEXT_FAST_HANG_JIFFIES))
banned = true;
if (banned) {
- DRM_DEBUG_DRIVER("context %s: guilty %d, banned\n",
-ctx->name, atomic_read(&ctx->guilty_count));
+ drm_dbg(&ctx->i915->drm, "context %s: guilty %d, banned\n",
+ ctx->name, atomic_read(&ctx->guilty_count));
intel_context_set_banned(rq->context);
}
@@ -226,7 +227,7 @@ static int g4x_do_reset(struct intel_gt *gt,
GRDOM_MEDIA | GRDOM_RESET_ENABLE);
ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
if (ret) {
- DRM_DEBUG_DRIVER("Wait for media reset failed\n");
+ drm_dbg(>->i915->drm, "Wait for media reset failed\n");
goto out;
}
@@ -234,7 +235,7 @@ static int g4x_do_reset(struct intel_gt *gt,
GRDOM_RENDER | GRDOM_RESET_ENABLE);
ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
if (ret) {
- DRM_DEBUG_DRIVER("Wait for render reset failed\n");
+ drm_dbg(>->i915->drm, "Wait for render reset failed\n");
goto out;
}
@@ -260,7 +261,7 @@ static int ilk_do_reset(struct intel_gt *gt,
intel_engine_mask_t engine_mask,
5000, 0,
NULL);
if (ret) {
- DRM_DEBUG_DRIVER("Wait for render reset failed\n");
+ drm_dbg(>->i915->drm, "Wait for render reset failed\n");
goto out;
}
@@ -271,7 +272,7 @@ static int ilk_do_reset(struct intel_gt *gt,
intel_engine_mask_t engine_mask,
5000, 0,
NULL);
if (ret) {
- DRM_DEBUG_DRIVER("Wait for media reset failed\n");
+ drm_dbg(>->i915->drm, "Wait for media reset failed\n");
goto out;
}
@@ -300,8 +301,9 @@ static int gen6_hw_domain_reset(struct intel_gt *gt, u32
hw_domain_mask)
500, 0,
NULL);
if (err)
- DRM_DEBUG_DRIVER("Wait for 0x%08x engines reset failed\n",
-hw_domain_mask);
+ drm_dbg(>->i915->drm,
+ "Wait for 0x%08x engines reset failed\n",
+ hw_domain_mask);
return err;
}
@@ -401,7 +403,8 @@ static int gen11_lock_sfc(struct intel_engine_cs *engine,
u32 *hw_mask)
return 0;
if (ret) {
- DRM_DEBUG_DRIVER("Wait for SFC forced lock ack failed\n");
+ drm_dbg(&engine->i915->drm,
+ "Wait for SFC forced lock ack failed\n");
return ret;
}
@@ -515,9 +518,10 @@ static int gen8_engine_reset_prepare(struct
intel_engine_cs *engine)
ret = __intel_wait_for_register_fw(uncore, reg, mask, ack,
700, 0, NULL);
if (ret)
- DRM_ERROR("%s reset request timed out: {request: %08x,
RESET_CTL: %08x}\n",
- engine->name, request,
- intel_uncore_read_fw(uncore, reg));
+ drm_err(&engine->i915->drm,
+ "%s reset request timed out: {request: %08x, RESET_CTL:
%08x}\n",
+ engine->name, request,
+ intel_uncore_read_fw(uncore, reg));
return ret;
}
@@ -1022,7 +1026,7 @@ void intel_gt_reset(struct intel_gt *gt,
if (i915_modparams.reset)
dev_err(gt->i915->drm.dev, "GPU reset not support
[Intel-gfx] [PATCH 6/8] drm/i915/gt: convert to new logging macros in gt/intel_gt.c
Convert remaining instances of the printk based logging macros in
i915/gt/intel_gt to the struct drm_device based logging macros.
Signed-off-by: Wambui Karuga
---
drivers/gpu/drm/i915/gt/intel_gt.c | 43 +++---
1 file changed, 21 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index a1ba0097117e..448afdcf40ab 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -198,16 +198,16 @@ static void gen6_check_faults(struct intel_gt *gt)
for_each_engine(engine, gt, id) {
fault = GEN6_RING_FAULT_REG_READ(engine);
if (fault & RING_FAULT_VALID) {
- DRM_DEBUG_DRIVER("Unexpected fault\n"
-"\tAddr: 0x%08lx\n"
-"\tAddress space: %s\n"
-"\tSource ID: %d\n"
-"\tType: %d\n",
-fault & PAGE_MASK,
-fault & RING_FAULT_GTTSEL_MASK ?
-"GGTT" : "PPGTT",
-RING_FAULT_SRCID(fault),
-RING_FAULT_FAULT_TYPE(fault));
+ drm_dbg(&engine->i915->drm, "Unexpected fault\n"
+ "\tAddr: 0x%08lx\n"
+ "\tAddress space: %s\n"
+ "\tSource ID: %d\n"
+ "\tType: %d\n",
+ fault & PAGE_MASK,
+ fault & RING_FAULT_GTTSEL_MASK ?
+ "GGTT" : "PPGTT",
+ RING_FAULT_SRCID(fault),
+ RING_FAULT_FAULT_TYPE(fault));
}
}
}
@@ -239,18 +239,17 @@ static void gen8_check_faults(struct intel_gt *gt)
fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
((u64)fault_data0 << 12);
- DRM_DEBUG_DRIVER("Unexpected fault\n"
-"\tAddr: 0x%08x_%08x\n"
-"\tAddress space: %s\n"
-"\tEngine ID: %d\n"
-"\tSource ID: %d\n"
-"\tType: %d\n",
-upper_32_bits(fault_addr),
-lower_32_bits(fault_addr),
-fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
-GEN8_RING_FAULT_ENGINE_ID(fault),
-RING_FAULT_SRCID(fault),
-RING_FAULT_FAULT_TYPE(fault));
+ drm_dbg(&uncore->i915->drm, "Unexpected fault\n"
+ "\tAddr: 0x%08x_%08x\n"
+ "\tAddress space: %s\n"
+ "\tEngine ID: %d\n"
+ "\tSource ID: %d\n"
+ "\tType: %d\n",
+ upper_32_bits(fault_addr), lower_32_bits(fault_addr),
+ fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
+ GEN8_RING_FAULT_ENGINE_ID(fault),
+ RING_FAULT_SRCID(fault),
+ RING_FAULT_FAULT_TYPE(fault));
}
}
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 7/8] drm/i915/ring: convert to new logging macros in gt/intel_ring_submission.c
Manually convert the remaining instance of the printk based drm logging
macros to the struct drm_device based logging macros in
i915/gt/intel_ring_submission.c
Signed-off-by: Wambui Karuga
---
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 964a8d8d28b5..0f2e8a010794 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -1666,7 +1666,8 @@ static void gen6_bsd_submit_request(struct i915_request
*request)
GEN6_BSD_SLEEP_INDICATOR,
0,
1000, 0, NULL))
- DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
+ drm_err(&uncore->i915->drm,
+ "timed out waiting for the BSD ring to wake up\n");
/* Now that the ring is fully powered up, update the tail */
i9xx_submit_request(request);
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/8] drm/i915/engine_cs: use new drm logging macros in gt/intel_engine_cs.c
Conversion of the remaining printk based drm logging macros to the new
struct drm_device based logging macros in i915/gt/intel_engine_cs.c.
Signed-off-by: Wambui Karuga
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 084abc577b14..b9511e045eee 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -200,10 +200,10 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8
class)
* out in the wash.
*/
cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
- DRM_DEBUG_DRIVER("gen%d CXT_SIZE = %d bytes [0x%08x]\n",
-INTEL_GEN(gt->i915),
-cxt_size * 64,
-cxt_size - 1);
+ drm_dbg(>->i915->drm,
+ "gen%d CXT_SIZE = %d bytes [0x%08x]\n",
+ INTEL_GEN(gt->i915), cxt_size * 64,
+ cxt_size - 1);
return round_up(cxt_size * 64, PAGE_SIZE);
case 3:
case 2:
@@ -562,7 +562,8 @@ static int init_status_page(struct intel_engine_cs *engine)
*/
obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
if (IS_ERR(obj)) {
- DRM_ERROR("Failed to allocate status page\n");
+ drm_err(&engine->i915->drm,
+ "Failed to allocate status page\n");
return PTR_ERR(obj);
}
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/8] drm/i915/lrc: conversion to new drm logging macros in gt/intel_lrc.c
Converts most instances of the printk based drm logging macros in
i915/gt/intel_lrc.c to the new struct drm_device based logging macros.
In some instances, extracts the struct drm_i915_private device for use
in the logging macros.
Signed-off-by: Wambui Karuga
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 5003c2e84786..57bd77120b5f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3310,7 +3310,8 @@ static int intel_init_workaround_bb(struct
intel_engine_cs *engine)
ret = lrc_setup_wa_ctx(engine);
if (ret) {
- DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
+ drm_dbg(&engine->i915->drm,
+ "Failed to setup context WA page: %d\n", ret);
return ret;
}
@@ -3372,7 +3373,8 @@ static bool unexpected_starting_state(struct
intel_engine_cs *engine)
bool unexpected = false;
if (ENGINE_READ_FW(engine, RING_MI_MODE) & STOP_RING) {
- DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
+ drm_dbg(&engine->i915->drm,
+ "STOP_RING still set in RING_MI_MODE\n");
unexpected = true;
}
@@ -4502,6 +4504,7 @@ populate_lr_context(struct intel_context *ce,
struct intel_engine_cs *engine,
struct intel_ring *ring)
{
+ struct drm_i915_private *i915 = to_i915(ctx_obj->base.dev);
bool inhibit = true;
void *vaddr;
int ret;
@@ -4509,7 +4512,7 @@ populate_lr_context(struct intel_context *ce,
vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
if (IS_ERR(vaddr)) {
ret = PTR_ERR(vaddr);
- DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
+ drm_dbg(&i915->drm, "Could not map object pages! (%d)\n", ret);
return ret;
}
@@ -4588,7 +4591,8 @@ static int __execlists_context_alloc(struct intel_context
*ce,
ret = populate_lr_context(ce, ctx_obj, engine, ring);
if (ret) {
- DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
+ drm_dbg(&engine->i915->drm,
+ "Failed to populate LRC: %d\n", ret);
goto error_ring_free;
}
@@ -4975,8 +4979,9 @@ intel_execlists_create_virtual(struct intel_engine_cs
**siblings,
GEM_BUG_ON(!is_power_of_2(sibling->mask));
if (sibling->mask & ve->base.mask) {
- DRM_DEBUG("duplicate %s entry in load balancer\n",
- sibling->name);
+ drm_dbg(&sibling->i915->drm,
+ "duplicate %s entry in load balancer\n",
+ sibling->name);
err = -EINVAL;
goto err_put;
}
@@ -5009,8 +5014,9 @@ intel_execlists_create_virtual(struct intel_engine_cs
**siblings,
*/
if (ve->base.class != OTHER_CLASS) {
if (ve->base.class != sibling->class) {
- DRM_DEBUG("invalid mixing of engine class,
sibling %d, already %d\n",
- sibling->class, ve->base.class);
+ drm_dbg(&sibling->i915->drm,
+ "invalid mixing of engine class,
sibling %d, already %d\n",
+ sibling->class, ve->base.class);
err = -EINVAL;
goto err_put;
}
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/8] drm/i915/gt conversion to new drm logging macros.
This series continues the conversion to the new drm logging macros focused on the drm/i915/gt folder. This was done both manually and using coccinelle. Wambui Karuga (8): drm/i915/gt: conversion to struct drm_device macros when struct drm_i915_private is available. drm/i915/ggtt: use new drm logging macros in gt/intel_ggtt.c drm/i915/reset: conversion to new drm logging macros in gt/intel_reset.c drm/i915/engine_cs: use new drm logging macros in gt/intel_engine_cs.c drm/i915/lrc: conversion to new drm logging macros in gt/intel_lrc.c drm/i915/gt: convert to new logging macros in gt/intel_gt.c drm/i915/ring: convert to new logging macros in gt/intel_ring_submission.c drm/i915/rps: move to new drm logging macros in gt/intel_rps.c drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 +-- drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +- drivers/gpu/drm/i915/gt/intel_ggtt.c | 63 +-- drivers/gpu/drm/i915/gt/intel_gt.c| 49 ++- drivers/gpu/drm/i915/gt/intel_lrc.c | 24 +++--- drivers/gpu/drm/i915/gt/intel_rc6.c | 30 --- drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +- drivers/gpu/drm/i915/gt/intel_reset.c | 48 ++- .../gpu/drm/i915/gt/intel_ring_submission.c | 36 + drivers/gpu/drm/i915/gt/intel_rps.c | 81 +-- drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +- drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 3 +- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +- 13 files changed, 196 insertions(+), 164 deletions(-) -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/8] drm/i915/gt: conversion to struct drm_device macros when struct drm_i915_private is available.
This patch is the conversion of printk based logging macros to the new
struct drm_device based logging macros in the drm/i915/gt folder by
running the following coccinelle script that matches when the struct
drm_i915_private device is present:
@rule1@
identifier fn, T;
@@
fn(...,struct drm_i915_private *T,...) {
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
@rule2@
identifier fn, T;
@@
fn(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
Checkpatch warnings were fixed manually.
Signed-off-by: Wambui Karuga
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 38 ++-
drivers/gpu/drm/i915/gt/intel_gt.c| 6 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 30 +
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 33 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 66 +--
drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 3 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
11 files changed, 101 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c
b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 848decee9066..c8a63e9c8f0d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -215,7 +215,7 @@ void intel_engines_driver_register(struct drm_i915_private
*i915)
scnprintf(engine->name, sizeof(engine->name), "%s%u",
intel_engine_class_repr(engine->class),
engine->uabi_instance);
- DRM_DEBUG_DRIVER("renamed %s to %s\n", old, engine->name);
+ drm_dbg(&i915->drm, "renamed %s to %s\n", old, engine->name);
rb_link_node(&engine->uabi_node, prev, p);
rb_insert_color(&engine->uabi_node, &i915->uabi_engines);
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 79096722ce16..d938cf8db460 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -791,13 +791,13 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64
size)
else
ggtt->gsm = ioremap_wc(phys_addr, size);
if (!ggtt->gsm) {
- DRM_ERROR("Failed to map the ggtt page table\n");
+ drm_err(&i915->drm, "Failed to map the ggtt page table\n");
return -ENOMEM;
}
ret = setup_scratch_page(&ggtt->vm, GFP_DMA32);
if (ret) {
- DRM_ERROR("Scratch setup failed\n");
+ drm_err(&i915->drm, "Scratch setup failed\n");
/* iounmap will also get called at remove, but meh */
iounmap(ggtt->gsm);
return ret;
@@ -857,7 +857,8 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
if (!err)
err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39));
if (err)
- DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err);
+ drm_err(&i915->drm,
+ "Can't set DMA mask/consistent mask (%d)\n", err);
pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
if (IS_CHERRYVIEW(i915))
@@ -1004,7 +1005,8 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
* just a coarse sanity check.
*/
if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) {
- DRM_ERROR("Unknown GMADR size (%pa)\n", &ggtt->mappable_end);
+ drm_err(&i915->drm, "Unknown GMADR size (%pa)\n",
+ &ggtt->mappable_end);
return -ENXIO;
}
@@ -1012,7 +1014,8 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
if (!err)
err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40));
if (err)
- DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err);
+ drm_err(&i915->drm,
+ "Can't set DMA mask/consistent mask (%d)\n", err);
pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
size = gen6_get_total_gtt_size(snb_gmch_ctl);
@@ -1059,7 +1062,7 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
ret = intel_gmch_probe(
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce CAP_PERFMON to secure system performance monitoring and observability (rev2)
== Series Details == Series: Introduce CAP_PERFMON to secure system performance monitoring and observability (rev2) URL : https://patchwork.freedesktop.org/series/72273/ State : warning == Summary == $ dim checkpatch origin/drm-tip 00180af79ca9 capabilities: introduce CAP_PERFMON to kernel and user space -:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #13: is available to a CAP_SYS_ADMIN privileged process [2]. Providing the access total: 0 errors, 1 warnings, 0 checks, 36 lines checked 2b6eefdcee3f perf/core: open access to the core for CAP_PERFMON privileged process -:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #9: CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, total: 0 errors, 1 warnings, 0 checks, 32 lines checked 67949e980fe0 perf/core: open access to probes for CAP_PERFMON privileged process -:18: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #18: monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle total: 0 errors, 1 warnings, 0 checks, 16 lines checked e16c0ae49641 perf tool: extend Perf tool with CAP_PERFMON capability support -:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #13: monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle total: 0 errors, 1 warnings, 0 checks, 56 lines checked 0ded358c0c9a drm/i915/perf: open access for CAP_PERFMON privileged process -:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #12: monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle total: 0 errors, 1 warnings, 0 checks, 39 lines checked 1ec452341389 trace/bpf_trace: open access for CAP_PERFMON privileged process -:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #13: monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle total: 0 errors, 1 warnings, 0 checks, 8 lines checked 346f1feb325c powerpc/perf: open access for CAP_PERFMON privileged process -:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #12: monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle total: 0 errors, 1 warnings, 0 checks, 16 lines checked 80510aa6fcc1 parisc/perf: open access for CAP_PERFMON privileged process -:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #12: monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle total: 0 errors, 1 warnings, 0 checks, 8 lines checked d4bca6e41e7d drivers/perf: open access for CAP_PERFMON privileged process -:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #12: monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle total: 0 errors, 1 warnings, 0 checks, 16 lines checked e309daf46905 drivers/oprofile: open access for CAP_PERFMON privileged process -:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #13: monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle total: 0 errors, 1 warnings, 0 checks, 8 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 09/10] drivers/perf: open access for CAP_PERFMON privileged process
Open access to monitoring for CAP_PERFMON privileged process. Providing the access under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes operation more secure. CAP_PERFMON implements the principal of least privilege for performance monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle of least privilege: A security design principle that states that a process or program be granted only those privileges (e.g., capabilities) necessary to accomplish its legitimate function, and only for the time that such privileges are actually required) For backward compatibility reasons access to the monitoring remains open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage for secure monitoring is discouraged with respect to CAP_PERFMON capability. Signed-off-by: Alexey Budankov --- drivers/perf/arm_spe_pmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 4e4984a55cd1..5dff81bc3324 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -274,7 +274,7 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *event) if (!attr->exclude_kernel) reg |= BIT(SYS_PMSCR_EL1_E1SPE_SHIFT); - if (IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR) && capable(CAP_SYS_ADMIN)) + if (IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR) && perfmon_capable()) reg |= BIT(SYS_PMSCR_EL1_CX_SHIFT); return reg; @@ -700,7 +700,7 @@ static int arm_spe_pmu_event_init(struct perf_event *event) return -EOPNOTSUPP; reg = arm_spe_event_to_pmscr(event); - if (!capable(CAP_SYS_ADMIN) && + if (!perfmon_capable() && (reg & (BIT(SYS_PMSCR_EL1_PA_SHIFT) | BIT(SYS_PMSCR_EL1_CX_SHIFT) | BIT(SYS_PMSCR_EL1_PCT_SHIFT -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 10/10] drivers/oprofile: open access for CAP_PERFMON privileged process
Open access to monitoring for CAP_PERFMON privileged process. Providing
the access under CAP_PERFMON capability singly, without the rest of
CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and
makes operation more secure.
CAP_PERFMON implements the principal of least privilege for performance
monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle
of least privilege: A security design principle that states that a process
or program be granted only those privileges (e.g., capabilities) necessary
to accomplish its legitimate function, and only for the time that such
privileges are actually required)
For backward compatibility reasons access to the monitoring remains open
for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage for secure
monitoring is discouraged with respect to CAP_PERFMON capability.
Signed-off-by: Alexey Budankov
---
drivers/oprofile/event_buffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/oprofile/event_buffer.c b/drivers/oprofile/event_buffer.c
index 12ea4a4ad607..6c9edc8bbc95 100644
--- a/drivers/oprofile/event_buffer.c
+++ b/drivers/oprofile/event_buffer.c
@@ -113,7 +113,7 @@ static int event_buffer_open(struct inode *inode, struct
file *file)
{
int err = -EPERM;
- if (!capable(CAP_SYS_ADMIN))
+ if (!perfmon_capable())
return -EPERM;
if (test_and_set_bit_lock(0, &buffer_opened))
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 08/10] parisc/perf: open access for CAP_PERFMON privileged process
Open access to monitoring for CAP_PERFMON privileged process. Providing the access under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes operation more secure. CAP_PERFMON implements the principal of least privilege for performance monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle of least privilege: A security design principle that states that a process or program be granted only those privileges (e.g., capabilities) necessary to accomplish its legitimate function, and only for the time that such privileges are actually required) For backward compatibility reasons access to the monitoring remains open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage for secure monitoring is discouraged with respect to CAP_PERFMON capability. Signed-off-by: Alexey Budankov --- arch/parisc/kernel/perf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/parisc/kernel/perf.c b/arch/parisc/kernel/perf.c index 676683641d00..c4208d027794 100644 --- a/arch/parisc/kernel/perf.c +++ b/arch/parisc/kernel/perf.c @@ -300,7 +300,7 @@ static ssize_t perf_write(struct file *file, const char __user *buf, else return -EFAULT; - if (!capable(CAP_SYS_ADMIN)) + if (!perfmon_capable()) return -EACCES; if (count != sizeof(uint32_t)) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 07/10] powerpc/perf: open access for CAP_PERFMON privileged process
Open access to monitoring for CAP_PERFMON privileged process. Providing the access under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes operation more secure. CAP_PERFMON implements the principal of least privilege for performance monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle of least privilege: A security design principle that states that a process or program be granted only those privileges (e.g., capabilities) necessary to accomplish its legitimate function, and only for the time that such privileges are actually required) For backward compatibility reasons access to the monitoring remains open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage for secure monitoring is discouraged with respect to CAP_PERFMON capability. Signed-off-by: Alexey Budankov --- arch/powerpc/perf/imc-pmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c index cb50a9e1fd2d..e837717492e4 100644 --- a/arch/powerpc/perf/imc-pmu.c +++ b/arch/powerpc/perf/imc-pmu.c @@ -898,7 +898,7 @@ static int thread_imc_event_init(struct perf_event *event) if (event->attr.type != event->pmu->type) return -ENOENT; - if (!capable(CAP_SYS_ADMIN)) + if (!perfmon_capable()) return -EACCES; /* Sampling not supported */ @@ -1307,7 +1307,7 @@ static int trace_imc_event_init(struct perf_event *event) if (event->attr.type != event->pmu->type) return -ENOENT; - if (!capable(CAP_SYS_ADMIN)) + if (!perfmon_capable()) return -EACCES; /* Return if this is a couting event */ -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 06/10] trace/bpf_trace: open access for CAP_PERFMON privileged process
Open access to bpf_trace monitoring for CAP_PERFMON privileged process. Providing the access under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes operation more secure. CAP_PERFMON implements the principal of least privilege for performance monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle of least privilege: A security design principle that states that a process or program be granted only those privileges (e.g., capabilities) necessary to accomplish its legitimate function, and only for the time that such privileges are actually required) For backward compatibility reasons access to bpf_trace monitoring remains open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage for secure bpf_trace monitoring is discouraged with respect to CAP_PERFMON capability. Signed-off-by: Alexey Budankov --- kernel/trace/bpf_trace.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c index e5ef4ae9edb5..334f1d71ebb1 100644 --- a/kernel/trace/bpf_trace.c +++ b/kernel/trace/bpf_trace.c @@ -1395,7 +1395,7 @@ int perf_event_query_prog_array(struct perf_event *event, void __user *info) u32 *ids, prog_cnt, ids_len; int ret; - if (!capable(CAP_SYS_ADMIN)) + if (!perfmon_capable()) return -EPERM; if (event->attr.type != PERF_TYPE_TRACEPOINT) return -EINVAL; -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 05/10] drm/i915/perf: open access for CAP_PERFMON privileged process
Open access to i915_perf monitoring for CAP_PERFMON privileged process.
Providing the access under CAP_PERFMON capability singly, without the
rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the
credentials and makes operation more secure.
CAP_PERFMON implements the principal of least privilege for performance
monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle
of least privilege: A security design principle that states that a process
or program be granted only those privileges (e.g., capabilities) necessary
to accomplish its legitimate function, and only for the time that such
privileges are actually required)
For backward compatibility reasons access to i915_events subsystem remains
open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage for
secure i915_events monitoring is discouraged with respect to CAP_PERFMON
capability.
Signed-off-by: Alexey Budankov
---
drivers/gpu/drm/i915/i915_perf.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2ae14bc14931..d89347861b7d 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3375,10 +3375,10 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
/* Similar to perf's kernel.perf_paranoid_cpu sysctl option
* we check a dev.i915.perf_stream_paranoid sysctl option
* to determine if it's ok to access system wide OA counters
-* without CAP_SYS_ADMIN privileges.
+* without CAP_PERFMON or CAP_SYS_ADMIN privileges.
*/
if (privileged_op &&
- i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) {
+ i915_perf_stream_paranoid && !perfmon_capable()) {
DRM_DEBUG("Insufficient privileges to open i915 perf stream\n");
ret = -EACCES;
goto err_ctx;
@@ -3571,9 +3571,8 @@ static int read_properties_unlocked(struct i915_perf
*perf,
} else
oa_freq_hz = 0;
- if (oa_freq_hz > i915_oa_max_sample_rate &&
- !capable(CAP_SYS_ADMIN)) {
- DRM_DEBUG("OA exponent would exceed the max
sampling frequency (sysctl dev.i915.oa_max_sample_rate) %uHz without root
privileges\n",
+ if (oa_freq_hz > i915_oa_max_sample_rate &&
!perfmon_capable()) {
+ DRM_DEBUG("OA exponent would exceed the max
sampling frequency (sysctl dev.i915.oa_max_sample_rate) %uHz without
CAP_PERFMON or CAP_SYS_ADMIN privileges\n",
i915_oa_max_sample_rate);
return -EACCES;
}
@@ -3994,7 +3993,7 @@ int i915_perf_add_config_ioctl(struct drm_device *dev,
void *data,
return -EINVAL;
}
- if (i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) {
+ if (i915_perf_stream_paranoid && !perfmon_capable()) {
DRM_DEBUG("Insufficient privileges to add i915 OA config\n");
return -EACCES;
}
@@ -4141,7 +4140,7 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev,
void *data,
return -ENOTSUPP;
}
- if (i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) {
+ if (i915_perf_stream_paranoid && !perfmon_capable()) {
DRM_DEBUG("Insufficient privileges to remove i915 OA config\n");
return -EACCES;
}
--
2.20.1
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 04/10] perf tool: extend Perf tool with CAP_PERFMON capability support
Extend error messages to mention CAP_PERFMON capability as an option
to substitute CAP_SYS_ADMIN capability for secure system performance
monitoring and observability operations. Make perf_event_paranoid_check()
and __cmd_ftrace() to be aware of CAP_PERFMON capability.
CAP_PERFMON implements the principal of least privilege for performance
monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle
of least privilege: A security design principle that states that a process
or program be granted only those privileges (e.g., capabilities) necessary
to accomplish its legitimate function, and only for the time that such
privileges are actually required)
For backward compatibility reasons access to perf_events subsystem remains
open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage for
secure perf_events monitoring is discouraged with respect to CAP_PERFMON
capability.
Signed-off-by: Alexey Budankov
---
tools/perf/builtin-ftrace.c | 5 +++--
tools/perf/design.txt | 3 ++-
tools/perf/util/cap.h | 4
tools/perf/util/evsel.c | 10 +-
tools/perf/util/util.c | 1 +
5 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/tools/perf/builtin-ftrace.c b/tools/perf/builtin-ftrace.c
index d5adc417a4ca..55eda54240fb 100644
--- a/tools/perf/builtin-ftrace.c
+++ b/tools/perf/builtin-ftrace.c
@@ -284,10 +284,11 @@ static int __cmd_ftrace(struct perf_ftrace *ftrace, int
argc, const char **argv)
.events = POLLIN,
};
- if (!perf_cap__capable(CAP_SYS_ADMIN)) {
+ if (!(perf_cap__capable(CAP_PERFMON) ||
+ perf_cap__capable(CAP_SYS_ADMIN))) {
pr_err("ftrace only works for %s!\n",
#ifdef HAVE_LIBCAP_SUPPORT
- "users with the SYS_ADMIN capability"
+ "users with the CAP_PERFMON or CAP_SYS_ADMIN capability"
#else
"root"
#endif
diff --git a/tools/perf/design.txt b/tools/perf/design.txt
index 0453ba26cdbd..a42fab308ff6 100644
--- a/tools/perf/design.txt
+++ b/tools/perf/design.txt
@@ -258,7 +258,8 @@ gets schedule to. Per task counters can be created by any
user, for
their own tasks.
A 'pid == -1' and 'cpu == x' counter is a per CPU counter that counts
-all events on CPU-x. Per CPU counters need CAP_SYS_ADMIN privilege.
+all events on CPU-x. Per CPU counters need CAP_PERFMON or CAP_SYS_ADMIN
+privilege.
The 'flags' parameter is currently unused and must be zero.
diff --git a/tools/perf/util/cap.h b/tools/perf/util/cap.h
index 051dc590ceee..ae52878c0b2e 100644
--- a/tools/perf/util/cap.h
+++ b/tools/perf/util/cap.h
@@ -29,4 +29,8 @@ static inline bool perf_cap__capable(int cap __maybe_unused)
#define CAP_SYSLOG 34
#endif
+#ifndef CAP_PERFMON
+#define CAP_PERFMON38
+#endif
+
#endif /* __PERF_CAP_H */
diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
index a69e64236120..a35f17723dd3 100644
--- a/tools/perf/util/evsel.c
+++ b/tools/perf/util/evsel.c
@@ -2491,14 +2491,14 @@ int perf_evsel__open_strerror(struct evsel *evsel,
struct target *target,
"You may not have permission to collect %sstats.\n\n"
"Consider tweaking /proc/sys/kernel/perf_event_paranoid,\n"
"which controls use of the performance events system by\n"
-"unprivileged users (without CAP_SYS_ADMIN).\n\n"
+"unprivileged users (without CAP_PERFMON or
CAP_SYS_ADMIN).\n\n"
"The current value is %d:\n\n"
" -1: Allow use of (almost) all events by all users\n"
" Ignore mlock limit after perf_event_mlock_kb without
CAP_IPC_LOCK\n"
-">= 0: Disallow ftrace function tracepoint by users without
CAP_SYS_ADMIN\n"
-" Disallow raw tracepoint access by users without
CAP_SYS_ADMIN\n"
-">= 1: Disallow CPU event access by users without
CAP_SYS_ADMIN\n"
-">= 2: Disallow kernel profiling by users without
CAP_SYS_ADMIN\n\n"
+">= 0: Disallow ftrace function tracepoint by users without
CAP_PERFMON or CAP_SYS_ADMIN\n"
+" Disallow raw tracepoint access by users without
CAP_SYS_PERFMON or CAP_SYS_ADMIN\n"
+">= 1: Disallow CPU event access by users without CAP_PERFMON
or CAP_SYS_ADMIN\n"
+">= 2: Disallow kernel profiling by users without CAP_PERFMON
or CAP_SYS_ADMIN\n\n"
"To make this setting permanent, edit /etc/sysctl.conf too,
e.g.:\n\n"
" kernel.perf_event_paranoid = -1\n" ,
target->system_wide ? "system-wide " : "",
diff --git a/tools/perf/util/util.c b/tools/perf/util/util.c
index 969ae560dad9..51cf3071db74 100644
--- a/tools/perf/util/util.c
+++ b/tools/perf/util/util.c
@@ -272,6 +272,7 @@ int perf_event_paranoid(void)
bool perf_event_paranoid_check(int max_level)
{
return perf_cap__capable(CAP_SYS_ADMIN) ||
[Intel-gfx] [PATCH v6 03/10] perf/core: open access to probes for CAP_PERFMON privileged process
Open access to monitoring via kprobes and uprobes and eBPF tracing for CAP_PERFMON privileged process. Providing the access under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes operation more secure. perf kprobes and uprobes are used by ftrace and eBPF. perf probe uses ftrace to define new kprobe events, and those events are treated as tracepoint events. eBPF defines new probes via perf_event_open interface and then the probes are used in eBPF tracing. CAP_PERFMON implements the principal of least privilege for performance monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle of least privilege: A security design principle that states that a process or program be granted only those privileges (e.g., capabilities) necessary to accomplish its legitimate function, and only for the time that such privileges are actually required) For backward compatibility reasons access to perf_events subsystem remains open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage for secure perf_events monitoring is discouraged with respect to CAP_PERFMON capability. Signed-off-by: Alexey Budankov --- kernel/events/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/events/core.c b/kernel/events/core.c index d956c81bd310..c6453320ffea 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -9088,7 +9088,7 @@ static int perf_kprobe_event_init(struct perf_event *event) if (event->attr.type != perf_kprobe.type) return -ENOENT; - if (!capable(CAP_SYS_ADMIN)) + if (!perfmon_capable()) return -EACCES; /* @@ -9148,7 +9148,7 @@ static int perf_uprobe_event_init(struct perf_event *event) if (event->attr.type != perf_uprobe.type) return -ENOENT; - if (!capable(CAP_SYS_ADMIN)) + if (!perfmon_capable()) return -EACCES; /* -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 02/10] perf/core: open access to the core for CAP_PERFMON privileged process
Open access to monitoring of kernel code, cpus, tracepoints and namespaces
data for a CAP_PERFMON privileged process. Providing the access under
CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials,
excludes chances to misuse the credentials and makes operation more secure.
CAP_PERFMON implements the principal of least privilege for performance
monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle
of least privilege: A security design principle that states that a process or
program be granted only those privileges (e.g., capabilities) necessary to
accomplish its legitimate function, and only for the time that such privileges
are actually required)
For backward compatibility reasons access to perf_events subsystem remains
open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage for secure
perf_events monitoring is discouraged with respect to CAP_PERFMON capability.
Signed-off-by: Alexey Budankov
---
include/linux/perf_event.h | 6 +++---
kernel/events/core.c | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 6d4c22aee384..730469babcc2 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -1285,7 +1285,7 @@ static inline int perf_is_paranoid(void)
static inline int perf_allow_kernel(struct perf_event_attr *attr)
{
- if (sysctl_perf_event_paranoid > 1 && !capable(CAP_SYS_ADMIN))
+ if (sysctl_perf_event_paranoid > 1 && !perfmon_capable())
return -EACCES;
return security_perf_event_open(attr, PERF_SECURITY_KERNEL);
@@ -1293,7 +1293,7 @@ static inline int perf_allow_kernel(struct
perf_event_attr *attr)
static inline int perf_allow_cpu(struct perf_event_attr *attr)
{
- if (sysctl_perf_event_paranoid > 0 && !capable(CAP_SYS_ADMIN))
+ if (sysctl_perf_event_paranoid > 0 && !perfmon_capable())
return -EACCES;
return security_perf_event_open(attr, PERF_SECURITY_CPU);
@@ -1301,7 +1301,7 @@ static inline int perf_allow_cpu(struct perf_event_attr
*attr)
static inline int perf_allow_tracepoint(struct perf_event_attr *attr)
{
- if (sysctl_perf_event_paranoid > -1 && !capable(CAP_SYS_ADMIN))
+ if (sysctl_perf_event_paranoid > -1 && !perfmon_capable())
return -EPERM;
return security_perf_event_open(attr, PERF_SECURITY_TRACEPOINT);
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 2173c23c25b4..d956c81bd310 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -11186,7 +11186,7 @@ SYSCALL_DEFINE5(perf_event_open,
}
if (attr.namespaces) {
- if (!capable(CAP_SYS_ADMIN))
+ if (!perfmon_capable())
return -EACCES;
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 01/10] capabilities: introduce CAP_PERFMON to kernel and user space
Introduce CAP_PERFMON capability designed to secure system performance
monitoring and observability operations so that CAP_PERFMON would assist
CAP_SYS_ADMIN capability in its governing role for performance monitoring
and observability subsystems.
CAP_PERFMON hardens system security and integrity during system performance
monitoring and observability operations by decreasing attack surface that
is available to a CAP_SYS_ADMIN privileged process [2]. Providing the access
to system performance monitoring and observability operations under CAP_PERFMON
capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes
chances to misuse the credentials and makes the operation more secure.
Thus, CAP_PERFMON implements the principal of least privilege for performance
monitoring and observability operations (POSIX IEEE 1003.1e: 2.2.2.39 principle
of least privilege: A security design principle that states that a process
or program be granted only those privileges (e.g., capabilities) necessary
to accomplish its legitimate function, and only for the time that such
privileges are actually required)
CAP_PERFMON meets the demand to secure system performance monitoring and
observability operations for adoption in security sensitive, restricted,
multiuser production environments (e.g. HPC clusters, cloud and virtual compute
environments), where root or CAP_SYS_ADMIN credentials are not available to
mass users of a system, and securely unblocks applicability and scalability
of system performance monitoring and observability operations beyond root
and CAP_SYS_ADMIN process use cases.
CAP_PERFMON takes over CAP_SYS_ADMIN credentials related to system performance
monitoring and observability operations and balances amount of CAP_SYS_ADMIN
credentials following the recommendations in the capabilities man page [1]
for CAP_SYS_ADMIN: "Note: this capability is overloaded; see Notes to kernel
developers, below." For backward compatibility reasons access to system
performance monitoring and observability subsystems of the kernel remains
open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN capability
usage for secure system performance monitoring and observability operations
is discouraged with respect to the designed CAP_PERFMON capability.
Although the software running under CAP_PERFMON can not ensure avoidance
of related hardware issues, the software can still mitigate these issues
following the official embargoed hardware issues mitigation procedure [2].
The bugs in the software itself can be fixed following the standard kernel
development process [3] to maintain and harden security of system performance
monitoring and observability operations.
[1] http://man7.org/linux/man-pages/man7/capabilities.7.html
[2]
https://www.kernel.org/doc/html/latest/process/embargoed-hardware-issues.html
[3] https://www.kernel.org/doc/html/latest/admin-guide/security-bugs.html
Signed-off-by: Alexey Budankov
---
include/linux/capability.h | 4
include/uapi/linux/capability.h | 8 +++-
security/selinux/include/classmap.h | 4 ++--
3 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/include/linux/capability.h b/include/linux/capability.h
index ecce0f43c73a..027d7e4a853b 100644
--- a/include/linux/capability.h
+++ b/include/linux/capability.h
@@ -251,6 +251,10 @@ extern bool privileged_wrt_inode_uidgid(struct
user_namespace *ns, const struct
extern bool capable_wrt_inode_uidgid(const struct inode *inode, int cap);
extern bool file_ns_capable(const struct file *file, struct user_namespace
*ns, int cap);
extern bool ptracer_capable(struct task_struct *tsk, struct user_namespace
*ns);
+static inline bool perfmon_capable(void)
+{
+ return capable(CAP_PERFMON) || capable(CAP_SYS_ADMIN);
+}
/* audit system wants to get cap info from files as well */
extern int get_vfs_caps_from_disk(const struct dentry *dentry, struct
cpu_vfs_cap_data *cpu_caps);
diff --git a/include/uapi/linux/capability.h b/include/uapi/linux/capability.h
index 240fdb9a60f6..8b416e5f3afa 100644
--- a/include/uapi/linux/capability.h
+++ b/include/uapi/linux/capability.h
@@ -366,8 +366,14 @@ struct vfs_ns_cap_data {
#define CAP_AUDIT_READ 37
+/*
+ * Allow system performance and observability privileged operations
+ * using perf_events, i915_perf and other kernel subsystems
+ */
+
+#define CAP_PERFMON38
-#define CAP_LAST_CAP CAP_AUDIT_READ
+#define CAP_LAST_CAP CAP_PERFMON
#define cap_valid(x) ((x) >= 0 && (x) <= CAP_LAST_CAP)
diff --git a/security/selinux/include/classmap.h
b/security/selinux/include/classmap.h
index 7db24855e12d..c599b0c2b0e7 100644
--- a/security/selinux/include/classmap.h
+++ b/security/selinux/include/classmap.h
@@ -27,9 +27,9 @@
"audit_control", "setfcap"
#define COMMON_CAP2_PERMS "mac_override", "mac_admin", "syslog", \
- "wake_alarm", "block_suspend", "audit_read"
+ "wake_alarm", "block_suspend",
[Intel-gfx] [PATCH v6 00/10] Introduce CAP_PERFMON to secure system performance monitoring and observability
Currently access to perf_events, i915_perf and other performance monitoring and observability subsystems of the kernel is open only for a privileged process [1] with CAP_SYS_ADMIN capability enabled in the process effective set [2]. This patch set introduces CAP_PERFMON capability designed to secure system performance monitoring and observability operations so that CAP_PERFMON would assist CAP_SYS_ADMIN capability in its governing role for performance monitoring and observability subsystems of the kernel. CAP_PERFMON intends to harden system security and integrity during system performance monitoring and observability operations by decreasing attack surface that is available to a CAP_SYS_ADMIN privileged process [2]. Providing the access to system performance monitoring and observability operations under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes the operation more secure. Thus, CAP_PERFMON implements the principal of least privilege for performance monitoring and observability operations (POSIX IEEE 1003.1e: 2.2.2.39 principle of least privilege: A security design principle that states that a process or program be granted only those privileges (e.g., capabilities) necessary to accomplish its legitimate function, and only for the time that such privileges are actually required) CAP_PERFMON intends to meet the demand to secure system performance monitoring and observability operations for adoption in security sensitive, restricted, multiuser production environments (e.g. HPC clusters, cloud and virtual compute environments), where root or CAP_SYS_ADMIN credentials are not available to mass users of a system, and securely unblock applicability and scalability of system performance monitoring and observability operations beyond root or CAP_SYS_ADMIN process use cases. CAP_PERFMON intends to take over CAP_SYS_ADMIN credentials related to system performance monitoring and observability operations and balance amount of CAP_SYS_ADMIN credentials following the recommendations in the capabilities man page [2] for CAP_SYS_ADMIN: "Note: this capability is overloaded; see Notes to kernel developers, below." For backward compatibility reasons access to system performance monitoring and observability subsystems of the kernel remains open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN capability usage for secure system performance monitoring and observability operations is discouraged with respect to the designed CAP_PERFMON capability. Possible alternative solution to this system security hardening, capabilities balancing task of making performance monitoring and observability operations more accessible could be to use the existing CAP_SYS_PTRACE capability to govern system performance monitoring and observability subsystems. However CAP_SYS_PTRACE capability still provides users with more credentials than are required for secure performance monitoring and observability operations and this excess is avoided by the designed CAP_PERFMON capability. Although software running under CAP_PERFMON can not ensure avoidance of related hardware issues, the software can still mitigate those issues following the official embargoed hardware issues mitigation procedure [3]. The bugs in the software itself can be fixed following the standard kernel development process [4] to maintain and harden security of system performance monitoring and observability operations. Finally, the patch set is shaped in the way that simplifies backtracking procedure of possible induced issues [5] as much as possible. The patch set is for tip perf/core repository: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip perf/core sha1: 56ee04aa63285d6bc8a995a26e2441ae3d419bcd --- Changes in v6: - avoided noaudit checks in perfmon_capable() to explicitly advertise CAP_PERFMON usage thru audit logs to secure system performance monitoring and observability Changes in v5: - renamed CAP_SYS_PERFMON to CAP_PERFMON - extended perfmon_capable() with noaudit checks Changes in v4: - converted perfmon_capable() into an inline function - made perf_events kprobes, uprobes, hw breakpoints and namespaces data available to CAP_SYS_PERFMON privileged processes - applied perfmon_capable() to drivers/perf and drivers/oprofile - extended __cmd_ftrace() with support of CAP_SYS_PERFMON Changes in v3: - implemented perfmon_capable() macros aggregating required capabilities checks Changes in v2: - made perf_events trace points available to CAP_SYS_PERFMON privileged processes - made perf_event_paranoid_check() treat CAP_SYS_PERFMON equally to CAP_SYS_ADMIN - applied CAP_SYS_PERFMON to i915_perf, bpf_trace, powerpc and parisc system performance monitoring and observability related subsystems --- Alexey Budankov (10): capabilities: introduce CAP_PERFMON to kernel and user space perf/core: open access to the core for CAP_PERFMON privileged process perf/
Re: [Intel-gfx] [PATCH v2] drm/hdcp: optimizing the srm handling
On 2020-01-27 at 16:10:32 -0500, Sean Paul wrote:
> On Mon, Jan 27, 2020 at 11:42:31PM +0530, Ramalingam C wrote:
> > As we are not using the sysfs infrastructure anymore, link to it is
> > removed. And global srm data and mutex to protect it are removed,
> > with required handling at revocation check function.
> >
> > v2:
> > srm_data is dropped and few more comments are addressed.
> >
> > Signed-off-by: Ramalingam C
> > Suggested-by: Sean Paul
> > ---
> > drivers/gpu/drm/drm_hdcp.c | 144 -
> > drivers/gpu/drm/drm_internal.h | 4 -
> > drivers/gpu/drm/drm_sysfs.c| 2 -
> > include/drm/drm_hdcp.h | 4 +-
> > 4 files changed, 55 insertions(+), 99 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c
> > index 9191633a3c43..30749a13108e 100644
> > --- a/drivers/gpu/drm/drm_hdcp.c
> > +++ b/drivers/gpu/drm/drm_hdcp.c
> > @@ -23,14 +23,6 @@
> >
> > #include "drm_internal.h"
> >
> > -static struct hdcp_srm {
> > - u32 revoked_ksv_cnt;
> > - u8 *revoked_ksv_list;
> > -
> > - /* Mutex to protect above struct member */
> > - struct mutex mutex;
> > -} *srm_data;
> > -
> > static inline void drm_hdcp_print_ksv(const u8 *ksv)
> > {
> > DRM_DEBUG("\t%#02x, %#02x, %#02x, %#02x, %#02x\n",
> > @@ -91,7 +83,8 @@ static inline u32 get_vrl_length(const u8 *buf)
> > return drm_hdcp_be24_to_cpu(buf);
> > }
> >
> > -static int drm_hdcp_parse_hdcp1_srm(const u8 *buf, size_t count)
> > +static int drm_hdcp_parse_hdcp1_srm(const u8 *buf, size_t count,
> > + u8 *revoked_ksv_list, u32 *revoked_ksv_cnt)
>
> Shouldn't this be u8 **revoked_ksv_list since you want to return the pointer
> for
> use in the caller? I'm surprised any of this worked when you tested it...
Not tested yet. And forgot to add RFC too. Sorry for wasting your time.
-Ram
>
> > {
> > struct hdcp_srm_header *header;
> > u32 vrl_length, ksv_count;
> > @@ -131,29 +124,28 @@ static int drm_hdcp_parse_hdcp1_srm(const u8 *buf,
> > size_t count)
> > ksv_count = drm_hdcp_get_revoked_ksv_count(buf, vrl_length);
> > if (!ksv_count) {
> > DRM_DEBUG("Revoked KSV count is 0\n");
> > - return count;
> > + return 0;
> > }
> >
> > - kfree(srm_data->revoked_ksv_list);
> > - srm_data->revoked_ksv_list = kcalloc(ksv_count, DRM_HDCP_KSV_LEN,
> > -GFP_KERNEL);
> > - if (!srm_data->revoked_ksv_list) {
> > + revoked_ksv_list = kcalloc(ksv_count, DRM_HDCP_KSV_LEN, GFP_KERNEL);
> > + if (!revoked_ksv_list) {
> > DRM_ERROR("Out of Memory\n");
> > return -ENOMEM;
> > }
> >
> > - if (drm_hdcp_get_revoked_ksvs(buf, srm_data->revoked_ksv_list,
> > + if (drm_hdcp_get_revoked_ksvs(buf, revoked_ksv_list,
> > vrl_length) != ksv_count) {
> > - srm_data->revoked_ksv_cnt = 0;
> > - kfree(srm_data->revoked_ksv_list);
> > + *revoked_ksv_cnt = 0;
> > + kfree(revoked_ksv_list);
> > return -EINVAL;
> > }
> >
> > - srm_data->revoked_ksv_cnt = ksv_count;
> > - return count;
> > + *revoked_ksv_cnt = ksv_count;
> > + return 0;
> > }
> >
> > -static int drm_hdcp_parse_hdcp2_srm(const u8 *buf, size_t count)
> > +static int drm_hdcp_parse_hdcp2_srm(const u8 *buf, size_t count,
> > + u8 *revoked_ksv_list, u32 *revoked_ksv_cnt)
>
> Same comment here, this should be u8 **
>
> > {
> > struct hdcp_srm_header *header;
> > u32 vrl_length, ksv_count, ksv_sz;
> > @@ -195,13 +187,11 @@ static int drm_hdcp_parse_hdcp2_srm(const u8 *buf,
> > size_t count)
> > ksv_count = (*buf << 2) | DRM_HDCP_2_KSV_COUNT_2_LSBITS(*(buf + 1));
> > if (!ksv_count) {
> > DRM_DEBUG("Revoked KSV count is 0\n");
> > - return count;
> > + return 0;
> > }
> >
> > - kfree(srm_data->revoked_ksv_list);
> > - srm_data->revoked_ksv_list = kcalloc(ksv_count, DRM_HDCP_KSV_LEN,
> > -GFP_KERNEL);
> > - if (!srm_data->revoked_ksv_list) {
> > + revoked_ksv_list = kcalloc(ksv_count, DRM_HDCP_KSV_LEN, GFP_KERNEL);
> > + if (!revoked_ksv_list) {
> > DRM_ERROR("Out of Memory\n");
> > return -ENOMEM;
> > }
> > @@ -210,10 +200,10 @@ static int drm_hdcp_parse_hdcp2_srm(const u8 *buf,
> > size_t count)
> > buf += DRM_HDCP_2_NO_OF_DEV_PLUS_RESERVED_SZ;
> >
> > DRM_DEBUG("Revoked KSVs: %d\n", ksv_count);
> > - memcpy(srm_data->revoked_ksv_list, buf, ksv_sz);
> > + memcpy(revoked_ksv_list, buf, ksv_sz);
> >
> > - srm_data->revoked_ksv_cnt = ksv_count;
> > - return count;
> > + *revoked_ksv_cnt = ksv_count;
> > + return 0;
> > }
> >
> > static inline bool is_srm_version_hdcp1(const u8 *buf)
> > @@ -226,18 +216,22 @@ static inline bool is_srm_version_hdcp2(const u8 *buf)
> > return
[Intel-gfx] ✗ Fi.CI.BUILD: warning for series starting with [1/6] drm/i915: Skip capturing errors from internal contexts
== Series Details ==
Series: series starting with [1/6] drm/i915: Skip capturing errors from
internal contexts
URL : https://patchwork.freedesktop.org/series/72639/
State : warning
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/gt/intel_lrc.o
In file included from ./include/linux/printk.h:7:0,
from ./include/linux/kernel.h:15,
from ./include/linux/interrupt.h:6,
from drivers/gpu/drm/i915/gt/intel_lrc.c:134:
drivers/gpu/drm/i915/gt/selftest_lrc.c: In function ‘live_error_interrupt’:
./include/linux/kern_levels.h:5:18: error: format ‘%ld’ expects argument of
type ‘long int’, but argument 3 has type ‘int’ [-Werror=format=]
#define KERN_SOH "\001" /* ASCII Start Of Header */
^
./include/linux/kern_levels.h:11:18: note: in expansion of macro ‘KERN_SOH’
#define KERN_ERR KERN_SOH "3" /* error conditions */
^~~~
./include/linux/printk.h:304:9: note: in expansion of macro ‘KERN_ERR’
printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
^~~~
drivers/gpu/drm/i915/gt/selftest_lrc.c:525:5: note: in expansion of macro
‘pr_err’
pr_err("%s: failed at phase[%ld] { %d, %d }\n",
^~
In file included from drivers/gpu/drm/i915/gt/intel_lrc.c:5285:0:
drivers/gpu/drm/i915/gt/selftest_lrc.c:525:35: note: format string is defined
here
pr_err("%s: failed at phase[%ld] { %d, %d }\n",
~~^
%d
cc1: all warnings being treated as errors
scripts/Makefile.build:265: recipe for target
'drivers/gpu/drm/i915/gt/intel_lrc.o' failed
make[4]: *** [drivers/gpu/drm/i915/gt/intel_lrc.o] Error 1
scripts/Makefile.build:503: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:503: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:503: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1693: recipe for target 'drivers' failed
make: *** [drivers] Error 2
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/build_32bit.log
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Skip capturing errors from internal contexts
== Series Details ==
Series: series starting with [1/6] drm/i915: Skip capturing errors from
internal contexts
URL : https://patchwork.freedesktop.org/series/72639/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7827 -> Patchwork_16288
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/index.html
Known issues
Here are the changes found in Patchwork_16288 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_close_race@basic-threads:
- fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([i915#45])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-byt-j1900/igt@gem_close_r...@basic-threads.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/fi-byt-j1900/igt@gem_close_r...@basic-threads.html
* igt@i915_selftest@live_execlists:
- fi-icl-y: [PASS][3] -> [INCOMPLETE][4] ([i915#140])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-icl-y/igt@i915_selftest@live_execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/fi-icl-y/igt@i915_selftest@live_execlists.html
Possible fixes
* igt@i915_selftest@live_blt:
- fi-hsw-4770:[DMESG-FAIL][5] ([i915#553] / [i915#725]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-hsw-4770/igt@i915_selftest@live_blt.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/fi-hsw-4770/igt@i915_selftest@live_blt.html
Warnings
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [DMESG-WARN][7] ([IGT#4] / [i915#263]) -> [FAIL][8]
([i915#217])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
[IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4
[i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
[i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217
[i915#263]: https://gitlab.freedesktop.org/drm/intel/issues/263
[i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
Participating hosts (46 -> 35)
--
Additional (3): fi-cfl-8109u fi-ivb-3770 fi-skl-6600u
Missing(14): fi-ilk-m540 fi-kbl-7560u fi-hsw-peppy fi-byt-squawks
fi-bsw-cyan fi-ilk-650 fi-ctg-p8600 fi-icl-u3 fi-bsw-kefka fi-skl-lmem
fi-blb-e6850 fi-byt-clapper fi-bdw-samus fi-snb-2600
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7827 -> Patchwork_16288
CI-20190529: 20190529
CI_DRM_7827: c8969aeacfff681c83a800e82b0f18a6ab3e77ea @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5389: 966c58649dee31bb5bf2fad92f75ffd365968b81 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16288: da5f1d218ee1d45fecdd7d3f95d004277529bfe9 @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/Patchwork_16288/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/gt/intel_lrc.o
In file included from ./include/linux/printk.h:7:0,
from ./include/linux/kernel.h:15,
from ./include/linux/interrupt.h:6,
from drivers/gpu/drm/i915/gt/intel_lrc.c:134:
drivers/gpu/drm/i915/gt/selftest_lrc.c: In function ‘live_error_interrupt’:
./include/linux/kern_levels.h:5:18: error: format ‘%ld’ expects argument of
type ‘long int’, but argument 3 has type ‘int’ [-Werror=format=]
#define KERN_SOH "\001" /* ASCII Start Of Header */
^
./include/linux/kern_levels.h:11:18: note: in expansion of macro ‘KERN_SOH’
#define KERN_ERR KERN_SOH "3" /* error conditions */
^~~~
./include/linux/printk.h:304:9: note: in expansion of macro ‘KERN_ERR’
printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
^~~~
drivers/gpu/drm/i915/gt/selftest_lrc.c:525:5: note: in expansion of macro
‘pr_err’
pr_err("%s: failed at phase[%ld] { %d, %d }\n",
^~
In file included from drivers/gpu/drm/i915/gt/intel_lrc.c:5285:0:
drivers/gpu/drm/i915/gt/selftest_lrc.c:525:35: note: format string is defined
here
pr_err("%s: failed at phase[%ld] { %d, %d }\n",
~~^
%d
cc1: all warnings being treated as errors
scripts/Makefile.build:265: recipe for target
'drivers/gpu/drm/i915/gt/intel_lrc.o' failed
make[4]: *** [drivers/gpu/drm/i915/gt/intel_lrc.o] Error 1
scripts/Makefile.buil
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/8] drm/i915/gt: Expose engine properties via sysfs
== Series Details == Series: series starting with [1/8] drm/i915/gt: Expose engine properties via sysfs URL : https://patchwork.freedesktop.org/series/72638/ State : success == Summary == CI Bug Log - changes from CI_DRM_7827 -> Patchwork_16287 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16287/index.html Known issues Here are the changes found in Patchwork_16287 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([i915#45]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16287/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@gem_exec_suspend@basic-s0: - fi-cml-s: [PASS][3] -> [FAIL][4] ([fdo#103375]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-cml-s/igt@gem_exec_susp...@basic-s0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16287/fi-cml-s/igt@gem_exec_susp...@basic-s0.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#111096] / [i915#323]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16287/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-n2820: [INCOMPLETE][7] ([i915#45]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16287/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][9] ([i915#553] / [i915#725]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-hsw-4770/igt@i915_selftest@live_blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16287/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_hangcheck: - fi-icl-u3: [INCOMPLETE][11] ([fdo#108569] / [i915#140]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16287/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 Participating hosts (46 -> 42) -- Additional (5): fi-bsw-n3050 fi-gdg-551 fi-cfl-8109u fi-ivb-3770 fi-skl-6600u Missing(9): fi-ilk-m540 fi-skl-guc fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 fi-byt-clapper fi-bsw-nick fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7827 -> Patchwork_16287 CI-20190529: 20190529 CI_DRM_7827: c8969aeacfff681c83a800e82b0f18a6ab3e77ea @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5389: 966c58649dee31bb5bf2fad92f75ffd365968b81 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16287: ee38c0c884e09522addb9b1878ca62a96410f046 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ee38c0c884e0 drm/i915/gt: Limit C-states while waiting for requests 34c7e80d10c4 drm/i915/gt: Expose heartbeat interval via sysfs b5a6e0a034f4 drm/i915/gt: Expose preempt reset timeout via sysfs d8525a46fca0 drm/i915/gt: Expose reset stop timeout via sysfs bbaa9815c6d6 drm/i915/gt: Expose busywait duration to sysfs 8d73412baf92 drm/i915/gt: Expose timeslice duration to sysfs 91825d7a3da0 drm/i915/gt: Expose engine->mmio_base via sysfs 988fe3ead6d1 drm/i915/gt: Expose engine properties via sysfs == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16287/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Skip capturing errors from internal contexts
== Series Details == Series: series starting with [1/6] drm/i915: Skip capturing errors from internal contexts URL : https://patchwork.freedesktop.org/series/72639/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5176f847f2a0 drm/i915: Skip capturing errors from internal contexts 5c4b9c7eca9e drm/i915/gt: Reorganise gen8+ interrupt handler 5b77c1593e67 drm/i915/gt: Tidy repetition in declaring gen8+ interrupts 1c4461c839c0 drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore -:176: WARNING:LONG_LINE: line over 100 characters #176: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:1875: + yesno(upper_32_bits(last->context->lrc_desc) == READ_ONCE(execlists->yield))); total: 0 errors, 1 warnings, 0 checks, 155 lines checked e99cb72106a0 drm/i915/gt: Hook up CS_MASTER_ERROR_INTERRUPT da5f1d218ee1 drm/i915/gt: Lift set-wedged engine dumping out of user paths ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/8] drm/i915/gt: Expose engine properties via sysfs
== Series Details == Series: series starting with [1/8] drm/i915/gt: Expose engine properties via sysfs URL : https://patchwork.freedesktop.org/series/72638/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/gt: Expose engine properties via sysfs - +drivers/gpu/drm/i915/gt/sysfs_engines.c:51:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:52:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:56:10: error: bad integer constant expression Commit: drm/i915/gt: Expose engine->mmio_base via sysfs +drivers/gpu/drm/i915/gt/sysfs_engines.c:60:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression -O:drivers/gpu/drm/i915/gt/sysfs_engines.c:51:10: error: bad integer constant expression -O:drivers/gpu/drm/i915/gt/sysfs_engines.c:52:10: error: bad integer constant expression Commit: drm/i915/gt: Expose timeslice duration to sysfs Okay! Commit: drm/i915/gt: Expose busywait duration to sysfs +drivers/gpu/drm/i915/intel_wakeref.c:135:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock +drivers/gpu/drm/i915/selftests/i915_syncmap.c:80:54: warning: dubious: x | !y Commit: drm/i915/gt: Expose reset stop timeout via sysfs Okay! Commit: drm/i915/gt: Expose preempt reset timeout via sysfs Okay! Commit: drm/i915/gt: Expose heartbeat interval via sysfs Okay! Commit: drm/i915/gt: Limit C-states while waiting for requests Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/8] drm/i915/gt: Expose engine properties via sysfs
== Series Details ==
Series: series starting with [1/8] drm/i915/gt: Expose engine properties via
sysfs
URL : https://patchwork.freedesktop.org/series/72638/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
988fe3ead6d1 drm/i915/gt: Expose engine properties via sysfs
-:91: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#91:
new file mode 100644
-:196: CHECK:SPACING: No space is necessary after a cast
#196: FILE: drivers/gpu/drm/i915/gt/sysfs_engines.c:101:
+show_unknown ? BITS_PER_TYPE(typeof(caps)) : count) {
total: 0 errors, 1 warnings, 1 checks, 255 lines checked
91825d7a3da0 drm/i915/gt: Expose engine->mmio_base via sysfs
8d73412baf92 drm/i915/gt: Expose timeslice duration to sysfs
bbaa9815c6d6 drm/i915/gt: Expose busywait duration to sysfs
d8525a46fca0 drm/i915/gt: Expose reset stop timeout via sysfs
b5a6e0a034f4 drm/i915/gt: Expose preempt reset timeout via sysfs
34c7e80d10c4 drm/i915/gt: Expose heartbeat interval via sysfs
ee38c0c884e0 drm/i915/gt: Limit C-states while waiting for requests
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Check current i915_vma.pin_count status first on unbind (rev3)
== Series Details == Series: drm/i915: Check current i915_vma.pin_count status first on unbind (rev3) URL : https://patchwork.freedesktop.org/series/72529/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7827 -> Patchwork_16286 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16286 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16286, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16286/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16286: ### IGT changes ### Possible regressions * igt@gem_exec_suspend@basic: - fi-kbl-7500u: [PASS][1] -> [FAIL][2] +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-kbl-7500u/igt@gem_exec_susp...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16286/fi-kbl-7500u/igt@gem_exec_susp...@basic.html * igt@gem_exec_suspend@basic-s0: - fi-kbl-r: [PASS][3] -> [FAIL][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-kbl-r/igt@gem_exec_susp...@basic-s0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16286/fi-kbl-r/igt@gem_exec_susp...@basic-s0.html - fi-skl-lmem:[PASS][5] -> [FAIL][6] +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-skl-lmem/igt@gem_exec_susp...@basic-s0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16286/fi-skl-lmem/igt@gem_exec_susp...@basic-s0.html - fi-cfl-8700k: [PASS][7] -> [FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-cfl-8700k/igt@gem_exec_susp...@basic-s0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16286/fi-cfl-8700k/igt@gem_exec_susp...@basic-s0.html * igt@gem_exec_suspend@basic-s3: - fi-bxt-dsi: [PASS][9] -> [FAIL][10] +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-bxt-dsi/igt@gem_exec_susp...@basic-s3.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16286/fi-bxt-dsi/igt@gem_exec_susp...@basic-s3.html - fi-apl-guc: [PASS][11] -> [FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-apl-guc/igt@gem_exec_susp...@basic-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16286/fi-apl-guc/igt@gem_exec_susp...@basic-s3.html * igt@gem_exec_suspend@basic-s4-devices: - fi-glk-dsi: [PASS][13] -> [FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-glk-dsi/igt@gem_exec_susp...@basic-s4-devices.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16286/fi-glk-dsi/igt@gem_exec_susp...@basic-s4-devices.html - fi-cml-u2: [PASS][15] -> [FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-cml-u2/igt@gem_exec_susp...@basic-s4-devices.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16286/fi-cml-u2/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_selftest@live_gtt: - fi-skl-guc: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-skl-guc/igt@i915_selftest@live_gtt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16286/fi-skl-guc/igt@i915_selftest@live_gtt.html - fi-cfl-8109u: NOTRUN -> [INCOMPLETE][19] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16286/fi-cfl-8109u/igt@i915_selftest@live_gtt.html - fi-kbl-7500u: [PASS][20] -> [INCOMPLETE][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-kbl-7500u/igt@i915_selftest@live_gtt.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16286/fi-kbl-7500u/igt@i915_selftest@live_gtt.html - fi-kbl-guc: [PASS][22] -> [INCOMPLETE][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-kbl-guc/igt@i915_selftest@live_gtt.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16286/fi-kbl-guc/igt@i915_selftest@live_gtt.html - fi-kbl-8809g: [PASS][24] -> [INCOMPLETE][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-kbl-8809g/igt@i915_selftest@live_gtt.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16286/fi-kbl-8809g/igt@i915_selftest@live_gtt.html - fi-cfl-8700k: [PASS][26] -> [INCOMPLETE][27] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-cfl-8700k/igt@i915_selftest@live_gtt.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16286/fi-cfl-8700k/igt@i915_selftest@live_gtt.html - fi-kbl-r: [PASS][28] -> [INCOMPLETE][29] [28]: https://intel-gfx-ci
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Suppress DC5/DC6 around DSB usage (rev3)
== Series Details == Series: drm/i915/tgl: Suppress DC5/DC6 around DSB usage (rev3) URL : https://patchwork.freedesktop.org/series/72549/ State : success == Summary == CI Bug Log - changes from CI_DRM_7827 -> Patchwork_16285 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16285/index.html Known issues Here are the changes found in Patchwork_16285 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][1] -> [DMESG-FAIL][2] ([i915#553] / [i915#725]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-hsw-4770r/igt@i915_selftest@live_blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16285/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gt_heartbeat: - fi-bsw-kefka: [PASS][3] -> [DMESG-FAIL][4] ([i915#541]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-bsw-kefka/igt@i915_selftest@live_gt_heartbeat.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16285/fi-bsw-kefka/igt@i915_selftest@live_gt_heartbeat.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#111407]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16285/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-n2820: [INCOMPLETE][7] ([i915#45]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16285/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][9] ([i915#553] / [i915#725]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-hsw-4770/igt@i915_selftest@live_blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16285/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_hangcheck: - fi-icl-u3: [INCOMPLETE][11] ([fdo#108569] / [i915#140]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16285/fi-icl-u3/igt@i915_selftest@live_hangcheck.html Warnings * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [DMESG-WARN][13] ([IGT#4] / [i915#263]) -> [DMESG-FAIL][14] ([IGT#4] / [i915#263]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16285/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140 [i915#263]: https://gitlab.freedesktop.org/drm/intel/issues/263 [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45 [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 Participating hosts (46 -> 43) -- Additional (5): fi-bsw-n3050 fi-gdg-551 fi-cfl-8109u fi-ivb-3770 fi-skl-6600u Missing(8): fi-ilk-m540 fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7827 -> Patchwork_16285 CI-20190529: 20190529 CI_DRM_7827: c8969aeacfff681c83a800e82b0f18a6ab3e77ea @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5389: 966c58649dee31bb5bf2fad92f75ffd365968b81 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16285: 26b8e88007de1480a95f6a35404a60d322529eda @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 26b8e88007de drm/i915/tgl: Suppress DC5/DC6 around DSB usage == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16285/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v5, 3/3] drm/i915: Add support for integrated privacy screens
On Fri, Jan 24, 2020 at 4:11 PM Guenter Roeck wrote:
>
> On Fri, Dec 20, 2019 at 12:03:53PM -0800, Rajat Jain wrote:
> > Certain laptops now come with panels that have integrated privacy
> > screens on them. This patch adds support for such panels by adding
> > a privacy-screen property to the intel_connector for the panel, that
> > the userspace can then use to control and check the status.
> >
> > Identifying the presence of privacy screen, and controlling it, is done
> > via ACPI _DSM methods.
> >
> > Currently, this is done only for the Intel display ports. But in future,
> > this can be done for any other ports if the hardware becomes available
> > (e.g. external monitors supporting integrated privacy screens?).
> >
> > Signed-off-by: Rajat Jain
> > ---
> > v5: fix a cosmetic checkpatch warning
> > v4: Fix a typo in intel_privacy_screen.h
> > v3: * Change license to GPL-2.0 OR MIT
> > * Move privacy screen enum from UAPI to intel_display_types.h
> > * Rename parameter name and some other minor changes.
> > v2: Formed by splitting the original patch into multiple patches.
> > - All code has been moved into i915 now.
> > - Privacy screen is a i915 property
> > - Have a local state variable to store the prvacy screen. Don't read
> > it from hardware.
> >
> > drivers/gpu/drm/i915/Makefile | 3 +-
> > drivers/gpu/drm/i915/display/intel_atomic.c | 13 +++-
> > .../gpu/drm/i915/display/intel_connector.c| 35 +
> > .../gpu/drm/i915/display/intel_connector.h| 1 +
> > .../drm/i915/display/intel_display_types.h| 18 +
> > drivers/gpu/drm/i915/display/intel_dp.c | 6 ++
> > .../drm/i915/display/intel_privacy_screen.c | 72 +++
> > .../drm/i915/display/intel_privacy_screen.h | 27 +++
> > 8 files changed, 171 insertions(+), 4 deletions(-)
> > create mode 100644 drivers/gpu/drm/i915/display/intel_privacy_screen.c
> > create mode 100644 drivers/gpu/drm/i915/display/intel_privacy_screen.h
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> > index 90dcf09f52cc..f7067c8f0407 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -197,7 +197,8 @@ i915-y += \
> > display/intel_vga.o
> > i915-$(CONFIG_ACPI) += \
> > display/intel_acpi.o \
> > - display/intel_opregion.o
> > + display/intel_opregion.o \
> > + display/intel_privacy_screen.o
> > i915-$(CONFIG_DRM_FBDEV_EMULATION) += \
> > display/intel_fbdev.o
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> > b/drivers/gpu/drm/i915/display/intel_atomic.c
> > index c2875b10adf9..c73b81c4c3f6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > @@ -37,6 +37,7 @@
> > #include "intel_atomic.h"
> > #include "intel_display_types.h"
> > #include "intel_hdcp.h"
> > +#include "intel_privacy_screen.h"
> > #include "intel_sprite.h"
> >
> > /**
> > @@ -57,11 +58,14 @@ int intel_digital_connector_atomic_get_property(struct
> > drm_connector *connector,
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > struct intel_digital_connector_state *intel_conn_state =
> > to_intel_digital_connector_state(state);
> > + struct intel_connector *intel_connector =
> > to_intel_connector(connector);
> >
> > if (property == dev_priv->force_audio_property)
> > *val = intel_conn_state->force_audio;
> > else if (property == dev_priv->broadcast_rgb_property)
> > *val = intel_conn_state->broadcast_rgb;
> > + else if (property == intel_connector->privacy_screen_property)
> > + *val = intel_conn_state->privacy_screen_status;
> > else {
> > DRM_DEBUG_ATOMIC("Unknown property [PROP:%d:%s]\n",
> >property->base.id, property->name);
> > @@ -89,15 +93,18 @@ int intel_digital_connector_atomic_set_property(struct
> > drm_connector *connector,
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > struct intel_digital_connector_state *intel_conn_state =
> > to_intel_digital_connector_state(state);
> > + struct intel_connector *intel_connector =
> > to_intel_connector(connector);
> >
> > if (property == dev_priv->force_audio_property) {
> > intel_conn_state->force_audio = val;
> > return 0;
> > - }
> > -
> > - if (property == dev_priv->broadcast_rgb_property) {
> > + } else if (property == dev_priv->broadcast_rgb_property) {
> > intel_conn_state->broadcast_rgb = val;
> > return 0;
> > + } else if (property == intel_connector->privacy_screen_property) {
> > + intel_privacy_screen_set_val(intel_connector, val);
> > + intel_conn_state->privacy_screen_status = val;
> > + return 0;
> > }
> >
> > DRM_DEBUG_ATOMIC("Unknown prope
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Adding YUV444 packed format support for skl+ (rev3)
== Series Details == Series: drm/i915: Adding YUV444 packed format support for skl+ (rev3) URL : https://patchwork.freedesktop.org/series/66770/ State : success == Summary == CI Bug Log - changes from CI_DRM_7827 -> Patchwork_16284 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16284/index.html Known issues Here are the changes found in Patchwork_16284 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([i915#45]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16284/fi-byt-j1900/igt@gem_close_r...@basic-threads.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-n2820: [INCOMPLETE][3] ([i915#45]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16284/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_hangcheck: - fi-icl-u3: [INCOMPLETE][5] ([fdo#108569] / [i915#140]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16284/fi-icl-u3/igt@i915_selftest@live_hangcheck.html Warnings * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][7] ([i915#553] / [i915#725]) -> [DMESG-FAIL][8] ([i915#563]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-hsw-4770/igt@i915_selftest@live_blt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16284/fi-hsw-4770/igt@i915_selftest@live_blt.html [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140 [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 Participating hosts (46 -> 40) -- Additional (5): fi-bsw-n3050 fi-gdg-551 fi-cfl-8109u fi-ivb-3770 fi-skl-6600u Missing(11): fi-ilk-m540 fi-bdw-samus fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 fi-elk-e7500 fi-skl-lmem fi-kbl-7560u fi-byt-clapper fi-skl-6700k2 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7827 -> Patchwork_16284 CI-20190529: 20190529 CI_DRM_7827: c8969aeacfff681c83a800e82b0f18a6ab3e77ea @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5389: 966c58649dee31bb5bf2fad92f75ffd365968b81 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16284: a705c01c469eb9cfaa89e35d27a1e17b7389d308 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a705c01c469e drm/i915: Adding YUV444 packed format support for skl+ (V13) == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16284/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: mass conversion to intel_de_*() register accessors (rev2)
== Series Details == Series: drm/i915/display: mass conversion to intel_de_*() register accessors (rev2) URL : https://patchwork.freedesktop.org/series/72533/ State : success == Summary == CI Bug Log - changes from CI_DRM_7827 -> Patchwork_16283 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16283/index.html Known issues Here are the changes found in Patchwork_16283 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][1] -> [DMESG-FAIL][2] ([i915#553] / [i915#725]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-hsw-4770r/igt@i915_selftest@live_blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16283/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-hsw-peppy: [PASS][3] -> [DMESG-FAIL][4] ([i915#722]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16283/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html Possible fixes * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][5] ([i915#553] / [i915#725]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-hsw-4770/igt@i915_selftest@live_blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16283/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_hangcheck: - fi-icl-u3: [INCOMPLETE][7] ([fdo#108569] / [i915#140]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16283/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 Participating hosts (46 -> 39) -- Additional (3): fi-gdg-551 fi-cfl-8109u fi-bsw-n3050 Missing(10): fi-ilk-m540 fi-bdw-5557u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bsw-nick fi-bdw-samus fi-snb-2600 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7827 -> Patchwork_16283 CI-20190529: 20190529 CI_DRM_7827: c8969aeacfff681c83a800e82b0f18a6ab3e77ea @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5389: 966c58649dee31bb5bf2fad92f75ffd365968b81 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16283: 926ad0bb0b6374995ae9697bfe561eed406609d8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 926ad0bb0b63 drm/i915/psr: use intel_de_*() functions for register access ce03b8b21b79 drm/i915/hdcp: use intel_de_*() functions for register access 34efc8c86da2 drm/i915/dp: use intel_de_*() functions for register access e1d262411740 drm/i915/display_power: use intel_de_*() functions for register access 9e1d8d3f24f2 drm/i915/display: use intel_de_*() functions for register access b38e2a044bff drm/i915/ddi: use intel_de_*() functions for register access bfcd10dad4e2 drm/i915/combo_phy: use intel_de_*() functions for register access e3fe468e8ec9 drm/i915/icl_dsi: use intel_de_*() functions for register access == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16283/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Adding YUV444 packed format support for skl+ (rev3)
== Series Details == Series: drm/i915: Adding YUV444 packed format support for skl+ (rev3) URL : https://patchwork.freedesktop.org/series/66770/ State : warning == Summary == $ dim checkpatch origin/drm-tip a705c01c469e drm/i915: Adding YUV444 packed format support for skl+ (V13) -:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #9: PLANE_CTL_FORMAT_AYUV is already supported, according to hardware specification. total: 0 errors, 1 warnings, 0 checks, 66 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH i-g-t] tests/gem_userptr_blits: Enhance invalid mapping exercise
On 22/01/20 08:26, Janusz Krzysztofik wrote:
Working with a userptr GEM object backed by any type of mapping to
another GEM object, not only GTT mapping currently examined bu the
test, may cause a currently unavoidable lockdep splat inside the i915
driver. Then, such operations are expected to fail in advance to
prevent from that badness to happen.
Extend the scope of the test by adding subtests which exercise other,
non-GTT mapping types. Moreover, also succeed if a failure happens
as soon as a userptr object is created on top of an invalid mapping.
Suggested-by: Chris Wilson
Signed-off-by: Janusz Krzysztofik
---
tests/i915/gem_userptr_blits.c | 87 +++---
1 file changed, 59 insertions(+), 28 deletions(-)
diff --git a/tests/i915/gem_userptr_blits.c b/tests/i915/gem_userptr_blits.c
index a8d3783f..69e5bd1f 100644
--- a/tests/i915/gem_userptr_blits.c
+++ b/tests/i915/gem_userptr_blits.c
@@ -60,6 +60,7 @@
#include "drm.h"
#include "i915_drm.h"
+#include "i915/gem_mman.h"
#include "intel_bufmgr.h"
@@ -577,11 +578,11 @@ static int test_invalid_null_pointer(int fd)
return 0;
}
-static int test_invalid_gtt_mapping(int fd)
+static int test_invalid_mapping(int fd, uint64_t flags)
{
- struct drm_i915_gem_mmap_gtt arg;
+ struct drm_i915_gem_mmap_offset arg;
uint32_t handle;
- char *gtt, *map;
+ char *offset, *map;
/* Anonymous mapping to find a hole */
map = mmap(NULL, sizeof(linear) + 2 * PAGE_SIZE,
@@ -602,39 +603,46 @@ static int test_invalid_gtt_mapping(int fd)
igt_assert_eq(copy(fd, handle, handle), 0);
gem_close(fd, handle);
- /* GTT mapping */
+ /* object mapping */
memset(&arg, 0, sizeof(arg));
arg.handle = create_bo(fd, 0);
- do_ioctl(fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &arg);
- gtt = mmap(map + PAGE_SIZE, sizeof(linear),
- PROT_READ | PROT_WRITE,
- MAP_SHARED | MAP_FIXED,
- fd, arg.offset);
- igt_assert(gtt == map + PAGE_SIZE);
+ arg.flags = flags;
+ do_ioctl(fd, DRM_IOCTL_I915_GEM_MMAP_OFFSET, &arg);
+ offset = mmap(map + PAGE_SIZE, sizeof(linear), PROT_READ | PROT_WRITE,
+ MAP_SHARED | MAP_FIXED, fd, arg.offset);
+ igt_assert(offset == map + PAGE_SIZE);
gem_close(fd, arg.handle);
- igt_assert(((unsigned long)gtt & (PAGE_SIZE - 1)) == 0);
+ igt_assert(((unsigned long)offset & (PAGE_SIZE - 1)) == 0);
igt_assert((sizeof(linear) & (PAGE_SIZE - 1)) == 0);
- gem_userptr(fd, gtt, sizeof(linear), 0, userptr_flags, &handle);
- igt_assert_eq(copy(fd, handle, handle), -EFAULT);
- gem_close(fd, handle);
+ if (!__gem_userptr(fd, offset, sizeof(linear), 0, userptr_flags,
+ &handle)) {
Not sure I follow why you converted this to an if. Do we expect the
userptr IOCTL not to work? Could you add a small comment.
Antonio
+ igt_assert_eq(copy(fd, handle, handle), -EFAULT);
+ gem_close(fd, handle);
+ }
- gem_userptr(fd, gtt, PAGE_SIZE, 0, userptr_flags, &handle);
- igt_assert_eq(copy(fd, handle, handle), -EFAULT);
- gem_close(fd, handle);
+ if (!__gem_userptr(fd, offset, PAGE_SIZE, 0, userptr_flags, &handle)) {
+ igt_assert_eq(copy(fd, handle, handle), -EFAULT);
+ gem_close(fd, handle);
+ }
- gem_userptr(fd, gtt + sizeof(linear) - PAGE_SIZE, PAGE_SIZE, 0, userptr_flags, &handle);
- igt_assert_eq(copy(fd, handle, handle), -EFAULT);
- gem_close(fd, handle);
+ if (!__gem_userptr(fd, offset + sizeof(linear) - PAGE_SIZE, PAGE_SIZE,
+ 0, userptr_flags, &handle)) {
+ igt_assert_eq(copy(fd, handle, handle), -EFAULT);
+ gem_close(fd, handle);
+ }
/* boundaries */
- gem_userptr(fd, map, 2*PAGE_SIZE, 0, userptr_flags, &handle);
- igt_assert_eq(copy(fd, handle, handle), -EFAULT);
- gem_close(fd, handle);
+ if (!__gem_userptr(fd, map, 2 * PAGE_SIZE, 0, userptr_flags, &handle)) {
+ igt_assert_eq(copy(fd, handle, handle), -EFAULT);
+ gem_close(fd, handle);
+ }
- gem_userptr(fd, map + sizeof(linear), 2*PAGE_SIZE, 0, userptr_flags, &handle);
- igt_assert_eq(copy(fd, handle, handle), -EFAULT);
- gem_close(fd, handle);
+ if (!__gem_userptr(fd, map + sizeof(linear), 2 * PAGE_SIZE, 0,
+ userptr_flags, &handle)) {
+ igt_assert_eq(copy(fd, handle, handle), -EFAULT);
+ gem_close(fd, handle);
+ }
munmap(map, sizeof(linear) + 2*PAGE_SIZE);
@@ -2009,8 +2017,31 @@ igt_main_args("c:", NULL, help_str, opt_handler, NULL)
igt_subtest("invalid-null-pointer")
test_invalid_null_pointer(fd);
- igt_subtest("invalid-gtt-mapping")
- test_invalid_gtt_mapping(fd);
+
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: mass conversion to intel_de_*() register accessors (rev2)
== Series Details == Series: drm/i915/display: mass conversion to intel_de_*() register accessors (rev2) URL : https://patchwork.freedesktop.org/series/72533/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/icl_dsi: use intel_de_*() functions for register access Okay! Commit: drm/i915/combo_phy: use intel_de_*() functions for register access Okay! Commit: drm/i915/ddi: use intel_de_*() functions for register access Okay! Commit: drm/i915/display: use intel_de_*() functions for register access +drivers/gpu/drm/i915/display/intel_display.c:1218:22: error: Expected constant expression in case statement -O:drivers/gpu/drm/i915/display/intel_display.c:1219:22: error: Expected constant expression in case statement Commit: drm/i915/display_power: use intel_de_*() functions for register access Okay! Commit: drm/i915/dp: use intel_de_*() functions for register access Okay! Commit: drm/i915/hdcp: use intel_de_*() functions for register access Okay! Commit: drm/i915/psr: use intel_de_*() functions for register access Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: mass conversion to intel_de_*() register accessors (rev2)
== Series Details == Series: drm/i915/display: mass conversion to intel_de_*() register accessors (rev2) URL : https://patchwork.freedesktop.org/series/72533/ State : warning == Summary == $ dim checkpatch origin/drm-tip e3fe468e8ec9 drm/i915/icl_dsi: use intel_de_*() functions for register access bfcd10dad4e2 drm/i915/combo_phy: use intel_de_*() functions for register access b38e2a044bff drm/i915/ddi: use intel_de_*() functions for register access -:131: WARNING:LONG_LINE: line over 100 characters #131: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1168: + FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); -:164: WARNING:LONG_LINE: line over 100 characters #164: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1192: + DP_TP_CTL_FDI_AUTOTRAIN | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_ENABLE); -:176: WARNING:LONG_LINE: line over 100 characters #176: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1199: + DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2)); -:259: WARNING:LONG_LINE: line over 100 characters #259: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1267: + DP_TP_CTL_FDI_AUTOTRAIN | DP_TP_CTL_LINK_TRAIN_NORMAL | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_ENABLE); -:956: WARNING:LONG_LINE: line over 100 characters #956: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:3211: + intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port)); total: 0 errors, 5 warnings, 0 checks, 1137 lines checked 9e1d8d3f24f2 drm/i915/display: use intel_de_*() functions for register access -:66: WARNING:LONG_LINE: line over 100 characters #66: FILE: drivers/gpu/drm/i915/display/intel_display.c:523: + intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS); -:66: ERROR:CODE_INDENT: code indent should use tabs where possible #66: FILE: drivers/gpu/drm/i915/display/intel_display.c:523: +^I^I intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);$ -:72: WARNING:LONG_LINE: line over 100 characters #72: FILE: drivers/gpu/drm/i915/display/intel_display.c:526: + intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); -:72: ERROR:CODE_INDENT: code indent should use tabs where possible #72: FILE: drivers/gpu/drm/i915/display/intel_display.c:526: +^I^I intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));$ -:83: ERROR:CODE_INDENT: code indent should use tabs where possible #83: FILE: drivers/gpu/drm/i915/display/intel_display.c:536: +^I^I intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);$ -:88: ERROR:CODE_INDENT: code indent should use tabs where possible #88: FILE: drivers/gpu/drm/i915/display/intel_display.c:539: +^I^I intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);$ -:659: WARNING:LONG_LINE: line over 100 characters #659: FILE: drivers/gpu/drm/i915/display/intel_display.c:5035: + intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE); -:659: ERROR:CODE_INDENT: code indent should use tabs where possible #659: FILE: drivers/gpu/drm/i915/display/intel_display.c:5035: +^I^I intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);$ -:1590: WARNING:LONG_LINE: line over 100 characters #1590: FILE: drivers/gpu/drm/i915/display/intel_display.c:8298: + pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); -:1631: ERROR:CODE_INDENT: code indent should use tabs where possible #1631: FILE: drivers/gpu/drm/i915/display/intel_display.c:8699: +^I^I vsyncshift);$ -:1634: WARNING:LONG_LINE: line over 100 characters #1634: FILE: drivers/gpu/drm/i915/display/intel_display.c:8702: + (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); -:1636: WARNING:LONG_LINE: line over 100 characters #1636: FILE: drivers/gpu/drm/i915/display/intel_display.c:8704: + (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); -:1638: WARNING:LONG_LINE: line over 100 characters #1638: FILE: drivers/gpu/drm/i915/display/intel_display.c:8706: + (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); -:1645: WARNING:LONG_LINE: line over 100 characters #1645: FILE: drivers/gpu/drm/i915/display/intel_display.c:8713: + (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); -:1655: ERROR:CODE_INDENT: code indent should use tabs where possible #1655: FILE: drivers/gpu
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/hdcp: optimizing the srm handling (rev2)
== Series Details == Series: drm/hdcp: optimizing the srm handling (rev2) URL : https://patchwork.freedesktop.org/series/72312/ State : success == Summary == CI Bug Log - changes from CI_DRM_7827 -> Patchwork_16282 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16282/index.html Known issues Here are the changes found in Patchwork_16282 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-process: - fi-byt-j1900: [PASS][1] -> [FAIL][2] ([i915#694]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-byt-j1900/igt@gem_close_r...@basic-process.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16282/fi-byt-j1900/igt@gem_close_r...@basic-process.html * igt@gem_exec_parallel@fds: - fi-hsw-peppy: [PASS][3] -> [INCOMPLETE][4] ([i915#694]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-hsw-peppy/igt@gem_exec_paral...@fds.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16282/fi-hsw-peppy/igt@gem_exec_paral...@fds.html * igt@i915_pm_rpm@basic-rte: - fi-hsw-4770:[PASS][5] -> [SKIP][6] ([fdo#109271]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-hsw-4770/igt@i915_pm_...@basic-rte.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16282/fi-hsw-4770/igt@i915_pm_...@basic-rte.html * igt@i915_selftest@live_gem_contexts: - fi-byt-j1900: [PASS][7] -> [DMESG-FAIL][8] ([i915#722]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16282/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][9] -> [FAIL][10] ([fdo#111096] / [i915#323]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16282/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@i915_selftest@live_hangcheck: - fi-icl-u3: [INCOMPLETE][11] ([fdo#108569] / [i915#140]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16282/fi-icl-u3/igt@i915_selftest@live_hangcheck.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [DMESG-WARN][13] ([IGT#4] / [i915#263]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16282/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140 [i915#263]: https://gitlab.freedesktop.org/drm/intel/issues/263 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694 [i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722 Participating hosts (46 -> 38) -- Additional (3): fi-ivb-3770 fi-skl-6600u fi-bsw-n3050 Missing(11): fi-ilk-m540 fi-kbl-7560u fi-byt-squawks fi-bsw-cyan fi-ilk-650 fi-ctg-p8600 fi-whl-u fi-kbl-8809g fi-blb-e6850 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7827 -> Patchwork_16282 CI-20190529: 20190529 CI_DRM_7827: c8969aeacfff681c83a800e82b0f18a6ab3e77ea @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5389: 966c58649dee31bb5bf2fad92f75ffd365968b81 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16282: 026d21a8ab510a3005f4fdbc95b84ca88449606c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 026d21a8ab51 drm/hdcp: optimizing the srm handling == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16282/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: Modeset only the tiled connectors with CRTC (rev2)
== Series Details == Series: drm/i915/dp: Modeset only the tiled connectors with CRTC (rev2) URL : https://patchwork.freedesktop.org/series/72559/ State : success == Summary == CI Bug Log - changes from CI_DRM_7827 -> Patchwork_16281 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16281/index.html Known issues Here are the changes found in Patchwork_16281 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@module-reload: - fi-icl-guc: [PASS][1] -> [DMESG-WARN][2] ([i915#109]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-icl-guc/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16281/fi-icl-guc/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][3] -> [DMESG-FAIL][4] ([i915#553] / [i915#725]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-hsw-4770r/igt@i915_selftest@live_blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16281/fi-hsw-4770r/igt@i915_selftest@live_blt.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-n2820: [INCOMPLETE][5] ([i915#45]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16281/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][7] ([i915#553] / [i915#725]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-hsw-4770/igt@i915_selftest@live_blt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16281/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_hangcheck: - fi-icl-u3: [INCOMPLETE][9] ([fdo#108569] / [i915#140]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16281/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109 [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140 [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 Participating hosts (46 -> 38) -- Additional (3): fi-cfl-8109u fi-gdg-551 fi-ivb-3770 Missing(11): fi-ilk-m540 fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-cfl-8700k fi-cfl-guc fi-kbl-7500u fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7827 -> Patchwork_16281 CI-20190529: 20190529 CI_DRM_7827: c8969aeacfff681c83a800e82b0f18a6ab3e77ea @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5389: 966c58649dee31bb5bf2fad92f75ffd365968b81 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16281: 37497c9a2541d7074ea72436475569bdaacd2bea @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 37497c9a2541 drm/i915/dp: Modeset only the tiled connectors with CRTC == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16281/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/7] drm/i915/uc: Abort early on uc_init failure
On 1/14/20 5:31 PM, Daniele Ceraolo Spurio wrote:
> Now that we can differentiate wants vs uses GuC/HuC, intel_uc_init is
> restricted to running only if we have successfully fetched the required
> blob(s) and are committed to using the microcontroller(s).
> The only remaining thing that can go wrong in uc_init is the allocation
> of GuC/HuC related objects; if we get such a failure better to bail out
> immediately instead of wedging later, like we do for e.g.
> intel_engines_init, since without objects we can't use the HW, including
> not being able to attempt the firmware load.
>
> While at it, remove the unneeded fw_cleanup call (this is handled
> outside of gt_init) and add a probe failure injection point for testing.
> Also, update the logs for uc_init failures to probe_failure() since
> they will cause the driver load to fail.
Reviewed-by: Fernando Pacheco
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Michal Wajdeczko
> Cc: John Harrison
> Cc: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 4 +++-
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 24 +---
> drivers/gpu/drm/i915/gt/uc/intel_uc.h | 4 ++--
> 5 files changed, 24 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index da2b6e2ae692..85f21f18c785 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -584,7 +584,9 @@ int intel_gt_init(struct intel_gt *gt)
> if (err)
> goto err_engines;
>
> - intel_uc_init(>->uc);
> + err = intel_uc_init(>->uc);
> + if (err)
> + goto err_engines;
>
> err = intel_gt_resume(gt);
> if (err)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 5d00a3b2d914..c46f5ae77348 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -376,7 +376,7 @@ int intel_guc_init(struct intel_guc *guc)
> intel_uc_fw_fini(&guc->fw);
> err_fetch:
> intel_uc_fw_cleanup_fetch(&guc->fw);
> - DRM_DEV_DEBUG_DRIVER(gt->i915->drm.dev, "failed with %d\n", ret);
> + i915_probe_error(gt->i915, "failed with %d\n", ret);
> return ret;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> index 32a069841c14..5f448d0e360b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> @@ -127,7 +127,7 @@ int intel_huc_init(struct intel_huc *huc)
> intel_uc_fw_fini(&huc->fw);
> out:
> intel_uc_fw_cleanup_fetch(&huc->fw);
> - DRM_DEV_DEBUG_DRIVER(i915->drm.dev, "failed with %d\n", err);
> + i915_probe_error(i915, "failed with %d\n", err);
> return err;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index 8843d4f16a7f..d57b731952ef 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -273,7 +273,7 @@ static void __uc_cleanup_firmwares(struct intel_uc *uc)
> intel_uc_fw_cleanup_fetch(&uc->guc.fw);
> }
>
> -static void __uc_init(struct intel_uc *uc)
> +static int __uc_init(struct intel_uc *uc)
> {
> struct intel_guc *guc = &uc->guc;
> struct intel_huc *huc = &uc->huc;
> @@ -282,19 +282,29 @@ static void __uc_init(struct intel_uc *uc)
> GEM_BUG_ON(!intel_uc_wants_guc(uc));
>
> if (!intel_uc_uses_guc(uc))
> - return;
> + return 0;
> +
> + if (i915_inject_probe_failure(uc_to_gt(uc)->i915))
> + return -ENOMEM;
>
> /* XXX: GuC submission is unavailable for now */
> GEM_BUG_ON(intel_uc_supports_guc_submission(uc));
>
> ret = intel_guc_init(guc);
> - if (ret) {
> - intel_uc_fw_cleanup_fetch(&huc->fw);
> - return;
> + if (ret)
> + return ret;
> +
> + if (intel_uc_uses_huc(uc)) {
> + ret = intel_huc_init(huc);
> + if (ret)
> + goto out_guc;
> }
>
> - if (intel_uc_uses_huc(uc))
> - intel_huc_init(huc);
> + return 0;
> +
> +out_guc:
> + intel_guc_fini(guc);
> + return ret;
> }
>
> static void __uc_fini(struct intel_uc *uc)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> index f2f7351ff22a..2d9f17196761 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> @@ -16,7 +16,7 @@ struct intel_uc_ops {
> int (*sanitize)(struct intel_uc *uc);
> void (*init_fw)(struct intel_uc *uc);
> void (*fini_fw)(struct intel_uc *uc);
> - void (*init)(struct intel_uc *uc);
> + int (*init)(struct intel_uc *uc);
> void (*fini)(struct intel_uc *uc);
> int (*i
Re: [Intel-gfx] [PATCH 3/7] drm/i915/uc: Improve tracking of uC init status
On 1/14/20 5:31 PM, Daniele Ceraolo Spurio wrote:
> To be able to setup GuC submission functions during engine init we need
> to commit to using GuC as soon as possible.
> Currently, the only thing that can stop us from using the
> microcontrollers once we've fetched the blobs is a fundamental
> error (e.g. OOM); given that if we hit such an error we can't really
> fall-back to anything, we can "officialize" the FW fetching completion
> as the moment at which we're committing to using GuC.
>
> To better differentiate this case, the uses_guc check, which indicates
> that GuC is supported and was selected in modparam, is renamed to
> wants_guc and a new uses_guc is introduced to represent the case were
> we're committed to using the GuC. Note that uses_guc does still not imply
> that the blob is actually loaded on the HW (is_running is the check for
> that). Also, since we need to have attempted the fetch for the result
> of uses_guc to be meaningful, we need to make sure we've moved away
> from INTEL_UC_FIRMWARE_SELECTED.
>
> All the GuC changes have been mirrored on the HuC for coherency.
Reviewed-by: Fernando Pacheco
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Chris Wilson
> Cc: Tvrtko Ursulin
> Cc: Michal Wajdeczko
> Cc: John Harrison
> Cc: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 8 +++-
> drivers/gpu/drm/i915/gt/uc/intel_huc.h| 8 +++-
> drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 23 +-
> drivers/gpu/drm/i915/gt/uc/intel_uc.h | 52 +++
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
> 6 files changed, 64 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index 910d49590068..f9e0be843992 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -143,11 +143,17 @@ static inline bool intel_guc_is_supported(struct
> intel_guc *guc)
> return intel_uc_fw_is_supported(&guc->fw);
> }
>
> -static inline bool intel_guc_is_enabled(struct intel_guc *guc)
> +static inline bool intel_guc_is_wanted(struct intel_guc *guc)
> {
> return intel_uc_fw_is_enabled(&guc->fw);
> }
>
> +static inline bool intel_guc_is_used(struct intel_guc *guc)
> +{
> + GEM_BUG_ON(__intel_uc_fw_status(&guc->fw) ==
> INTEL_UC_FIRMWARE_SELECTED);
> + return intel_uc_fw_is_available(&guc->fw);
> +}
> +
> static inline bool intel_guc_is_running(struct intel_guc *guc)
> {
> return intel_uc_fw_is_running(&guc->fw);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
> index 644c059fe01d..a40b9cfc6c22 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
> @@ -41,11 +41,17 @@ static inline bool intel_huc_is_supported(struct
> intel_huc *huc)
> return intel_uc_fw_is_supported(&huc->fw);
> }
>
> -static inline bool intel_huc_is_enabled(struct intel_huc *huc)
> +static inline bool intel_huc_is_wanted(struct intel_huc *huc)
> {
> return intel_uc_fw_is_enabled(&huc->fw);
> }
>
> +static inline bool intel_huc_is_used(struct intel_huc *huc)
> +{
> + GEM_BUG_ON(__intel_uc_fw_status(&huc->fw) ==
> INTEL_UC_FIRMWARE_SELECTED);
> + return intel_uc_fw_is_available(&huc->fw);
> +}
> +
> static inline bool intel_huc_is_authenticated(struct intel_huc *huc)
> {
> return intel_uc_fw_is_running(&huc->fw);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> index eee193bf2cc4..fd7d04690ded 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> @@ -20,7 +20,7 @@ void intel_huc_fw_init_early(struct intel_huc *huc)
> struct drm_i915_private *i915 = gt->i915;
>
> intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC,
> -intel_uc_uses_guc(uc),
> +intel_uc_supports_guc(uc),
> INTEL_INFO(i915)->platform, INTEL_REVID(i915));
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index 64934a876a50..8843d4f16a7f 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -48,17 +48,17 @@ static void __confirm_options(struct intel_uc *uc)
> DRM_DEV_DEBUG_DRIVER(i915->drm.dev,
>"enable_guc=%d (guc:%s submission:%s huc:%s)\n",
>i915_modparams.enable_guc,
> - yesno(intel_uc_uses_guc(uc)),
> + yesno(intel_uc_wants_guc(uc)),
>yesno(intel_uc_uses_guc_submission(uc)),
> - yesno(intel_uc_uses_huc(uc)));
> + yesno(intel_uc_wants_huc(uc)));
>
> if (i915_modparams.enable_
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: Modeset only the tiled connectors with CRTC (rev2)
== Series Details == Series: drm/i915/dp: Modeset only the tiled connectors with CRTC (rev2) URL : https://patchwork.freedesktop.org/series/72559/ State : warning == Summary == $ dim checkpatch origin/drm-tip 37497c9a2541 drm/i915/dp: Modeset only the tiled connectors with CRTC -:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #11: that the connector has a CRTC before forcing a modeset on that else it fails total: 0 errors, 1 warnings, 0 checks, 37 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Lift set-wedged engine dumping out of user paths (rev2)
== Series Details ==
Series: drm/i915/gt: Lift set-wedged engine dumping out of user paths (rev2)
URL : https://patchwork.freedesktop.org/series/72611/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7827 -> Patchwork_16279
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16279/index.html
Known issues
Here are the changes found in Patchwork_16279 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rpm@basic-rte:
- fi-hsw-4770:[PASS][1] -> [SKIP][2] ([fdo#109271]) +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-hsw-4770/igt@i915_pm_...@basic-rte.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16279/fi-hsw-4770/igt@i915_pm_...@basic-rte.html
Possible fixes
* igt@i915_selftest@live_blt:
- fi-hsw-4770:[DMESG-FAIL][3] ([i915#553] / [i915#725]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-hsw-4770/igt@i915_selftest@live_blt.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16279/fi-hsw-4770/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [INCOMPLETE][5] ([fdo#108569] / [i915#140]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16279/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#998]: https://gitlab.freedesktop.org/drm/intel/issues/998
Participating hosts (46 -> 36)
--
Additional (3): fi-cfl-8109u fi-skl-6600u fi-bsw-n3050
Missing(13): fi-ilk-m540 fi-byt-j1900 fi-byt-squawks fi-bsw-cyan
fi-bwr-2160 fi-ctg-p8600 fi-whl-u fi-bsw-kefka fi-skl-lmem fi-byt-n2820
fi-byt-clapper fi-bsw-nick fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7827 -> Patchwork_16279
CI-20190529: 20190529
CI_DRM_7827: c8969aeacfff681c83a800e82b0f18a6ab3e77ea @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5389: 966c58649dee31bb5bf2fad92f75ffd365968b81 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16279: 5eb050655662d644bd793673c023e8fbbb14ae22 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5eb050655662 drm/i915/gt: Lift set-wedged engine dumping out of user paths
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16279/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Acquire ce->active before ce->pin_count/ce->pin_mutex
== Series Details == Series: drm/i915/gt: Acquire ce->active before ce->pin_count/ce->pin_mutex URL : https://patchwork.freedesktop.org/series/72626/ State : failure == Summary == Applying: drm/i915/gt: Acquire ce->active before ce->pin_count/ce->pin_mutex Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gt/intel_context.c M drivers/gpu/drm/i915/i915_active.h Falling back to patching base and 3-way merge... No changes -- Patch already applied. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests/perf: measure memcpy bw between regions
== Series Details == Series: drm/i915/selftests/perf: measure memcpy bw between regions URL : https://patchwork.freedesktop.org/series/72621/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7827 -> Patchwork_16278 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16278 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16278, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16278/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16278: ### IGT changes ### Possible regressions * igt@i915_selftest@live_gem_contexts: - fi-byt-j1900: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16278/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html Known issues Here are the changes found in Patchwork_16278 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-j1900: [PASS][3] -> [TIMEOUT][4] ([fdo#112271] / [i915#816]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16278/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#111407]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16278/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][7] ([i915#553] / [i915#725]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-hsw-4770/igt@i915_selftest@live_blt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16278/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_hangcheck: - fi-icl-u3: [INCOMPLETE][9] ([fdo#108569] / [i915#140]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16278/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 Participating hosts (46 -> 43) -- Additional (5): fi-bsw-n3050 fi-gdg-551 fi-cfl-8109u fi-ivb-3770 fi-skl-6600u Missing(8): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-x1275 fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7827 -> Patchwork_16278 CI-20190529: 20190529 CI_DRM_7827: c8969aeacfff681c83a800e82b0f18a6ab3e77ea @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5389: 966c58649dee31bb5bf2fad92f75ffd365968b81 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16278: a5ec4dca083a83834ed122d8a96655ad4d05c205 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a5ec4dca083a drm/i915/selftests/perf: measure memcpy bw between regions == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16278/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/6] drm/i915/gt: Hook up CS_MASTER_ERROR_INTERRUPT
Now that we have offline error capture and can reset an engine from
inside an atomic context while also preserving the GPU state for
post-mortem analysis, it is time to handle error interrupts thrown by
the command parser.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 8 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 10 ++
drivers/gpu/drm/i915/gt/intel_gt.c | 5 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 19 ++-
drivers/gpu/drm/i915/gt/intel_lrc.c | 54 --
drivers/gpu/drm/i915/gt/selftest_lrc.c | 166 +--
drivers/gpu/drm/i915/i915_gpu_error.c| 2 +
drivers/gpu/drm/i915/i915_gpu_error.h| 1 +
drivers/gpu/drm/i915/i915_reg.h | 5 +-
9 files changed, 237 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 841fe1a4b0a5..4a2693fb5f8d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1299,8 +1299,14 @@ static void intel_engine_print_registers(struct
intel_engine_cs *engine,
}
if (INTEL_GEN(dev_priv) >= 6) {
- drm_printf(m, "\tRING_IMR: %08x\n",
+ drm_printf(m, "\tRING_IMR: 0x%08x\n",
ENGINE_READ(engine, RING_IMR));
+ drm_printf(m, "\tRING_ESR: 0x%08x\n",
+ ENGINE_READ(engine, RING_ESR));
+ drm_printf(m, "\tRING_EMR: 0x%08x\n",
+ ENGINE_READ(engine, RING_EMR));
+ drm_printf(m, "\tRING_EIR: 0x%08x\n",
+ ENGINE_READ(engine, RING_EIR));
}
addr = intel_engine_get_active_head(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 58725024ffa4..c7ea986878c3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -165,6 +165,16 @@ struct intel_engine_execlists {
*/
u32 yield;
+ /**
+* @error_interrupt: CS Master EIR
+*
+* The CS generates an interrupt when it detects an error. We capture
+* the first error interrupt, record the EIR and schedule the tasklet.
+* In the tasklet, we process the pending CS events to ensure we have
+* the guilty request, and then reset the engine.
+*/
+ u32 error_interrupt;
+
/**
* @no_priolist: priority lists disabled
*/
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 88b6c904607c..143268083135 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -455,6 +455,11 @@ static int __engines_record_defaults(struct intel_gt *gt)
if (!rq)
continue;
+ if (rq->fence.error) {
+ err = -EIO;
+ goto out;
+ }
+
GEM_BUG_ON(!test_bit(CONTEXT_ALLOC_BIT, &rq->context->flags));
state = rq->context->state;
if (!state)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index cf8c71eb6d16..68557a263009 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -24,6 +24,21 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
{
bool tasklet = false;
+ if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) {
+ u32 eir;
+
+ eir = ENGINE_READ(engine, RING_EIR);
+ ENGINE_TRACE(engine, "CS error: %x\n", eir);
+
+ /* Disable the error interrupt until after the reset */
+ if (likely(eir)) {
+ ENGINE_WRITE(engine, RING_EMR, ~0u);
+ ENGINE_WRITE(engine, RING_EIR, eir);
+ engine->execlists.error_interrupt = eir;
+ tasklet = true;
+ }
+ }
+
if (iir & GT_WAIT_SEMAPHORE_INTERRUPT) {
WRITE_ONCE(engine->execlists.yield,
ENGINE_READ_FW(engine, EXECLIST_CCID));
@@ -218,6 +233,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
void gen11_gt_irq_postinstall(struct intel_gt *gt)
{
const u32 irqs =
+ GT_CS_MASTER_ERROR_INTERRUPT |
GT_RENDER_USER_INTERRUPT |
GT_CONTEXT_SWITCH_INTERRUPT |
GT_WAIT_SEMAPHORE_INTERRUPT;
@@ -289,7 +305,7 @@ void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)
if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
GT_BSD_CS_ERROR_INTERRUPT |
- GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
+ GT_CS_MASTER_ERROR_INTERRUPT))
DRM_DEBUG("Command parser error, gt_iir 0x%08x\n",
[Intel-gfx] [PATCH 2/6] drm/i915/gt: Reorganise gen8+ interrupt handler
We always use a deferred bottom-half (either tasklet or irq_work) for
processing the response to an interrupt which means we can recombine the
GT irq ack+handler into one. This simplicity is important in later
patches as we will need to handle and then ack multiple interrupt levels
before acking the GT and master interrupts.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 70 +++---
drivers/gpu/drm/i915/gt/intel_gt_irq.h | 3 +-
drivers/gpu/drm/i915/i915_irq.c| 10 +---
3 files changed, 33 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index f796bdf1ed30..71873a4cafc0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -286,59 +286,49 @@ void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)
gen7_parity_error_irq_handler(gt, gt_iir);
}
-void gen8_gt_irq_ack(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4])
+void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl)
{
void __iomem * const regs = gt->uncore->regs;
+ u32 iir;
if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
- gt_iir[0] = raw_reg_read(regs, GEN8_GT_IIR(0));
- if (likely(gt_iir[0]))
- raw_reg_write(regs, GEN8_GT_IIR(0), gt_iir[0]);
- }
-
- if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
- gt_iir[1] = raw_reg_read(regs, GEN8_GT_IIR(1));
- if (likely(gt_iir[1]))
- raw_reg_write(regs, GEN8_GT_IIR(1), gt_iir[1]);
- }
-
- if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
- gt_iir[2] = raw_reg_read(regs, GEN8_GT_IIR(2));
- if (likely(gt_iir[2]))
- raw_reg_write(regs, GEN8_GT_IIR(2), gt_iir[2]);
- }
-
- if (master_ctl & GEN8_GT_VECS_IRQ) {
- gt_iir[3] = raw_reg_read(regs, GEN8_GT_IIR(3));
- if (likely(gt_iir[3]))
- raw_reg_write(regs, GEN8_GT_IIR(3), gt_iir[3]);
- }
-}
-
-void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4])
-{
- if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
- cs_irq_handler(gt->engine_class[RENDER_CLASS][0],
- gt_iir[0] >> GEN8_RCS_IRQ_SHIFT);
- cs_irq_handler(gt->engine_class[COPY_ENGINE_CLASS][0],
- gt_iir[0] >> GEN8_BCS_IRQ_SHIFT);
+ iir = raw_reg_read(regs, GEN8_GT_IIR(0));
+ if (likely(iir)) {
+ cs_irq_handler(gt->engine_class[RENDER_CLASS][0],
+ iir >> GEN8_RCS_IRQ_SHIFT);
+ cs_irq_handler(gt->engine_class[COPY_ENGINE_CLASS][0],
+ iir >> GEN8_BCS_IRQ_SHIFT);
+ raw_reg_write(regs, GEN8_GT_IIR(0), iir);
+ }
}
if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
- cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][0],
- gt_iir[1] >> GEN8_VCS0_IRQ_SHIFT);
- cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][1],
- gt_iir[1] >> GEN8_VCS1_IRQ_SHIFT);
+ iir = raw_reg_read(regs, GEN8_GT_IIR(1));
+ if (likely(iir)) {
+ cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][0],
+ iir >> GEN8_VCS0_IRQ_SHIFT);
+ cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][1],
+ iir >> GEN8_VCS1_IRQ_SHIFT);
+ raw_reg_write(regs, GEN8_GT_IIR(1), iir);
+ }
}
if (master_ctl & GEN8_GT_VECS_IRQ) {
- cs_irq_handler(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0],
- gt_iir[3] >> GEN8_VECS_IRQ_SHIFT);
+ iir = raw_reg_read(regs, GEN8_GT_IIR(3));
+ if (likely(iir)) {
+
cs_irq_handler(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0],
+ iir >> GEN8_VECS_IRQ_SHIFT);
+ raw_reg_write(regs, GEN8_GT_IIR(3), iir);
+ }
}
if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
- gen6_rps_irq_handler(>->rps, gt_iir[2]);
- guc_irq_handler(>->uc.guc, gt_iir[2] >> 16);
+ iir = raw_reg_read(regs, GEN8_GT_IIR(2));
+ if (likely(iir)) {
+ gen6_rps_irq_handler(>->rps, iir);
+ guc_irq_handler(>->uc.guc, iir >> 16);
+ raw_reg_write(regs, GEN8_GT_IIR(2), iir);
+ }
}
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.h
b/drivers/gpu/drm/i915/gt/intel_gt_irq.h
index 8f37
[Intel-gfx] [PATCH 4/6] drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore
If we find ourselves waiting on a MI_SEMAPHORE_WAIT, either within the
user batch or in our own preamble, the engine raises a
GT_WAIT_ON_SEMAPHORE interrupt. We can unmask that interrupt and so
respond to a semaphore wait by yielding the timeslice, if we have
another context to yield to!
The only real complication is that the interrupt is only generated for
the start of the semaphore wait, and is asynchronous to our
process_csb() -- that is, we may not have registered the timeslice before
we see the interrupt. To ensure we don't miss a potential semaphore
blocking forward progress (e.g. selftests/live_timeslice_preempt) we mark
the interrupt and apply it to the next timeslice regardless of whether it
was active at the time.
v2: We use semaphores in preempt-to-busy, within the timeslicing
implementation itself! Ergo, when we do insert a preemption due to an
expired timeslice, the new context may start with the missed semaphore
flagged by the retired context and be yielded, ad infinitum. To avoid
this, read the context id at the time of the semaphore interrupt and
only yield if that context is still active.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 6
drivers/gpu/drm/i915/gt/intel_engine_types.h | 9 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 17 +++--
drivers/gpu/drm/i915/gt/intel_lrc.c | 36
drivers/gpu/drm/i915/i915_reg.h | 5 +++
5 files changed, 65 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 9b965d1f811d..841fe1a4b0a5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1277,6 +1277,12 @@ static void intel_engine_print_registers(struct
intel_engine_cs *engine,
if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
+ if (HAS_EXECLISTS(dev_priv)) {
+ drm_printf(m, "\tEL_CCID:0x%08x\n",
+ ENGINE_READ(engine, EXECLIST_CCID));
+ drm_printf(m, "\tEL_STATUS: 0x%08x\n",
+ ENGINE_READ(engine, EXECLIST_STATUS));
+ }
drm_printf(m, "\tRING_START: 0x%08x\n",
ENGINE_READ(engine, RING_START));
drm_printf(m, "\tRING_HEAD: 0x%08x\n",
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 92be41a6903c..58725024ffa4 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -156,6 +156,15 @@ struct intel_engine_execlists {
*/
struct i915_priolist default_priolist;
+ /**
+* @yield: CCID at the time of the last semaphore-wait interrupt.
+*
+* Instead of leaving a semaphore busy-spinning on an engine, we would
+* like to switch to another ready context, i.e. yielding the semaphore
+* timeslice.
+*/
+ u32 yield;
+
/**
* @no_priolist: priority lists disabled
*/
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 7278b10e1a03..cf8c71eb6d16 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -24,6 +24,13 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
{
bool tasklet = false;
+ if (iir & GT_WAIT_SEMAPHORE_INTERRUPT) {
+ WRITE_ONCE(engine->execlists.yield,
+ ENGINE_READ_FW(engine, EXECLIST_CCID));
+ if (del_timer(&engine->execlists.timer))
+ tasklet = true;
+ }
+
if (iir & GT_CONTEXT_SWITCH_INTERRUPT)
tasklet = true;
@@ -210,7 +217,10 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
void gen11_gt_irq_postinstall(struct intel_gt *gt)
{
- const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
+ const u32 irqs =
+ GT_RENDER_USER_INTERRUPT |
+ GT_CONTEXT_SWITCH_INTERRUPT |
+ GT_WAIT_SEMAPHORE_INTERRUPT;
struct intel_uncore *uncore = gt->uncore;
const u32 dmask = irqs << 16 | irqs;
const u32 smask = irqs << 16;
@@ -345,7 +355,10 @@ void gen8_gt_irq_reset(struct intel_gt *gt)
void gen8_gt_irq_postinstall(struct intel_gt *gt)
{
/* These are interrupts we'll toggle with the ring mask register */
- const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
+ const u32 irqs =
+ GT_RENDER_USER_INTERRUPT |
+ GT_CONTEXT_SWITCH_INTERRUPT |
+ GT_WAIT_SEMAPHORE_INTERRUPT;
const u32 gt_interrupts[] = {
irqs << GEN8_RCS_IRQ_SHIFT | irqs << GEN8_BCS_IRQ_SHIFT,
irqs << GEN8_VCS0_IRQ_SHIFT | irqs << GEN8_VCS
[Intel-gfx] [PATCH 6/6] drm/i915/gt: Lift set-wedged engine dumping out of user paths
The user (e.g. gem_eio) can manipulate the driver into wedging itself,
allowing the user to trigger voluminous logging of inconsequential
details. If we lift the dump to direct calls to intel_gt_set_wedged(),
out of the intel_reset failure handling, we keep the detail logging for
what we expect are true HW or test failures without being tricked.
Reported-by: Tomi Sarvela
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tomi Sarvela
---
drivers/gpu/drm/i915/gt/intel_reset.c | 30 +++
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index beee0cf89bce..423a02506b2d 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -800,13 +800,6 @@ static void __intel_gt_set_wedged(struct intel_gt *gt)
if (test_bit(I915_WEDGED, >->reset.flags))
return;
- if (GEM_SHOW_DEBUG() && !intel_engines_are_idle(gt)) {
- struct drm_printer p = drm_debug_printer(__func__);
-
- for_each_engine(engine, gt, id)
- intel_engine_dump(engine, &p, "%s\n", engine->name);
- }
-
GT_TRACE(gt, "start\n");
/*
@@ -845,10 +838,29 @@ void intel_gt_set_wedged(struct intel_gt *gt)
{
intel_wakeref_t wakeref;
+ if (test_bit(I915_WEDGED, >->reset.flags))
+ return;
+
+ wakeref = intel_runtime_pm_get(gt->uncore->rpm);
mutex_lock(>->reset.mutex);
- with_intel_runtime_pm(gt->uncore->rpm, wakeref)
- __intel_gt_set_wedged(gt);
+
+ if (GEM_SHOW_DEBUG() && !intel_engines_are_idle(gt)) {
+ struct drm_printer p = drm_debug_printer(__func__);
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ for_each_engine(engine, gt, id) {
+ if (intel_engine_is_idle(engine))
+ continue;
+
+ intel_engine_dump(engine, &p, "%s\n", engine->name);
+ }
+ }
+
+ __intel_gt_set_wedged(gt);
+
mutex_unlock(>->reset.mutex);
+ intel_runtime_pm_put(gt->uncore->rpm, wakeref);
}
static bool __intel_gt_unset_wedged(struct intel_gt *gt)
--
2.25.0
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[Intel-gfx] [PATCH 3/6] drm/i915/gt: Tidy repetition in declaring gen8+ interrupts
We use the same interrupt mask for each engine, so define it once in a
local and reuse.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 22 ++
1 file changed, 6 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 71873a4cafc0..7278b10e1a03 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -344,25 +344,15 @@ void gen8_gt_irq_reset(struct intel_gt *gt)
void gen8_gt_irq_postinstall(struct intel_gt *gt)
{
- struct intel_uncore *uncore = gt->uncore;
-
/* These are interrupts we'll toggle with the ring mask register */
- u32 gt_interrupts[] = {
- (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
-GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
-GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
-GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT),
-
- (GT_RENDER_USER_INTERRUPT << GEN8_VCS0_IRQ_SHIFT |
-GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS0_IRQ_SHIFT |
-GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
-GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT),
-
+ const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
+ const u32 gt_interrupts[] = {
+ irqs << GEN8_RCS_IRQ_SHIFT | irqs << GEN8_BCS_IRQ_SHIFT,
+ irqs << GEN8_VCS0_IRQ_SHIFT | irqs << GEN8_VCS1_IRQ_SHIFT,
0,
-
- (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
-GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT)
+ irqs << GEN8_VECS_IRQ_SHIFT,
};
+ struct intel_uncore *uncore = gt->uncore;
gt->pm_ier = 0x0;
gt->pm_imr = ~gt->pm_ier;
--
2.25.0
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[Intel-gfx] [PATCH 1/6] drm/i915: Skip capturing errors from internal contexts
We don't want to report errors on the internal contexts to userspace,
suppressing their own, so treat them as simulated errors. These mostly
arise inside selftests and so are simulated anyway. For the rest, we can
rely on the normal debug channels in CI.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gpu_error.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 594341e27a47..0f67bef83106 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1228,7 +1228,7 @@ static bool record_context(struct
i915_gem_context_coredump *e,
{
struct i915_gem_context *ctx;
struct task_struct *task;
- bool capture;
+ bool simulated;
rcu_read_lock();
ctx = rcu_dereference(rq->context->gem_context);
@@ -1236,7 +1236,7 @@ static bool record_context(struct
i915_gem_context_coredump *e,
ctx = NULL;
rcu_read_unlock();
if (!ctx)
- return false;
+ return true;
rcu_read_lock();
task = pid_task(ctx->pid, PIDTYPE_PID);
@@ -1250,10 +1250,10 @@ static bool record_context(struct
i915_gem_context_coredump *e,
e->guilty = atomic_read(&ctx->guilty_count);
e->active = atomic_read(&ctx->active_count);
- capture = i915_gem_context_no_error_capture(ctx);
+ simulated = i915_gem_context_no_error_capture(ctx);
i915_gem_context_put(ctx);
- return capture;
+ return simulated;
}
struct intel_engine_capture_vma {
--
2.25.0
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Re: [Intel-gfx] linux-next: manual merge of the generic-ioremap tree with the drm-intel tree
Hi all,
On Wed, 8 Jan 2020 17:08:03 +1100 Stephen Rothwell
wrote:
>
> Today's linux-next merge of the generic-ioremap tree got a conflict in:
>
> drivers/gpu/drm/i915/i915_gem_gtt.c
>
> between commit:
>
> 2c86e55d2ab5 ("drm/i915/gtt: split up i915_gem_gtt")
>
> from the drm-intel tree and commit:
>
> 4bdc0d676a64 ("remove ioremap_nocache and devm_ioremap_nocache")
>
> from the generic-ioremap tree.
>
> I fixed it up (I used the file from the former and added the following
> merge fix patch) and can carry the fix as necessary. This is now fixed
> as far as linux-next is concerned, but any non trivial conflicts should
> be mentioned to your upstream maintainer when your tree is submitted for
> merging. You may also want to consider cooperating with the maintainer
> of the conflicting tree to minimise any particularly complex conflicts.
>
> From: Stephen Rothwell
> Date: Wed, 8 Jan 2020 17:04:59 +1100
> Subject: [PATCH] fix up for "drm/i915/gtt: split up i915_gem_gtt"
>
> Signed-off-by: Stephen Rothwell
> ---
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 99189cdba8a9..1a2b5dcde960 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -801,7 +801,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64
> size)
>* readback check when writing GTT PTE entries.
>*/
> if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
> - ggtt->gsm = ioremap_nocache(phys_addr, size);
> + ggtt->gsm = ioremap(phys_addr, size);
> else
> ggtt->gsm = ioremap_wc(phys_addr, size);
> if (!ggtt->gsm) {
> --
> 2.24.0
This is now a conflict between the drm tree and Linus' tree.
--
Cheers,
Stephen Rothwell
pgp7688N9RO1e.pgp
Description: OpenPGP digital signature
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dp: Modeset only the tiled connectors with CRTC
On Sat, Jan 25, 2020 at 01:31:06AM -0800, Saarinen, Jani wrote: > + Martin to re-report. Could you re-report this so we get the full CI IGT results? Manasi > > > -Original Message- > > From: Navare, Manasi D > > Sent: lauantai 25. tammikuuta 2020 4.19 > > To: intel-gfx@lists.freedesktop.org > > Cc: Sarvela, Tomi P ; Saarinen, Jani > > ; Nautiyal, Ankit K ; > > Nikkanen, Kimmo > > Subject: RE: ✗ Fi.CI.BAT: failure for drm/i915/dp: Modeset only the tiled > > connectors > > with CRTC > > > > This Gem related failure is not relevant to this patch, but because of this > > it doesn’t > > run full IGT, I want to make sure that the kms_flip tests are not getting > > hung. > > > > Or can we confirm this with manual testing? > > > > Manasi > > > > -Original Message- > > From: Patchwork > > Sent: Friday, January 24, 2020 5:47 PM > > To: Navare, Manasi D > > Cc: intel-gfx@lists.freedesktop.org > > Subject: ✗ Fi.CI.BAT: failure for drm/i915/dp: Modeset only the tiled > > connectors > > with CRTC > > > > == Series Details == > > > > Series: drm/i915/dp: Modeset only the tiled connectors with CRTC > > URL : https://patchwork.freedesktop.org/series/72559/ > > State : failure > > > > == Summary == > > > > CI Bug Log - changes from CI_DRM_7811 -> Patchwork_16267 > > > > > > Summary > > --- > > > > **FAILURE** > > > > Serious unknown changes coming with Patchwork_16267 absolutely need to be > > verified manually. > > > > If you think the reported changes have nothing to do with the changes > > introduced in Patchwork_16267, please notify your bug team to allow them > > to document this new failure mode, which will reduce false positives in > > CI. > > > > External URL: https://intel-gfx-ci.01.org/tree/drm- > > tip/Patchwork_16267/index.html > > > > Possible new issues > > --- > > > > Here are the unknown changes that may have been introduced in > > Patchwork_16267: > > > > ### IGT changes ### > > > > Possible regressions > > > > * igt@gem_close_race@basic-threads: > > - fi-hsw-peppy: [PASS][1] -> [INCOMPLETE][2] > >[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-hsw- > > peppy/igt@gem_close_r...@basic-threads.html > >[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-hsw- > > peppy/igt@gem_close_r...@basic-threads.html > > > > > > Known issues > > > > > > Here are the changes found in Patchwork_16267 that come from known issues: > > > > ### IGT changes ### > > > > Issues hit > > > > * igt@kms_chamelium@hdmi-hpd-fast: > > - fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#111096] / [i915#323]) > >[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-kbl- > > 7500u/igt@kms_chamel...@hdmi-hpd-fast.html > >[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-kbl- > > 7500u/igt@kms_chamel...@hdmi-hpd-fast.html > > > > > > Possible fixes > > > > * igt@gem_exec_parallel@fds: > > - fi-byt-n2820: [TIMEOUT][5] ([fdo#112271]) -> [PASS][6] > >[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-byt- > > n2820/igt@gem_exec_paral...@fds.html > >[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-byt- > > n2820/igt@gem_exec_paral...@fds.html > > > > * igt@i915_module_load@reload-with-fault-injection: > > - fi-cfl-8700k: [DMESG-WARN][7] ([i915#889]) -> [PASS][8] > >[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-cfl- > > 8700k/igt@i915_module_l...@reload-with-fault-injection.html > >[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-cfl- > > 8700k/igt@i915_module_l...@reload-with-fault-injection.html > > > > * igt@i915_selftest@live_blt: > > - fi-hsw-4770:[DMESG-FAIL][9] ([i915#725]) -> [PASS][10] > >[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-hsw- > > 4770/igt@i915_selftest@live_blt.html > >[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-hsw- > > 4770/igt@i915_selftest@live_blt.html > > > > * igt@i915_selftest@live_gem_contexts: > > - fi-byt-n2820: [DMESG-FAIL][11] ([i915#722]) -> [PASS][12] > >[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-byt- > > n2820/igt@i915_selftest@live_gem_contexts.html > >[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-byt- > > n2820/igt@i915_selftest@live_gem_contexts.html > > > > * igt@i915_selftest@live_gtt: > > - fi-bdw-5557u: [TIMEOUT][13] ([fdo#112271]) -> [PASS][14] > >[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7811/fi-bdw- > > 5557u/igt@i915_selftest@live_gtt.html > >[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16267/fi-bdw- > > 5557u/igt@i915_selftest@live_gtt.html > > > > > > Warnings > > > > * igt@gem_exec_parallel@contexts: > > - fi-byt-n2820: [FAIL][15] ([i915#694]) -
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/selftests/perf: measure memcpy bw between regions
== Series Details == Series: drm/i915/selftests/perf: measure memcpy bw between regions URL : https://patchwork.freedesktop.org/series/72621/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/selftests/perf: measure memcpy bw between regions +drivers/gpu/drm/i915/selftests/intel_memory_region.c:613:5: warning: symbol '_perf_memcpy' was not declared. Should it be static? +drivers/gpu/drm/i915/selftests/intel_memory_region.c:686:5: warning: symbol 'perf_memcpy' was not declared. Should it be static? ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests/perf: measure memcpy bw between regions
== Series Details == Series: drm/i915/selftests/perf: measure memcpy bw between regions URL : https://patchwork.freedesktop.org/series/72621/ State : warning == Summary == $ dim checkpatch origin/drm-tip a5ec4dca083a drm/i915/selftests/perf: measure memcpy bw between regions -:175: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #175: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:714: + if (ret) total: 0 errors, 1 warnings, 0 checks, 183 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsi: Enable dsi as part of encoder->enable
== Series Details == Series: drm/i915/dsi: Enable dsi as part of encoder->enable URL : https://patchwork.freedesktop.org/series/72619/ State : success == Summary == CI Bug Log - changes from CI_DRM_7827 -> Patchwork_16277 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16277/index.html Known issues Here are the changes found in Patchwork_16277 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_parallel@fds: - fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([i915#45]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-byt-j1900/igt@gem_exec_paral...@fds.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16277/fi-byt-j1900/igt@gem_exec_paral...@fds.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-n2820: [INCOMPLETE][3] ([i915#45]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16277/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_hangcheck: - fi-icl-u3: [INCOMPLETE][5] ([fdo#108569] / [i915#140]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16277/fi-icl-u3/igt@i915_selftest@live_hangcheck.html * igt@kms_flip@basic-flip-vs-dpms: - fi-icl-dsi: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-icl-dsi/igt@kms_f...@basic-flip-vs-dpms.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16277/fi-icl-dsi/igt@kms_f...@basic-flip-vs-dpms.html Warnings * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][9] ([i915#553] / [i915#725]) -> [DMESG-FAIL][10] ([i915#725]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-hsw-4770/igt@i915_selftest@live_blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16277/fi-hsw-4770/igt@i915_selftest@live_blt.html [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140 [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 Participating hosts (46 -> 44) -- Additional (5): fi-bsw-n3050 fi-gdg-551 fi-cfl-8109u fi-ivb-3770 fi-skl-6600u Missing(7): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7827 -> Patchwork_16277 CI-20190529: 20190529 CI_DRM_7827: c8969aeacfff681c83a800e82b0f18a6ab3e77ea @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5389: 966c58649dee31bb5bf2fad92f75ffd365968b81 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16277: 90cfe8a7b2cb1bccf85c8b718153f3a6ba60cc6c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 90cfe8a7b2cb drm/i915/dsi: Enable dsi as part of encoder->enable == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16277/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/tgl: Add Wa_1606054188;tgl
On Fri, Jan 17, 2020 at 04:16:28AM -0500, Matt Atwood wrote:
> On Tiger Lake we do not support source keying in the pixel formats P010,
> P012, P016.
>
> Bspec: 52890
> Cc: Matt Roper
> Signed-off-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index fca77ec1e0dd..67176524e60f 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -2049,6 +2049,19 @@ static int skl_plane_check_fb(const struct
> intel_crtc_state *crtc_state,
> unsigned int rotation = plane_state->hw.rotation;
> struct drm_format_name_buf format_name;
>
> + /* Wa_1606054188;tgl
^ This should be a :
> + *
> + * TODO: Add format RGB64i when implemented
> + *
> + */
> + if (IS_GEN(dev_priv, 12) &&
> + (plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE))
> + if (fb->format->format & (DRM_FORMAT_P010 | DRM_FORMAT_P012
> + | DRM_FORMAT_P016)) {
> + DRM_DEBUG_KMS("GEN12 does not support source color key
> planes in formats P01x\n");
> + return -EINVAL;
> + }
> +
I think this whole WA and check should be added after the check for !fb else we
might have a risk
of dereferencing a NULL pointer.
With the above fixs
Reviewed-by: Manasi Navare
Manasi
> if (!fb)
> return 0;
>
> --
> 2.21.1
>
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Re: [Intel-gfx] [PATCH 1/8] drm/edid: Check the number of detailed timing descriptors in the CEA ext block
On Fri, Jan 24, 2020 at 3:03 PM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> CEA-861 says :
> "d = offset for the byte following the reserved data block.
> If no data is provided in the reserved data block, then d=4.
> If no DTDs are provided, then d=0."
>
> So let's not look for DTDs when d==0. In fact let's just make that
> <4 since those values would just mean that he DTDs overlap the block
> header. And let's also check that d isn't so big as to declare
> the descriptors to live past the block end, although the code
> does already survive that case as we'd just end up with a negative
> number of descriptors and the loop would not do anything.
>
> Cc: Allen Chen
> Signed-off-by: Ville Syrjälä
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/drm_edid.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 99769d6c9f84..1b6e544cf5c7 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -2201,10 +2201,13 @@ typedef void detailed_cb(struct detailed_timing
> *timing, void *closure);
> static void
> cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
> {
> - int i, n = 0;
> + int i, n;
> u8 d = ext[0x02];
> u8 *det_base = ext + d;
>
> + if (d < 4 || d > 127)
> + return;
> +
> n = (127 - d) / 18;
> for (i = 0; i < n; i++)
> cb((struct detailed_timing *)(det_base + 18 * i), closure);
> --
> 2.24.1
>
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Re: [Intel-gfx] [PATCH 8/8] drm/edid: Dump bogus 18 byte descriptors
On Fri, Jan 24, 2020 at 3:03 PM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> I'm curious if there are any bogus 18 byte descriptors around.
> Let's dump them out if we encounter them.
>
> Not sure we'd actually want this, but at least I get to see
> if our CI has anything that hits this :)
>
> Signed-off-by: Ville Syrjälä
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/drm_edid.c | 22 +++---
> 1 file changed, 19 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 8e76efe1654d..4d8303e56536 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -2202,6 +2202,12 @@ static bool is_display_descriptor(const u8 d[18], u8
> tag)
> d[2] == 0x00 && d[3] == tag;
> }
>
> +static bool is_any_display_descriptor(const u8 d[18])
> +{
> + return d[0] == 0x00 && d[1] == 0x00 &&
> + d[2] == 0x00;
> +}
> +
> static bool is_detailed_timing_descriptor(const u8 d[18])
> {
> return d[0] != 0x00 || d[1] != 0x00;
> @@ -2209,6 +2215,15 @@ static bool is_detailed_timing_descriptor(const u8
> d[18])
>
> typedef void detailed_cb(const struct detailed_timing *timing, void
> *closure);
>
> +static void do_detailed_block(const u8 d[18], detailed_cb *cb, void *closure)
> +{
> + if (!is_detailed_timing_descriptor(d) &&
> + !is_any_display_descriptor(d))
> + DRM_WARN("Unrecognized 18 byte descriptor: %*ph\n", 18, d);
> +
> + cb((const struct detailed_timing *)d, closure);
> +}
> +
> static void
> cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
> {
> @@ -2221,7 +2236,7 @@ cea_for_each_detailed_block(const u8 *ext, detailed_cb
> *cb, void *closure)
>
> n = (127 - d) / 18;
> for (i = 0; i < n; i++)
> - cb((const struct detailed_timing *)(det_base + 18 * i),
> closure);
> + do_detailed_block(det_base + 18 * i, cb, closure);
> }
>
> static void
> @@ -2234,7 +2249,7 @@ vtb_for_each_detailed_block(const u8 *ext, detailed_cb
> *cb, void *closure)
> return; /* unknown version */
>
> for (i = 0; i < n; i++)
> - cb((const struct detailed_timing *)(det_base + 18 * i),
> closure);
> + do_detailed_block(det_base + 18 * i, cb, closure);
> }
>
> static void
> @@ -2247,7 +2262,8 @@ drm_for_each_detailed_block(const u8 *raw_edid,
> detailed_cb *cb, void *closure)
> return;
>
> for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
> - cb(&(edid->detailed_timings[i]), closure);
> + do_detailed_block((const u8 *)&edid->detailed_timings[i],
> + cb, closure);
>
> for (i = 1; i <= raw_edid[0x7e]; i++) {
> const u8 *ext = raw_edid + (i * EDID_LENGTH);
> --
> 2.24.1
>
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Re: [Intel-gfx] [PATCH 7/8] drm/edid: Constify lots of things
On Fri, Jan 24, 2020 at 3:03 PM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> Let's try to make a lot more stuff const in the edid parser.
>
> The "downside" is that we can no longer mangle the EDID in the
> middle of the parsing to apply quirks (drm_mode_detailed()).
> I don't really think mangling the blob itself is such a great
> idea anyway so I won't miss that part. But if we do want it
> back I guess we should do the mangling in one explicit place
> before we otherwise parse the EDID.
>
> Signed-off-by: Ville Syrjälä
I generally agree, but are there any userspace expectations that they
will be getting a corrected EDID in some cases?
Alex
> ---
> drivers/gpu/drm/drm_connector.c | 4 +-
> drivers/gpu/drm/drm_edid.c | 303 ++--
> include/drm/drm_connector.h | 4 +-
> 3 files changed, 176 insertions(+), 135 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index f632ca05960e..92a5cd6ff6b1 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -2377,7 +2377,7 @@ EXPORT_SYMBOL(drm_mode_put_tile_group);
> * tile group or NULL if not found.
> */
> struct drm_tile_group *drm_mode_get_tile_group(struct drm_device *dev,
> - char topology[8])
> + const u8 topology[8])
> {
> struct drm_tile_group *tg;
> int id;
> @@ -2407,7 +2407,7 @@ EXPORT_SYMBOL(drm_mode_get_tile_group);
> * new tile group or NULL.
> */
> struct drm_tile_group *drm_mode_create_tile_group(struct drm_device *dev,
> - char topology[8])
> + const u8 topology[8])
> {
> struct drm_tile_group *tg;
> int ret;
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index fd9b724067a7..8e76efe1654d 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -88,7 +88,7 @@
>
> struct detailed_mode_closure {
> struct drm_connector *connector;
> - struct edid *edid;
> + const struct edid *edid;
> bool preferred;
> u32 quirks;
> int modes;
> @@ -1584,8 +1584,8 @@ MODULE_PARM_DESC(edid_fixup,
> "Minimum number of valid EDID header bytes (0-8, default
> 6)");
>
> static void drm_get_displayid(struct drm_connector *connector,
> - struct edid *edid);
> -static int validate_displayid(u8 *displayid, int length, int idx);
> + const struct edid *edid);
> +static int validate_displayid(const u8 *displayid, int length, int idx);
>
> static int drm_edid_block_checksum(const u8 *raw_edid)
> {
> @@ -2207,41 +2207,41 @@ static bool is_detailed_timing_descriptor(const u8
> d[18])
> return d[0] != 0x00 || d[1] != 0x00;
> }
>
> -typedef void detailed_cb(struct detailed_timing *timing, void *closure);
> +typedef void detailed_cb(const struct detailed_timing *timing, void
> *closure);
>
> static void
> -cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
> +cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
> {
> int i, n;
> u8 d = ext[0x02];
> - u8 *det_base = ext + d;
> + const u8 *det_base = ext + d;
>
> if (d < 4 || d > 127)
> return;
>
> n = (127 - d) / 18;
> for (i = 0; i < n; i++)
> - cb((struct detailed_timing *)(det_base + 18 * i), closure);
> + cb((const struct detailed_timing *)(det_base + 18 * i),
> closure);
> }
>
> static void
> -vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
> +vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
> {
> unsigned int i, n = min((int)ext[0x02], 6);
> - u8 *det_base = ext + 5;
> + const u8 *det_base = ext + 5;
>
> if (ext[0x01] != 1)
> return; /* unknown version */
>
> for (i = 0; i < n; i++)
> - cb((struct detailed_timing *)(det_base + 18 * i), closure);
> + cb((const struct detailed_timing *)(det_base + 18 * i),
> closure);
> }
>
> static void
> -drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
> +drm_for_each_detailed_block(const u8 *raw_edid, detailed_cb *cb, void
> *closure)
> {
> + const struct edid *edid = (struct edid *)raw_edid;
> int i;
> - struct edid *edid = (struct edid *)raw_edid;
>
> if (edid == NULL)
> return;
> @@ -2250,7 +2250,7 @@ drm_for_each_detailed_block(u8 *raw_edid, detailed_cb
> *cb, void *closure)
> cb(&(edid->detailed_timings[i]), closure);
>
> for (i = 1; i <= raw_edid[0x7e]; i++) {
> - u8 *ext = raw_edid + (i * EDID_LENGTH);
> + const u8 *ext = raw_edid + (i * EDID_LENGTH);
>
Re: [Intel-gfx] [PATCH 3/8] drm/edid: Introduce is_detailed_timing_descritor()
On Fri, Jan 24, 2020 at 3:02 PM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> Let's introduce is_detailed_timing_descritor() as the opposite
> counterpart of is_display_descriptor().
>
> Cc: Allen Chen
> Signed-off-by: Ville Syrjälä
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/drm_edid.c | 42 ++
> 1 file changed, 24 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 96ae1fde4ce2..d6bce58b27ac 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -2202,6 +2202,11 @@ static bool is_display_descriptor(const u8 d[18], u8
> tag)
> d[2] == 0x00 && d[3] == tag;
> }
>
> +static bool is_detailed_timing_descriptor(const u8 d[18])
> +{
> + return d[0] != 0x00 || d[1] != 0x00;
> +}
> +
> typedef void detailed_cb(struct detailed_timing *timing, void *closure);
>
> static void
> @@ -3101,27 +3106,28 @@ do_detailed_mode(struct detailed_timing *timing, void
> *c)
> struct detailed_mode_closure *closure = c;
> struct drm_display_mode *newmode;
>
> - if (timing->pixel_clock) {
> - newmode = drm_mode_detailed(closure->connector->dev,
> - closure->edid, timing,
> - closure->quirks);
> - if (!newmode)
> - return;
> + if (!is_detailed_timing_descriptor((const u8 *)timing))
> + return;
> +
> + newmode = drm_mode_detailed(closure->connector->dev,
> + closure->edid, timing,
> + closure->quirks);
> + if (!newmode)
> + return;
>
> - if (closure->preferred)
> - newmode->type |= DRM_MODE_TYPE_PREFERRED;
> + if (closure->preferred)
> + newmode->type |= DRM_MODE_TYPE_PREFERRED;
>
> - /*
> -* Detailed modes are limited to 10kHz pixel clock resolution,
> -* so fix up anything that looks like CEA/HDMI mode, but the
> clock
> -* is just slightly off.
> -*/
> - fixup_detailed_cea_mode_clock(newmode);
> + /*
> +* Detailed modes are limited to 10kHz pixel clock resolution,
> +* so fix up anything that looks like CEA/HDMI mode, but the clock
> +* is just slightly off.
> +*/
> + fixup_detailed_cea_mode_clock(newmode);
>
> - drm_mode_probed_add(closure->connector, newmode);
> - closure->modes++;
> - closure->preferred = false;
> - }
> + drm_mode_probed_add(closure->connector, newmode);
> + closure->modes++;
> + closure->preferred = false;
> }
>
> /*
> --
> 2.24.1
>
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Re: [Intel-gfx] [PATCH 2/8] drm/edid: Don't accept any old garbage as a display descriptor
On Fri, Jan 24, 2020 at 3:02 PM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> Currently we assume any 18 byte descriptor to be a display descritor
> if only the tag byte matches the expected value. But for detailed
> timing descriptors that same byte is just the lower 8 bits of
> hblank, and as such can match any display descriptor tag. To
> properly validate that the 18 byte descriptor is in fact a
> display descriptor we must also examine bytes 0-2 (just byte 1
> should actually suffice but the spec does say that bytes 0 and
> 2 must also always be zero for display descriptors so we check
> those too).
>
> Unlike Allen's original proposed patch to just fix is_rb() we
> roll this out across the board to fix everything.
>
> Cc: Allen Chen
> Signed-off-by: Ville Syrjälä
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/drm_edid.c | 65 --
> 1 file changed, 41 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 1b6e544cf5c7..96ae1fde4ce2 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -2196,6 +2196,12 @@ struct drm_display_mode *drm_mode_find_dmt(struct
> drm_device *dev,
> }
> EXPORT_SYMBOL(drm_mode_find_dmt);
>
> +static bool is_display_descriptor(const u8 d[18], u8 tag)
> +{
> + return d[0] == 0x00 && d[1] == 0x00 &&
> + d[2] == 0x00 && d[3] == tag;
> +}
> +
> typedef void detailed_cb(struct detailed_timing *timing, void *closure);
>
> static void
> @@ -2257,9 +2263,12 @@ static void
> is_rb(struct detailed_timing *t, void *data)
> {
> u8 *r = (u8 *)t;
> - if (r[3] == EDID_DETAIL_MONITOR_RANGE)
> - if (r[15] & 0x10)
> - *(bool *)data = true;
> +
> + if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
> + return;
> +
> + if (r[15] & 0x10)
> + *(bool *)data = true;
> }
>
> /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
> @@ -2279,7 +2288,11 @@ static void
> find_gtf2(struct detailed_timing *t, void *data)
> {
> u8 *r = (u8 *)t;
> - if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
> +
> + if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
> + return;
> +
> + if (r[10] == 0x02)
> *(u8 **)data = r;
> }
>
> @@ -2818,7 +2831,7 @@ do_inferred_modes(struct detailed_timing *timing, void
> *c)
> struct detailed_non_pixel *data = &timing->data.other_data;
> struct detailed_data_monitor_range *range = &data->data.range;
>
> - if (data->type != EDID_DETAIL_MONITOR_RANGE)
> + if (!is_display_descriptor((const u8 *)timing,
> EDID_DETAIL_MONITOR_RANGE))
> return;
>
> closure->modes += drm_dmt_modes_for_range(closure->connector,
> @@ -2897,10 +2910,11 @@ static void
> do_established_modes(struct detailed_timing *timing, void *c)
> {
> struct detailed_mode_closure *closure = c;
> - struct detailed_non_pixel *data = &timing->data.other_data;
>
> - if (data->type == EDID_DETAIL_EST_TIMINGS)
> - closure->modes += drm_est3_modes(closure->connector, timing);
> + if (!is_display_descriptor((const u8 *)timing,
> EDID_DETAIL_EST_TIMINGS))
> + return;
> +
> + closure->modes += drm_est3_modes(closure->connector, timing);
> }
>
> /**
> @@ -2949,19 +2963,19 @@ do_standard_modes(struct detailed_timing *timing,
> void *c)
> struct detailed_non_pixel *data = &timing->data.other_data;
> struct drm_connector *connector = closure->connector;
> struct edid *edid = closure->edid;
> + int i;
>
> - if (data->type == EDID_DETAIL_STD_MODES) {
> - int i;
> - for (i = 0; i < 6; i++) {
> - struct std_timing *std;
> - struct drm_display_mode *newmode;
> + if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES))
> + return;
>
> - std = &data->data.timings[i];
> - newmode = drm_mode_std(connector, edid, std);
> - if (newmode) {
> - drm_mode_probed_add(connector, newmode);
> - closure->modes++;
> - }
> + for (i = 0; i < 6; i++) {
> + struct std_timing *std = &data->data.timings[i];
> + struct drm_display_mode *newmode;
> +
> + newmode = drm_mode_std(connector, edid, std);
> + if (newmode) {
> + drm_mode_probed_add(connector, newmode);
> + closure->modes++;
> }
> }
> }
> @@ -3056,10 +3070,11 @@ static void
> do_cvt_mode(struct detailed_timing *timing, void *c)
> {
> struct detailed_mode_closure *closure = c;
> - struct detailed_non_pixel *data = &timing->
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: Enable dsi as part of encoder->enable
== Series Details == Series: drm/i915/dsi: Enable dsi as part of encoder->enable URL : https://patchwork.freedesktop.org/series/72619/ State : warning == Summary == $ dim checkpatch origin/drm-tip 90cfe8a7b2cb drm/i915/dsi: Enable dsi as part of encoder->enable -:31: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #31: FILE: drivers/gpu/drm/i915/display/icl_dsi.c:1105: +static void gen11_dsi_enable(struct intel_encoder *encoder, +const struct intel_crtc_state *pipe_config, total: 0 errors, 0 warnings, 1 checks, 28 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 6/8] drm/edid: Add a FIXME about DispID CEA data block revision
On Fri, Jan 24, 2020 at 3:02 PM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> I don't understand what the DispID CEA data block revision
> means. The spec doesn't say. I guess some DispID must have
> a value of >= 3 in there or else we generally wouldn't
> even parse the CEA data blocks. Or does all this code
> actually not do anything?
>
> Cc: Andres Rodriguez
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_edid.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 0369a54e3d32..fd9b724067a7 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -3977,6 +3977,13 @@ cea_db_tag(const u8 *db)
> static int
> cea_revision(const u8 *cea)
> {
> + /*
> +* FIXME is this correct for the DispID variant?
> +* The DispID spec doesn't really specify whether
> +* this is the revision of the CEA extension or
> +* the DispID CEA data block. And the only value
> +* given as an example is 0.
> +*/
Same comment as the previous patch regarding the comment formatting.
Alex
> return cea[1];
> }
>
> --
> 2.24.1
>
> ___
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Re: [Intel-gfx] [PATCH 5/8] drm/edid: Document why we don't bounds check the DispID CEA block start/end
On Fri, Jan 24, 2020 at 3:03 PM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> After much head scratching I managed to convince myself that
> for_each_displayid_db() has already done the bounds checks for
> the DispID CEA data block. Which is why we don't need to repeat
> them in cea_db_offsets(). To avoid having to go through that
> pain again in the future add a comment which explains this fact.
>
> Cc: Andres Rodriguez
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_edid.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 3df5744026b0..0369a54e3d32 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -4001,6 +4001,10 @@ cea_db_offsets(const u8 *cea, int *start, int *end)
> * no non-DTD data.
> */
> if (cea[0] == DATA_BLOCK_CTA) {
> + /*
> +* for_each_displayid_db() has already verified
> +* that these stay within expected bounds.
> +*/
I think the preferred format is to have the start of the comment be on
the first line after the /* with that fixed:
Acked-by: Alex Deucher
> *start = 3;
> *end = *start + cea[2];
> } else if (cea[0] == CEA_EXT) {
> --
> 2.24.1
>
> ___
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Re: [Intel-gfx] [PATCH 4/8] drm/i915: Clear out spurious whitespace
Title should be s/i915/edid/ , with that fixed:
Reviewed-by: Alex Deucher
On Fri, Jan 24, 2020 at 3:03 PM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> Nuke some whitespace that shouldn't be there.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_edid.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index d6bce58b27ac..3df5744026b0 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -2842,7 +2842,7 @@ do_inferred_modes(struct detailed_timing *timing, void
> *c)
> closure->modes += drm_dmt_modes_for_range(closure->connector,
> closure->edid,
> timing);
> -
> +
> if (!version_greater(closure->edid, 1, 1))
> return; /* GTF not defined yet */
>
> @@ -3084,7 +3084,7 @@ do_cvt_mode(struct detailed_timing *timing, void *c)
>
> static int
> add_cvt_modes(struct drm_connector *connector, struct edid *edid)
> -{
> +{
> struct detailed_mode_closure closure = {
> .connector = connector,
> .edid = edid,
> @@ -4342,7 +4342,7 @@ void drm_edid_get_monitor_name(struct edid *edid, char
> *name, int bufsize)
> {
> int name_length;
> char buf[13];
> -
> +
> if (bufsize <= 0)
> return;
>
> --
> 2.24.1
>
> ___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Remove 'prefault_disable' modparam (rev2)
== Series Details == Series: drm/i915: Remove 'prefault_disable' modparam (rev2) URL : https://patchwork.freedesktop.org/series/72557/ State : failure == Summary == Applying: drm/i915: Remove 'prefault_disable' modparam Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c M drivers/gpu/drm/i915/i915_params.c M drivers/gpu/drm/i915/i915_params.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c No changes -- Patch already applied. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Add missing HDMI audio pixel clocks for gen12
== Series Details == Series: drm/i915: Add missing HDMI audio pixel clocks for gen12 URL : https://patchwork.freedesktop.org/series/72617/ State : failure == Summary == Applying: drm/i915: Add missing HDMI audio pixel clocks for gen12 Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_audio.c M drivers/gpu/drm/i915/i915_reg.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_reg.h Auto-merging drivers/gpu/drm/i915/display/intel_audio.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_audio.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915: Add missing HDMI audio pixel clocks for gen12 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 8/8] drm/i915/gt: Limit C-states while waiting for requests
Allow the sysadmin to specify whether we should prevent the CPU from
entering higher C-states while waiting for the CPU, in order to reduce
the latency of request completions and so speed up client continuations.
The target dma latency can be adjusted per-engine using,
/sys/class/drm/card?/engine/*/dma_latency_ns
(For waiting on a virtual engine, the underlying physical engine is used
for the wait once the request is active, so set all the physical engines
in the virtual set to the same target dma latency.)
Note that in most cases, the ratelimiting step does not appear to the
interrupt latency per se, but secondary effects of avoiding additional
memory latencies while active.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
Cc: Eero Tamminen
Cc: Francisco Jerez
Cc: Mika Kuoppala
Cc: Dmitry Rogozhkin
---
drivers/gpu/drm/i915/Kconfig.profile | 14 ++
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 48
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 2 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 9
drivers/gpu/drm/i915/gt/sysfs_engines.c | 31 +
5 files changed, 104 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.profile
b/drivers/gpu/drm/i915/Kconfig.profile
index ba8767fc0d6e..a956f1bb9caf 100644
--- a/drivers/gpu/drm/i915/Kconfig.profile
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -12,6 +12,20 @@ config DRM_I915_USERFAULT_AUTOSUSPEND
May be 0 to disable the extra delay and solely use the device level
runtime pm autosuspend delay tunable.
+config DRM_I915_DMA_LATENCY
+ int "Target CPU-DMA latency while waiting on active requests (ns)"
+ default -1 # nanoseconds
+ help
+ Specify a target latency for DMA wakeup, see /dev/cpu_dma_latency,
+ used while the CPU is waiting for GPU results.
+
+ This is adjustable via
+ /sys/class/drm/card?/engine/*/dma_latency_ns
+
+ May be -1 to prevent specifying a target wakeup and let the CPU
+ enter powersaving while waiting. Conversely, 0 may be used to
+ prevent the CPU from entering any C-states while waiting.
+
config DRM_I915_HEARTBEAT_INTERVAL
int "Interval between heartbeat pulses (ms)"
default 2500 # milliseconds
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
index 0ba524a414c6..34779d4f5012 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
@@ -31,6 +31,42 @@
#include "intel_gt_pm.h"
#include "intel_gt_requests.h"
+static void __dma_qos_update(struct work_struct *work)
+{
+ struct intel_breadcrumbs_dma_qos *qos =
+ container_of(work, typeof(*qos), update);
+
+ if (pm_qos_request_active(&qos->req)) {
+ if (qos->latency < 0)
+ pm_qos_remove_request(&qos->req);
+ else
+ pm_qos_update_request(&qos->req, qos->latency);
+ } else {
+ if (qos->latency != -1)
+ pm_qos_add_request(&qos->req,
+ PM_QOS_CPU_DMA_LATENCY,
+ qos->latency);
+ }
+}
+
+static void dma_qos_add(struct intel_breadcrumbs *b, s32 latency)
+{
+ if (latency < 0)
+ return;
+
+ b->qos.latency = latency;
+ queue_work(system_highpri_wq, &b->qos.update);
+}
+
+static void dma_qos_del(struct intel_breadcrumbs *b)
+{
+ if (b->qos.latency < 0)
+ return;
+
+ b->qos.latency = -1;
+ queue_work(system_highpri_wq, &b->qos.update);
+}
+
static void irq_enable(struct intel_engine_cs *engine)
{
if (!engine->irq_enable)
@@ -64,6 +100,8 @@ static void __intel_breadcrumbs_disarm_irq(struct
intel_breadcrumbs *b)
if (!--b->irq_enabled)
irq_disable(engine);
+ dma_qos_del(b);
+
b->irq_armed = false;
intel_gt_pm_put_async(engine->gt);
}
@@ -243,6 +281,8 @@ static bool __intel_breadcrumbs_arm_irq(struct
intel_breadcrumbs *b)
if (!b->irq_enabled++)
irq_enable(engine);
+ dma_qos_add(b, engine->props.dma_latency_ns);
+
return true;
}
@@ -253,6 +293,9 @@ void intel_engine_init_breadcrumbs(struct intel_engine_cs
*engine)
spin_lock_init(&b->irq_lock);
INIT_LIST_HEAD(&b->signalers);
+ b->qos.latency = -1;
+ INIT_WORK(&b->qos.update, __dma_qos_update);
+
init_irq_work(&b->irq_work, signal_irq_work);
}
@@ -273,6 +316,11 @@ void intel_engine_reset_breadcrumbs(struct intel_engine_cs
*engine)
void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine)
{
+ struct intel_breadcrumbs *b = &engine->breadcrumbs;
+
+ GEM_BUG_ON(b->qos.latency != -1);
+ flush_work(&b->qos.update);
+ GEM_BUG_ON(pm_qos_request_active(&b->qos.req));
}
bool i915_request_
[Intel-gfx] [PATCH 1/8] drm/i915/gt: Expose engine properties via sysfs
Preliminary stub to add engines underneath /sys/class/drm/cardN/, so
that we can expose properties on each engine to the sysadmin.
To start with we have basic analogues of the i915_query ioctl so that we
can pretty print engine discovery from the shell, and flesh out the
directory structure. Later we will add writeable sysadmin properties such
as per-engine timeout controls.
An example tree of the engine properties on Braswell:
/sys/class/drm/card0
└── engine
├── bcs0
│ ├── capabilities
│ ├── class
│ ├── instance
│ ├── known_capabilities
│ └── name
├── rcs0
│ ├── capabilities
│ ├── class
│ ├── instance
│ ├── known_capabilities
│ └── name
├── vcs0
│ ├── capabilities
│ ├── class
│ ├── instance
│ ├── known_capabilities
│ └── name
└── vecs0
├── capabilities
├── class
├── instance
├── known_capabilities
└── name
v2: Include stringified capabilities
v3: Include all known capabilities for futureproofing.
v4: Combine the two caps loops into one
v5: Hide underneath Kconfig.unstable for wider discussion
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Acked-by: Rodrigo Vivi
Reviewed-by: Tvrtko Ursulin
Tested-by: Steve Carbonari
Reviewed-by: Steve Carbonari
---
drivers/gpu/drm/i915/Kconfig.unstable | 7 +
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/gt/sysfs_engines.c | 208
drivers/gpu/drm/i915/gt/sysfs_engines.h | 13 ++
drivers/gpu/drm/i915/i915_sysfs.c | 3 +
5 files changed, 233 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/gt/sysfs_engines.c
create mode 100644 drivers/gpu/drm/i915/gt/sysfs_engines.h
diff --git a/drivers/gpu/drm/i915/Kconfig.unstable
b/drivers/gpu/drm/i915/Kconfig.unstable
index 0c2276155c2b..1f866cae943b 100644
--- a/drivers/gpu/drm/i915/Kconfig.unstable
+++ b/drivers/gpu/drm/i915/Kconfig.unstable
@@ -27,3 +27,10 @@ config DRM_I915_UNSTABLE_FAKE_LMEM
help
Convert some system memory into a fake local memory region for
testing.
+
+config DRM_I915_UNSTABLE_SYSFS
+ bool "Enable the experimental sysfs properties"
+ depends on DRM_I915_UNSTABLE
+ default n
+ help
+ Explore the HW property space from the shell command line!
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3c88d7d8c764..8a9a55525a21 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -105,7 +105,8 @@ gt-y += \
gt/intel_rps.o \
gt/intel_sseu.o \
gt/intel_timeline.o \
- gt/intel_workarounds.o
+ gt/intel_workarounds.o \
+ gt/sysfs_engines.o
# autogenerated null render state
gt-y += \
gt/gen6_renderstate.o \
diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.c
b/drivers/gpu/drm/i915/gt/sysfs_engines.c
new file mode 100644
index ..264cf51f5acc
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/sysfs_engines.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include
+#include
+
+#include "i915_drv.h"
+#include "intel_engine.h"
+#include "sysfs_engines.h"
+
+struct kobj_engine {
+ struct kobject base;
+ struct intel_engine_cs *engine;
+};
+
+static struct intel_engine_cs *kobj_to_engine(struct kobject *kobj)
+{
+ return container_of(kobj, struct kobj_engine, base)->engine;
+}
+
+static ssize_t
+name_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%s\n", kobj_to_engine(kobj)->name);
+}
+
+static struct kobj_attribute name_attr =
+__ATTR(name, 0444, name_show, NULL);
+
+static ssize_t
+class_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", kobj_to_engine(kobj)->uabi_class);
+}
+
+static struct kobj_attribute class_attr =
+__ATTR(class, 0444, class_show, NULL);
+
+static ssize_t
+inst_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", kobj_to_engine(kobj)->uabi_instance);
+}
+
+static struct kobj_attribute inst_attr =
+__ATTR(instance, 0444, inst_show, NULL);
+
+static const char * const vcs_caps[] = {
+ [ilog2(I915_VIDEO_CLASS_CAPABILITY_HEVC)] = "hevc",
+ [ilog2(I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC)] = "sfc",
+};
+
+static const char * const vecs_caps[] = {
+ [ilog2(I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC)] = "sfc",
+};
+
+static ssize_t repr_trim(char *buf, ssize_t len)
+{
+ /* Trim off the trailing space and replace with a newline */
+ if (len > PAGE_SIZE)
+ len = PAGE_SIZE;
+ if (len > 0)
+ buf[len - 1] = '\n';
+
+ return len;
+}
+
+static ss
[Intel-gfx] [PATCH 4/8] drm/i915/gt: Expose busywait duration to sysfs
We busywait on an inflight request (one that is currently executing on
HW, and so might complete quickly) prior to setting up an interrupt and
sleeping. The trade off is that we keep an expensive CPU core busy in
order to avoid wake up latency: where that trade off should lie is best
left to the sysadmin.
The busywait mechanism can be compiled out with
./scripts/config --set-val DRM_I915_SPIN_REQUEST 0
The maximum busywait duration can be adjusted per-engine using,
/sys/class/drm/card?/engine/*/ms_busywait_duration_ns
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Reviewed-by: Steve Carbonari
Tested-by: Steve Carbonari
---
drivers/gpu/drm/i915/Kconfig.profile | 9 ++--
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 2 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/drm/i915/gt/sysfs_engines.c | 49
drivers/gpu/drm/i915/i915_request.c | 19
5 files changed, 68 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/Kconfig.profile
b/drivers/gpu/drm/i915/Kconfig.profile
index d8d4a16179bd..9ee3b59685b9 100644
--- a/drivers/gpu/drm/i915/Kconfig.profile
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -35,9 +35,9 @@ config DRM_I915_PREEMPT_TIMEOUT
May be 0 to disable the timeout.
-config DRM_I915_SPIN_REQUEST
- int "Busywait for request completion (us)"
- default 5 # microseconds
+config DRM_I915_MAX_REQUEST_BUSYWAIT
+ int "Busywait for request completion limit (ns)"
+ default 8000 # nanoseconds
help
Before sleeping waiting for a request (GPU operation) to complete,
we may spend some time polling for its completion. As the IRQ may
@@ -45,6 +45,9 @@ config DRM_I915_SPIN_REQUEST
check if the request will complete in the time it would have taken
us to enable the interrupt.
+ This is adjustable via
+ /sys/class/drm/card?/engine/*/max_busywait_duration_ns
+
May be 0 to disable the initial spin. In practice, we estimate
the cost of enabling the interrupt (if currently disabled) to be
a few microseconds.
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 9b965d1f811d..af28ad168834 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -313,6 +313,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id)
engine->props.heartbeat_interval_ms =
CONFIG_DRM_I915_HEARTBEAT_INTERVAL;
+ engine->props.max_busywait_duration_ns =
+ CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT;
engine->props.preempt_timeout_ms =
CONFIG_DRM_I915_PREEMPT_TIMEOUT;
engine->props.stop_timeout_ms =
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 92be41a6903c..ed433c6386fb 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -537,6 +537,7 @@ struct intel_engine_cs {
struct {
unsigned long heartbeat_interval_ms;
+ unsigned long max_busywait_duration_ns;
unsigned long preempt_timeout_ms;
unsigned long stop_timeout_ms;
unsigned long timeslice_duration_ms;
diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.c
b/drivers/gpu/drm/i915/gt/sysfs_engines.c
index dd93e87ea5a8..061facb41602 100644
--- a/drivers/gpu/drm/i915/gt/sysfs_engines.c
+++ b/drivers/gpu/drm/i915/gt/sysfs_engines.c
@@ -142,6 +142,54 @@ all_caps_show(struct kobject *kobj, struct kobj_attribute
*attr, char *buf)
static struct kobj_attribute all_caps_attr =
__ATTR(known_capabilities, 0444, all_caps_show, NULL);
+static ssize_t
+max_spin_store(struct kobject *kobj, struct kobj_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct intel_engine_cs *engine = kobj_to_engine(kobj);
+ unsigned long long duration;
+ int err;
+
+ /*
+* When waiting for a request, if is it currently being executed
+* on the GPU, we busywait for a short while before sleeping. The
+* premise is that most requests are short, and if it is already
+* executing then there is a good chance that it will complete
+* before we can setup the interrupt handler and go to sleep.
+* We try to offset the cost of going to sleep, by first spinning
+* on the request -- if it completed in less time than it would take
+* to go sleep, process the interrupt and return back to the client,
+* then we have saved the client some latency, albeit at the cost
+* of spinning on an expensive CPU core.
+*
+* While we try to avoid waiting at all for a request that is unlikely
+* to complete, deciding how long it is worth spinning is for is an
+* arbitrary
[Intel-gfx] [PATCH 5/8] drm/i915/gt: Expose reset stop timeout via sysfs
When we allow ourselves to sleep before a GPU reset after disabling
submission, even for a few milliseconds, gives an innocent context the
opportunity to clear the GPU before the reset occurs. However, how long
to sleep depends on the typical non-preemptible duration (a similar
problem to determining the ideal preempt-reset timeout or even the
heartbeat interval). As this seems of a hard policy decision, punt it to
userspace.
The timeout can be adjusted using
/sys/class/drm/card?/engine/*/stop_timeout_ms
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Reviewed-by: Steve Carbonari
Tested-by: Steve Carbonari
---
drivers/gpu/drm/i915/Kconfig.profile| 3 ++
drivers/gpu/drm/i915/gt/sysfs_engines.c | 40 +
2 files changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.profile
b/drivers/gpu/drm/i915/Kconfig.profile
index 9ee3b59685b9..5f4ec3aec1d2 100644
--- a/drivers/gpu/drm/i915/Kconfig.profile
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -63,6 +63,9 @@ config DRM_I915_STOP_TIMEOUT
that the reset itself may take longer and so be more disruptive to
interactive or low latency workloads.
+ This is adjustable via
+ /sys/class/drm/card?/engine/*/stop_timeout_ms
+
config DRM_I915_TIMESLICE_DURATION
int "Scheduling quantum for userspace batches (ms, jiffy granularity)"
default 1 # milliseconds
diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.c
b/drivers/gpu/drm/i915/gt/sysfs_engines.c
index 061facb41602..93ab6e880fc3 100644
--- a/drivers/gpu/drm/i915/gt/sysfs_engines.c
+++ b/drivers/gpu/drm/i915/gt/sysfs_engines.c
@@ -232,6 +232,45 @@ timeslice_show(struct kobject *kobj, struct kobj_attribute
*attr, char *buf)
static struct kobj_attribute timeslice_duration_attr =
__ATTR(timeslice_duration_ms, 0644, timeslice_show, timeslice_store);
+static ssize_t
+stop_store(struct kobject *kobj, struct kobj_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct intel_engine_cs *engine = kobj_to_engine(kobj);
+ unsigned long long duration;
+ int err;
+
+ /*
+* When we allow ourselves to sleep before a GPU reset after disabling
+* submission, even for a few milliseconds, gives an innocent context
+* the opportunity to clear the GPU before the reset occurs. However,
+* how long to sleep depends on the typical non-preemptible duration
+* (a similar problem to determining the ideal preempt-reset timeout
+* or even the heartbeat interval).
+*/
+
+ err = kstrtoull(buf, 0, &duration);
+ if (err)
+ return err;
+
+ if (duration > jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT))
+ return -EINVAL;
+
+ WRITE_ONCE(engine->props.stop_timeout_ms, duration);
+ return count;
+}
+
+static ssize_t
+stop_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+ struct intel_engine_cs *engine = kobj_to_engine(kobj);
+
+ return sprintf(buf, "%lu\n", engine->props.stop_timeout_ms);
+}
+
+static struct kobj_attribute stop_timeout_attr =
+__ATTR(stop_timeout_ms, 0644, stop_show, stop_store);
+
static void kobj_engine_release(struct kobject *kobj)
{
kfree(kobj);
@@ -273,6 +312,7 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915)
&caps_attr.attr,
&all_caps_attr.attr,
&max_spin_attr.attr,
+ &stop_timeout_attr.attr,
NULL
};
--
2.25.0
___
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[Intel-gfx] [PATCH 7/8] drm/i915/gt: Expose heartbeat interval via sysfs
We monitor the health of the system via periodic heartbeat pulses. The
pulses also provide the opportunity to perform garbage collection.
However, we interpret an incomplete pulse (a missed heartbeat) as an
indication that the system is no longer responsive, i.e. hung, and
perform an engine or full GPU reset. Given that the preemption
granularity can be very coarse on a system, we let the sysadmin override
our legacy timeouts which were "optimised" for desktop applications.
The heartbeat interval can be adjusted per-engine using,
/sys/class/drm/card?/engine/*/heartbeat_interval_ms
Signed-off-by: Chris Wilson
Reviewed-by: Steve Carbonari
Tested-by: Steve Carbonari
---
drivers/gpu/drm/i915/Kconfig.profile| 3 ++
drivers/gpu/drm/i915/gt/sysfs_engines.c | 47 +
2 files changed, 50 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.profile
b/drivers/gpu/drm/i915/Kconfig.profile
index 1f4e98a8532f..ba8767fc0d6e 100644
--- a/drivers/gpu/drm/i915/Kconfig.profile
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -20,6 +20,9 @@ config DRM_I915_HEARTBEAT_INTERVAL
check the health of the GPU and undertake regular house-keeping of
internal driver state.
+ This is adjustable via
+ /sys/class/drm/card?/engine/*/heartbeat_interval_ms
+
May be 0 to disable heartbeats and therefore disable automatic GPU
hang detection.
diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.c
b/drivers/gpu/drm/i915/gt/sysfs_engines.c
index 1ebb221bd1cb..b39d4a365d73 100644
--- a/drivers/gpu/drm/i915/gt/sysfs_engines.c
+++ b/drivers/gpu/drm/i915/gt/sysfs_engines.c
@@ -8,6 +8,7 @@
#include "i915_drv.h"
#include "intel_engine.h"
+#include "intel_engine_heartbeat.h"
#include "sysfs_engines.h"
struct kobj_engine {
@@ -315,6 +316,49 @@ preempt_timeout_show(struct kobject *kobj, struct
kobj_attribute *attr,
static struct kobj_attribute preempt_timeout_attr =
__ATTR(preempt_timeout_ms, 0644, preempt_timeout_show, preempt_timeout_store);
+static ssize_t
+heartbeat_store(struct kobject *kobj, struct kobj_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct intel_engine_cs *engine = kobj_to_engine(kobj);
+ unsigned long long delay;
+ int err;
+
+ /*
+* We monitor the health of the system via periodic heartbeat pulses.
+* The pulses also provide the opportunity to perform garbage
+* collection. However, we interpret an incomplete pulse (a missed
+* heartbeat) as an indication that the system is no longer responsive,
+* i.e. hung, and perform an engine or full GPU reset. Given that the
+* preemption granularity can be very coarse on a system, the optimal
+* value for any workload is unknowable!
+*/
+
+ err = kstrtoull(buf, 0, &delay);
+ if (err)
+ return err;
+
+ if (delay >= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT))
+ return -EINVAL;
+
+ err = intel_engine_set_heartbeat(engine, delay);
+ if (err)
+ return err;
+
+ return count;
+}
+
+static ssize_t
+heartbeat_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+ struct intel_engine_cs *engine = kobj_to_engine(kobj);
+
+ return sprintf(buf, "%lu\n", engine->props.heartbeat_interval_ms);
+}
+
+static struct kobj_attribute heartbeat_interval_attr =
+__ATTR(heartbeat_interval_ms, 0644, heartbeat_show, heartbeat_store);
+
static void kobj_engine_release(struct kobject *kobj)
{
kfree(kobj);
@@ -357,6 +401,9 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915)
&all_caps_attr.attr,
&max_spin_attr.attr,
&stop_timeout_attr.attr,
+#if CONFIG_DRM_I915_HEARTBEAT_INTERVAL
+ &heartbeat_interval_attr.attr,
+#endif
NULL
};
--
2.25.0
___
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[Intel-gfx] [PATCH 3/8] drm/i915/gt: Expose timeslice duration to sysfs
Execlists uses a scheduling quantum (a timeslice) to alternate execution
between ready-to-run contexts of equal priority. This ensures that all
users (though only if they of equal importance) have the opportunity to
run and prevents livelocks where contexts may have implicit ordering due
to userspace semaphores.
The timeslicing mechanism can be compiled out with
./scripts/config --set-val DRM_I915_TIMESLICE_DURATION 0
The timeslice duration can be adjusted per-engine using,
/sys/class/drm/card?/engine/*/timeslice_duration_ms
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Reviewed-by: Steve Carbonari
Tested-by: Steve Carbonari
---
drivers/gpu/drm/i915/Kconfig.profile| 3 ++
drivers/gpu/drm/i915/gt/sysfs_engines.c | 46 +
2 files changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.profile
b/drivers/gpu/drm/i915/Kconfig.profile
index c280b6ae38eb..d8d4a16179bd 100644
--- a/drivers/gpu/drm/i915/Kconfig.profile
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -73,4 +73,7 @@ config DRM_I915_TIMESLICE_DURATION
is scheduled for execution for the timeslice duration, before
switching to the next context.
+ This is adjustable via
+ /sys/class/drm/card?/engine/*/timeslice_duration_ms
+
May be 0 to disable timeslicing.
diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.c
b/drivers/gpu/drm/i915/gt/sysfs_engines.c
index ddf8bcca0471..dd93e87ea5a8 100644
--- a/drivers/gpu/drm/i915/gt/sysfs_engines.c
+++ b/drivers/gpu/drm/i915/gt/sysfs_engines.c
@@ -142,6 +142,48 @@ all_caps_show(struct kobject *kobj, struct kobj_attribute
*attr, char *buf)
static struct kobj_attribute all_caps_attr =
__ATTR(known_capabilities, 0444, all_caps_show, NULL);
+static ssize_t
+timeslice_store(struct kobject *kobj, struct kobj_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct intel_engine_cs *engine = kobj_to_engine(kobj);
+ unsigned long long duration;
+ int err;
+
+ /*
+* Execlists uses a scheduling quantum (a timeslice) to alternate
+* execution between ready-to-run contexts of equal priority. This
+* ensures that all users (though only if they of equal importance)
+* have the opportunity to run and prevents livelocks where contexts
+* may have implicit ordering due to userspace semaphores.
+*/
+
+ err = kstrtoull(buf, 0, &duration);
+ if (err)
+ return err;
+
+ if (duration > jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT))
+ return -EINVAL;
+
+ WRITE_ONCE(engine->props.timeslice_duration_ms, duration);
+
+ if (execlists_active(&engine->execlists))
+ set_timer_ms(&engine->execlists.timer, duration);
+
+ return count;
+}
+
+static ssize_t
+timeslice_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+ struct intel_engine_cs *engine = kobj_to_engine(kobj);
+
+ return sprintf(buf, "%lu\n", engine->props.timeslice_duration_ms);
+}
+
+static struct kobj_attribute timeslice_duration_attr =
+__ATTR(timeslice_duration_ms, 0644, timeslice_show, timeslice_store);
+
static void kobj_engine_release(struct kobject *kobj)
{
kfree(kobj);
@@ -206,6 +248,10 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915)
if (sysfs_create_files(kobj, files))
goto err_object;
+ if (intel_engine_has_timeslices(engine) &&
+ sysfs_create_file(kobj, ×lice_duration_attr.attr))
+ goto err_engine;
+
if (0) {
err_object:
kobject_put(kobj);
--
2.25.0
___
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[Intel-gfx] [PATCH 2/8] drm/i915/gt: Expose engine->mmio_base via sysfs
Use the per-engine sysfs directory to let userspace discover the
mmio_base of each engine. Prior to recent generations, the user
accessible registers on each engine are at a fixed offset relative to
each engine -- but require absolute addressing. As the absolute address
depends on the actual physical engine, this is not always possible to
determine from userspace (for example icl may expose vcs1 or vcs2 as the
second vcs engine). Make this easy for userspace to discover by
providing the mmio_base in sysfs.
Signed-off-by: Chris Wilson
Acked-by: Lionel Landwerlin
Reviewed-by: Steve Carbonari
Tested-by: Steve Carbonari
---
drivers/gpu/drm/i915/gt/sysfs_engines.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.c
b/drivers/gpu/drm/i915/gt/sysfs_engines.c
index 264cf51f5acc..ddf8bcca0471 100644
--- a/drivers/gpu/drm/i915/gt/sysfs_engines.c
+++ b/drivers/gpu/drm/i915/gt/sysfs_engines.c
@@ -47,6 +47,15 @@ inst_show(struct kobject *kobj, struct kobj_attribute *attr,
char *buf)
static struct kobj_attribute inst_attr =
__ATTR(instance, 0444, inst_show, NULL);
+static ssize_t
+mmio_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+ return sprintf(buf, "0x%x\n", kobj_to_engine(kobj)->mmio_base);
+}
+
+static struct kobj_attribute mmio_attr =
+__ATTR(mmio_base, 0444, mmio_show, NULL);
+
static const char * const vcs_caps[] = {
[ilog2(I915_VIDEO_CLASS_CAPABILITY_HEVC)] = "hevc",
[ilog2(I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC)] = "sfc",
@@ -170,6 +179,7 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915)
&name_attr.attr,
&class_attr.attr,
&inst_attr.attr,
+ &mmio_attr.attr,
&caps_attr.attr,
&all_caps_attr.attr,
NULL
--
2.25.0
___
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[Intel-gfx] [PATCH 6/8] drm/i915/gt: Expose preempt reset timeout via sysfs
After initialising a preemption request, we give the current resident a
small amount of time to vacate the GPU. The preemption request is for a
higher priority context and should be immediate to maintain high
quality of service (and avoid priority inversion). However, the
preemption granularity of the GPU can be quite coarse and so we need a
compromise.
The preempt timeout can be adjusted per-engine using,
/sys/class/drm/card?/engine/*/preempt_timeout_ms
and can be disabled by setting it to 0.
Signed-off-by: Chris Wilson
Reviewed-by: Steve Carbonari
Tested-by: Steve Carbonari
---
drivers/gpu/drm/i915/Kconfig.profile| 3 ++
drivers/gpu/drm/i915/gt/sysfs_engines.c | 48 +
2 files changed, 51 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.profile
b/drivers/gpu/drm/i915/Kconfig.profile
index 5f4ec3aec1d2..1f4e98a8532f 100644
--- a/drivers/gpu/drm/i915/Kconfig.profile
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -33,6 +33,9 @@ config DRM_I915_PREEMPT_TIMEOUT
expires, the HW will be reset to allow the more important context
to execute.
+ This is adjustable via
+ /sys/class/drm/card?/engine/*/preempt_timeout_ms
+
May be 0 to disable the timeout.
config DRM_I915_MAX_REQUEST_BUSYWAIT
diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.c
b/drivers/gpu/drm/i915/gt/sysfs_engines.c
index 93ab6e880fc3..1ebb221bd1cb 100644
--- a/drivers/gpu/drm/i915/gt/sysfs_engines.c
+++ b/drivers/gpu/drm/i915/gt/sysfs_engines.c
@@ -271,6 +271,50 @@ stop_show(struct kobject *kobj, struct kobj_attribute
*attr, char *buf)
static struct kobj_attribute stop_timeout_attr =
__ATTR(stop_timeout_ms, 0644, stop_show, stop_store);
+static ssize_t
+preempt_timeout_store(struct kobject *kobj, struct kobj_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct intel_engine_cs *engine = kobj_to_engine(kobj);
+ unsigned long long timeout;
+ int err;
+
+ /*
+* After initialising a preemption request, we give the current
+* resident a small amount of time to vacate the GPU. The preemption
+* request is for a higher priority context and should be immediate to
+* maintain high quality of service (and avoid priority inversion).
+* However, the preemption granularity of the GPU can be quite coarse
+* and so we need a compromise.
+*/
+
+ err = kstrtoull(buf, 0, &timeout);
+ if (err)
+ return err;
+
+ if (timeout > jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT))
+ return -EINVAL;
+
+ WRITE_ONCE(engine->props.preempt_timeout_ms, timeout);
+
+ if (READ_ONCE(engine->execlists.pending[0]))
+ set_timer_ms(&engine->execlists.preempt, timeout);
+
+ return count;
+}
+
+static ssize_t
+preempt_timeout_show(struct kobject *kobj, struct kobj_attribute *attr,
+char *buf)
+{
+ struct intel_engine_cs *engine = kobj_to_engine(kobj);
+
+ return sprintf(buf, "%lu\n", engine->props.preempt_timeout_ms);
+}
+
+static struct kobj_attribute preempt_timeout_attr =
+__ATTR(preempt_timeout_ms, 0644, preempt_timeout_show, preempt_timeout_store);
+
static void kobj_engine_release(struct kobject *kobj)
{
kfree(kobj);
@@ -341,6 +385,10 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915)
sysfs_create_file(kobj, ×lice_duration_attr.attr))
goto err_engine;
+ if (intel_engine_has_preempt_reset(engine) &&
+ sysfs_create_file(kobj, &preempt_timeout_attr.attr))
+ goto err_engine;
+
if (0) {
err_object:
kobject_put(kobj);
--
2.25.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/auth: Drop master_create/destroy hooks
== Series Details == Series: drm/auth: Drop master_create/destroy hooks URL : https://patchwork.freedesktop.org/series/72609/ State : success == Summary == CI Bug Log - changes from CI_DRM_7826 -> Patchwork_16274 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16274/index.html Known issues Here are the changes found in Patchwork_16274 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([i915#45]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7826/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16274/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#111096] / [i915#323]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7826/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16274/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@i915_module_load@reload-with-fault-injection: - fi-skl-lmem:[DMESG-WARN][5] ([i915#889]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7826/fi-skl-lmem/igt@i915_module_l...@reload-with-fault-injection.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16274/fi-skl-lmem/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][7] ([i915#770]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7826/fi-hsw-4770/igt@i915_selftest@live_blt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16274/fi-hsw-4770/igt@i915_selftest@live_blt.html Warnings * igt@i915_module_load@reload-with-fault-injection: - fi-cfl-8700k: [DMESG-WARN][9] ([i915#889]) -> [INCOMPLETE][10] ([i915#505]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7826/fi-cfl-8700k/igt@i915_module_l...@reload-with-fault-injection.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16274/fi-cfl-8700k/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-kbl-guc: [FAIL][11] ([i915#704]) -> [SKIP][12] ([fdo#109271]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7826/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16274/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45 [i915#505]: https://gitlab.freedesktop.org/drm/intel/issues/505 [i915#704]: https://gitlab.freedesktop.org/drm/intel/issues/704 [i915#770]: https://gitlab.freedesktop.org/drm/intel/issues/770 [i915#889]: https://gitlab.freedesktop.org/drm/intel/issues/889 Participating hosts (46 -> 39) -- Additional (2): fi-skl-6600u fi-bsw-n3050 Missing(9): fi-hsw-peppy fi-byt-squawks fi-ctg-p8600 fi-kbl-x1275 fi-bsw-kefka fi-bdw-samus fi-byt-clapper fi-skl-6700k2 fi-kbl-r Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7826 -> Patchwork_16274 CI-20190529: 20190529 CI_DRM_7826: 04d0421c09d70ea76da8a3685347740df9f84aaf @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5389: 966c58649dee31bb5bf2fad92f75ffd365968b81 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16274: 502e4c060823985320f8dff3c98f1daa3460f344 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 502e4c060823 drm/auth: Drop master_create/destroy hooks == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16274/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915: Check current i915_vma.pin_count status first on unbind
Do an early rejection of a i915_vma_unbind() attempt if the i915_vma is
currently pinned, without waiting to see if the inflight operations may
unpin it. We see this problem with the shrinker trying to unbind the
active vma from inside its bind worker:
<6> [472.618968] Workqueue: events_unbound fence_work [i915]
<4> [472.618970] Call Trace:
<4> [472.618974] ? __schedule+0x2e5/0x810
<4> [472.618978] schedule+0x37/0xe0
<4> [472.618982] schedule_preempt_disabled+0xf/0x20
<4> [472.618984] __mutex_lock+0x281/0x9c0
<4> [472.618987] ? mark_held_locks+0x49/0x70
<4> [472.618989] ? _raw_spin_unlock_irqrestore+0x47/0x60
<4> [472.619038] ? i915_vma_unbind+0xae/0x110 [i915]
<4> [472.619084] ? i915_vma_unbind+0xae/0x110 [i915]
<4> [472.619122] i915_vma_unbind+0xae/0x110 [i915]
<4> [472.619165] i915_gem_object_unbind+0x1dc/0x400 [i915]
<4> [472.619208] i915_gem_shrink+0x328/0x660 [i915]
<4> [472.619250] ? i915_gem_shrink_all+0x38/0x60 [i915]
<4> [472.619282] i915_gem_shrink_all+0x38/0x60 [i915]
<4> [472.619325] vm_alloc_page.constprop.25+0x1aa/0x240 [i915]
<4> [472.619330] ? rcu_read_lock_sched_held+0x4d/0x80
<4> [472.619363] ? __alloc_pd+0xb/0x30 [i915]
<4> [472.619366] ? module_assert_mutex_or_preempt+0xf/0x30
<4> [472.619368] ? __module_address+0x23/0xe0
<4> [472.619371] ? is_module_address+0x26/0x40
<4> [472.619374] ? static_obj+0x34/0x50
<4> [472.619376] ? lockdep_init_map+0x4d/0x1e0
<4> [472.619407] setup_page_dma+0xd/0x90 [i915]
<4> [472.619437] alloc_pd+0x29/0x50 [i915]
<4> [472.619470] __gen8_ppgtt_alloc+0x443/0x6b0 [i915]
<4> [472.619503] gen8_ppgtt_alloc+0xd7/0x300 [i915]
<4> [472.619535] ppgtt_bind_vma+0x2a/0xe0 [i915]
<4> [472.619577] __vma_bind+0x26/0x40 [i915]
<4> [472.619611] fence_work+0x1c/0x90 [i915]
<4> [472.619617] process_one_work+0x26a/0x620
Fixes: 2850748ef876 ("drm/i915: Pull i915_vma_pin under the vm->mutex")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_vma.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 84e03da0d5f9..24dd912fdd6b 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -317,6 +317,8 @@ static void __vma_release(struct dma_fence_work *work)
if (vw->pinned)
__i915_gem_object_unpin_pages(vw->pinned);
+ if (vw->vma)
+ i915_vma_unpin(vw->vma);
}
static const struct dma_fence_work_ops bind_ops = {
@@ -407,6 +409,7 @@ int i915_vma_bind(struct i915_vma *vma,
__i915_gem_object_pin_pages(vma->obj);
work->pinned = vma->obj;
}
+ __i915_vma_pin(vma);
} else {
GEM_BUG_ON((bind_flags & ~vma_flags) &
vma->vm->bind_async_flags);
ret = vma->ops->bind_vma(vma, cache_level, bind_flags);
@@ -1033,6 +1036,7 @@ void i915_vma_release(struct kref *ref)
struct i915_vma *vma = container_of(ref, typeof(*vma), ref);
if (drm_mm_node_allocated(&vma->node)) {
+ WARN_ON(i915_vma_sync(vma));
mutex_lock(&vma->vm->mutex);
atomic_and(~I915_VMA_PIN_MASK, &vma->flags);
WARN_ON(__i915_vma_unbind(vma));
@@ -1190,18 +1194,6 @@ int __i915_vma_unbind(struct i915_vma *vma)
lockdep_assert_held(&vma->vm->mutex);
- /*
-* First wait upon any activity as retiring the request may
-* have side-effects such as unpinning or even unbinding this vma.
-*
-* XXX Actually waiting under the vm->mutex is a hinderance and
-* should be pipelined wherever possible. In cases where that is
-* unavoidable, we should lift the wait to before the mutex.
-*/
- ret = i915_vma_sync(vma);
- if (ret)
- return ret;
-
if (i915_vma_is_pinned(vma)) {
vma_print_allocator(vma, "is pinned");
return -EAGAIN;
@@ -1275,6 +1267,11 @@ int i915_vma_unbind(struct i915_vma *vma)
if (!drm_mm_node_allocated(&vma->node))
return 0;
+ if (i915_vma_is_pinned(vma)) {
+ vma_print_allocator(vma, "is pinned");
+ return -EAGAIN;
+ }
+
if (i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND))
/* XXX not always required: nop_clear_range */
wakeref = intel_runtime_pm_get(&vm->i915->runtime_pm);
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/hdcp: optimizing the srm handling
On Mon, Jan 27, 2020 at 11:42:31PM +0530, Ramalingam C wrote:
> As we are not using the sysfs infrastructure anymore, link to it is
> removed. And global srm data and mutex to protect it are removed,
> with required handling at revocation check function.
>
> v2:
> srm_data is dropped and few more comments are addressed.
>
> Signed-off-by: Ramalingam C
> Suggested-by: Sean Paul
> ---
> drivers/gpu/drm/drm_hdcp.c | 144 -
> drivers/gpu/drm/drm_internal.h | 4 -
> drivers/gpu/drm/drm_sysfs.c| 2 -
> include/drm/drm_hdcp.h | 4 +-
> 4 files changed, 55 insertions(+), 99 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c
> index 9191633a3c43..30749a13108e 100644
> --- a/drivers/gpu/drm/drm_hdcp.c
> +++ b/drivers/gpu/drm/drm_hdcp.c
> @@ -23,14 +23,6 @@
>
> #include "drm_internal.h"
>
> -static struct hdcp_srm {
> - u32 revoked_ksv_cnt;
> - u8 *revoked_ksv_list;
> -
> - /* Mutex to protect above struct member */
> - struct mutex mutex;
> -} *srm_data;
> -
> static inline void drm_hdcp_print_ksv(const u8 *ksv)
> {
> DRM_DEBUG("\t%#02x, %#02x, %#02x, %#02x, %#02x\n",
> @@ -91,7 +83,8 @@ static inline u32 get_vrl_length(const u8 *buf)
> return drm_hdcp_be24_to_cpu(buf);
> }
>
> -static int drm_hdcp_parse_hdcp1_srm(const u8 *buf, size_t count)
> +static int drm_hdcp_parse_hdcp1_srm(const u8 *buf, size_t count,
> + u8 *revoked_ksv_list, u32 *revoked_ksv_cnt)
Shouldn't this be u8 **revoked_ksv_list since you want to return the pointer for
use in the caller? I'm surprised any of this worked when you tested it...
> {
> struct hdcp_srm_header *header;
> u32 vrl_length, ksv_count;
> @@ -131,29 +124,28 @@ static int drm_hdcp_parse_hdcp1_srm(const u8 *buf,
> size_t count)
> ksv_count = drm_hdcp_get_revoked_ksv_count(buf, vrl_length);
> if (!ksv_count) {
> DRM_DEBUG("Revoked KSV count is 0\n");
> - return count;
> + return 0;
> }
>
> - kfree(srm_data->revoked_ksv_list);
> - srm_data->revoked_ksv_list = kcalloc(ksv_count, DRM_HDCP_KSV_LEN,
> - GFP_KERNEL);
> - if (!srm_data->revoked_ksv_list) {
> + revoked_ksv_list = kcalloc(ksv_count, DRM_HDCP_KSV_LEN, GFP_KERNEL);
> + if (!revoked_ksv_list) {
> DRM_ERROR("Out of Memory\n");
> return -ENOMEM;
> }
>
> - if (drm_hdcp_get_revoked_ksvs(buf, srm_data->revoked_ksv_list,
> + if (drm_hdcp_get_revoked_ksvs(buf, revoked_ksv_list,
> vrl_length) != ksv_count) {
> - srm_data->revoked_ksv_cnt = 0;
> - kfree(srm_data->revoked_ksv_list);
> + *revoked_ksv_cnt = 0;
> + kfree(revoked_ksv_list);
> return -EINVAL;
> }
>
> - srm_data->revoked_ksv_cnt = ksv_count;
> - return count;
> + *revoked_ksv_cnt = ksv_count;
> + return 0;
> }
>
> -static int drm_hdcp_parse_hdcp2_srm(const u8 *buf, size_t count)
> +static int drm_hdcp_parse_hdcp2_srm(const u8 *buf, size_t count,
> + u8 *revoked_ksv_list, u32 *revoked_ksv_cnt)
Same comment here, this should be u8 **
> {
> struct hdcp_srm_header *header;
> u32 vrl_length, ksv_count, ksv_sz;
> @@ -195,13 +187,11 @@ static int drm_hdcp_parse_hdcp2_srm(const u8 *buf,
> size_t count)
> ksv_count = (*buf << 2) | DRM_HDCP_2_KSV_COUNT_2_LSBITS(*(buf + 1));
> if (!ksv_count) {
> DRM_DEBUG("Revoked KSV count is 0\n");
> - return count;
> + return 0;
> }
>
> - kfree(srm_data->revoked_ksv_list);
> - srm_data->revoked_ksv_list = kcalloc(ksv_count, DRM_HDCP_KSV_LEN,
> - GFP_KERNEL);
> - if (!srm_data->revoked_ksv_list) {
> + revoked_ksv_list = kcalloc(ksv_count, DRM_HDCP_KSV_LEN, GFP_KERNEL);
> + if (!revoked_ksv_list) {
> DRM_ERROR("Out of Memory\n");
> return -ENOMEM;
> }
> @@ -210,10 +200,10 @@ static int drm_hdcp_parse_hdcp2_srm(const u8 *buf,
> size_t count)
> buf += DRM_HDCP_2_NO_OF_DEV_PLUS_RESERVED_SZ;
>
> DRM_DEBUG("Revoked KSVs: %d\n", ksv_count);
> - memcpy(srm_data->revoked_ksv_list, buf, ksv_sz);
> + memcpy(revoked_ksv_list, buf, ksv_sz);
>
> - srm_data->revoked_ksv_cnt = ksv_count;
> - return count;
> + *revoked_ksv_cnt = ksv_count;
> + return 0;
> }
>
> static inline bool is_srm_version_hdcp1(const u8 *buf)
> @@ -226,18 +216,22 @@ static inline bool is_srm_version_hdcp2(const u8 *buf)
> return *buf == (u8)(DRM_HDCP_2_SRM_ID << 4 | DRM_HDCP_2_INDICATOR);
> }
>
> -static void drm_hdcp_srm_update(const u8 *buf, size_t count)
> +static void drm_hdcp_srm_update(const u8 *buf, size_t count,
> + u8 *revoked_ksv_list, u32 *rev
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Restore the kernel context after verifying the w/a (rev2)
== Series Details == Series: drm/i915: Restore the kernel context after verifying the w/a (rev2) URL : https://patchwork.freedesktop.org/series/72588/ State : success == Summary == CI Bug Log - changes from CI_DRM_7826 -> Patchwork_16271 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16271/index.html Known issues Here are the changes found in Patchwork_16271 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-j1900: [PASS][1] -> [TIMEOUT][2] ([fdo#112271] / [i915#816]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7826/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16271/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@gem_exec_parallel@fds: - fi-byt-j1900: [PASS][3] -> [TIMEOUT][4] ([fdo#112271]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7826/fi-byt-j1900/igt@gem_exec_paral...@fds.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16271/fi-byt-j1900/igt@gem_exec_paral...@fds.html Possible fixes * igt@gem_close_race@basic-threads: - fi-hsw-peppy: [INCOMPLETE][5] ([i915#816]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7826/fi-hsw-peppy/igt@gem_close_r...@basic-threads.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16271/fi-hsw-peppy/igt@gem_close_r...@basic-threads.html * igt@i915_module_load@reload-with-fault-injection: - fi-cfl-8700k: [DMESG-WARN][7] ([i915#889]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7826/fi-cfl-8700k/igt@i915_module_l...@reload-with-fault-injection.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16271/fi-cfl-8700k/igt@i915_module_l...@reload-with-fault-injection.html - fi-skl-lmem:[DMESG-WARN][9] ([i915#889]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7826/fi-skl-lmem/igt@i915_module_l...@reload-with-fault-injection.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16271/fi-skl-lmem/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_pm_rpm@module-reload: - fi-cfl-8700k: [INCOMPLETE][11] ([i915#148] / [i915#971]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7826/fi-cfl-8700k/igt@i915_pm_...@module-reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16271/fi-cfl-8700k/igt@i915_pm_...@module-reload.html - fi-skl-6700k2: [DMESG-WARN][13] ([i915#889]) -> [PASS][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7826/fi-skl-6700k2/igt@i915_pm_...@module-reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16271/fi-skl-6700k2/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][15] ([i915#770]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7826/fi-hsw-4770/igt@i915_selftest@live_blt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16271/fi-hsw-4770/igt@i915_selftest@live_blt.html Warnings * igt@gem_exec_parallel@contexts: - fi-byt-j1900: [TIMEOUT][17] ([fdo#112271]) -> [FAIL][18] ([i915#694]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7826/fi-byt-j1900/igt@gem_exec_paral...@contexts.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16271/fi-byt-j1900/igt@gem_exec_paral...@contexts.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-kbl-guc: [FAIL][19] ([i915#704]) -> [SKIP][20] ([fdo#109271]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7826/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16271/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html * igt@i915_selftest@live_blt: - fi-hsw-4770r: [DMESG-FAIL][21] ([i915#553] / [i915#725]) -> [DMESG-FAIL][22] ([i915#770]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7826/fi-hsw-4770r/igt@i915_selftest@live_blt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16271/fi-hsw-4770r/igt@i915_selftest@live_blt.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#148]: https://gitlab.freedesktop.org/drm/intel/issues/148 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694 [i915#704]: https://gitlab.freedesktop.org/drm/intel/issues/704 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#770]: https://gitlab.freedesktop.org/drm/intel/issues/770 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 [
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/auth: Drop master_create/destroy hooks
== Series Details == Series: drm/auth: Drop master_create/destroy hooks URL : https://patchwork.freedesktop.org/series/72609/ State : warning == Summary == $ dim checkpatch origin/drm-tip 502e4c060823 drm/auth: Drop master_create/destroy hooks -:78: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter ' total: 0 errors, 1 warnings, 0 checks, 40 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm: Introduce struct drm_device based WARN* and use them in i915 (rev4)
== Series Details == Series: drm: Introduce struct drm_device based WARN* and use them in i915 (rev4) URL : https://patchwork.freedesktop.org/series/72035/ State : failure == Summary == Applying: drm/i915/display: Make WARN* drm specific where drm_device ptr is available Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_display.c M drivers/gpu/drm/i915/display/intel_dp.c M drivers/gpu/drm/i915/display/intel_dpll_mgr.c M drivers/gpu/drm/i915/display/intel_hdmi.c M drivers/gpu/drm/i915/display/intel_hotplug.c M drivers/gpu/drm/i915/display/intel_lvds.c M drivers/gpu/drm/i915/display/intel_pipe_crc.c M drivers/gpu/drm/i915/display/intel_sdvo.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/intel_sdvo.c Auto-merging drivers/gpu/drm/i915/display/intel_pipe_crc.c Auto-merging drivers/gpu/drm/i915/display/intel_lvds.c Auto-merging drivers/gpu/drm/i915/display/intel_hotplug.c Auto-merging drivers/gpu/drm/i915/display/intel_hdmi.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_hdmi.c Auto-merging drivers/gpu/drm/i915/display/intel_dpll_mgr.c Auto-merging drivers/gpu/drm/i915/display/intel_dp.c Auto-merging drivers/gpu/drm/i915/display/intel_display.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_display.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915/display: Make WARN* drm specific where drm_device ptr is available When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Squelch kerneldoc complaints (rev2)
== Series Details == Series: drm/i915/display: Squelch kerneldoc complaints (rev2) URL : https://patchwork.freedesktop.org/series/72182/ State : failure == Summary == Applying: drm/i915/display: Squelch kerneldoc complaints Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_atomic.c M drivers/gpu/drm/i915/display/intel_display.c M drivers/gpu/drm/i915/display/intel_fbc.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/intel_fbc.c Auto-merging drivers/gpu/drm/i915/display/intel_display.c No changes -- Patch already applied. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC v3] drm/i915/tgl: Suppress DC5/DC6 around DSB usage
There are reports of unexpected DSB busy/timeout happening after IGT
tests finish running that apparently go away when the DMC firmware isn't
loaded. The bspec doesn't say anything specific about DSB needing us to
exit DC5/DC6, but let's try adding DSB usage to the "DC off" list and
see if that changes the behavior.
v2: Include intel_wakeref.h from intel_dsb.h to ensure the header stays
self-contained. (CI)
v3: Move intel_display_power_get() call earlier to cover cases where
dsb->refcount is already non-zero and we return early. Also don't
drop the wakeref at the end of the 'get' routine; wait until the
'put' for that, even in error conditions. (Swati)
Cc: Swati Sharma
Signed-off-by: Matt Roper
Reviewed-by(v1): José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++
drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
drivers/gpu/drm/i915/display/intel_dsb.c | 10 --
drivers/gpu/drm/i915/display/intel_dsb.h | 2 ++
4 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 761be9fcaf10..99e6afda2db9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -150,6 +150,8 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
return "GT_IRQ";
case POWER_DOMAIN_DPLL_DC_OFF:
return "DPLL_DC_OFF";
+ case POWER_DOMAIN_DSB:
+ return "DSB";
default:
MISSING_CASE(domain);
return "?";
@@ -2679,6 +2681,7 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
BIT_ULL(POWER_DOMAIN_AUX_A) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_DSB) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define TGL_DDI_IO_D_TC1_POWER_DOMAINS ( \
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index 2608a65af7fa..5e8136c65e02 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -77,6 +77,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_GT_IRQ,
POWER_DOMAIN_DPLL_DC_OFF,
POWER_DOMAIN_INIT,
+ POWER_DOMAIN_DSB,
POWER_DOMAIN_NUM,
};
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index ada006a690df..b47c31fa2551 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -103,16 +103,15 @@ intel_dsb_get(struct intel_crtc *crtc)
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
u32 *buf;
- intel_wakeref_t wakeref;
if (!HAS_DSB(i915))
return dsb;
+ dsb->wakeref = intel_display_power_get(i915, POWER_DOMAIN_DSB);
+
if (dsb->refcount++ != 0)
return dsb;
- wakeref = intel_runtime_pm_get(&i915->runtime_pm);
-
obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
if (IS_ERR(obj)) {
DRM_ERROR("Gem object creation failed\n");
@@ -143,9 +142,6 @@ intel_dsb_get(struct intel_crtc *crtc)
* corresponding intel_dsb_put(): the important error message will
* already be logged above.
*/
-
- intel_runtime_pm_put(&i915->runtime_pm, wakeref);
-
return dsb;
}
@@ -174,6 +170,8 @@ void intel_dsb_put(struct intel_dsb *dsb)
dsb->free_pos = 0;
dsb->ins_start_offset = 0;
}
+
+ intel_display_power_put(i915, POWER_DOMAIN_DSB, dsb->wakeref);
}
/**
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index 395ef9ce558e..ffb5afa935b7 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -9,6 +9,7 @@
#include
#include "i915_reg.h"
+#include "intel_wakeref.h"
struct intel_crtc;
struct i915_vma;
@@ -26,6 +27,7 @@ struct intel_dsb {
enum dsb_id id;
u32 *cmd_buf;
struct i915_vma *vma;
+ intel_wakeref_t wakeref;
/*
* free_pos will point the first free entry position
--
2.23.0
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[Intel-gfx] [PATCH i-g-t] lib/color_encoding: Fix up support for XYUV format
Add XYUV to the list of DRM Formats to test.
Also fix the byte order for the format.
Signed-off-by: Bob Paauwe
Reviewed-by: Uma Shankar
---
lib/igt_color_encoding.c | 1 +
lib/igt_fb.c | 6 +++---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/lib/igt_color_encoding.c b/lib/igt_color_encoding.c
index 7de6d5ab..a7bd2b22 100644
--- a/lib/igt_color_encoding.c
+++ b/lib/igt_color_encoding.c
@@ -160,6 +160,7 @@ static const struct color_encoding_format {
{ DRM_FORMAT_XVYU2101010, 1023.f, 64.f, 940.f, 64.f, 512.f, 960.f },
{ DRM_FORMAT_XVYU12_16161616, 65520.f, 4096.f, 60160.f, 4096.f,
32768.f, 61440.f },
{ DRM_FORMAT_XVYU16161616, 65535.f, 4096.f, 60160.f, 4096.f, 32768.f,
61440.f },
+ { DRM_FORMAT_XYUV, 255.f, 16.f, 235.f, 16.f, 128.f, 240.f },
};
static const struct color_encoding_format *lookup_fourcc(uint32_t fourcc)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index c81b9de8..7409e6b3 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -2634,9 +2634,9 @@ static void get_yuv_parameters(struct igt_fb *fb, struct
yuv_parameters *params)
break;
case DRM_FORMAT_XYUV:
- params->y_offset = fb->offsets[0] + 1;
- params->u_offset = fb->offsets[0] + 2;
- params->v_offset = fb->offsets[0] + 3;
+ params->y_offset = fb->offsets[0] + 2;
+ params->u_offset = fb->offsets[0] + 1;
+ params->v_offset = fb->offsets[0] + 0;
break;
}
}
--
2.21.0
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[Intel-gfx] [PATCH] drm/i915: Adding YUV444 packed format support for skl+ (V13)
From: Stanislav Lisovskiy
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
labels.
v5: Started to use XYUV instead of AYUV, as we don't use alpha.
v6: Removed unneeded initializer for new XYUV format.
v7: Added scaling support for DRM_FORMAT_XYUV
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
v9: Moved DRM format check to proper place in intel_framebuffer_init.
v10: Added missing XYUV format to sprite planes for skl+.
v11: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV.
v12: Fixed rebase conflicts
V13: Rebased.
Added format to ICL format lists.
v12:
Reviewed-by: Ville Syrjälä
Reviewed-by: Matt Roper
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 7f94d5ca4207..b9f993769a4a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3328,6 +3328,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool
alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_XYUV:
+ return DRM_FORMAT_XYUV;
case PLANE_CTL_FORMAT_P010:
return DRM_FORMAT_P010;
case PLANE_CTL_FORMAT_P012:
@@ -4538,6 +4540,8 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
case DRM_FORMAT_XRGB16161616F:
case DRM_FORMAT_ARGB16161616F:
return PLANE_CTL_FORMAT_XRGB_16161616F;
+ case DRM_FORMAT_XYUV:
+ return PLANE_CTL_FORMAT_XYUV;
case DRM_FORMAT_YUYV:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
case DRM_FORMAT_YVYU:
@@ -6147,6 +6151,7 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 2f277d1fc6f1..aafe04b29a61 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2470,6 +2470,7 @@ static const u32 skl_plane_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_XYUV,
};
static const u32 skl_planar_formats[] = {
@@ -2488,6 +2489,7 @@ static const u32 skl_planar_formats[] = {
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
DRM_FORMAT_NV12,
+ DRM_FORMAT_XYUV,
};
static const u32 glk_planar_formats[] = {
@@ -2559,6 +2561,7 @@ static const u32 icl_sdr_uv_plane_formats[] = {
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
+ DRM_FORMAT_XYUV,
};
static const u32 icl_hdr_plane_formats[] = {
@@ -2590,6 +2593,7 @@ static const u32 icl_hdr_plane_formats[] = {
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
+ DRM_FORMAT_XYUV,
};
static const u64 skl_plane_format_modifiers_noccs[] = {
@@ -2757,6 +2761,7 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b93c4c18f05c..b3848e73de29 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6764,7 +6764,7 @@ enum {
#define PLANE_CTL_FORMAT_P012(5 << 24)
#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
#define PLANE_CTL_FORMAT_P016(7 << 24)
-#define PLANE_CTL_FORMAT_AYUV(8 << 24)
+#define PLANE_CTL_FORMAT_XYUV(8 << 24)
#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
#define ICL_PLANE_CTL_FORMAT_MASK(0x1f << 23)
--
2.21.0
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Re: [Intel-gfx] [PATCH 2/6] drm/i915: Check current i915_vma.pin_count status first on unbind
On 26/01/2020 10:23, Chris Wilson wrote:
Do an early rejection of a i915_vma_unbind() attempt if the i915_vma is
currently pinned, without waiting to see if the inflight operations may
unpin it. We see this problem with the shrinker trying to unbind the
active vma from inside its bind worker:
<6> [472.618968] Workqueue: events_unbound fence_work [i915]
<4> [472.618970] Call Trace:
<4> [472.618974] ? __schedule+0x2e5/0x810
<4> [472.618978] schedule+0x37/0xe0
<4> [472.618982] schedule_preempt_disabled+0xf/0x20
<4> [472.618984] __mutex_lock+0x281/0x9c0
<4> [472.618987] ? mark_held_locks+0x49/0x70
<4> [472.618989] ? _raw_spin_unlock_irqrestore+0x47/0x60
<4> [472.619038] ? i915_vma_unbind+0xae/0x110 [i915]
<4> [472.619084] ? i915_vma_unbind+0xae/0x110 [i915]
<4> [472.619122] i915_vma_unbind+0xae/0x110 [i915]
<4> [472.619165] i915_gem_object_unbind+0x1dc/0x400 [i915]
<4> [472.619208] i915_gem_shrink+0x328/0x660 [i915]
<4> [472.619250] ? i915_gem_shrink_all+0x38/0x60 [i915]
<4> [472.619282] i915_gem_shrink_all+0x38/0x60 [i915]
<4> [472.619325] vm_alloc_page.constprop.25+0x1aa/0x240 [i915]
<4> [472.619330] ? rcu_read_lock_sched_held+0x4d/0x80
<4> [472.619363] ? __alloc_pd+0xb/0x30 [i915]
<4> [472.619366] ? module_assert_mutex_or_preempt+0xf/0x30
<4> [472.619368] ? __module_address+0x23/0xe0
<4> [472.619371] ? is_module_address+0x26/0x40
<4> [472.619374] ? static_obj+0x34/0x50
<4> [472.619376] ? lockdep_init_map+0x4d/0x1e0
<4> [472.619407] setup_page_dma+0xd/0x90 [i915]
<4> [472.619437] alloc_pd+0x29/0x50 [i915]
<4> [472.619470] __gen8_ppgtt_alloc+0x443/0x6b0 [i915]
<4> [472.619503] gen8_ppgtt_alloc+0xd7/0x300 [i915]
<4> [472.619535] ppgtt_bind_vma+0x2a/0xe0 [i915]
<4> [472.619577] __vma_bind+0x26/0x40 [i915]
<4> [472.619611] fence_work+0x1c/0x90 [i915]
<4> [472.619617] process_one_work+0x26a/0x620
Fixes: 2850748ef876 ("drm/i915: Pull i915_vma_pin under the vm->mutex")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_vma.c | 17 +
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 84e03da0d5f9..2ffc68e18dd0 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1190,18 +1190,6 @@ int __i915_vma_unbind(struct i915_vma *vma)
lockdep_assert_held(&vma->vm->mutex);
- /*
-* First wait upon any activity as retiring the request may
-* have side-effects such as unpinning or even unbinding this vma.
-*
-* XXX Actually waiting under the vm->mutex is a hinderance and
-* should be pipelined wherever possible. In cases where that is
-* unavoidable, we should lift the wait to before the mutex.
-*/
- ret = i915_vma_sync(vma);
- if (ret)
- return ret;
-
if (i915_vma_is_pinned(vma)) {
vma_print_allocator(vma, "is pinned");
return -EAGAIN;
@@ -1275,6 +1263,11 @@ int i915_vma_unbind(struct i915_vma *vma)
if (!drm_mm_node_allocated(&vma->node))
return 0;
+ if (i915_vma_is_pinned(vma)) {
+ vma_print_allocator(vma, "is pinned");
+ return -EAGAIN;
+ }
+
if (i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND))
/* XXX not always required: nop_clear_range */
wakeref = intel_runtime_pm_get(&vm->i915->runtime_pm);
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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Re: [Intel-gfx] [RFC 00/33] drm/i915/display: mass conversion to intel_de_*() register accessors
On Fri, 24 Jan 2020, Matt Roper wrote: > There's a lot of display (watermark) code in intel_pm.c as well, even > though it doesn't live in the display/ directory. We should probably > pull the watermark stuff out into a separate display/intel_wm.c or > something soon, but in the meantime we'll probably want to switch a > bunch of that code over to using these new functions. But I guess you > can't do that with coccinelle though since there are parts of the file > that aren't display-related and shouldn't use the same display helpers. Yeah, display/ was a clear-cut line. I may have already pushed some patches using intel_de_*_fw from the top level code, but I think it would be better to move all large chunks of code that do display uncore stuff under display/. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 5/8] drm/i915/display_power: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson
Acked-by: Rodrigo Vivi
Acked-by: Joonas Lahtinen
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_power.c| 292 ++
1 file changed, 157 insertions(+), 135 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 18d8bfdcb086..b24f2b041d99 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -304,11 +304,11 @@ static u32 hsw_power_well_requesters(struct
drm_i915_private *dev_priv,
u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
u32 ret;
- ret = I915_READ(regs->bios) & req_mask ? 1 : 0;
- ret |= I915_READ(regs->driver) & req_mask ? 2 : 0;
+ ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0;
+ ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 : 0;
if (regs->kvmr.reg)
- ret |= I915_READ(regs->kvmr) & req_mask ? 4 : 0;
- ret |= I915_READ(regs->debug) & req_mask ? 8 : 0;
+ ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ? 4 : 0;
+ ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0;
return ret;
}
@@ -330,7 +330,7 @@ static void hsw_wait_for_power_well_disable(struct
drm_i915_private *dev_priv,
* Skip the wait in case any of the request bits are set and print a
* diagnostic message.
*/
- wait_for((disabled = !(I915_READ(regs->driver) &
+ wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) &
HSW_PWR_WELL_CTL_STATE(pw_idx))) ||
(reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1);
if (disabled)
@@ -373,17 +373,18 @@ static void hsw_power_well_enable(struct drm_i915_private
*dev_priv,
gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0);
}
- val = I915_READ(regs->driver);
- I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
+ val = intel_de_read(dev_priv, regs->driver);
+ intel_de_write(dev_priv, regs->driver,
+ val | HSW_PWR_WELL_CTL_REQ(pw_idx));
hsw_wait_for_power_well_enable(dev_priv, power_well);
/* Display WA #1178: cnl */
if (IS_CANNONLAKE(dev_priv) &&
pw_idx >= GLK_PW_CTL_IDX_AUX_B &&
pw_idx <= CNL_PW_CTL_IDX_AUX_F) {
- val = I915_READ(CNL_AUX_ANAOVRD1(pw_idx));
+ val = intel_de_read(dev_priv, CNL_AUX_ANAOVRD1(pw_idx));
val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
- I915_WRITE(CNL_AUX_ANAOVRD1(pw_idx), val);
+ intel_de_write(dev_priv, CNL_AUX_ANAOVRD1(pw_idx), val);
}
if (wait_fuses)
@@ -404,8 +405,9 @@ static void hsw_power_well_disable(struct drm_i915_private
*dev_priv,
hsw_power_well_pre_disable(dev_priv,
power_well->desc->hsw.irq_pipe_mask);
- val = I915_READ(regs->driver);
- I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
+ val = intel_de_read(dev_priv, regs->driver);
+ intel_de_write(dev_priv, regs->driver,
+ val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
hsw_wait_for_power_well_disable(dev_priv, power_well);
}
@@ -422,12 +424,14 @@ icl_combo_phy_aux_power_well_enable(struct
drm_i915_private *dev_priv,
WARN_ON(!IS_ICELAKE(dev_priv));
- val = I915_READ(regs->driver);
- I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
+ val = intel_de_read(dev_priv, regs->driver);
+ intel_de_write(dev_priv, regs->driver,
+ val | HSW_PWR_WELL_CTL_REQ(pw_idx));
if (INTEL_GEN(dev_priv) < 12) {
- val = I915_READ(ICL_PORT_CL_DW12(phy));
- I915_WRITE(ICL_PORT_CL_DW12(phy), val | ICL_LANE_ENABLE_AUX);
+ val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy));
+ intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy),
+
[Intel-gfx] [PATCH v2 7/8] drm/i915/hdcp: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson
Acked-by: Rodrigo Vivi
Acked-by: Joonas Lahtinen
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 142 --
1 file changed, 79 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 33dc40a63fce..2d25244f38df 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -112,7 +112,8 @@ static inline
bool intel_hdcp_in_use(struct drm_i915_private *dev_priv,
enum transcoder cpu_transcoder, enum port port)
{
- return I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
+ return intel_de_read(dev_priv,
+HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
HDCP_STATUS_ENC;
}
@@ -120,7 +121,8 @@ static inline
bool intel_hdcp2_in_use(struct drm_i915_private *dev_priv,
enum transcoder cpu_transcoder, enum port port)
{
- return I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
+ return intel_de_read(dev_priv,
+HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
LINK_ENCRYPTION_STATUS;
}
@@ -184,9 +186,9 @@ static bool hdcp_key_loadable(struct drm_i915_private
*dev_priv)
static void intel_hdcp_clear_keys(struct drm_i915_private *dev_priv)
{
- I915_WRITE(HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER);
- I915_WRITE(HDCP_KEY_STATUS, HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS |
- HDCP_FUSE_IN_PROGRESS | HDCP_FUSE_ERROR | HDCP_FUSE_DONE);
+ intel_de_write(dev_priv, HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER);
+ intel_de_write(dev_priv, HDCP_KEY_STATUS,
+ HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS |
HDCP_FUSE_IN_PROGRESS | HDCP_FUSE_ERROR | HDCP_FUSE_DONE);
}
static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
@@ -194,7 +196,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private
*dev_priv)
int ret;
u32 val;
- val = I915_READ(HDCP_KEY_STATUS);
+ val = intel_de_read(dev_priv, HDCP_KEY_STATUS);
if ((val & HDCP_KEY_LOAD_DONE) && (val & HDCP_KEY_LOAD_STATUS))
return 0;
@@ -203,7 +205,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private
*dev_priv)
* out of reset. So if Key is not already loaded, its an error state.
*/
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- if (!(I915_READ(HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE))
+ if (!(intel_de_read(dev_priv, HDCP_KEY_STATUS) &
HDCP_KEY_LOAD_DONE))
return -ENXIO;
/*
@@ -223,7 +225,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private
*dev_priv)
return ret;
}
} else {
- I915_WRITE(HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER);
+ intel_de_write(dev_priv, HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER);
}
/* Wait for the keys to load (500us) */
@@ -236,7 +238,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private
*dev_priv)
return -ENXIO;
/* Send Aksv over to PCH display for use in authentication */
- I915_WRITE(HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER);
+ intel_de_write(dev_priv, HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER);
return 0;
}
@@ -244,7 +246,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private
*dev_priv)
/* Returns updated SHA-1 index */
static int intel_write_sha_text(struct drm_i915_private *dev_priv, u32
sha_text)
{
- I915_WRITE(HDCP_SHA_TEXT, sha_text);
+ intel_de_write(dev_priv, HDCP_SHA_TEXT, sha_text);
if (intel_de_wait_for_set(dev_priv, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) {
drm_err(&dev_priv->drm, "Timed out waiting for SHA1 ready\n");
return -ETIMEDOUT;
@@ -311,7 +313,7 @@ int intel_hdcp_validate_v_prime(struct intel_connector
*connector,
ret = shim->read_v_prime_part(intel_dig_port, i, &vprim
[Intel-gfx] [PATCH v2 1/8] drm/i915/icl_dsi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson
Acked-by: Rodrigo Vivi
Acked-by: Joonas Lahtinen
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 271 +
1 file changed, 145 insertions(+), 126 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 1186a5df057e..f553ba4c63c7 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -39,14 +39,14 @@
static inline int header_credits_available(struct drm_i915_private *dev_priv,
enum transcoder dsi_trans)
{
- return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
+ return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) &
FREE_HEADER_CREDIT_MASK)
>> FREE_HEADER_CREDIT_SHIFT;
}
static inline int payload_credits_available(struct drm_i915_private *dev_priv,
enum transcoder dsi_trans)
{
- return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
+ return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) &
FREE_PLOAD_CREDIT_MASK)
>> FREE_PLOAD_CREDIT_SHIFT;
}
@@ -110,7 +110,7 @@ static void wait_for_cmds_dispatched_to_panel(struct
intel_encoder *encoder)
/* wait for LP TX in progress bit to be cleared */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) &
+ if (wait_for_us(!(intel_de_read(dev_priv,
DSI_LP_MSG(dsi_trans)) &
LPTX_IN_PROGRESS), 20))
drm_err(&dev_priv->drm, "LPTX bit not cleared\n");
}
@@ -138,7 +138,7 @@ static bool add_payld_to_queue(struct intel_dsi_host *host,
const u8 *data,
for (j = 0; j < min_t(u32, len - i, 4); j++)
tmp |= *data++ << 8 * j;
- I915_WRITE(DSI_CMD_TXPYLD(dsi_trans), tmp);
+ intel_de_write(dev_priv, DSI_CMD_TXPYLD(dsi_trans), tmp);
}
return true;
@@ -161,7 +161,7 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
return -1;
}
- tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans));
+ tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans));
if (pkt.payload)
tmp |= PAYLOAD_PRESENT;
@@ -178,7 +178,7 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT);
tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT);
tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT);
- I915_WRITE(DSI_CMD_TXHDR(dsi_trans), tmp);
+ intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp);
return 0;
}
@@ -215,53 +215,55 @@ static void dsi_program_swing_and_deemphasis(struct
intel_encoder *encoder)
* Program voltage swing and pre-emphasis level values as per
* table in BSPEC under DDI buffer programing
*/
- tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
+ tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
tmp |= SCALING_MODE_SEL(0x2);
tmp |= TAP2_DISABLE | TAP3_DISABLE;
tmp |= RTERM_SELECT(0x6);
- I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
+ intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
- tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
+ tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
tmp |= SCALING_MODE_SEL(0x2);
tmp |= TAP2_DISABLE | TAP3_DISABLE;
tmp |= RTERM_SELECT(0x6);
- I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
+ intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
- tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy
[Intel-gfx] [PATCH i-g-t v2 2/2] i915/gem_ctx_isolation: use the gem_engine_topology library, part 2
Switch from simple iteration over all potential engines to using
macro __for_each_physical_engine which only returns engines that are
actually present.
For each context (as it is created) call gem_context_set_all_engines
so that execbuf will interpret the engine specification in the new way.
Signed-off-by: Dale B Stimson
---
tests/i915/gem_ctx_isolation.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index c45617456..1b66fec11 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -586,7 +586,8 @@ static void nonpriv(int fd,
igt_spin_t *spin = NULL;
uint32_t ctx, regs[2], tmpl;
- ctx = gem_context_create(fd);
+ ctx = gem_context_clone_with_engines(fd, 0);
+
tmpl = read_regs(fd, ctx, e, flags);
regs[0] = read_regs(fd, ctx, e, flags);
@@ -599,7 +600,7 @@ static void nonpriv(int fd,
write_regs(fd, ctx, e, flags, values[v]);
if (flags & DIRTY2) {
- uint32_t sw = gem_context_create(fd);
+ uint32_t sw = gem_context_clone_with_engines(fd, 0);
igt_spin_t *syncpt, *dirt;
/* Explicit sync to keep the switch between write/read
*/
@@ -668,7 +669,7 @@ static void isolation(int fd,
igt_spin_t *spin = NULL;
uint32_t ctx[2], regs[2], tmp;
- ctx[0] = gem_context_create(fd);
+ ctx[0] = gem_context_clone_with_engines(fd, 0);
regs[0] = read_regs(fd, ctx[0], e, flags);
spin = igt_spin_new(fd, .ctx = ctx[0], .engine = e->flags);
@@ -687,7 +688,7 @@ static void isolation(int fd,
* the default values from this context, but if goes badly we
* see the corruption from the previous context instead!
*/
- ctx[1] = gem_context_create(fd);
+ ctx[1] = gem_context_clone_with_engines(fd, 0);
regs[1] = read_regs(fd, ctx[1], e, flags);
if (flags & DIRTY2) {
@@ -727,7 +728,7 @@ static void isolation(int fd,
static void inject_reset_context(int fd, const struct intel_execution_engine2
*e)
{
struct igt_spin_factory opts = {
- .ctx = gem_context_create(fd),
+ .ctx = gem_context_clone_with_engines(fd, 0),
.engine = e->flags,
.flags = IGT_SPIN_FAST,
};
@@ -775,11 +776,11 @@ static void preservation(int fd,
gem_quiescent_gpu(fd);
- ctx[num_values] = gem_context_create(fd);
+ ctx[num_values] = gem_context_clone_with_engines(fd, 0);
spin = igt_spin_new(fd, .ctx = ctx[num_values], .engine = e->flags);
regs[num_values][0] = read_regs(fd, ctx[num_values], e, flags);
for (int v = 0; v < num_values; v++) {
- ctx[v] = gem_context_create(fd);
+ ctx[v] = gem_context_clone_with_engines(fd, 0);
write_regs(fd, ctx[v], e, flags, values[v]);
regs[v][0] = read_regs(fd, ctx[v], e, flags);
@@ -874,7 +875,9 @@ igt_main
igt_skip_on(gen > LAST_KNOWN_GEN);
}
- __for_each_static_engine(e) {
+ /* __for_each_physical_engine switches context to all engines. */
+
+ __for_each_physical_engine(fd, e) {
igt_subtest_group {
igt_fixture {
igt_require(has_context_isolation & (1 <<
e->class));
--
2.25.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 05/33] drm/i915/combo_phy: use intel_de_*() functions for register access
On Fri, 24 Jan 2020, Matt Roper wrote:
> On Fri, Jan 24, 2020 at 03:25:26PM +0200, Jani Nikula wrote:
>> @@ -151,20 +151,20 @@ static void cnl_combo_phys_init(struct
>> drm_i915_private *dev_priv)
>> {
>> u32 val;
>>
>> -val = I915_READ(CHICKEN_MISC_2);
>> +val = intel_de_read(dev_priv, CHICKEN_MISC_2);
>> val &= ~CNL_COMP_PWR_DOWN;
>> -I915_WRITE(CHICKEN_MISC_2, val);
>> +intel_de_write(dev_priv, CHICKEN_MISC_2, val);
>>
>> /* Dummy PORT_A to get the correct CNL register from the ICL macro */
>> cnl_set_procmon_ref_values(dev_priv, PHY_A);
>>
>> -val = I915_READ(CNL_PORT_COMP_DW0);
>> +val = intel_de_read(dev_priv, CNL_PORT_COMP_DW0);
>> val |= COMP_INIT;
>> -I915_WRITE(CNL_PORT_COMP_DW0, val);
>> +intel_de_write(dev_priv, CNL_PORT_COMP_DW0, val);
>
> Drive by comment...could some fancier coccinelle usage change these to
> intel_de_rmw() instead? We have a lot of rmw behavior for PHY
> registers, and I believe some for pre-ilk watermarks and clock gating
> workarounds in intel_pm.c too.
I decided I wanted to get these merged, as folks seemed to agree with
the approach. The fancy cocci would take a while to figure out. But I'll
look into it as a follow-up.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 00/33] drm/i915/display: mass conversion to intel_de_*() register accessors
On Sat, 25 Jan 2020, Jani Nikula wrote: > On Fri, 24 Jan 2020, Rodrigo Vivi wrote: >> On Fri, Jan 24, 2020 at 01:54:58PM +, Chris Wilson wrote: >>> Quoting Jani Nikula (2020-01-24 13:25:21) >>> > Hey all, >>> > >>> > So I sent [1] to convert some forcewake register accessors... but what if >>> > we >>> > just ripped off the bandage once and for all? It's going to hurt, a lot, >>> > but >>> > we'd get it done. >>> > >>> > This completely rids us of the "dev_priv" dependency in display/. >>> > >>> > All the patches here are per-file and independent of each other. We could >>> > also >>> > pick and apply the ones that are least likely to conflict. >>> > >>> > Opinions? >>> > >>> > >>> > BR, >>> > Jani. >>> > >>> > >>> > PS. I didn't bother looking at the checkpatch warnings this may generate >>> > at this >>> > point. I just used the --linux-spacing option for spatch, and closed my >>> > eyes. I >>> > completely scripted the generation of the series, apart from just a >>> > couple of >>> > build fixes. >>> >>> Yup. Suck it all in, clean up with the usual code refreshes. >>> Schadenfreude-by: Chris Wilson >>> >>> I've looked at a couple of patches to confirm that it does appear purely >>> mechanical, >>> Acked-by: Chris Wilson >> >> Since it is purely mechanical with coccinelle, why not to make in only one >> patch? > > Because such a mega patch would conflict before being able to > merge. You'd have to block everything else. I don't think I'd be able to > merge these in one go either even if we wanted to. Indeed, I started pushing the patches, pushed all that applied, and eight will need a rebase. Thanks for the acks. BR, Jani. > >> Anyway: >> Acked-by: Rodrigo Vivi > > Thanks, > Jani. > >> >>> -Chris >>> ___ >>> Intel-gfx mailing list >>> Intel-gfx@lists.freedesktop.org >>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/8] drm/i915/combo_phy: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson
Acked-by: Rodrigo Vivi
Acked-by: Joonas Lahtinen
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_combo_phy.c| 66 +--
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index ec63c2657923..11f80f15cb4d 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -48,7 +48,7 @@ cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv,
enum phy phy)
const struct cnl_procmon *procmon;
u32 val;
- val = I915_READ(ICL_PORT_COMP_DW3(phy));
+ val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy));
switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
default:
MISSING_CASE(val);
@@ -81,20 +81,20 @@ static void cnl_set_procmon_ref_values(struct
drm_i915_private *dev_priv,
procmon = cnl_get_procmon_ref_values(dev_priv, phy);
- val = I915_READ(ICL_PORT_COMP_DW1(phy));
+ val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy));
val &= ~((0xff << 16) | 0xff);
val |= procmon->dw1;
- I915_WRITE(ICL_PORT_COMP_DW1(phy), val);
+ intel_de_write(dev_priv, ICL_PORT_COMP_DW1(phy), val);
- I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9);
- I915_WRITE(ICL_PORT_COMP_DW10(phy), procmon->dw10);
+ intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9);
+ intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10);
}
static bool check_phy_reg(struct drm_i915_private *dev_priv,
enum phy phy, i915_reg_t reg, u32 mask,
u32 expected_val)
{
- u32 val = I915_READ(reg);
+ u32 val = intel_de_read(dev_priv, reg);
if ((val & mask) != expected_val) {
DRM_DEBUG_DRIVER("Combo PHY %c reg %08x state mismatch: "
@@ -127,8 +127,8 @@ static bool cnl_verify_procmon_ref_values(struct
drm_i915_private *dev_priv,
static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv)
{
- return !(I915_READ(CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) &&
- (I915_READ(CNL_PORT_COMP_DW0) & COMP_INIT);
+ return !(intel_de_read(dev_priv, CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) &&
+ (intel_de_read(dev_priv, CNL_PORT_COMP_DW0) & COMP_INIT);
}
static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv)
@@ -151,20 +151,20 @@ static void cnl_combo_phys_init(struct drm_i915_private
*dev_priv)
{
u32 val;
- val = I915_READ(CHICKEN_MISC_2);
+ val = intel_de_read(dev_priv, CHICKEN_MISC_2);
val &= ~CNL_COMP_PWR_DOWN;
- I915_WRITE(CHICKEN_MISC_2, val);
+ intel_de_write(dev_priv, CHICKEN_MISC_2, val);
/* Dummy PORT_A to get the correct CNL register from the ICL macro */
cnl_set_procmon_ref_values(dev_priv, PHY_A);
- val = I915_READ(CNL_PORT_COMP_DW0);
+ val = intel_de_read(dev_priv, CNL_PORT_COMP_DW0);
val |= COMP_INIT;
- I915_WRITE(CNL_PORT_COMP_DW0, val);
+ intel_de_write(dev_priv, CNL_PORT_COMP_DW0, val);
- val = I915_READ(CNL_PORT_CL1CM_DW5);
+ val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
val |= CL_POWER_DOWN_ENABLE;
- I915_WRITE(CNL_PORT_CL1CM_DW5, val);
+ intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
}
static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv)
@@ -174,9 +174,9 @@ static void cnl_combo_phys_uninit(struct drm_i915_private
*dev_priv)
if (!cnl_combo_phy_verify_state(dev_priv))
DRM_WARN("Combo PHY HW state changed unexpectedly.\n");
- val = I915_READ(CHICKEN_MISC_2);
+ val = intel_de_read(dev_priv, CHICKEN_MISC_2);
val |= CNL_COMP_PWR_DOWN;
- I915_WRITE(CHICKEN_MISC_2, val);
+ intel_de_write(dev_priv, CHICKEN_MISC_2, val);
}
static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
@@ -184,11 +184,11 @@ static bool icl_combo_phy_enabled(struct
[Intel-gfx] [PATCH v2 8/8] drm/i915/psr: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain point in the register access macros I915_READ(), I915_WRITE(), POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW(). Replace them with the corresponding new display engine register accessors intel_de_read(), intel_de_write(), intel_de_posting_read(), intel_de_read_fw(), and intel_de_write_fw(). No functional changes. Generated using the following semantic patch: @@ expression REG, OFFSET; @@ - I915_READ(REG) + intel_de_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - POSTING_READ(REG) + intel_de_posting_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE(REG, OFFSET) + intel_de_write(dev_priv, REG, OFFSET) @@ expression REG; @@ - I915_READ_FW(REG) + intel_de_read_fw(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE_FW(REG, OFFSET) + intel_de_write_fw(dev_priv, REG, OFFSET) Acked-by: Chris Wilson Acked-by: Rodrigo Vivi Acked-by: Joonas Lahtinen Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_psr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index b9dd9763c0f7..e41ed962aa80 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -832,11 +832,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, * TODO: if future platforms supports DC3CO in more than one * transcoder, EXITLINE will need to be unset when disabling PSR */ - val = I915_READ(EXITLINE(cpu_transcoder)); + val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder)); val &= ~EXITLINE_MASK; val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT; val |= EXITLINE_ENABLE; - I915_WRITE(EXITLINE(cpu_transcoder), val); + intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); } } -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
