[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gvt: remove unused variable gma_bottom in command parser (rev2)
== Series Details ==
Series: drm/i915/gvt: remove unused variable gma_bottom in command parser (rev2)
URL : https://patchwork.freedesktop.org/series/118512/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13207_full -> Patchwork_118512v2_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_118512v2_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_118512v2_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_118512v2_full:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@gt_timelines:
- shard-apl: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-apl1/igt@i915_selftest@live@gt_timelines.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118512v2/shard-apl3/igt@i915_selftest@live@gt_timelines.html
* igt@kms_big_fb@linear-16bpp-rotate-180:
- shard-apl: [PASS][3] -> [DMESG-WARN][4] +37 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-apl2/igt@kms_big...@linear-16bpp-rotate-180.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118512v2/shard-apl2/igt@kms_big...@linear-16bpp-rotate-180.html
Warnings
* igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-c-dp-1:
- shard-apl: [FAIL][5] ([i915#4573]) -> [DMESG-FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-apl2/igt@kms_plane_alpha_blend@alpha-transparent...@pipe-c-dp-1.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118512v2/shard-apl2/igt@kms_plane_alpha_blend@alpha-transparent...@pipe-c-dp-1.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_balancer@noheartbeat:
- {shard-dg1}:NOTRUN -> [SKIP][7]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118512v2/shard-dg1-19/igt@gem_exec_balan...@noheartbeat.html
Known issues
Here are the changes found in Patchwork_118512v2_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][8] -> [FAIL][9] ([i915#2846])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-glk3/igt@gem_exec_f...@basic-deadline.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118512v2/shard-glk5/igt@gem_exec_f...@basic-deadline.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-glk: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118512v2/shard-glk9/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@gem_pwrite@basic-exhaustion:
- shard-glk: NOTRUN -> [WARN][11] ([i915#2658])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118512v2/shard-glk9/igt@gem_pwr...@basic-exhaustion.html
* igt@gem_userptr_blits@vma-merge:
- shard-glk: NOTRUN -> [FAIL][12] ([i915#3318])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118512v2/shard-glk9/igt@gem_userptr_bl...@vma-merge.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs:
- shard-snb: NOTRUN -> [SKIP][13] ([fdo#109271]) +21 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118512v2/shard-snb5/igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs.html
* igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#3886]) +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118512v2/shard-glk7/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_content_protection@lic:
- shard-glk: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4579]) +8
similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118512v2/shard-glk9/igt@kms_content_protect...@lic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-apl: [PASS][16] -> [FAIL][17] ([i915#2346])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-apl6/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118512v2/shard-apl3/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-apl: [PASS][18] ->
[Intel-gfx] ✗ Fi.CI.IGT: failure for s/ADL/ALDERLAKE
== Series Details ==
Series: s/ADL/ALDERLAKE
URL : https://patchwork.freedesktop.org/series/118596/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13207_full -> Patchwork_118596v1_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_118596v1_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_118596v1_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_118596v1_full:
### IGT changes ###
Possible regressions
* igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs:
- shard-apl: [PASS][1] -> [DMESG-WARN][2] +11 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-apl3/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-apl2/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs.html
Warnings
* igt@kms_ccs@pipe-a-bad-rotation-90-yf_tiled_ccs:
- shard-snb: [SKIP][3] ([fdo#109271]) -> [ABORT][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-snb2/igt@kms_ccs@pipe-a-bad-rotation-90-yf_tiled_ccs.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-snb6/igt@kms_ccs@pipe-a-bad-rotation-90-yf_tiled_ccs.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_balancer@noheartbeat:
- {shard-dg1}:NOTRUN -> [SKIP][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-dg1-19/igt@gem_exec_balan...@noheartbeat.html
Known issues
Here are the changes found in Patchwork_118596v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][6] -> [FAIL][7] ([i915#2846])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-glk3/igt@gem_exec_f...@basic-deadline.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-glk6/igt@gem_exec_f...@basic-deadline.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-glk: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-glk5/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@gem_pwrite@basic-exhaustion:
- shard-glk: NOTRUN -> [WARN][9] ([i915#2658])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-glk5/igt@gem_pwr...@basic-exhaustion.html
* igt@gem_spin_batch@spin-each:
- shard-apl: [PASS][10] -> [FAIL][11] ([i915#2898])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-apl6/igt@gem_spin_ba...@spin-each.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-apl3/igt@gem_spin_ba...@spin-each.html
* igt@gem_userptr_blits@vma-merge:
- shard-glk: NOTRUN -> [FAIL][12] ([i915#3318])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-glk5/igt@gem_userptr_bl...@vma-merge.html
* igt@kms_atomic@plane-invalid-params:
- shard-snb: [PASS][13] -> [SKIP][14] ([fdo#109271])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-snb6/igt@kms_ato...@plane-invalid-params.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-snb2/igt@kms_ato...@plane-invalid-params.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs:
- shard-snb: NOTRUN -> [SKIP][15] ([fdo#109271]) +19 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-snb4/igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs.html
* igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#3886]) +1
similar issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-glk1/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_content_protection@lic:
- shard-glk: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4579]) +8
similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-glk5/igt@kms_content_protect...@lic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-apl: [PASS][18] -> [FAIL][19] ([i915#2346])
[18]:
[Intel-gfx] ✗ Fi.CI.BUILD: failure for dim: Disallow remote branch deletions with 'dim push'
== Series Details == Series: dim: Disallow remote branch deletions with 'dim push' URL : https://patchwork.freedesktop.org/series/118744/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/118744/revisions/1/mbox/ not applied Applying: dim: Disallow remote branch deletions with 'dim push' error: sha1 information is lacking or useless (dim). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 dim: Disallow remote branch deletions with 'dim push' When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". Build failed, no error log produced
[Intel-gfx] [PATCH] dim: Disallow remote branch deletions with 'dim push'
An inadvertent 'dim push -d' can delete remote branches. Disallow such remote branch deletions. Signed-off-by: Ashutosh Dixit --- dim | 6 ++ 1 file changed, 6 insertions(+) diff --git a/dim b/dim index 126568e..e5899e6 100755 --- a/dim +++ b/dim @@ -1029,6 +1029,12 @@ function dim_push_branch fi fi + # Disallow remote branch deletions, say with 'dim push -d' + if [[ "$@" == *"-d"* ]]; then + echoerr "Attempt to delete remote branch, aborting." + return 1 + fi + git_push $remote $branch "$@" update_linux_next $branch drm-intel-next drm-intel-next-fixes drm-intel-fixes -- 2.38.0
Re: [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
On Thu, 01 Jun 2023 17:40:18 -0700, Andi Shyti wrote:
>
Hi Andi,
> On Thu, Jun 01, 2023 at 05:23:24PM -0700, Dixit, Ashutosh wrote:
> > On Thu, 01 Jun 2023 11:30:44 -0700, Dixit, Ashutosh wrote:
> > >
> > > On Thu, 01 Jun 2023 11:22:18 -0700, Dixit, Ashutosh wrote:
> > > >
> > > > On Wed, 31 May 2023 14:35:47 -0700, Matt Atwood wrote:
> > > > >
> > > >
> > > > Hi Matt,
> > > >
> > > > > Set I915_PMU_MAX_GTS to value in I915_MAX_GT, theres no reason for
> > > > > these
> > > > > values to be different.
> > >
> > > Also, we can't be so sure so as to be able to say "theres no reason for
> > > these values to be different" till we have actually verified it. E.g.
> > > there
> > > are various bitfields in the code which might not fit in a u32 if we
> > > increase MAX_GT from 2 to 4. Has this been verified?
> > >
> > > If anything, to keep the code from doing unnecessary stuff, IMO
> > > I915_MAX_GT
> > > should be reduced to 2 and should be increased to 4 only once/if we have
> > > i915 supported platforms with 4 GT's.
> >
> > Matt explained the issue offline to me (it would have helped to explain the
> > reason for the patch in the commit message). The issue is that in uses of
> > for_each_gt such as below (there are others too in the PMU code):
> >
> > for_each_gt(gt, i915, i) {
> > intel_wakeref_t wakeref;
> >
> > with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
> > u64 val = __get_rc6(gt);
> >
> > store_sample(pmu, i, __I915_SAMPLE_RC6, val);
> > store_sample(pmu, i,
> > __I915_SAMPLE_RC6_LAST_REPORTED,
> > val);
> > pmu->sleep_last[i] = ktime_get_raw();
> > }
> > }
> >
> > static checkers are complaining that for_each_gt can read/write outside the
> > bounds of PMU arrays. Because absent gt's will be NULL in for_each_gt this
> > cannot really happen but we still need to keep static checkers happy.
> >
> > So to resolve this issue we need I915_PMU_MAX_GTS and I915_MAX_GT to have
> > the same value. So either we need to increase I915_PMU_MAX_GTS to 4 or
> > reduce I915_MAX_GT to 2.
>
> the number of GT's is a GPU concept and should remain as such all
> over the GPU. If max GT is 4 then it should be 4 everywhere.
>
> The I915_PMU_MAX_GTS define should not exist at all as it is
> creating this sort of inconsistencies and everything should refer
> to a single I915_MAX_GT. The reason for having I915_PMU_MAX_GTS,
> in a first place, is purely practical to avoid over inclusions.
> Still I consider it hacky.
>
> On the other had, already I915_MAX_GT is a hardcoded value and
> many times there have been discussions about removing it and
> fetch it dynamically during the i915 boot. But this requires
> quite a good amount of refactoring that no one is willing to do.
>
> If we can't get rid of I915_PMU_MAX_GTS then I strongly believe
> it should be aligned with I915_MAX_GT and for this reason I gave
> my r-b. The use of for_each_gt() is a clear consequence of this
> difference.
Yes, not disagreeing. At this point I think my preferred solution is
something like:
#define I915_MAX_GT 2
#define I915_PMU_MAX_GTS I915_MAX_GT
Unless someone can explain why I915_MAX_GT cannot be 2. As I see it,
there's no need for I915_MAX_GT to be 4 after xehpsdv disappeared and
support for future platforms is moving to xe.
Thanks.
--
Ashutosh
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Print usefull information on error (rev3)
== Series Details ==
Series: drm/i915/display: Print usefull information on error (rev3)
URL : https://patchwork.freedesktop.org/series/118685/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13218 -> Patchwork_118685v3
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v3/index.html
Participating hosts (38 -> 38)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_118685v3:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_force_connector_basic@force-connector-state:
- {bat-adlp-11}: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v3/bat-adlp-11/igt@kms_force_connector_ba...@force-connector-state.html
Known issues
Here are the changes found in Patchwork_118685v3 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-hsw-4770:[PASS][2] -> [SKIP][3] ([fdo#109271])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13218/fi-hsw-4770/igt@i915_pm_...@basic-pci-d3-state.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v3/fi-hsw-4770/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- fi-hsw-4770:[PASS][4] -> [FAIL][5] ([i915#7364])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13218/fi-hsw-4770/igt@i915_pm_...@basic-rte.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v3/fi-hsw-4770/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [PASS][6] -> [DMESG-FAIL][7] ([i915#5334] /
[i915#7872])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13218/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v3/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [PASS][8] -> [ABORT][9] ([i915#4983] / [i915#7911] /
[i915#7920])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13218/bat-rpls-1/igt@i915_selftest@l...@requests.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v3/bat-rpls-1/igt@i915_selftest@l...@requests.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: NOTRUN -> [ABORT][10] ([i915#4983] / [i915#7461] /
[i915#7913] / [i915#8347])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v3/bat-rpls-2/igt@i915_selftest@l...@reset.html
Possible fixes
* igt@core_auth@basic-auth:
- {bat-adlp-11}: [ABORT][11] ([i915#4423] / [i915#8011]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13218/bat-adlp-11/igt@core_a...@basic-auth.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v3/bat-adlp-11/igt@core_a...@basic-auth.html
* igt@i915_module_load@load:
- {bat-adlp-11}: [DMESG-WARN][13] ([i915#4423]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13218/bat-adlp-11/igt@i915_module_l...@load.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v3/bat-adlp-11/igt@i915_module_l...@load.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][15] ([i915#5334]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13218/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v3/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hugepages:
- fi-apl-guc: [DMESG-FAIL][17] -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13218/fi-apl-guc/igt@i915_selftest@l...@hugepages.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v3/fi-apl-guc/igt@i915_selftest@l...@hugepages.html
* igt@i915_selftest@live@requests:
- bat-rpls-2: [ABORT][19] ([i915#4983] / [i915#7913]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13218/bat-rpls-2/igt@i915_selftest@l...@requests.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v3/bat-rpls-2/igt@i915_selftest@l...@requests.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#4093]: https://gitlab.freedesktop.org/drm/intel/issues/4093
[Intel-gfx] [PATCHv3] drm/i915/display: Print useful information on error
For modifier not supporting async flip, print the modifier and display
version. Helps in reading the error message.
v2: Reframe the error message (Jani)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f51a55f4e9d0..f23dd937c27c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6012,8 +6012,9 @@ static int intel_async_flip_check_hw(struct
intel_atomic_state *state, struct in
*/
if (DISPLAY_VER(i915) < 12) {
drm_dbg_kms(>drm,
- "[PLANE:%d:%s] Modifier does not
support async flips\n",
- plane->base.base.id,
plane->base.name);
+ "[PLANE:%d:%s] Modifier 0x%llx does
not support async flip on display ver %d\n",
+ plane->base.base.id,
plane->base.name,
+ new_plane_state->hw.fb->modifier,
DISPLAY_VER(i915));
return -EINVAL;
}
break;
@@ -6025,8 +6026,9 @@ static int intel_async_flip_check_hw(struct
intel_atomic_state *state, struct in
break;
default:
drm_dbg_kms(>drm,
- "[PLANE:%d:%s] Modifier does not support
async flips\n",
- plane->base.base.id, plane->base.name);
+ "[PLANE:%d:%s] Modifier 0x%llx does not
support async flip\n",
+ plane->base.base.id, plane->base.name,
+ new_plane_state->hw.fb->modifier);
return -EINVAL;
}
--
2.25.1
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/pxp: Fix size_t format specifier in gsccs_send_message()
== Series Details ==
Series: drm/i915/pxp: Fix size_t format specifier in gsccs_send_message()
URL : https://patchwork.freedesktop.org/series/118593/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13206_full -> Patchwork_118593v1_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_118593v1_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_118593v1_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_118593v1_full:
### IGT changes ###
Possible regressions
* igt@runner@aborted:
- shard-snb: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v1/shard-snb5/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_118593v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][2] -> [ABORT][3] ([i915#5566])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-glk6/igt@gen9_exec_pa...@allowed-single.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v1/shard-glk6/igt@gen9_exec_pa...@allowed-single.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [PASS][4] -> [FAIL][5] ([i915#72])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-glk4/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v1/shard-glk7/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html
* igt@kms_flip@2x-plain-flip:
- shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271]) +4 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v1/shard-snb5/igt@kms_f...@2x-plain-flip.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-apl: [PASS][7] -> [ABORT][8] ([i915#180])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-apl4/igt@kms_flip@flip-vs-suspend-interrupti...@b-dp1.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v1/shard-apl6/igt@kms_flip@flip-vs-suspend-interrupti...@b-dp1.html
*
igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4579]) +2
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v1/shard-snb1/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0...@pipe-b-hdmi-a-1.html
Possible fixes
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- {shard-rkl}:[FAIL][10] ([i915#7742]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-rkl-1/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v1/shard-rkl-1/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-rkl}:[FAIL][12] ([i915#6268]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-rkl-4/igt@gem_ctx_e...@basic-nohangcheck.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v1/shard-rkl-6/igt@gem_ctx_e...@basic-nohangcheck.html
* igt@gem_eio@hibernate:
- {shard-tglu}: [ABORT][14] ([i915#7975] / [i915#8213] / [i915#8398])
-> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-tglu-10/igt@gem_...@hibernate.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v1/shard-tglu-4/igt@gem_...@hibernate.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- {shard-rkl}:[FAIL][16] ([i915#2842]) -> [PASS][17] +1 similar
issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-rkl-7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v1/shard-rkl-4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@i915_pm_rc6_residency@rc6-idle@bcs0:
- {shard-dg1}:[FAIL][18] ([i915#3591]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-i...@bcs0.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118593v1/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-i...@bcs0.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- {shard-dg1}:[SKIP][20] ([i915#1397]) -> [PASS][21]
[20]:
Re: [Intel-gfx] [PATCH 0/2] drm/i915/gt: Fix recent kCFI violations
Hi Nathan,
On Tue, May 30, 2023 at 11:24:37AM -0700, Nathan Chancellor wrote:
> Hi all,
>
> This series fixes a few clang kernel Control Flow Integrity (kCFI)
> violations that appear after commit 9275277d5324 ("drm/i915: use
> pat_index instead of cache_level"). They were found between run time
> testing on real hardware and compile time testing with
> -Wincompatible-function-pointer-types-strict (which is not yet enabled
> for the kernel but I build with it locally to catch new instances).
>
> If there are any problems or questions, please let me know.
>
> ---
> Nathan Chancellor (2):
> drm/i915/gt: Fix second parameter type of pre-gen8 pte_encode callbacks
> drm/i915/gt: Fix parameter in gmch_ggtt_insert_{entries,page}()
pushed in drm-intel-gt-next.
Thank you,
Andi
Re: [Intel-gfx] [PATCH] drm/i915/pxp: use correct format string for size_t
Hi Arnd,
On Thu, Jun 01, 2023 at 10:00:27PM +, Teres Alexis, Alan Previn wrote:
> On Thu, 2023-06-01 at 23:36 +0200, Arnd Bergmann wrote:
> > From: Arnd Bergmann
> >
> > While 'unsigned long' needs the %ld format string, size_t needs the %z
> > modifier:
>
> alan:snip
>
>
> > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
> > @@ -143,7 +143,7 @@ gsccs_send_message(struct intel_pxp *pxp,
> >
> > reply_size = header->message_size - sizeof(*header);
> > if (reply_size > msg_out_size_max) {
> > - drm_warn(>drm, "caller with insufficient PXP reply size
> > %u (%ld)\n",
> > + drm_warn(>drm, "caller with insufficient PXP reply size
> > %u (%zd)\n",
> > reply_size, msg_out_size_max);
> > reply_size = msg_out_size_max;
> > }
> Thanks Arnd for catching this, although i believe Nathan sumbmitted a patch
> for the same fix yesterday and received an RB from Andi.
yes, the patch is here:
https://patchwork.freedesktop.org/patch/540272/?series=118593=1
I'm waiting for full CI results to merge this.
Thanks,
Andi
Re: [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
Hi Ashutosh,
On Thu, Jun 01, 2023 at 05:23:24PM -0700, Dixit, Ashutosh wrote:
> On Thu, 01 Jun 2023 11:30:44 -0700, Dixit, Ashutosh wrote:
> >
> > On Thu, 01 Jun 2023 11:22:18 -0700, Dixit, Ashutosh wrote:
> > >
> > > On Wed, 31 May 2023 14:35:47 -0700, Matt Atwood wrote:
> > > >
> > >
> > > Hi Matt,
> > >
> > > > Set I915_PMU_MAX_GTS to value in I915_MAX_GT, theres no reason for these
> > > > values to be different.
> >
> > Also, we can't be so sure so as to be able to say "theres no reason for
> > these values to be different" till we have actually verified it. E.g. there
> > are various bitfields in the code which might not fit in a u32 if we
> > increase MAX_GT from 2 to 4. Has this been verified?
> >
> > If anything, to keep the code from doing unnecessary stuff, IMO I915_MAX_GT
> > should be reduced to 2 and should be increased to 4 only once/if we have
> > i915 supported platforms with 4 GT's.
>
> Matt explained the issue offline to me (it would have helped to explain the
> reason for the patch in the commit message). The issue is that in uses of
> for_each_gt such as below (there are others too in the PMU code):
>
> for_each_gt(gt, i915, i) {
> intel_wakeref_t wakeref;
>
> with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
> u64 val = __get_rc6(gt);
>
> store_sample(pmu, i, __I915_SAMPLE_RC6, val);
> store_sample(pmu, i, __I915_SAMPLE_RC6_LAST_REPORTED,
> val);
> pmu->sleep_last[i] = ktime_get_raw();
> }
> }
>
> static checkers are complaining that for_each_gt can read/write outside the
> bounds of PMU arrays. Because absent gt's will be NULL in for_each_gt this
> cannot really happen but we still need to keep static checkers happy.
>
> So to resolve this issue we need I915_PMU_MAX_GTS and I915_MAX_GT to have
> the same value. So either we need to increase I915_PMU_MAX_GTS to 4 or
> reduce I915_MAX_GT to 2.
the number of GT's is a GPU concept and should remain as such all
over the GPU. If max GT is 4 then it should be 4 everywhere.
The I915_PMU_MAX_GTS define should not exist at all as it is
creating this sort of inconsistencies and everything should refer
to a single I915_MAX_GT. The reason for having I915_PMU_MAX_GTS,
in a first place, is purely practical to avoid over inclusions.
Still I consider it hacky.
On the other had, already I915_MAX_GT is a hardcoded value and
many times there have been discussions about removing it and
fetch it dynamically during the i915 boot. But this requires
quite a good amount of refactoring that no one is willing to do.
If we can't get rid of I915_PMU_MAX_GTS then I strongly believe
it should be aligned with I915_MAX_GT and for this reason I gave
my r-b. The use of for_each_gt() is a clear consequence of this
difference.
Thanks for chiming in,
Andi
Re: [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
On Thu, 01 Jun 2023 11:30:44 -0700, Dixit, Ashutosh wrote:
>
> On Thu, 01 Jun 2023 11:22:18 -0700, Dixit, Ashutosh wrote:
> >
> > On Wed, 31 May 2023 14:35:47 -0700, Matt Atwood wrote:
> > >
> >
> > Hi Matt,
> >
> > > Set I915_PMU_MAX_GTS to value in I915_MAX_GT, theres no reason for these
> > > values to be different.
>
> Also, we can't be so sure so as to be able to say "theres no reason for
> these values to be different" till we have actually verified it. E.g. there
> are various bitfields in the code which might not fit in a u32 if we
> increase MAX_GT from 2 to 4. Has this been verified?
>
> If anything, to keep the code from doing unnecessary stuff, IMO I915_MAX_GT
> should be reduced to 2 and should be increased to 4 only once/if we have
> i915 supported platforms with 4 GT's.
Matt explained the issue offline to me (it would have helped to explain the
reason for the patch in the commit message). The issue is that in uses of
for_each_gt such as below (there are others too in the PMU code):
for_each_gt(gt, i915, i) {
intel_wakeref_t wakeref;
with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
u64 val = __get_rc6(gt);
store_sample(pmu, i, __I915_SAMPLE_RC6, val);
store_sample(pmu, i, __I915_SAMPLE_RC6_LAST_REPORTED,
val);
pmu->sleep_last[i] = ktime_get_raw();
}
}
static checkers are complaining that for_each_gt can read/write outside the
bounds of PMU arrays. Because absent gt's will be NULL in for_each_gt this
cannot really happen but we still need to keep static checkers happy.
So to resolve this issue we need I915_PMU_MAX_GTS and I915_MAX_GT to have
the same value. So either we need to increase I915_PMU_MAX_GTS to 4 or
reduce I915_MAX_GT to 2.
Regards,
Ashutosh
>
>
> > >
> > > Cc: Tvrtko Ursulin
> > > Cc: Umesh Nerlige Ramappa
> > > Cc: Ashutosh Dixit
> >
> > I don't believe the mailer actually Cc'd us. I just saw this and am Cc'ing
> > the people who authored/reviewed the previous series now.
> >
> > > Signed-off-by: Matt Atwood
> > > ---
> > > drivers/gpu/drm/i915/i915_pmu.h | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_pmu.h
> > > b/drivers/gpu/drm/i915/i915_pmu.h
> > > index 33d80fbaab8b..aa929d8c224a 100644
> > > --- a/drivers/gpu/drm/i915/i915_pmu.h
> > > +++ b/drivers/gpu/drm/i915/i915_pmu.h
> > > @@ -38,7 +38,7 @@ enum {
> > > __I915_NUM_PMU_SAMPLERS
> > > };
> > >
> > > -#define I915_PMU_MAX_GTS 2
> > > +#define I915_PMU_MAX_GTS 4
> >
> > This was a discussed during the previous review and it was decided to keep
> > the two values (I915_PMU_MAX_GTS and I915_MAX_GT) different. There are
> > currently no platforms and there will be no i915 supported platforms with
> > MAX_GT 4. So I prefer to leave the values as they currently are. Unless
> > Umesh or Tvrtko agrees to this patch.
> >
> > Thanks.
> > --
> > Ashutosh
> >
> > >
> > > /*
> > > * How many different events we track in the global PMU mask.
> > > --
> > > 2.40.0
> > >
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pxp: use correct format string for size_t
== Series Details ==
Series: drm/i915/pxp: use correct format string for size_t
URL : https://patchwork.freedesktop.org/series/118731/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13217 -> Patchwork_118731v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118731v1/index.html
Participating hosts (38 -> 37)
--
Missing(1): bat-rpls-2
Known issues
Here are the changes found in Patchwork_118731v1 that come from known issues:
### CI changes ###
Possible fixes
* boot:
- fi-kbl-8809g: [FAIL][1] ([i915#8293] / [i915#8298]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/fi-kbl-8809g/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118731v1/fi-kbl-8809g/boot.html
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-kbl-8809g: NOTRUN -> [ABORT][3] ([i915#8298] / [i915#8299] /
[i915#8397])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118731v1/fi-kbl-8809g/igt@core_hotunp...@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118731v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-hsw-4770:[PASS][5] -> [SKIP][6] ([fdo#109271])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/fi-hsw-4770/igt@i915_pm_...@basic-pci-d3-state.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118731v1/fi-hsw-4770/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- fi-hsw-4770:[PASS][7] -> [FAIL][8] ([i915#7364])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/fi-hsw-4770/igt@i915_pm_...@basic-rte.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118731v1/fi-hsw-4770/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live@migrate:
- bat-rpls-1: [PASS][9] -> [DMESG-FAIL][10] ([i915#7699])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-rpls-1/igt@i915_selftest@l...@migrate.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118731v1/bat-rpls-1/igt@i915_selftest@l...@migrate.html
* igt@i915_selftest@live@workarounds:
- bat-adlm-1: [PASS][11] -> [INCOMPLETE][12] ([i915#4983] /
[i915#7677])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-adlm-1/igt@i915_selftest@l...@workarounds.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118731v1/bat-adlm-1/igt@i915_selftest@l...@workarounds.html
* igt@kms_addfb_basic@too-high:
- fi-kbl-8809g: NOTRUN -> [FAIL][13] ([i915#8296]) +2 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118731v1/fi-kbl-8809g/igt@kms_addfb_ba...@too-high.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][14] ([i915#7828])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118731v1/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-8809g: NOTRUN -> [DMESG-FAIL][15] ([i915#8299])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118731v1/fi-kbl-8809g/igt@kms_force_connector_ba...@force-connector-state.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-8809g: NOTRUN -> [CRASH][16] ([i915#8299])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118731v1/fi-kbl-8809g/igt@kms_force_connector_ba...@force-edid.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-adlp-9: NOTRUN -> [SKIP][17] ([i915#3546]) +1 similar issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118731v1/bat-adlp-9/igt@kms_pipe_crc_ba...@read-crc.html
- bat-dg2-11: NOTRUN -> [SKIP][18] ([i915#1845] / [i915#5354]) +1
similar issue
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118731v1/bat-dg2-11/igt@kms_pipe_crc_ba...@read-crc.html
* igt@kms_psr@cursor_plane_move:
- fi-kbl-8809g: NOTRUN -> [SKIP][19] ([fdo#109271]) +59 similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118731v1/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-kbl-8809g: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4579])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118731v1/fi-kbl-8809g/igt@kms_setm...@basic-clone-single-crtc.html
Possible fixes
* igt@i915_selftest@live@gt_mocs:
- {bat-mtlp-8}: [DMESG-FAIL][21] ([i915#7059]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
[22]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/pxp: use correct format string for size_t
== Series Details ==
Series: drm/i915/pxp: use correct format string for size_t
URL : https://patchwork.freedesktop.org/series/118731/
State : warning
== Summary ==
Error: dim checkpatch failed
f813cf5d141a drm/i915/pxp: use correct format string for size_t
-:13: WARNING:BAD_FIXES_TAG: Please use correct Fixes: style 'Fixes: <12 chars
of sha1> ("")' - ie: 'Fixes: dc9ac125d81f ("drm/i915/pxp: Add
GSC-CS backend to send GSC fw messages")'
#13:
Fixes: dc9ac125d81fa ("drm/i915/pxp: Add GSC-CS backend to send GSC fw
messages")
total: 0 errors, 1 warnings, 0 checks, 8 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Extract display init from intel_device_info_runtime_init
== Series Details ==
Series: drm/i915/display: Extract display init from
intel_device_info_runtime_init
URL : https://patchwork.freedesktop.org/series/118730/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13217 -> Patchwork_118730v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v1/index.html
Participating hosts (38 -> 38)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_118730v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@reset:
- bat-rpls-1: [PASS][1] -> [ABORT][2] ([i915#4983] / [i915#7461] /
[i915#8347] / [i915#8384])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-rpls-1/igt@i915_selftest@l...@reset.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v1/bat-rpls-1/igt@i915_selftest@l...@reset.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][3] ([i915#7828])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v1/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1:
- bat-dg2-8: [PASS][4] -> [FAIL][5] ([i915#7932])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-adlp-9: NOTRUN -> [SKIP][6] ([i915#3546]) +1 similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v1/bat-adlp-9/igt@kms_pipe_crc_ba...@read-crc.html
- bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#1845] / [i915#5354]) +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v1/bat-dg2-11/igt@kms_pipe_crc_ba...@read-crc.html
Possible fixes
* igt@i915_module_load@load:
- {bat-adlp-11}: [ABORT][8] ([i915#4423]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-adlp-11/igt@i915_module_l...@load.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v1/bat-adlp-11/igt@i915_module_l...@load.html
* igt@i915_selftest@live@gt_mocs:
- {bat-mtlp-8}: [DMESG-FAIL][10] ([i915#7059]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v1/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@gt_pm:
- bat-rpls-2: [DMESG-FAIL][12] ([i915#4258] / [i915#7913]) ->
[PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v1/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@reset:
- bat-dg2-11: [INCOMPLETE][14] ([i915#7913]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-dg2-11/igt@i915_selftest@l...@reset.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v1/bat-dg2-11/igt@i915_selftest@l...@reset.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1:
- bat-dg2-8: [FAIL][16] ([i915#7932]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#8347]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: Extract display init from intel_device_info_runtime_init
== Series Details == Series: drm/i915/display: Extract display init from intel_device_info_runtime_init URL : https://patchwork.freedesktop.org/series/118730/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Extract display init from intel_device_info_runtime_init
== Series Details == Series: drm/i915/display: Extract display init from intel_device_info_runtime_init URL : https://patchwork.freedesktop.org/series/118730/ State : warning == Summary == Error: dim checkpatch failed 7e88c49f41ae drm/i915/display: Extract display init from intel_device_info_runtime_init -:304: CHECK:SPACING: No space is necessary after a cast #304: FILE: drivers/gpu/drm/i915/intel_device_info.c:416: + BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); total: 0 errors, 0 warnings, 1 checks, 291 lines checked
Re: [Intel-gfx] [PATCH v5 5/7] drm/i915/mtl/huc: auth HuC via GSC
On Wed, 2023-05-31 at 16:54 -0700, Ceraolo Spurio, Daniele wrote: > The full authentication via the GSC requires an heci packet submission > to the GSC FW via the GSC CS. The GSC has new PXP command for this > (literally called NEW_HUC_AUTH). > The intel_huc_auth function is also updated to handle both authentication > types. > > alan:snip > @@ -399,6 +416,9 @@ void intel_huc_fini(struct intel_huc *huc) >*/ > delayed_huc_load_fini(huc); > > + if (huc->heci_pkt) > + i915_vma_unpin_and_release(>heci_pkt, 0); alan: nit: i just realized that for consistency (init mirror-ing fini), we should be doing this heci releasing after the intel_uc_fw_fini below. But since the below object isnt referencing the heci packet, this doens't matter, so consider a nit. alan:snip > @@ -470,31 +491,41 @@ int intel_huc_auth(struct intel_huc *huc) > if (!intel_uc_fw_is_loaded(>fw)) > return -ENOEXEC; > > - /* GSC will do the auth */ > + /* GSC will do the auth with the load */ > if (intel_huc_is_loaded_by_gsc(huc)) > return -ENODEV; alan: nit: sorry for another late comment but merely a nit - wondering if we should add a warn in here (to catch if we could end up here) but its okay - this in theory shouldnt happen anyway. alan:snip > +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c alan:snip Only a couple of late-comer-nits that you can ignore, else LGTM: Reviewed-by: Alan Previn
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pxp: Optimize GET_PARAM:PXP_STATUS
== Series Details ==
Series: drm/i915/pxp: Optimize GET_PARAM:PXP_STATUS
URL : https://patchwork.freedesktop.org/series/118723/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13217 -> Patchwork_118723v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v1/index.html
Participating hosts (38 -> 37)
--
Missing(1): fi-kbl-soraka
Known issues
Here are the changes found in Patchwork_118723v1 that come from known issues:
### CI changes ###
Possible fixes
* boot:
- fi-kbl-8809g: [FAIL][1] ([i915#8293] / [i915#8298]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/fi-kbl-8809g/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v1/fi-kbl-8809g/boot.html
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-kbl-8809g: NOTRUN -> [ABORT][3] ([i915#8298] / [i915#8299] /
[i915#8397])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v1/fi-kbl-8809g/igt@core_hotunp...@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: [PASS][5] -> [ABORT][6] ([i915#4983] / [i915#7461] /
[i915#7913] / [i915#8347])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-rpls-2/igt@i915_selftest@l...@reset.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v1/bat-rpls-2/igt@i915_selftest@l...@reset.html
* igt@kms_addfb_basic@too-high:
- fi-kbl-8809g: NOTRUN -> [FAIL][7] ([i915#8296]) +2 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v1/fi-kbl-8809g/igt@kms_addfb_ba...@too-high.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#7828])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v1/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-8809g: NOTRUN -> [DMESG-FAIL][9] ([i915#8299])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v1/fi-kbl-8809g/igt@kms_force_connector_ba...@force-connector-state.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-8809g: NOTRUN -> [CRASH][10] ([i915#8299])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v1/fi-kbl-8809g/igt@kms_force_connector_ba...@force-edid.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-adlp-9: NOTRUN -> [SKIP][11] ([i915#3546]) +1 similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v1/bat-adlp-9/igt@kms_pipe_crc_ba...@read-crc.html
- bat-dg2-11: NOTRUN -> [SKIP][12] ([i915#1845] / [i915#5354]) +1
similar issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v1/bat-dg2-11/igt@kms_pipe_crc_ba...@read-crc.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-3:
- bat-dg2-9: [PASS][13] -> [FAIL][14] ([fdo#103375]) +1 similar
issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-dp-3.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v1/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-dp-3.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-3:
- bat-dg2-9: [PASS][15] -> [FAIL][16] ([fdo#103375] / [i915#7932])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-dp-3.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v1/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-dp-3.html
* igt@kms_psr@cursor_plane_move:
- fi-kbl-8809g: NOTRUN -> [SKIP][17] ([fdo#109271]) +59 similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v1/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-kbl-8809g: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4579])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v1/fi-kbl-8809g/igt@kms_setm...@basic-clone-single-crtc.html
Possible fixes
* igt@i915_selftest@live@gt_mocs:
- {bat-mtlp-8}: [DMESG-FAIL][19] ([i915#7059]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118723v1/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@gt_pm:
- bat-rpls-2: [DMESG-FAIL][21] ([i915#4258] /
Re: [Intel-gfx] [PATCH 2/2] drm/i915/hdcp: Modify intel_gsc_send_sync function
On 5/29/2023 4:49 AM, Suraj Kandpal wrote:
Modify intel_gsc_send_sync() to take into account header_out
and addr_out so as to use them to verify the message send status.
Cc: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: Ankit Nautiyal
Signed-off-by: Suraj Kandpal
I think this patch should be squashed with the previous one, because if
I understand correctly the code won't work with just the first one,
which could be a problem with bisection. The changes themselves look ok
to me though, so for the unified patch (with the small fix I pointed out
in the other reply):
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 29 +++
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
index 72d1e261d0a9..5f29c3c559fa 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
@@ -726,38 +726,42 @@ void intel_hdcp_gsc_fini(struct drm_i915_private *i915)
}
static int intel_gsc_send_sync(struct drm_i915_private *i915,
- struct intel_gsc_mtl_header *header, u64 addr,
+ struct intel_gsc_mtl_header *header_in,
+ struct intel_gsc_mtl_header *header_out,
+ u64 addr_in, u64 addr_out,
size_t msg_out_len)
{
struct intel_gt *gt = i915->media_gt;
int ret;
- header->flags = 0;
- ret = intel_gsc_uc_heci_cmd_submit_packet(>uc.gsc, addr,
- header->message_size,
- addr,
- msg_out_len +
sizeof(*header));
+ ret = intel_gsc_uc_heci_cmd_submit_packet(>uc.gsc, addr_in,
+ header_in->message_size,
+ addr_out,
+ msg_out_len +
sizeof(*header_out));
if (ret) {
drm_err(>drm, "failed to send gsc HDCP msg (%d)\n", ret);
return ret;
}
/*
-* Checking validity marker for memory sanity
+* Checking validity marker and header status to see if some error has
+* blocked us from sending message to gsc cs
*/
- if (header->validity_marker != GSC_HECI_VALIDITY_MARKER) {
+ if (header_out->validity_marker != GSC_HECI_VALIDITY_MARKER) {
drm_err(>drm, "invalid validity marker\n");
return -EINVAL;
}
- if (header->status != 0) {
+ if (header_out->status != 0) {
drm_err(>drm, "header status indicates error %d\n",
- header->status);
+ header_out->status);
return -EINVAL;
}
- if (header->flags & GSC_OUTFLAG_MSG_PENDING)
+ if (header_out->flags & GSC_OUTFLAG_MSG_PENDING) {
+ header_in->gsc_message_handle = header_out->gsc_message_handle;
return -EAGAIN;
+ }
return 0;
}
@@ -809,7 +813,8 @@ ssize_t intel_hdcp_gsc_msg_send(struct drm_i915_private
*i915, u8 *msg_in,
* 20 times each message 50 ms apart
*/
do {
- ret = intel_gsc_send_sync(i915, header_in, addr_in,
msg_out_len);
+ ret = intel_gsc_send_sync(i915, header_in, header_out, addr_in,
+ addr_out, msg_out_len);
/* Only try again if gsc says so */
if (ret != -EAGAIN)
Re: [Intel-gfx] [PATCH 1/2] drm/i915/hdcp: Allocate a multipage object to hdcp_gsc_message
On 5/29/2023 4:49 AM, Suraj Kandpal wrote:
Allocate a multipage object that can be used for input
and output for intel_hdcp_gsc_message so that corruption of
output message can be avoided by the current overwriting method.
--v2
-Change approach from allocating two objects to just one multipage
object [Daniele]
Cc: Ankit Nautiyal
Cc: Alan Previn
Cc: Daniele Ceraolo Spurio
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 55 +++
drivers/gpu/drm/i915/display/intel_hdcp_gsc.h | 3 +-
2 files changed, 34 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
index 7e52aea6aa17..72d1e261d0a9 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
@@ -621,24 +621,26 @@ static int intel_hdcp_gsc_initialize_message(struct
drm_i915_private *i915,
struct intel_gt *gt = i915->media_gt;
struct drm_i915_gem_object *obj = NULL;
struct i915_vma *vma = NULL;
- void *cmd;
+ void *cmd_in, *cmd_out;
int err;
- /* allocate object of one page for HDCP command memory and store it */
- obj = i915_gem_object_create_shmem(i915, PAGE_SIZE);
+ /* allocate object of two page for HDCP command memory and store it */
+ obj = i915_gem_object_create_shmem(i915, 2 * PAGE_SIZE);
if (IS_ERR(obj)) {
drm_err(>drm, "Failed to allocate HDCP streaming
command!\n");
return PTR_ERR(obj);
}
- cmd = i915_gem_object_pin_map_unlocked(obj, i915_coherent_map_type(i915, obj, true));
- if (IS_ERR(cmd)) {
+ cmd_in = i915_gem_object_pin_map_unlocked(obj,
i915_coherent_map_type(i915, obj, true));
+ if (IS_ERR(cmd_in)) {
drm_err(>drm, "Failed to map gsc message page!\n");
- err = PTR_ERR(cmd);
+ err = PTR_ERR(cmd_in);
goto out_unpin;
}
+ cmd_out = cmd_in + PAGE_SIZE;
+
vma = i915_vma_instance(obj, >ggtt->vm, NULL);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
@@ -649,9 +651,10 @@ static int intel_hdcp_gsc_initialize_message(struct
drm_i915_private *i915,
if (err)
goto out_unmap;
- memset(cmd, 0, obj->base.size);
+ memset(cmd_in, 0, obj->base.size);
- hdcp_message->hdcp_cmd = cmd;
+ hdcp_message->hdcp_cmd_in = cmd_in;
+ hdcp_message->hdcp_cmd_out = cmd_out;
hdcp_message->vma = vma;
return 0;
@@ -668,7 +671,7 @@ static int intel_hdcp_gsc_hdcp2_init(struct
drm_i915_private *i915)
struct intel_hdcp_gsc_message *hdcp_message;
int ret;
- hdcp_message = kzalloc(sizeof(*hdcp_message), GFP_KERNEL);
+ hdcp_message = kzalloc(2 * sizeof(*hdcp_message), GFP_KERNEL);
As far as I can see you only need 1 hdcp_message structure, so no need
to double the alloc size here.
With this fixed:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
if (!hdcp_message)
return -ENOMEM;
@@ -691,6 +694,8 @@ static void intel_hdcp_gsc_free_message(struct
drm_i915_private *i915)
struct intel_hdcp_gsc_message *hdcp_message =
i915->display.hdcp.hdcp_message;
+ hdcp_message->hdcp_cmd_in = NULL;
+ hdcp_message->hdcp_cmd_out = NULL;
i915_vma_unpin_and_release(_message->vma, I915_VMA_RELEASE_MAP);
kfree(hdcp_message);
}
@@ -769,11 +774,11 @@ ssize_t intel_hdcp_gsc_msg_send(struct drm_i915_private
*i915, u8 *msg_in,
size_t msg_out_len)
{
struct intel_gt *gt = i915->media_gt;
- struct intel_gsc_mtl_header *header;
- const size_t max_msg_size = PAGE_SIZE - sizeof(*header);
+ struct intel_gsc_mtl_header *header_in, *header_out;
+ const size_t max_msg_size = PAGE_SIZE - sizeof(*header_in);
struct intel_hdcp_gsc_message *hdcp_message;
- u64 addr, host_session_id;
- u32 reply_size, msg_size;
+ u64 addr_in, addr_out, host_session_id;
+ u32 reply_size, msg_size_in, msg_size_out;
int ret, tries = 0;
if (!intel_uc_uses_gsc_uc(>uc))
@@ -782,16 +787,20 @@ ssize_t intel_hdcp_gsc_msg_send(struct drm_i915_private
*i915, u8 *msg_in,
if (msg_in_len > max_msg_size || msg_out_len > max_msg_size)
return -ENOSPC;
+ msg_size_in = msg_in_len + sizeof(*header_in);
+ msg_size_out = msg_out_len + sizeof(*header_out);
hdcp_message = i915->display.hdcp.hdcp_message;
- header = hdcp_message->hdcp_cmd;
- addr = i915_ggtt_offset(hdcp_message->vma);
+ header_in = hdcp_message->hdcp_cmd_in;
+ header_out = hdcp_message->hdcp_cmd_out;
+ addr_in = i915_ggtt_offset(hdcp_message->vma);
+ addr_out = addr_in + PAGE_SIZE;
- msg_size = msg_in_len + sizeof(*header);
- memset(header, 0, msg_size);
+ memset(header_in,
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix error handling if driver creation fails during probe
== Series Details ==
Series: drm/i915: Fix error handling if driver creation fails during probe
URL : https://patchwork.freedesktop.org/series/118722/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13217 -> Patchwork_118722v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118722v1/index.html
Participating hosts (38 -> 36)
--
Missing(2): bat-rpls-2 bat-dg1-5
Known issues
Here are the changes found in Patchwork_118722v1 that come from known issues:
### CI changes ###
Possible fixes
* boot:
- fi-kbl-8809g: [FAIL][1] ([i915#8293] / [i915#8298]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/fi-kbl-8809g/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118722v1/fi-kbl-8809g/boot.html
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-kbl-8809g: NOTRUN -> [ABORT][3] ([i915#8298] / [i915#8299] /
[i915#8397])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118722v1/fi-kbl-8809g/igt@core_hotunp...@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118722v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@i915_selftest@live@guc:
- bat-rpls-1: [PASS][5] -> [DMESG-WARN][6] ([i915#7852])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-rpls-1/igt@i915_selftest@l...@guc.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118722v1/bat-rpls-1/igt@i915_selftest@l...@guc.html
* igt@kms_addfb_basic@too-high:
- fi-kbl-8809g: NOTRUN -> [FAIL][7] ([i915#8296]) +2 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118722v1/fi-kbl-8809g/igt@kms_addfb_ba...@too-high.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#7828])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118722v1/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-8809g: NOTRUN -> [DMESG-FAIL][9] ([i915#8299])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118722v1/fi-kbl-8809g/igt@kms_force_connector_ba...@force-connector-state.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-8809g: NOTRUN -> [CRASH][10] ([i915#8299])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118722v1/fi-kbl-8809g/igt@kms_force_connector_ba...@force-edid.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#1845] / [i915#5354]) +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118722v1/bat-dg2-11/igt@kms_pipe_crc_ba...@read-crc.html
* igt@kms_psr@cursor_plane_move:
- fi-kbl-8809g: NOTRUN -> [SKIP][12] ([fdo#109271]) +59 similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118722v1/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-kbl-8809g: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4579])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118722v1/fi-kbl-8809g/igt@kms_setm...@basic-clone-single-crtc.html
Possible fixes
* igt@i915_module_load@load:
- {bat-adlp-11}: [ABORT][14] ([i915#4423]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-adlp-11/igt@i915_module_l...@load.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118722v1/bat-adlp-11/igt@i915_module_l...@load.html
* igt@i915_selftest@live@reset:
- bat-dg2-11: [INCOMPLETE][16] ([i915#7913]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-dg2-11/igt@i915_selftest@l...@reset.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118722v1/bat-dg2-11/igt@i915_selftest@l...@reset.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1:
- bat-dg2-8: [FAIL][18] ([i915#7932]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118722v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3282]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix error handling if driver creation fails during probe
== Series Details == Series: drm/i915: Fix error handling if driver creation fails during probe URL : https://patchwork.freedesktop.org/series/118722/ State : warning == Summary == Error: dim checkpatch failed 69336201b326 drm/i915: Fix error handling if driver creation fails during probe -:12: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report #12: Reported-by: Dan Carpenter Signed-off-by: Matt Roper total: 0 errors, 1 warnings, 0 checks, 10 lines checked
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Fix recent kCFI violations
== Series Details ==
Series: drm/i915/gt: Fix recent kCFI violations
URL : https://patchwork.freedesktop.org/series/118591/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13206_full -> Patchwork_118591v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_118591v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][1] -> [DMESG-FAIL][2] ([i915#8319])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-snb5/igt@i915_pm_...@reset.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118591v1/shard-snb4/igt@i915_pm_...@reset.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4579]) +4
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118591v1/shard-snb1/igt@kms_dither@fb-8bpc-vs-panel-6...@pipe-a-hdmi-a-1.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][4] -> [FAIL][5] ([i915#4767])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-apl7/igt@kms_fbcon_...@fbc-suspend.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118591v1/shard-apl6/igt@kms_fbcon_...@fbc-suspend.html
* igt@kms_flip@flip-vs-suspend@b-dp1:
- shard-apl: [PASS][6] -> [ABORT][7] ([i915#180]) +1 similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-apl1/igt@kms_flip@flip-vs-susp...@b-dp1.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118591v1/shard-apl2/igt@kms_flip@flip-vs-susp...@b-dp1.html
*
igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-20x20@pipe-a-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271]) +7 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118591v1/shard-snb1/igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-20...@pipe-a-hdmi-a-1.html
* igt@prime_busy@hang@vecs0:
- shard-glk: [PASS][9] -> [INCOMPLETE][10] ([i915#8218])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-glk9/igt@prime_busy@h...@vecs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118591v1/shard-glk7/igt@prime_busy@h...@vecs0.html
Possible fixes
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- {shard-rkl}:[FAIL][11] ([i915#7742]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-rkl-1/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118591v1/shard-rkl-3/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
* igt@gem_eio@hibernate:
- {shard-tglu}: [ABORT][13] ([i915#7975] / [i915#8213] / [i915#8398])
-> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-tglu-10/igt@gem_...@hibernate.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118591v1/shard-tglu-9/igt@gem_...@hibernate.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][15] ([i915#2846]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-glk5/igt@gem_exec_f...@basic-deadline.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118591v1/shard-glk9/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [FAIL][17] ([i915#2842]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-apl7/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118591v1/shard-apl6/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@i915_pm_rc6_residency@rc6-idle@bcs0:
- {shard-dg1}:[FAIL][19] ([i915#3591]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-i...@bcs0.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118591v1/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-i...@bcs0.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- {shard-rkl}:[SKIP][21] ([i915#1397]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-rkl-7/igt@i915_pm_...@modeset-non-lpsp-stress-no-wait.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118591v1/shard-rkl-6/igt@i915_pm_...@modeset-non-lpsp-stress-no-wait.html
* igt@kms_cursor_legacy@single-move@pipe-b:
- {shard-rkl}:[INCOMPLETE][23] ([i915#8011]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-rkl-7/igt@kms_cursor_legacy@single-m...@pipe-b.html
[24]:
[Intel-gfx] ✓ Fi.CI.BAT: success for mtl: add support for pmdemand (rev12)
== Series Details == Series: mtl: add support for pmdemand (rev12) URL : https://patchwork.freedesktop.org/series/116949/ State : success == Summary == CI Bug Log - changes from CI_DRM_13217 -> Patchwork_116949v12 Summary --- **WARNING** Minor unknown changes coming with Patchwork_116949v12 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_116949v12, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v12/index.html Participating hosts (38 -> 37) -- Missing(1): fi-kbl-soraka Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_116949v12: ### IGT changes ### Warnings * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-a-edp-1: - bat-adlp-6: [ABORT][1] ([i915#8434]) -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-adlp-6/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-a-edp-1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v12/bat-adlp-6/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-a-edp-1.html * igt@kms_psr@sprite_plane_onoff: - bat-rplp-1: [SKIP][3] ([i915#1072]) -> [ABORT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v12/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html Known issues Here are the changes found in Patchwork_116949v12 that come from known issues: ### CI changes ### Possible fixes * boot: - fi-kbl-8809g: [FAIL][5] ([i915#8293] / [i915#8298]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/fi-kbl-8809g/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v12/fi-kbl-8809g/boot.html ### IGT changes ### Issues hit * igt@core_hotunplug@unbind-rebind: - fi-kbl-8809g: NOTRUN -> [ABORT][7] ([i915#8298] / [i915#8299] / [i915#8397]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v12/fi-kbl-8809g/igt@core_hotunp...@unbind-rebind.html * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v12/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@i915_selftest@live@mman: - bat-rpls-2: [PASS][9] -> [TIMEOUT][10] ([i915#6794] / [i915#7392]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-rpls-2/igt@i915_selftest@l...@mman.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v12/bat-rpls-2/igt@i915_selftest@l...@mman.html * igt@i915_selftest@live@requests: - bat-rpls-1: [PASS][11] -> [ABORT][12] ([i915#7911] / [i915#7920]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-rpls-1/igt@i915_selftest@l...@requests.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v12/bat-rpls-1/igt@i915_selftest@l...@requests.html * igt@kms_addfb_basic@too-high: - fi-kbl-8809g: NOTRUN -> [FAIL][13] ([i915#8296]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v12/fi-kbl-8809g/igt@kms_addfb_ba...@too-high.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-dg2-11: NOTRUN -> [SKIP][14] ([i915#7828]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v12/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_force_connector_basic@force-connector-state: - fi-kbl-8809g: NOTRUN -> [DMESG-FAIL][15] ([i915#8299]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v12/fi-kbl-8809g/igt@kms_force_connector_ba...@force-connector-state.html * igt@kms_force_connector_basic@force-edid: - fi-kbl-8809g: NOTRUN -> [CRASH][16] ([i915#8299]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v12/fi-kbl-8809g/igt@kms_force_connector_ba...@force-edid.html * igt@kms_pipe_crc_basic@read-crc: - bat-dg2-11: NOTRUN -> [SKIP][17] ([i915#1845] / [i915#5354]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v12/bat-dg2-11/igt@kms_pipe_crc_ba...@read-crc.html * igt@kms_psr@cursor_plane_move: - fi-kbl-8809g: NOTRUN -> [SKIP][18] ([fdo#109271]) +59 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v12/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html * igt@kms_setmode@basic-clone-single-crtc: - fi-kbl-8809g: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4579]) [19]:
Re: [Intel-gfx] [PATCH] drm/i915/pxp: use correct format string for size_t
On Thu, 2023-06-01 at 23:36 +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> While 'unsigned long' needs the %ld format string, size_t needs the %z
> modifier:
alan:snip
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
> @@ -143,7 +143,7 @@ gsccs_send_message(struct intel_pxp *pxp,
>
> reply_size = header->message_size - sizeof(*header);
> if (reply_size > msg_out_size_max) {
> - drm_warn(>drm, "caller with insufficient PXP reply size
> %u (%ld)\n",
> + drm_warn(>drm, "caller with insufficient PXP reply size
> %u (%zd)\n",
>reply_size, msg_out_size_max);
> reply_size = msg_out_size_max;
> }
Thanks Arnd for catching this, although i believe Nathan sumbmitted a patch for
the same fix yesterday and received an RB from Andi.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for mtl: add support for pmdemand (rev12)
== Series Details == Series: mtl: add support for pmdemand (rev12) URL : https://patchwork.freedesktop.org/series/116949/ State : warning == Summary == Error: dim checkpatch failed 8ae8740d3ed0 drm/i915: fix the derating percentage for MTL 277951603ecd drm/i915: update the QGV point frequency calculations 2d21cda650ba drm/i915: store the peak bw per QGV point a7ee7441f55e drm/i915: extract intel_bw_check_qgv_points() 74a46c7841e5 drm/i915: modify max_bw to return index to intel_bw_info c3f2f3aae217 drm/i915/mtl: find the best QGV point for the SAGV configuration b8e50275587b drm/i915/mtl: Add support for PM DEMAND Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:352: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #352: new file mode 100644 -:967: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #967: FILE: drivers/gpu/drm/i915/i915_reg.h:4511: +#define XELPDP_PMDEMAND_QCLK_GV_BW(x) REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, x) -:969: WARNING:LONG_LINE: line length of 109 exceeds 100 columns #969: FILE: drivers/gpu/drm/i915/i915_reg.h:4513: +#define XELPDP_PMDEMAND_VOLTAGE_INDEX(x) REG_FIELD_PREP(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, x) -:971: WARNING:LONG_LINE: line length of 109 exceeds 100 columns #971: FILE: drivers/gpu/drm/i915/i915_reg.h:4515: +#define XELPDP_PMDEMAND_QCLK_GV_INDEX(x) REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, x) -:973: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #973: FILE: drivers/gpu/drm/i915/i915_reg.h:4517: +#define XELPDP_PMDEMAND_PIPES(x) REG_FIELD_PREP(XELPDP_PMDEMAND_PIPES_MASK, x) -:975: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #975: FILE: drivers/gpu/drm/i915/i915_reg.h:4519: +#define XELPDP_PMDEMAND_DBUFS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK, x) -:981: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #981: FILE: drivers/gpu/drm/i915/i915_reg.h:4525: +#define XELPDP_PMDEMAND_CDCLK_FREQ(x) REG_FIELD_PREP(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, x) -:983: WARNING:LONG_LINE: line length of 107 exceeds 100 columns #983: FILE: drivers/gpu/drm/i915/i915_reg.h:4527: +#define XELPDP_PMDEMAND_DDICLK_FREQ(x) REG_FIELD_PREP(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, x) -:985: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #985: FILE: drivers/gpu/drm/i915/i915_reg.h:4529: +#define XELPDP_PMDEMAND_SCALERS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_SCALERS_MASK, x) total: 0 errors, 9 warnings, 0 checks, 870 lines checked
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for mtl: add support for pmdemand (rev12)
== Series Details == Series: mtl: add support for pmdemand (rev12) URL : https://patchwork.freedesktop.org/series/116949/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] [PATCH] drm/i915/pxp: use correct format string for size_t
From: Arnd Bergmann
While 'unsigned long' needs the %ld format string, size_t needs the %z
modifier:
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c: In function 'gsccs_send_message':
include/drm/drm_print.h:456:39: error: format '%ld' expects argument of type
'long int', but argument 4 has type 'size_t' {aka 'unsigned int'}
[-Werror=format=]
456 | dev_##level##type((drm)->dev, "[drm] " fmt, ##__VA_ARGS__)
Fixes: dc9ac125d81fa ("drm/i915/pxp: Add GSC-CS backend to send GSC fw
messages")
Signed-off-by: Arnd Bergmann
---
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
index 8dc41de3f6f74..290ed5ac487de 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
@@ -143,7 +143,7 @@ gsccs_send_message(struct intel_pxp *pxp,
reply_size = header->message_size - sizeof(*header);
if (reply_size > msg_out_size_max) {
- drm_warn(>drm, "caller with insufficient PXP reply size
%u (%ld)\n",
+ drm_warn(>drm, "caller with insufficient PXP reply size
%u (%zd)\n",
reply_size, msg_out_size_max);
reply_size = msg_out_size_max;
}
--
2.39.2
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pxp/mtl: intel_pxp_init_hw needs runtime-pm inside pm-complete
== Series Details ==
Series: drm/i915/pxp/mtl: intel_pxp_init_hw needs runtime-pm inside pm-complete
URL : https://patchwork.freedesktop.org/series/118714/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13217 -> Patchwork_118714v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118714v1/index.html
Participating hosts (38 -> 37)
--
Missing(1): fi-kbl-soraka
Known issues
Here are the changes found in Patchwork_118714v1 that come from known issues:
### CI changes ###
Possible fixes
* boot:
- fi-kbl-8809g: [FAIL][1] ([i915#8293] / [i915#8298]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/fi-kbl-8809g/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118714v1/fi-kbl-8809g/boot.html
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-kbl-8809g: NOTRUN -> [ABORT][3] ([i915#8298] / [i915#8299] /
[i915#8397])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118714v1/fi-kbl-8809g/igt@core_hotunp...@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118714v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@i915_selftest@live@guc:
- bat-rpls-2: [PASS][5] -> [DMESG-WARN][6] ([i915#7852])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-rpls-2/igt@i915_selftest@l...@guc.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118714v1/bat-rpls-2/igt@i915_selftest@l...@guc.html
* igt@i915_selftest@live@hangcheck:
- bat-dg2-11: NOTRUN -> [INCOMPLETE][7] ([i915#7913])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118714v1/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html
* igt@kms_addfb_basic@too-high:
- fi-kbl-8809g: NOTRUN -> [FAIL][8] ([i915#8296]) +2 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118714v1/fi-kbl-8809g/igt@kms_addfb_ba...@too-high.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-8809g: NOTRUN -> [DMESG-FAIL][9] ([i915#8299])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118714v1/fi-kbl-8809g/igt@kms_force_connector_ba...@force-connector-state.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-8809g: NOTRUN -> [CRASH][10] ([i915#8299])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118714v1/fi-kbl-8809g/igt@kms_force_connector_ba...@force-edid.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-adlp-9: NOTRUN -> [SKIP][11] ([i915#3546]) +1 similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118714v1/bat-adlp-9/igt@kms_pipe_crc_ba...@read-crc.html
- bat-dg2-11: NOTRUN -> [SKIP][12] ([i915#1845] / [i915#5354]) +1
similar issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118714v1/bat-dg2-11/igt@kms_pipe_crc_ba...@read-crc.html
* igt@kms_psr@cursor_plane_move:
- fi-kbl-8809g: NOTRUN -> [SKIP][13] ([fdo#109271]) +59 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118714v1/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-kbl-8809g: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4579])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118714v1/fi-kbl-8809g/igt@kms_setm...@basic-clone-single-crtc.html
Possible fixes
* igt@i915_selftest@live@gt_mocs:
- {bat-mtlp-8}: [DMESG-FAIL][15] ([i915#7059]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118714v1/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@reset:
- bat-dg2-11: [INCOMPLETE][17] ([i915#7913]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-dg2-11/igt@i915_selftest@l...@reset.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118714v1/bat-dg2-11/igt@i915_selftest@l...@reset.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1:
- bat-dg2-8: [FAIL][19] ([i915#7932]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118714v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html
Warnings
* igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: [SKIP][21] ([i915#3555] / [i915#4579]) -> [ABORT][22]
([i915#4579] / [i915#8260])
[21]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests (rev2)
== Series Details ==
Series: drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests
(rev2)
URL : https://patchwork.freedesktop.org/series/117713/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13206_full -> Patchwork_117713v2_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_117713v2_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@system-suspend-devices:
- {shard-tglu}: [PASS][1] -> [ABORT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-tglu-2/igt@i915_pm_...@system-suspend-devices.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v2/shard-tglu-8/igt@i915_pm_...@system-suspend-devices.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@a-hdmi-a1:
- {shard-tglu}: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-tglu-2/igt@kms_flip@flip-vs-blocking-wf-vbl...@a-hdmi-a1.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v2/shard-tglu-9/igt@kms_flip@flip-vs-blocking-wf-vbl...@a-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a4:
- {shard-dg1}:[PASS][5] -> [FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-dg1-14/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-hdmi-a4.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v2/shard-dg1-18/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-hdmi-a4.html
Known issues
Here are the changes found in Patchwork_117713v2_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-glk3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v2/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
*
igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][9] ([fdo#109271]) +4 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v2/shard-snb1/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scal...@pipe-a-hdmi-a-1.html
*
igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20@pipe-b-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4579]) +2
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v2/shard-snb1/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20...@pipe-b-hdmi-a-1.html
Possible fixes
* igt@gem_eio@hibernate:
- {shard-tglu}: [ABORT][11] ([i915#7975] / [i915#8213] / [i915#8398])
-> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-tglu-10/igt@gem_...@hibernate.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v2/shard-tglu-2/igt@gem_...@hibernate.html
* igt@gem_exec_fair@basic-none@vcs0:
- {shard-rkl}:[FAIL][13] ([i915#2842]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-rkl-6/igt@gem_exec_fair@basic-n...@vcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v2/shard-rkl-6/igt@gem_exec_fair@basic-n...@vcs0.html
* igt@i915_pm_rc6_residency@rc6-idle@bcs0:
- {shard-dg1}:[FAIL][15] ([i915#3591]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-i...@bcs0.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v2/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-i...@bcs0.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- {shard-rkl}:[SKIP][17] ([i915#1397]) -> [PASS][18] +2 similar
issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-rkl-3/igt@i915_pm_...@dpms-mode-unset-lpsp.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v2/shard-rkl-7/igt@i915_pm_...@dpms-mode-unset-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- {shard-dg1}:[SKIP][19] ([i915#1397]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13206/shard-dg1-13/igt@i915_pm_...@modeset-lpsp-stress.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v2/shard-dg1-19/igt@i915_pm_...@modeset-lpsp-stress.html
* igt@kms_cursor_legacy@single-move@pipe-b:
- {shard-rkl}:[INCOMPLETE][21] ([i915#8011]) -> [PASS][22]
[Intel-gfx] [PATCH] drm/i915/display: Extract display init from intel_device_info_runtime_init
Moving display-specific runtime info initialization into display/ makes
the display code more self-contained and also makes it easier to call
from the Xe driver.
Cc: Jani Nikula
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_display_device.c | 124 +
.../drm/i915/display/intel_display_device.h | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 130 +-
3 files changed, 128 insertions(+), 127 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index 464df1764a86..8d379da877dc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -7,6 +7,8 @@
#include
#include
+#include "display/intel_de.h"
+#include "display/intel_display.h"
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_display_device.h"
@@ -778,3 +780,125 @@ intel_display_device_probe(struct drm_i915_private *i915,
bool has_gmdid,
return _display;
}
+
+void intel_display_device_info_runtime_init(struct drm_i915_private *i915)
+{
+ struct intel_display_runtime_info *display_runtime =
DISPLAY_RUNTIME_INFO(i915);
+ enum pipe pipe;
+
+ /* Wa_14011765242: adl-s A0,A1 */
+ if (IS_ADLS_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
+ for_each_pipe(i915, pipe)
+ display_runtime->num_scalers[pipe] = 0;
+ else if (DISPLAY_VER(i915) >= 11) {
+ for_each_pipe(i915, pipe)
+ display_runtime->num_scalers[pipe] = 2;
+ } else if (DISPLAY_VER(i915) >= 9) {
+ display_runtime->num_scalers[PIPE_A] = 2;
+ display_runtime->num_scalers[PIPE_B] = 2;
+ display_runtime->num_scalers[PIPE_C] = 1;
+ }
+
+ if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915))
+ for_each_pipe(i915, pipe)
+ display_runtime->num_sprites[pipe] = 4;
+ else if (DISPLAY_VER(i915) >= 11)
+ for_each_pipe(i915, pipe)
+ display_runtime->num_sprites[pipe] = 6;
+ else if (DISPLAY_VER(i915) == 10)
+ for_each_pipe(i915, pipe)
+ display_runtime->num_sprites[pipe] = 3;
+ else if (IS_BROXTON(i915)) {
+ /*
+* Skylake and Broxton currently don't expose the topmost plane
as its
+* use is exclusive with the legacy cursor and we only want to
expose
+* one of those, not both. Until we can safely expose the
topmost plane
+* as a DRM_PLANE_TYPE_CURSOR with all the features
exposed/supported,
+* we don't expose the topmost plane at all to prevent ABI
breakage
+* down the line.
+*/
+
+ display_runtime->num_sprites[PIPE_A] = 2;
+ display_runtime->num_sprites[PIPE_B] = 2;
+ display_runtime->num_sprites[PIPE_C] = 1;
+ } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
+ for_each_pipe(i915, pipe)
+ display_runtime->num_sprites[pipe] = 2;
+ } else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) {
+ for_each_pipe(i915, pipe)
+ display_runtime->num_sprites[pipe] = 1;
+ }
+
+ if ((IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) &&
+ !(intel_de_read(i915, GU_CNTL_PROTECTED) & DEPRESENT)) {
+ drm_info(>drm, "Display not present, disabling\n");
+ goto display_fused_off;
+ }
+
+ if (IS_GRAPHICS_VER(i915, 7, 8) && HAS_PCH_SPLIT(i915)) {
+ u32 fuse_strap = intel_de_read(i915, FUSE_STRAP);
+ u32 sfuse_strap = intel_de_read(i915, SFUSE_STRAP);
+
+ /*
+* SFUSE_STRAP is supposed to have a bit signalling the display
+* is fused off. Unfortunately it seems that, at least in
+* certain cases, fused off display means that PCH display
+* reads don't land anywhere. In that case, we read 0s.
+*
+* On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
+* should be set when taking over after the firmware.
+*/
+ if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
+ sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
+ (HAS_PCH_CPT(i915) &&
+!(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
+ drm_info(>drm,
+"Display fused off, disabling\n");
+ goto display_fused_off;
+ } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
+ drm_info(>drm, "PipeC fused off\n");
+ display_runtime->pipe_mask &= ~BIT(PIPE_C);
+ display_runtime->cpu_transcoder_mask &=
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: limit lmem allocation size to succeed on SmallBars
== Series Details == Series: drm/i915/gt: limit lmem allocation size to succeed on SmallBars URL : https://patchwork.freedesktop.org/series/118711/ State : success == Summary == CI Bug Log - changes from CI_DRM_13217 -> Patchwork_118711v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118711v1/index.html Participating hosts (38 -> 38) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_118711v1 that come from known issues: ### CI changes ### Possible fixes * boot: - fi-kbl-8809g: [FAIL][1] ([i915#8293] / [i915#8298]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/fi-kbl-8809g/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118711v1/fi-kbl-8809g/boot.html ### IGT changes ### Issues hit * igt@core_hotunplug@unbind-rebind: - fi-kbl-8809g: NOTRUN -> [ABORT][3] ([i915#8298] / [i915#8299] / [i915#8397]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118711v1/fi-kbl-8809g/igt@core_hotunp...@unbind-rebind.html * igt@gem_exec_suspend@basic-s3@smem: - fi-kbl-x1275: [PASS][4] -> [ABORT][5] ([i915#8213]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/fi-kbl-x1275/igt@gem_exec_suspend@basic...@smem.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118711v1/fi-kbl-x1275/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118711v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-hsw-4770:[PASS][7] -> [SKIP][8] ([fdo#109271]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/fi-hsw-4770/igt@i915_pm_...@basic-pci-d3-state.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118711v1/fi-hsw-4770/igt@i915_pm_...@basic-pci-d3-state.html * igt@i915_pm_rpm@basic-rte: - fi-hsw-4770:[PASS][9] -> [FAIL][10] ([i915#7364]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/fi-hsw-4770/igt@i915_pm_...@basic-rte.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118711v1/fi-hsw-4770/igt@i915_pm_...@basic-rte.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: [PASS][11] -> [DMESG-FAIL][12] ([i915#5334] / [i915#7872]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118711v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@requests: - bat-rpls-2: [PASS][13] -> [ABORT][14] ([i915#4983] / [i915#7913]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-rpls-2/igt@i915_selftest@l...@requests.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118711v1/bat-rpls-2/igt@i915_selftest@l...@requests.html * igt@kms_addfb_basic@too-high: - fi-kbl-8809g: NOTRUN -> [FAIL][15] ([i915#8296]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118711v1/fi-kbl-8809g/igt@kms_addfb_ba...@too-high.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-dg2-11: NOTRUN -> [SKIP][16] ([i915#7828]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118711v1/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_force_connector_basic@force-connector-state: - fi-kbl-8809g: NOTRUN -> [DMESG-FAIL][17] ([i915#8299]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118711v1/fi-kbl-8809g/igt@kms_force_connector_ba...@force-connector-state.html * igt@kms_force_connector_basic@force-edid: - fi-kbl-8809g: NOTRUN -> [CRASH][18] ([i915#8299]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118711v1/fi-kbl-8809g/igt@kms_force_connector_ba...@force-edid.html * igt@kms_pipe_crc_basic@read-crc: - bat-adlp-9: NOTRUN -> [SKIP][19] ([i915#3546]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118711v1/bat-adlp-9/igt@kms_pipe_crc_ba...@read-crc.html * igt@kms_psr@cursor_plane_move: - fi-kbl-8809g: NOTRUN -> [SKIP][20] ([fdo#109271]) +59 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118711v1/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html * igt@kms_setmode@basic-clone-single-crtc: - fi-kbl-8809g: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4579]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118711v1/fi-kbl-8809g/igt@kms_setm...@basic-clone-single-crtc.html Possible fixes * igt@i915_selftest@live@reset: - bat-dg2-11:
Re: [Intel-gfx] [PATCH v5 3/7] drm/i915/huc: Load GSC-enabled HuC via DMA xfer if the fuse says so
On 5/31/2023 16:54, Daniele Ceraolo Spurio wrote:
In the previous patch we extracted the offset of the legacy-style HuC
binary located within the GSC-enabled blob, so now we can use that to
load the HuC via DMA if the fuse is set that way.
Note that we now need to differentiate between "GSC-enabled binary" and
"loaded by GSC", so the former case has been renamed to "has GSC headers"
for clarity, while the latter is now based on the fuse instead of the
binary format. This way, all the legacy load paths are automatically
taken (including the auth by GuC) without having to implement further
code changes.
v2: s/is_meu_binary/has_gsc_headers/, clearer logs (John)
v3: split check for GSC access, better comments (John)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 49 +--
drivers/gpu/drm/i915/gt/uc/intel_huc.h| 4 +-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 12 +++---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 2 +-
5 files changed, 47 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 6d795438b3e4..27c5e41fa84c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -298,31 +298,54 @@ void intel_huc_init_early(struct intel_huc *huc)
static int check_huc_loading_mode(struct intel_huc *huc)
{
struct intel_gt *gt = huc_to_gt(huc);
- bool fw_needs_gsc = intel_huc_is_loaded_by_gsc(huc);
- bool hw_uses_gsc = false;
+ bool gsc_enabled = huc->fw.has_gsc_headers;
/*
* The fuse for HuC load via GSC is only valid on platforms that have
* GuC deprivilege.
*/
if (HAS_GUC_DEPRIVILEGE(gt->i915))
- hw_uses_gsc = intel_uncore_read(gt->uncore, GUC_SHIM_CONTROL2) &
- GSC_LOADS_HUC;
+ huc->loaded_via_gsc = intel_uncore_read(gt->uncore,
GUC_SHIM_CONTROL2) &
+ GSC_LOADS_HUC;
- if (fw_needs_gsc != hw_uses_gsc) {
- huc_err(huc, "mismatch between FW (%s) and HW (%s) load
modes\n",
- HUC_LOAD_MODE_STRING(fw_needs_gsc),
HUC_LOAD_MODE_STRING(hw_uses_gsc));
+ if (huc->loaded_via_gsc && !gsc_enabled) {
+ huc_err(huc, "HW requires a GSC-enabled blob, but we found a legacy
one\n");
return -ENOEXEC;
}
- /* make sure we can access the GSC via the mei driver if we need it */
- if (!(IS_ENABLED(CONFIG_INTEL_MEI_PXP) && IS_ENABLED(CONFIG_INTEL_MEI_GSC))
&&
- fw_needs_gsc) {
- huc_info(huc, "can't load due to missing MEI modules\n");
- return -EIO;
+ /*
+* On newer platforms we have GSC-enabled binaries but we load the HuC
+* via DMA. To do so we need to find the location of the legacy-style
+* binary inside the GSC-enabled one, which we do at fetch time. Make
+* sure that we were able to do so if the fuse says we need to load via
+* DMA and the binary is GSC-enabled.
+*/
+ if (!huc->loaded_via_gsc && gsc_enabled && !huc->fw.dma_start_offset) {
+ huc_err(huc, "HW in DMA mode, but we have an incompatible
GSC-enabled blob\n");
+ return -ENOEXEC;
+ }
+
+ /*
+* If the HuC is loaded via GSC, we need to be able to access the GSC.
+* On DG2 this is done via the mei components, while on newer platforms
+* it is done via the GSCCS,
+*/
+ if (huc->loaded_via_gsc) {
+ if (IS_DG2(gt->i915)) {
+ if (!IS_ENABLED(CONFIG_INTEL_MEI_PXP) ||
+ !IS_ENABLED(CONFIG_INTEL_MEI_GSC)) {
+ huc_info(huc, "can't load due to missing mei
modules\n");
+ return -EIO;
+ }
+ } else {
+ if (!HAS_ENGINE(gt, GSC0)){
Checkpatch is complaining about lack of a space here. Maybe fix on merge
rather than repost if that is the only issue?
John.
Re: [Intel-gfx] [PATCH v5 4/7] drm/i915/huc: differentiate the 2 steps of the MTL HuC auth flow
On 5/31/2023 16:54, Daniele Ceraolo Spurio wrote:
Before we add the second step of the MTL HuC auth (via GSC), we need to
have the ability to differentiate between them. To do so, the huc
authentication check is duplicated for GuC and GSC auth, with
GSC-enabled binaries being considered fully authenticated only after
the GSC auth step.
To report the difference between the 2 auth steps, a new case is added
to the HuC getparam. This way, the clear media driver can start
submitting before full auth, as partial auth is enough for those
workloads.
v2: fix authentication status check for DG2
v3: add a better comment at the top of the HuC file to explain the
different approaches to load and auth (John)
v4: update call to intel_huc_is_authenticated in the pxp code to check
for GSC authentication
v5: drop references to meu and esclamation mark in huc_auth print (John)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
Reviewed-by: Alan Previn #v2
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 111 -
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 16 ++-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h| 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c | 2 +-
include/uapi/drm/i915_drm.h| 3 +-
6 files changed, 104 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 27c5e41fa84c..73efdb027082 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -10,6 +10,7 @@
#include "intel_huc.h"
#include "intel_huc_print.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include
#include
@@ -22,15 +23,23 @@
* capabilities by adding HuC specific commands to batch buffers.
*
* The kernel driver is only responsible for loading the HuC firmware and
- * triggering its security authentication, which is performed by the GuC on
- * older platforms and by the GSC on newer ones. For the GuC to correctly
- * perform the authentication, the HuC binary must be loaded before the GuC
one.
+ * triggering its security authentication. This is done differently depending
+ * on the platform:
+ * - older platforms (from Gen9 to most Gen12s): the load is performed via DMA
+ * and the authentication via GuC
+ * - DG2: load and authentication are both performed via GSC.
+ * - MTL and newer platforms: the load is performed via DMA (same as with
+ * not-DG2 older platforms), while the authentication is done in 2-steps,
+ * a first auth for clear-media workloads via GuC and a second one for all
+ * workloads via GSC.
+ * On platforms where the GuC does the authentication, to correctly do so the
+ * HuC binary must be loaded before the GuC one.
* Loading the HuC is optional; however, not using the HuC might negatively
* impact power usage and/or performance of media workloads, depending on the
* use-cases.
* HuC must be reloaded on events that cause the WOPCM to lose its contents
- * (S3/S4, FLR); GuC-authenticated HuC must also be reloaded on GuC/GT reset,
- * while GSC-managed HuC will survive that.
+ * (S3/S4, FLR); on older platforms the HuC must also be reloaded on GuC/GT
+ * reset, while on newer ones it will survive that.
*
* See https://github.com/intel/media-driver for the latest details on HuC
* functionality.
@@ -106,7 +115,7 @@ static enum hrtimer_restart
huc_delayed_load_timer_callback(struct hrtimer *hrti
{
struct intel_huc *huc = container_of(hrtimer, struct intel_huc,
delayed_load.timer);
- if (!intel_huc_is_authenticated(huc)) {
+ if (!intel_huc_is_authenticated(huc, INTEL_HUC_AUTH_BY_GSC)) {
if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_GSC)
huc_notice(huc, "timed out waiting for MEI GSC\n");
else if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_PXP)
@@ -124,7 +133,7 @@ static void huc_delayed_load_start(struct intel_huc *huc)
{
ktime_t delay;
- GEM_BUG_ON(intel_huc_is_authenticated(huc));
+ GEM_BUG_ON(intel_huc_is_authenticated(huc, INTEL_HUC_AUTH_BY_GSC));
/*
* On resume we don't have to wait for MEI-GSC to be re-probed, but we
@@ -284,13 +293,23 @@ void intel_huc_init_early(struct intel_huc *huc)
}
if (GRAPHICS_VER(i915) >= 11) {
- huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO;
- huc->status.mask = HUC_LOAD_SUCCESSFUL;
- huc->status.value = HUC_LOAD_SUCCESSFUL;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].reg =
GEN11_HUC_KERNEL_LOAD_INFO;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_LOAD_SUCCESSFUL;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_LOAD_SUCCESSFUL;
} else {
- huc->status.reg = HUC_STATUS2;
- huc->status.mask = HUC_FW_VERIFIED;
-
Re: [Intel-gfx] [PATCH v5 3/7] drm/i915/huc: Load GSC-enabled HuC via DMA xfer if the fuse says so
On 5/31/2023 16:54, Daniele Ceraolo Spurio wrote:
In the previous patch we extracted the offset of the legacy-style HuC
binary located within the GSC-enabled blob, so now we can use that to
load the HuC via DMA if the fuse is set that way.
Note that we now need to differentiate between "GSC-enabled binary" and
"loaded by GSC", so the former case has been renamed to "has GSC headers"
for clarity, while the latter is now based on the fuse instead of the
binary format. This way, all the legacy load paths are automatically
taken (including the auth by GuC) without having to implement further
code changes.
v2: s/is_meu_binary/has_gsc_headers/, clearer logs (John)
v3: split check for GSC access, better comments (John)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 49 +--
drivers/gpu/drm/i915/gt/uc/intel_huc.h| 4 +-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 12 +++---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 2 +-
5 files changed, 47 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 6d795438b3e4..27c5e41fa84c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -298,31 +298,54 @@ void intel_huc_init_early(struct intel_huc *huc)
static int check_huc_loading_mode(struct intel_huc *huc)
{
struct intel_gt *gt = huc_to_gt(huc);
- bool fw_needs_gsc = intel_huc_is_loaded_by_gsc(huc);
- bool hw_uses_gsc = false;
+ bool gsc_enabled = huc->fw.has_gsc_headers;
/*
* The fuse for HuC load via GSC is only valid on platforms that have
* GuC deprivilege.
*/
if (HAS_GUC_DEPRIVILEGE(gt->i915))
- hw_uses_gsc = intel_uncore_read(gt->uncore, GUC_SHIM_CONTROL2) &
- GSC_LOADS_HUC;
+ huc->loaded_via_gsc = intel_uncore_read(gt->uncore,
GUC_SHIM_CONTROL2) &
+ GSC_LOADS_HUC;
- if (fw_needs_gsc != hw_uses_gsc) {
- huc_err(huc, "mismatch between FW (%s) and HW (%s) load
modes\n",
- HUC_LOAD_MODE_STRING(fw_needs_gsc),
HUC_LOAD_MODE_STRING(hw_uses_gsc));
+ if (huc->loaded_via_gsc && !gsc_enabled) {
+ huc_err(huc, "HW requires a GSC-enabled blob, but we found a legacy
one\n");
return -ENOEXEC;
}
- /* make sure we can access the GSC via the mei driver if we need it */
- if (!(IS_ENABLED(CONFIG_INTEL_MEI_PXP) && IS_ENABLED(CONFIG_INTEL_MEI_GSC))
&&
- fw_needs_gsc) {
- huc_info(huc, "can't load due to missing MEI modules\n");
- return -EIO;
+ /*
+* On newer platforms we have GSC-enabled binaries but we load the HuC
+* via DMA. To do so we need to find the location of the legacy-style
+* binary inside the GSC-enabled one, which we do at fetch time. Make
+* sure that we were able to do so if the fuse says we need to load via
+* DMA and the binary is GSC-enabled.
+*/
+ if (!huc->loaded_via_gsc && gsc_enabled && !huc->fw.dma_start_offset) {
+ huc_err(huc, "HW in DMA mode, but we have an incompatible
GSC-enabled blob\n");
+ return -ENOEXEC;
+ }
+
+ /*
+* If the HuC is loaded via GSC, we need to be able to access the GSC.
+* On DG2 this is done via the mei components, while on newer platforms
+* it is done via the GSCCS,
+*/
+ if (huc->loaded_via_gsc) {
+ if (IS_DG2(gt->i915)) {
+ if (!IS_ENABLED(CONFIG_INTEL_MEI_PXP) ||
+ !IS_ENABLED(CONFIG_INTEL_MEI_GSC)) {
+ huc_info(huc, "can't load due to missing mei
modules\n");
+ return -EIO;
+ }
+ } else {
+ if (!HAS_ENGINE(gt, GSC0)){
+ huc_info(huc, "can't load due to missing
GSCCS\n");
+ return -EIO;
+ }
+ }
}
- huc_dbg(huc, "loaded by GSC = %s\n", str_yes_no(fw_needs_gsc));
+ huc_dbg(huc, "loaded by GSC = %s\n", str_yes_no(huc->loaded_via_gsc));
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index 0789184d81a2..112f0dce4702 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -39,6 +39,8 @@ struct intel_huc {
struct notifier_block nb;
enum intel_huc_delayed_load_status status;
} delayed_load;
+
+ bool loaded_via_gsc;
};
int intel_huc_sanitize(struct intel_huc *huc);
@@ -73,7 +75,7 @@ static
Re: [Intel-gfx] [PATCH v5 2/7] drm/i915/huc: Parse the GSC-enabled HuC binary
On 5/31/2023 16:54, Daniele Ceraolo Spurio wrote:
The new binaries that support the 2-step authentication contain the
legacy-style binary, which we can use for loading the HuC via DMA. To
find out where this is located in the image, we need to parse the
manifest of the GSC-enabled HuC binary. The manifest consist of a
partition header followed by entries, one of which contains the offset
we're looking for.
Note that the DG2 GSC binary contains entries with the same names, but
it doesn't contain a full legacy binary, so we need to skip assigning
the dma offset in that case (which we can do by checking the ccs).
Also, since we're now parsing the entries, we can extract the HuC
version that way instead of using hardcoded offsets.
Note that the GSC binary uses the same structures in its binary header,
so they've been added in their own header file.
v2: fix structure names to match meu defines (s/CPT/CPD/), update commit
message, check ccs validity, drop old version location defines.
v3: drop references to the MEU tool to reduce confusion, fix log (John)
v4: fix log for real (John)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
Reviewed-by: Alan Previn #v2
Reviewed-by: John Harrison
---
.../drm/i915/gt/uc/intel_gsc_binary_headers.h | 74 ++
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 11 +-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 136 ++
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h | 5 +-
drivers/gpu/drm/i915/gt/uc/intel_huc_print.h | 21 +++
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 72 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 2 +
drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 6 -
8 files changed, 274 insertions(+), 53 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_binary_headers.h
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_huc_print.h
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_binary_headers.h
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_binary_headers.h
new file mode 100644
index ..714f0c256118
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_binary_headers.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _INTEL_GSC_BINARY_HEADERS_H_
+#define _INTEL_GSC_BINARY_HEADERS_H_
+
+#include
+
+/* Code partition directory (CPD) structures */
+struct intel_gsc_cpd_header_v2 {
+ u32 header_marker;
+#define INTEL_GSC_CPD_HEADER_MARKER 0x44504324
+
+ u32 num_of_entries;
+ u8 header_version;
+ u8 entry_version;
+ u8 header_length; /* in bytes */
+ u8 flags;
+ u32 partition_name;
+ u32 crc32;
+} __packed;
+
+struct intel_gsc_cpd_entry {
+ u8 name[12];
+
+ /*
+* Bits 0-24: offset from the beginning of the code partition
+* Bit 25: huffman compressed
+* Bits 26-31: reserved
+*/
+ u32 offset;
+#define INTEL_GSC_CPD_ENTRY_OFFSET_MASK GENMASK(24, 0)
+#define INTEL_GSC_CPD_ENTRY_HUFFMAN_COMP BIT(25)
+
+ /*
+* Module/Item length, in bytes. For Huffman-compressed modules, this
+* refers to the uncompressed size. For software-compressed modules,
+* this refers to the compressed size.
+*/
+ u32 length;
+
+ u8 reserved[4];
+} __packed;
+
+struct intel_gsc_version {
+ u16 major;
+ u16 minor;
+ u16 hotfix;
+ u16 build;
+} __packed;
+
+struct intel_gsc_manifest_header {
+ u32 header_type; /* 0x4 for manifest type */
+ u32 header_length; /* in dwords */
+ u32 header_version;
+ u32 flags;
+ u32 vendor;
+ u32 date;
+ u32 size; /* In dwords, size of entire manifest (header + extensions) */
+ u32 header_id;
+ u32 internal_data;
+ struct intel_gsc_version fw_version;
+ u32 security_version;
+ struct intel_gsc_version meu_kit_version;
+ u32 meu_manifest_version;
+ u8 general_data[4];
+ u8 reserved3[56];
+ u32 modulus_size; /* in dwords */
+ u32 exponent_size; /* in dwords */
+} __packed;
+
+#endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 268e036f8f28..6d795438b3e4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -6,23 +6,14 @@
#include
#include "gt/intel_gt.h"
-#include "gt/intel_gt_print.h"
#include "intel_guc_reg.h"
#include "intel_huc.h"
+#include "intel_huc_print.h"
#include "i915_drv.h"
#include
#include
-#define huc_printk(_huc, _level, _fmt, ...) \
- gt_##_level(huc_to_gt(_huc), "HuC: " _fmt, ##__VA_ARGS__)
-#define huc_err(_huc, _fmt, ...) huc_printk((_huc), err, _fmt,
##__VA_ARGS__)
-#define huc_warn(_huc, _fmt, ...) huc_printk((_huc), warn, _fmt,
##__VA_ARGS__)
-#define huc_notice(_huc, _fmt, ...)huc_printk((_huc), notice, _fmt,
##__VA_ARGS__)
-#define
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: No 10bit gamma on desktop gen3 parts (rev2)
== Series Details ==
Series: drm/i915: No 10bit gamma on desktop gen3 parts (rev2)
URL : https://patchwork.freedesktop.org/series/118651/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13217 -> Patchwork_118651v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118651v2/index.html
Participating hosts (38 -> 38)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_118651v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@execlists:
- fi-kbl-soraka: [PASS][1] -> [INCOMPLETE][2] ([i915#7156] /
[i915#7913])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118651v2/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@reset:
- bat-rpls-1: [PASS][3] -> [ABORT][4] ([i915#4983] / [i915#7461] /
[i915#7981] / [i915#8347] / [i915#8384])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-rpls-1/igt@i915_selftest@l...@reset.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118651v2/bat-rpls-1/igt@i915_selftest@l...@reset.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][5] ([i915#7828])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118651v2/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-adlp-9: NOTRUN -> [SKIP][6] ([i915#3546]) +1 similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118651v2/bat-adlp-9/igt@kms_pipe_crc_ba...@read-crc.html
- bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#1845] / [i915#5354]) +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118651v2/bat-dg2-11/igt@kms_pipe_crc_ba...@read-crc.html
Possible fixes
* igt@i915_selftest@live@gt_mocs:
- {bat-mtlp-8}: [DMESG-FAIL][8] ([i915#7059]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118651v2/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@reset:
- bat-dg2-11: [INCOMPLETE][10] ([i915#7913]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-dg2-11/igt@i915_selftest@l...@reset.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118651v2/bat-dg2-11/igt@i915_selftest@l...@reset.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: [DMESG-WARN][12] ([i915#6367]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-rpls-2/igt@i915_selftest@l...@slpc.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118651v2/bat-rpls-2/igt@i915_selftest@l...@slpc.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1:
- bat-dg2-8: [FAIL][14] ([i915#7932]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118651v2/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7156]: https://gitlab.freedesktop.org/drm/intel/issues/7156
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
[i915#8384]: https://gitlab.freedesktop.org/drm/intel/issues/8384
Build changes
-
* Linux: CI_DRM_13217 -> Patchwork_118651v2
CI-20190529: 20190529
CI_DRM_13217: 37b9b6d05f2421323eb83d005d8863f59855b003 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7317: c902b72df45aa49faa38205bc5be3c748d33a3e0 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_118651v2: 37b9b6d05f2421323eb83d005d8863f59855b003 @
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] tests/i915/gem_ctx_persistence: Skip some subtests
On 24.05.2023 21:19, Vinay Belgaumkar wrote:
Hang and heartbeat subtests are not supported with GuC submission
enabled.
Signed-off-by: Vinay Belgaumkar
---
tests/i915/gem_ctx_persistence.c | 32 +++-
1 file changed, 19 insertions(+), 13 deletions(-)
diff --git a/tests/i915/gem_ctx_persistence.c b/tests/i915/gem_ctx_persistence.c
index 42cf96329..1e122535e 100644
--- a/tests/i915/gem_ctx_persistence.c
+++ b/tests/i915/gem_ctx_persistence.c
@@ -1366,19 +1366,25 @@ igt_main
igt_subtest("hostile")
test_nohangcheck_hostile(i915, _cfg);
- igt_subtest("hang")
- test_nohangcheck_hang(i915, _cfg);
-
- igt_subtest("heartbeat-stop")
- test_noheartbeat_many(i915, 1, 0);
- igt_subtest("heartbeat-hang")
- test_noheartbeat_many(i915, 1, IGT_SPIN_NO_PREEMPTION);
- igt_subtest("heartbeat-many")
- test_noheartbeat_many(i915, 16, 0);
- igt_subtest("heartbeat-close")
- test_noheartbeat_close(i915, 0);
- igt_subtest("heartbeat-hostile")
- test_noheartbeat_close(i915, IGT_SPIN_NO_PREEMPTION);
+
+ igt_subtest_group {
+ igt_fixture
+ igt_skip_on(gem_using_guc_submission(i915));
As Kamil said this should be put into test function.
Otherwise you will have misleading errors in other tests - fixture will
be called always regardless of running test.
+
+ igt_subtest("hang")
+ test_nohangcheck_hang(i915, _cfg);
What is 'missing' in GuC in case of this test? CI is happy :)
+
+ igt_subtest("heartbeat-stop")
+ test_noheartbeat_many(i915, 1, 0);
+ igt_subtest("heartbeat-hang")
+ test_noheartbeat_many(i915, 1, IGT_SPIN_NO_PREEMPTION);
+ igt_subtest("heartbeat-many")
+ test_noheartbeat_many(i915, 16, 0);
+ igt_subtest("heartbeat-close")
+ test_noheartbeat_close(i915, 0);
+ igt_subtest("heartbeat-hostile")
+ test_noheartbeat_close(i915, IGT_SPIN_NO_PREEMPTION);
These tests are handled already by recently merged:
https://patchwork.freedesktop.org/patch/539647/?series=118423=3
Regards
Andrzej
+ }
igt_subtest_group {
igt_fixture
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Add workaround 14016712196 (rev5)
== Series Details ==
Series: drm/i915/gt: Add workaround 14016712196 (rev5)
URL : https://patchwork.freedesktop.org/series/117661/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13217 -> Patchwork_117661v5
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v5/index.html
Participating hosts (38 -> 38)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_117661v5 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-hsw-4770:[PASS][1] -> [SKIP][2] ([fdo#109271])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/fi-hsw-4770/igt@i915_pm_...@basic-pci-d3-state.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v5/fi-hsw-4770/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- fi-hsw-4770:[PASS][3] -> [FAIL][4] ([i915#7364])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/fi-hsw-4770/igt@i915_pm_...@basic-rte.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v5/fi-hsw-4770/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [PASS][5] -> [DMESG-FAIL][6] ([i915#5334] /
[i915#7872])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v5/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_lrc:
- bat-adlp-9: [PASS][7] -> [INCOMPLETE][8] ([i915#4983] /
[i915#7913])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-adlp-9/igt@i915_selftest@live@gt_lrc.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v5/bat-adlp-9/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@hangcheck:
- bat-dg2-9: [PASS][9] -> [DMESG-FAIL][10] ([i915#6998] /
[i915#7913])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-dg2-9/igt@i915_selftest@l...@hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v5/bat-dg2-9/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@migrate:
- bat-dg2-11: [PASS][11] -> [DMESG-WARN][12] ([i915#7699])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-dg2-11/igt@i915_selftest@l...@migrate.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v5/bat-dg2-11/igt@i915_selftest@l...@migrate.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][13] ([i915#7828])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v5/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-adlp-9: NOTRUN -> [SKIP][14] ([i915#3546]) +1 similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v5/bat-adlp-9/igt@kms_pipe_crc_ba...@read-crc.html
- bat-dg2-11: NOTRUN -> [SKIP][15] ([i915#1845] / [i915#5354]) +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v5/bat-dg2-11/igt@kms_pipe_crc_ba...@read-crc.html
Possible fixes
* igt@i915_module_load@load:
- {bat-adlp-11}: [ABORT][16] ([i915#4423]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-adlp-11/igt@i915_module_l...@load.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v5/bat-adlp-11/igt@i915_module_l...@load.html
* igt@i915_selftest@live@gt_mocs:
- {bat-mtlp-8}: [DMESG-FAIL][18] ([i915#7059]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v5/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@gt_pm:
- bat-rpls-2: [DMESG-FAIL][20] ([i915#4258] / [i915#7913]) ->
[PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v5/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@reset:
- bat-dg2-11: [INCOMPLETE][22] ([i915#7913]) -> [PASS][23]
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-dg2-11/igt@i915_selftest@l...@reset.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v5/bat-dg2-11/igt@i915_selftest@l...@reset.html
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [DMESG-WARN][24] ([i915#6367]) -> [PASS][25]
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-rpls-1/igt@i915_selftest@l...@slpc.html
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Print usefull information on error (rev2)
== Series Details ==
Series: drm/i915/display: Print usefull information on error (rev2)
URL : https://patchwork.freedesktop.org/series/118685/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13217 -> Patchwork_118685v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v2/index.html
Participating hosts (38 -> 38)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_118685v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][1] ([i915#7828])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v2/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-dg2-11: NOTRUN -> [SKIP][2] ([i915#1845] / [i915#5354]) +1
similar issue
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v2/bat-dg2-11/igt@kms_pipe_crc_ba...@read-crc.html
Possible fixes
* igt@i915_selftest@live@gt_mocs:
- {bat-mtlp-8}: [DMESG-FAIL][3] ([i915#7059]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v2/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@gt_pm:
- bat-rpls-2: [DMESG-FAIL][5] ([i915#4258] / [i915#7913]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v2/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@reset:
- bat-dg2-11: [INCOMPLETE][7] ([i915#7913]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-dg2-11/igt@i915_selftest@l...@reset.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v2/bat-dg2-11/igt@i915_selftest@l...@reset.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1:
- bat-dg2-8: [FAIL][9] ([i915#7932]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v2/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html
Warnings
* igt@kms_psr@primary_mmap_gtt:
- bat-rplp-1: [SKIP][11] ([i915#1072]) -> [ABORT][12] ([i915#8442])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v2/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
[i915#8497]: https://gitlab.freedesktop.org/drm/intel/issues/8497
Build changes
-
* Linux: CI_DRM_13217 -> Patchwork_118685v2
CI-20190529: 20190529
CI_DRM_13217: 37b9b6d05f2421323eb83d005d8863f59855b003 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7317: c902b72df45aa49faa38205bc5be3c748d33a3e0 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_118685v2: 37b9b6d05f2421323eb83d005d8863f59855b003 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
ffd3c07352cc drm/i915/display: Print useful information on error
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v2/index.html
Re: [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
On Thu, Jun 01, 2023 at 11:22:18AM -0700, Dixit, Ashutosh wrote:
On Wed, 31 May 2023 14:35:47 -0700, Matt Atwood wrote:
Hi Matt,
Set I915_PMU_MAX_GTS to value in I915_MAX_GT, theres no reason for these
values to be different.
Cc: Tvrtko Ursulin
Cc: Umesh Nerlige Ramappa
Cc: Ashutosh Dixit
I don't believe the mailer actually Cc'd us. I just saw this and am Cc'ing
the people who authored/reviewed the previous series now.
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/i915_pmu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index 33d80fbaab8b..aa929d8c224a 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -38,7 +38,7 @@ enum {
__I915_NUM_PMU_SAMPLERS
};
-#define I915_PMU_MAX_GTS 2
+#define I915_PMU_MAX_GTS 4
This was a discussed during the previous review and it was decided to keep
the two values (I915_PMU_MAX_GTS and I915_MAX_GT) different. There are
currently no platforms and there will be no i915 supported platforms with
MAX_GT 4. So I prefer to leave the values as they currently are. Unless
Umesh or Tvrtko agrees to this patch.
I would leave it as 2 since we specifically changed it to 2 (was 4
earlier) during review of the PMU multi tile support patches.
Thanks,
Umesh
Thanks.
--
Ashutosh
/*
* How many different events we track in the global PMU mask.
--
2.40.0
Re: [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
On Thu, 01 Jun 2023 11:22:18 -0700, Dixit, Ashutosh wrote:
>
> On Wed, 31 May 2023 14:35:47 -0700, Matt Atwood wrote:
> >
>
> Hi Matt,
>
> > Set I915_PMU_MAX_GTS to value in I915_MAX_GT, theres no reason for these
> > values to be different.
Also, we can't be so sure so as to be able to say "theres no reason for
these values to be different" till we have actually verified it. E.g. there
are various bitfields in the code which might not fit in a u32 if we
increase MAX_GT from 2 to 4. Has this been verified?
If anything, to keep the code from doing unnecessary stuff, IMO I915_MAX_GT
should be reduced to 2 and should be increased to 4 only once/if we have
i915 supported platforms with 4 GT's.
Thanks.
--
Ashutosh
> >
> > Cc: Tvrtko Ursulin
> > Cc: Umesh Nerlige Ramappa
> > Cc: Ashutosh Dixit
>
> I don't believe the mailer actually Cc'd us. I just saw this and am Cc'ing
> the people who authored/reviewed the previous series now.
>
> > Signed-off-by: Matt Atwood
> > ---
> > drivers/gpu/drm/i915/i915_pmu.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_pmu.h
> > b/drivers/gpu/drm/i915/i915_pmu.h
> > index 33d80fbaab8b..aa929d8c224a 100644
> > --- a/drivers/gpu/drm/i915/i915_pmu.h
> > +++ b/drivers/gpu/drm/i915/i915_pmu.h
> > @@ -38,7 +38,7 @@ enum {
> > __I915_NUM_PMU_SAMPLERS
> > };
> >
> > -#define I915_PMU_MAX_GTS 2
> > +#define I915_PMU_MAX_GTS 4
>
> This was a discussed during the previous review and it was decided to keep
> the two values (I915_PMU_MAX_GTS and I915_MAX_GT) different. There are
> currently no platforms and there will be no i915 supported platforms with
> MAX_GT 4. So I prefer to leave the values as they currently are. Unless
> Umesh or Tvrtko agrees to this patch.
>
> Thanks.
> --
> Ashutosh
>
> >
> > /*
> > * How many different events we track in the global PMU mask.
> > --
> > 2.40.0
> >
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Reset only one lane in case of MFD (rev2)
== Series Details ==
Series: drm/i915/mtl: Reset only one lane in case of MFD (rev2)
URL : https://patchwork.freedesktop.org/series/118308/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13217 -> Patchwork_118308v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v2/index.html
Participating hosts (38 -> 38)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_118308v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-hsw-4770:[PASS][1] -> [SKIP][2] ([fdo#109271])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/fi-hsw-4770/igt@i915_pm_...@basic-pci-d3-state.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v2/fi-hsw-4770/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- fi-hsw-4770:[PASS][3] -> [FAIL][4] ([i915#7364])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/fi-hsw-4770/igt@i915_pm_...@basic-rte.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v2/fi-hsw-4770/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [PASS][5] -> [DMESG-FAIL][6] ([i915#5334] /
[i915#7872])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v2/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@mman:
- bat-rpls-2: [PASS][7] -> [TIMEOUT][8] ([i915#6794] / [i915#7392])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-rpls-2/igt@i915_selftest@l...@mman.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v2/bat-rpls-2/igt@i915_selftest@l...@mman.html
* igt@i915_selftest@live@reset:
- bat-rpls-1: [PASS][9] -> [ABORT][10] ([i915#4983] / [i915#7461] /
[i915#8347] / [i915#8384])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-rpls-1/igt@i915_selftest@l...@reset.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v2/bat-rpls-1/igt@i915_selftest@l...@reset.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#7828])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v2/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html
Possible fixes
* igt@i915_selftest@live@gt_mocs:
- {bat-mtlp-8}: [DMESG-FAIL][12] ([i915#7059]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v2/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@reset:
- bat-dg2-11: [INCOMPLETE][14] ([i915#7913]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-dg2-11/igt@i915_selftest@l...@reset.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v2/bat-dg2-11/igt@i915_selftest@l...@reset.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1:
- bat-dg2-8: [FAIL][16] ([i915#7932]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v2/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html
Warnings
* igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: [SKIP][18] ([i915#3555] / [i915#4579]) -> [ABORT][19]
([i915#4579] / [i915#8260])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13217/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v2/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6763]: https://gitlab.freedesktop.org/drm/intel/issues/6763
[i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7364]: https://gitlab.freedesktop.org/drm/intel/issues/7364
Re: [Intel-gfx] [PATCH i-g-t] tests/i915/gem_ctx_persistence: Skip some subtests
On 5/25/2023 11:25 AM, Kamil Konieczny wrote:
Hi Vinay,
On 2023-05-24 at 12:19:06 -0700, Vinay Belgaumkar wrote:
Hang and heartbeat subtests are not supported with GuC submission
enabled.
Signed-off-by: Vinay Belgaumkar
---
tests/i915/gem_ctx_persistence.c | 32 +++-
1 file changed, 19 insertions(+), 13 deletions(-)
diff --git a/tests/i915/gem_ctx_persistence.c b/tests/i915/gem_ctx_persistence.c
index 42cf96329..1e122535e 100644
--- a/tests/i915/gem_ctx_persistence.c
+++ b/tests/i915/gem_ctx_persistence.c
@@ -1366,19 +1366,25 @@ igt_main
igt_subtest("hostile")
test_nohangcheck_hostile(i915, _cfg);
- igt_subtest("hang")
- test_nohangcheck_hang(i915, _cfg);
-
- igt_subtest("heartbeat-stop")
- test_noheartbeat_many(i915, 1, 0);
- igt_subtest("heartbeat-hang")
- test_noheartbeat_many(i915, 1, IGT_SPIN_NO_PREEMPTION);
- igt_subtest("heartbeat-many")
- test_noheartbeat_many(i915, 16, 0);
- igt_subtest("heartbeat-close")
- test_noheartbeat_close(i915, 0);
- igt_subtest("heartbeat-hostile")
- test_noheartbeat_close(i915, IGT_SPIN_NO_PREEMPTION);
+
+ igt_subtest_group {
+ igt_fixture
+ igt_skip_on(gem_using_guc_submission(i915));
--- ^^^
You cannot put this in fixture as there is no test defined in it.
Place skips at begin of test functions that need it.
Hi Kamil,
That's why I created a subtest_group. Is that not sufficient?
Thanks,
Vinay.
Regards,
Kamil
+
+ igt_subtest("hang")
+ test_nohangcheck_hang(i915, _cfg);
+
+ igt_subtest("heartbeat-stop")
+ test_noheartbeat_many(i915, 1, 0);
+ igt_subtest("heartbeat-hang")
+ test_noheartbeat_many(i915, 1, IGT_SPIN_NO_PREEMPTION);
+ igt_subtest("heartbeat-many")
+ test_noheartbeat_many(i915, 16, 0);
+ igt_subtest("heartbeat-close")
+ test_noheartbeat_close(i915, 0);
+ igt_subtest("heartbeat-hostile")
+ test_noheartbeat_close(i915, IGT_SPIN_NO_PREEMPTION);
+ }
igt_subtest_group {
igt_fixture
--
2.38.1
Re: [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
On Wed, 31 May 2023 14:35:47 -0700, Matt Atwood wrote:
>
Hi Matt,
> Set I915_PMU_MAX_GTS to value in I915_MAX_GT, theres no reason for these
> values to be different.
>
> Cc: Tvrtko Ursulin
> Cc: Umesh Nerlige Ramappa
> Cc: Ashutosh Dixit
I don't believe the mailer actually Cc'd us. I just saw this and am Cc'ing
the people who authored/reviewed the previous series now.
> Signed-off-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/i915_pmu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
> index 33d80fbaab8b..aa929d8c224a 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.h
> +++ b/drivers/gpu/drm/i915/i915_pmu.h
> @@ -38,7 +38,7 @@ enum {
> __I915_NUM_PMU_SAMPLERS
> };
>
> -#define I915_PMU_MAX_GTS 2
> +#define I915_PMU_MAX_GTS 4
This was a discussed during the previous review and it was decided to keep
the two values (I915_PMU_MAX_GTS and I915_MAX_GT) different. There are
currently no platforms and there will be no i915 supported platforms with
MAX_GT 4. So I prefer to leave the values as they currently are. Unless
Umesh or Tvrtko agrees to this patch.
Thanks.
--
Ashutosh
>
> /*
> * How many different events we track in the global PMU mask.
> --
> 2.40.0
>
Re: [Intel-gfx] [PATCH 3/3] i915/perf: Drop the aged_tail from rewind logic
On Wed, May 31, 2023 at 09:13:02PM -0700, Dixit, Ashutosh wrote:
On Wed, 31 May 2023 16:56:34 -0700, Umesh Nerlige Ramappa wrote:
Hi Umesh,
Instead of aged_tail use an iterator that starts from the hw_tail and
goes backward until the oa_buffer.tail looking for valid reports.
Hmm I don't think this description is correct. All this patch is doing is
the following:
a. s/aged_tail/tail/
b. s/tail/iter/
So basically I don't think we need this patch. All we want to do here is
change the variable name aged_tail to something else (to completely remove
the concept of aging from the OA code) but other changes such as name
change to iter etc. is unnecessary.
So I would just keep the patch simple and change the name aged_tail to
advertized_tail or exported_tail or read_tail, because basically
stream->oa_buffer.tail is the tail which the writer updates (or advertizes
or exports) for the reader.
So we only should rename aged_tail here, the other changes are not needed.
We could even squash this change into Patch 1 or Patch 2, since it is
really a trivial variable rename.
The whole point was just readability. head/tail point to what the user
consumes. hw_tail points to the actual hw register value and iter is
just loop iterator.
Since the intent of the series is to just get rid of aging/aged logic, I
can just s/aged_tail/read_tail/ and squash it with 1 since it belongs
more to 1 than 2, although, I still like the my current patch (maybe
with additional description in the commit message to clarify that the
patch is just renames for readability).
Will post next rev with the simple rename and squash.
Thanks,
Umesh
Thanks.
--
Ashutosh
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index beb1269422ca..39f5ab1911c8 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -543,7 +543,7 @@ static bool oa_buffer_check_unlocked(struct
i915_perf_stream *stream)
{
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
int report_size = stream->oa_buffer.format->size;
- u32 head, tail, aged_tail;
+ u32 head, tail, iter;
unsigned long flags;
bool pollin;
u32 hw_tail;
@@ -567,15 +567,14 @@ static bool oa_buffer_check_unlocked(struct
i915_perf_stream *stream)
/* Subtract partial amount off the tail */
hw_tail = OA_TAKEN(hw_tail, partial_report_size);
-
/* NB: The head we observe here might effectively be a little
* out of date. If a read() is in progress, the head could be
* anywhere between this head and stream->oa_buffer.tail.
*/
head = stream->oa_buffer.head - gtt_offset;
- aged_tail = stream->oa_buffer.tail - gtt_offset;
+ tail = stream->oa_buffer.tail - gtt_offset;
- tail = hw_tail;
+ iter = hw_tail;
/* Walk the stream backward until we find a report with report
* id and timestmap not at 0. Since the circular buffer pointers
@@ -588,23 +587,23 @@ static bool oa_buffer_check_unlocked(struct
i915_perf_stream *stream)
* memory in the order they were written to.
* If not : (╯°□°）╯︵ ┻━┻
*/
- while (OA_TAKEN(tail, aged_tail) >= report_size) {
- void *report = stream->oa_buffer.vaddr + tail;
+ while (OA_TAKEN(iter, tail) >= report_size) {
+ void *report = stream->oa_buffer.vaddr + iter;
if (oa_report_id(stream, report) ||
oa_timestamp(stream, report))
break;
- tail = (tail - report_size) & (OA_BUFFER_SIZE - 1);
+ iter = (iter - report_size) & (OA_BUFFER_SIZE - 1);
}
- if (OA_TAKEN(hw_tail, tail) > report_size &&
+ if (OA_TAKEN(hw_tail, iter) > report_size &&
__ratelimit(>perf->tail_pointer_race))
drm_notice(>uncore->i915->drm,
"unlanded report(s) head=0x%x tail=0x%x
hw_tail=0x%x\n",
head, tail, hw_tail);
- stream->oa_buffer.tail = gtt_offset + tail;
+ stream->oa_buffer.tail = gtt_offset + iter;
pollin = OA_TAKEN(stream->oa_buffer.tail - gtt_offset,
stream->oa_buffer.head - gtt_offset) >= report_size;
--
2.36.1
Re: [Intel-gfx] [PATCH] drm/i915: Fix error handling if driver creation fails during probe
Quoting Matt Roper (2023-06-01 14:38:04-03:00)
>If i915_driver_create() fails to create a valid 'i915' object, we
>should just disable the PCI device and return immediately without trying
>to call i915_probe_error() that relies on a valid i915 pointer.
>
>Fixes: 12e6f6dc78e4 ("drm/i915/display: Handle GMD_ID identification in
>display code")
>Reported-by: Dan Carpenter
>Signed-off-by: Matt Roper
Reviewed-by: Gustavo Sousa
>---
> drivers/gpu/drm/i915/i915_driver.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_driver.c
>b/drivers/gpu/drm/i915/i915_driver.c
>index c3ab5c32d492..5c3fc57cc4fe 100644
>--- a/drivers/gpu/drm/i915/i915_driver.c
>+++ b/drivers/gpu/drm/i915/i915_driver.c
>@@ -762,8 +762,8 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
>pci_device_id *ent)
>
> i915 = i915_driver_create(pdev, ent);
> if (IS_ERR(i915)) {
>-ret = PTR_ERR(i915);
>-goto out_pci_disable;
>+pci_disable_device(pdev);
>+return PTR_ERR(i915);
> }
>
> ret = i915_driver_early_probe(i915);
>--
>2.40.1
>
[Intel-gfx] [PATCH] drm/i915/pxp: Optimize GET_PARAM:PXP_STATUS
After recent discussions with Mesa folks, it was requested
that we optimize i915's GET_PARAM for the PXP_STATUS without
changing the UAPI spec.
This patch adds this additional optimizations:
- If any PXP initializatoin flow failed, then ensure that
we catch it so that we can change the returned PXP_STATUS
from "2" (i.e. 'PXP is supported but not yet ready')
to "-ENODEV". This typically should not happen and if it
does, we have a platform configuration.
- If a PXP arbitration session creation event failed
due to incorrect firmware version or blocking SOC fusing
or blocking BIOS configuration (platform reasons that won't
change if we retry), then reflect that blockage by also
returning -ENODEV in the GET_PARAM-PXP_STATUS.
- GET_PARAM:PXP_STATUS should not wait at all if PXP is
supported but non-i915 dependencies (component-driver /
firmware) we are still pending to complete the init flows.
In this case, just return "2" immediately (i.e. 'PXP is
supported but not yet ready').
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c | 11 +-
drivers/gpu/drm/i915/i915_getparam.c | 2 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 25 ++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 2 +-
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c | 7 +++---
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 7 +++---
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 9
7 files changed, 50 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
index fb0984f875f9..4dd744c96a37 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
@@ -42,8 +42,17 @@ static void gsc_work(struct work_struct *work)
}
ret = intel_gsc_proxy_request_handler(gsc);
- if (ret)
+ if (ret) {
+ if (actions & GSC_ACTION_FW_LOAD) {
+ /*
+* a proxy request failure that came together
with the
+* firmware load action means the last part of
init has
+* failed so GSC fw won't be usable after this
+*/
+ intel_uc_fw_change_status(>fw,
INTEL_UC_FIRMWARE_LOAD_FAIL);
+ }
goto out_put;
+ }
/* mark the GSC FW init as done the first time we run this */
if (actions & GSC_ACTION_FW_LOAD) {
diff --git a/drivers/gpu/drm/i915/i915_getparam.c
b/drivers/gpu/drm/i915/i915_getparam.c
index 6f11d7eaa91a..1b2ee98a158a 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -105,7 +105,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
return value;
break;
case I915_PARAM_PXP_STATUS:
- value = intel_pxp_get_readiness_status(i915->pxp);
+ value = intel_pxp_get_readiness_status(i915->pxp, 1);
if (value < 0)
return value;
break;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index bb2e15329f34..1478bb9b4e26 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -359,21 +359,38 @@ void intel_pxp_end(struct intel_pxp *pxp)
intel_runtime_pm_put(>runtime_pm, wakeref);
}
+static bool pxp_required_fw_failed(struct intel_pxp *pxp)
+{
+ if (__intel_uc_fw_status(>ctrl_gt->uc.huc.fw) ==
INTEL_UC_FIRMWARE_LOAD_FAIL)
+ return true;
+ if (HAS_ENGINE(pxp->ctrl_gt, GSC0) &&
+ __intel_uc_fw_status(>ctrl_gt->uc.gsc.fw) ==
INTEL_UC_FIRMWARE_LOAD_FAIL)
+ return true;
+
+ return false;
+}
+
/*
* this helper is used by both intel_pxp_start and by
* the GET_PARAM IOCTL that user space calls. Thus, the
* return values here should match the UAPI spec.
*/
-int intel_pxp_get_readiness_status(struct intel_pxp *pxp)
+int intel_pxp_get_readiness_status(struct intel_pxp *pxp, int timeout)
{
if (!intel_pxp_is_enabled(pxp))
return -ENODEV;
+ if (pxp_required_fw_failed(pxp))
+ return -ENODEV;
+
+ if (pxp->platform_cfg_is_bad)
+ return -ENODEV;
+
if (HAS_ENGINE(pxp->ctrl_gt, GSC0)) {
- if (wait_for(intel_pxp_gsccs_is_ready_for_sessions(pxp), 250))
+ if (wait_for(intel_pxp_gsccs_is_ready_for_sessions(pxp),
timeout))
return 2;
} else {
- if (wait_for(pxp_component_bound(pxp), 250))
+ if (wait_for(pxp_component_bound(pxp), timeout))
return 2;
}
return 1;
@@ -387,7 +404,7
Re: [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
Hi Matt,
> > > > --- a/drivers/gpu/drm/i915/i915_pmu.h
> > > > +++ b/drivers/gpu/drm/i915/i915_pmu.h
> > > > @@ -38,7 +38,7 @@ enum {
> > > > __I915_NUM_PMU_SAMPLERS
> > > > };
> > > >
> > > > -#define I915_PMU_MAX_GTS 2
> > > > +#define I915_PMU_MAX_GTS 4
> > >
> > > right! Why not having
> > >
> > > #define I915_PMU_MAX_GTSI915_MAX_GT
> > >
> > > or... why having I915_PMU_MAX_GTS at all?
> > Originally I went the route of s/I915_PMU_MAX_GTS/I915_MAX_GT/g.
> > However, this introduces many changes to where you then move
> > I915_MAX_GT to and #include blocks in fiels that require these values.
> > In the end I decided it was better to keep define and just change the
> > value.
>
> OK, makes sense, then how about
>
> #define I915_PMU_MAX_GTSI915_MAX_GT
>
> i915_pmu.h has visibility on I915_MAX_GT.
ops... it doesn't... sorry!
Reviewed-by: Andi Shyti
Andi
> Andi
>
> > >
> > > Andi
> > >
> > > > /*
> > > > * How many different events we track in the global PMU mask.
> > > > --
> > > > 2.40.0
> > MattA
[Intel-gfx] [PATCH] drm/i915: Fix error handling if driver creation fails during probe
If i915_driver_create() fails to create a valid 'i915' object, we
should just disable the PCI device and return immediately without trying
to call i915_probe_error() that relies on a valid i915 pointer.
Fixes: 12e6f6dc78e4 ("drm/i915/display: Handle GMD_ID identification in display
code")
Reported-by: Dan Carpenter
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_driver.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index c3ab5c32d492..5c3fc57cc4fe 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -762,8 +762,8 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
i915 = i915_driver_create(pdev, ent);
if (IS_ERR(i915)) {
- ret = PTR_ERR(i915);
- goto out_pci_disable;
+ pci_disable_device(pdev);
+ return PTR_ERR(i915);
}
ret = i915_driver_early_probe(i915);
--
2.40.1
Re: [Intel-gfx] [PATCH v8 0/7] drm/i915: use ref_tracker library for tracking wakerefs
On Thu, 1 Jun 2023 19:14:50 +0200 Andrzej Hajda wrote: > Ping on the series, everything reviewed. > Eric, Dave, Jakub, could you take patches 1-4 via net tree? Sure thing, would you mind reposting them separately? Easier for us to apply and it's been over a month since posting, a fresh run of build bots won't hurt either.
Re: [Intel-gfx] [PATCH v8 0/7] drm/i915: use ref_tracker library for tracking wakerefs
On 08.05.2023 19:16, Andrzej Hajda wrote: On 05.05.2023 22:06, Rodrigo Vivi wrote: On Thu, May 04, 2023 at 06:27:53PM +0200, Andrzej Hajda wrote: Hi maintainers of net and i915, On 25.04.2023 00:05, Andrzej Hajda wrote: This is revived patchset improving ref_tracker library and converting i915 internal tracker to ref_tracker. The old thread ended without consensus about small kernel allocations, which are performed under spinlock. I have tried to solve the problem by splitting the calls, but it results in complicated API, so I went back to original solution. If there are better solutions I am glad to discuss them. Meanwhile I send original patchset with addressed remaining comments. Ping on the series, everything reviewed. Eric, Dave, Jakub, could you take patches 1-4 via net tree? Regards Andrzej To: Jani Nikula To: Joonas Lahtinen To: Rodrigo Vivi To: Tvrtko Ursulin To: David Airlie To: Daniel Vetter To: Eric Dumazet Cc: linux-ker...@vger.kernel.org Cc: intel-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Cc: Chris Wilson Cc: net...@vger.kernel.org Cc: Jakub Kicinski Cc: Dmitry Vyukov Cc: "David S. Miller" Cc: Andi Shyti Cc: Das, Nirmoy Signed-off-by: Andrzej Hajda --- Changes in v8: - addressed comments from Eric, Zhou and CI, thanks, - added ref_tracker_dir_init name argument to all callers in one patch - moved intel_wakeref_tracker_show to *.c - s/intel_wakeref_tracker_show/intel_ref_tracker_show/ - removed 'default n' from Kconfig - changed strlcpy to strscpy, - removed assignement from if condition, - removed long lines from patch description - added tags - Link to v7: https://lore.kernel.org/r/20230224-track_gt-v7-0-11f08358c...@intel.com Changes in v7: - removed 8th patch (hold wakeref), as it was already merged - added tags (thx Andi) - Link to v6: https://lore.kernel.org/r/20230224-track_gt-v6-0-0dc8601fd...@intel.com Changes in v6: - rebased to solve minor conflict and allow CI testing - Link to v5: https://lore.kernel.org/r/20230224-track_gt-v5-0-77be86f2c...@intel.com Changes in v5 (thx Andi for review): - use *_locked convention instead of __*, - improved commit messages, - re-worked i915 patches, squashed separation and conversion patches, - added tags, - Link to v4: https://lore.kernel.org/r/20230224-track_gt-v4-0-464e8ab4c...@intel.com Changes in v4: - split "Separate wakeref tracking" to smaller parts - fixed typos, - Link to v1-v3: https://patchwork.freedesktop.org/series/100327/ --- Andrzej Hajda (7): lib/ref_tracker: add unlocked leak print helper lib/ref_tracker: improve printing stats lib/ref_tracker: add printing to memory buffer lib/ref_tracker: remove warnings in case of allocation failure drm/i915: Correct type of wakeref variable drm/i915: Replace custom intel runtime_pm tracker with ref_tracker library drm/i915: Track gt pm wakerefs Finally all patches are reviewed. Question to network and i915 maintainers, how to merge this patchset: 1. Patches 1-4 belongs rather to network domain (especially patch 2). 2. Patches 5-7 are for i915. Well, probably the easiest way to avoid conflicts would be to send this right now through the net repo. And hold patches 5-7 after drm-intel-next can backmerge them. At this point I believe we would be looking at 6.5-rc2 backmerge to drm-intel-next in likely 11 weeks from now. Do we have any urgency on them? Looking to all the changes in i915 I believe we will get many conflicts if we let all these i915 patches go through net tree as well. Eric, Dave, Jakub, could you take patches 1-4? Regards Andrzej What would be the best way to do it? Regards Andrzej drivers/gpu/drm/i915/Kconfig.debug | 18 ++ drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 7 +- .../drm/i915/gem/selftests/i915_gem_coherency.c | 10 +- drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 14 +- drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 13 +- drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h | 3 +- drivers/gpu/drm/i915/gt/intel_context.h | 4 +- drivers/gpu/drm/i915/gt/intel_context_types.h | 2 + drivers/gpu/drm/i915/gt/intel_engine_pm.c | 7 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 + .../gpu/drm/i915/gt/intel_execlists_submission.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 12 +- drivers/gpu/drm/i915/gt/intel_gt_pm.h | 38 +++- drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 4 +- drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 20 +- drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 5 +- drivers/gpu/drm/i915/gt/selftest_reset.c | 10 +- drivers/gpu/drm/i915/gt/selftest_rps.c | 17 +- drivers/gpu/drm/i915/gt/selftest_slpc.c | 5 +-
Re: [Intel-gfx] [PATCH v5 11/13] drm/msm: Use regular fbdev I/O helpers
On 5/30/2023 8:02 AM, Thomas Zimmermann wrote: Use the regular fbdev helpers for framebuffer I/O instead of DRM's helpers. Msm does not use damage handling, so DRM's fbdev helpers are mere wrappers around the fbdev code. By using fbdev helpers directly within each DRM fbdev emulation, we can eventually remove DRM's wrapper functions entirely. Msm's fbdev emulation has been incomplete as it didn't implement damage handling. Partilly fix this by implementing damage handling for write and draw operation. It is still missing for mmaped pages. v4: * use initializer macros for struct fb_ops * partially support damage handling v2: * use FB_SYS_HELPERS option Signed-off-by: Thomas Zimmermann Reviewed-by: Dmitry Baryshkov Acked-by: Sam Ravnborg Cc: Rob Clark Cc: Abhinav Kumar Cc: Dmitry Baryshkov Cc: Sean Paul --- Reviewed-by: Abhinav Kumar
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/fbdev: Remove DRM's helpers for fbdev I/O (rev5)
== Series Details ==
Series: drm/fbdev: Remove DRM's helpers for fbdev I/O (rev5)
URL : https://patchwork.freedesktop.org/series/117671/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13204_full -> Patchwork_117671v5_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
New tests
-
New tests have been introduced between CI_DRM_13204_full and
Patchwork_117671v5_full:
### New IGT tests (4) ###
*
igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
*
igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
*
igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
*
igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_117671v5_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_close_race@multigpu-basic-process:
- shard-apl: NOTRUN -> [SKIP][1] ([fdo#109271]) +6 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117671v5/shard-apl7/igt@gem_close_r...@multigpu-basic-process.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][2] -> [FAIL][3] ([i915#2842])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13204/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117671v5/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][4] -> [ABORT][5] ([i915#5566])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13204/shard-glk3/igt@gen9_exec_pa...@allowed-single.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117671v5/shard-glk9/igt@gen9_exec_pa...@allowed-single.html
* igt@i915_module_load@load:
- shard-glk: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#6227])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117671v5/shard-glk1/igt@i915_module_l...@load.html
* igt@kms_hdmi_inject@inject-audio:
- shard-glk: [PASS][7] -> [SKIP][8] ([fdo#109271])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13204/shard-glk1/igt@kms_hdmi_inj...@inject-audio.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117671v5/shard-glk6/igt@kms_hdmi_inj...@inject-audio.html
*
igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-c-dp-1:
- shard-apl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4579])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117671v5/shard-apl7/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0...@pipe-c-dp-1.html
*
igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-vga-1:
- shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271]) +20 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117671v5/shard-snb7/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotat...@pipe-a-vga-1.html
*
igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4579]) +11
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117671v5/shard-snb1/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0...@pipe-b-hdmi-a-1.html
*
igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-hdmi-a-3
(NEW):
- {shard-dg1}:NOTRUN -> [SKIP][12] ([i915#5235]) +2 similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117671v5/shard-dg1-13/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0...@pipe-b-hdmi-a-3.html
*
igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d-hdmi-a-3
(NEW):
- {shard-dg1}:NOTRUN -> [SKIP][13] ([i915#4579] / [i915#5235])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117671v5/shard-dg1-13/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0...@pipe-d-hdmi-a-3.html
* igt@kms_selftest@all-tests:
- shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4579]) +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117671v5/shard-glk1/igt@kms_selft...@all-tests.html
* igt@kms_setmode@basic@pipe-a-hdmi-a-1:
- shard-snb: NOTRUN -> [FAIL][15] ([i915#5465]) +1 similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117671v5/shard-snb1/igt@kms_setmode@ba...@pipe-a-hdmi-a-1.html
*
[Intel-gfx] [PATCH v12 0/7] mtl: add support for pmdemand
SAGV configuration support for MTL v2: added one missing patch in the previous version v3: chekcpatch warning fixes update index handling for the icl/tgl QGV point handling program pmdemand code simplified v4: update to debufs and pipe values pmdemand regiters removed the macro usage in update_pmdemand_values V5: Addressing comments from Gustavo and Jani And some other fixes for issues from CI v6: Addressing some comments from Gustavo Updates to pmdemand state struct, active phys calculations Got rid of suppress warning patch from v5 v7: Rebased and updates to max ddiclk and active phys calculations v8: updates to active phys calcuations v9: Address styling issues v10: Updates to phys calculation, pmdemand state initialization during HW readout / sanitization v11: Fix CI checkpatch warnings v12: Addressing comments Mika Kahola (1): drm/i915/mtl: Add support for PM DEMAND Vinod Govindapillai (6): drm/i915: fix the derating percentage for MTL drm/i915: update the QGV point frequency calculations drm/i915: store the peak bw per QGV point drm/i915: extract intel_bw_check_qgv_points() drm/i915: modify max_bw to return index to intel_bw_info drm/i915/mtl: find the best QGV point for the SAGV configuration drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_bw.c | 353 drivers/gpu/drm/i915/display/intel_bw.h | 6 + drivers/gpu/drm/i915/display/intel_display.c | 14 + .../gpu/drm/i915/display/intel_display_core.h | 11 + .../drm/i915/display/intel_display_driver.c | 7 + .../gpu/drm/i915/display/intel_display_irq.c | 23 +- .../drm/i915/display/intel_display_power.c| 14 +- .../drm/i915/display/intel_modeset_setup.c| 18 + drivers/gpu/drm/i915/display/intel_pmdemand.c | 525 ++ drivers/gpu/drm/i915/display/intel_pmdemand.h | 56 ++ drivers/gpu/drm/i915/i915_reg.h | 36 +- 12 files changed, 941 insertions(+), 123 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h -- 2.34.1
[Intel-gfx] [PATCH v12 7/7] drm/i915/mtl: Add support for PM DEMAND
From: Mika Kahola
MTL introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case scenarios. Changes made to use REG_BIT
for a register that we touched(GEN8_DE_MISC_IER _MMIO).
Wa_14016740474 is added which applies to Xe_LPD+ display
v2: checkpatch warning fixes, simplify program pmdemand part
v3: update to dbufs and pipes values to pmdemand register(stan)
Removed the macro usage in update_pmdemand_values()
v4: move the pmdemand_pre_plane_update before cdclk update
pmdemand_needs_update included cdclk params comparisons
pmdemand_state NULL check (Gustavo)
pmdemand.o in sorted order in the makefile (Jani)
update pmdemand misc irq handler loop (Gustavo)
active phys bitmask and programming correction (Gustavo)
v5: simplify pmdemand_state structure
simplify methods to find active phys and max port clock
Timeout in case of previou pmdemand task pending (Gustavo)
v6: rebasing
updates to max_ddiclk calculations (Gustavo)
updates to active_phys count method (Gustavo)
v7: use two separate loop to iterate throug old and new
crtc states to calculate the active phys (Gustavo)
v8: use uniform function names (Gustavo)
v9: For phys change iterate through connectors (Imre)
Look for change in phys for pmdemand update (Gustavo, Imre)
Some more stlying changes (Imre)
Update pmdemand state during HW readout/sanitize (Imre)
v10: Fix CI checkpatch warnings
v11: use correct pmdemand object pointer during hw readout,
simplify the check for phys need update (Gustavo)
Bspec: 66451, 64636, 64602, 64603
Cc: Matt Atwood
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Gustavo Sousa
Signed-off-by: José Roberto de Souza
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Gustavo Sousa
Signed-off-by: Mika Kahola
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
Acked-by: Gustavo Sousa
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 14 +
.../gpu/drm/i915/display/intel_display_core.h | 9 +
.../drm/i915/display/intel_display_driver.c | 7 +
.../gpu/drm/i915/display/intel_display_irq.c | 23 +-
.../drm/i915/display/intel_display_power.c| 14 +-
.../drm/i915/display/intel_modeset_setup.c| 18 +
drivers/gpu/drm/i915/display/intel_pmdemand.c | 525 ++
drivers/gpu/drm/i915/display/intel_pmdemand.h | 56 ++
drivers/gpu/drm/i915/i915_reg.h | 36 +-
10 files changed, 697 insertions(+), 6 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1c9ed4c52760..2cd8de174bf6 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -269,6 +269,7 @@ i915-y += \
display/intel_pch_display.o \
display/intel_pch_refclk.o \
display/intel_plane_initial.o \
+ display/intel_pmdemand.o \
display/intel_psr.o \
display/intel_quirks.o \
display/intel_sprite.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f51a55f4e9d0..5cbf5eae2414 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -99,6 +99,7 @@
#include "intel_pcode.h"
#include "intel_pipe_crc.h"
#include "intel_plane_initial.h"
+#include "intel_pmdemand.h"
#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_sdvo.h"
@@ -6352,6 +6353,10 @@ int intel_atomic_check(struct drm_device *dev,
return ret;
}
+ ret = intel_pmdemand_atomic_check(state);
+ if (ret)
+ goto fail;
+
ret = intel_atomic_check_crtcs(state);
if (ret)
goto fail;
@@ -6997,6 +7002,14 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
crtc->config = new_crtc_state;
+ /*
+* In XE_LPD+ Pmdemand combines many parameters such as voltage index,
+* plls, cdclk frequency, QGV point selection parameter etc. Voltage
+* index, cdclk/ddiclk frequencies are supposed to be configured before
+* the cdclk config is set.
+*/
+ intel_pmdemand_pre_plane_update(state);
+
if (state->modeset) {
drm_atomic_helper_update_legacy_modeset_state(dev,
>base);
@@ -7116,6 +7129,7 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
intel_verify_planes(state);
intel_sagv_post_plane_update(state);
+ intel_pmdemand_post_plane_update(state);
[Intel-gfx] [PATCH v12 5/7] drm/i915: modify max_bw to return index to intel_bw_info
MTL uses the peak BW of a QGV point to lock the required QGV
point instead of the QGV index. Instead of passing the deratedbw
of the selected bw_info, return the index to the selected
bw_info so that either deratedbw or peakbw can be used based on
the platform.
v2: use idx to store index returned by max_bw_index functions
v3: return UINT_MAX in icl_max_bw_index in case no match found
v3: check idx >= ARRAY_SIZE
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 27 -
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 56b3975f3ccb..b1cbeda0b2e3 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -593,8 +593,8 @@ static void dg2_get_bw_info(struct drm_i915_private *i915)
i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
}
-static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
- int num_planes, int qgv_point)
+static unsigned int icl_max_bw_index(struct drm_i915_private *dev_priv,
+int num_planes, int qgv_point)
{
int i;
@@ -615,14 +615,14 @@ static unsigned int icl_max_bw(struct drm_i915_private
*dev_priv,
return UINT_MAX;
if (num_planes >= bi->num_planes)
- return bi->deratedbw[qgv_point];
+ return i;
}
- return 0;
+ return UINT_MAX;
}
-static unsigned int tgl_max_bw(struct drm_i915_private *dev_priv,
- int num_planes, int qgv_point)
+static unsigned int tgl_max_bw_index(struct drm_i915_private *dev_priv,
+int num_planes, int qgv_point)
{
int i;
@@ -643,10 +643,10 @@ static unsigned int tgl_max_bw(struct drm_i915_private
*dev_priv,
return UINT_MAX;
if (num_planes <= bi->num_planes)
- return bi->deratedbw[qgv_point];
+ return i;
}
- return dev_priv->display.bw.max[0].deratedbw[qgv_point];
+ return 0;
}
static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
@@ -823,12 +823,19 @@ static int icl_find_qgv_points(struct drm_i915_private
*i915,
return ret;
for (i = 0; i < num_qgv_points; i++) {
+ unsigned int idx;
unsigned int max_data_rate;
if (DISPLAY_VER(i915) > 11)
- max_data_rate = tgl_max_bw(i915, num_active_planes, i);
+ idx = tgl_max_bw_index(i915, num_active_planes, i);
else
- max_data_rate = icl_max_bw(i915, num_active_planes, i);
+ idx = icl_max_bw_index(i915, num_active_planes, i);
+
+ if (idx >= ARRAY_SIZE(i915->display.bw.max))
+ continue;
+
+ max_data_rate = i915->display.bw.max[idx].deratedbw[i];
+
/*
* We need to know which qgv point gives us
* maximum bandwidth in order to disable SAGV
--
2.34.1
[Intel-gfx] [PATCH v12 6/7] drm/i915/mtl: find the best QGV point for the SAGV configuration
>From MTL onwards, we need to find the best QGV point based on
the required data rate and pass the peak BW of that point to
the punit to lock the corresponding QGV point.
v1: Fix for warning from kernel test robot
Bspec: 64636
Reported-by: kernel test robot
Closes: https://lore.kernel.org/r/202305280253.ab8brv2w-...@intel.com/
Reported-by: Dan Carpenter
Closes: https://lore.kernel.org/r/202305280253.ab8brv2w-...@intel.com/
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 87 -
drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
2 files changed, 91 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index b1cbeda0b2e3..7672963dc49c 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -803,6 +803,85 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
return to_intel_bw_state(bw_state);
}
+static int mtl_find_qgv_points(struct drm_i915_private *i915,
+ unsigned int data_rate,
+ unsigned int num_active_planes,
+ const struct intel_bw_state *old_bw_state,
+ struct intel_bw_state *new_bw_state)
+{
+ unsigned int best_rate = UINT_MAX;
+ unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
+ unsigned int qgv_peak_bw = 0;
+ int i;
+ int ret;
+
+ ret = intel_atomic_lock_global_state(_bw_state->base);
+ if (ret)
+ return ret;
+
+ /*
+* If SAGV cannot be enabled, disable the pcode SAGV by passing all 1's
+* for qgv peak bw in PM Demand request. So assign UINT_MAX if SAGV is
+* not enabled. PM Demand code will clamp the value for the register
+*/
+ if (!intel_can_enable_sagv(i915, new_bw_state)) {
+ new_bw_state->qgv_point_peakbw = UINT_MAX;
+ drm_dbg_kms(>drm, "No SAGV, use UINT_MAX as peak bw.");
+ goto out;
+ }
+
+ /*
+* Find the best QGV point by comparing the data_rate with max data rate
+* offered per plane group
+*/
+ for (i = 0; i < num_qgv_points; i++) {
+ unsigned int bw_index =
+ tgl_max_bw_index(i915, num_active_planes, i);
+ unsigned int max_data_rate;
+
+ if (bw_index >= ARRAY_SIZE(i915->display.bw.max))
+ continue;
+
+ max_data_rate = i915->display.bw.max[bw_index].deratedbw[i];
+
+ if (max_data_rate < data_rate)
+ continue;
+
+ if (max_data_rate - data_rate < best_rate) {
+ best_rate = max_data_rate - data_rate;
+ qgv_peak_bw = i915->display.bw.max[bw_index].peakbw[i];
+ }
+
+ drm_dbg_kms(>drm, "QGV point %d: max bw %d required %d
qgv_peak_bw: %d\n",
+ i, max_data_rate, data_rate, qgv_peak_bw);
+ }
+
+ drm_dbg_kms(>drm, "Matching peaks QGV bw: %d for required data
rate: %d\n",
+ qgv_peak_bw, data_rate);
+
+ /*
+* The display configuration cannot be supported if no QGV point
+* satisfying the required data rate is found
+*/
+ if (qgv_peak_bw == 0) {
+ drm_dbg_kms(>drm, "No QGV points for bw %d for display
configuration(%d active planes).\n",
+ data_rate, num_active_planes);
+ return -EINVAL;
+ }
+
+ /* MTL PM DEMAND expects QGV BW parameter in multiples of 100 mbps */
+ new_bw_state->qgv_point_peakbw = DIV_ROUND_CLOSEST(qgv_peak_bw, 100);
+
+out:
+ if (new_bw_state->qgv_point_peakbw != old_bw_state->qgv_point_peakbw) {
+ ret = intel_atomic_serialize_global_state(_bw_state->base);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static int icl_find_qgv_points(struct drm_i915_private *i915,
unsigned int data_rate,
unsigned int num_active_planes,
@@ -928,8 +1007,12 @@ static int intel_bw_check_qgv_points(struct
drm_i915_private *i915,
data_rate = DIV_ROUND_UP(data_rate, 1000);
- return icl_find_qgv_points(i915, data_rate, num_active_planes,
- old_bw_state, new_bw_state);
+ if (DISPLAY_VER(i915) >= 14)
+ return mtl_find_qgv_points(i915, data_rate, num_active_planes,
+ old_bw_state, new_bw_state);
+ else
+ return icl_find_qgv_points(i915, data_rate, num_active_planes,
+ old_bw_state, new_bw_state);
}
static bool intel_bw_state_changed(struct drm_i915_private *i915,
diff --git
[Intel-gfx] [PATCH v12 4/7] drm/i915: extract intel_bw_check_qgv_points()
Extract intel_bw_check_qgv_points() from intel_bw_atomic_check
to facilitate future platform variations in handling SAGV
configurations.
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 235 +---
1 file changed, 130 insertions(+), 105 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index b792d307e9d5..56b3975f3ccb 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -803,6 +803,128 @@ intel_atomic_get_bw_state(struct intel_atomic_state
*state)
return to_intel_bw_state(bw_state);
}
+static int icl_find_qgv_points(struct drm_i915_private *i915,
+ unsigned int data_rate,
+ unsigned int num_active_planes,
+ const struct intel_bw_state *old_bw_state,
+ struct intel_bw_state *new_bw_state)
+{
+ unsigned int max_bw_point = 0;
+ unsigned int max_bw = 0;
+ unsigned int num_psf_gv_points =
i915->display.bw.max[0].num_psf_gv_points;
+ unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
+ u16 psf_points = 0;
+ u16 qgv_points = 0;
+ int i;
+ int ret;
+
+ ret = intel_atomic_lock_global_state(_bw_state->base);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < num_qgv_points; i++) {
+ unsigned int max_data_rate;
+
+ if (DISPLAY_VER(i915) > 11)
+ max_data_rate = tgl_max_bw(i915, num_active_planes, i);
+ else
+ max_data_rate = icl_max_bw(i915, num_active_planes, i);
+ /*
+* We need to know which qgv point gives us
+* maximum bandwidth in order to disable SAGV
+* if we find that we exceed SAGV block time
+* with watermarks. By that moment we already
+* have those, as it is calculated earlier in
+* intel_atomic_check,
+*/
+ if (max_data_rate > max_bw) {
+ max_bw_point = i;
+ max_bw = max_data_rate;
+ }
+ if (max_data_rate >= data_rate)
+ qgv_points |= BIT(i);
+
+ drm_dbg_kms(>drm, "QGV point %d: max bw %d required %d\n",
+ i, max_data_rate, data_rate);
+ }
+
+ for (i = 0; i < num_psf_gv_points; i++) {
+ unsigned int max_data_rate = adl_psf_bw(i915, i);
+
+ if (max_data_rate >= data_rate)
+ psf_points |= BIT(i);
+
+ drm_dbg_kms(>drm, "PSF GV point %d: max bw %d"
+ " required %d\n",
+ i, max_data_rate, data_rate);
+ }
+
+ /*
+* BSpec states that we always should have at least one allowed point
+* left, so if we couldn't - simply reject the configuration for obvious
+* reasons.
+*/
+ if (qgv_points == 0) {
+ drm_dbg_kms(>drm, "No QGV points provide sufficient
memory"
+ " bandwidth %d for display configuration(%d active
planes).\n",
+ data_rate, num_active_planes);
+ return -EINVAL;
+ }
+
+ if (num_psf_gv_points > 0 && psf_points == 0) {
+ drm_dbg_kms(>drm, "No PSF GV points provide sufficient
memory"
+ " bandwidth %d for display configuration(%d active
planes).\n",
+ data_rate, num_active_planes);
+ return -EINVAL;
+ }
+
+ /*
+* Leave only single point with highest bandwidth, if
+* we can't enable SAGV due to the increased memory latency it may
+* cause.
+*/
+ if (!intel_can_enable_sagv(i915, new_bw_state)) {
+ qgv_points = BIT(max_bw_point);
+ drm_dbg_kms(>drm, "No SAGV, using single QGV point %d\n",
+ max_bw_point);
+ }
+
+ /*
+* We store the ones which need to be masked as that is what PCode
+* actually accepts as a parameter.
+*/
+ new_bw_state->qgv_points_mask =
+ ~(ICL_PCODE_REQ_QGV_PT(qgv_points) |
+ ADLS_PCODE_REQ_PSF_PT(psf_points)) &
+ icl_qgv_points_mask(i915);
+
+ /*
+* If the actual mask had changed we need to make sure that
+* the commits are serialized(in case this is a nomodeset, nonblocking)
+*/
+ if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
+ ret = intel_atomic_serialize_global_state(_bw_state->base);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int
[Intel-gfx] [PATCH v12 3/7] drm/i915: store the peak bw per QGV point
In MTL onwards, pcode locks the GV point based on the peak BW
of a QGV point. So store the peak BW of all the QGV points.
v2: use DIV_ROUND_CLOSEST() for the peakBW calculation
Bspec: 64636
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 8 ++--
drivers/gpu/drm/i915/display/intel_display_core.h | 2 ++
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 61b3babf2d83..b792d307e9d5 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -534,10 +534,14 @@ static int tgl_get_bw_info(struct drm_i915_private
*dev_priv, const struct intel
bi->deratedbw[j] = min(maxdebw,
bw * (100 - sa->derating) / 100);
+ bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
+ num_channels *
+ qi.channel_width, 8);
drm_dbg_kms(_priv->drm,
- "BW%d / QGV %d: num_planes=%d
deratedbw=%u\n",
- i, j, bi->num_planes, bi->deratedbw[j]);
+ "BW%d / QGV %d: num_planes=%d deratedbw=%u
peakbw: %u\n",
+ i, j, bi->num_planes, bi->deratedbw[j],
+ bi->peakbw[j]);
}
for (j = 0; j < qi.num_psf_points; j++) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 2209811eb29e..dd8e08c8598f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -314,6 +314,8 @@ struct intel_display {
unsigned int deratedbw[I915_NUM_QGV_POINTS];
/* for each PSF GV point */
unsigned int psf_bw[I915_NUM_PSF_GV_POINTS];
+ /* Peak BW for each QGV point */
+ unsigned int peakbw[I915_NUM_QGV_POINTS];
u8 num_qgv_points;
u8 num_psf_gv_points;
u8 num_planes;
--
2.34.1
[Intel-gfx] [PATCH v12 2/7] drm/i915: update the QGV point frequency calculations
>From MTL onwwards, pcode locks the QGV point based on peak BW of the intended QGV point passed by the driver. So the peak BW calculation must match the value expected by the pcode. Update the calculations as per the Bspec. v2: use DIV_ROUND_* macro for the calculations (Ville) v3: Use only DIV_ROUN_CLOSEST and remove divisor / 2 again Bspec: 64636 Signed-off-by: Vinod Govindapillai Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_bw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index ab405c48ca3a..61b3babf2d83 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -182,7 +182,7 @@ static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv, val2 = intel_uncore_read(_priv->uncore, MTL_MEM_SS_INFO_QGV_POINT_HIGH(point)); dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); - sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000); + sp->dclk = DIV_ROUND_CLOSEST(16667 * dclk, 1000); sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val); sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val); -- 2.34.1
[Intel-gfx] [PATCH v12 1/7] drm/i915: fix the derating percentage for MTL
Follow the values from bspec for the percentage overhead for
efficiency in MTL BW calculations.
Bspec: 64631
Signed-off-by: Vinod Govindapillai
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 597d5816ad1b..ab405c48ca3a 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -379,7 +379,7 @@ static const struct intel_sa_info mtl_sa_info = {
.deburst = 32,
.deprogbwlimit = 38, /* GB/s */
.displayrtids = 256,
- .derating = 20,
+ .derating = 10,
};
static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct
intel_sa_info *sa)
--
2.34.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: pre-initialize some values in probe_gmdid_display()
== Series Details == Series: drm/i915/display: pre-initialize some values in probe_gmdid_display() URL : https://patchwork.freedesktop.org/series/118690/ State : success == Summary == CI Bug Log - changes from CI_DRM_13215 -> Patchwork_118690v1 Summary --- **WARNING** Minor unknown changes coming with Patchwork_118690v1 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_118690v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118690v1/index.html Participating hosts (37 -> 38) -- Additional (1): bat-dg1-5 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_118690v1: ### IGT changes ### Warnings * igt@kms_psr@primary_mmap_gtt: - bat-rplp-1: [SKIP][1] ([i915#1072]) -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13215/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118690v1/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html Known issues Here are the changes found in Patchwork_118690v1 that come from known issues: ### CI changes ### Issues hit * boot: - fi-kbl-8809g: [PASS][3] -> [FAIL][4] ([i915#8293] / [i915#8298]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13215/fi-kbl-8809g/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118690v1/fi-kbl-8809g/boot.html ### IGT changes ### Issues hit * igt@gem_mmap@basic: - bat-dg1-5: NOTRUN -> [SKIP][5] ([i915#4083]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118690v1/bat-dg1-5/igt@gem_m...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-5: NOTRUN -> [SKIP][6] ([i915#4077]) +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118690v1/bat-dg1-5/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-5: NOTRUN -> [SKIP][7] ([i915#4079]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118690v1/bat-dg1-5/igt@gem_tiled_pread_basic.html * igt@i915_module_load@load: - fi-kbl-soraka: [PASS][8] -> [DMESG-WARN][9] ([i915#1982]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13215/fi-kbl-soraka/igt@i915_module_l...@load.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118690v1/fi-kbl-soraka/igt@i915_module_l...@load.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-5: NOTRUN -> [SKIP][10] ([i915#7561]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118690v1/bat-dg1-5/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-dg1-5: NOTRUN -> [SKIP][11] ([i915#6621]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118690v1/bat-dg1-5/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [PASS][12] -> [DMESG-FAIL][13] ([i915#5334]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13215/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118690v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_addfb_basic@basic-x-tiled-legacy: - bat-dg1-5: NOTRUN -> [SKIP][14] ([i915#4212]) +7 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118690v1/bat-dg1-5/igt@kms_addfb_ba...@basic-x-tiled-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-5: NOTRUN -> [SKIP][15] ([i915#4215]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118690v1/bat-dg1-5/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_chamelium_hpd@vga-hpd-fast: - bat-dg1-5: NOTRUN -> [SKIP][16] ([i915#7828]) +8 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118690v1/bat-dg1-5/igt@kms_chamelium_...@vga-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-dg1-5: NOTRUN -> [SKIP][17] ([i915#4103] / [i915#4213]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118690v1/bat-dg1-5/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg1-5: NOTRUN -> [SKIP][18] ([fdo#109285]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118690v1/bat-dg1-5/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1: - bat-dg2-8: [PASS][19] -> [FAIL][20] ([i915#7932]) [19]:
[Intel-gfx] [PATCH] drm/i915/pxp/mtl: intel_pxp_init_hw needs runtime-pm inside pm-complete
In the case of failed suspend flow or cases where the kernel does not go
into full suspend but goes from suspend_prepare back to resume_complete,
we get called for a pm_complete but without runtime_pm guaranteed.
Thus, ensure we take the runtime_pm when calling intel_pxp_init_hw
from within intel_pxp_resume_complete.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
index 1a04067f61fc..1d184dcd63c7 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -36,6 +36,8 @@ void intel_pxp_suspend(struct intel_pxp *pxp)
void intel_pxp_resume_complete(struct intel_pxp *pxp)
{
+ intel_wakeref_t wakeref;
+
if (!intel_pxp_is_enabled(pxp))
return;
@@ -48,7 +50,8 @@ void intel_pxp_resume_complete(struct intel_pxp *pxp)
if (!HAS_ENGINE(pxp->ctrl_gt, GSC0) && !pxp->pxp_component)
return;
- intel_pxp_init_hw(pxp);
+ with_intel_runtime_pm(>ctrl_gt->i915->runtime_pm, wakeref)
+ intel_pxp_init_hw(pxp);
}
void intel_pxp_runtime_suspend(struct intel_pxp *pxp)
base-commit: a66da4c33d8ede541aea9ba6d0d73b556a072d54
--
2.39.0
Re: [Intel-gfx] [PATCH v11 7/7] drm/i915/mtl: Add support for PM DEMAND
On Thu, 2023-06-01 at 11:34 -0300, Gustavo Sousa wrote: > Hi, Vinod. > > I have some comments for this version, please see them below. With those > fixed, > > Acked-by: Gustavo Sousa > > Quoting Vinod Govindapillai (2023-06-01 09:19:23-03:00) > > From: Mika Kahola > > > > MTL introduces a new way to instruct the PUnit with > > power and bandwidth requirements of DE. Add the functionality > > to program the registers and handle waits using interrupts. > > The current wait time for timeouts is programmed for 10 msecs to > > factor in the worst case scenarios. Changes made to use REG_BIT > > for a register that we touched(GEN8_DE_MISC_IER _MMIO). > > > > Wa_14016740474 is added which applies to Xe_LPD+ display > > > > v2: checkpatch warning fixes, simplify program pmdemand part > > > > v3: update to dbufs and pipes values to pmdemand register(stan) > > Removed the macro usage in update_pmdemand_values() > > > > v4: move the pmdemand_pre_plane_update before cdclk update > > pmdemand_needs_update included cdclk params comparisons > > pmdemand_state NULL check (Gustavo) > > pmdemand.o in sorted order in the makefile (Jani) > > update pmdemand misc irq handler loop (Gustavo) > > active phys bitmask and programming correction (Gustavo) > > > > v5: simplify pmdemand_state structure > > simplify methods to find active phys and max port clock > > Timeout in case of previou pmdemand task pending (Gustavo) > > > > v6: rebasing > > updates to max_ddiclk calculations (Gustavo) > > updates to active_phys count method (Gustavo) > > > > v7: use two separate loop to iterate throug old and new > > crtc states to calculate the active phys (Gustavo) > > > > v8: use uniform function names (Gustavo) > > > > v9: For phys change iterate through connectors (Imre) > > Look for change in phys for pmdemand update (Gustavo, Imre) > > Some more stlying changes (Imre) > > Update pmdemand state during HW readout/sanitize (Imre) > > > > v10: Fix CI checkpatch warnings > > > > Bspec: 66451, 64636, 64602, 64603 > > Cc: Matt Atwood > > Cc: Matt Roper > > Cc: Lucas De Marchi > > Cc: Gustavo Sousa > > Signed-off-by: José Roberto de Souza > > Signed-off-by: Radhakrishna Sripada > > Signed-off-by: Gustavo Sousa > > Signed-off-by: Mika Kahola > > Signed-off-by: Vinod Govindapillai > > Reviewed-by: Stanislav Lisovskiy > > --- > > drivers/gpu/drm/i915/Makefile | 1 + > > drivers/gpu/drm/i915/display/intel_display.c | 14 + > > .../gpu/drm/i915/display/intel_display_core.h | 9 + > > .../drm/i915/display/intel_display_driver.c | 7 + > > .../gpu/drm/i915/display/intel_display_irq.c | 23 +- > > .../drm/i915/display/intel_display_power.c | 14 +- > > .../drm/i915/display/intel_modeset_setup.c | 18 + > > drivers/gpu/drm/i915/display/intel_pmdemand.c | 555 ++ > > drivers/gpu/drm/i915/display/intel_pmdemand.h | 56 ++ > > drivers/gpu/drm/i915/i915_reg.h | 36 +- > > 10 files changed, 727 insertions(+), 6 deletions(-) > > create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c > > create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h > > > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > > index 1c9ed4c52760..2cd8de174bf6 100644 > > --- a/drivers/gpu/drm/i915/Makefile > > +++ b/drivers/gpu/drm/i915/Makefile > > @@ -269,6 +269,7 @@ i915-y += \ > > display/intel_pch_display.o \ > > display/intel_pch_refclk.o \ > > display/intel_plane_initial.o \ > > + display/intel_pmdemand.o \ > > display/intel_psr.o \ > > display/intel_quirks.o \ > > display/intel_sprite.o \ > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > b/drivers/gpu/drm/i915/display/intel_display.c > > index f51a55f4e9d0..5cbf5eae2414 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -99,6 +99,7 @@ > > #include "intel_pcode.h" > > #include "intel_pipe_crc.h" > > #include "intel_plane_initial.h" > > +#include "intel_pmdemand.h" > > #include "intel_pps.h" > > #include "intel_psr.h" > > #include "intel_sdvo.h" > > @@ -6352,6 +6353,10 @@ int intel_atomic_check(struct drm_device *dev, > > return ret; > > } > > > > + ret = intel_pmdemand_atomic_check(state); > > + if (ret) > > + goto fail; > > + > > ret = intel_atomic_check_crtcs(state); > > if (ret) > > goto fail; > > @@ -6997,6 +7002,14 @@ static void intel_atomic_commit_tail(struct > > intel_atomic_state *state) > > for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) > > crtc->config = new_crtc_state; > > > > + /* > > + * In XE_LPD+ Pmdemand combines many parameters such as voltage > > index, > > + * plls, cdclk frequency, QGV point selection parameter etc. > > Voltage > > +
Re: [Intel-gfx] [PATCH V5] drm/i915/gt: Add workaround 14016712196
On 01.06.2023 13:09, Tejas Upadhyay wrote:
For mtl, workaround suggests that, SW insert a
dummy PIPE_CONTROL prior to PIPE_CONTROL which
contains a post sync: Timestamp or Write Immediate.
Bspec: 72197
V5:
- Remove ret variable - Andi
V4:
- Update commit message, avoid returing cs - Andi/Matt
V3:
- Wrap dummy pipe control stuff in API - Andi
V2:
- Fix kernel test robot warnings
Closes:
https://lore.kernel.org/oe-kbuild-all/202305121525.3ewdgoby-...@intel.com/
Reviewed-by: Andi Shyti
Signed-off-by: Tejas Upadhyay
Reviewed-by: Andrzej Hajda
Regards
Andrzej
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 38
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index e1c76e5bfa82..23857cc08eca 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -177,14 +177,40 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32
*cs, const i915_reg_t inv
return cs;
}
+static int mtl_dummy_pipe_control(struct i915_request *rq)
+{
+ /* Wa_14016712196 */
+ if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
+ u32 *cs;
+
+ /* dummy PIPE_CONTROL + depth flush */
+ cs = intel_ring_begin(rq, 6);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+ cs = gen12_emit_pipe_control(cs,
+0,
+PIPE_CONTROL_DEPTH_CACHE_FLUSH,
+LRC_PPHWSP_SCRATCH_ADDR);
+ intel_ring_advance(rq, cs);
+ }
+
+ return 0;
+}
+
int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
{
struct intel_engine_cs *engine = rq->engine;
if (mode & EMIT_FLUSH) {
u32 flags = 0;
+ int err;
u32 *cs;
+ err = mtl_dummy_pipe_control(rq);
+ if (err)
+ return err;
+
flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
flags |= PIPE_CONTROL_FLUSH_L3;
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
@@ -217,6 +243,11 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
if (mode & EMIT_INVALIDATE) {
u32 flags = 0;
u32 *cs, count;
+ int err;
+
+ err = mtl_dummy_pipe_control(rq);
+ if (err)
+ return err;
flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
flags |= PIPE_CONTROL_TLB_INVALIDATE;
@@ -733,6 +764,13 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request
*rq, u32 *cs)
PIPE_CONTROL_DC_FLUSH_ENABLE |
PIPE_CONTROL_FLUSH_ENABLE);
+ /* Wa_14016712196 */
+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ /* dummy PIPE_CONTROL + depth flush */
+ cs = gen12_emit_pipe_control(cs, 0,
+PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
+
if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12,
50))
/* Wa_1409600907 */
flags |= PIPE_CONTROL_DEPTH_STALL;
[Intel-gfx] [PATCH] drm/i915/gt: limit lmem allocation size to succeed on SmallBars
In case system is short on mappable memory (256MB on SmallBar) allocation
of two 1GB buffers will fail.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8300
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/selftest_tlb.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_tlb.c
b/drivers/gpu/drm/i915/gt/selftest_tlb.c
index 4493c8518e91b2..3bd6b540257b46 100644
--- a/drivers/gpu/drm/i915/gt/selftest_tlb.c
+++ b/drivers/gpu/drm/i915/gt/selftest_tlb.c
@@ -190,11 +190,18 @@ pte_tlbinv(struct intel_context *ce,
static struct drm_i915_gem_object *create_lmem(struct intel_gt *gt)
{
+ struct intel_memory_region *mr =
gt->i915->mm.regions[INTEL_REGION_LMEM_0];
+ resource_size_t size = SZ_1G;
+
/*
* Allocation of largest possible page size allows to test all types
-* of pages.
+* of pages. To succeed with both allocations, especially in case of
Small
+* BAR, try to allocate no more than quarter of mappable memory.
*/
- return i915_gem_object_create_lmem(gt->i915, SZ_1G,
I915_BO_ALLOC_CONTIGUOUS);
+ if (mr && size > mr->io_size / 4)
+ size = mr->io_size / 4;
+
+ return i915_gem_object_create_lmem(gt->i915, size,
I915_BO_ALLOC_CONTIGUOUS);
}
static struct drm_i915_gem_object *create_smem(struct intel_gt *gt)
--
2.34.1
Re: [Intel-gfx] [PATCH] drm/i915/gt: Use the correct error value when kernel_context() fails
> -Original Message-
> From: Intel-gfx On Behalf Of
> Andrzej Hajda
> Sent: Thursday, June 1, 2023 6:14 PM
> To: Andi Shyti ; Intel GFX g...@lists.freedesktop.org>; DRI Devel
> Cc: Chris Wilson ; sta...@vger.kernel.org; Dan
> Carpenter ; Andi Shyti
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/gt: Use the correct error value
> when kernel_context() fails
>
> On 26.05.2023 14:41, Andi Shyti wrote:
> > kernel_context() returns an error pointer. Use pointer-error
> > conversion functions to evaluate its return value, rather than
> > checking for a '0' return.
> >
> > Fixes: eb5c10cbbc2f ("drm/i915: Remove I915_USER_PRIORITY_SHIFT")
> > Reported-by: Dan Carpenter
> > Signed-off-by: Andi Shyti
> > Cc: Chris Wilson < ch...@chris-wilson.co.uk>
> > Cc: # v5.13+
>
> Reviewed-by: Andrzej Hajda
>
> Regards
> Andrzej
>
> > ---
> > drivers/gpu/drm/i915/gt/selftest_execlists.c | 12
> > 1 file changed, 8 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c
> > b/drivers/gpu/drm/i915/gt/selftest_execlists.c
> > index 736b89a8ecf54..4202df5b8c122 100644
> > --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
> > +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
> > @@ -1530,8 +1530,8 @@ static int live_busywait_preempt(void *arg)
> > struct drm_i915_gem_object *obj;
> > struct i915_vma *vma;
> > enum intel_engine_id id;
> > - int err = -ENOMEM;
> > u32 *map;
> > + int err;
We could initialize err with 0 and remove err = 0 assignment below but leaving
up to you.
> >
> > /*
> > * Verify that even without HAS_LOGICAL_RING_PREEMPTION, we
> can @@
> > -1539,13 +1539,17 @@ static int live_busywait_preempt(void *arg)
> > */
> >
> > ctx_hi = kernel_context(gt->i915, NULL);
> > - if (!ctx_hi)
> > - return -ENOMEM;
> > + if (IS_ERR(ctx_hi))
> > + return PTR_ERR(ctx_hi);
> > +
> > ctx_hi->sched.priority = I915_CONTEXT_MAX_USER_PRIORITY;
> >
> > ctx_lo = kernel_context(gt->i915, NULL);
> > - if (!ctx_lo)
> > + if (IS_ERR(ctx_lo)) {
> > + err = PTR_ERR(ctx_lo);
> > goto err_ctx_hi;
> > + }
> > +
Looks fine,
Acked-by: Tejas Upadhyay
> > ctx_lo->sched.priority = I915_CONTEXT_MIN_USER_PRIORITY;
> >
> > obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
Re: [Intel-gfx] [PATCH] drm/i915/gt: Use the correct error value when kernel_context() fails
Hi Tejas,
> > > @@ -1530,8 +1530,8 @@ static int live_busywait_preempt(void *arg)
> > > struct drm_i915_gem_object *obj;
> > > struct i915_vma *vma;
> > > enum intel_engine_id id;
> > > - int err = -ENOMEM;
> > > u32 *map;
> > > + int err;
>
> We could initialize err with 0 and remove err = 0 assignment below but
> leaving up to you.
that assignement must be a leftover from previous patches because
err is already initialized here:
err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
will remove it. Thanks!
> > >
> > > /*
> > >* Verify that even without HAS_LOGICAL_RING_PREEMPTION, we
> > can @@
> > > -1539,13 +1539,17 @@ static int live_busywait_preempt(void *arg)
> > >*/
> > >
> > > ctx_hi = kernel_context(gt->i915, NULL);
> > > - if (!ctx_hi)
> > > - return -ENOMEM;
> > > + if (IS_ERR(ctx_hi))
> > > + return PTR_ERR(ctx_hi);
> > > +
> > > ctx_hi->sched.priority = I915_CONTEXT_MAX_USER_PRIORITY;
> > >
> > > ctx_lo = kernel_context(gt->i915, NULL);
> > > - if (!ctx_lo)
> > > + if (IS_ERR(ctx_lo)) {
> > > + err = PTR_ERR(ctx_lo);
> > > goto err_ctx_hi;
> > > + }
> > > +
>
> Looks fine,
> Acked-by: Tejas Upadhyay
Thank you!
Andi
>
> > > ctx_lo->sched.priority = I915_CONTEXT_MIN_USER_PRIORITY;
> > >
> > > obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
>
Re: [Intel-gfx] [PATCH v11 7/7] drm/i915/mtl: Add support for PM DEMAND
Hi, Vinod.
I have some comments for this version, please see them below. With those
fixed,
Acked-by: Gustavo Sousa
Quoting Vinod Govindapillai (2023-06-01 09:19:23-03:00)
>From: Mika Kahola
>
>MTL introduces a new way to instruct the PUnit with
>power and bandwidth requirements of DE. Add the functionality
>to program the registers and handle waits using interrupts.
>The current wait time for timeouts is programmed for 10 msecs to
>factor in the worst case scenarios. Changes made to use REG_BIT
>for a register that we touched(GEN8_DE_MISC_IER _MMIO).
>
>Wa_14016740474 is added which applies to Xe_LPD+ display
>
>v2: checkpatch warning fixes, simplify program pmdemand part
>
>v3: update to dbufs and pipes values to pmdemand register(stan)
>Removed the macro usage in update_pmdemand_values()
>
>v4: move the pmdemand_pre_plane_update before cdclk update
>pmdemand_needs_update included cdclk params comparisons
>pmdemand_state NULL check (Gustavo)
>pmdemand.o in sorted order in the makefile (Jani)
>update pmdemand misc irq handler loop (Gustavo)
>active phys bitmask and programming correction (Gustavo)
>
>v5: simplify pmdemand_state structure
>simplify methods to find active phys and max port clock
>Timeout in case of previou pmdemand task pending (Gustavo)
>
>v6: rebasing
>updates to max_ddiclk calculations (Gustavo)
>updates to active_phys count method (Gustavo)
>
>v7: use two separate loop to iterate throug old and new
>crtc states to calculate the active phys (Gustavo)
>
>v8: use uniform function names (Gustavo)
>
>v9: For phys change iterate through connectors (Imre)
>Look for change in phys for pmdemand update (Gustavo, Imre)
>Some more stlying changes (Imre)
>Update pmdemand state during HW readout/sanitize (Imre)
>
>v10: Fix CI checkpatch warnings
>
>Bspec: 66451, 64636, 64602, 64603
>Cc: Matt Atwood
>Cc: Matt Roper
>Cc: Lucas De Marchi
>Cc: Gustavo Sousa
>Signed-off-by: José Roberto de Souza
>Signed-off-by: Radhakrishna Sripada
>Signed-off-by: Gustavo Sousa
>Signed-off-by: Mika Kahola
>Signed-off-by: Vinod Govindapillai
>Reviewed-by: Stanislav Lisovskiy
>---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 14 +
> .../gpu/drm/i915/display/intel_display_core.h | 9 +
> .../drm/i915/display/intel_display_driver.c | 7 +
> .../gpu/drm/i915/display/intel_display_irq.c | 23 +-
> .../drm/i915/display/intel_display_power.c| 14 +-
> .../drm/i915/display/intel_modeset_setup.c| 18 +
> drivers/gpu/drm/i915/display/intel_pmdemand.c | 555 ++
> drivers/gpu/drm/i915/display/intel_pmdemand.h | 56 ++
> drivers/gpu/drm/i915/i915_reg.h | 36 +-
> 10 files changed, 727 insertions(+), 6 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h
>
>diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>index 1c9ed4c52760..2cd8de174bf6 100644
>--- a/drivers/gpu/drm/i915/Makefile
>+++ b/drivers/gpu/drm/i915/Makefile
>@@ -269,6 +269,7 @@ i915-y += \
> display/intel_pch_display.o \
> display/intel_pch_refclk.o \
> display/intel_plane_initial.o \
>+display/intel_pmdemand.o \
> display/intel_psr.o \
> display/intel_quirks.o \
> display/intel_sprite.o \
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index f51a55f4e9d0..5cbf5eae2414 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -99,6 +99,7 @@
> #include "intel_pcode.h"
> #include "intel_pipe_crc.h"
> #include "intel_plane_initial.h"
>+#include "intel_pmdemand.h"
> #include "intel_pps.h"
> #include "intel_psr.h"
> #include "intel_sdvo.h"
>@@ -6352,6 +6353,10 @@ int intel_atomic_check(struct drm_device *dev,
> return ret;
> }
>
>+ret = intel_pmdemand_atomic_check(state);
>+if (ret)
>+goto fail;
>+
> ret = intel_atomic_check_crtcs(state);
> if (ret)
> goto fail;
>@@ -6997,6 +7002,14 @@ static void intel_atomic_commit_tail(struct
>intel_atomic_state *state)
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
> crtc->config = new_crtc_state;
>
>+/*
>+ * In XE_LPD+ Pmdemand combines many parameters such as voltage index,
>+ * plls, cdclk frequency, QGV point selection parameter etc. Voltage
>+ * index, cdclk/ddiclk frequencies are supposed to be configured
>before
>+ * the cdclk config is set.
>+ */
>+intel_pmdemand_pre_plane_update(state);
>+
> if (state->modeset) {
> drm_atomic_helper_update_legacy_modeset_state(dev,
> >base);
>
>@@ -7116,6 +7129,7 @@ static void intel_atomic_commit_tail(struct
Re: [Intel-gfx] [PATCH v6 09/10] vfio/pci: Extend VFIO_DEVICE_GET_PCI_HOT_RESET_INFO for vfio device cdev
On Thu, 1 Jun 2023 06:06:17 +
"Liu, Yi L" wrote:
> > From: Jason Gunthorpe
> > Sent: Thursday, June 1, 2023 3:00 AM
> >
> > On Fri, May 26, 2023 at 10:04:27AM +0800, Baolu Lu wrote:
> > > On 5/25/23 9:02 PM, Liu, Yi L wrote:
> > > > > It's possible that requirement
> > > > > might be relaxed in the new DMA ownership model, but as it is right
> > > > > now, the code enforces that requirement and any new discussion about
> > > > > what makes hot-reset available should note both the ownership and
> > > > > dev_set requirement. Thanks,
> > > > I think your point is that if an iommufd_ctx has acquired DMA ownerhisp
> > > > of an iommu_group, it means the device is owned. And it should not
> > > > matter whether all the devices in the iommu_group is present in the
> > > > dev_set. It is allowed that some devices are bound to pci-stub or
> > > > pcieport driver. Is it?
> > > >
> > > > Actually I have a doubt on it. IIUC, the above requirement on dev_set
> > > > is to ensure the reset to the devices are protected by the
> > > > dev_set->lock.
> > > > So that either the reset issued by driver itself or a hot reset request
> > > > from user, there is no race. But if a device is not in the dev_set, then
> > > > hot reset request from user might race with the bound driver. DMA
> > > > ownership
> > > > only guarantees the drivers won't handle DMA via DMA API which would
> > > > have
> > > > conflict with DMA mappings from user. I'm not sure if it is able to
> > > > guarantee reset is exclusive as well. I see pci-stub and pcieport driver
> > > > are the only two drivers that set the driver_managed_dma flag besides
> > > > the
> > > > vfio drivers. pci-stub may be fine. not sure about pcieport driver.
> > >
> > > commit c7d469849747 ("PCI: portdrv: Set driver_managed_dma") described
> > > the criteria of adding driver_managed_dma to the pcieport driver.
> > >
> > > "
> > > We achieve this by setting ".driver_managed_dma = true" in pci_driver
> > > structure. It is safe because the portdrv driver meets below criteria:
> > >
> > > - This driver doesn't use DMA, as you can't find any related calls like
> > > pci_set_master() or any kernel DMA API (dma_map_*() and etc.).
> > > - It doesn't use MMIO as you can't find ioremap() or similar calls. It's
> > > tolerant to userspace possibly also touching the same MMIO registers
> > > via P2P DMA access.
> > > "
> > >
> > > pci_rest_device() definitely shouldn't be done by the kernel drivers
> > > that have driver_managed_dma set.
> >
> > Right
> >
> > The only time it is safe to reset is if you know there is no attached
> > driver or you know VFIO is the attached driver and the caller owns the
> > VFIO too.
> >
> > We haven't done a no attached driver test due to races.
>
> Ok. @Alex, should we relax the above dev_set requirement now or should
> be in a separate series?
Sounds like no, you should be rejecting enhancements that increase
scope at this point and I don't see consensus here. My concern was
that we're not correctly describing the dev_set restriction which is
already in place but needs to be more explicitly described in an
implied ownership model vs proof of ownership model. Thanks,
Alex
Re: [Intel-gfx] [PATCHv2] drm/i915/display: Print useful information on error
On Thu, 01 Jun 2023, Arun R Murthy wrote:
> For modifier not supporting async flip, print the modifier and display
> version. Helps in reading the error message.
>
> v2: Reframe the error message (Jani)
>
> Signed-off-by: Arun R Murthy
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 10 ++
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f51a55f4e9d0..adaba43bde2b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6012,8 +6012,9 @@ static int intel_async_flip_check_hw(struct
> intel_atomic_state *state, struct in
>*/
> if (DISPLAY_VER(i915) < 12) {
> drm_dbg_kms(>drm,
> - "[PLANE:%d:%s] Modifier does not
> support async flips\n",
> - plane->base.base.id,
> plane->base.name);
> + "[PLANE:%d:%s] Modifier 0x%llx does
> not support asyn flip on display ver %d\n",
*async
> + plane->base.base.id,
> plane->base.name,
> + new_plane_state->hw.fb->modifier,
> DISPLAY_VER(i915));
> return -EINVAL;
> }
> break;
> @@ -6025,8 +6026,9 @@ static int intel_async_flip_check_hw(struct
> intel_atomic_state *state, struct in
> break;
> default:
> drm_dbg_kms(>drm,
> - "[PLANE:%d:%s] Modifier does not support
> async flips\n",
> - plane->base.base.id, plane->base.name);
> + "[PLANE:%d:%s] Modifier 0x%llx does not
> support async flip\n",
> + plane->base.base.id, plane->base.name,
> + new_plane_state->hw.fb->modifier);
> return -EINVAL;
> }
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave & Daniel, One fix appeared this morning, related to OA API for non-power-of-two reports. Full CI results not in yet, BAT is looking good so please check before pulling the trigger. Regards, Joonas *** drm-intel-fixes-2023-06-01: - Fix for OA reporting to allow detecting non-power-of-two reports The following changes since commit 7877cb91f1081754a1487c144d85dc0d2e2e7fc4: Linux 6.4-rc4 (2023-05-28 07:49:00 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2023-06-01 for you to fetch changes up to 62fe398761cd06a428e6f367aba84732a2f1c268: drm/i915/perf: Clear out entire reports after reading if not power of 2 size (2023-06-01 09:41:58 +0300) - Fix for OA reporting to allow detecting non-power-of-two reports Ashutosh Dixit (1): drm/i915/perf: Clear out entire reports after reading if not power of 2 size drivers/gpu/drm/i915/i915_perf.c | 17 +++-- 1 file changed, 11 insertions(+), 6 deletions(-)
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v5,01/13] fbdev: Add Kconfig options to select different fb_ops helpers
== Series Details ==
Series: series starting with [v5,01/13] fbdev: Add Kconfig options to select
different fb_ops helpers
URL : https://patchwork.freedesktop.org/series/118574/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13204_full -> Patchwork_118574v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_118574v1_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_flip@dpms-off-confusion@b-hdmi-a3:
- {shard-dg1}:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13204/shard-dg1-13/igt@kms_flip@dpms-off-confus...@b-hdmi-a3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118574v1/shard-dg1-13/igt@kms_flip@dpms-off-confus...@b-hdmi-a3.html
New tests
-
New tests have been introduced between CI_DRM_13204_full and
Patchwork_118574v1_full:
### New IGT tests (4) ###
*
igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-a-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
*
igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-b-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
*
igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-c-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
*
igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-d-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_118574v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_barrier_race@remote-request@rcs0:
- shard-apl: [PASS][3] -> [ABORT][4] ([i915#7461] / [i915#8211] /
[i915#8234])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13204/shard-apl3/igt@gem_barrier_race@remote-requ...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118574v1/shard-apl3/igt@gem_barrier_race@remote-requ...@rcs0.html
* igt@gem_busy@close-race:
- shard-glk: [PASS][5] -> [ABORT][6] ([i915#6016])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13204/shard-glk2/igt@gem_b...@close-race.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118574v1/shard-glk7/igt@gem_b...@close-race.html
* igt@gem_close_race@multigpu-basic-process:
- shard-apl: NOTRUN -> [SKIP][7] ([fdo#109271]) +6 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118574v1/shard-apl6/igt@gem_close_r...@multigpu-basic-process.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][8] -> [FAIL][9] ([i915#2846])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13204/shard-glk8/igt@gem_exec_f...@basic-deadline.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118574v1/shard-glk4/igt@gem_exec_f...@basic-deadline.html
* igt@i915_module_load@load:
- shard-glk: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#6227])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118574v1/shard-glk1/igt@i915_module_l...@load.html
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][11] -> [INCOMPLETE][12] ([i915#7790])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13204/shard-snb5/igt@i915_pm_...@reset.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118574v1/shard-snb1/igt@i915_pm_...@reset.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: NOTRUN -> [FAIL][13] ([i915#72])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118574v1/shard-glk1/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html
* igt@kms_hdmi_inject@inject-audio:
- shard-glk: [PASS][14] -> [SKIP][15] ([fdo#109271])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13204/shard-glk1/igt@kms_hdmi_inj...@inject-audio.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118574v1/shard-glk3/igt@kms_hdmi_inj...@inject-audio.html
*
igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-c-dp-1:
- shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4579])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118574v1/shard-apl6/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0...@pipe-c-dp-1.html
*
igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-vga-1:
- shard-snb: NOTRUN -> [SKIP][17] ([fdo#109271]) +20 similar issues
[17]:
[Intel-gfx] WW22.4 Linux-next Regression update
Regression found: #1 Test case: igt@runner@aborted boards impacted: multiple Logs: https://intel-gfx-ci.01.org/tree/linux-next/next-20230601/bat-mtlp-6/boot0.txt Already existing issue: -NA- Next Steps: Bisecting in progress Linux-kernel tag: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20230601 CI Run Status : https://intel-gfx-ci.01.org/tree/linux-next/combined-alt.html? Note: Please reply to this thread for any kind of information on this regression.
Re: [Intel-gfx] [PATCH] drm/i915/gt: Use the correct error value when kernel_context() fails
On 26.05.2023 14:41, Andi Shyti wrote:
kernel_context() returns an error pointer. Use pointer-error
conversion functions to evaluate its return value, rather than
checking for a '0' return.
Fixes: eb5c10cbbc2f ("drm/i915: Remove I915_USER_PRIORITY_SHIFT")
Reported-by: Dan Carpenter
Signed-off-by: Andi Shyti
Cc: Chris Wilson < ch...@chris-wilson.co.uk>
Cc: # v5.13+
Reviewed-by: Andrzej Hajda
Regards
Andrzej
---
drivers/gpu/drm/i915/gt/selftest_execlists.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c
b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 736b89a8ecf54..4202df5b8c122 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -1530,8 +1530,8 @@ static int live_busywait_preempt(void *arg)
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
enum intel_engine_id id;
- int err = -ENOMEM;
u32 *map;
+ int err;
/*
* Verify that even without HAS_LOGICAL_RING_PREEMPTION, we can
@@ -1539,13 +1539,17 @@ static int live_busywait_preempt(void *arg)
*/
ctx_hi = kernel_context(gt->i915, NULL);
- if (!ctx_hi)
- return -ENOMEM;
+ if (IS_ERR(ctx_hi))
+ return PTR_ERR(ctx_hi);
+
ctx_hi->sched.priority = I915_CONTEXT_MAX_USER_PRIORITY;
ctx_lo = kernel_context(gt->i915, NULL);
- if (!ctx_lo)
+ if (IS_ERR(ctx_lo)) {
+ err = PTR_ERR(ctx_lo);
goto err_ctx_hi;
+ }
+
ctx_lo->sched.priority = I915_CONTEXT_MIN_USER_PRIORITY;
obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
Re: [Intel-gfx] [PATCH v2] drm/i915/mtl: Reset only one lane in case of MFD
On Thu, 2023-06-01 at 13:13 +0300, Mika Kahola wrote: > In case when only two or less transmit lanes are owned such as MFD > (DP-alt with x2 lanes) we need to reset only one data lane (lane0). > With only x2 lanes we don't need to poll for the phy current > status on both data lanes since only the owned data lane will respond. > > v2: Find better naming for lanes and revise the commit message (Luca) > > Reviewed-by: Arun R Murthy (v1) > Signed-off-by: Mika Kahola > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 39 > 1 file changed, 23 insertions(+), 16 deletions(-) Reviewed-by: Luca Coelho -- Cheers, Luca.
[Intel-gfx] [PATCH v11 7/7] drm/i915/mtl: Add support for PM DEMAND
From: Mika Kahola
MTL introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case scenarios. Changes made to use REG_BIT
for a register that we touched(GEN8_DE_MISC_IER _MMIO).
Wa_14016740474 is added which applies to Xe_LPD+ display
v2: checkpatch warning fixes, simplify program pmdemand part
v3: update to dbufs and pipes values to pmdemand register(stan)
Removed the macro usage in update_pmdemand_values()
v4: move the pmdemand_pre_plane_update before cdclk update
pmdemand_needs_update included cdclk params comparisons
pmdemand_state NULL check (Gustavo)
pmdemand.o in sorted order in the makefile (Jani)
update pmdemand misc irq handler loop (Gustavo)
active phys bitmask and programming correction (Gustavo)
v5: simplify pmdemand_state structure
simplify methods to find active phys and max port clock
Timeout in case of previou pmdemand task pending (Gustavo)
v6: rebasing
updates to max_ddiclk calculations (Gustavo)
updates to active_phys count method (Gustavo)
v7: use two separate loop to iterate throug old and new
crtc states to calculate the active phys (Gustavo)
v8: use uniform function names (Gustavo)
v9: For phys change iterate through connectors (Imre)
Look for change in phys for pmdemand update (Gustavo, Imre)
Some more stlying changes (Imre)
Update pmdemand state during HW readout/sanitize (Imre)
v10: Fix CI checkpatch warnings
Bspec: 66451, 64636, 64602, 64603
Cc: Matt Atwood
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Gustavo Sousa
Signed-off-by: José Roberto de Souza
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Gustavo Sousa
Signed-off-by: Mika Kahola
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 14 +
.../gpu/drm/i915/display/intel_display_core.h | 9 +
.../drm/i915/display/intel_display_driver.c | 7 +
.../gpu/drm/i915/display/intel_display_irq.c | 23 +-
.../drm/i915/display/intel_display_power.c| 14 +-
.../drm/i915/display/intel_modeset_setup.c| 18 +
drivers/gpu/drm/i915/display/intel_pmdemand.c | 555 ++
drivers/gpu/drm/i915/display/intel_pmdemand.h | 56 ++
drivers/gpu/drm/i915/i915_reg.h | 36 +-
10 files changed, 727 insertions(+), 6 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1c9ed4c52760..2cd8de174bf6 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -269,6 +269,7 @@ i915-y += \
display/intel_pch_display.o \
display/intel_pch_refclk.o \
display/intel_plane_initial.o \
+ display/intel_pmdemand.o \
display/intel_psr.o \
display/intel_quirks.o \
display/intel_sprite.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f51a55f4e9d0..5cbf5eae2414 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -99,6 +99,7 @@
#include "intel_pcode.h"
#include "intel_pipe_crc.h"
#include "intel_plane_initial.h"
+#include "intel_pmdemand.h"
#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_sdvo.h"
@@ -6352,6 +6353,10 @@ int intel_atomic_check(struct drm_device *dev,
return ret;
}
+ ret = intel_pmdemand_atomic_check(state);
+ if (ret)
+ goto fail;
+
ret = intel_atomic_check_crtcs(state);
if (ret)
goto fail;
@@ -6997,6 +7002,14 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
crtc->config = new_crtc_state;
+ /*
+* In XE_LPD+ Pmdemand combines many parameters such as voltage index,
+* plls, cdclk frequency, QGV point selection parameter etc. Voltage
+* index, cdclk/ddiclk frequencies are supposed to be configured before
+* the cdclk config is set.
+*/
+ intel_pmdemand_pre_plane_update(state);
+
if (state->modeset) {
drm_atomic_helper_update_legacy_modeset_state(dev,
>base);
@@ -7116,6 +7129,7 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
intel_verify_planes(state);
intel_sagv_post_plane_update(state);
+ intel_pmdemand_post_plane_update(state);
drm_atomic_helper_commit_hw_done(>base);
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
[Intel-gfx] [PATCH v11 6/7] drm/i915/mtl: find the best QGV point for the SAGV configuration
>From MTL onwards, we need to find the best QGV point based on
the required data rate and pass the peak BW of that point to
the punit to lock the corresponding QGV point.
v1: Fix for warning from kernel test robot
Bspec: 64636
Reported-by: kernel test robot
Closes: https://lore.kernel.org/r/202305280253.ab8brv2w-...@intel.com/
Reported-by: Dan Carpenter
Closes: https://lore.kernel.org/r/202305280253.ab8brv2w-...@intel.com/
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 87 -
drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
2 files changed, 91 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index b1cbeda0b2e3..7672963dc49c 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -803,6 +803,85 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
return to_intel_bw_state(bw_state);
}
+static int mtl_find_qgv_points(struct drm_i915_private *i915,
+ unsigned int data_rate,
+ unsigned int num_active_planes,
+ const struct intel_bw_state *old_bw_state,
+ struct intel_bw_state *new_bw_state)
+{
+ unsigned int best_rate = UINT_MAX;
+ unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
+ unsigned int qgv_peak_bw = 0;
+ int i;
+ int ret;
+
+ ret = intel_atomic_lock_global_state(_bw_state->base);
+ if (ret)
+ return ret;
+
+ /*
+* If SAGV cannot be enabled, disable the pcode SAGV by passing all 1's
+* for qgv peak bw in PM Demand request. So assign UINT_MAX if SAGV is
+* not enabled. PM Demand code will clamp the value for the register
+*/
+ if (!intel_can_enable_sagv(i915, new_bw_state)) {
+ new_bw_state->qgv_point_peakbw = UINT_MAX;
+ drm_dbg_kms(>drm, "No SAGV, use UINT_MAX as peak bw.");
+ goto out;
+ }
+
+ /*
+* Find the best QGV point by comparing the data_rate with max data rate
+* offered per plane group
+*/
+ for (i = 0; i < num_qgv_points; i++) {
+ unsigned int bw_index =
+ tgl_max_bw_index(i915, num_active_planes, i);
+ unsigned int max_data_rate;
+
+ if (bw_index >= ARRAY_SIZE(i915->display.bw.max))
+ continue;
+
+ max_data_rate = i915->display.bw.max[bw_index].deratedbw[i];
+
+ if (max_data_rate < data_rate)
+ continue;
+
+ if (max_data_rate - data_rate < best_rate) {
+ best_rate = max_data_rate - data_rate;
+ qgv_peak_bw = i915->display.bw.max[bw_index].peakbw[i];
+ }
+
+ drm_dbg_kms(>drm, "QGV point %d: max bw %d required %d
qgv_peak_bw: %d\n",
+ i, max_data_rate, data_rate, qgv_peak_bw);
+ }
+
+ drm_dbg_kms(>drm, "Matching peaks QGV bw: %d for required data
rate: %d\n",
+ qgv_peak_bw, data_rate);
+
+ /*
+* The display configuration cannot be supported if no QGV point
+* satisfying the required data rate is found
+*/
+ if (qgv_peak_bw == 0) {
+ drm_dbg_kms(>drm, "No QGV points for bw %d for display
configuration(%d active planes).\n",
+ data_rate, num_active_planes);
+ return -EINVAL;
+ }
+
+ /* MTL PM DEMAND expects QGV BW parameter in multiples of 100 mbps */
+ new_bw_state->qgv_point_peakbw = DIV_ROUND_CLOSEST(qgv_peak_bw, 100);
+
+out:
+ if (new_bw_state->qgv_point_peakbw != old_bw_state->qgv_point_peakbw) {
+ ret = intel_atomic_serialize_global_state(_bw_state->base);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static int icl_find_qgv_points(struct drm_i915_private *i915,
unsigned int data_rate,
unsigned int num_active_planes,
@@ -928,8 +1007,12 @@ static int intel_bw_check_qgv_points(struct
drm_i915_private *i915,
data_rate = DIV_ROUND_UP(data_rate, 1000);
- return icl_find_qgv_points(i915, data_rate, num_active_planes,
- old_bw_state, new_bw_state);
+ if (DISPLAY_VER(i915) >= 14)
+ return mtl_find_qgv_points(i915, data_rate, num_active_planes,
+ old_bw_state, new_bw_state);
+ else
+ return icl_find_qgv_points(i915, data_rate, num_active_planes,
+ old_bw_state, new_bw_state);
}
static bool intel_bw_state_changed(struct drm_i915_private *i915,
diff --git
[Intel-gfx] [PATCH v11 5/7] drm/i915: modify max_bw to return index to intel_bw_info
MTL uses the peak BW of a QGV point to lock the required QGV
point instead of the QGV index. Instead of passing the deratedbw
of the selected bw_info, return the index to the selected
bw_info so that either deratedbw or peakbw can be used based on
the platform.
v2: use idx to store index returned by max_bw_index functions
v3: return UINT_MAX in icl_max_bw_index in case no match found
v3: check idx >= ARRAY_SIZE
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 27 -
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 56b3975f3ccb..b1cbeda0b2e3 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -593,8 +593,8 @@ static void dg2_get_bw_info(struct drm_i915_private *i915)
i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
}
-static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
- int num_planes, int qgv_point)
+static unsigned int icl_max_bw_index(struct drm_i915_private *dev_priv,
+int num_planes, int qgv_point)
{
int i;
@@ -615,14 +615,14 @@ static unsigned int icl_max_bw(struct drm_i915_private
*dev_priv,
return UINT_MAX;
if (num_planes >= bi->num_planes)
- return bi->deratedbw[qgv_point];
+ return i;
}
- return 0;
+ return UINT_MAX;
}
-static unsigned int tgl_max_bw(struct drm_i915_private *dev_priv,
- int num_planes, int qgv_point)
+static unsigned int tgl_max_bw_index(struct drm_i915_private *dev_priv,
+int num_planes, int qgv_point)
{
int i;
@@ -643,10 +643,10 @@ static unsigned int tgl_max_bw(struct drm_i915_private
*dev_priv,
return UINT_MAX;
if (num_planes <= bi->num_planes)
- return bi->deratedbw[qgv_point];
+ return i;
}
- return dev_priv->display.bw.max[0].deratedbw[qgv_point];
+ return 0;
}
static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
@@ -823,12 +823,19 @@ static int icl_find_qgv_points(struct drm_i915_private
*i915,
return ret;
for (i = 0; i < num_qgv_points; i++) {
+ unsigned int idx;
unsigned int max_data_rate;
if (DISPLAY_VER(i915) > 11)
- max_data_rate = tgl_max_bw(i915, num_active_planes, i);
+ idx = tgl_max_bw_index(i915, num_active_planes, i);
else
- max_data_rate = icl_max_bw(i915, num_active_planes, i);
+ idx = icl_max_bw_index(i915, num_active_planes, i);
+
+ if (idx >= ARRAY_SIZE(i915->display.bw.max))
+ continue;
+
+ max_data_rate = i915->display.bw.max[idx].deratedbw[i];
+
/*
* We need to know which qgv point gives us
* maximum bandwidth in order to disable SAGV
--
2.34.1
[Intel-gfx] [PATCH v11 3/7] drm/i915: store the peak bw per QGV point
In MTL onwards, pcode locks the GV point based on the peak BW
of a QGV point. So store the peak BW of all the QGV points.
v2: use DIV_ROUND_CLOSEST() for the peakBW calculation
Bspec: 64636
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 8 ++--
drivers/gpu/drm/i915/display/intel_display_core.h | 2 ++
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 61b3babf2d83..b792d307e9d5 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -534,10 +534,14 @@ static int tgl_get_bw_info(struct drm_i915_private
*dev_priv, const struct intel
bi->deratedbw[j] = min(maxdebw,
bw * (100 - sa->derating) / 100);
+ bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
+ num_channels *
+ qi.channel_width, 8);
drm_dbg_kms(_priv->drm,
- "BW%d / QGV %d: num_planes=%d
deratedbw=%u\n",
- i, j, bi->num_planes, bi->deratedbw[j]);
+ "BW%d / QGV %d: num_planes=%d deratedbw=%u
peakbw: %u\n",
+ i, j, bi->num_planes, bi->deratedbw[j],
+ bi->peakbw[j]);
}
for (j = 0; j < qi.num_psf_points; j++) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 2209811eb29e..dd8e08c8598f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -314,6 +314,8 @@ struct intel_display {
unsigned int deratedbw[I915_NUM_QGV_POINTS];
/* for each PSF GV point */
unsigned int psf_bw[I915_NUM_PSF_GV_POINTS];
+ /* Peak BW for each QGV point */
+ unsigned int peakbw[I915_NUM_QGV_POINTS];
u8 num_qgv_points;
u8 num_psf_gv_points;
u8 num_planes;
--
2.34.1
[Intel-gfx] [PATCH v11 4/7] drm/i915: extract intel_bw_check_qgv_points()
Extract intel_bw_check_qgv_points() from intel_bw_atomic_check
to facilitate future platform variations in handling SAGV
configurations.
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 235 +---
1 file changed, 130 insertions(+), 105 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index b792d307e9d5..56b3975f3ccb 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -803,6 +803,128 @@ intel_atomic_get_bw_state(struct intel_atomic_state
*state)
return to_intel_bw_state(bw_state);
}
+static int icl_find_qgv_points(struct drm_i915_private *i915,
+ unsigned int data_rate,
+ unsigned int num_active_planes,
+ const struct intel_bw_state *old_bw_state,
+ struct intel_bw_state *new_bw_state)
+{
+ unsigned int max_bw_point = 0;
+ unsigned int max_bw = 0;
+ unsigned int num_psf_gv_points =
i915->display.bw.max[0].num_psf_gv_points;
+ unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
+ u16 psf_points = 0;
+ u16 qgv_points = 0;
+ int i;
+ int ret;
+
+ ret = intel_atomic_lock_global_state(_bw_state->base);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < num_qgv_points; i++) {
+ unsigned int max_data_rate;
+
+ if (DISPLAY_VER(i915) > 11)
+ max_data_rate = tgl_max_bw(i915, num_active_planes, i);
+ else
+ max_data_rate = icl_max_bw(i915, num_active_planes, i);
+ /*
+* We need to know which qgv point gives us
+* maximum bandwidth in order to disable SAGV
+* if we find that we exceed SAGV block time
+* with watermarks. By that moment we already
+* have those, as it is calculated earlier in
+* intel_atomic_check,
+*/
+ if (max_data_rate > max_bw) {
+ max_bw_point = i;
+ max_bw = max_data_rate;
+ }
+ if (max_data_rate >= data_rate)
+ qgv_points |= BIT(i);
+
+ drm_dbg_kms(>drm, "QGV point %d: max bw %d required %d\n",
+ i, max_data_rate, data_rate);
+ }
+
+ for (i = 0; i < num_psf_gv_points; i++) {
+ unsigned int max_data_rate = adl_psf_bw(i915, i);
+
+ if (max_data_rate >= data_rate)
+ psf_points |= BIT(i);
+
+ drm_dbg_kms(>drm, "PSF GV point %d: max bw %d"
+ " required %d\n",
+ i, max_data_rate, data_rate);
+ }
+
+ /*
+* BSpec states that we always should have at least one allowed point
+* left, so if we couldn't - simply reject the configuration for obvious
+* reasons.
+*/
+ if (qgv_points == 0) {
+ drm_dbg_kms(>drm, "No QGV points provide sufficient
memory"
+ " bandwidth %d for display configuration(%d active
planes).\n",
+ data_rate, num_active_planes);
+ return -EINVAL;
+ }
+
+ if (num_psf_gv_points > 0 && psf_points == 0) {
+ drm_dbg_kms(>drm, "No PSF GV points provide sufficient
memory"
+ " bandwidth %d for display configuration(%d active
planes).\n",
+ data_rate, num_active_planes);
+ return -EINVAL;
+ }
+
+ /*
+* Leave only single point with highest bandwidth, if
+* we can't enable SAGV due to the increased memory latency it may
+* cause.
+*/
+ if (!intel_can_enable_sagv(i915, new_bw_state)) {
+ qgv_points = BIT(max_bw_point);
+ drm_dbg_kms(>drm, "No SAGV, using single QGV point %d\n",
+ max_bw_point);
+ }
+
+ /*
+* We store the ones which need to be masked as that is what PCode
+* actually accepts as a parameter.
+*/
+ new_bw_state->qgv_points_mask =
+ ~(ICL_PCODE_REQ_QGV_PT(qgv_points) |
+ ADLS_PCODE_REQ_PSF_PT(psf_points)) &
+ icl_qgv_points_mask(i915);
+
+ /*
+* If the actual mask had changed we need to make sure that
+* the commits are serialized(in case this is a nomodeset, nonblocking)
+*/
+ if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
+ ret = intel_atomic_serialize_global_state(_bw_state->base);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int
[Intel-gfx] [PATCH v11 2/7] drm/i915: update the QGV point frequency calculations
>From MTL onwwards, pcode locks the QGV point based on peak BW of the intended QGV point passed by the driver. So the peak BW calculation must match the value expected by the pcode. Update the calculations as per the Bspec. v2: use DIV_ROUND_* macro for the calculations (Ville) v3: Use only DIV_ROUN_CLOSEST and remove divisor / 2 again Bspec: 64636 Signed-off-by: Vinod Govindapillai Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_bw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index ab405c48ca3a..61b3babf2d83 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -182,7 +182,7 @@ static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv, val2 = intel_uncore_read(_priv->uncore, MTL_MEM_SS_INFO_QGV_POINT_HIGH(point)); dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); - sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000); + sp->dclk = DIV_ROUND_CLOSEST(16667 * dclk, 1000); sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val); sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val); -- 2.34.1
[Intel-gfx] [PATCH v11 1/7] drm/i915: fix the derating percentage for MTL
Follow the values from bspec for the percentage overhead for
efficiency in MTL BW calculations.
Bspec: 64631
Signed-off-by: Vinod Govindapillai
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 597d5816ad1b..ab405c48ca3a 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -379,7 +379,7 @@ static const struct intel_sa_info mtl_sa_info = {
.deburst = 32,
.deprogbwlimit = 38, /* GB/s */
.displayrtids = 256,
- .derating = 20,
+ .derating = 10,
};
static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct
intel_sa_info *sa)
--
2.34.1
[Intel-gfx] [PATCH v11 0/7] mtl: add support for pmdemand
SAGV configuration support for MTL v2: added one missing patch in the previous version v3: chekcpatch warning fixes update index handling for the icl/tgl QGV point handling program pmdemand code simplified v4: update to debufs and pipe values pmdemand regiters removed the macro usage in update_pmdemand_values V5: Addressing comments from Gustavo and Jani And some other fixes for issues from CI v6: Addressing some comments from Gustavo Updates to pmdemand state struct, active phys calculations Got rid of suppress warning patch from v5 v7: Rebased and updates to max ddiclk and active phys calculations v8: updates to active phys calcuations v9: Address styling issues v10: Updates to phys calculation, pmdemand state initialization during HW readout / sanitization v11: Fix CI checkpatch warnings Mika Kahola (1): drm/i915/mtl: Add support for PM DEMAND Vinod Govindapillai (6): drm/i915: fix the derating percentage for MTL drm/i915: update the QGV point frequency calculations drm/i915: store the peak bw per QGV point drm/i915: extract intel_bw_check_qgv_points() drm/i915: modify max_bw to return index to intel_bw_info drm/i915/mtl: find the best QGV point for the SAGV configuration drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_bw.c | 353 +++ drivers/gpu/drm/i915/display/intel_bw.h | 6 + drivers/gpu/drm/i915/display/intel_display.c | 14 + .../gpu/drm/i915/display/intel_display_core.h | 11 + .../drm/i915/display/intel_display_driver.c | 7 + .../gpu/drm/i915/display/intel_display_irq.c | 23 +- .../drm/i915/display/intel_display_power.c| 14 +- .../drm/i915/display/intel_modeset_setup.c| 18 + drivers/gpu/drm/i915/display/intel_pmdemand.c | 555 ++ drivers/gpu/drm/i915/display/intel_pmdemand.h | 56 ++ drivers/gpu/drm/i915/i915_reg.h | 36 +- 12 files changed, 971 insertions(+), 123 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h -- 2.34.1
[Intel-gfx] [PULL] drm-misc-next
Hi Dave and Daniel, here's the weekly PR for drm-misc-next. There's support for some new panels; some improvements to bridge drivers. The code around show_fdinfo can now be shared among DRM drivers. Fbdev emulation got improved file I/O code. Plus the usual fixes. Best regards Thomas drm-misc-next-2023-06-01: drm-misc-next for v6.5: UAPI Changes: Cross-subsystem Changes: * fbdev: * Add Kconfig options and initializer macros for file I/O, convert DRM fbdev emulation Core Changes: * Unify handling of struct file_operations.show_fdinfo * Use .probe in all i2c code (interface cleanup) * TTM: * Remove unused code Driver Changes: * amdgpu: * Use shared show_fdinfo code * Fix building without procfs * bridge: * display-connector: Add support for external power supply * samsung-dsim: Fix enabling; Support variable clocking * tc358767: Fixes * ti-sn65dsi83: Fix enabling * msm: * Use shared show_fdinfo code * msxfb: * Add support for i.MX93 LCDIF * panel: * Add support for Ampire AM-800480L1TMQW-T00H plus DT bindings * panel-edp: Convert .remove to return void * stm: * dsi: Use devm_ helper * ltdc: Fix potential invalid pointer deref The following changes since commit 85d712f033d23bb56a373e29465470c036532d46: Merge tag 'drm-intel-gt-next-2023-05-24' of git://anongit.freedesktop.org/drm/drm-intel into drm-next (2023-05-29 06:21:51 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2023-06-01 for you to fetch changes up to 43049f17b5262826ef64a19762a096782398ef8f: drm/i915: Implement dedicated fbdev I/O helpers (2023-06-01 12:41:40 +0200) drm-misc-next for v6.5: UAPI Changes: Cross-subsystem Changes: * fbdev: * Add Kconfig options and initializer macros for file I/O, convert DRM fbdev emulation Core Changes: * Unify handling of struct file_operations.show_fdinfo * Use .probe in all i2c code (interface cleanup) * TTM: * Remove unused code Driver Changes: * amdgpu: * Use shared show_fdinfo code * Fix building without procfs * bridge: * display-conenctor: Add support for external power supply * samsung-dsim: Fix enabling; Support variable clocking * tc358767: Fixes * ti-sn65dsi83: Fix enabling * msm: * Use shared show_fdinfo code * msxfb: * Add support for i.MX93 LCDIF * panel: * Add support for Ampire AM-800480L1TMQW-T00H plus DT bindings * panel-edp: Convert .remove to return void * stm: * dsi: Use devm_ helper * ltdc: Fix potential invalid pointer deref Adam Ford (7): drm: bridge: samsung-dsim: Fix PMS Calculator on imx8m[mnp] drm: bridge: samsung-dsim: Fetch pll-clock-frequency automatically drm: bridge: samsung-dsim: Select GENERIC_PHY_MIPI_DPHY drm: bridge: samsung-dsim: Dynamically configure DPHY timing drm: bridge: samsung-dsim: Support non-burst mode dt-bindings: bridge: samsung-dsim: Make some flags optional dt-bindings: bridge: samsung-dsim: Make some flags optional Alexander Stein (1): drm/bridge: tc358767: explicitly set readable registers Dario Binacchi (1): drm/panel: simple: fix active size for Ampire AM-480272H3TMQW-T01H Dmitry Baryshkov (3): dt-bindings: display: hdmi-connector: add hdmi-pwr supply drm/bridge: display-connector: rename dp_pwr to connector_pwr drm/bridge: display-connector: handle hdmi-pwr supply Fabio Estevam (1): dt-bindings: samsung,mipi-dsim: Use port-base reference Frieder Schrempf (2): drm: bridge: samsung-dsim: Fix i.MX8M enable flow to meet spec drm/bridge: ti-sn65dsi83: Fix enable/disable flow to meet spec Geert Uytterhoeven (2): dt-bindings: display: panel-simple: Add Ampire AM-800480L1TMQW-T00H drm/panel: simple: Add Ampire AM-800480L1TMQW-T00H Liu Ying (6): dt-bindings: lcdif: Add i.MX93 LCDIF support drm: lcdif: Drop unnecessary NULL pointer check on lcdif->bridge drm: lcdif: Determine bus format and flags in ->atomic_check() drm: lcdif: Check consistent bus format and flags across first bridges drm: lcdif: Add multiple encoders and first bridges support drm: lcdif: Add i.MX93 LCDIF compatible string Lucas Stach (1): drm: bridge: samsung-dsim: fix blanking packet size calculation Ma Jun (1): drm/ttm: Remove redundant code in ttm_tt_init_fields Neil Armstrong (1): Revert "dt-bindings: bridge: samsung-dsim: Make some flags optional" Raphael Gallais-Pou (1): drm/stm: ltdc: fix late dereference check Rob Clark (8): drm/docs: Fix usage stats typos drm: Add common fdinfo helper drm/msm: Switch to fdinfo helper drm/amdgpu: Switch to fdinfo helper drm: Add fdinfo memory stats drm/msm: Add memory stats to fdinfo drm/doc: Relax
[Intel-gfx] [PATCH V5] drm/i915/gt: Add workaround 14016712196
For mtl, workaround suggests that, SW insert a
dummy PIPE_CONTROL prior to PIPE_CONTROL which
contains a post sync: Timestamp or Write Immediate.
Bspec: 72197
V5:
- Remove ret variable - Andi
V4:
- Update commit message, avoid returing cs - Andi/Matt
V3:
- Wrap dummy pipe control stuff in API - Andi
V2:
- Fix kernel test robot warnings
Closes:
https://lore.kernel.org/oe-kbuild-all/202305121525.3ewdgoby-...@intel.com/
Reviewed-by: Andi Shyti
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 38
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index e1c76e5bfa82..23857cc08eca 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -177,14 +177,40 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32
*cs, const i915_reg_t inv
return cs;
}
+static int mtl_dummy_pipe_control(struct i915_request *rq)
+{
+ /* Wa_14016712196 */
+ if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
+ u32 *cs;
+
+ /* dummy PIPE_CONTROL + depth flush */
+ cs = intel_ring_begin(rq, 6);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+ cs = gen12_emit_pipe_control(cs,
+0,
+PIPE_CONTROL_DEPTH_CACHE_FLUSH,
+LRC_PPHWSP_SCRATCH_ADDR);
+ intel_ring_advance(rq, cs);
+ }
+
+ return 0;
+}
+
int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
{
struct intel_engine_cs *engine = rq->engine;
if (mode & EMIT_FLUSH) {
u32 flags = 0;
+ int err;
u32 *cs;
+ err = mtl_dummy_pipe_control(rq);
+ if (err)
+ return err;
+
flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
flags |= PIPE_CONTROL_FLUSH_L3;
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
@@ -217,6 +243,11 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
if (mode & EMIT_INVALIDATE) {
u32 flags = 0;
u32 *cs, count;
+ int err;
+
+ err = mtl_dummy_pipe_control(rq);
+ if (err)
+ return err;
flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
flags |= PIPE_CONTROL_TLB_INVALIDATE;
@@ -733,6 +764,13 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request
*rq, u32 *cs)
PIPE_CONTROL_DC_FLUSH_ENABLE |
PIPE_CONTROL_FLUSH_ENABLE);
+ /* Wa_14016712196 */
+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ /* dummy PIPE_CONTROL + depth flush */
+ cs = gen12_emit_pipe_control(cs, 0,
+PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
+
if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12,
50))
/* Wa_1409600907 */
flags |= PIPE_CONTROL_DEPTH_STALL;
--
2.25.1
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Use 18 fast wake AUX sync len (rev2)
== Series Details ==
Series: drm/i915: Use 18 fast wake AUX sync len (rev2)
URL : https://patchwork.freedesktop.org/series/118517/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13203_full -> Patchwork_118517v2_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 8)
--
Additional (1): shard-rkl0
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_118517v2_full:
### IGT changes ###
Possible regressions
*
{igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc_ccs}
(NEW):
- {shard-dg1}:NOTRUN -> [SKIP][1] +7 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118517v2/shard-dg1-12/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc_ccs.html
New tests
-
New tests have been introduced between CI_DRM_13203_full and
Patchwork_118517v2_full:
### New IGT tests (19) ###
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
*
igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc_ccs:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
*
igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc_ccs-cc:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-3-y:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
*
igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-3-y-rc_ccs:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
*
igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-3-y-rc_ccs-cc:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-3-y:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
*
igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-3-y-rc_ccs:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
*
igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-3-y-rc_ccs-cc:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-y:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
*
igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-y-rc_ccs:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
*
igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-y-rc_ccs-cc:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
*
igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-a-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
*
igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-b-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
*
igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
*
igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-d-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
*
igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-b-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
*
igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-c-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
*
igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-d-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_118517v2_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_close_race@multigpu-basic-process:
- shard-apl: NOTRUN -> [SKIP][2] ([fdo#109271]) +6 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118517v2/shard-apl6/igt@gem_close_r...@multigpu-basic-process.html
* igt@gem_ctx_persistence@engines-hostile:
- shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118517v2/shard-snb1/igt@gem_ctx_persiste...@engines-hostile.html
* igt@gem_lmem_swapping@massive:
- shard-glk: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118517v2/shard-glk3/igt@gem_lmem_swapp...@massive.html
* igt@gem_pwrite@basic-exhaustion:
- shard-glk: NOTRUN -> [WARN][5] ([i915#2658])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118517v2/shard-glk3/igt@gem_pwr...@basic-exhaustion.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [PASS][6] -> [ABORT][7] ([i915#5566])
[6]:
[Intel-gfx] [PATCHv2] drm/i915/display: Print useful information on error
For modifier not supporting async flip, print the modifier and display
version. Helps in reading the error message.
v2: Reframe the error message (Jani)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f51a55f4e9d0..adaba43bde2b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6012,8 +6012,9 @@ static int intel_async_flip_check_hw(struct
intel_atomic_state *state, struct in
*/
if (DISPLAY_VER(i915) < 12) {
drm_dbg_kms(>drm,
- "[PLANE:%d:%s] Modifier does not
support async flips\n",
- plane->base.base.id,
plane->base.name);
+ "[PLANE:%d:%s] Modifier 0x%llx does
not support asyn flip on display ver %d\n",
+ plane->base.base.id,
plane->base.name,
+ new_plane_state->hw.fb->modifier,
DISPLAY_VER(i915));
return -EINVAL;
}
break;
@@ -6025,8 +6026,9 @@ static int intel_async_flip_check_hw(struct
intel_atomic_state *state, struct in
break;
default:
drm_dbg_kms(>drm,
- "[PLANE:%d:%s] Modifier does not support
async flips\n",
- plane->base.base.id, plane->base.name);
+ "[PLANE:%d:%s] Modifier 0x%llx does not
support async flip\n",
+ plane->base.base.id, plane->base.name,
+ new_plane_state->hw.fb->modifier);
return -EINVAL;
}
--
2.25.1
[Intel-gfx] [PATCH v2] drm/i915/mtl: Reset only one lane in case of MFD
In case when only two or less transmit lanes are owned such as MFD
(DP-alt with x2 lanes) we need to reset only one data lane (lane0).
With only x2 lanes we don't need to poll for the phy current
status on both data lanes since only the owned data lane will respond.
v2: Find better naming for lanes and revise the commit message (Luca)
Reviewed-by: Arun R Murthy (v1)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 39
1 file changed, 23 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index ee6902118860..0600fdcd06ef 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2528,13 +2528,23 @@ static u32 intel_cx0_get_pclk_refclk_ack(u8 lane_mask)
return val;
}
-/* FIXME: Some Type-C cases need not reset both the lanes. Handle those cases.
*/
-static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, enum port
port,
+static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
+struct intel_encoder *encoder,
bool lane_reversal)
{
+ enum port port = encoder->port;
enum phy phy = intel_port_to_phy(i915, port);
+ bool both_lanes =
intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)) > 2;
u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 :
INTEL_CX0_LANE0;
+ u32 lane_pipe_reset = both_lanes ?
+ XELPDP_LANE_PIPE_RESET(0) |
+ XELPDP_LANE_PIPE_RESET(1) :
+ XELPDP_LANE_PIPE_RESET(0);
+ u32 lane_phy_current_status = both_lanes ?
+ XELPDP_LANE_PHY_CURRENT_STATUS(0) |
+ XELPDP_LANE_PHY_CURRENT_STATUS(1) :
+ XELPDP_LANE_PHY_CURRENT_STATUS(0);
if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port),
XELPDP_PORT_BUF_SOC_PHY_READY,
@@ -2545,23 +2555,24 @@ static void intel_cx0_phy_lane_reset(struct
drm_i915_private *i915, enum port po
intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1),
-XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1));
+lane_pipe_reset);
if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
-XELPDP_LANE_PHY_CURRENT_STATUS(0) |
-XELPDP_LANE_PHY_CURRENT_STATUS(1),
-XELPDP_LANE_PHY_CURRENT_STATUS(0) |
-XELPDP_LANE_PHY_CURRENT_STATUS(1),
+lane_phy_current_status,
lane_phy_current_status,
XELPDP_PORT_RESET_START_TIMEOUT_US, 0,
NULL))
drm_warn(>drm, "PHY %c failed to bring out of Lane reset
after %dus.\n",
phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
-intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES),
+intel_cx0_get_pclk_refclk_request(both_lanes ?
+ INTEL_CX0_BOTH_LANES :
+ INTEL_CX0_LANE0),
intel_cx0_get_pclk_refclk_request(lane_mask));
if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port),
-
intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES),
+
intel_cx0_get_pclk_refclk_ack(both_lanes ?
+
INTEL_CX0_BOTH_LANES :
+
INTEL_CX0_LANE0),
intel_cx0_get_pclk_refclk_ack(lane_mask),
XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0,
NULL))
drm_warn(>drm, "PHY %c failed to request refclk after
%dus.\n",
@@ -2571,13 +2582,9 @@ static void intel_cx0_phy_lane_reset(struct
drm_i915_private *i915, enum port po
CX0_P2_STATE_RESET);
intel_cx0_setup_powerdown(i915, port);
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
-XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1),
-0);
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset, 0);
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(port),
- XELPDP_LANE_PHY_CURRENT_STATUS(0) |
-
Re: [Intel-gfx] [PATCH V4] drm/i915/gt: Add workaround 14016712196
On Thu, Jun 01, 2023 at 02:45:18PM +0530, Tejas Upadhyay wrote:
> For mtl, workaround suggests that, SW insert a
> dummy PIPE_CONTROL prior to PIPE_CONTROL which
> contains a post sync: Timestamp or Write Immediate.
>
> Bspec: 72197
>
> V4:
> - Update commit message, avoid returing cs - Andi/Matt
> V3:
> - Wrap dummy pipe control stuff in API - Andi
> V2:
> - Fix kernel test robot warnings
>
> Closes:
> https://lore.kernel.org/oe-kbuild-all/202305121525.3ewdgoby-...@intel.com/
> Signed-off-by: Tejas Upadhyay
> ---
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 40
> 1 file changed, 40 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index e1c76e5bfa82..9e3d4323f36f 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -177,14 +177,42 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32
> *cs, const i915_reg_t inv
> return cs;
> }
>
> +static int mtl_dummy_pipe_control(struct i915_request *rq)
> +{
> + /* Wa_14016712196 */
> + if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
> + int ret = 0;
I think this is not needed.
> + u32 *cs;
> +
> + /* dummy PIPE_CONTROL + depth flush */
> + cs = intel_ring_begin(rq, 6);
> + ret = IS_ERR(cs);
not needed.
> + if (ret)
> + return PTR_ERR(cs);
if (IS_ERR(cs))
return PTR_ERR(cs);
with this change:
Reviewed-by: Andi Shyti
Andi
> + cs = gen12_emit_pipe_control(cs,
> + 0,
> + PIPE_CONTROL_DEPTH_CACHE_FLUSH,
> + LRC_PPHWSP_SCRATCH_ADDR);
> + intel_ring_advance(rq, cs);
> + }
> +
> + return 0;
> +}
> +
> int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> {
> struct intel_engine_cs *engine = rq->engine;
>
> if (mode & EMIT_FLUSH) {
> u32 flags = 0;
> + int err;
> u32 *cs;
>
> + err = mtl_dummy_pipe_control(rq);
> + if (err)
> + return err;
> +
> flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
> flags |= PIPE_CONTROL_FLUSH_L3;
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> @@ -217,6 +245,11 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32
> mode)
> if (mode & EMIT_INVALIDATE) {
> u32 flags = 0;
> u32 *cs, count;
> + int err;
> +
> + err = mtl_dummy_pipe_control(rq);
> + if (err)
> + return err;
>
> flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
> flags |= PIPE_CONTROL_TLB_INVALIDATE;
> @@ -733,6 +766,13 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request
> *rq, u32 *cs)
>PIPE_CONTROL_DC_FLUSH_ENABLE |
>PIPE_CONTROL_FLUSH_ENABLE);
>
> + /* Wa_14016712196 */
> + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> + /* dummy PIPE_CONTROL + depth flush */
> + cs = gen12_emit_pipe_control(cs, 0,
> + PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
> +
> if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12,
> 50))
> /* Wa_1409600907 */
> flags |= PIPE_CONTROL_DEPTH_STALL;
> --
> 2.25.1
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/display & drm/i915: more struct drm_edid conversions (rev2)
== Series Details ==
Series: drm/display & drm/i915: more struct drm_edid conversions (rev2)
URL : https://patchwork.freedesktop.org/series/116813/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13203_full -> Patchwork_116813v2_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_116813v2_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_gttfill@engines@vecs0:
- {shard-dg1}:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-dg1-16/igt@gem_exec_gttfill@engi...@vecs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v2/shard-dg1-12/igt@gem_exec_gttfill@engi...@vecs0.html
Known issues
Here are the changes found in Patchwork_116813v2_full that come from known
issues:
### CI changes ###
Issues hit
* boot:
- shard-apl: ([PASS][3], [PASS][4], [PASS][5], [PASS][6],
[PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12],
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18],
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24],
[PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30],
[PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36],
[PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42],
[PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [FAIL][48],
[PASS][49], [PASS][50], [PASS][51], [PASS][52]) ([i915#4386] / [i915#8293])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl1/boot.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl1/boot.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl2/boot.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl2/boot.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl2/boot.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl2/boot.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl3/boot.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl3/boot.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl3/boot.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl3/boot.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl4/boot.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl4/boot.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl4/boot.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl4/boot.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl4/boot.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl6/boot.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl6/boot.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl6/boot.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl6/boot.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl7/boot.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl7/boot.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl7/boot.html
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl7/boot.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl7/boot.html
[27]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/shard-apl1/boot.html
[28]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v2/shard-apl1/boot.html
[29]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v2/shard-apl1/boot.html
[30]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v2/shard-apl1/boot.html
[31]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v2/shard-apl1/boot.html
[32]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v2/shard-apl2/boot.html
[33]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v2/shard-apl2/boot.html
[34]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v2/shard-apl2/boot.html
[35]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v2/shard-apl2/boot.html
[36]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v2/shard-apl2/boot.html
[37]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116813v2/shard-apl3/boot.html
[38]:
Re: [Intel-gfx] [PATCH v5 09/13] drm/tegra: Use regular fbdev I/O helpers
On Tue, May 30, 2023 at 05:12:24PM +0200, Thomas Zimmermann wrote: > Use the regular fbdev helpers for framebuffer I/O instead of DRM's > helpers. Tegra does not use damage handling, so DRM's fbdev helpers > are mere wrappers around the fbdev code. > > By using fbdev helpers directly within each DRM fbdev emulation, > we can eventually remove DRM's wrapper functions entirely. > > v4: > * use initializer macros for struct fb_ops > v2: > * use FB_SYS_HELPERS option > > Signed-off-by: Thomas Zimmermann > Acked-by: Sam Ravnborg > Cc: Thierry Reding > Cc: Mikko Perttunen > Cc: Jonathan Hunter > --- > drivers/gpu/drm/tegra/Kconfig | 1 + > drivers/gpu/drm/tegra/fbdev.c | 8 +++- > 2 files changed, 4 insertions(+), 5 deletions(-) Acked-by: Thierry Reding signature.asc Description: PGP signature
Re: [Intel-gfx] [PATCH] drm/i915/display: Print usefull information on error
On Thu, 01 Jun 2023, Arun R Murthy wrote:
> For modifier not supporting async flip, print the modifier and display
> version. Helps in reading the error message.
>
> Signed-off-by: Arun R Murthy
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 10 ++
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f51a55f4e9d0..0877f1e251a0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6012,8 +6012,9 @@ static int intel_async_flip_check_hw(struct
> intel_atomic_state *state, struct in
>*/
> if (DISPLAY_VER(i915) < 12) {
> drm_dbg_kms(>drm,
> - "[PLANE:%d:%s] Modifier does not
> support async flips\n",
> - plane->base.base.id,
> plane->base.name);
> + "[PLANE:%d:%s] Asyn flip on
> modifier 0x%llx not supported on Display Ver %d\n",
How about:
"Modifier 0x%llx does not support async flips on display ver %d\n"
> + plane->base.base.id,
> plane->base.name,
> + new_plane_state->hw.fb->modifier,
> DISPLAY_VER(i915));
> return -EINVAL;
> }
> break;
> @@ -6025,8 +6026,9 @@ static int intel_async_flip_check_hw(struct
> intel_atomic_state *state, struct in
> break;
> default:
> drm_dbg_kms(>drm,
> - "[PLANE:%d:%s] Modifier does not support
> async flips\n",
> - plane->base.base.id, plane->base.name);
> + "[PLANE:%d:%s] Unknown modifier 0x%llx !
> async flip not supported\n",
It's not unknown, it just doesn't support async flips? Why the
exclamation mark?
How about:
"Modifier 0x%llx does not support async flips\n"
> + plane->base.base.id, plane->base.name,
> + new_plane_state->hw.fb->modifier);
> return -EINVAL;
> }
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH V4] drm/i915/gt: Add workaround 14016712196
For mtl, workaround suggests that, SW insert a
dummy PIPE_CONTROL prior to PIPE_CONTROL which
contains a post sync: Timestamp or Write Immediate.
Bspec: 72197
V4:
- Update commit message, avoid returing cs - Andi/Matt
V3:
- Wrap dummy pipe control stuff in API - Andi
V2:
- Fix kernel test robot warnings
Closes:
https://lore.kernel.org/oe-kbuild-all/202305121525.3ewdgoby-...@intel.com/
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 40
1 file changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index e1c76e5bfa82..9e3d4323f36f 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -177,14 +177,42 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32
*cs, const i915_reg_t inv
return cs;
}
+static int mtl_dummy_pipe_control(struct i915_request *rq)
+{
+ /* Wa_14016712196 */
+ if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
+ int ret = 0;
+ u32 *cs;
+
+ /* dummy PIPE_CONTROL + depth flush */
+ cs = intel_ring_begin(rq, 6);
+ ret = IS_ERR(cs);
+ if (ret)
+ return PTR_ERR(cs);
+ cs = gen12_emit_pipe_control(cs,
+0,
+PIPE_CONTROL_DEPTH_CACHE_FLUSH,
+LRC_PPHWSP_SCRATCH_ADDR);
+ intel_ring_advance(rq, cs);
+ }
+
+ return 0;
+}
+
int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
{
struct intel_engine_cs *engine = rq->engine;
if (mode & EMIT_FLUSH) {
u32 flags = 0;
+ int err;
u32 *cs;
+ err = mtl_dummy_pipe_control(rq);
+ if (err)
+ return err;
+
flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
flags |= PIPE_CONTROL_FLUSH_L3;
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
@@ -217,6 +245,11 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
if (mode & EMIT_INVALIDATE) {
u32 flags = 0;
u32 *cs, count;
+ int err;
+
+ err = mtl_dummy_pipe_control(rq);
+ if (err)
+ return err;
flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
flags |= PIPE_CONTROL_TLB_INVALIDATE;
@@ -733,6 +766,13 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request
*rq, u32 *cs)
PIPE_CONTROL_DC_FLUSH_ENABLE |
PIPE_CONTROL_FLUSH_ENABLE);
+ /* Wa_14016712196 */
+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ /* dummy PIPE_CONTROL + depth flush */
+ cs = gen12_emit_pipe_control(cs, 0,
+PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
+
if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12,
50))
/* Wa_1409600907 */
flags |= PIPE_CONTROL_DEPTH_STALL;
--
2.25.1
[Intel-gfx] [PATCH] drm/i915/display: pre-initialize some values in probe_gmdid_display()
When intel_display_device_probe() (and, subsequently,
probe_gmdid_display()) returns, the caller expects ver, rel and step
to be initialized. Since there's no way to check that there was a
failure and no_display was returned without some further refactoring,
pre-initiliaze all these values to zero to keep it simple and safe.
Signed-off-by: Luca Coelho
---
drivers/gpu/drm/i915/display/intel_display_device.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index 464df1764a86..fb6354e9e704 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -731,6 +731,15 @@ probe_gmdid_display(struct drm_i915_private *i915, u16
*ver, u16 *rel, u16 *step
u32 val;
int i;
+ /* The caller expects to ver, rel and step to be initialized
+* here, and there's no good way to check when there was a
+* failure and no_display was returned. So initialize all these
+* values here zero, to be sure.
+*/
+ *ver = 0;
+ *rel = 0;
+ *step = 0;
+
addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY),
sizeof(u32));
if (!addr) {
drm_err(>drm, "Cannot map MMIO BAR to read display
GMD_ID\n");
--
2.39.2
[Intel-gfx] ✓ Fi.CI.IGT: success for Do not access i915_gem_object members from frontbuffer tracking (rev2)
== Series Details == Series: Do not access i915_gem_object members from frontbuffer tracking (rev2) URL : https://patchwork.freedesktop.org/series/118475/ State : success == Summary == CI Bug Log - changes from CI_DRM_13202_full -> Patchwork_118475v2_full Summary --- **SUCCESS** No regressions found. Participating hosts (7 -> 7) -- No changes in participating hosts New tests - New tests have been introduced between CI_DRM_13202_full and Patchwork_118475v2_full: ### New IGT tests (1) ### * igt@kms_flip@flip-vs-panning-vs-hang@b-hdmi-a1: - Statuses : 1 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_118475v2_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_fair@basic-deadline: - shard-glk: [PASS][1] -> [FAIL][2] ([i915#2846]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13202/shard-glk3/igt@gem_exec_f...@basic-deadline.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118475v2/shard-glk6/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-apl: [PASS][3] -> [FAIL][4] ([i915#2842]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13202/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118475v2/shard-apl7/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][5] -> [FAIL][6] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13202/shard-glk4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118475v2/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_lmem_swapping@verify-ccs: - shard-glk: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118475v2/shard-glk8/igt@gem_lmem_swapp...@verify-ccs.html * igt@i915_pm_rps@reset: - shard-snb: [PASS][8] -> [INCOMPLETE][9] ([i915#7790]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13202/shard-snb4/igt@i915_pm_...@reset.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118475v2/shard-snb2/igt@i915_pm_...@reset.html * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs: - shard-glk: NOTRUN -> [SKIP][10] ([fdo#109271]) +16 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118475v2/shard-glk8/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs.html * igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs: - shard-glk: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#3886]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118475v2/shard-glk8/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-glk: [PASS][12] -> [FAIL][13] ([i915#2346]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13202/shard-glk4/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118475v2/shard-glk1/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2: - shard-glk: [PASS][14] -> [FAIL][15] ([i915#79]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13202/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-hdmi-a2.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118475v2/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-hdmi-a2.html * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode: - shard-glk: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4579]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118475v2/shard-glk3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscal...@pipe-a-valid-mode.html * igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-b-hdmi-a-1: - shard-snb: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4579]) +16 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118475v2/shard-snb1/igt@kms_plane_scaling@plane-upscale-with-modifiers-20...@pipe-b-hdmi-a-1.html * igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1: - shard-snb: NOTRUN -> [SKIP][18] ([fdo#109271]) +19 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118475v2/shard-snb7/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0...@pipe-a-vga-1.html * igt@kms_setmode@basic@pipe-a-hdmi-a-1: - shard-snb: NOTRUN -> [FAIL][19] ([i915#5465]) +1 similar issue [19]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Use 18 fast wake fast wake AUX sync len
== Series Details == Series: drm/i915: Use 18 fast wake fast wake AUX sync len URL : https://patchwork.freedesktop.org/series/118504/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13202_full -> Patchwork_118504v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_118504v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_118504v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (7 -> 7) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_118504v1_full: ### IGT changes ### Possible regressions * igt@runner@aborted: - shard-apl: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118504v1/shard-apl7/igt@run...@aborted.html New tests - New tests have been introduced between CI_DRM_13202_full and Patchwork_118504v1_full: ### New IGT tests (1) ### * igt@kms_flip@flip-vs-panning-vs-hang@b-hdmi-a1: - Statuses : 1 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_118504v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_lmem_swapping@massive: - shard-glk: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118504v1/shard-glk7/igt@gem_lmem_swapp...@massive.html * igt@gem_pwrite@basic-exhaustion: - shard-glk: NOTRUN -> [WARN][3] ([i915#2658]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118504v1/shard-glk7/igt@gem_pwr...@basic-exhaustion.html * igt@gen9_exec_parse@allowed-single: - shard-apl: [PASS][4] -> [ABORT][5] ([i915#5566]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13202/shard-apl2/igt@gen9_exec_pa...@allowed-single.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118504v1/shard-apl3/igt@gen9_exec_pa...@allowed-single.html - shard-glk: [PASS][6] -> [ABORT][7] ([i915#5566]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13202/shard-glk8/igt@gen9_exec_pa...@allowed-single.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118504v1/shard-glk9/igt@gen9_exec_pa...@allowed-single.html * igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs: - shard-glk: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#3886]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118504v1/shard-glk7/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-glk: [PASS][9] -> [FAIL][10] ([i915#2346]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13202/shard-glk4/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118504v1/shard-glk4/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html * igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#79]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13202/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vbl...@ab-hdmi-a1-hdmi-a2.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118504v1/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vbl...@ab-hdmi-a1-hdmi-a2.html * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode: - shard-glk: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4579]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118504v1/shard-glk7/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscal...@pipe-a-valid-mode.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-wc: - shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271]) +43 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118504v1/shard-glk7/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-indfb-draw-mmap-wc.html * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-1: - shard-snb: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4579]) +14 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118504v1/shard-snb1/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotat...@pipe-b-hdmi-a-1.html * igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1: - shard-snb: NOTRUN -> [SKIP][16] ([fdo#109271]) +20 similar issues [16]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Print usefull information on error
== Series Details ==
Series: drm/i915/display: Print usefull information on error
URL : https://patchwork.freedesktop.org/series/118685/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13210 -> Patchwork_118685v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v1/index.html
Participating hosts (37 -> 36)
--
Missing(1): bat-rpls-2
Known issues
Here are the changes found in Patchwork_118685v1 that come from known issues:
### CI changes ###
Possible fixes
* boot:
- fi-kbl-8809g: [FAIL][1] ([i915#8293] / [i915#8298]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/fi-kbl-8809g/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v1/fi-kbl-8809g/boot.html
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-kbl-8809g: NOTRUN -> [ABORT][3] ([i915#8298] / [i915#8299] /
[i915#8397])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v1/fi-kbl-8809g/igt@core_hotunp...@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@i915_selftest@live@hangcheck:
- bat-dg2-9: [PASS][5] -> [DMESG-FAIL][6] ([i915#6998] /
[i915#7913])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/bat-dg2-9/igt@i915_selftest@l...@hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v1/bat-dg2-9/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@migrate:
- bat-dg2-11: [PASS][7] -> [DMESG-WARN][8] ([i915#7699])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/bat-dg2-11/igt@i915_selftest@l...@migrate.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html
* igt@kms_addfb_basic@too-high:
- fi-kbl-8809g: NOTRUN -> [FAIL][9] ([i915#8296]) +2 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v1/fi-kbl-8809g/igt@kms_addfb_ba...@too-high.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-8809g: NOTRUN -> [DMESG-FAIL][10] ([i915#8299])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v1/fi-kbl-8809g/igt@kms_force_connector_ba...@force-connector-state.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-8809g: NOTRUN -> [CRASH][11] ([i915#8299])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v1/fi-kbl-8809g/igt@kms_force_connector_ba...@force-edid.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-adlp-9: NOTRUN -> [SKIP][12] ([i915#3546]) +1 similar issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v1/bat-adlp-9/igt@kms_pipe_crc_ba...@read-crc.html
* igt@kms_psr@cursor_plane_move:
- fi-kbl-8809g: NOTRUN -> [SKIP][13] ([fdo#109271]) +59 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v1/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-kbl-8809g: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4579])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v1/fi-kbl-8809g/igt@kms_setm...@basic-clone-single-crtc.html
Possible fixes
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [DMESG-WARN][15] ([i915#6367]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/bat-rpls-1/igt@i915_selftest@l...@slpc.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118685v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6998]: https://gitlab.freedesktop.org/drm/intel/issues/6998
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8189]: https://gitlab.freedesktop.org/drm/intel/issues/8189
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8296]: https://gitlab.freedesktop.org/drm/intel/issues/8296
