[Intel-gfx] [PATCH] drm/i915: Add intel_pcode_probe
Added intel_pcode_probe, promoted wait for lmem init and
intel_pcode_init prior to mmio_probe during load,
so that GT registers can be accessed only after this, else MCA
is observed.
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_driver.c | 37 -
drivers/gpu/drm/i915/intel_uncore.c | 12 --
2 files changed, 31 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index f8dbee7a5af7..92cafceaf447 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -93,6 +93,7 @@
#include "i915_memcpy.h"
#include "i915_perf.h"
#include "i915_query.h"
+#include "i915_reg.h"
#include "i915_suspend.h"
#include "i915_switcheroo.h"
#include "i915_sysfs.h"
@@ -436,6 +437,32 @@ static int i915_pcode_init(struct drm_i915_private *i915)
return 0;
}
+static int intel_pcode_probe(struct drm_i915_private *i915)
+{
+ struct intel_uncore *uncore;
+ int ret;
+
+ /*
+* The boot firmware initializes local memory and assesses its health.
+* If memory training fails, the punit will have been instructed to
+* keep the GT powered down; we won't be able to communicate with it
+* and we should not continue with driver initialization.
+*/
+ if (IS_DGFX(i915) &&
+ !(__raw_uncore_read32(uncore, GU_CNTL) & LMEM_INIT)) {
+ drm_err(>drm, "LMEM not initialized by firmware\n");
+ return -ENODEV;
+ }
+
+ /*
+* Driver handshakes with pcode via mailbox command to know that SoC
+* initialization is complete before proceeding further
+*/
+ ret = i915_pcode_init(i915);
+
+ return ret;
+}
+
/**
* i915_driver_hw_probe - setup state requiring device access
* @dev_priv: device private
@@ -547,10 +574,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
intel_opregion_setup(dev_priv);
- ret = i915_pcode_init(dev_priv);
- if (ret)
- goto err_opregion;
-
/*
* Fill the dram structure to get the system dram info. This will be
* used for memory latency calculation.
@@ -561,8 +584,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
return 0;
-err_opregion:
- intel_opregion_cleanup(dev_priv);
err_msi:
if (pdev->msi_enabled)
pci_disable_msi(pdev);
@@ -778,6 +799,10 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (ret < 0)
goto out_runtime_pm_put;
+ ret = intel_pcode_probe(i915);
+ if (ret)
+ goto out_tiles_cleanup;
+
ret = i915_driver_mmio_probe(i915);
if (ret < 0)
goto out_tiles_cleanup;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index dfefad5a5fec..4a353d4adf86 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2658,18 +2658,6 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
if (ret)
return ret;
- /*
-* The boot firmware initializes local memory and assesses its health.
-* If memory training fails, the punit will have been instructed to
-* keep the GT powered down; we won't be able to communicate with it
-* and we should not continue with driver initialization.
-*/
- if (IS_DGFX(i915) &&
- !(__raw_uncore_read32(uncore, GU_CNTL) & LMEM_INIT)) {
- drm_err(>drm, "LMEM not initialized by firmware\n");
- return -ENODEV;
- }
-
if (GRAPHICS_VER(i915) > 5 && !intel_vgpu_active(i915))
uncore->flags |= UNCORE_HAS_FORCEWAKE;
--
2.41.0
[Intel-gfx] [PATCH v2] drm/i915/gt: Add sysfs RAPL PL1 interface
Adding sysfs attribute rapl_pl1_freq_mhz. This shows the RAPL PL1
FREQUENCY LIMIT.
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 15 +++
drivers/gpu/drm/i915/gt/intel_rps.c | 18 ++
drivers/gpu/drm/i915/gt/intel_rps.h | 1 +
4 files changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 7fa18a3b3957..1c78fc89a37a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1656,6 +1656,10 @@
#define GT0_PACKAGE_POWER_SKU_UNIT _MMIO(0x250068)
#define GT0_PLATFORM_ENERGY_STATUS _MMIO(0x25006c)
+#define XEHPSDV_RAPL_PL1_FREQ_LIMIT_MMIO(0x250070)
+#define MTL_RAPL_PL1_FREQ_LIMIT_MMIO(0x281070)
+#define RAPL_PL1_FREQ_LIMIT_MASK REG_GENMASK(15, 0)
+
/*
* Standalone Media's non-engine GT registers are located at their regular GT
* offsets plus 0x38. This extra offset is stored inside the intel_uncore
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 28f27091cd3b..0b52962e2856 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -451,6 +451,16 @@ static ssize_t punit_req_freq_mhz_show(struct kobject
*kobj,
return sysfs_emit(buff, "%u\n", preq);
}
+static ssize_t rapl_pl1_freq_mhz_show(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ char *buff)
+{
+ struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
+ u32 rapl_pl1 = intel_rps_read_rapl_pl1(>rps);
+
+ return sysfs_emit(buff, "%u\n", rapl_pl1);
+}
+
struct intel_gt_bool_throttle_attr {
struct attribute attr;
ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
@@ -480,6 +490,7 @@ struct intel_gt_bool_throttle_attr attr_##sysfs_func__ = { \
}
INTEL_GT_ATTR_RO(punit_req_freq_mhz);
+INTEL_GT_ATTR_RO(rapl_pl1_freq_mhz);
static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_status,
GT0_PERF_LIMIT_REASONS_MASK);
static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl1, POWER_LIMIT_1_MASK);
static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl2, POWER_LIMIT_2_MASK);
@@ -744,6 +755,10 @@ void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct
kobject *kobj)
if (ret)
gt_warn(gt, "failed to create punit_req_freq_mhz sysfs (%pe)",
ERR_PTR(ret));
+ ret = sysfs_create_file(kobj, _rapl_pl1_freq_mhz.attr);
+ if (ret)
+ gt_warn(gt, "failed to create rapl_pl1_freq_mhz sysfs (%pe)",
ERR_PTR(ret));
+
if (i915_mmio_reg_valid(intel_gt_perf_limit_reasons_reg(gt))) {
ret = sysfs_create_files(kobj, throttle_reason_attrs);
if (ret)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index f5d7b5126433..f66d6f47f2cf 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2202,6 +2202,24 @@ u32 intel_rps_get_max_frequency(struct intel_rps *rps)
return intel_gpu_freq(rps, rps->max_freq_softlimit);
}
+u32 intel_rps_read_rapl_pl1(struct intel_rps *rps)
+{
+ struct drm_i915_private *i915 = rps_to_i915(rps);
+ u32 rapl_pl1;
+ u32 rapl;
+
+ if (IS_METEORLAKE(i915))
+ rapl_pl1 = intel_uncore_read(rps_to_gt(rps)->uncore,
MTL_RAPL_PL1_FREQ_LIMIT);
+ else if (IS_XEHPSDV(i915))
+ rapl_pl1 = intel_uncore_read(rps_to_gt(rps)->uncore,
XEHPSDV_RAPL_PL1_FREQ_LIMIT);
+
+
+ if (IS_METEORLAKE(i915) || IS_XEHPSDV(i915))
+ rapl = REG_FIELD_GET(RAPL_PL1_FREQ_LIMIT_MASK, rapl_pl1);
+
+ return rapl;
+}
+
/**
* intel_rps_get_max_raw_freq - returns the max frequency in some raw format.
* @rps: the intel_rps structure
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h
b/drivers/gpu/drm/i915/gt/intel_rps.h
index c622962c6bef..c37d297c9d82 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -51,6 +51,7 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps);
u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);
u32 intel_rps_read_punit_req(struct intel_rps *rps);
u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
+u32 intel_rps_read_rapl_pl1(struct intel_rps *rps);
u32 intel_rps_read_rpstat(struct intel_rps *rps);
u32 intel_rps_read_rpstat_fw(struct intel_rps *rps);
void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps
*caps);
--
2.34.1
[Intel-gfx] [PATCH v1] drm/i915/gt: Add sysfs RAPL PL1 interface
Adding the rapl_pl1_freq_mhz sysfs attribute.
Signed-off-by: Sujaritha Sundaresan
Cc: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 20 ++
drivers/gpu/drm/i915/gt/intel_rps.c | 44 +
drivers/gpu/drm/i915/gt/intel_rps.h | 3 ++
drivers/gpu/drm/i915/i915_reg.h | 4 ++
4 files changed, 71 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 904160952369..e7f00ec252f8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -496,6 +496,17 @@ static DEVICE_ATTR_RO(vlv_rpe_freq_mhz);
static const struct attribute * const gen6_rps_attrs[] = GEN6_RPS_ATTR;
static const struct attribute * const gen6_gt_attrs[] = GEN6_GT_ATTR;
+static ssize_t rapl_pl1_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buff)
+{
+ struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+ u32 rapl_pl1 = intel_rps_read_rapl_pl1_frequency(>rps);
+
+ return sysfs_emit(buff, "%u\n", rapl_pl1);
+}
+
+
static ssize_t punit_req_freq_mhz_show(struct device *dev,
struct device_attribute *attr,
char *buff)
@@ -534,6 +545,7 @@ struct intel_gt_bool_throttle_attr attr_##sysfs_func__ = { \
.mask = mask__, \
}
+static DEVICE_ATTR_RO(rapl_pl1_freq_mhz);
static DEVICE_ATTR_RO(punit_req_freq_mhz);
static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_status,
GT0_PERF_LIMIT_REASONS_MASK);
static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl1, POWER_LIMIT_1_MASK);
@@ -790,12 +802,20 @@ void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct
kobject *kobj)
if (!is_object_gt(kobj))
return;
+ ret = sysfs_create_file(kobj, _attr_rapl_pl1_freq_mhz.attr);
+ if (ret)
+ drm_warn(>i915->drm,
+ "failed to create gt%u rapl_pl1_freq_mhz sysfs(%pe)",
+ gt->info.id, ERR_PTR(ret));
+
+
ret = sysfs_create_file(kobj, _attr_punit_req_freq_mhz.attr);
if (ret)
drm_warn(>i915->drm,
"failed to create gt%u punit_req_freq_mhz sysfs (%pe)",
gt->info.id, ERR_PTR(ret));
+
if (i915_mmio_reg_valid(intel_gt_perf_limit_reasons_reg(gt))) {
ret = sysfs_create_files(kobj, throttle_reason_attrs);
if (ret)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 17b40b625e31..0e89b941e3be 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -9,6 +9,7 @@
#include "i915_drv.h"
#include "i915_irq.h"
+#include "i915_reg.h"
#include "intel_breadcrumbs.h"
#include "intel_gt.h"
#include "intel_gt_clock_utils.h"
@@ -2422,6 +2423,49 @@ bool rps_read_mask_mmio(struct intel_rps *rps,
return rps_read_mmio(rps, reg32) & mask;
}
+u32 intel_rps_read_rapl_pl1(struct intel_rps *rps)
+{
+ struct drm_i915_private *i915 = rps_to_i915(rps);
+ i915_reg_t rgadr;
+ u32 rapl_pl1;
+
+ if (IS_METEORLAKE(i915)) {
+ rgadr = MTL_RAPL_PL1_FREQ_LIMIT;
+ } else if (IS_XEHPSDV(i915)) {
+ rgadr = XEHPSDV_RAPL_PL1_FREQ_LIMIT;
+ } else {
+ MISSING_CASE(GRAPHICS_VER(i915));
+ rgadr = INVALID_MMIO_REG;
+ }
+
+ if (!i915_mmio_reg_valid(rgadr))
+ rapl_pl1 = 0;
+ else
+ rapl_pl1 = rps_read_mmio(rps, rgadr);
+
+ return rapl_pl1;
+}
+
+u32 intel_rps_get_rapl(struct intel_rps *rps, u32 rapl_pl1)
+{
+ struct drm_i915_private *i915 = rps_to_i915(rps);
+ u32 rapl = 0;
+
+ if (IS_METEORLAKE(i915) || IS_XEHPSDV(i915))
+ rapl = rapl_pl1 & RAPL_PL1_FREQ_LIMIT_MASK;
+ else
+ MISSING_CASE(GRAPHICS_VER(i915));
+
+ return rapl;
+}
+
+u32 intel_rps_read_rapl_pl1_frequency(struct intel_rps *rps)
+{
+ u32 rapl_freq = intel_rps_get_rapl(rps, intel_rps_read_rapl_pl1(rps));
+
+ return (rapl_freq >> 8) * GT_FREQUENCY_MULTIPLIER;
+}
+
/* External interface for intel_ips.ko */
static struct drm_i915_private __rcu *ips_mchdev;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h
b/drivers/gpu/drm/i915/gt/intel_rps.h
index 4509dfdc52e0..4adc6aaedba0 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -34,6 +34,7 @@ void intel_rps_mark_interactive(struct intel_rps *rps, bool
interactive);
int intel_gpu_freq(struct intel_rps *rps, int val);
int intel_freq_opcode(struct intel_rps *rps, int val);
u32 intel_rps_get_cagf(struct intel_rps *rps, u
[Intel-gfx] [PATCH 1/1] RFC : drm/i915: Adding new sysfs frequency attributes
This patch adds the following new sysfs frequency attributes;
- punit_req_freq_mhz
- throttle_reason_status
- throttle_reason_pl1
- throttle_reason_pl2
- throttle_reason_pl4
- throttle_reason_thermal
- throttle_reason_prochot
- throttle_reason_ratl
- throttle_reason_vr_thermalert
- throttle_reason_vr_tdc
Signed-off-by: Sujaritha Sundaresan
Cc: Dale B Stimson
---
drivers/gpu/drm/i915/gt/intel_rps.c | 83 +
drivers/gpu/drm/i915/gt/intel_rps.h | 10 +++
drivers/gpu/drm/i915/i915_reg.h | 11 +++
drivers/gpu/drm/i915/i915_sysfs.c | 135
4 files changed, 239 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 172de6c9f949..c03d99f2608c 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2153,6 +2153,89 @@ u32 intel_rps_read_state_cap(struct intel_rps *rps)
return intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
}
+static u32 __rps_read_mmio(struct intel_gt *gt, i915_reg_t reg32)
+{
+ intel_wakeref_t wakeref;
+ u32 val;
+
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ val = intel_uncore_read(gt->uncore, reg32);
+
+ return val;
+}
+
+u32 intel_rps_read_throttle_reason_status(struct intel_rps *rps)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ u32 status = __rps_read_mmio(gt, GT0_PERF_LIMIT_REASONS) &
GT0_PERF_LIMIT_REASONS_MASK;
+
+ return status;
+}
+
+u32 intel_rps_read_throttle_reason_pl1(struct intel_rps *rps)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ u32 pl1 = __rps_read_mmio(gt, GT0_PERF_LIMIT_REASONS) &
POWER_LIMIT_1_MASK;
+
+ return pl1;
+}
+
+u32 intel_rps_read_throttle_reason_pl2(struct intel_rps *rps)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ u32 pl2 = __rps_read_mmio(gt, GT0_PERF_LIMIT_REASONS) &
POWER_LIMIT_2_MASK;
+
+ return pl2;
+}
+
+u32 intel_rps_read_throttle_reason_pl4(struct intel_rps *rps)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ u32 pl4 = __rps_read_mmio(gt, GT0_PERF_LIMIT_REASONS) &
POWER_LIMIT_4_MASK;
+
+ return pl4;
+}
+
+u32 intel_rps_read_throttle_reason_thermal(struct intel_rps *rps)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ u32 thermal = __rps_read_mmio(gt, GT0_PERF_LIMIT_REASONS) &
THERMAL_LIMIT_MASK;
+
+ return thermal;
+}
+
+u32 intel_rps_read_throttle_reason_prochot(struct intel_rps *rps)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ u32 prochot = __rps_read_mmio(gt, GT0_PERF_LIMIT_REASONS) &
PROCHOT_MASK;
+
+ return prochot;
+}
+
+u32 intel_rps_read_throttle_reason_ratl(struct intel_rps *rps)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ u32 ratl = __rps_read_mmio(gt, GT0_PERF_LIMIT_REASONS) & RATL_MASK;
+
+ return ratl;
+}
+
+u32 intel_rps_read_throttle_reason_vr_thermalert(struct intel_rps *rps)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ u32 thermalert = __rps_read_mmio(gt, GT0_PERF_LIMIT_REASONS) &
VR_THERMALERT_MASK;
+
+ return thermalert;
+}
+
+u32 intel_rps_read_throttle_reason_vr_tdc(struct intel_rps *rps)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ u32 tdc = __rps_read_mmio(gt, GT0_PERF_LIMIT_REASONS) & VR_TDC_MASK;
+
+ return tdc;
+}
+
/* External interface for intel_ips.ko */
static struct drm_i915_private __rcu *ips_mchdev;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h
b/drivers/gpu/drm/i915/gt/intel_rps.h
index 11960d64ca82..d6ac97f1facd 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -42,6 +42,16 @@ u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);
u32 intel_rps_read_punit_req(struct intel_rps *rps);
u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
u32 intel_rps_read_state_cap(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason_status(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason_pl1(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason_pl2(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason_pl4(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason_thermal(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason_prochot(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason_ratl(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason_vr_thermalert(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason_vr_tdc(struct intel_rps *rps);
void gen5_rps_irq_handler(struct intel_rps *rps);
void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a897f4abea0c..9ac322269d49 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4152,6 +4152
[Intel-gfx] [PATCH v2] drm/i915/guc: GuC suspend path cleanup
Adding a call to intel_uc_suspend in i915_gem_suspend, which is a common point for the suspend/resume and hibernate paths. This fixes an unbalanced call that causes issues with the CTB register/deregister. v2: Making the call unconditional (Daniele) Moving the call to after the GEM_BUG_ON (Chris) Cc: Daniele Ceraolo Spurio Cc: Chris Wilson Cc: Michal Wajdeczko Signed-off-by: Sujaritha Sundaresan --- drivers/gpu/drm/i915/i915_gem.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 1a684b7e8c09..8e8b79711a31 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4388,6 +4388,8 @@ void i915_gem_suspend(struct drm_i915_private *i915) */ GEM_BUG_ON(i915->gt.awake); + intel_uc_suspend(i915); + intel_runtime_pm_put(i915, wakeref); } -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/guc: GuC suspend path cleanup
Adding a call to intel_uc_suspend in i915_gem_suspend, which is a common point for the suspend/resume and hibernate paths. This fixes an unbalanced call that causes issues with the CTB register/deregister. Cc: Daniele Ceraolo Spurio Cc: Chris Wilson Cc: Michal Wajdeczko Signed-off-by: Sujaritha Sundaresan --- drivers/gpu/drm/i915/i915_gem.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 1a684b7e8c09..980855ebdeda 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4371,6 +4371,9 @@ void i915_gem_suspend(struct drm_i915_private *i915) */ switch_to_kernel_context_sync(i915, i915->gt.active_engines); + if (!__i915_wedged(>gpu_error)) + intel_uc_suspend(i915); + mutex_unlock(>drm.struct_mutex); i915_reset_flush(i915); -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/1] drm/i915/guc: Preparing for GuC reset along with engine reset
Adding the call to prepare for guc reset along with engine reset. intel_uc_reset_prepare() calls to disable guc communication and to sanitize. Cc: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Signed-off-by: Sujaritha Sundaresan --- drivers/gpu/drm/i915/i915_reset.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c index 3fbaa72a9eac..dcaa33b72636 100644 --- a/drivers/gpu/drm/i915/i915_reset.c +++ b/drivers/gpu/drm/i915/i915_reset.c @@ -820,6 +820,8 @@ static void __i915_gem_set_wedged(struct drm_i915_private *i915) for_each_engine(engine, i915, id) reset_prepare_engine(engine); + intel_uc_reset_prepare(i915); + /* Even if the GPU reset fails, it should still stop the engines */ if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) intel_gpu_reset(i915, ALL_ENGINES); -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/guc: Fixing error code for WOPCM initialization
Replacing the -E2BIG error code return for WOPCM
initialization with -ENODEV. This will prevent the pci from
picking this up as a warning during fault injection testing.
v2: change the final return code in i915_pci_probe() to ENODEV
instead of the specific wopcm change. - Daniele
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c42c5ccf38fe..f962b5c0b3c1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -778,7 +778,7 @@ static int i915_pci_probe(struct pci_dev *pdev, const
struct pci_device_id *ent)
err = i915_driver_load(pdev, ent);
if (err)
- return err;
+ return i915_error_injected() ? -ENODEV : err;
if (i915_inject_load_failure()) {
i915_pci_remove(pdev);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/1] drm/i915: Fixing error code for WOPCM initialization
Replacing the -E2BIG error code return for WOPCM
initialization with -ENODEV. This will prevent the pci from
picking this up as a warning during fault injection testing.
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/intel_wopcm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
b/drivers/gpu/drm/i915/intel_wopcm.c
index f82a415ea2ba..a651557e6e4e 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -169,7 +169,7 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
GEM_BUG_ON(!wopcm->size);
if (i915_inject_load_failure())
- return -E2BIG;
+ return -ENODEV;
if (guc_fw_size >= wopcm->size) {
DRM_ERROR("GuC FW (%uKiB) is too big to fit in WOPCM.",
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 1/2] drm/i915/guc: Splitting CT channel open/close functions
The aim of this patch is to allow enabling and disabling
of CTB without requiring the mutex lock.
v2: Phasing out ctch_is_enabled function and replacing it with
ctch->enabled (Daniele)
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/intel_guc.c| 12
drivers/gpu/drm/i915/intel_guc_ct.c | 90 +
drivers/gpu/drm/i915/intel_guc_ct.h | 3 +
3 files changed, 80 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 8660af3fd755..a4e1fc6b9eee 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -203,11 +203,19 @@ int intel_guc_init(struct intel_guc *guc)
goto err_log;
GEM_BUG_ON(!guc->ads_vma);
+ if (HAS_GUC_CT(dev_priv)) {
+ ret = intel_guc_ct_init(>ct);
+ if (ret)
+ goto err_ads;
+ }
+
/* We need to notify the guc whenever we change the GGTT */
i915_ggtt_enable_guc(dev_priv);
return 0;
+err_ads:
+ intel_guc_ads_destroy(guc);
err_log:
intel_guc_log_destroy(>log);
err_shared:
@@ -222,6 +230,10 @@ void intel_guc_fini(struct intel_guc *guc)
struct drm_i915_private *dev_priv = guc_to_i915(guc);
i915_ggtt_disable_guc(dev_priv);
+
+ if (HAS_GUC_CT(dev_priv))
+ intel_guc_ct_fini(>ct);
+
intel_guc_ads_destroy(guc);
intel_guc_log_destroy(>log);
guc_shared_data_destroy(guc);
diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c
b/drivers/gpu/drm/i915/intel_guc_ct.c
index a52883e9146f..b8d57f01d8e4 100644
--- a/drivers/gpu/drm/i915/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/intel_guc_ct.c
@@ -140,11 +140,6 @@ static int guc_action_deregister_ct_buffer(struct
intel_guc *guc,
return err;
}
-static bool ctch_is_open(struct intel_guc_ct_channel *ctch)
-{
- return ctch->vma != NULL;
-}
-
static int ctch_init(struct intel_guc *guc,
struct intel_guc_ct_channel *ctch)
{
@@ -214,25 +209,21 @@ static int ctch_init(struct intel_guc *guc,
static void ctch_fini(struct intel_guc *guc,
struct intel_guc_ct_channel *ctch)
{
+ GEM_BUG_ON(ctch->enabled);
+
i915_vma_unpin_and_release(>vma, I915_VMA_RELEASE_MAP);
}
-static int ctch_open(struct intel_guc *guc,
+static int ctch_enable(struct intel_guc *guc,
struct intel_guc_ct_channel *ctch)
{
u32 base;
int err;
int i;
- CT_DEBUG_DRIVER("CT: channel %d reopen=%s\n",
- ctch->owner, yesno(ctch_is_open(ctch)));
+ GEM_BUG_ON(!ctch->vma);
- if (!ctch->vma) {
- err = ctch_init(guc, ctch);
- if (unlikely(err))
- goto err_out;
- GEM_BUG_ON(!ctch->vma);
- }
+ GEM_BUG_ON(ctch->enabled);
/* vma should be already allocated and map'ed */
base = intel_guc_ggtt_offset(guc, ctch->vma);
@@ -255,7 +246,7 @@ static int ctch_open(struct intel_guc *guc,
base + PAGE_SIZE/4 * CTB_RECV,
INTEL_GUC_CT_BUFFER_TYPE_RECV);
if (unlikely(err))
- goto err_fini;
+ goto err_out;
err = guc_action_register_ct_buffer(guc,
base + PAGE_SIZE/4 * CTB_SEND,
@@ -263,23 +254,25 @@ static int ctch_open(struct intel_guc *guc,
if (unlikely(err))
goto err_deregister;
+ ctch->enabled = true;
+
return 0;
err_deregister:
guc_action_deregister_ct_buffer(guc,
ctch->owner,
INTEL_GUC_CT_BUFFER_TYPE_RECV);
-err_fini:
- ctch_fini(guc, ctch);
err_out:
DRM_ERROR("CT: can't open channel %d; err=%d\n", ctch->owner, err);
return err;
}
-static void ctch_close(struct intel_guc *guc,
+static void ctch_disable(struct intel_guc *guc,
struct intel_guc_ct_channel *ctch)
{
- GEM_BUG_ON(!ctch_is_open(ctch));
+ GEM_BUG_ON(!ctch->enabled);
+
+ ctch->enabled = false;
guc_action_deregister_ct_buffer(guc,
ctch->owner,
@@ -287,7 +280,6 @@ static void ctch_close(struct intel_guc *guc,
guc_action_deregister_ct_buffer(guc,
ctch->owner,
INTEL_GUC_CT_BUFFER_TYPE_RECV);
- ctch_fini(guc, ctch);
}
static u32 ctch_get_next_fence(struct intel_guc_ct_channel *ctch)
@@ -481,7 +473,7 @@ static int ctch_send(struct intel_guc_ct *ct,
u32 fence;
int err;
- GEM_BUG_ON(!ctch_is_open(ctch));
+ GEM_BUG_ON(!c
[Intel-gfx] [PATCH v3 0/2] GuC suspend paths cleanup
The work was started to fix bugs that were seen on the suspend and hibernate devices path.The initial issue to be seen was a warning with the CTB. In parallel there were issues seen on the suspend paths. This series works to resolve the errors in the GuC cleanup paths and be compatible with lockless reset. Sujaritha Sundaresan (2): drm/i915/guc: Splitting CT channel open/close functions drm/i915/guc: Calling guc_disable_communication in all suspend paths drivers/gpu/drm/i915/i915_reset.c | 2 +- drivers/gpu/drm/i915/intel_guc.c| 12 drivers/gpu/drm/i915/intel_guc_ct.c | 90 + drivers/gpu/drm/i915/intel_guc_ct.h | 3 + drivers/gpu/drm/i915/intel_uc.c | 23 ++-- drivers/gpu/drm/i915/intel_uc.h | 1 + 6 files changed, 101 insertions(+), 30 deletions(-) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 2/2] drm/i915/guc: Calling guc_disable_communication in all suspend paths
This aim of this patch is to call guc_disable_communication in all
suspend paths. The reason to introduce this is to resolve a bug that
occurred due to suspend late not being called in the hibernate devices
path.
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_reset.c | 2 +-
drivers/gpu/drm/i915/intel_uc.c | 23 +++
drivers/gpu/drm/i915/intel_uc.h | 1 +
3 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index c234feb5fdf5..0c7ba6fe5b7d 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -673,7 +673,7 @@ static void reset_prepare(struct drm_i915_private *i915)
for_each_engine(engine, i915, id)
reset_prepare_engine(engine);
- intel_uc_sanitize(i915);
+ intel_uc_reset_prepare(i915);
revoke_mmaps(i915);
}
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index e711eb3268bc..2d360d53757f 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -332,8 +332,6 @@ void intel_uc_sanitize(struct drm_i915_private *i915)
GEM_BUG_ON(!HAS_GUC(i915));
- guc_disable_communication(guc);
-
intel_huc_sanitize(huc);
intel_guc_sanitize(guc);
@@ -451,6 +449,23 @@ void intel_uc_fini_hw(struct drm_i915_private *i915)
guc_disable_communication(guc);
}
+/**
+ * intel_uc_reset_prepare - Prepare for reset
+ * @i915: device private
+ *
+ * Preparing for full gpu reset.
+ */
+void intel_uc_reset_prepare(struct drm_i915_private *i915)
+{
+ struct intel_guc *guc = >guc;
+
+ if (!USES_GUC(i915))
+ return;
+
+ guc_disable_communication(guc);
+ intel_uc_sanitize(i915);
+}
+
int intel_uc_suspend(struct drm_i915_private *i915)
{
struct intel_guc *guc = >guc;
@@ -468,7 +483,7 @@ int intel_uc_suspend(struct drm_i915_private *i915)
return err;
}
- gen9_disable_guc_interrupts(i915);
+ guc_disable_communication(guc);
return 0;
}
@@ -484,7 +499,7 @@ int intel_uc_resume(struct drm_i915_private *i915)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
- gen9_enable_guc_interrupts(i915);
+ guc_enable_communication(guc);
err = intel_guc_resume(guc);
if (err) {
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 870faf9011b9..c14729786652 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -38,6 +38,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv);
void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
int intel_uc_init(struct drm_i915_private *dev_priv);
void intel_uc_fini(struct drm_i915_private *dev_priv);
+void intel_uc_reset_prepare(struct drm_i915_private *i915);
int intel_uc_suspend(struct drm_i915_private *dev_priv);
int intel_uc_resume(struct drm_i915_private *dev_priv);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 0/2] GuC suspend paths cleanup
The work was started to fix bugs that were seen on the suspend and hibernate devices path.The initial issue to be seen was a warning with the CTB. In parallel there were issues seen on the suspend paths. This series works to resolve the errors in the GuC cleanup paths and be compatible with lockless reset. Sujaritha Sundaresan (2): drm/i915/guc: Splitting CT channel open/close functions drm/i915/guc: Calling guc_disable_communication in all suspend paths drivers/gpu/drm/i915/i915_reset.c | 2 +- drivers/gpu/drm/i915/intel_guc.c| 12 drivers/gpu/drm/i915/intel_guc_ct.c | 90 + drivers/gpu/drm/i915/intel_guc_ct.h | 3 + drivers/gpu/drm/i915/intel_uc.c | 23 ++-- drivers/gpu/drm/i915/intel_uc.h | 1 + integration-manifest| 32 ++ 7 files changed, 133 insertions(+), 30 deletions(-) create mode 100644 integration-manifest -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/2] drm/i915/guc: Splitting CT channel open/close functions
The aim of this patch is to allow enabling and disabling
of CTB without requiring the mutex lock.
v2: Phasing out ctch_is_enabled function and replacing it with
ctch->enabled (Daniele)
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/intel_guc.c| 12
drivers/gpu/drm/i915/intel_guc_ct.c | 90 +
drivers/gpu/drm/i915/intel_guc_ct.h | 3 +
3 files changed, 80 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 8660af3fd755..a4e1fc6b9eee 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -203,11 +203,19 @@ int intel_guc_init(struct intel_guc *guc)
goto err_log;
GEM_BUG_ON(!guc->ads_vma);
+ if (HAS_GUC_CT(dev_priv)) {
+ ret = intel_guc_ct_init(>ct);
+ if (ret)
+ goto err_ads;
+ }
+
/* We need to notify the guc whenever we change the GGTT */
i915_ggtt_enable_guc(dev_priv);
return 0;
+err_ads:
+ intel_guc_ads_destroy(guc);
err_log:
intel_guc_log_destroy(>log);
err_shared:
@@ -222,6 +230,10 @@ void intel_guc_fini(struct intel_guc *guc)
struct drm_i915_private *dev_priv = guc_to_i915(guc);
i915_ggtt_disable_guc(dev_priv);
+
+ if (HAS_GUC_CT(dev_priv))
+ intel_guc_ct_fini(>ct);
+
intel_guc_ads_destroy(guc);
intel_guc_log_destroy(>log);
guc_shared_data_destroy(guc);
diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c
b/drivers/gpu/drm/i915/intel_guc_ct.c
index a52883e9146f..9332a35f60f8 100644
--- a/drivers/gpu/drm/i915/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/intel_guc_ct.c
@@ -140,11 +140,6 @@ static int guc_action_deregister_ct_buffer(struct
intel_guc *guc,
return err;
}
-static bool ctch_is_open(struct intel_guc_ct_channel *ctch)
-{
- return ctch->vma != NULL;
-}
-
static int ctch_init(struct intel_guc *guc,
struct intel_guc_ct_channel *ctch)
{
@@ -214,25 +209,21 @@ static int ctch_init(struct intel_guc *guc,
static void ctch_fini(struct intel_guc *guc,
struct intel_guc_ct_channel *ctch)
{
+ GEM_BUG_ON(ctch->enabled);
+
i915_vma_unpin_and_release(>vma, I915_VMA_RELEASE_MAP);
}
-static int ctch_open(struct intel_guc *guc,
+static int ctch_enable(struct intel_guc *guc,
struct intel_guc_ct_channel *ctch)
{
u32 base;
int err;
int i;
- CT_DEBUG_DRIVER("CT: channel %d reopen=%s\n",
- ctch->owner, yesno(ctch_is_open(ctch)));
+ GEM_BUG_ON(!ctch->vma);
- if (!ctch->vma) {
- err = ctch_init(guc, ctch);
- if (unlikely(err))
- goto err_out;
- GEM_BUG_ON(!ctch->vma);
- }
+ GEM_BUG_ON(ctch->enabled)
/* vma should be already allocated and map'ed */
base = intel_guc_ggtt_offset(guc, ctch->vma);
@@ -255,7 +246,7 @@ static int ctch_open(struct intel_guc *guc,
base + PAGE_SIZE/4 * CTB_RECV,
INTEL_GUC_CT_BUFFER_TYPE_RECV);
if (unlikely(err))
- goto err_fini;
+ goto err_out;
err = guc_action_register_ct_buffer(guc,
base + PAGE_SIZE/4 * CTB_SEND,
@@ -263,23 +254,25 @@ static int ctch_open(struct intel_guc *guc,
if (unlikely(err))
goto err_deregister;
+ ctch->enabled = true;
+
return 0;
err_deregister:
guc_action_deregister_ct_buffer(guc,
ctch->owner,
INTEL_GUC_CT_BUFFER_TYPE_RECV);
-err_fini:
- ctch_fini(guc, ctch);
err_out:
DRM_ERROR("CT: can't open channel %d; err=%d\n", ctch->owner, err);
return err;
}
-static void ctch_close(struct intel_guc *guc,
+static void ctch_disable(struct intel_guc *guc,
struct intel_guc_ct_channel *ctch)
{
- GEM_BUG_ON(!ctch_is_open(ctch));
+ GEM_BUG_ON(!ctch->enabled);
+
+ ctch->enabled = false;
guc_action_deregister_ct_buffer(guc,
ctch->owner,
@@ -287,7 +280,6 @@ static void ctch_close(struct intel_guc *guc,
guc_action_deregister_ct_buffer(guc,
ctch->owner,
INTEL_GUC_CT_BUFFER_TYPE_RECV);
- ctch_fini(guc, ctch);
}
static u32 ctch_get_next_fence(struct intel_guc_ct_channel *ctch)
@@ -481,7 +473,7 @@ static int ctch_send(struct intel_guc_ct *ct,
u32 fence;
int err;
- GEM_BUG_ON(!ctch_is_open(ctch));
+ GEM_BUG_ON(!c
[Intel-gfx] [PATCH v2 2/2] drm/i915/guc: Calling guc_disable_communication in all suspend paths
This aim of this patch is to call guc_disable_communication in all
suspend paths. The reason to introduce this is to resolve a bug that
occurred due to suspend late not being called in the hibernate devices
path.
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_reset.c | 2 +-
drivers/gpu/drm/i915/intel_uc.c | 23 +++
drivers/gpu/drm/i915/intel_uc.h | 1 +
3 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index c234feb5fdf5..0c7ba6fe5b7d 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -673,7 +673,7 @@ static void reset_prepare(struct drm_i915_private *i915)
for_each_engine(engine, i915, id)
reset_prepare_engine(engine);
- intel_uc_sanitize(i915);
+ intel_uc_reset_prepare(i915);
revoke_mmaps(i915);
}
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index e711eb3268bc..2d360d53757f 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -332,8 +332,6 @@ void intel_uc_sanitize(struct drm_i915_private *i915)
GEM_BUG_ON(!HAS_GUC(i915));
- guc_disable_communication(guc);
-
intel_huc_sanitize(huc);
intel_guc_sanitize(guc);
@@ -451,6 +449,23 @@ void intel_uc_fini_hw(struct drm_i915_private *i915)
guc_disable_communication(guc);
}
+/**
+ * intel_uc_reset_prepare - Prepare for reset
+ * @i915: device private
+ *
+ * Preparing for full gpu reset.
+ */
+void intel_uc_reset_prepare(struct drm_i915_private *i915)
+{
+ struct intel_guc *guc = >guc;
+
+ if (!USES_GUC(i915))
+ return;
+
+ guc_disable_communication(guc);
+ intel_uc_sanitize(i915);
+}
+
int intel_uc_suspend(struct drm_i915_private *i915)
{
struct intel_guc *guc = >guc;
@@ -468,7 +483,7 @@ int intel_uc_suspend(struct drm_i915_private *i915)
return err;
}
- gen9_disable_guc_interrupts(i915);
+ guc_disable_communication(guc);
return 0;
}
@@ -484,7 +499,7 @@ int intel_uc_resume(struct drm_i915_private *i915)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
- gen9_enable_guc_interrupts(i915);
+ guc_enable_communication(guc);
err = intel_guc_resume(guc);
if (err) {
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 870faf9011b9..c14729786652 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -38,6 +38,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv);
void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
int intel_uc_init(struct drm_i915_private *dev_priv);
void intel_uc_fini(struct drm_i915_private *dev_priv);
+void intel_uc_reset_prepare(struct drm_i915_private *i915);
int intel_uc_suspend(struct drm_i915_private *dev_priv);
int intel_uc_resume(struct drm_i915_private *dev_priv);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/guc: Calling guc_disable_communication in all suspend paths
This aim of this patch is to call guc_disable_communication in all
suspend paths. The reason to introduce this is to resolve a bug that
occured due to suspend late not being called in the hibernate devices
path.
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_reset.c | 2 +-
drivers/gpu/drm/i915/intel_uc.c | 23 +++
drivers/gpu/drm/i915/intel_uc.h | 1 +
3 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index 12e74decd7a2..36e5c9c64285 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -673,7 +673,7 @@ static void reset_prepare(struct drm_i915_private *i915)
for_each_engine(engine, i915, id)
reset_prepare_engine(engine);
- intel_uc_sanitize(i915);
+ intel_uc_reset_prepare(i915);
revoke_mmaps(i915);
}
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index e711eb3268bc..2d360d53757f 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -332,8 +332,6 @@ void intel_uc_sanitize(struct drm_i915_private *i915)
GEM_BUG_ON(!HAS_GUC(i915));
- guc_disable_communication(guc);
-
intel_huc_sanitize(huc);
intel_guc_sanitize(guc);
@@ -451,6 +449,23 @@ void intel_uc_fini_hw(struct drm_i915_private *i915)
guc_disable_communication(guc);
}
+/**
+ * intel_uc_reset_prepare - Prepare for reset
+ * @i915: device private
+ *
+ * Preparing for full gpu reset.
+ */
+void intel_uc_reset_prepare(struct drm_i915_private *i915)
+{
+ struct intel_guc *guc = >guc;
+
+ if (!USES_GUC(i915))
+ return;
+
+ guc_disable_communication(guc);
+ intel_uc_sanitize(i915);
+}
+
int intel_uc_suspend(struct drm_i915_private *i915)
{
struct intel_guc *guc = >guc;
@@ -468,7 +483,7 @@ int intel_uc_suspend(struct drm_i915_private *i915)
return err;
}
- gen9_disable_guc_interrupts(i915);
+ guc_disable_communication(guc);
return 0;
}
@@ -484,7 +499,7 @@ int intel_uc_resume(struct drm_i915_private *i915)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
- gen9_enable_guc_interrupts(i915);
+ guc_enable_communication(guc);
err = intel_guc_resume(guc);
if (err) {
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 870faf9011b9..c14729786652 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -38,6 +38,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv);
void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
int intel_uc_init(struct drm_i915_private *dev_priv);
void intel_uc_fini(struct drm_i915_private *dev_priv);
+void intel_uc_reset_prepare(struct drm_i915_private *i915);
int intel_uc_suspend(struct drm_i915_private *dev_priv);
int intel_uc_resume(struct drm_i915_private *dev_priv);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/guc: Splitting CT channel open/close functions
The aim of this patch is to allow enabling and disabling
of CTB without requiring the mutex lock.
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/intel_guc.c| 12
drivers/gpu/drm/i915/intel_guc_ct.c | 85 +
drivers/gpu/drm/i915/intel_guc_ct.h | 3 +
3 files changed, 77 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 8660af3fd755..8ecb47087457 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -203,11 +203,19 @@ int intel_guc_init(struct intel_guc *guc)
goto err_log;
GEM_BUG_ON(!guc->ads_vma);
+ if (HAS_GUC_CT(dev_priv)) {
+ ret = intel_guc_ct_init(>ct);
+ if (ret)
+ goto err_ads;
+ }
+
/* We need to notify the guc whenever we change the GGTT */
i915_ggtt_enable_guc(dev_priv);
return 0;
+err_ads:
+ intel_guc_ads_destroy(guc);
err_log:
intel_guc_log_destroy(>log);
err_shared:
@@ -222,6 +230,10 @@ void intel_guc_fini(struct intel_guc *guc)
struct drm_i915_private *dev_priv = guc_to_i915(guc);
i915_ggtt_disable_guc(dev_priv);
+
+ if (HAS_GUC_CT(dev_priv))
+ intel_guc_ct_fini(>ct);
+
intel_guc_ads_destroy(guc);
intel_guc_log_destroy(>log);
guc_shared_data_destroy(guc);
diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c
b/drivers/gpu/drm/i915/intel_guc_ct.c
index a52883e9146f..fbf9da247975 100644
--- a/drivers/gpu/drm/i915/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/intel_guc_ct.c
@@ -140,9 +140,9 @@ static int guc_action_deregister_ct_buffer(struct intel_guc
*guc,
return err;
}
-static bool ctch_is_open(struct intel_guc_ct_channel *ctch)
+static bool ctch_is_enabled(struct intel_guc_ct_channel *ctch)
{
- return ctch->vma != NULL;
+ return ctch->is_enabled;
}
static int ctch_init(struct intel_guc *guc,
@@ -217,22 +217,14 @@ static void ctch_fini(struct intel_guc *guc,
i915_vma_unpin_and_release(>vma, I915_VMA_RELEASE_MAP);
}
-static int ctch_open(struct intel_guc *guc,
+static int ctch_enable(struct intel_guc *guc,
struct intel_guc_ct_channel *ctch)
{
u32 base;
int err;
int i;
- CT_DEBUG_DRIVER("CT: channel %d reopen=%s\n",
- ctch->owner, yesno(ctch_is_open(ctch)));
-
- if (!ctch->vma) {
- err = ctch_init(guc, ctch);
- if (unlikely(err))
- goto err_out;
- GEM_BUG_ON(!ctch->vma);
- }
+ GEM_BUG_ON(!ctch->vma);
/* vma should be already allocated and map'ed */
base = intel_guc_ggtt_offset(guc, ctch->vma);
@@ -255,7 +247,7 @@ static int ctch_open(struct intel_guc *guc,
base + PAGE_SIZE/4 * CTB_RECV,
INTEL_GUC_CT_BUFFER_TYPE_RECV);
if (unlikely(err))
- goto err_fini;
+ goto err_out;
err = guc_action_register_ct_buffer(guc,
base + PAGE_SIZE/4 * CTB_SEND,
@@ -263,23 +255,25 @@ static int ctch_open(struct intel_guc *guc,
if (unlikely(err))
goto err_deregister;
+ ctch->is_enabled = true;
+
return 0;
err_deregister:
guc_action_deregister_ct_buffer(guc,
ctch->owner,
INTEL_GUC_CT_BUFFER_TYPE_RECV);
-err_fini:
- ctch_fini(guc, ctch);
err_out:
DRM_ERROR("CT: can't open channel %d; err=%d\n", ctch->owner, err);
return err;
}
-static void ctch_close(struct intel_guc *guc,
+static void ctch_disable(struct intel_guc *guc,
struct intel_guc_ct_channel *ctch)
{
- GEM_BUG_ON(!ctch_is_open(ctch));
+ GEM_BUG_ON(!ctch_is_enabled(ctch));
+
+ ctch->is_enabled = false;
guc_action_deregister_ct_buffer(guc,
ctch->owner,
@@ -287,7 +281,6 @@ static void ctch_close(struct intel_guc *guc,
guc_action_deregister_ct_buffer(guc,
ctch->owner,
INTEL_GUC_CT_BUFFER_TYPE_RECV);
- ctch_fini(guc, ctch);
}
static u32 ctch_get_next_fence(struct intel_guc_ct_channel *ctch)
@@ -481,7 +474,7 @@ static int ctch_send(struct intel_guc_ct *ct,
u32 fence;
int err;
- GEM_BUG_ON(!ctch_is_open(ctch));
+ GEM_BUG_ON(!ctch_is_enabled(ctch));
GEM_BUG_ON(!len);
GEM_BUG_ON(len & ~GUC_CT_MSG_LEN_MASK);
GEM_BUG_ON(!response_buf && response_buf_size);
@@ -817,7 +810,7 @@ static void ct_process_host_channel(struct i
[Intel-gfx] [PATCH 0/2] GuC suspend paths cleanup
The work was started to fix bugs that were seen on the suspend and hibernate devices path.The initial issue to be seen was a warning with the CTB. In parallel there were issues seen on the suspend paths. This series works to resolve the errors in the GuC cleanup paths and be compatible with lockless reset. Sujaritha Sundaresan (2): drm/i915/guc: Splitting CT channel open/close functions drm/i915/guc: Calling guc_disable_communication in all suspend paths drivers/gpu/drm/i915/i915_reset.c | 2 +- drivers/gpu/drm/i915/intel_guc.c| 12 drivers/gpu/drm/i915/intel_guc_ct.c | 85 + drivers/gpu/drm/i915/intel_guc_ct.h | 3 + drivers/gpu/drm/i915/intel_uc.c | 23 ++-- drivers/gpu/drm/i915/intel_uc.h | 1 + 6 files changed, 98 insertions(+), 28 deletions(-) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v2 PATCH 2/2] drm/i915/guc : GEM_BUG_ON on invoking GuC reset function
Instead of returning -EINVAL, GEM_BUG_ON when GuC reset is invoked for
platforms not supporting as we don't expect to invoke it.
v2: re-wording commit message and subject (Sagar)
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 89547b61..94e1fb3 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1936,8 +1936,7 @@ int intel_reset_guc(struct drm_i915_private *dev_priv)
{
int ret;
- if (!HAS_GUC(dev_priv))
- return -EINVAL;
+ GEM_BUG_ON(!HAS_GUC(dev_priv));
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v2 PATCH 1/2] drm/i915/guc : Decoupling ADS and logs from submission
The Additional Data Struct (ADS) contains objects that are required by
GuC post FW load and are not necessarily submission-only. Even with
submission disabled we may require something inside the ADS, so it
makes more sense for them to be always created.
Similarly, we need to access GuC logs and even if GuC submission
is disabled, to debug issues with GuC loading or with whatever we're using
GuC for.
v2: re-wording commit message (Sagar)
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/intel_guc.c| 18
drivers/gpu/drm/i915/intel_guc_ads.c| 151
drivers/gpu/drm/i915/intel_guc_ads.h| 33 ++
drivers/gpu/drm/i915/intel_guc_submission.c | 134
5 files changed, 203 insertions(+), 134 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.c
create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 091aef2..4d9e2f8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -83,6 +83,7 @@ i915-y += i915_cmd_parser.o \
i915-y += intel_uc.o \
intel_uc_fw.o \
intel_guc.o \
+ intel_guc_ads.o \
intel_guc_ct.o \
intel_guc_fw.o \
intel_guc_log.o \
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 3c6bf5a..50b4725 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -23,6 +23,7 @@
*/
#include "intel_guc.h"
+#include "intel_guc_ads.h"
#include "intel_guc_submission.h"
#include "i915_drv.h"
@@ -163,10 +164,25 @@ int intel_guc_init(struct intel_guc *guc)
return ret;
GEM_BUG_ON(!guc->shared_data);
+ ret = intel_guc_log_create(guc);
+ if (ret)
+ goto err_shared;
+
+ ret = intel_guc_ads_create(guc);
+ if (ret)
+ goto err_log;
+ GEM_BUG_ON(!guc->ads_vma);
+
/* We need to notify the guc whenever we change the GGTT */
i915_ggtt_enable_guc(dev_priv);
return 0;
+
+err_log:
+ intel_guc_log_destroy(guc);
+err_shared:
+ guc_shared_data_destroy(guc);
+ return ret;
}
void intel_guc_fini(struct intel_guc *guc)
@@ -174,6 +190,8 @@ void intel_guc_fini(struct intel_guc *guc)
struct drm_i915_private *dev_priv = guc_to_i915(guc);
i915_ggtt_disable_guc(dev_priv);
+ intel_guc_ads_destroy(guc);
+ intel_guc_log_destroy(guc);
guc_shared_data_destroy(guc);
}
diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c
b/drivers/gpu/drm/i915/intel_guc_ads.c
new file mode 100644
index 000..f6066bc
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc_ads.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright © 2014-2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "intel_guc_ads.h"
+#include "intel_uc.h"
+#include "i915_drv.h"
+
+/*
+ * The Additional Data Struct (ADS) has pointers for different buffers used by
+ * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
+ * scheduling policies (guc_policies), a structure describing a collection of
+ * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
+ * its internal state for sleep.
+ */
+
+static void guc_policy_init(struct guc_policy *policy)
+{
+ policy->execution_quantum = POLICY_DEFAULT_EXECUTION_QUANTUM_US;
+ polic
[Intel-gfx] [v2 PATCH 2/2] drm/i915/guc : GEM_BUG_ON on invoking GuC reset function
Instead of returning -EINVAL, GEM_BUG_ON when GuC reset is invoked for
platforms not supporting as we don't expect to invoke it.
v2: re-wording commit message and subject (Sagar)
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 89547b61..94e1fb3 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1936,8 +1936,7 @@ int intel_reset_guc(struct drm_i915_private *dev_priv)
{
int ret;
- if (!HAS_GUC(dev_priv))
- return -EINVAL;
+ GEM_BUG_ON(!HAS_GUC(dev_priv));
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/guc : Decoupling ADS and logs from submission
The Additional Data Struct (ADS) contains objects that are required by
GuC post FW load and are not necessarily submission-only. Even with
submission disabled we may require something inside the ADS, so it
makes more sense for them to be always created.
Similarly, we still want to access GuC logs and even if GuC submission
is disable to debug issues with GuC loading or with whatever we're using
GuC for. To make a concrete example, the pages used by GuC to save state
during suspend are allocated as part of the ADS.
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/intel_guc.c| 18
drivers/gpu/drm/i915/intel_guc_ads.c| 151
drivers/gpu/drm/i915/intel_guc_ads.h| 33 ++
drivers/gpu/drm/i915/intel_guc_submission.c | 134
5 files changed, 203 insertions(+), 134 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.c
create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 091aef2..4d9e2f8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -83,6 +83,7 @@ i915-y += i915_cmd_parser.o \
i915-y += intel_uc.o \
intel_uc_fw.o \
intel_guc.o \
+ intel_guc_ads.o \
intel_guc_ct.o \
intel_guc_fw.o \
intel_guc_log.o \
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 3c6bf5a..50b4725 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -23,6 +23,7 @@
*/
#include "intel_guc.h"
+#include "intel_guc_ads.h"
#include "intel_guc_submission.h"
#include "i915_drv.h"
@@ -163,10 +164,25 @@ int intel_guc_init(struct intel_guc *guc)
return ret;
GEM_BUG_ON(!guc->shared_data);
+ ret = intel_guc_log_create(guc);
+ if (ret)
+ goto err_shared;
+
+ ret = intel_guc_ads_create(guc);
+ if (ret)
+ goto err_log;
+ GEM_BUG_ON(!guc->ads_vma);
+
/* We need to notify the guc whenever we change the GGTT */
i915_ggtt_enable_guc(dev_priv);
return 0;
+
+err_log:
+ intel_guc_log_destroy(guc);
+err_shared:
+ guc_shared_data_destroy(guc);
+ return ret;
}
void intel_guc_fini(struct intel_guc *guc)
@@ -174,6 +190,8 @@ void intel_guc_fini(struct intel_guc *guc)
struct drm_i915_private *dev_priv = guc_to_i915(guc);
i915_ggtt_disable_guc(dev_priv);
+ intel_guc_ads_destroy(guc);
+ intel_guc_log_destroy(guc);
guc_shared_data_destroy(guc);
}
diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c
b/drivers/gpu/drm/i915/intel_guc_ads.c
new file mode 100644
index 000..f6066bc
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc_ads.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright © 2014-2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "intel_guc_ads.h"
+#include "intel_uc.h"
+#include "i915_drv.h"
+
+/*
+ * The Additional Data Struct (ADS) has pointers for different buffers used by
+ * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
+ * scheduling policies (guc_policies), a structure describing a collection of
+ * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
+ * its internal state for sleep.
+ */
+
+static void guc_policy_init(struct guc_policy *policy)
+{
+ policy->execution_quantum = POLICY_DEFAULT_EXECUTION_QUANTUM_US;
+
[Intel-gfx] [v2 PATCH 2/2] drm/i915/guc : GEM_BUG_ON on invoking GuC reset function
Instead of returning -EINVAL, GEM_BUG_ON when GuC reset is invoked for
platforms not supporting as we don't expect to invoke it.
v2: re-wording commit message and subject (Sagar)
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 89547b61..94e1fb3 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1936,8 +1936,7 @@ int intel_reset_guc(struct drm_i915_private *dev_priv)
{
int ret;
- if (!HAS_GUC(dev_priv))
- return -EINVAL;
+ GEM_BUG_ON(!HAS_GUC(dev_priv));
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/guc : Decoupling ADS and logs from submission
The Additional Data Struct (ADS) contains objects that are required by
GuC post FW load and are not necessarily submission-only. Even with
submission disabled we may require something inside the ADS, so it
makes more sense for them to be always created.
Similarly, we still want to access GuC logs and even if GuC submission
is disable to debug issues with GuC loading or with whatever we're using
GuC for. To make a concrete example, the pages used by GuC to save state
during suspend are allocated as part of the ADS.
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/intel_guc.c| 18
drivers/gpu/drm/i915/intel_guc_ads.c| 151
drivers/gpu/drm/i915/intel_guc_ads.h| 33 ++
drivers/gpu/drm/i915/intel_guc_submission.c | 134
5 files changed, 203 insertions(+), 134 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.c
create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 091aef2..4d9e2f8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -83,6 +83,7 @@ i915-y += i915_cmd_parser.o \
i915-y += intel_uc.o \
intel_uc_fw.o \
intel_guc.o \
+ intel_guc_ads.o \
intel_guc_ct.o \
intel_guc_fw.o \
intel_guc_log.o \
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 3c6bf5a..50b4725 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -23,6 +23,7 @@
*/
#include "intel_guc.h"
+#include "intel_guc_ads.h"
#include "intel_guc_submission.h"
#include "i915_drv.h"
@@ -163,10 +164,25 @@ int intel_guc_init(struct intel_guc *guc)
return ret;
GEM_BUG_ON(!guc->shared_data);
+ ret = intel_guc_log_create(guc);
+ if (ret)
+ goto err_shared;
+
+ ret = intel_guc_ads_create(guc);
+ if (ret)
+ goto err_log;
+ GEM_BUG_ON(!guc->ads_vma);
+
/* We need to notify the guc whenever we change the GGTT */
i915_ggtt_enable_guc(dev_priv);
return 0;
+
+err_log:
+ intel_guc_log_destroy(guc);
+err_shared:
+ guc_shared_data_destroy(guc);
+ return ret;
}
void intel_guc_fini(struct intel_guc *guc)
@@ -174,6 +190,8 @@ void intel_guc_fini(struct intel_guc *guc)
struct drm_i915_private *dev_priv = guc_to_i915(guc);
i915_ggtt_disable_guc(dev_priv);
+ intel_guc_ads_destroy(guc);
+ intel_guc_log_destroy(guc);
guc_shared_data_destroy(guc);
}
diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c
b/drivers/gpu/drm/i915/intel_guc_ads.c
new file mode 100644
index 000..f6066bc
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc_ads.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright © 2014-2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "intel_guc_ads.h"
+#include "intel_uc.h"
+#include "i915_drv.h"
+
+/*
+ * The Additional Data Struct (ADS) has pointers for different buffers used by
+ * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
+ * scheduling policies (guc_policies), a structure describing a collection of
+ * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
+ * its internal state for sleep.
+ */
+
+static void guc_policy_init(struct guc_policy *policy)
+{
+ policy->execution_quantum = POLICY_DEFAULT_EXECUTION_QUANTUM_US;
+
[Intel-gfx] [PATCH 2/2] drm/i915/guc : GEM_BUG_ON for GuC reset
Including GEM_BUG_ON for GuC reset function in
intel_uncore.
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 89547b61..94e1fb3 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1936,8 +1936,7 @@ int intel_reset_guc(struct drm_i915_private *dev_priv)
{
int ret;
- if (!HAS_GUC(dev_priv))
- return -EINVAL;
+ GEM_BUG_ON(!HAS_GUC(dev_priv));
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/guc : Decoupling ADS and logs from submission
The Additional Data Struct (ADS) contains objects that are required by
GuC post FW load and are not necessarily submission-only. Even with
submission disabled we may require something inside the ADS, so it
makes more sense for them to be always created.
Similarly, we still want to access GuC logs and even if GuC submission
is disable to debug issues with GuC loading or with whatever we're using
GuC for. To make a concrete example, the pages used by GuC to save state
during suspend are allocated as part of the ADS.
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/intel_guc.c| 18
drivers/gpu/drm/i915/intel_guc_ads.c| 151
drivers/gpu/drm/i915/intel_guc_ads.h| 33 ++
drivers/gpu/drm/i915/intel_guc_submission.c | 134
5 files changed, 203 insertions(+), 134 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.c
create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 091aef2..4d9e2f8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -83,6 +83,7 @@ i915-y += i915_cmd_parser.o \
i915-y += intel_uc.o \
intel_uc_fw.o \
intel_guc.o \
+ intel_guc_ads.o \
intel_guc_ct.o \
intel_guc_fw.o \
intel_guc_log.o \
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 3c6bf5a..50b4725 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -23,6 +23,7 @@
*/
#include "intel_guc.h"
+#include "intel_guc_ads.h"
#include "intel_guc_submission.h"
#include "i915_drv.h"
@@ -163,10 +164,25 @@ int intel_guc_init(struct intel_guc *guc)
return ret;
GEM_BUG_ON(!guc->shared_data);
+ ret = intel_guc_log_create(guc);
+ if (ret)
+ goto err_shared;
+
+ ret = intel_guc_ads_create(guc);
+ if (ret)
+ goto err_log;
+ GEM_BUG_ON(!guc->ads_vma);
+
/* We need to notify the guc whenever we change the GGTT */
i915_ggtt_enable_guc(dev_priv);
return 0;
+
+err_log:
+ intel_guc_log_destroy(guc);
+err_shared:
+ guc_shared_data_destroy(guc);
+ return ret;
}
void intel_guc_fini(struct intel_guc *guc)
@@ -174,6 +190,8 @@ void intel_guc_fini(struct intel_guc *guc)
struct drm_i915_private *dev_priv = guc_to_i915(guc);
i915_ggtt_disable_guc(dev_priv);
+ intel_guc_ads_destroy(guc);
+ intel_guc_log_destroy(guc);
guc_shared_data_destroy(guc);
}
diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c
b/drivers/gpu/drm/i915/intel_guc_ads.c
new file mode 100644
index 000..f6066bc
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc_ads.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright © 2014-2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "intel_guc_ads.h"
+#include "intel_uc.h"
+#include "i915_drv.h"
+
+/*
+ * The Additional Data Struct (ADS) has pointers for different buffers used by
+ * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
+ * scheduling policies (guc_policies), a structure describing a collection of
+ * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
+ * its internal state for sleep.
+ */
+
+static void guc_policy_init(struct guc_policy *policy)
+{
+ policy
[Intel-gfx] [PATCH v10 1/2] drm/i915/guc : Removing enable_guc_loading and enable_guc_submission module parameters
We currently have two module parameters that control GuC:
"enable_guc_loading" and "enable_guc_submission". Whenever
we need submission=1, we also need loading=1.We also need
loading=1 when we want to want to verify the HuC, which
is every time we have a HuC (but all platforms with HuC
have a GuC and viceversa).
The above module parameters are being replaced by a single
enable_guc modparam.
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, Re-factoring code as per review (Michal)
v4: Rebase
v5: Separating message unification into a separate patch
v6: Re-factoring code (Sagar, Michal)
Rebase
v7: Applying review comments (Sagar)
Rebase
v8: Change to NEEDS_GUC_FW (Chris)
Applying review comments (Michal)
Clarifying commit message (Joonas)
v9: Applying review comments (Michal)
v10: Introducing enable_guc modparam
Applying review comments (Michal)
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
drivers/gpu/drm/i915/i915_drv.h | 12 +++--
drivers/gpu/drm/i915/i915_gem_context.c | 4 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 4 +-
drivers/gpu/drm/i915/i915_params.c | 11 ++--
drivers/gpu/drm/i915/i915_params.h | 3 +-
drivers/gpu/drm/i915/intel_guc.c| 2 +-
drivers/gpu/drm/i915/intel_guc_log.c| 6 +--
drivers/gpu/drm/i915/intel_uc.c | 96
++
10 files changed, 77 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index cb3e5aa..c12452d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2360,7 +2360,7 @@ static int i915_huc_load_status_info(struct seq_file *m,
void *data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct drm_printer p;
- if (!HAS_HUC_UCODE(dev_priv)) {
+ if (!HAS_HUC(dev_priv)) {
seq_puts(m, "not supported\n");
return 0;
}
@@ -2381,7 +2381,7 @@ static int i915_guc_load_status_info(struct seq_file *m,
void *data)
struct drm_printer p;
u32 tmp, i;
- if (!HAS_GUC_UCODE(dev_priv)) {
+ if (!HAS_GUC(dev_priv)) {
seq_puts(m, "not supported\n");
return 0;
}
@@ -2466,7 +2466,7 @@ static bool check_guc_submission(struct seq_file *m)
seq_printf(m, "GuC submission %s\n",
HAS_GUC(dev_priv) ?
"not supported" :
- HAS_GUC_SCHED(dev_priv) ?
+ NEEDS_GUC_LOAD(dev_priv) ?
"disabled" :
"failed");
return false;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2b76625..c4e1c7e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3220,10 +3220,16 @@ static inline unsigned int i915_sg_segment_size(void)
* properties, so we have separate macros to test them.
*/
#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
+#define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
-#define HAS_GUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_GUC_SCHED(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_HUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
+#define HAS_GUC_FW(dev_priv) \
+ ((dev_priv)->guc.fw.fetch_status == INTEL_UC_FIRMWARE_SUCCESS)
+#define HAS_HUC_FW(dev_priv) \
+ ((dev_priv)->huc.fw.fetch_status == INTEL_UC_FIRMWARE_SUCCESS)
+
+#define NEEDS_GUC_LOAD(dev_priv) \
+ (HAS_GUC(dev_priv) && HAS_GUC_FW(dev_priv) && \
+ (HAS_HUC_FW(dev_priv) || i915_modparams.enable_guc))
#define HAS_RESOURCE_STREAMER(dev_priv)
((dev_priv)->info.has_resource_streamer)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index c1efbaf..f9240dd 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -316,7 +316,7 @@ static u32 default_desc_template(const struct
drm_i915_private *i915,
* present or not in use we still need a small bias as ring wraparound
* at offset 0 sometimes hangs. No idea why.
*/
- if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading)
+ if (NEEDS_GUC_LOAD(dev_pri
[Intel-gfx] [PATCH v10 2/2] drm/i915/guc : Updating GuC and HuC firmware select function
Updating GuC and HuC firmware select function to support removing
i915_modparams.enable_guc_loading module parameter.
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, Re-factoring code as per review (Michal)
v4: Rebase
v5: Separating message unification into a separate patch
v6: Re-factoring code (Sagar, Michal)
Rebase
v7: Separating from previuos patch (Sagar)
Rebase
v8: Including change to intel_uc.c
Applying review comments (Michal)
v9: Including HAS_HUC macro
v10: Applying review comments (Michal)
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/intel_guc_fw.c | 15 +--
drivers/gpu/drm/i915/intel_guc_fw.h | 2 +-
drivers/gpu/drm/i915/intel_huc.c| 8
drivers/gpu/drm/i915/intel_uc.c | 4
4 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index 69ba015..52d126d 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -58,18 +58,18 @@
/**
* intel_guc_fw_select() - selects GuC firmware for uploading
- *
* @guc: intel_guc struct
- *
- * Return: zero when we know firmware, non-zero in other case
*/
-int intel_guc_fw_select(struct intel_guc *guc)
+void intel_guc_fw_select(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
intel_uc_fw_init(>fw, INTEL_UC_FW_TYPE_GUC);
- if (i915_modparams.guc_firmware_path) {
+ if (HAS_GUC(dev_priv)) {
+ DRM_ERROR("No GuC FW known for platform with GuC!\n");
+ return;
+ } else if (i915_modparams.guc_firmware_path) {
guc->fw.path = i915_modparams.guc_firmware_path;
guc->fw.major_ver_wanted = 0;
guc->fw.minor_ver_wanted = 0;
@@ -89,12 +89,7 @@ int intel_guc_fw_select(struct intel_guc *guc)
guc->fw.path = I915_GLK_GUC_UCODE;
guc->fw.major_ver_wanted = GLK_FW_MAJOR;
guc->fw.minor_ver_wanted = GLK_FW_MINOR;
- } else {
- DRM_ERROR("No GuC firmware known for platform with GuC!\n");
- return -ENOENT;
}
-
- return 0;
}
static void guc_prepare_xfer(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.h
b/drivers/gpu/drm/i915/intel_guc_fw.h
index 023f5ba..7f6ccaf 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.h
+++ b/drivers/gpu/drm/i915/intel_guc_fw.h
@@ -27,7 +27,7 @@
struct intel_guc;
-int intel_guc_fw_select(struct intel_guc *guc);
+void intel_guc_fw_select(struct intel_guc *guc);
int intel_guc_fw_upload(struct intel_guc *guc);
#endif
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 98d1725..911405d 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -87,7 +87,10 @@ void intel_huc_select_fw(struct intel_huc *huc)
intel_uc_fw_init(>fw, INTEL_UC_FW_TYPE_HUC);
- if (i915_modparams.huc_firmware_path) {
+ if (HAS_HUC(dev_priv)) {
+ DRM_ERROR("No HuC FW known for platform with HuC!\n");
+ return;
+ } else if (i915_modparams.huc_firmware_path) {
huc->fw.path = i915_modparams.huc_firmware_path;
huc->fw.major_ver_wanted = 0;
huc->fw.minor_ver_wanted = 0;
@@ -107,9 +110,6 @@ void intel_huc_select_fw(struct intel_huc *huc)
huc->fw.path = I915_GLK_HUC_UCODE;
huc->fw.major_ver_wanted = GLK_HUC_FW_MAJOR;
huc->fw.minor_ver_wanted = GLK_HUC_FW_MINOR;
- } else {
- DRM_ERROR("No HuC firmware known for platform with HuC!\n");
- return;
}
}
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 233f680..2fdd7a8 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -91,10 +91,14 @@ void intel_uc_sanitize_options(struct drm_i915_private
*dev_priv)
void intel_uc_init_early(struct drm_i915_private *dev_priv)
{
intel_guc_init_early(_priv->guc);
+ intel_guc_fw_select(_priv->guc);
+ intel_huc_select_fw(_priv->huc);
}
void intel_uc_init_fw(struct drm_i915_private *dev_priv)
{
+ if (!HAS_GUC(dev_priv))
+ return;
intel_uc_fw_fetch(dev_priv, _priv->huc.fw);
intel_uc_fw_fetch(dev_priv, _priv->guc.fw);
}
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/2] drm/i915/guc : Removing GuC loading and submission modparams
The aim of this series is to remove the enable_guc_loading and enable_guc_submission module parameters. They are being replaced by a common, newly defined enable_guc module parameter. This series has been split from a bigger series that has previously been sent to this mailing list. Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Sujaritha Sundaresan (2): drm/i915/guc : Removing enable_guc_loading and enable_guc_submission module parameters drm/i915/guc : Updating GuC and HuC firmware select function drivers/gpu/drm/i915/i915_debugfs.c | 64 +- drivers/gpu/drm/i915/i915_drv.h | 12 +++-- drivers/gpu/drm/i915/i915_gem_context.c | 4 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- drivers/gpu/drm/i915/i915_irq.c | 4 +- drivers/gpu/drm/i915/i915_params.c | 11 ++-- drivers/gpu/drm/i915/i915_params.h | 3 +- drivers/gpu/drm/i915/intel_guc.c| 2 +- drivers/gpu/drm/i915/intel_guc_fw.c | 12 ++--- drivers/gpu/drm/i915/intel_guc_fw.h | 2 +- drivers/gpu/drm/i915/intel_guc_log.c| 6 +-- drivers/gpu/drm/i915/intel_huc.c| 8 +-- drivers/gpu/drm/i915/intel_uc.c | 95 + 13 files changed, 127 insertions(+), 103 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v10 1/1] drm/i915 : Unifying seq_puts messages for feature support
Unifying the various seq_puts messages in debugfs to a common one for
feature support.
v2: Clarifying the commit message (Anusha)
v3: Re-factoring code as per review (Michal)
v4: Rebase
v5: Split from following patch
v6: Re-factoring code (Michal, Sagar)
Clarifying commit message (Sagar)
v7: Generalizing subject to drm/i915 (Sagar)
v8: Omitting DRRS seq_puts unification (Michal)
v9: Including the HAS_HUC condition (Michal)
Updating more functions with unified message (Sagar)
v10: Sepearating from patch series
Reverting macro changes
Suggested by : Michal Wajdeczko <michal.wajdec...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 49 +
1 file changed, 34 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index ff8f508..a029842 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1641,7 +1641,7 @@ static int i915_fbc_status(struct seq_file *m, void
*unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
if (!HAS_FBC(dev_priv)) {
- seq_puts(m, "FBC unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -1809,7 +1809,7 @@ static int i915_ring_freq_table(struct seq_file *m, void
*unused)
unsigned int max_gpu_freq, min_gpu_freq;
if (!HAS_LLC(dev_priv)) {
- seq_puts(m, "unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2360,8 +2360,10 @@ static int i915_huc_load_status_info(struct seq_file *m,
void *data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct drm_printer p;
- if (!HAS_HUC_UCODE(dev_priv))
+ if (!HAS_HUC_UCODE(dev_priv)) {
+ seq_puts(m, "not supported\n");
return 0;
+ }
p = drm_seq_file_printer(m);
intel_uc_fw_dump(_priv->huc.fw, );
@@ -2379,8 +2381,10 @@ static int i915_guc_load_status_info(struct seq_file *m,
void *data)
struct drm_printer p;
u32 tmp, i;
- if (!HAS_GUC_UCODE(dev_priv))
+ if (!HAS_GUC_UCODE(dev_priv)) {
+ seq_puts(m, "not supported\n");
return 0;
+ }
p = drm_seq_file_printer(m);
intel_uc_fw_dump(_priv->guc.fw, );
@@ -2460,9 +2464,11 @@ static bool check_guc_submission(struct seq_file *m)
if (!guc->execbuf_client) {
seq_printf(m, "GuC submission %s\n",
+ HAS_GUC(dev_priv) ?
+ "not supported" :
HAS_GUC_SCHED(dev_priv) ?
"disabled" :
- "not supported");
+ "failed");
return false;
}
@@ -2651,7 +2657,7 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
bool enabled = false;
if (!HAS_PSR(dev_priv)) {
- seq_puts(m, "PSR not supported\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2828,7 +2834,7 @@ static int i915_runtime_pm_status(struct seq_file *m,
void *unused)
struct pci_dev *pdev = dev_priv->drm.pdev;
if (!HAS_RUNTIME_PM(dev_priv))
- seq_puts(m, "Runtime power management not supported\n");
+ seq_puts(m, "not supported\n");
seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
seq_printf(m, "IRQs disabled: %s\n",
@@ -3432,9 +3438,12 @@ static int i915_ipc_status_show(struct seq_file *m, void
*data)
static int i915_ipc_status_open(struct inode *inode, struct file *file)
{
struct drm_i915_private *dev_priv = inode->i_private;
+ struct seq_file *m;
- if (!HAS_IPC(dev_priv))
- return -ENODEV;
+ if (!HAS_IPC(dev_priv)) {
+ seq_puts(m, "not supported\n");
+ return 0;
+ }
return single_open(file, i915_ipc_status_show, dev_priv);
}
@@ -3939,9 +3948,12 @@ static int cur_wm_latency_show(struct seq_file *m, void
*data)
static int pri_wm_latency_open(struct inode *inode, struct file *file)
{
struct drm_i915_private *dev_priv = inode->i_private;
+ struct seq_file *m;
- if (INTEL_
[Intel-gfx] [PATCH v9 8/8] drm/i915/guc : Calling intel_guc_init in i915_gem_init
Placing the call to intel_guc_init after i915_gem_contexts_init,
based on the dependency within i915_gem_init.
Will move the function if required, depending on the review
comments.
Suggested by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/i915_gem.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 889ae88..c877a5d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -36,6 +36,7 @@
#include "intel_frontbuffer.h"
#include "intel_mocs.h"
#include "i915_gemfs.h"
+#include "intel_guc.h"
#include
#include
#include
@@ -4972,6 +4973,7 @@ bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv, int value)
int i915_gem_init(struct drm_i915_private *dev_priv)
{
+ struct intel_guc *guc = _priv->guc;
int ret;
mutex_lock(_priv->drm.struct_mutex);
@@ -5015,6 +5017,18 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
if (ret)
goto out_unlock;
+ ret = intel_guc_init(guc);
+
+ if (i915_modparams.enable_guc) {
+ /*
+* This is stuff we need to have available at fw load
time
+* if we are planning to enable submission later
+*/
+ ret = intel_guc_init(guc);
+ if (ret)
+ goto err_shared;
+ }
+
ret = intel_engines_init(dev_priv);
if (ret)
goto out_unlock;
@@ -5035,7 +5049,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
out_unlock:
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
mutex_unlock(_priv->drm.struct_mutex);
-
+err_shared:
+ intel_guc_fini(guc);
return ret;
}
@@ -5192,6 +5207,7 @@ void i915_gem_load_cleanup(struct drm_i915_private
*dev_priv)
rcu_barrier();
i915_gemfs_fini(dev_priv);
+ intel_guc_fini(_priv->guc);
}
int i915_gem_freeze(struct drm_i915_private *dev_priv)
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 5/8] drm/i915/guc : GEM_BUG_ON for GuC reset function
Including GEM_BUG_ON for GuC reset function in intel_uncore.
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 211acee7..653ef4e 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1928,8 +1928,7 @@ int intel_reset_guc(struct drm_i915_private *dev_priv)
{
int ret;
- if (!HAS_GUC(dev_priv))
- return -EINVAL;
+ GEM_BUG_ON(!HAS_GUC(dev_priv));
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 2/8] drm/i915/guc : Removing i915_modparams.enable_guc_loading module parameter
We currently have two module parameters that control GuC:
"enable_guc_loading" and "enable_guc_submission". Whenever
we need submission=1, we also need loading=1.We also need
loading=1 when we want to want to verify the HuC, which
is every time we have a HuC (but all platforms with HuC
have a GuC and viceversa).
Also if we have HuC have firmware to be loaded, we need to
have GuC to actually load it. So if the user wants to avoid
the GuC from getting loaded, they must not have a HuC
firmware to be loaded, in addition to not using submission.
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, Re-factoring code as per review (Michal)
v4: Rebase
v5: Separating message unification into a separate patch
v6: Re-factoring code (Sagar, Michal)
Rebase
v7: Applying review comments (Sagar)
Rebase
v8: Change to NEEDS_GUC_FW (Chris)
Applying review comments (Michal)
Clarifying commit message (Joonas)
v9: Applying review comments (Michal)
Suggested by; Oscar Mateo <oscar.ma...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 9 +++--
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/i915_params.c | 4 ---
drivers/gpu/drm/i915/i915_params.h | 1 -
drivers/gpu/drm/i915/intel_uc.c | 59 --
7 files changed, 35 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c94f34f..798fa8a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3219,10 +3219,13 @@ static inline unsigned int i915_sg_segment_size(void)
* properties, so we have separate macros to test them.
*/
#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
+#define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
-#define HAS_GUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_GUC_SCHED(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_HUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
+#define HAS_GUC_UCODE(dev_priv)((dev_priv)->guc.fw.path != NULL)
+#define HAS_HUC_UCODE(dev_priv)((dev_priv)->huc.fw.path != NULL)
+
+#define NEEDS_GUC_FW(dev_priv) \
+ (HAS_GUC(dev_priv) && i915_modparams.enable_guc_submission)
#define HAS_RESOURCE_STREAMER(dev_priv)
((dev_priv)->info.has_resource_streamer)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index c05c3d7..6a819c0 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -316,7 +316,7 @@ static u32 default_desc_template(const struct
drm_i915_private *i915,
* present or not in use we still need a small bias as ring wraparound
* at offset 0 sometimes hangs. No idea why.
*/
- if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading)
+ if (NEEDS_GUC_FW(dev_priv))
ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
else
ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 1e40eeb..b634edf 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3476,7 +3476,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
* currently don't have any bits spare to pass in this upper
* restriction!
*/
- if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading) {
+ if (NEEDS_GUC_FW(dev_priv)) {
ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP);
ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
}
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ff00e46..a414bca 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4032,7 +4032,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
for (i = 0; i < MAX_L3_SLICES; ++i)
dev_priv->l3_parity.remap_info[i] = NULL;
- if (HAS_GUC_SCHED(dev_priv))
+ if (HAS_GUC(dev_priv))
dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
/* Let's track the enabled rps events */
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
in
[Intel-gfx] [PATCH v9 6/8] drm/i915/guc : Introducing enable_guc module parameter
Replacing enable_guc_submission with enable_guc modparam.
In effect enable_guc is replacing enable_guc_loading and
enable_guc_submission.
Suggested by : Michal Wajdeczko <michal.wajdec...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nik...@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/i915_params.c | 7 ---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_guc.c| 2 +-
drivers/gpu/drm/i915/intel_uc.c | 35 +
7 files changed, 27 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 798fa8a..ad73cee 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3225,7 +3225,7 @@ static inline unsigned int i915_sg_segment_size(void)
#define HAS_HUC_UCODE(dev_priv)((dev_priv)->huc.fw.path != NULL)
#define NEEDS_GUC_FW(dev_priv) \
- (HAS_GUC(dev_priv) && i915_modparams.enable_guc_submission)
+ (HAS_GUC(dev_priv) && i915_modparams.enable_guc)
#define HAS_RESOURCE_STREAMER(dev_priv)
((dev_priv)->info.has_resource_streamer)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 6a819c0..43210df 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -409,7 +409,7 @@ struct i915_gem_context *
i915_gem_context_set_closed(ctx); /* not user accessible */
i915_gem_context_clear_bannable(ctx);
i915_gem_context_set_force_single_submission(ctx);
- if (!i915_modparams.enable_guc_submission)
+ if (!i915_modparams.enable_guc)
ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a414bca..693b345 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1400,7 +1400,7 @@ static void snb_gt_irq_handler(struct drm_i915_private
*dev_priv,
if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) {
notify_ring(engine);
- tasklet |= i915_modparams.enable_guc_submission;
+ tasklet |= i915_modparams.enable_guc;
}
if (tasklet)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 1c25f45..51cf6bd 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -162,9 +162,10 @@ struct i915_params i915_modparams __read_mostly = {
"(0=use value from vbt [default], 1=low power swing(200mV),"
"2=default swing(400mV))");
-i915_param_named_unsafe(enable_guc_submission, int, 0400,
- "Enable GuC submission "
- "(-1=auto, 0=never [default], 1=if available, 2=required)");
+i915_param_named_unsafe(enable_guc, int, 0400,
+ "Enable GuC submission and loading "
+ "(-1=auto [default], 0=No GuC or HuC, 1=Load & use GuC, HuC on the side"
+ " 2=Load GuC only for HuC)");
i915_param_named(guc_log_level, int, 0400,
"GuC firmware logging level (-1:disabled (default), 0-3:enabled)");
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 9e1e231..7bf4dce 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -44,7 +44,7 @@
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc_submission, 0) \
+ param(int, enable_guc, -1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 823d0c2..629ef5d 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -128,7 +128,7 @@ void intel_guc_init_params(struct intel_guc *guc)
}
/* If GuC submission is enabled, set up additional parameters here */
- if (i915_modparams.enable_guc_submission) {
+ if (i915_modparams.enable_guc) {
u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);
u32
[Intel-gfx] [PATCH v9 7/8] drm/i915/guc : Decouple logs and ADS from submission
The Additional Data Struct (ADS) contains objects that are required by
guc post FW load and are not necessarily submission-only (although that's
our current only use-case). If in the future we load GuC with submission
disabled to use some other GuC feature we might still end up requiring
something inside the ADS, so it makes more sense for them to be always
created if GuC is loaded.
Similarly, we still want to access GuC logs even if GuC submission is
disable to debug issues with GuC loading or with wathever we're using
GuC for.
To make a concrete example, the pages used by GuC to save state during
suspend are allocated as part of the ADS.
v3: Group initialization of GuC objects
v2: Decoupling ADS together with logs
v3: Re-factoring code as per review (Michal)
v4: Rebase
v5: Separating group object initialization into next patch
Clarifying commit message
v6: Reverting to goto err format (Michal)
Moved guc_ads functions to dedicated file
Rebase
v7: Rebase
v8: Applying review comments (Michal)
v9: Defining intel_guc_init function (Sagar)
Applying review comments (Michal, Sagar)
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/intel_guc.c| 63 ++
drivers/gpu/drm/i915/intel_guc.h| 2 +
drivers/gpu/drm/i915/intel_guc_ads.c| 147 ++
drivers/gpu/drm/i915/intel_guc_ads.h| 33 +
drivers/gpu/drm/i915/intel_guc_submission.c | 189 +---
drivers/gpu/drm/i915/intel_guc_submission.h | 9 +-
drivers/gpu/drm/i915/intel_uc.c | 16 +--
8 files changed, 261 insertions(+), 199 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.c
create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 9469c37..694e7ca 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -82,6 +82,7 @@ i915-y += i915_cmd_parser.o \
i915-y += intel_uc.o \
intel_uc_fw.o \
intel_guc.o \
+ intel_guc_ads.o \
intel_guc_ct.o \
intel_guc_fw.o \
intel_guc_log.o \
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 629ef5d..c688586 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -23,6 +23,7 @@
*/
#include "intel_guc.h"
+#include "intel_guc_ads.h"
#include "intel_guc_submission.h"
#include "i915_drv.h"
@@ -224,6 +225,68 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*action, u32 len)
return ret;
}
+/*
+ * Set up the memory resources to be shared with the GuC (via the GGTT)
+ * at firmware loading time.
+ */
+
+int intel_guc_init(struct intel_guc *guc)
+{
+ int ret;
+
+ if (guc->stage_desc_pool)
+ return 0;
+
+ ret = guc_stage_desc_pool_create(guc);
+ if (ret)
+ return ret;
+ /*
+* Keep static analysers happy, let them know that we allocated the
+* vma after testing that it didn't exist earlier.
+*/
+ GEM_BUG_ON(!guc->stage_desc_pool);
+
+ ret = guc_shared_data_create(guc);
+ if (ret)
+ goto err_stage_desc_pool;
+ GEM_BUG_ON(!guc->shared_data);
+
+ ret = intel_guc_log_create(guc);
+ if (ret < 0)
+ goto err_shared_data;
+
+ ret = guc_preempt_work_create(guc);
+ if (ret)
+ goto err_log;
+ GEM_BUG_ON(!guc->preempt_wq);
+
+ ret = intel_guc_ads_create(guc);
+ if (ret < 0)
+ goto err_wq;
+ GEM_BUG_ON(!guc->ads_vma);
+
+ return 0;
+
+err_wq:
+ guc_preempt_work_destroy(guc);
+err_log:
+ intel_guc_log_destroy(guc);
+err_shared_data:
+ guc_shared_data_destroy(guc);
+err_stage_desc_pool:
+ guc_stage_desc_pool_destroy(guc);
+ return ret;
+}
+
+void intel_guc_fini(struct intel_guc *guc)
+{
+ intel_guc_ads_destroy(guc);
+ guc_preempt_work_destroy(guc);
+ intel_guc_log_destroy(guc);
+ guc_shared_data_destroy(guc);
+ guc_stage_desc_pool_destroy(guc);
+}
+
int intel_guc_sample_forcewake(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 75c4cfe..a805c79 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -121,6 +121,8 @@ static in
[Intel-gfx] [PATCH v9 0/8] drm/i915/guc : Removing enable_guc_loading module and Decoupling logs and ADS from submission
The first patch simply unifies different seq_puts messages found in debugfs. Patch 2 and 3 involve replacing te enable_guc_loading module. Patches 4 and 5 deal with removing dependancies on enable_guc_submission. Patch 6 introduces the enable_guc parameter. Patches 7 and 8 deal with decoupling GuC logs and ADS from submission. Cc: Anusha Srivatsa <anusha.sriva...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Sujaritha Sundaresan (8): drm/i915 : Unifying seq_puts messages for feature support drm/i915/guc : Removing i915_modparams.enable_guc_loading module parameter drm/i915/guc : Updating GuC and HuC firmware select function drm/i915/guc : Updating GuC logs to remove enable_guc_submission parameter drm/i915/guc : GEM_BUG_ON for GuC reset function drm/i915/guc : Introducing enable_guc module parameter drm/i915/guc : Decouple logs and ADS from submission drm/i915/guc : Calling intel_guc_init in i915_gem_init drivers/gpu/drm/i915/Makefile |1 + drivers/gpu/drm/i915/i915_debugfs.c | 59 +- drivers/gpu/drm/i915/i915_drv.h |9 +- drivers/gpu/drm/i915/i915_gem.c | 18 +- drivers/gpu/drm/i915/i915_gem_context.c |4 +- drivers/gpu/drm/i915/i915_gem_gtt.c |2 +- drivers/gpu/drm/i915/i915_irq.c |4 +- drivers/gpu/drm/i915/i915_params.c | 11 +- drivers/gpu/drm/i915/i915_params.h |3 +- drivers/gpu/drm/i915/intel_guc.c| 67 +- drivers/gpu/drm/i915/intel_guc.h|8 +- drivers/gpu/drm/i915/intel_guc_ads.c| 147 +++ drivers/gpu/drm/i915/intel_guc_ads.h| 33 + drivers/gpu/drm/i915/intel_guc_fw.c |6 +- drivers/gpu/drm/i915/intel_guc_fw.h |2 +- drivers/gpu/drm/i915/intel_guc_log.c|6 +- drivers/gpu/drm/i915/intel_guc_submission.c | 1286 +++ drivers/gpu/drm/i915/intel_guc_submission.h | 85 ++ drivers/gpu/drm/i915/intel_huc.c|3 +- drivers/gpu/drm/i915/intel_uc.c | 101 +-- drivers/gpu/drm/i915/intel_uncore.c |3 +- 21 files changed, 1750 insertions(+), 112 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.c create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.h create mode 100644 drivers/gpu/drm/i915/intel_guc_submission.c create mode 100644 drivers/gpu/drm/i915/intel_guc_submission.h -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 4/8] drm/i915/guc : Updating GuC logs to remove enable_guc_submission parameter
Replacing conditions to remove dependance on enable_guc_submission
v9: Including guc_log_level in the condition (Sagar)
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/intel_guc_log.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c
b/drivers/gpu/drm/i915/intel_guc_log.c
index 76d3eb1..4dbe5be 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -505,7 +505,7 @@ static void guc_flush_logs(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
- if (!i915_modparams.enable_guc_submission ||
+ if (!NEEDS_GUC_FW(dev_priv) ||
(i915_modparams.guc_log_level < 0))
return;
@@ -646,7 +646,7 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv,
u64 control_val)
void i915_guc_log_register(struct drm_i915_private *dev_priv)
{
- if (!i915_modparams.enable_guc_submission ||
+ if (!NEEDS_GUC_FW(dev_priv) ||
(i915_modparams.guc_log_level < 0))
return;
@@ -657,7 +657,7 @@ void i915_guc_log_register(struct drm_i915_private
*dev_priv)
void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
{
- if (!i915_modparams.enable_guc_submission)
+ if (!NEEDS_GUC_FW(dev_priv))
return;
mutex_lock(_priv->drm.struct_mutex);
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 3/8] drm/i915/guc : Updating GuC and HuC firmware select function
Updating GuC and HuC firmware select function to support removing
i915_modparams.enable_guc_loading module parameter.
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, Re-factoring code as per review (Michal)
v4: Rebase
v5: Separating message unification into a separate patch
v6: Re-factoring code (Sagar, Michal)
Rebase
v7: Separating from previuos patch (Sagar)
Rebase
v8: Including change to intel_uc.c
Applying review comments (Michal)
v9: Including HAS_HUC macro
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/intel_guc_fw.c | 6 ++
drivers/gpu/drm/i915/intel_guc_fw.h | 2 +-
drivers/gpu/drm/i915/intel_huc.c| 3 ++-
drivers/gpu/drm/i915/intel_uc.c | 7 +++
4 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index 69ba015..112c89d 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -63,7 +63,7 @@
*
* Return: zero when we know firmware, non-zero in other case
*/
-int intel_guc_fw_select(struct intel_guc *guc)
+void intel_guc_fw_select(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -91,10 +91,8 @@ int intel_guc_fw_select(struct intel_guc *guc)
guc->fw.minor_ver_wanted = GLK_FW_MINOR;
} else {
DRM_ERROR("No GuC firmware known for platform with GuC!\n");
- return -ENOENT;
+ return;
}
-
- return 0;
}
static void guc_prepare_xfer(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.h
b/drivers/gpu/drm/i915/intel_guc_fw.h
index 023f5ba..7f6ccaf 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.h
+++ b/drivers/gpu/drm/i915/intel_guc_fw.h
@@ -27,7 +27,7 @@
struct intel_guc;
-int intel_guc_fw_select(struct intel_guc *guc);
+void intel_guc_fw_select(struct intel_guc *guc);
int intel_guc_fw_upload(struct intel_guc *guc);
#endif
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 98d1725..7f4bbc1 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -108,7 +108,8 @@ void intel_huc_select_fw(struct intel_huc *huc)
huc->fw.major_ver_wanted = GLK_HUC_FW_MAJOR;
huc->fw.minor_ver_wanted = GLK_HUC_FW_MINOR;
} else {
- DRM_ERROR("No HuC firmware known for platform with HuC!\n");
+ if (HAS_HUC(dev_priv))
+ DRM_ERROR("No HuC firmware known for platform with
HuC!\n");
return;
}
}
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 648e59c..320165a 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -82,11 +82,18 @@ void intel_uc_sanitize_options(struct drm_i915_private
*dev_priv)
void intel_uc_init_early(struct drm_i915_private *dev_priv)
{
+ struct intel_guc *guc = _priv->guc;
+ struct intel_huc *huc = _priv->huc;
+
intel_guc_init_early(_priv->guc);
+ intel_guc_fw_select(guc);
+ intel_huc_select_fw(huc);
}
void intel_uc_init_fw(struct drm_i915_private *dev_priv)
{
+ if (!HAS_GUC(dev_priv))
+ return;
intel_uc_fw_fetch(dev_priv, _priv->huc.fw);
intel_uc_fw_fetch(dev_priv, _priv->guc.fw);
}
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 1/8] drm/i915 : Unifying seq_puts messages for feature support
Unifying the various seq_puts messages in debugfs to the simplest one for
feature support.
v2: Clarifying the commit message (Anusha)
v3: Re-factoring code as per review (Michal)
v4: Rebase
v5: Split from following patch
v6: Re-factoring code (Michal, Sagar)
Clarifying commit message (Sagar)
v7: Generalizing subject to drm/i915 (Sagar)
v8: Omitting DRRS seq_puts unification (Michal)
v9: Including the HAS_HUC condition (Michal)
Updating more functions with unified message (Sagar)
Suggested by : Michal Wajdeczko <michal.wajdec...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 53 +
1 file changed, 36 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index add6af4..462e448 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1641,7 +1641,7 @@ static int i915_fbc_status(struct seq_file *m, void
*unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
if (!HAS_FBC(dev_priv)) {
- seq_puts(m, "FBC unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -1809,7 +1809,7 @@ static int i915_ring_freq_table(struct seq_file *m, void
*unused)
unsigned int max_gpu_freq, min_gpu_freq;
if (!HAS_LLC(dev_priv)) {
- seq_puts(m, "unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2361,8 +2361,10 @@ static int i915_huc_load_status_info(struct seq_file *m,
void *data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct drm_printer p;
- if (!HAS_HUC_UCODE(dev_priv))
+ if (!HAS_HUC(dev_priv)) {
+ seq_puts(m, "not supported\n");
return 0;
+ }
p = drm_seq_file_printer(m);
intel_uc_fw_dump(_priv->huc.fw, );
@@ -2380,8 +2382,10 @@ static int i915_guc_load_status_info(struct seq_file *m,
void *data)
struct drm_printer p;
u32 tmp, i;
- if (!HAS_GUC_UCODE(dev_priv))
+ if (!HAS_GUC(dev_priv)) {
+ seq_puts(m, "not supported\n");
return 0;
+ }
p = drm_seq_file_printer(m);
intel_uc_fw_dump(_priv->guc.fw, );
@@ -2461,9 +2465,11 @@ static bool check_guc_submission(struct seq_file *m)
if (!guc->execbuf_client) {
seq_printf(m, "GuC submission %s\n",
- HAS_GUC_SCHED(dev_priv) ?
- "disabled" :
- "not supported");
+ HAS_GUC(dev_priv) ?
+ "not supported" :
+ NEEDS_GUC_FW(dev_priv) ?
+ "disabled" :
+ "failed");
return false;
}
@@ -2652,7 +2658,7 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
bool enabled = false;
if (!HAS_PSR(dev_priv)) {
- seq_puts(m, "PSR not supported\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2805,7 +2811,7 @@ static int i915_runtime_pm_status(struct seq_file *m,
void *unused)
struct pci_dev *pdev = dev_priv->drm.pdev;
if (!HAS_RUNTIME_PM(dev_priv))
- seq_puts(m, "Runtime power management not supported\n");
+ seq_puts(m, "not supported\n");
seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
seq_printf(m, "IRQs disabled: %s\n",
@@ -3407,9 +3413,13 @@ static int i915_ipc_status_show(struct seq_file *m, void
*data)
static int i915_ipc_status_open(struct inode *inode, struct file *file)
{
struct drm_i915_private *dev_priv = inode->i_private;
+ struct seq_file *m;
- if (!HAS_IPC(dev_priv))
- return -ENODEV;
+ if (!HAS_IPC(dev_priv)) {
+ seq_puts(m, "not supported\n");
+ return 0;
+ }
+
return single_open(file, i915_ipc_status_show, dev_priv);
}
@@ -3914,9 +3924,12 @@ static int cur_wm_latency_show(struct seq_file *m, void
*data)
static int pri_wm_latency_open(struct inode *inode, struct file *file)
{
struct drm_i915_private *dev_priv = inode->i_private;
+ struct seq_file *m;
- if (IN
[Intel-gfx] [PATCH v8 2/6] drm/i915/guc : Removing i915_modparams.enable_guc_loading module parameter
We currently have two module parameters that control GuC:
"enable_guc_loading" and "enable_guc_submission". Whenever
we need submission=1, we also need loading=1.We also need
loading=1 when we want to want to verify the HuC, which
is every time we have a HuC (but all platforms with HuC
have a GuC and viceversa).
Also if we have HuC have firmware to be loaded, we need to
have GuC to actually load it. So if the user wants to avoid
the GuC from getting loaded, they must not have a HuC
firmware to be loaded, in addition to not using submission.
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, Re-factoring code as per review (Michal)
v4: Rebase
v5: Separating message unification into a separate patch
v6: Re-factoring code (Sagar, Michal)
Rebase
v7: Applying review comments (Sagar)
Rebase
v8: Change to NEEDS_GUC_FW (Chris)
Applying review comments (Michal)
Clarifying commit message (Joonas)
Suggested by: Oscar Mateo <oscar.ma...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 9 +++--
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/i915_params.c | 4 ---
drivers/gpu/drm/i915/i915_params.h | 1 -
drivers/gpu/drm/i915/intel_uc.c | 57 +++--
8 files changed, 34 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 8edd029..25c47a0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2465,7 +2465,7 @@ static bool check_guc_submission(struct seq_file *m)
if (!guc->execbuf_client) {
seq_printf(m, "GuC submission %s\n",
- HAS_GUC_SCHED(dev_priv) ?
+ HAS_GUC(dev_priv) ?
"disabled" :
"not supported");
return false;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f01c800..ede5004 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3205,9 +3205,11 @@ static inline unsigned int i915_sg_segment_size(void)
*/
#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
-#define HAS_GUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_GUC_SCHED(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_HUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
+#define HAS_GUC_UCODE(dev_priv) ((dev_priv)->guc.fw.path != NULL)
+#define HAS_HUC_UCODE(dev_priv) ((dev_priv)->huc.fw.path != NULL)
+
+#define NEEDS_GUC_FW(dev_priv) \
+ (HAS_GUC(dev_priv) && \
+ (i915_modparams.enable_guc_submission ||
HAS_HUC_UCODE(dev_priv)))
#define HAS_RESOURCE_STREAMER(dev_priv)
((dev_priv)->info.has_resource_streamer)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 5bf96a2..4f0692e 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -314,7 +314,7 @@ static u32 default_desc_template(const struct
drm_i915_private *i915,
* present or not in use we still need a small bias as ring wraparound
* at offset 0 sometimes hangs. No idea why.
*/
- if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading)
+ if (NEEDS_GUC_FW(dev_priv))
ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
else
ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 527a2d2..9d78233 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3481,7 +3481,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
* currently don't have any bits spare to pass in this upper
* restriction!
*/
- if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading) {
+ if (NEEDS_GUC_FW(dev_priv)) {
ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP);
ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
}
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b1296a5..ec76aac 100644
--- a/drivers
[Intel-gfx] [PATCH v8 0/6] drm/i915/guc : Removing enable_guc_loading module and Decoupling logs and ADS from submission
The first patch simply unifies different seq_puts messages found in debugfs. Patch 2,3 and 4 involve replacing te enable_guc_loading module. Patches 5 and 6 deal with decoupling GuC logs and ADS from submission. Cc: Anusha Srivatsa <anusha.sriva...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Sujaritha Sundaresan (6): drm/i915 : Unifying seq_puts messages for feature support drm/i915/guc : Removing i915_modparams.enable_guc_loading module parameter drm/i915/guc : GEM_BUG_ON for GuC reset function drm/i915/guc : Updating GuC and HuC firmware select function drm/i915/guc : Updating GuC logs to remove enable_guc_submission parameter drm/i915/guc : Decouple logs and ADS from submission drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_debugfs.c| 17 ++-- drivers/gpu/drm/i915/i915_drv.h| 8 +- drivers/gpu/drm/i915/i915_gem_context.c| 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c| 2 +- drivers/gpu/drm/i915/i915_guc_submission.c | 139 +-- drivers/gpu/drm/i915/i915_irq.c| 2 +- drivers/gpu/drm/i915/i915_params.c | 4 - drivers/gpu/drm/i915/i915_params.h | 1 - drivers/gpu/drm/i915/intel_guc_ads.c | 149 + drivers/gpu/drm/i915/intel_guc_ads.h | 33 +++ drivers/gpu/drm/i915/intel_guc_fw.c| 10 +- drivers/gpu/drm/i915/intel_guc_fw.h| 2 +- drivers/gpu/drm/i915/intel_guc_log.c | 8 +- drivers/gpu/drm/i915/intel_huc.c | 3 +- drivers/gpu/drm/i915/intel_uc.c| 101 --- drivers/gpu/drm/i915/intel_uncore.c| 3 +- 17 files changed, 279 insertions(+), 205 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.c create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.h -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 3/6] drm/i915/guc : GEM_BUG_ON for GuC reset function
Including GEM_BUG_ON for GuC reset function in intel_uncore.
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 20e3c65c..c631b0e 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1803,8 +1803,7 @@ int intel_guc_reset(struct drm_i915_private *dev_priv)
{
int ret;
- if (!HAS_GUC(dev_priv))
- return -EINVAL;
+ GEM_BUG_ON(!HAS_GUC(dev_priv));
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 6/6] drm/i915/guc : Decouple logs and ADS from submission
The Additional Data Struct (ADS) contains objects that are required by
guc post FW load and are not necessarily submission-only (although that's
our current only use-case). If in the future we load GuC with submission
disabled to use some other GuC feature we might still end up requiring
something inside the ADS, so it makes more sense for them to be always
created if GuC is loaded.
Similarly, we still want to access GuC logs even if GuC submission is
disable to debug issues with GuC loading or with wathever we're using
GuC for.
To make a concrete example, the pages used by GuC to save state during
suspend are allocated as part of the ADS.
v3: Group initialization of GuC objects
v2: Decoupling ADS together with logs
v3: Re-factoring code as per review (Michal)
v4: Rebase
v5: Separating group object initialization into next patch
Clarifying commit message
v6: Reverting to goto err format (Michal)
Moved guc_ads functions to dedicated file
Rebase
v7: Rebase
v8: Applying review comments (Michal)
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_guc_submission.c | 139 +--
drivers/gpu/drm/i915/intel_guc_ads.c | 149 +
drivers/gpu/drm/i915/intel_guc_ads.h | 33 +++
drivers/gpu/drm/i915/intel_uc.c| 38 +++-
5 files changed, 220 insertions(+), 140 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.c
create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6c3b048..d7ce07e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -62,6 +62,7 @@ i915-y += i915_cmd_parser.o \
i915-y += intel_uc.o \
intel_uc_fw.o \
intel_guc.o \
+ intel_guc_ads.o \
intel_guc_ct.o \
intel_guc_log.o \
intel_guc_fw.o \
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index a2e8114..3a56429 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -72,13 +72,6 @@
* ELSP context descriptor dword into Work Item.
* See guc_wq_item_append()
*
- * ADS:
- * The Additional Data Struct (ADS) has pointers for different buffers used by
- * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
- * scheduling policies (guc_policies), a structure describing a collection of
- * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
- * its internal state for sleep.
- *
*/
static inline bool is_high_priority(struct i915_guc_client* client)
@@ -855,115 +848,6 @@ static void guc_client_free(struct i915_guc_client
*client)
kfree(client);
}
-static void guc_policy_init(struct guc_policy *policy)
-{
- policy->execution_quantum = POLICY_DEFAULT_EXECUTION_QUANTUM_US;
- policy->preemption_time = POLICY_DEFAULT_PREEMPTION_TIME_US;
- policy->fault_time = POLICY_DEFAULT_FAULT_TIME_US;
- policy->policy_flags = 0;
-}
-
-static void guc_policies_init(struct guc_policies *policies)
-{
- struct guc_policy *policy;
- u32 p, i;
-
- policies->dpc_promote_time = POLICY_DEFAULT_DPC_PROMOTE_TIME_US;
- policies->max_num_work_items = POLICY_MAX_NUM_WI;
-
- for (p = 0; p < GUC_CLIENT_PRIORITY_NUM; p++) {
- for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) {
- policy = >policy[p][i];
-
- guc_policy_init(policy);
- }
- }
-
- policies->is_valid = 1;
-}
-
-/*
- * The first 80 dwords of the register state context, containing the
- * execlists and ppgtt registers.
- */
-#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
-
-static int guc_ads_create(struct intel_guc *guc)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- struct i915_vma *vma;
- struct page *page;
- /* The ads obj includes the struct itself and buffers passed to GuC */
- struct {
- struct guc_ads ads;
- struct guc_policies policies;
- struct guc_mmio_reg_state reg_state;
- u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
- } __packed *blob;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
- const u32 skipped_offset = LRC_HEADER_PAGES * PAGE_SIZE;
- const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
- u32 base;
-
- GEM_BUG_ON(guc->ads_vma);
-
- vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(s
[Intel-gfx] [PATCH v8 5/6] drm/i915/guc : Updating GuC logs to remove enable_guc_submission parameter
Replacing conditions to remove dependance on enable_guc_submission
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/intel_guc_log.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c
b/drivers/gpu/drm/i915/intel_guc_log.c
index 76d3eb1..c9f0167 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -505,8 +505,7 @@ static void guc_flush_logs(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
- if (!i915_modparams.enable_guc_submission ||
- (i915_modparams.guc_log_level < 0))
+ if (!NEEDS_GUC_FW(dev_priv))
return;
/* First disable the interrupts, will be renabled afterwards */
@@ -646,8 +645,7 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv,
u64 control_val)
void i915_guc_log_register(struct drm_i915_private *dev_priv)
{
- if (!i915_modparams.enable_guc_submission ||
- (i915_modparams.guc_log_level < 0))
+ if (!NEEDS_GUC_FW(dev_priv))
return;
mutex_lock(_priv->drm.struct_mutex);
@@ -657,7 +655,7 @@ void i915_guc_log_register(struct drm_i915_private
*dev_priv)
void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
{
- if (!i915_modparams.enable_guc_submission)
+ if (!NEEDS_GUC_FW(dev_priv))
return;
mutex_lock(_priv->drm.struct_mutex);
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 4/6] drm/i915/guc : Updating GuC and HuC firmware select function
Updating GuC and HuC firmware select function to support removing
i915_modparams.enable_guc_loading module parameter.
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, Re-factoring code as per review (Michal)
v4: Rebase
v5: Separating message unification into a separate patch
v6: Re-factoring code (Sagar, Michal)
Rebase
v7: Separating from previuos patch (Sagar)
Rebase
v8: Including change to intel_uc.c
Applying review comments (Michal)
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/intel_guc_fw.c | 10 +++---
drivers/gpu/drm/i915/intel_guc_fw.h | 2 +-
drivers/gpu/drm/i915/intel_huc.c| 3 ++-
drivers/gpu/drm/i915/intel_uc.c | 6 ++
4 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index ef67a36..b9f834f 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -60,10 +60,8 @@
* intel_guc_fw_select() - selects GuC firmware for uploading
*
* @guc: intel_guc struct
- *
- * Return: zero when we know firmware, non-zero in other case
*/
-int intel_guc_fw_select(struct intel_guc *guc)
+void intel_guc_fw_select(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -90,11 +88,9 @@ int intel_guc_fw_select(struct intel_guc *guc)
guc->fw.major_ver_wanted = GLK_FW_MAJOR;
guc->fw.minor_ver_wanted = GLK_FW_MINOR;
} else {
- DRM_ERROR("No GuC firmware known for platform with GuC!\n");
- return -ENOENT;
+ DRM_ERROR("No GuC FW known for platform with GuC!\n");
+ return;
}
-
- return 0;
}
/*
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.h
b/drivers/gpu/drm/i915/intel_guc_fw.h
index 023f5ba..7f6ccaf 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.h
+++ b/drivers/gpu/drm/i915/intel_guc_fw.h
@@ -27,7 +27,7 @@
struct intel_guc;
-int intel_guc_fw_select(struct intel_guc *guc);
+void intel_guc_fw_select(struct intel_guc *guc);
int intel_guc_fw_upload(struct intel_guc *guc);
#endif
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index c8a48cb..4e700ab 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -108,7 +108,8 @@ void intel_huc_select_fw(struct intel_huc *huc)
huc->fw.major_ver_wanted = GLK_HUC_FW_MAJOR;
huc->fw.minor_ver_wanted = GLK_HUC_FW_MINOR;
} else {
- DRM_ERROR("No HuC firmware known for platform with HuC!\n");
+ if (HAS_GUC(dev_priv))
+ DRM_ERROR("No HuC FW known for platform with HuC!\n");
return;
}
}
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 9369ade..dc978a0 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -82,11 +82,17 @@ void intel_uc_sanitize_options(struct drm_i915_private
*dev_priv)
void intel_uc_init_early(struct drm_i915_private *dev_priv)
{
+ struct intel_guc *guc = _priv->guc;
+ struct intel_huc *huc = _priv->huc;
intel_guc_init_early(_priv->guc);
+ intel_guc_fw_select(guc);
+ intel_huc_select_fw(huc);
}
void intel_uc_init_fw(struct drm_i915_private *dev_priv)
{
+ if (!HAS_GUC(dev_priv))
+ return;
intel_uc_fw_fetch(dev_priv, _priv->huc.fw);
intel_uc_fw_fetch(dev_priv, _priv->guc.fw);
}
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 1/6] drm/i915 : Unifying seq_puts messages for feature support
Unifying the various seq_puts messages in debugfs to the simplest one for
feature support.
v2: Clarifying the commit message (Anusha)
v3: Re-factoring code as per review (Michal)
v4: Rebase
v5: Split from following patch
v6: Re-factoring code (Michal, Sagar)
Clarifying commit message (Sagar)
v7: Generalizing subject to drm/i915 (Sagar)
v8: Omitting DRRS seq_puts unification (Michal)
Suggested by: Michal Wajdeczko <michal.wajdec...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index c65e381..8edd029 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1641,7 +1641,7 @@ static int i915_fbc_status(struct seq_file *m, void
*unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
if (!HAS_FBC(dev_priv)) {
- seq_puts(m, "FBC unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -1809,7 +1809,7 @@ static int i915_ring_freq_table(struct seq_file *m, void
*unused)
unsigned int max_gpu_freq, min_gpu_freq;
if (!HAS_LLC(dev_priv)) {
- seq_puts(m, "unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2361,8 +2361,10 @@ static int i915_huc_load_status_info(struct seq_file *m,
void *data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct drm_printer p;
- if (!HAS_HUC_UCODE(dev_priv))
+ if (!HAS_GUC(dev_priv)) {
+ seq_puts(m, "not supported\n");
return 0;
+ }
p = drm_seq_file_printer(m);
intel_uc_fw_dump(_priv->huc.fw, );
@@ -2380,8 +2382,10 @@ static int i915_guc_load_status_info(struct seq_file *m,
void *data)
struct drm_printer p;
u32 tmp, i;
- if (!HAS_GUC_UCODE(dev_priv))
+ if (!HAS_GUC(dev_priv)) {
+ seq_puts(m, "not supported\n");
return 0;
+ }
p = drm_seq_file_printer(m);
intel_uc_fw_dump(_priv->guc.fw, );
@@ -2650,7 +2654,7 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
bool enabled = false;
if (!HAS_PSR(dev_priv)) {
- seq_puts(m, "PSR not supported\n");
+ seq_puts(m, "not supported\n");
return 0;
}
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 3/4] drm/i915/guc : Updating GuC and HuC FW select function
Updating GuC and HuC firmware select function to support removing
i915_modparams.enable_guc_loading module parameter.
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, Re-factoring code as per review (Michal)
v4: Rebase
v5: Separating message unification into a separate patch
v6: Re-factoring code (Sagar, Michal)
Rebase
v7: Separating from previuos patch (Sagar)
Rebase
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
---
drivers/gpu/drm/i915/intel_guc_fw.c | 9 -
drivers/gpu/drm/i915/intel_guc_fw.h | 2 +-
drivers/gpu/drm/i915/intel_huc.c| 4 +++-
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index ef67a36..5bffeef 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -63,7 +63,7 @@
*
* Return: zero when we know firmware, non-zero in other case
*/
-int intel_guc_fw_select(struct intel_guc *guc)
+void intel_guc_fw_select(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -90,11 +90,10 @@ int intel_guc_fw_select(struct intel_guc *guc)
guc->fw.major_ver_wanted = GLK_FW_MAJOR;
guc->fw.minor_ver_wanted = GLK_FW_MINOR;
} else {
- DRM_ERROR("No GuC firmware known for platform with GuC!\n");
- return -ENOENT;
+ if (!HAS_GUC(dev_priv))
+ DRM_ERROR("No GuC FW known for platform with GuC!\n");
+ return;
}
-
- return 0;
}
/*
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.h
b/drivers/gpu/drm/i915/intel_guc_fw.h
index 023f5ba..7f6ccaf 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.h
+++ b/drivers/gpu/drm/i915/intel_guc_fw.h
@@ -27,7 +27,7 @@
struct intel_guc;
-int intel_guc_fw_select(struct intel_guc *guc);
+void intel_guc_fw_select(struct intel_guc *guc);
int intel_guc_fw_upload(struct intel_guc *guc);
#endif
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index c8a48cb..fc61779 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -108,7 +108,9 @@ void intel_huc_select_fw(struct intel_huc *huc)
huc->fw.major_ver_wanted = GLK_HUC_FW_MAJOR;
huc->fw.minor_ver_wanted = GLK_HUC_FW_MINOR;
} else {
- DRM_ERROR("No HuC firmware known for platform with HuC!\n");
+ /* For now, everything with a GuC also has a HuC */
+ if (HAS_GUC(dev_priv))
+ DRM_ERROR("No HuC FW known for platform with HuC!\n");
return;
}
}
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 4/4] drm/i915/guc : Decouple logs and ADS from submission
The Additional Data Struct (ADS) contains objects that are required by
guc post FW load and are not necessarily submission-only (although that's
our current only use-case). If in the future we load GuC with submission
disabled to use some other GuC feature we might still end up requiring
something inside the ADS, so it makes more sense for them to be always
created if GuC is loaded.
Similarly, we still want to access GuC logs even if GuC submission is
disable to debug issues with GuC loading or with wathever we're using
GuC for.
To make a concrete example, the pages used by GuC to save state during
suspend are allocated as part of the ADS.
v3: Group initialization of GuC objects
v2: Decoupling ADS together with logs
v3: Re-factoring code as per review (Michal)
v4: Rebase
v5: Separating group object initialization into next patch
Clarifying commit message
v6: Reverting to goto err format (Michal)
Moved guc_ads functions to dedicated file
Rebase
v7: Rebase
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_guc_submission.c | 106 +
drivers/gpu/drm/i915/intel_guc.h | 1 +
drivers/gpu/drm/i915/intel_guc_ads.c | 119 +
drivers/gpu/drm/i915/intel_guc_ads.h | 31
drivers/gpu/drm/i915/intel_guc_log.c | 6 +-
drivers/gpu/drm/i915/intel_uc.c| 39 +-
7 files changed, 195 insertions(+), 108 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.c
create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6c3b048..d7ce07e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -62,6 +62,7 @@ i915-y += i915_cmd_parser.o \
i915-y += intel_uc.o \
intel_uc_fw.o \
intel_guc.o \
+ intel_guc_ads.o \
intel_guc_ct.o \
intel_guc_log.o \
intel_guc_fw.o \
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index a2e8114..d3c0b01 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -26,6 +26,7 @@
#include
#include "i915_guc_submission.h"
+#include "intel_guc_ads.h"
#include "i915_drv.h"
/**
@@ -72,13 +73,6 @@
* ELSP context descriptor dword into Work Item.
* See guc_wq_item_append()
*
- * ADS:
- * The Additional Data Struct (ADS) has pointers for different buffers used by
- * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
- * scheduling policies (guc_policies), a structure describing a collection of
- * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
- * its internal state for sleep.
- *
*/
static inline bool is_high_priority(struct i915_guc_client* client)
@@ -863,7 +857,7 @@ static void guc_policy_init(struct guc_policy *policy)
policy->policy_flags = 0;
}
-static void guc_policies_init(struct guc_policies *policies)
+void i915_guc_policies_init(struct guc_policies *policies)
{
struct guc_policy *policy;
u32 p, i;
@@ -883,88 +877,6 @@ static void guc_policies_init(struct guc_policies
*policies)
}
/*
- * The first 80 dwords of the register state context, containing the
- * execlists and ppgtt registers.
- */
-#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
-
-static int guc_ads_create(struct intel_guc *guc)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- struct i915_vma *vma;
- struct page *page;
- /* The ads obj includes the struct itself and buffers passed to GuC */
- struct {
- struct guc_ads ads;
- struct guc_policies policies;
- struct guc_mmio_reg_state reg_state;
- u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
- } __packed *blob;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
- const u32 skipped_offset = LRC_HEADER_PAGES * PAGE_SIZE;
- const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
- u32 base;
-
- GEM_BUG_ON(guc->ads_vma);
-
- vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(sizeof(*blob)));
- if (IS_ERR(vma))
- return PTR_ERR(vma);
-
- guc->ads_vma = vma;
-
- page = i915_vma_first_page(vma);
- blob = kmap(page);
-
- /* GuC scheduling policies */
- guc_policies_init(>policies);
-
- /* MMIO reg state */
- for_each_engine(eng
[Intel-gfx] [PATCH v7 2/4] drm/i915/guc : Removing i915_modparams.enable_guc_loading module parameter
We currently have two module parameters that control GuC:
"enable_guc_loading" and "enable_guc_submission". Whenever
we need i915_modparams.enable_guc_submission=1, we also need
enable_guc_loading=1. We also need enable_guc_loading=1 when
we want to verify the HuC, which is every time we have a HuC
(but all platforms with HuC have a GuC and viceversa).
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, Re-factoring code as per review (Michal)
v4: Rebase
v5: Separating message unification into a separate patch
v6: Re-factoring code (Sagar, Michal)
Rebase
v7: Applying review comments (Sagar)
Rebase
Suggested by: Oscar Mateo <oscar.ma...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
drivers/gpu/drm/i915/i915_drv.h | 9 +++--
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/i915_params.c | 4 --
drivers/gpu/drm/i915/i915_params.h | 1 -
drivers/gpu/drm/i915/intel_uc.c | 69 ++---
drivers/gpu/drm/i915/intel_uncore.c | 3 +-
9 files changed, 50 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index ac25d63..bc31769 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2361,7 +2361,7 @@ static int i915_huc_load_status_info(struct seq_file *m,
void *data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct intel_uc_fw *huc_fw = _priv->huc.fw;
- if (!HAS_HUC_UCODE(dev_priv)) {
+ if (!HAS_GUC(dev_priv)) {
seq_puts(m, "not supported\n");
return 0;
}
@@ -2397,7 +2397,7 @@ static int i915_guc_load_status_info(struct seq_file *m,
void *data)
struct intel_uc_fw *guc_fw = _priv->guc.fw;
u32 tmp, i;
- if (!HAS_GUC_UCODE(dev_priv)) {
+ if (!HAS_GUC(dev_priv)) {
seq_puts(m, "not supported\n");
return 0;
}
@@ -2496,7 +2496,7 @@ static bool check_guc_submission(struct seq_file *m)
if (!guc->execbuf_client) {
seq_printf(m, "GuC submission %s\n",
- HAS_GUC_SCHED(dev_priv) ?
+ HAS_GUC(dev_priv) ?
"disabled" :
"not supported");
return false;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dd141b2..5b9bdd0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3201,9 +3201,12 @@ static inline unsigned int i915_sg_segment_size(void)
*/
#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
-#define HAS_GUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_GUC_SCHED(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_HUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
+#define HAS_GUC_UCODE(dev_priv) ((dev_priv)->guc.fw.path != NULL)
+#define HAS_HUC_UCODE(dev_priv) ((dev_priv)->huc.fw.path != NULL)
+
+#define NEEDS_GUC_LOADING(dev_priv) \
+ (HAS_GUC(dev_priv) && \
+ (i915_modparams.enable_guc_submission || HAS_HUC_UCODE(dev_priv)))
#define HAS_RESOURCE_STREAMER(dev_priv)
((dev_priv)->info.has_resource_streamer)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 5bf96a2..692d609 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -314,7 +314,7 @@ static u32 default_desc_template(const struct
drm_i915_private *i915,
* present or not in use we still need a small bias as ring wraparound
* at offset 0 sometimes hangs. No idea why.
*/
- if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading)
+ if (NEEDS_GUC_LOADING(dev_priv))
ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
else
ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 527a2d2..0bbc8f0 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3481,7 +3481,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
* currently don't have any bits spare to pass in this upper
* restriction!
*/
- if (HAS_GUC(dev_priv) && i915_modparams.e
[Intel-gfx] [PATCH v7 0/4] drm/i915/guc : Removing enable_guc_loading module and Decoupling logs and ADS from submission
The first patch simply unifies different seq_puts messages found in debugfs. Patch 2 and 3 involve replacing te enable_guc_loading module. Patch 4 deals with decoupling GuC logs and ADS from submission. Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Anusha Srivatsa <anusha.sriva...@intel.com> Sujaritha Sundaresan (4): drm/i915 : Unifying seq_puts messages for feature support drm/i915/guc : Removing i915_modparams.enable_guc_loading module parameter drm/i915/guc : Updating GuC and HuC FW select function drm/i915/guc : Decouple logs and ADS from submission drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_debugfs.c| 22 -- drivers/gpu/drm/i915/i915_drv.h| 9 ++- drivers/gpu/drm/i915/i915_gem_context.c| 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c| 2 +- drivers/gpu/drm/i915/i915_guc_submission.c | 106 + drivers/gpu/drm/i915/i915_irq.c| 2 +- drivers/gpu/drm/i915/i915_params.c | 4 - drivers/gpu/drm/i915/i915_params.h | 1 - drivers/gpu/drm/i915/intel_guc.h | 1 + drivers/gpu/drm/i915/intel_guc_ads.c | 119 + drivers/gpu/drm/i915/intel_guc_ads.h | 31 drivers/gpu/drm/i915/intel_guc_fw.c| 9 +-- drivers/gpu/drm/i915/intel_guc_fw.h| 2 +- drivers/gpu/drm/i915/intel_guc_log.c | 6 +- drivers/gpu/drm/i915/intel_huc.c | 4 +- drivers/gpu/drm/i915/intel_uc.c| 108 ++ drivers/gpu/drm/i915/intel_uncore.c| 3 +- 18 files changed, 264 insertions(+), 168 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.c create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.h -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 1/4] drm/i915 : Unifying seq_puts messages for feature support
Unifying the various seq_puts messages in debugfs to the simplest one for
feature support.
v2: Clarifying the commit message (Anusha)
v3: Re-factoring code as per review (Michal)
v4: Rebase
v5: Split from following patch
v6: Re-factoring code (Michal, Sagar)
Clarifying commit message (Sagar)
v7: Generalizing subject to drm/i915 (Sagar)
Suggested by: Michal Wajdeczko <michal.wajdec...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 40287e9..ac25d63 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1641,7 +1641,7 @@ static int i915_fbc_status(struct seq_file *m, void
*unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
if (!HAS_FBC(dev_priv)) {
- seq_puts(m, "FBC unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -1809,7 +1809,7 @@ static int i915_ring_freq_table(struct seq_file *m, void
*unused)
unsigned int max_gpu_freq, min_gpu_freq;
if (!HAS_LLC(dev_priv)) {
- seq_puts(m, "unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2361,8 +2361,11 @@ static int i915_huc_load_status_info(struct seq_file *m,
void *data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct intel_uc_fw *huc_fw = _priv->huc.fw;
- if (!HAS_HUC_UCODE(dev_priv))
+ if (!HAS_HUC_UCODE(dev_priv)) {
+ seq_puts(m, "not supported\n");
return 0;
+ }
+
seq_puts(m, "HuC firmware status:\n");
seq_printf(m, "\tpath: %s\n", huc_fw->path);
@@ -2394,8 +2397,11 @@ static int i915_guc_load_status_info(struct seq_file *m,
void *data)
struct intel_uc_fw *guc_fw = _priv->guc.fw;
u32 tmp, i;
- if (!HAS_GUC_UCODE(dev_priv))
+ if (!HAS_GUC_UCODE(dev_priv)) {
+ seq_puts(m, "not supported\n");
return 0;
+ }
+
seq_printf(m, "GuC firmware status:\n");
seq_printf(m, "\tpath: %s\n",
@@ -2679,7 +2685,7 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
bool enabled = false;
if (!HAS_PSR(dev_priv)) {
- seq_puts(m, "PSR not supported\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -3546,7 +3552,7 @@ static void drrs_status_per_crtc(struct seq_file *m,
mutex_lock(>mutex);
/* DRRS Supported */
- seq_puts(m, "\tDRRS Supported: Yes\n");
+ seq_puts(m, "supported\n");
/* disable_drrs() will make drrs->dp NULL */
if (!drrs->dp) {
@@ -3578,7 +3584,7 @@ static void drrs_status_per_crtc(struct seq_file *m,
mutex_unlock(>mutex);
} else {
/* DRRS not supported. Print the VBT parameter*/
- seq_puts(m, "\tDRRS Supported : No");
+ seq_puts(m, "not supported\n");
}
seq_puts(m, "\n");
}
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 4/4] drm/i915/guc : Decouple logs and ADS from submission
The Additional Data Struct (ADS) contains objects that are required by
guc post FW load and are not necessarily submission-only (although that's
our current only use-case). If in the future we load GuC with submission
disabled to use some other GuC feature we might still end up requiring
something inside the ADS, so it makes more sense for them to be always
created if GuC is loaded.
Similarly, we still want to access GuC logs even if GuC submission is
disable to debug issues with GuC loading or with wathever we're using
GuC for.
To make a concrete example, the pages used by GuC to save state during
suspend are allocated as part of the ADS.
v3: Group initialization of GuC objects
v2: Decoupling ADS together with logs
v3: Re-factoring code as per review (Michal)
v4: Rebase
v5: Separating group object initialization into next patch
Clarifying commit message
v6: Reverting to goto err format (Michal)
Moved guc_ads functions to dedicated file
Rebase
v7: Rebase
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_guc_submission.c | 106 +
drivers/gpu/drm/i915/intel_guc.h | 1 +
drivers/gpu/drm/i915/intel_guc_ads.c | 119 +
drivers/gpu/drm/i915/intel_guc_ads.h | 31
drivers/gpu/drm/i915/intel_guc_log.c | 6 +-
drivers/gpu/drm/i915/intel_uc.c| 39 +-
7 files changed, 195 insertions(+), 108 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.c
create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6c3b048..d7ce07e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -62,6 +62,7 @@ i915-y += i915_cmd_parser.o \
i915-y += intel_uc.o \
intel_uc_fw.o \
intel_guc.o \
+ intel_guc_ads.o \
intel_guc_ct.o \
intel_guc_log.o \
intel_guc_fw.o \
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index a2e8114..d3c0b01 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -26,6 +26,7 @@
#include
#include "i915_guc_submission.h"
+#include "intel_guc_ads.h"
#include "i915_drv.h"
/**
@@ -72,13 +73,6 @@
* ELSP context descriptor dword into Work Item.
* See guc_wq_item_append()
*
- * ADS:
- * The Additional Data Struct (ADS) has pointers for different buffers used by
- * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
- * scheduling policies (guc_policies), a structure describing a collection of
- * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
- * its internal state for sleep.
- *
*/
static inline bool is_high_priority(struct i915_guc_client* client)
@@ -863,7 +857,7 @@ static void guc_policy_init(struct guc_policy *policy)
policy->policy_flags = 0;
}
-static void guc_policies_init(struct guc_policies *policies)
+void i915_guc_policies_init(struct guc_policies *policies)
{
struct guc_policy *policy;
u32 p, i;
@@ -883,88 +877,6 @@ static void guc_policies_init(struct guc_policies
*policies)
}
/*
- * The first 80 dwords of the register state context, containing the
- * execlists and ppgtt registers.
- */
-#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
-
-static int guc_ads_create(struct intel_guc *guc)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- struct i915_vma *vma;
- struct page *page;
- /* The ads obj includes the struct itself and buffers passed to GuC */
- struct {
- struct guc_ads ads;
- struct guc_policies policies;
- struct guc_mmio_reg_state reg_state;
- u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
- } __packed *blob;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
- const u32 skipped_offset = LRC_HEADER_PAGES * PAGE_SIZE;
- const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
- u32 base;
-
- GEM_BUG_ON(guc->ads_vma);
-
- vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(sizeof(*blob)));
- if (IS_ERR(vma))
- return PTR_ERR(vma);
-
- guc->ads_vma = vma;
-
- page = i915_vma_first_page(vma);
- blob = kmap(page);
-
- /* GuC scheduling policies */
- guc_policies_init(>policies);
-
- /* MMIO reg state */
- for_each_engine(eng
[Intel-gfx] [PATCH v7 2/4] drm/i915/guc : Removing i915_modparams.enable_guc_loading module parameter
We currently have two module parameters that control GuC:
"enable_guc_loading" and "enable_guc_submission". Whenever
we need i915_modparams.enable_guc_submission=1, we also need
enable_guc_loading=1. We also need enable_guc_loading=1 when
we want to verify the HuC, which is every time we have a HuC
(but all platforms with HuC have a GuC and viceversa).
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, Re-factoring code as per review (Michal)
v4: Rebase
v5: Separating message unification into a separate patch
v6: Re-factoring code (Sagar, Michal)
Rebase
v7: Applying review comments (Sagar)
Rebase
Suggested by: Oscar Mateo <oscar.ma...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
drivers/gpu/drm/i915/i915_drv.h | 9 +++--
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/i915_params.c | 4 --
drivers/gpu/drm/i915/i915_params.h | 1 -
drivers/gpu/drm/i915/intel_uc.c | 69 ++---
drivers/gpu/drm/i915/intel_uncore.c | 3 +-
9 files changed, 50 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index ac25d63..bc31769 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2361,7 +2361,7 @@ static int i915_huc_load_status_info(struct seq_file *m,
void *data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct intel_uc_fw *huc_fw = _priv->huc.fw;
- if (!HAS_HUC_UCODE(dev_priv)) {
+ if (!HAS_GUC(dev_priv)) {
seq_puts(m, "not supported\n");
return 0;
}
@@ -2397,7 +2397,7 @@ static int i915_guc_load_status_info(struct seq_file *m,
void *data)
struct intel_uc_fw *guc_fw = _priv->guc.fw;
u32 tmp, i;
- if (!HAS_GUC_UCODE(dev_priv)) {
+ if (!HAS_GUC(dev_priv)) {
seq_puts(m, "not supported\n");
return 0;
}
@@ -2496,7 +2496,7 @@ static bool check_guc_submission(struct seq_file *m)
if (!guc->execbuf_client) {
seq_printf(m, "GuC submission %s\n",
- HAS_GUC_SCHED(dev_priv) ?
+ HAS_GUC(dev_priv) ?
"disabled" :
"not supported");
return false;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dd141b2..5b9bdd0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3201,9 +3201,12 @@ static inline unsigned int i915_sg_segment_size(void)
*/
#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
-#define HAS_GUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_GUC_SCHED(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_HUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
+#define HAS_GUC_UCODE(dev_priv) ((dev_priv)->guc.fw.path != NULL)
+#define HAS_HUC_UCODE(dev_priv) ((dev_priv)->huc.fw.path != NULL)
+
+#define NEEDS_GUC_LOADING(dev_priv) \
+ (HAS_GUC(dev_priv) && \
+ (i915_modparams.enable_guc_submission || HAS_HUC_UCODE(dev_priv)))
#define HAS_RESOURCE_STREAMER(dev_priv)
((dev_priv)->info.has_resource_streamer)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 5bf96a2..692d609 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -314,7 +314,7 @@ static u32 default_desc_template(const struct
drm_i915_private *i915,
* present or not in use we still need a small bias as ring wraparound
* at offset 0 sometimes hangs. No idea why.
*/
- if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading)
+ if (NEEDS_GUC_LOADING(dev_priv))
ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
else
ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 527a2d2..0bbc8f0 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3481,7 +3481,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
* currently don't have any bits spare to pass in this upper
* restriction!
*/
- if (HAS_GUC(dev_priv) && i915_modparams.e
[Intel-gfx] [PATCH v7 1/4] drm/i915 : Unifying seq_puts messages for feature support
Unifying the various seq_puts messages in debugfs to the simplest one for
feature support.
v2: Clarifying the commit message (Anusha)
v3: Re-factoring code as per review (Michal)
v4: Rebase
v5: Split from following patch
v6: Re-factoring code (Michal, Sagar)
Clarifying commit message (Sagar)
v7: Generalizing subject to drm/i915 (Sagar)
Suggested by: Michal Wajdeczko <michal.wajdec...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 40287e9..ac25d63 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1641,7 +1641,7 @@ static int i915_fbc_status(struct seq_file *m, void
*unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
if (!HAS_FBC(dev_priv)) {
- seq_puts(m, "FBC unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -1809,7 +1809,7 @@ static int i915_ring_freq_table(struct seq_file *m, void
*unused)
unsigned int max_gpu_freq, min_gpu_freq;
if (!HAS_LLC(dev_priv)) {
- seq_puts(m, "unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2361,8 +2361,11 @@ static int i915_huc_load_status_info(struct seq_file *m,
void *data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct intel_uc_fw *huc_fw = _priv->huc.fw;
- if (!HAS_HUC_UCODE(dev_priv))
+ if (!HAS_HUC_UCODE(dev_priv)) {
+ seq_puts(m, "not supported\n");
return 0;
+ }
+
seq_puts(m, "HuC firmware status:\n");
seq_printf(m, "\tpath: %s\n", huc_fw->path);
@@ -2394,8 +2397,11 @@ static int i915_guc_load_status_info(struct seq_file *m,
void *data)
struct intel_uc_fw *guc_fw = _priv->guc.fw;
u32 tmp, i;
- if (!HAS_GUC_UCODE(dev_priv))
+ if (!HAS_GUC_UCODE(dev_priv)) {
+ seq_puts(m, "not supported\n");
return 0;
+ }
+
seq_printf(m, "GuC firmware status:\n");
seq_printf(m, "\tpath: %s\n",
@@ -2679,7 +2685,7 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
bool enabled = false;
if (!HAS_PSR(dev_priv)) {
- seq_puts(m, "PSR not supported\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -3546,7 +3552,7 @@ static void drrs_status_per_crtc(struct seq_file *m,
mutex_lock(>mutex);
/* DRRS Supported */
- seq_puts(m, "\tDRRS Supported: Yes\n");
+ seq_puts(m, "supported\n");
/* disable_drrs() will make drrs->dp NULL */
if (!drrs->dp) {
@@ -3578,7 +3584,7 @@ static void drrs_status_per_crtc(struct seq_file *m,
mutex_unlock(>mutex);
} else {
/* DRRS not supported. Print the VBT parameter*/
- seq_puts(m, "\tDRRS Supported : No");
+ seq_puts(m, "not supported\n");
}
seq_puts(m, "\n");
}
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 3/4] drm/i915/guc : Updating GuC and HuC FW select function
Updating GuC and HuC firmware select function to support removing
i915_modparams.enable_guc_loading module parameter.
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, Re-factoring code as per review (Michal)
v4: Rebase
v5: Separating message unification into a separate patch
v6: Re-factoring code (Sagar, Michal)
Rebase
v7: Separating from previuos patch (Sagar)
Rebase
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
---
drivers/gpu/drm/i915/intel_guc_fw.c | 9 -
drivers/gpu/drm/i915/intel_guc_fw.h | 2 +-
drivers/gpu/drm/i915/intel_huc.c| 4 +++-
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index ef67a36..5bffeef 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -63,7 +63,7 @@
*
* Return: zero when we know firmware, non-zero in other case
*/
-int intel_guc_fw_select(struct intel_guc *guc)
+void intel_guc_fw_select(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -90,11 +90,10 @@ int intel_guc_fw_select(struct intel_guc *guc)
guc->fw.major_ver_wanted = GLK_FW_MAJOR;
guc->fw.minor_ver_wanted = GLK_FW_MINOR;
} else {
- DRM_ERROR("No GuC firmware known for platform with GuC!\n");
- return -ENOENT;
+ if (!HAS_GUC(dev_priv))
+ DRM_ERROR("No GuC FW known for platform with GuC!\n");
+ return;
}
-
- return 0;
}
/*
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.h
b/drivers/gpu/drm/i915/intel_guc_fw.h
index 023f5ba..7f6ccaf 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.h
+++ b/drivers/gpu/drm/i915/intel_guc_fw.h
@@ -27,7 +27,7 @@
struct intel_guc;
-int intel_guc_fw_select(struct intel_guc *guc);
+void intel_guc_fw_select(struct intel_guc *guc);
int intel_guc_fw_upload(struct intel_guc *guc);
#endif
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index c8a48cb..fc61779 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -108,7 +108,9 @@ void intel_huc_select_fw(struct intel_huc *huc)
huc->fw.major_ver_wanted = GLK_HUC_FW_MAJOR;
huc->fw.minor_ver_wanted = GLK_HUC_FW_MINOR;
} else {
- DRM_ERROR("No HuC firmware known for platform with HuC!\n");
+ /* For now, everything with a GuC also has a HuC */
+ if (HAS_GUC(dev_priv))
+ DRM_ERROR("No HuC FW known for platform with HuC!\n");
return;
}
}
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 0/4] drm/i915/guc : Removing enable_guc_loading module
The first patch simply unifies different seq_puts messages found in debugfs. Patch 2 and 3 involve replacing te enable_guc_loading module. Patch 4 deals with decoupling GuC logs and ADS from submission. Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Anusha Srivatsa <anusha.sriva...@intel.com> Sujaritha Sundaresan (4): drm/i915 : Unifying seq_puts messages for feature support drm/i915/guc : Removing i915_modparams.enable_guc_loading module parameter drm/i915/guc : Updating GuC and HuC FW select function drm/i915/guc : Decouple logs and ADS from submission drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_debugfs.c| 22 -- drivers/gpu/drm/i915/i915_drv.h| 9 ++- drivers/gpu/drm/i915/i915_gem_context.c| 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c| 2 +- drivers/gpu/drm/i915/i915_guc_submission.c | 106 + drivers/gpu/drm/i915/i915_irq.c| 2 +- drivers/gpu/drm/i915/i915_params.c | 4 - drivers/gpu/drm/i915/i915_params.h | 1 - drivers/gpu/drm/i915/intel_guc.h | 1 + drivers/gpu/drm/i915/intel_guc_ads.c | 119 + drivers/gpu/drm/i915/intel_guc_ads.h | 31 drivers/gpu/drm/i915/intel_guc_fw.c| 9 +-- drivers/gpu/drm/i915/intel_guc_fw.h| 2 +- drivers/gpu/drm/i915/intel_guc_log.c | 6 +- drivers/gpu/drm/i915/intel_huc.c | 4 +- drivers/gpu/drm/i915/intel_uc.c| 108 ++ drivers/gpu/drm/i915/intel_uncore.c| 3 +- 18 files changed, 264 insertions(+), 168 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.c create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.h -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 3/3] drm/i915/guc : Decouple logs and ADS from submission
The Additional Data Struct (ADS) contains objects that are required by
guc post FW load and are not necessarily submission-only (although that's
our current only use-case). If in the future we load GuC with submission
disabled to use some other GuC feature we might still end up requiring
something inside the ADS, so it makes more sense for them to be always
created if GuC is loaded.
Similarly, we still want to access GuC logs even if GuC submission is
disable to debug issues with GuC loading or with wathever we're using
GuC for.
To make a concrete example, the pages used by GuC to save state during
suspend are allocated as part of the ADS.
v3: Group initialization of GuC objects
v2: Decoupling ADS together with logs
v3: Re-factoring code as per review (Michal)
v4: Rebase
v5: Separating group object initialization into next patch
Clarifying commit message
v6: Reverting to goto err format (Michal)
Moved guc_ads functions to dedicated file
Rebase
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_guc_submission.c | 105 +
drivers/gpu/drm/i915/intel_guc.h | 1 +
drivers/gpu/drm/i915/intel_guc_ads.c | 120 +
drivers/gpu/drm/i915/intel_guc_ads.h | 31
drivers/gpu/drm/i915/intel_guc_log.c | 6 +-
drivers/gpu/drm/i915/intel_uc.c| 40 +-
7 files changed, 196 insertions(+), 108 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.c
create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 66d23b6..3aed5bf 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -62,6 +62,7 @@ i915-y += i915_cmd_parser.o \
i915-y += intel_uc.o \
intel_uc_fw.o \
intel_guc.o \
+ intel_guc_ads.o \
intel_guc_ct.o \
intel_guc_log.o \
intel_guc_loader.o \
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 31381a3..1ad1060 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -72,13 +72,6 @@
* ELSP context descriptor dword into Work Item.
* See guc_wq_item_append()
*
- * ADS:
- * The Additional Data Struct (ADS) has pointers for different buffers used by
- * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
- * scheduling policies (guc_policies), a structure describing a collection of
- * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
- * its internal state for sleep.
- *
*/
static inline bool is_high_priority(struct i915_guc_client* client)
@@ -863,7 +856,7 @@ static void guc_policy_init(struct guc_policy *policy)
policy->policy_flags = 0;
}
-static void guc_policies_init(struct guc_policies *policies)
+void i915_guc_policies_init(struct guc_policies *policies)
{
struct guc_policy *policy;
u32 p, i;
@@ -883,88 +876,6 @@ static void guc_policies_init(struct guc_policies
*policies)
}
/*
- * The first 80 dwords of the register state context, containing the
- * execlists and ppgtt registers.
- */
-#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
-
-static int guc_ads_create(struct intel_guc *guc)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- struct i915_vma *vma;
- struct page *page;
- /* The ads obj includes the struct itself and buffers passed to GuC */
- struct {
- struct guc_ads ads;
- struct guc_policies policies;
- struct guc_mmio_reg_state reg_state;
- u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
- } __packed *blob;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
- const u32 skipped_offset = LRC_HEADER_PAGES * PAGE_SIZE;
- const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
- u32 base;
-
- GEM_BUG_ON(guc->ads_vma);
-
- vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(sizeof(*blob)));
- if (IS_ERR(vma))
- return PTR_ERR(vma);
-
- guc->ads_vma = vma;
-
- page = i915_vma_first_page(vma);
- blob = kmap(page);
-
- /* GuC scheduling policies */
- guc_policies_init(>policies);
-
- /* MMIO reg state */
- for_each_engine(engine, dev_priv, id) {
- blob->reg_state.white_list[engine->guc_id].mmio_start =
- engine->mmio_base + GUC_MMIO_W
[Intel-gfx] [PATCH v6 2/3] drm/i915/guc : Removing i915_modparams.enable_guc_loading module parameter
We currently have two module parameters that control GuC: "enable_guc_loading"
and "enable_guc_submission".
Whenever we need i915_modparams.enable_guc_submission=1, we also need
enable_guc_loading=1.
We also need enable_guc_loading=1 when we want to verify the HuC,
which is every time we have a HuC (but all platforms with HuC have a GuC and
viceversa).
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, Re-factoring code as per review (Michal)
v4: Rebase
v5: Separating message unification into a separate patch
v6: Re-factoring code (Sagar, Michal)
Rebase
Suggested by: Oscar Mateo <oscar.ma...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
drivers/gpu/drm/i915/i915_drv.h | 9 +++--
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/i915_params.c | 4 --
drivers/gpu/drm/i915/i915_params.h | 1 -
drivers/gpu/drm/i915/intel_guc.h| 2 +-
drivers/gpu/drm/i915/intel_guc_loader.c | 9 ++---
drivers/gpu/drm/i915/intel_huc.c| 4 +-
drivers/gpu/drm/i915/intel_uc.c | 72 +
drivers/gpu/drm/i915/intel_uncore.c | 3 +-
12 files changed, 59 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9d0c27b..8abc47c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2390,7 +2390,7 @@ static int i915_huc_load_status_info(struct seq_file *m,
void *data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct intel_uc_fw *huc_fw = _priv->huc.fw;
- if (!HAS_HUC_UCODE(dev_priv))
+ if (!HAS_GUC(dev_priv))
seq_puts(m, "not supported\n");
return 0;
@@ -2424,7 +2424,7 @@ static int i915_guc_load_status_info(struct seq_file *m,
void *data)
struct intel_uc_fw *guc_fw = _priv->guc.fw;
u32 tmp, i;
- if (!HAS_GUC_UCODE(dev_priv))
+ if (!HAS_GUC(dev_priv))
seq_puts(m, "not supported\n");
return 0;
@@ -2521,7 +2521,7 @@ static bool check_guc_submission(struct seq_file *m)
if (!guc->execbuf_client) {
seq_printf(m, "GuC submission %s\n",
- HAS_GUC_SCHED(dev_priv) ?
+ HAS_GUC(dev_priv) ?
"disabled" :
"not supported");
return false;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 770305b..194cbc9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3182,9 +3182,12 @@ static inline unsigned int i915_sg_segment_size(void)
*/
#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
-#define HAS_GUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_GUC_SCHED(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_HUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
+#define HAS_GUC_UCODE(dev_priv)((dev_priv)->guc.fw.path != NULL)
+#define HAS_HUC_UCODE(dev_priv)((dev_priv)->huc.fw.path != NULL)
+
+#define NEEDS_GUC_LOADING(dev_priv) \
+ (HAS_GUC(dev_priv) && \
+ (i915_modparams.enable_guc_submission || HAS_HUC_UCODE(dev_priv)))
#define HAS_RESOURCE_STREAMER(dev_priv)
((dev_priv)->info.has_resource_streamer)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 5bf96a2..692d609 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -314,7 +314,7 @@ static u32 default_desc_template(const struct
drm_i915_private *i915,
* present or not in use we still need a small bias as ring wraparound
* at offset 0 sometimes hangs. No idea why.
*/
- if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading)
+ if (NEEDS_GUC_LOADING(dev_priv))
ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
else
ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4c60578..b71fd24 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3483,7 +3483,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
* currently don't have any bits spare to pass in
[Intel-gfx] [PATCH v6 0/3] drm/i915/guc : Removing enable_guc_loading module and Decoupling logs and ADS from submission
The first patch simply unifies different seq_puts messages found in debugfs. Patch 2 focuses on replacing the enable_guc_loading module. Patch 3 deals with decoupling guc logs and ADS from submission. Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Anusha Srivatsa <anusha.sriva...@intel.com> Sujaritha Sundaresan (3): drm/i915/guc : Unifying seq_puts messages for feature support drm/i915/guc : Removing i915_modparams.enable_guc_loading module parameter drm/i915/guc : Decouple logs and ADS from submission drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_debugfs.c| 18 +++-- drivers/gpu/drm/i915/i915_drv.h| 9 ++- drivers/gpu/drm/i915/i915_gem_context.c| 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c| 2 +- drivers/gpu/drm/i915/i915_guc_submission.c | 105 + drivers/gpu/drm/i915/i915_irq.c| 2 +- drivers/gpu/drm/i915/i915_params.c | 4 - drivers/gpu/drm/i915/i915_params.h | 1 - drivers/gpu/drm/i915/intel_guc.h | 3 +- drivers/gpu/drm/i915/intel_guc_ads.c | 120 + drivers/gpu/drm/i915/intel_guc_ads.h | 31 drivers/gpu/drm/i915/intel_guc_loader.c| 9 +-- drivers/gpu/drm/i915/intel_guc_log.c | 6 +- drivers/gpu/drm/i915/intel_huc.c | 4 +- drivers/gpu/drm/i915/intel_uc.c| 112 ++- drivers/gpu/drm/i915/intel_uncore.c| 3 +- 17 files changed, 262 insertions(+), 170 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.c create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.h -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 1/3] drm/i915/guc : Unifying seq_puts messages for feature support
Unifying the various seq_puts messages in debugfs to the simplest one for
feature support.
v2: Clarifying the commit message (Anusha)
v3: Re-factoring code as per review (Michal)
v4: Rebase
v5: Split from following patch
v6: Re-factoring code (Michal, Sagar)
Clarifying commit message (Sagar)
Suggested by: Michal Wajdeczko <michal.wajdec...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5b58d2b..9d0c27b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1670,7 +1670,7 @@ static int i915_fbc_status(struct seq_file *m, void
*unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
if (!HAS_FBC(dev_priv)) {
- seq_puts(m, "FBC unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -1837,7 +1837,7 @@ static int i915_ring_freq_table(struct seq_file *m, void
*unused)
unsigned int max_gpu_freq, min_gpu_freq;
if (!HAS_LLC(dev_priv)) {
- seq_puts(m, "unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2391,6 +2391,7 @@ static int i915_huc_load_status_info(struct seq_file *m,
void *data)
struct intel_uc_fw *huc_fw = _priv->huc.fw;
if (!HAS_HUC_UCODE(dev_priv))
+ seq_puts(m, "not supported\n");
return 0;
seq_puts(m, "HuC firmware status:\n");
@@ -2424,6 +2425,7 @@ static int i915_guc_load_status_info(struct seq_file *m,
void *data)
u32 tmp, i;
if (!HAS_GUC_UCODE(dev_priv))
+ seq_puts(m, "not supported\n");
return 0;
seq_printf(m, "GuC firmware status:\n");
@@ -2708,7 +2710,7 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
bool enabled = false;
if (!HAS_PSR(dev_priv)) {
- seq_puts(m, "PSR not supported\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -3565,7 +3567,7 @@ static void drrs_status_per_crtc(struct seq_file *m,
mutex_lock(>mutex);
/* DRRS Supported */
- seq_puts(m, "\tDRRS Supported: Yes\n");
+ seq_puts(m, "supported\n");
/* disable_drrs() will make drrs->dp NULL */
if (!drrs->dp) {
@@ -3597,7 +3599,7 @@ static void drrs_status_per_crtc(struct seq_file *m,
mutex_unlock(>mutex);
} else {
/* DRRS not supported. Print the VBT parameter*/
- seq_puts(m, "\tDRRS Supported : No");
+ seq_puts(m, "not supported\n");
}
seq_puts(m, "\n");
}
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/5] drm/i915/guc : Fixing argument type warning.
Reverting argument type (struct intel_guc *guc) to expected type due to warning.
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
---
drivers/gpu/drm/i915/i915_guc_submission.c | 7 +--
drivers/gpu/drm/i915/intel_uc.h| 4 ++--
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index a351339..0db1291 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -920,8 +920,9 @@ void i915_guc_policies_init(struct guc_policies *policies)
* Set up the memory resources to be shared with the GuC (via the GGTT)
* at firmware loading time.
*/
-int i915_guc_submission_shared_objects_init(struct intel_guc *guc)
+int i915_guc_submission_shared_objects_init(struct drm_i915_private *dev_priv)
{
+ struct intel_guc *guc = _priv->guc;
struct i915_vma *vma;
void *vaddr;
@@ -949,8 +950,10 @@ int i915_guc_submission_shared_objects_init(struct
intel_guc *guc)
return 0;
}
-void i915_guc_submission_shared_objects_fini(struct intel_guc *guc)
+void i915_guc_submission_shared_objects_fini(struct drm_i915_private *dev_priv)
{
+ struct intel_guc *guc = _priv->guc;
+
ida_destroy(>stage_ids);
i915_gem_object_unpin_map(guc->stage_desc_pool->obj);
i915_vma_unpin_and_release(>stage_desc_pool);
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 5106046..7a6c9b1 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -230,10 +230,10 @@ static inline void intel_guc_notify(struct intel_guc *guc)
u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
/* i915_guc_submission.c */
-int i915_guc_submission_shared_objects_init(struct intel_guc *guc);
+int i915_guc_submission_shared_objects_init(struct drm_i915_private *dev_priv);
int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
-void i915_guc_submission_shared_objects_fini(struct intel_guc *guc);
+void i915_guc_submission_shared_objects_fini(struct drm_i915_private
*dev_priv);
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
void i915_guc_policies_init(struct guc_policies *policies);
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/5] drm/i915/guc: group initialization of GuC objects
The previous patch has split up the initialization of some of the GuC
objects in 2 different functions, let's pull them back together.
v3: Group initialization of GuC objects
v2: Decoupling ADS together with logs (Daniele)
v3: Rebase
v4: Rebase
v5: Separated from previous patch
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
---
drivers/gpu/drm/i915/i915_guc_submission.c | 7 ++---
drivers/gpu/drm/i915/intel_uc.c| 41 +-
drivers/gpu/drm/i915/intel_uc.h| 4 +--
3 files changed, 28 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index c456c55..a351339 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -920,9 +920,8 @@ void i915_guc_policies_init(struct guc_policies *policies)
* Set up the memory resources to be shared with the GuC (via the GGTT)
* at firmware loading time.
*/
-int i915_guc_submission_init(struct drm_i915_private *dev_priv)
+int i915_guc_submission_shared_objects_init(struct intel_guc *guc)
{
- struct intel_guc *guc = _priv->guc;
struct i915_vma *vma;
void *vaddr;
@@ -950,10 +949,8 @@ int i915_guc_submission_init(struct drm_i915_private
*dev_priv)
return 0;
}
-void i915_guc_submission_fini(struct drm_i915_private *dev_priv)
+void i915_guc_submission_shared_objects_fini(struct intel_guc *guc)
{
- struct intel_guc *guc = _priv->guc;
-
ida_destroy(>stage_ids);
i915_gem_object_unpin_map(guc->stage_desc_pool->obj);
i915_vma_unpin_and_release(>stage_desc_pool);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 732f188..69239e4 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -423,13 +423,33 @@ static int guc_shared_objects_init(struct intel_guc *guc)
ret = guc_ads_create(guc);
if (ret < 0)
- intel_guc_log_destroy(guc);
+ goto err_logs;
+
+ if (i915_modparams.enable_guc_submission) {
+ /*
+* This is stuff we need to have available at fw load time
+* if we are planning to enable submission later
+*/
+ ret = i915_guc_submission_shared_objects_init(guc);
+ if (ret)
+ goto err_ads;
+ }
+
+ return 0;
+
+err_ads:
+ guc_ads_destroy(guc);
+err_logs:
+ intel_guc_log_destroy(guc);
return ret;
}
static void guc_shared_objects_fini(struct intel_guc *guc)
{
+ if (i915_modparams.enable_guc_submission)
+ i915_guc_submission_shared_objects_fini(guc);
+
guc_ads_destroy(guc);
intel_guc_log_destroy(guc);
}
@@ -452,16 +472,6 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
if (ret)
goto err_guc;
- if (i915_modparams.enable_guc_submission) {
- /*
-* This is stuff we need to have available at fw load time
-* if we are planning to enable submission later
-*/
- ret = i915_guc_submission_init(dev_priv);
- if (ret)
- goto err_shared;
- }
-
/* init WOPCM */
I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
I915_WRITE(DMA_GUC_WOPCM_OFFSET,
@@ -481,7 +491,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
*/
ret = __intel_uc_reset_hw(dev_priv);
if (ret)
- goto err_submission;
+ goto err_shared;
intel_huc_init_hw(_priv->huc);
ret = intel_guc_init_hw(_priv->guc);
@@ -526,11 +536,8 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
gen9_disable_guc_interrupts(dev_priv);
err_log_capture:
guc_capture_load_err_log(guc);
-err_submission:
- if (i915_modparams.enable_guc_submission)
- i915_guc_submission_fini(dev_priv);
err_shared:
- guc_shared_objects_fini(guc);
+ guc_shared_objects_fini(guc);
err_guc:
i915_ggtt_disable_guc(dev_priv);
@@ -567,7 +574,7 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
if (i915_modparams.enable_guc_submission) {
gen9_disable_guc_interrupts(dev_priv);
- i915_guc_submission_fini(dev_priv);
+ i915_guc_submission_shared_objects_fini(dev_priv);
}
guc_shared_objects_fini(_priv->guc);
diff --git a/drivers/gpu/drm/i915/i
[Intel-gfx] [PATCH v5 3/5] drm/i915/guc : Decouple logs and ADS from submission
The Additional Data Struct (ADS) contains objects that are required by
guc post FW load and are not necessarily submission-only (although that's
our current only use-case). If in the future we load GuC with submission
disabled to use some other GuC feature we might still end up requiring
something inside the ADS, so it makes more sense for them to be always
created if GuC is loaded.
Similarly, we still want to access GuC logs even if GuC submission is
disable to debug issues with GuC loading or with wathever we're using
GuC for.
To make a concrete example, the pages used by GuC to save state during
suspend are allocated as part of the ADS.
v3: Group initialization of GuC objects
v2: Decoupling ADS together with logs (Daniele)
v3: Re-factoring code as per review (Michal)
v4: Rebase
v5: Separating group object initialization into next patch
Clarifying commit message
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
---
drivers/gpu/drm/i915/i915_guc_submission.c | 114 +---
drivers/gpu/drm/i915/intel_guc_log.c | 6 +-
drivers/gpu/drm/i915/intel_uc.c| 115 -
drivers/gpu/drm/i915/intel_uc.h| 1 +
4 files changed, 121 insertions(+), 115 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 04f1281..c456c55 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -71,13 +71,6 @@
* ELSP context descriptor dword into Work Item.
* See guc_wq_item_append()
*
- * ADS:
- * The Additional Data Struct (ADS) has pointers for different buffers used by
- * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
- * scheduling policies (guc_policies), a structure describing a collection of
- * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
- * its internal state for sleep.
- *
*/
static inline bool is_high_priority(struct i915_guc_client* client)
@@ -904,7 +897,7 @@ static void guc_policy_init(struct guc_policy *policy)
policy->policy_flags = 0;
}
-static void guc_policies_init(struct guc_policies *policies)
+void i915_guc_policies_init(struct guc_policies *policies)
{
struct guc_policy *policy;
u32 p, i;
@@ -924,88 +917,6 @@ static void guc_policies_init(struct guc_policies
*policies)
}
/*
- * The first 80 dwords of the register state context, containing the
- * execlists and ppgtt registers.
- */
-#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
-
-static int guc_ads_create(struct intel_guc *guc)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- struct i915_vma *vma;
- struct page *page;
- /* The ads obj includes the struct itself and buffers passed to GuC */
- struct {
- struct guc_ads ads;
- struct guc_policies policies;
- struct guc_mmio_reg_state reg_state;
- u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
- } __packed *blob;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
- const u32 skipped_offset = LRC_HEADER_PAGES * PAGE_SIZE;
- const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
- u32 base;
-
- GEM_BUG_ON(guc->ads_vma);
-
- vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(sizeof(*blob)));
- if (IS_ERR(vma))
- return PTR_ERR(vma);
-
- guc->ads_vma = vma;
-
- page = i915_vma_first_page(vma);
- blob = kmap(page);
-
- /* GuC scheduling policies */
- guc_policies_init(>policies);
-
- /* MMIO reg state */
- for_each_engine(engine, dev_priv, id) {
- blob->reg_state.white_list[engine->guc_id].mmio_start =
- engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
-
- /* Nothing to be saved or restored for now. */
- blob->reg_state.white_list[engine->guc_id].count = 0;
- }
-
- /*
-* The GuC requires a "Golden Context" when it reinitialises
-* engines after a reset. Here we use the Render ring default
-* context, which must already exist and be pinned in the GGTT,
-* so its address won't change after we've told the GuC where
-* to find it. Note that we have to skip our header (1 page),
-* because our GuC shared data is there.
-*/
- blob->ads.golden_context_lrca =
- guc_ggtt_offset(dev_priv->kernel_context->engine[RCS].state) +
skipped_offset;
-
- /*
-* The GuC expects us
[Intel-gfx] [PATCH v5 2/5] drm/i915/guc : Removing i915_modparams.enable_guc_loading module
We currently have two module parameters that control GuC: "enable_guc_loading"
and "enable_guc_submission".
Whenever we need i915_modparams.enable_guc_submission=1, we also need
enable_guc_loading=1.
We also need enable_guc_loading=1 when we want to verify the HuC,
which is every time we have a HuC (but all platforms with HuC have a GuC and
viceversa).
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, Re-factoring code as per review (Michal)
v4: Rebase
v5: Separating message unification into a separate patch
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 11 +--
drivers/gpu/drm/i915/i915_drv.h | 9 --
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/i915_params.c | 5
drivers/gpu/drm/i915/i915_params.h | 1 -
drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++--
drivers/gpu/drm/i915/intel_huc.c| 4 ++-
drivers/gpu/drm/i915/intel_uc.c | 51 +
drivers/gpu/drm/i915/intel_uc.h | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 4 +--
12 files changed, 52 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 53e40dd..4fde4b2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2336,8 +2336,10 @@ static int i915_huc_load_status_info(struct seq_file *m,
void *data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct intel_uc_fw *huc_fw = _priv->huc.fw;
- if (!HAS_HUC_UCODE(dev_priv))
+ if (!HAS_GUC(dev_priv)){
+ seq_puts(m, "not supported\n");
return 0;
+ }
seq_puts(m, "HuC firmware status:\n");
seq_printf(m, "\tpath: %s\n", huc_fw->path);
@@ -2369,8 +2371,11 @@ static int i915_guc_load_status_info(struct seq_file *m,
void *data)
struct intel_uc_fw *guc_fw = _priv->guc.fw;
u32 tmp, i;
- if (!HAS_GUC_UCODE(dev_priv))
+ if (!HAS_GUC(dev_priv)){
+ seq_puts(m, "not supported\n");
return 0;
+
+ }
seq_printf(m, "GuC firmware status:\n");
seq_printf(m, "\tpath: %s\n",
@@ -2465,7 +2470,7 @@ static bool check_guc_submission(struct seq_file *m)
if (!guc->execbuf_client) {
seq_printf(m, "GuC submission %s\n",
- HAS_GUC_SCHED(dev_priv) ?
+ HAS_GUC(dev_priv) ?
"disabled" :
"not supported");
return false;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 61a4be9..6479b72 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3141,9 +3141,12 @@ static inline unsigned int i915_sg_segment_size(void)
*/
#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
-#define HAS_GUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_GUC_SCHED(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_HUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
+#define HAS_GUC_UCODE(dev_priv)((dev_priv)->guc.fw.path != NULL)
+#define HAS_HUC_UCODE(dev_priv)((dev_priv)->guc.fw.path != NULL)
+
+#define NEEDS_GUC_LOADING(dev_priv) \
+ (HAS_GUC(dev_priv) && \
+ (i915_modparams.enable_guc_submission || HAS_HUC_UCODE(dev_priv)))
#define HAS_RESOURCE_STREAMER(dev_priv)
((dev_priv)->info.has_resource_streamer)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 921ee36..0890341 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -314,7 +314,7 @@ static u32 default_desc_template(const struct
drm_i915_private *i915,
* present or not in use we still need a small bias as ring wraparound
* at offset 0 sometimes hangs. No idea why.
*/
- if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading)
+ if (NEEDS_GUC_LOADING(dev_priv))
ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
else
ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 64d7852..a32935a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm
[Intel-gfx] [PATCH v5 1/5] drm/i915/guc : Unifying seq_puts messages
Unifying the various seq_puts messages to the simplest one
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, Re-factoring code as per review (Michal)
v4: Rebase
v5: Separated into a separate patch
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 847f8e8..53e40dd 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1616,7 +1616,7 @@ static int i915_fbc_status(struct seq_file *m, void
*unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
if (!HAS_FBC(dev_priv)) {
- seq_puts(m, "FBC unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -1783,7 +1783,7 @@ static int i915_ring_freq_table(struct seq_file *m, void
*unused)
unsigned int max_gpu_freq, min_gpu_freq;
if (!HAS_LLC(dev_priv)) {
- seq_puts(m, "unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2654,7 +2654,7 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
bool enabled = false;
if (!HAS_PSR(dev_priv)) {
- seq_puts(m, "PSR not supported\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2807,7 +2807,7 @@ static int i915_runtime_pm_status(struct seq_file *m,
void *unused)
struct pci_dev *pdev = dev_priv->drm.pdev;
if (!HAS_RUNTIME_PM(dev_priv))
- seq_puts(m, "Runtime power management not supported\n");
+ seq_puts(m, "not supported\n");
seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
seq_printf(m, "IRQs disabled: %s\n",
@@ -3683,7 +3683,7 @@ static void drrs_status_per_crtc(struct seq_file *m,
mutex_unlock(>mutex);
} else {
/* DRRS not supported. Print the VBT parameter*/
- seq_puts(m, "\tDRRS Supported : No");
+ seq_puts(m, "not supported\n");
}
seq_puts(m, "\n");
}
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 0/5] Removing enable_guc_loading module and Decoupling logs and ADS from submission
The first patch simpily unifies different seq_puts messages found in debugfs. In earlier verions, Patch 1 and 2 were previuosly in one single patch. Patch 2 focuses on replacing the enable_guc_loading module. Patch 3 and 4 deal with decoupling guc logs and ADS from submission. Patch 5 fixes a warning generated as a result of patch 4. Cc: Anusha Srivatsa <anusha.sriva...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Sujaritha Sundaresan (5): drm/i915/guc : Unifying seq_puts messages drm/i915/guc : Removing i915_modparams.enable_guc_loading module drm/i915/guc : Decouple logs and ADS from submission drm/i915/guc : group initialization of GuC objects drm/i915/guc : Fixing argument type warning drivers/gpu/drm/i915/i915_debugfs.c| 21 +-- drivers/gpu/drm/i915/i915_drv.h| 9 +- drivers/gpu/drm/i915/i915_gem_context.c| 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c| 2 +- drivers/gpu/drm/i915/i915_guc_submission.c | 118 + drivers/gpu/drm/i915/i915_irq.c| 2 +- drivers/gpu/drm/i915/i915_params.c | 5 - drivers/gpu/drm/i915/i915_params.h | 1 - drivers/gpu/drm/i915/intel_guc_loader.c| 7 +- drivers/gpu/drm/i915/intel_guc_log.c | 6 +- drivers/gpu/drm/i915/intel_huc.c | 4 +- drivers/gpu/drm/i915/intel_uc.c| 199 +++-- drivers/gpu/drm/i915/intel_uc.h| 7 +- drivers/gpu/drm/i915/intel_uncore.c| 4 +- 14 files changed, 202 insertions(+), 185 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 2/2] drm/i915/guc : Decouple logs and ADS from submission
The Additional Data Struct (ADS) contains objects that are required by
guc post FW load and are not necessarily submission-only (although that's
our current only use-case). If in the future we load GuC with submission
disabled to use some other GuC feature we might still end up requiring
something inside the ADS, so it makes more sense for them to be always
created if GuC is loaded.
Similarly, we still want to access GuC logs even if GuC submission is
disable to debug issues with GuC loading or with wathever we're using GuC for.
v2: Decoupling ads together with logs
v3: Group initialization of GuC objects
v4: Rebased
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
---
drivers/gpu/drm/i915/i915_guc_submission.c | 121 +---
drivers/gpu/drm/i915/intel_guc_log.c | 6 +-
drivers/gpu/drm/i915/intel_uc.c| 145 ++---
drivers/gpu/drm/i915/intel_uc.h| 6 +-
4 files changed, 143 insertions(+), 135 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index e191d56..02fb1e6 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -71,13 +71,6 @@
* ELSP context descriptor dword into Work Item.
* See guc_wq_item_append()
*
- * ADS:
- * The Additional Data Struct (ADS) has pointers for different buffers used by
- * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
- * scheduling policies (guc_policies), a structure describing a collection of
- * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
- * its internal state for sleep.
- *
*/
static inline bool is_high_priority(struct i915_guc_client* client)
@@ -898,7 +891,7 @@ static void guc_policy_init(struct guc_policy *policy)
policy->policy_flags = 0;
}
-static void guc_policies_init(struct guc_policies *policies)
+void i915_guc_policies_init(struct guc_policies *policies)
{
struct guc_policy *policy;
u32 p, i;
@@ -918,97 +911,13 @@ static void guc_policies_init(struct guc_policies
*policies)
}
/*
- * The first 80 dwords of the register state context, containing the
- * execlists and ppgtt registers.
- */
-#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
-
-static int guc_ads_create(struct intel_guc *guc)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- struct i915_vma *vma;
- struct page *page;
- /* The ads obj includes the struct itself and buffers passed to GuC */
- struct {
- struct guc_ads ads;
- struct guc_policies policies;
- struct guc_mmio_reg_state reg_state;
- u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
- } __packed *blob;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
- const u32 skipped_offset = LRC_HEADER_PAGES * PAGE_SIZE;
- const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
- u32 base;
-
- GEM_BUG_ON(guc->ads_vma);
-
- vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(sizeof(*blob)));
- if (IS_ERR(vma))
- return PTR_ERR(vma);
-
- guc->ads_vma = vma;
-
- page = i915_vma_first_page(vma);
- blob = kmap(page);
-
- /* GuC scheduling policies */
- guc_policies_init(>policies);
-
- /* MMIO reg state */
- for_each_engine(engine, dev_priv, id) {
- blob->reg_state.white_list[engine->guc_id].mmio_start =
- engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
-
- /* Nothing to be saved or restored for now. */
- blob->reg_state.white_list[engine->guc_id].count = 0;
- }
-
- /*
-* The GuC requires a "Golden Context" when it reinitialises
-* engines after a reset. Here we use the Render ring default
-* context, which must already exist and be pinned in the GGTT,
-* so its address won't change after we've told the GuC where
-* to find it. Note that we have to skip our header (1 page),
-* because our GuC shared data is there.
-*/
- blob->ads.golden_context_lrca =
- guc_ggtt_offset(dev_priv->kernel_context->engine[RCS].state) +
skipped_offset;
-
- /*
-* The GuC expects us to exclude the portion of the context image that
-* it skips from the size it is to read. It starts reading from after
-* the execlist context (so skipping the first page [PPHWSP] and 80
-* dwords). Weird guc is weird.
-*/
- for_each_engine(engine, dev_priv, id)
- blo
[Intel-gfx] [PATCH v4 1/2] drm/i915/guc : Removing enable_guc_loading module
We currently have two module parameters that control GuC: "enable_guc_loading"
and "enable_guc_submission".
Whenever we need i915.enable_guc_submission=1, we also need
enable_guc_loading=1.
We also need enable_guc_loading=1 when we want to verify the HuC,
which is every time we have a HuC (but all platforms with HuC have a GuC and
viceversa).
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, correcting inconsistencies (Michal)
v4: Rebased
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 22 +
drivers/gpu/drm/i915/i915_drv.h | 11 +++--
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/i915_params.c | 5 --
drivers/gpu/drm/i915/i915_params.h | 1 -
drivers/gpu/drm/i915/intel_guc_loader.c | 6 ++-
drivers/gpu/drm/i915/intel_uc.c | 83 ++---
9 files changed, 73 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index ca6fa6d..063fbe3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1616,7 +1616,7 @@ static int i915_fbc_status(struct seq_file *m, void
*unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
if (!HAS_FBC(dev_priv)) {
- seq_puts(m, "FBC unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -1783,7 +1783,7 @@ static int i915_ring_freq_table(struct seq_file *m, void
*unused)
unsigned int max_gpu_freq, min_gpu_freq;
if (!HAS_LLC(dev_priv)) {
- seq_puts(m, "unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2336,8 +2336,11 @@ static int i915_huc_load_status_info(struct seq_file *m,
void *data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct intel_uc_fw *huc_fw = _priv->huc.fw;
- if (!HAS_HUC_UCODE(dev_priv))
+ if (!HAS_GUC(dev_priv)){
+ seq_puts(m, "not supported\n");
return 0;
+ }
+
seq_puts(m, "HuC firmware status:\n");
seq_printf(m, "\tpath: %s\n", huc_fw->path);
@@ -2369,8 +2372,11 @@ static int i915_guc_load_status_info(struct seq_file *m,
void *data)
struct intel_uc_fw *guc_fw = _priv->guc.fw;
u32 tmp, i;
- if (!HAS_GUC_UCODE(dev_priv))
+ if (!HAS_GUC(dev_priv)){
+ seq_puts(m, "not supported\n");
return 0;
+ }
+
seq_printf(m, "GuC firmware status:\n");
seq_printf(m, "\tpath: %s\n",
@@ -2465,7 +2471,7 @@ static bool check_guc_submission(struct seq_file *m)
if (!guc->execbuf_client) {
seq_printf(m, "GuC submission %s\n",
- HAS_GUC_SCHED(dev_priv) ?
+ HAS_GUC(dev_priv) ?
"disabled" :
"not supported");
return false;
@@ -2654,7 +2660,7 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
bool enabled = false;
if (!HAS_PSR(dev_priv)) {
- seq_puts(m, "PSR not supported\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2807,7 +2813,7 @@ static int i915_runtime_pm_status(struct seq_file *m,
void *unused)
struct pci_dev *pdev = dev_priv->drm.pdev;
if (!HAS_RUNTIME_PM(dev_priv))
- seq_puts(m, "Runtime power management not supported\n");
+ seq_puts(m, "not supported\n");
seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
seq_printf(m, "IRQs disabled: %s\n",
@@ -3683,7 +3689,7 @@ static void drrs_status_per_crtc(struct seq_file *m,
mutex_unlock(>mutex);
} else {
/* DRRS not supported. Print the VBT parameter*/
- seq_puts(m, "\tDRRS Supported : No");
+ seq_puts(m, "not supported\n");
}
seq_puts(m, "\n");
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6d7d871..bd583f7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3138,11 +313
[Intel-gfx] [PATCH v3 2/2] drm/i915/guc : Decouple logs and ADS from submission
The Additional Data Struct (ADS) contains objects that are required by
guc post FW load and are not necessarily submission-only (although that's
our current only use-case). If in the future we load GuC with submission
disabled to use some other GuC feature we might still end up requiring
something inside the ADS, so it makes more sense for them to be always
created if GuC is loaded.
Similarly, we still want to access GuC logs even if GuC submission is
disable to debug issues with GuC loading or with wathever we're using GuC for.
v2: Decoupling ads together with logs
v3: Group initialization of GuC objects
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
---
drivers/gpu/drm/i915/i915_guc_submission.c | 108 ++
drivers/gpu/drm/i915/intel_uc.c| 140 ++---
drivers/gpu/drm/i915/intel_uc.h| 6 +-
3 files changed, 134 insertions(+), 120 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index a15146e..3a4bdb4 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -70,14 +70,6 @@
* represents in-order queue. The kernel driver packs ring tail pointer and an
* ELSP context descriptor dword into Work Item.
* See guc_wq_item_append()
- *
- * ADS:
- * The Additional Data Struct (ADS) has pointers for different buffers used by
- * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
- * scheduling policies (guc_policies), a structure describing a collection of
- * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
- * its internal state for sleep.
- *
*/
static inline bool is_high_priority(struct i915_guc_client* client)
@@ -996,7 +988,7 @@ static void guc_client_free(struct i915_guc_client *client)
kfree(client);
}
-static void guc_policies_init(struct guc_policies *policies)
+void i915_guc_policies_init(struct guc_policies *policies)
{
struct guc_policy *policy;
u32 p, i;
@@ -1018,83 +1010,14 @@ static void guc_policies_init(struct guc_policies
*policies)
policies->is_valid = 1;
}
-static int guc_ads_create(struct intel_guc *guc)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- struct i915_vma *vma;
- struct page *page;
- /* The ads obj includes the struct itself and buffers passed to GuC */
- struct {
- struct guc_ads ads;
- struct guc_policies policies;
- struct guc_mmio_reg_state reg_state;
- u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
- } __packed *blob;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
- u32 base;
-
- GEM_BUG_ON(guc->ads_vma);
-
- vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(sizeof(*blob)));
- if (IS_ERR(vma))
- return PTR_ERR(vma);
-
- guc->ads_vma = vma;
-
- page = i915_vma_first_page(vma);
- blob = kmap(page);
-
- /* GuC scheduling policies */
- guc_policies_init(>policies);
-
- /* MMIO reg state */
- for_each_engine(engine, dev_priv, id) {
- blob->reg_state.white_list[engine->guc_id].mmio_start =
- engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
-
- /* Nothing to be saved or restored for now. */
- blob->reg_state.white_list[engine->guc_id].count = 0;
- }
-
- /*
-* The GuC requires a "Golden Context" when it reinitialises
-* engines after a reset. Here we use the Render ring default
-* context, which must already exist and be pinned in the GGTT,
-* so its address won't change after we've told the GuC where
-* to find it.
-*/
- blob->ads.golden_context_lrca =
- dev_priv->engine[RCS]->status_page.ggtt_offset;
-
- for_each_engine(engine, dev_priv, id)
- blob->ads.eng_state_size[engine->guc_id] = engine->context_size;
-
- base = guc_ggtt_offset(vma);
- blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
- blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer);
- blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state);
-
- kunmap(page);
-
- return 0;
-}
-
-static void guc_ads_destroy(struct intel_guc *guc)
-{
- i915_vma_unpin_and_release(>ads_vma);
-}
-
/*
* Set up the memory resources to be shared with the GuC (via the GGTT)
* at firmware loading time.
*/
-int i915_guc_submission_init(struct drm_i915_private *dev_priv)
+int i915_guc_su
[Intel-gfx] [PATCH v3 2/2] drm/i915/guc : Decouple logs from submission
The Additional Data Struct (ADS) contains objects that are required by
guc post FW load and are not necessarily submission-only (although that's
our current only use-case). If in the future we load GuC with submission
disabled to use some other GuC feature we might still end up requiring
something inside the ADS, so it makes more sense for them to be always
created if GuC is loaded.
Similarly, we still want to access GuC logs even if GuC submission is
disable to debug issues with GuC loading or with wathever we're using GuC for.
v2: Decoupling ads together with logs
v3: Group initialization of GuC objects
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
---
drivers/gpu/drm/i915/i915_guc_submission.c | 108 ++
drivers/gpu/drm/i915/intel_uc.c| 140 ++---
drivers/gpu/drm/i915/intel_uc.h| 6 +-
3 files changed, 134 insertions(+), 120 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index a15146e..3a4bdb4 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -70,14 +70,6 @@
* represents in-order queue. The kernel driver packs ring tail pointer and an
* ELSP context descriptor dword into Work Item.
* See guc_wq_item_append()
- *
- * ADS:
- * The Additional Data Struct (ADS) has pointers for different buffers used by
- * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
- * scheduling policies (guc_policies), a structure describing a collection of
- * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
- * its internal state for sleep.
- *
*/
static inline bool is_high_priority(struct i915_guc_client* client)
@@ -996,7 +988,7 @@ static void guc_client_free(struct i915_guc_client *client)
kfree(client);
}
-static void guc_policies_init(struct guc_policies *policies)
+void i915_guc_policies_init(struct guc_policies *policies)
{
struct guc_policy *policy;
u32 p, i;
@@ -1018,83 +1010,14 @@ static void guc_policies_init(struct guc_policies
*policies)
policies->is_valid = 1;
}
-static int guc_ads_create(struct intel_guc *guc)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- struct i915_vma *vma;
- struct page *page;
- /* The ads obj includes the struct itself and buffers passed to GuC */
- struct {
- struct guc_ads ads;
- struct guc_policies policies;
- struct guc_mmio_reg_state reg_state;
- u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
- } __packed *blob;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
- u32 base;
-
- GEM_BUG_ON(guc->ads_vma);
-
- vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(sizeof(*blob)));
- if (IS_ERR(vma))
- return PTR_ERR(vma);
-
- guc->ads_vma = vma;
-
- page = i915_vma_first_page(vma);
- blob = kmap(page);
-
- /* GuC scheduling policies */
- guc_policies_init(>policies);
-
- /* MMIO reg state */
- for_each_engine(engine, dev_priv, id) {
- blob->reg_state.white_list[engine->guc_id].mmio_start =
- engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
-
- /* Nothing to be saved or restored for now. */
- blob->reg_state.white_list[engine->guc_id].count = 0;
- }
-
- /*
-* The GuC requires a "Golden Context" when it reinitialises
-* engines after a reset. Here we use the Render ring default
-* context, which must already exist and be pinned in the GGTT,
-* so its address won't change after we've told the GuC where
-* to find it.
-*/
- blob->ads.golden_context_lrca =
- dev_priv->engine[RCS]->status_page.ggtt_offset;
-
- for_each_engine(engine, dev_priv, id)
- blob->ads.eng_state_size[engine->guc_id] = engine->context_size;
-
- base = guc_ggtt_offset(vma);
- blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
- blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer);
- blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state);
-
- kunmap(page);
-
- return 0;
-}
-
-static void guc_ads_destroy(struct intel_guc *guc)
-{
- i915_vma_unpin_and_release(>ads_vma);
-}
-
/*
* Set up the memory resources to be shared with the GuC (via the GGTT)
* at firmware loading time.
*/
-int i915_guc_submission_init(struct drm_i915_private *dev_priv)
+int i915_guc_su
[Intel-gfx] [PATCH v3 1/2] drm/i915/guc : Removing enable_guc_loading module
We currently have two module parameters that control GuC: "enable_guc_loading"
and "enable_guc_submission".
Whenever we need i915.enable_guc_submission=1, we also need
enable_guc_loading=1.
We also need enable_guc_loading=1 when we want to verify the HuC, which is
every time we have a HuC (but all platforms with HuC have a GuC and viceversa).
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, correcting inconsistencies (Michal)
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c| 18 +++---
drivers/gpu/drm/i915/i915_drv.c| 4 +-
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/i915_guc_submission.c | 15 -
drivers/gpu/drm/i915/intel_guc_loader.c| 50 ++---
drivers/gpu/drm/i915/intel_guc_log.c | 6 +-
drivers/gpu/drm/i915/intel_huc.c | 14 ++---
drivers/gpu/drm/i915/intel_uc.c| 90 ++
drivers/gpu/drm/i915/intel_uc.h| 3 +-
9 files changed, 97 insertions(+), 104 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 7cc53c2..9396de0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1612,7 +1612,7 @@ static int i915_fbc_status(struct seq_file *m, void
*unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
if (!HAS_FBC(dev_priv)) {
- seq_puts(m, "FBC unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -1779,7 +1779,7 @@ static int i915_ring_freq_table(struct seq_file *m, void
*unused)
unsigned int max_gpu_freq, min_gpu_freq;
if (!HAS_LLC(dev_priv)) {
- seq_puts(m, "unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2339,7 +2339,7 @@ static int i915_huc_load_status_info(struct seq_file *m,
void *data)
struct intel_uc_fw *huc_fw = _priv->huc.fw;
if (!HAS_GUC(dev_priv)){
- seq_puts(m, "No HuC support in HW\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2375,7 +2375,7 @@ static int i915_guc_load_status_info(struct seq_file *m,
void *data)
u32 tmp, i;
if (!HAS_GUC(dev_priv)){
- seq_puts(m, "No GuC supprot in HW\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2476,7 +2476,7 @@ static bool check_guc_submission(struct seq_file *m)
const struct intel_guc *guc = _priv->guc;
if (!guc->execbuf_client) {
- seq_printf(m, "GuC submission %s\n",
+ seq_printf(m,
HAS_GUC(dev_priv) ?
"disabled" :
"not supported");
@@ -2666,7 +2666,7 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
bool enabled = false;
if (!HAS_PSR(dev_priv)) {
- seq_puts(m, "PSR not supported\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2819,7 +2819,7 @@ static int i915_runtime_pm_status(struct seq_file *m,
void *unused)
struct pci_dev *pdev = dev_priv->drm.pdev;
if (!HAS_RUNTIME_PM(dev_priv))
- seq_puts(m, "Runtime power management not supported\n");
+ seq_puts(m, "not supported\n");
seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
seq_printf(m, "IRQs disabled: %s\n",
@@ -3639,7 +3639,7 @@ static void drrs_status_per_crtc(struct seq_file *m,
mutex_unlock(>mutex);
} else {
/* DRRS not supported. Print the VBT parameter*/
- seq_puts(m, "\tDRRS Supported : No");
+ seq_puts(m, "not supported\n");
}
seq_puts(m, "\n");
}
@@ -5039,4 +5039,4 @@ int i915_debugfs_connector_add(struct drm_connector
*connector)
connector, _panel_fops);
return 0;
-}
+}
\ No newline at end of file
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 00594dc..1c8d136 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1046,7 +1046,7 @@ static void intel_sanitize_options(struct
drm_i915
[Intel-gfx] [PATCH v2 2/2] drm/i915/guc : Decouple logs from submission
The Additional Data Struct (ADS) contains objects that are required by
guc post FW load and are not necessarily submission-only (although that's
our current only use-case). If in the future we load GuC with submission
disabled to use some other GuC feature we might still end up requiring
something inside the ADS, so it makes more sense for them to be always
created if GuC is loaded.
Similarly, we still want to access GuC logs even if GuC submission is
disable to debug issues with GuC loading or with wathever we're using GuC for.
v2: Decoupling ads together with logs
v2: Group initialization of GuC objects
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
---
drivers/gpu/drm/i915/i915_guc_submission.c | 108 ++
drivers/gpu/drm/i915/intel_uc.c| 140 ++---
drivers/gpu/drm/i915/intel_uc.h| 6 +-
3 files changed, 134 insertions(+), 120 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index a15146e..3a4bdb4 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -70,14 +70,6 @@
* represents in-order queue. The kernel driver packs ring tail pointer and an
* ELSP context descriptor dword into Work Item.
* See guc_wq_item_append()
- *
- * ADS:
- * The Additional Data Struct (ADS) has pointers for different buffers used by
- * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
- * scheduling policies (guc_policies), a structure describing a collection of
- * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
- * its internal state for sleep.
- *
*/
static inline bool is_high_priority(struct i915_guc_client* client)
@@ -996,7 +988,7 @@ static void guc_client_free(struct i915_guc_client *client)
kfree(client);
}
-static void guc_policies_init(struct guc_policies *policies)
+void i915_guc_policies_init(struct guc_policies *policies)
{
struct guc_policy *policy;
u32 p, i;
@@ -1018,83 +1010,14 @@ static void guc_policies_init(struct guc_policies
*policies)
policies->is_valid = 1;
}
-static int guc_ads_create(struct intel_guc *guc)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- struct i915_vma *vma;
- struct page *page;
- /* The ads obj includes the struct itself and buffers passed to GuC */
- struct {
- struct guc_ads ads;
- struct guc_policies policies;
- struct guc_mmio_reg_state reg_state;
- u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
- } __packed *blob;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
- u32 base;
-
- GEM_BUG_ON(guc->ads_vma);
-
- vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(sizeof(*blob)));
- if (IS_ERR(vma))
- return PTR_ERR(vma);
-
- guc->ads_vma = vma;
-
- page = i915_vma_first_page(vma);
- blob = kmap(page);
-
- /* GuC scheduling policies */
- guc_policies_init(>policies);
-
- /* MMIO reg state */
- for_each_engine(engine, dev_priv, id) {
- blob->reg_state.white_list[engine->guc_id].mmio_start =
- engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
-
- /* Nothing to be saved or restored for now. */
- blob->reg_state.white_list[engine->guc_id].count = 0;
- }
-
- /*
-* The GuC requires a "Golden Context" when it reinitialises
-* engines after a reset. Here we use the Render ring default
-* context, which must already exist and be pinned in the GGTT,
-* so its address won't change after we've told the GuC where
-* to find it.
-*/
- blob->ads.golden_context_lrca =
- dev_priv->engine[RCS]->status_page.ggtt_offset;
-
- for_each_engine(engine, dev_priv, id)
- blob->ads.eng_state_size[engine->guc_id] = engine->context_size;
-
- base = guc_ggtt_offset(vma);
- blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
- blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer);
- blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state);
-
- kunmap(page);
-
- return 0;
-}
-
-static void guc_ads_destroy(struct intel_guc *guc)
-{
- i915_vma_unpin_and_release(>ads_vma);
-}
-
/*
* Set up the memory resources to be shared with the GuC (via the GGTT)
* at firmware loading time.
*/
-int i915_guc_submission_init(struct drm_i915_private *dev_priv)
+int i915_guc_su
[Intel-gfx] [PATCH v2 2/2] drm/i915/guc : Decouple logs from submission
v2: Decoupling ADS together with logs
v2: Group initialization of GuC objects
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
---
drivers/gpu/drm/i915/i915_guc_submission.c | 108 ++
drivers/gpu/drm/i915/intel_uc.c| 140 ++---
drivers/gpu/drm/i915/intel_uc.h| 6 +-
3 files changed, 134 insertions(+), 120 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index a15146e..3a4bdb4 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -70,14 +70,6 @@
* represents in-order queue. The kernel driver packs ring tail pointer and an
* ELSP context descriptor dword into Work Item.
* See guc_wq_item_append()
- *
- * ADS:
- * The Additional Data Struct (ADS) has pointers for different buffers used by
- * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
- * scheduling policies (guc_policies), a structure describing a collection of
- * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
- * its internal state for sleep.
- *
*/
static inline bool is_high_priority(struct i915_guc_client* client)
@@ -996,7 +988,7 @@ static void guc_client_free(struct i915_guc_client *client)
kfree(client);
}
-static void guc_policies_init(struct guc_policies *policies)
+void i915_guc_policies_init(struct guc_policies *policies)
{
struct guc_policy *policy;
u32 p, i;
@@ -1018,83 +1010,14 @@ static void guc_policies_init(struct guc_policies
*policies)
policies->is_valid = 1;
}
-static int guc_ads_create(struct intel_guc *guc)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- struct i915_vma *vma;
- struct page *page;
- /* The ads obj includes the struct itself and buffers passed to GuC */
- struct {
- struct guc_ads ads;
- struct guc_policies policies;
- struct guc_mmio_reg_state reg_state;
- u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
- } __packed *blob;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
- u32 base;
-
- GEM_BUG_ON(guc->ads_vma);
-
- vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(sizeof(*blob)));
- if (IS_ERR(vma))
- return PTR_ERR(vma);
-
- guc->ads_vma = vma;
-
- page = i915_vma_first_page(vma);
- blob = kmap(page);
-
- /* GuC scheduling policies */
- guc_policies_init(>policies);
-
- /* MMIO reg state */
- for_each_engine(engine, dev_priv, id) {
- blob->reg_state.white_list[engine->guc_id].mmio_start =
- engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
-
- /* Nothing to be saved or restored for now. */
- blob->reg_state.white_list[engine->guc_id].count = 0;
- }
-
- /*
-* The GuC requires a "Golden Context" when it reinitialises
-* engines after a reset. Here we use the Render ring default
-* context, which must already exist and be pinned in the GGTT,
-* so its address won't change after we've told the GuC where
-* to find it.
-*/
- blob->ads.golden_context_lrca =
- dev_priv->engine[RCS]->status_page.ggtt_offset;
-
- for_each_engine(engine, dev_priv, id)
- blob->ads.eng_state_size[engine->guc_id] = engine->context_size;
-
- base = guc_ggtt_offset(vma);
- blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
- blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer);
- blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state);
-
- kunmap(page);
-
- return 0;
-}
-
-static void guc_ads_destroy(struct intel_guc *guc)
-{
- i915_vma_unpin_and_release(>ads_vma);
-}
-
/*
* Set up the memory resources to be shared with the GuC (via the GGTT)
* at firmware loading time.
*/
-int i915_guc_submission_init(struct drm_i915_private *dev_priv)
+int i915_guc_submission_shared_objects_init(struct intel_guc *guc)
{
- struct intel_guc *guc = _priv->guc;
struct i915_vma *vma;
void *vaddr;
- int ret;
if (guc->stage_desc_pool)
return 0;
@@ -1109,42 +1032,21 @@ int i915_guc_submission_init(struct drm_i915_private
*dev_priv)
vaddr = i915_gem_object_pin_map(guc->stage_desc_pool->obj, I915_MAP_WB);
if (IS_ERR(vaddr)) {
- ret = PTR_ERR(vaddr);
- goto err_vma;
+
[Intel-gfx] [PATCH v2 1/2] drm/i915/guc : Removing enable_guc_loading module
We currently have two module parameters that control GuC: "enable_guc_loading"
and "enable_guc_submission".
Whenever we need i915.enable_guc_submission=1, we also need
enable_guc_loading=1.
We also need enable_guc_loading=1 when we want to verify the HuC, which is
every time we have a HuC (but all platforms with HuC have a GuC and viceversa).
v2: Unify seq_puts messages, correcting inconsistencies (Michal)
v2: Clarifying the commit message (Anusha)
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c| 18 +++---
drivers/gpu/drm/i915/i915_drv.c| 4 +-
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/i915_guc_submission.c | 15 -
drivers/gpu/drm/i915/intel_guc_loader.c| 50 ++---
drivers/gpu/drm/i915/intel_guc_log.c | 6 +-
drivers/gpu/drm/i915/intel_huc.c | 14 ++---
drivers/gpu/drm/i915/intel_uc.c| 90 ++
drivers/gpu/drm/i915/intel_uc.h| 3 +-
9 files changed, 97 insertions(+), 104 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 7cc53c2..9396de0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1612,7 +1612,7 @@ static int i915_fbc_status(struct seq_file *m, void
*unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
if (!HAS_FBC(dev_priv)) {
- seq_puts(m, "FBC unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -1779,7 +1779,7 @@ static int i915_ring_freq_table(struct seq_file *m, void
*unused)
unsigned int max_gpu_freq, min_gpu_freq;
if (!HAS_LLC(dev_priv)) {
- seq_puts(m, "unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2339,7 +2339,7 @@ static int i915_huc_load_status_info(struct seq_file *m,
void *data)
struct intel_uc_fw *huc_fw = _priv->huc.fw;
if (!HAS_GUC(dev_priv)){
- seq_puts(m, "No HuC support in HW\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2375,7 +2375,7 @@ static int i915_guc_load_status_info(struct seq_file *m,
void *data)
u32 tmp, i;
if (!HAS_GUC(dev_priv)){
- seq_puts(m, "No GuC supprot in HW\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2476,7 +2476,7 @@ static bool check_guc_submission(struct seq_file *m)
const struct intel_guc *guc = _priv->guc;
if (!guc->execbuf_client) {
- seq_printf(m, "GuC submission %s\n",
+ seq_printf(m,
HAS_GUC(dev_priv) ?
"disabled" :
"not supported");
@@ -2666,7 +2666,7 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
bool enabled = false;
if (!HAS_PSR(dev_priv)) {
- seq_puts(m, "PSR not supported\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2819,7 +2819,7 @@ static int i915_runtime_pm_status(struct seq_file *m,
void *unused)
struct pci_dev *pdev = dev_priv->drm.pdev;
if (!HAS_RUNTIME_PM(dev_priv))
- seq_puts(m, "Runtime power management not supported\n");
+ seq_puts(m, "not supported\n");
seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
seq_printf(m, "IRQs disabled: %s\n",
@@ -3639,7 +3639,7 @@ static void drrs_status_per_crtc(struct seq_file *m,
mutex_unlock(>mutex);
} else {
/* DRRS not supported. Print the VBT parameter*/
- seq_puts(m, "\tDRRS Supported : No");
+ seq_puts(m, "not supported\n");
}
seq_puts(m, "\n");
}
@@ -5039,4 +5039,4 @@ int i915_debugfs_connector_add(struct drm_connector
*connector)
connector, _panel_fops);
return 0;
-}
+}
\ No newline at end of file
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 00594dc..1c8d136 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1046,7 +1046,7 @@ static void intel_sanitize_options(struct
drm_i915
[Intel-gfx] [PATCH v2 2/2] drm/i915/guc : Decouple logs from submission
The Additional Data Struct (ADS) contains objects that are required by
guc post FW load and are not necessarily submission-only (although that's
our current only use-case). If in the future we load GuC with submission
disabled to use some other GuC feature we might still end up requiring
something inside the ADS, so it makes more sense for them to be always
created if GuC is loaded.
Similarly, we still want to access GuC logs even if GuC submission is
disable to debug issues with GuC loading or with wathever we're using GuC for.
v2: Decoupling ads together with logs
v2: Group initialization of GuC objects
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
---
drivers/gpu/drm/i915/i915_guc_submission.c | 108 ++
drivers/gpu/drm/i915/intel_uc.c| 140 ++---
drivers/gpu/drm/i915/intel_uc.h| 6 +-
3 files changed, 134 insertions(+), 120 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index a15146e..3a4bdb4 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -70,14 +70,6 @@
* represents in-order queue. The kernel driver packs ring tail pointer and an
* ELSP context descriptor dword into Work Item.
* See guc_wq_item_append()
- *
- * ADS:
- * The Additional Data Struct (ADS) has pointers for different buffers used by
- * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
- * scheduling policies (guc_policies), a structure describing a collection of
- * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
- * its internal state for sleep.
- *
*/
static inline bool is_high_priority(struct i915_guc_client* client)
@@ -996,7 +988,7 @@ static void guc_client_free(struct i915_guc_client *client)
kfree(client);
}
-static void guc_policies_init(struct guc_policies *policies)
+void i915_guc_policies_init(struct guc_policies *policies)
{
struct guc_policy *policy;
u32 p, i;
@@ -1018,83 +1010,14 @@ static void guc_policies_init(struct guc_policies
*policies)
policies->is_valid = 1;
}
-static int guc_ads_create(struct intel_guc *guc)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- struct i915_vma *vma;
- struct page *page;
- /* The ads obj includes the struct itself and buffers passed to GuC */
- struct {
- struct guc_ads ads;
- struct guc_policies policies;
- struct guc_mmio_reg_state reg_state;
- u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
- } __packed *blob;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
- u32 base;
-
- GEM_BUG_ON(guc->ads_vma);
-
- vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(sizeof(*blob)));
- if (IS_ERR(vma))
- return PTR_ERR(vma);
-
- guc->ads_vma = vma;
-
- page = i915_vma_first_page(vma);
- blob = kmap(page);
-
- /* GuC scheduling policies */
- guc_policies_init(>policies);
-
- /* MMIO reg state */
- for_each_engine(engine, dev_priv, id) {
- blob->reg_state.white_list[engine->guc_id].mmio_start =
- engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
-
- /* Nothing to be saved or restored for now. */
- blob->reg_state.white_list[engine->guc_id].count = 0;
- }
-
- /*
-* The GuC requires a "Golden Context" when it reinitialises
-* engines after a reset. Here we use the Render ring default
-* context, which must already exist and be pinned in the GGTT,
-* so its address won't change after we've told the GuC where
-* to find it.
-*/
- blob->ads.golden_context_lrca =
- dev_priv->engine[RCS]->status_page.ggtt_offset;
-
- for_each_engine(engine, dev_priv, id)
- blob->ads.eng_state_size[engine->guc_id] = engine->context_size;
-
- base = guc_ggtt_offset(vma);
- blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
- blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer);
- blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state);
-
- kunmap(page);
-
- return 0;
-}
-
-static void guc_ads_destroy(struct intel_guc *guc)
-{
- i915_vma_unpin_and_release(>ads_vma);
-}
-
/*
* Set up the memory resources to be shared with the GuC (via the GGTT)
* at firmware loading time.
*/
-int i915_guc_submission_init(struct drm_i915_private *dev_priv)
+int i915_guc_su
[Intel-gfx] [PATCH v2 1/2] drm/i915/guc : Removing enable_guc_loading module
We currently have two module parameters that control GuC: "enable_guc_loading"
and "enable_guc_submission".
Whenever we need i915.enable_guc_submission=1, we also need
enable_guc_loading=1.
We also need enable_guc_loading=1 when we want to verify the HuC, which is
every time we have a HuC (but all platforms with HuC have a GuC and viceversa).
v2: Unify seq_puts messages, correcting inconsistencies (Michal)
v2: Clarifying the commit message (Anusha)
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c| 18 +++---
drivers/gpu/drm/i915/i915_drv.c| 4 +-
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/i915_guc_submission.c | 15 -
drivers/gpu/drm/i915/intel_guc_loader.c| 50 ++---
drivers/gpu/drm/i915/intel_guc_log.c | 6 +-
drivers/gpu/drm/i915/intel_huc.c | 14 ++---
drivers/gpu/drm/i915/intel_uc.c| 90 ++
drivers/gpu/drm/i915/intel_uc.h| 3 +-
9 files changed, 97 insertions(+), 104 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 7cc53c2..9396de0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1612,7 +1612,7 @@ static int i915_fbc_status(struct seq_file *m, void
*unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
if (!HAS_FBC(dev_priv)) {
- seq_puts(m, "FBC unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -1779,7 +1779,7 @@ static int i915_ring_freq_table(struct seq_file *m, void
*unused)
unsigned int max_gpu_freq, min_gpu_freq;
if (!HAS_LLC(dev_priv)) {
- seq_puts(m, "unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2339,7 +2339,7 @@ static int i915_huc_load_status_info(struct seq_file *m,
void *data)
struct intel_uc_fw *huc_fw = _priv->huc.fw;
if (!HAS_GUC(dev_priv)){
- seq_puts(m, "No HuC support in HW\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2375,7 +2375,7 @@ static int i915_guc_load_status_info(struct seq_file *m,
void *data)
u32 tmp, i;
if (!HAS_GUC(dev_priv)){
- seq_puts(m, "No GuC supprot in HW\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2476,7 +2476,7 @@ static bool check_guc_submission(struct seq_file *m)
const struct intel_guc *guc = _priv->guc;
if (!guc->execbuf_client) {
- seq_printf(m, "GuC submission %s\n",
+ seq_printf(m,
HAS_GUC(dev_priv) ?
"disabled" :
"not supported");
@@ -2666,7 +2666,7 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
bool enabled = false;
if (!HAS_PSR(dev_priv)) {
- seq_puts(m, "PSR not supported\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2819,7 +2819,7 @@ static int i915_runtime_pm_status(struct seq_file *m,
void *unused)
struct pci_dev *pdev = dev_priv->drm.pdev;
if (!HAS_RUNTIME_PM(dev_priv))
- seq_puts(m, "Runtime power management not supported\n");
+ seq_puts(m, "not supported\n");
seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
seq_printf(m, "IRQs disabled: %s\n",
@@ -3639,7 +3639,7 @@ static void drrs_status_per_crtc(struct seq_file *m,
mutex_unlock(>mutex);
} else {
/* DRRS not supported. Print the VBT parameter*/
- seq_puts(m, "\tDRRS Supported : No");
+ seq_puts(m, "not supported\n");
}
seq_puts(m, "\n");
}
@@ -5039,4 +5039,4 @@ int i915_debugfs_connector_add(struct drm_connector
*connector)
connector, _panel_fops);
return 0;
-}
+}
\ No newline at end of file
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 00594dc..1c8d136 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1046,7 +1046,7 @@ static void intel_sanitize_options(struct
drm_i915
[Intel-gfx] [PATCH 2/2] drm/i915/guc : Enable GuC logs even when submission is not enabled
Currently, we only enable GuC logs when enable_guc_submission is set.
But we could be interested in getting GuC logs in other cases as well.
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Joonas Lahtinen <joonas.lahti...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h| 2 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 13 ++---
drivers/gpu/drm/i915/intel_guc_log.c | 6 +++---
drivers/gpu/drm/i915/intel_uc.c| 22 +-
drivers/gpu/drm/i915/intel_uc.h| 1 +
5 files changed, 28 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8e18c67..437c3c6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3065,7 +3065,7 @@ static inline struct scatterlist *__sg_next(struct
scatterlist *sg)
* properties, so we have separate macros to test them.
*/
#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
-#define HAS_GUC(dev_priv) ((dev_priv)->info.has.guc)
+#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
#define HAS_GUC_UCODE(dev_priv)((dev_priv)->guc.fw.path !=
NULL)
#define HAS_HUC_UCODE(dev_priv)((dev_priv)->huc.fw.path !=
NULL)
#define NEEDS_GUC_LOADING(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 48a1e93..639e0d8 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1109,16 +1109,12 @@ int i915_guc_submission_init(struct drm_i915_private
*dev_priv)
vaddr = i915_gem_object_pin_map(guc->stage_desc_pool->obj, I915_MAP_WB);
if (IS_ERR(vaddr)) {
- ret = PTR_ERR(vaddr);
- goto err_vma;
+ i915_vma_unpin_and_release(>stage_desc_pool);
+ return PTR_ERR(vaddr);
}
guc->stage_desc_pool_vaddr = vaddr;
- ret = intel_guc_log_create(guc);
- if (ret < 0)
- goto err_vaddr;
-
ret = guc_ads_create(guc);
if (ret < 0)
goto err_log;
@@ -1129,10 +1125,6 @@ int i915_guc_submission_init(struct drm_i915_private
*dev_priv)
err_log:
intel_guc_log_destroy(guc);
-err_vaddr:
- i915_gem_object_unpin_map(guc->stage_desc_pool->obj);
-err_vma:
- i915_vma_unpin_and_release(>stage_desc_pool);
return ret;
}
@@ -1142,7 +1134,6 @@ void i915_guc_submission_fini(struct drm_i915_private
*dev_priv)
ida_destroy(>stage_ids);
guc_ads_destroy(guc);
- intel_guc_log_destroy(guc);
i915_gem_object_unpin_map(guc->stage_desc_pool->obj);
i915_vma_unpin_and_release(>stage_desc_pool);
}
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c
b/drivers/gpu/drm/i915/intel_guc_log.c
index 16d3b87..592b449 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -502,7 +502,7 @@ static void guc_flush_logs(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
- if (!i915.enable_guc_submission || (i915.guc_log_level < 0))
+ if (HAS_GUC_UCODE(dev_priv) || (i915.guc_log_level < 0))
return;
/* First disable the interrupts, will be renabled afterwards */
@@ -641,7 +641,7 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv,
u64 control_val)
void i915_guc_log_register(struct drm_i915_private *dev_priv)
{
- if (!i915.enable_guc_submission || i915.guc_log_level < 0)
+ if (HAS_GUC_UCODE(dev_priv) || i915.guc_log_level < 0)
return;
mutex_lock(_priv->drm.struct_mutex);
@@ -651,7 +651,7 @@ void i915_guc_log_register(struct drm_i915_private
*dev_priv)
void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
{
- if (!i915.enable_guc_submission)
+ if (HAS_GUC_UCODE(dev_priv))
return;
mutex_lock(_priv->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index d8fab3a..44faeac 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -298,6 +298,20 @@ static void guc_disable_communication(struct intel_guc
*guc)
guc->send = intel_guc_send_nop;
}
+static int guc_shared_objects_init(struct intel_guc *guc)
+{
+ int ret;
+
+ ret = intel_guc_log_create(guc);
+ if (ret < 0)
+ return ret;
+}
+
+static void guc_shared_objects_fini(struct intel_guc *guc)
+{
+ intel_guc_log_destroy(guc);
+}
+
int intel_uc_init_hw(struct drm_i915_private *dev_priv)
{
struct intel_guc *guc = _priv->guc;
@@ -311,6 +325,9 @@ int inte
[Intel-gfx] [PATCH 0/2] Changes to GuC loading and GuC logs
*** BLURB HERE *** Sujaritha Sundaresan (2): drm/i915/guc : Removing enable_guc_loading module drm/i915/guc : Enable GuC logs even when submission is not enabled drivers/gpu/drm/i915/i915_debugfs.c| 12 +++-- drivers/gpu/drm/i915/i915_drv.c| 2 +- drivers/gpu/drm/i915/i915_drv.h| 10 ++-- drivers/gpu/drm/i915/i915_gem_context.c| 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c| 2 +- drivers/gpu/drm/i915/i915_guc_submission.c | 13 + drivers/gpu/drm/i915/i915_irq.c| 2 +- drivers/gpu/drm/i915/i915_params.c | 6 --- drivers/gpu/drm/i915/i915_params.h | 1 - drivers/gpu/drm/i915/intel_guc_loader.c| 48 +++--- drivers/gpu/drm/i915/intel_guc_log.c | 6 +-- drivers/gpu/drm/i915/intel_huc.c | 4 +- drivers/gpu/drm/i915/intel_uc.c| 80 +- drivers/gpu/drm/i915/intel_uc.h| 5 +- drivers/gpu/drm/i915/intel_uncore.c| 4 +- 15 files changed, 107 insertions(+), 90 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/guc : Removing enable_guc_loading module
Whenever we need i915.enable_guc_submission=1, we also need
enable_guc_loading=1. We also need enable_guc_loading=1 when we want to verify
the HuC, which is every time we have a HuC (but all platforms with HuC have a
GuC and viceversa).
We don't need the user to tell when to enable the GuC loading
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Joonas Lahtinen <joonas.lahti...@intel.com>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +--
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 10 +++---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/i915_params.c | 6
drivers/gpu/drm/i915/i915_params.h | 1 -
drivers/gpu/drm/i915/intel_guc_loader.c | 48 +++
drivers/gpu/drm/i915/intel_huc.c| 4 ++-
drivers/gpu/drm/i915/intel_uc.c | 58 -
drivers/gpu/drm/i915/intel_uc.h | 4 +--
drivers/gpu/drm/i915/intel_uncore.c | 4 +--
13 files changed, 80 insertions(+), 75 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 329fb36..7cc53c2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2338,8 +2338,11 @@ static int i915_huc_load_status_info(struct seq_file *m,
void *data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct intel_uc_fw *huc_fw = _priv->huc.fw;
- if (!HAS_HUC_UCODE(dev_priv))
+ if (!HAS_GUC(dev_priv)){
+ seq_puts(m, "No HuC support in HW\n");
return 0;
+ }
+
seq_puts(m, "HuC firmware status:\n");
seq_printf(m, "\tpath: %s\n", huc_fw->path);
@@ -2371,8 +2374,11 @@ static int i915_guc_load_status_info(struct seq_file *m,
void *data)
struct intel_uc_fw *guc_fw = _priv->guc.fw;
u32 tmp, i;
- if (!HAS_GUC_UCODE(dev_priv))
+ if (!HAS_GUC(dev_priv)){
+ seq_puts(m, "No GuC supprot in HW\n");
return 0;
+ }
+
seq_printf(m, "GuC firmware status:\n");
seq_printf(m, "\tpath: %s\n",
@@ -2471,7 +2477,7 @@ static bool check_guc_submission(struct seq_file *m)
if (!guc->execbuf_client) {
seq_printf(m, "GuC submission %s\n",
- HAS_GUC_SCHED(dev_priv) ?
+ HAS_GUC(dev_priv) ?
"disabled" :
"not supported");
return false;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 25de4a9..00594dc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1046,7 +1046,7 @@ static void intel_sanitize_options(struct
drm_i915_private *dev_priv)
i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915.semaphores));
- intel_uc_sanitize_options(dev_priv);
+ intel_guc_sanitize_submission(dev_priv);
intel_gvt_sanitize_options(dev_priv);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 907603c..8e18c67 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3064,11 +3064,13 @@ static inline struct scatterlist *__sg_next(struct
scatterlist *sg)
* command submission once loaded. But these are logically independent
* properties, so we have separate macros to test them.
*/
-#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
-#define HAS_GUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_GUC_SCHED(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_HUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
+#define HAS_GUC(dev_priv) ((dev_priv)->info.has.guc)
+#define HAS_GUC_UCODE(dev_priv)((dev_priv)->guc.fw.path !=
NULL)
+#define HAS_HUC_UCODE(dev_priv)((dev_priv)->huc.fw.path !=
NULL)
+#define NEEDS_GUC_LOADING(dev_priv) \
+ (HAS_GUC(dev_priv) && \
+ (i915.enable_guc_submission || HAS_HUC_UCODE(dev_priv)))
#define HAS_RESOURCE_STREAMER(dev_priv)
((dev_priv)->info.has_resource_streamer)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index ed91ac8..5166a43 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -361,7 +361,7 @@ static u32 default_desc_template(const struct
drm_i915_private *i915,
