[Intel-gfx] [PATCH V3] drm/i915/dg2: add Wa_14014947963

[clinton . a . taylor]

From: Clint Taylor 

BSPEC: 46123
v2: Address review feedback [MattR]
v3: move register definition to gt_regs [MattR]
Cc: Matt Roper 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index a6f0220c2e9f..5c8c3bc65acc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -124,6 +124,9 @@
 #define   ECOCHK_PPGTT_WT_HSW  (0x2 << 3)
 #define   ECOCHK_PPGTT_WB_HSW  (0x3 << 3)
 
+#define VF_PREEMPTION  _MMIO(0x83a4)
+#define  PREEMPTION_VERTEX_COUNT   REG_GENMASK(15, 0)
+
 #define GEN8_RC6_CTX_INFO  _MMIO(0x8504)
 
 #define GAC_ECO_BITS   _MMIO(0x14090)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b146a393cd79..9416b1434c64 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -689,6 +689,11 @@ static void dg2_ctx_workarounds_init(struct 
intel_engine_cs *engine,
IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0))
wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
 DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA);
+
+   /* wa_14014947963: dg2_g10 [B0..NONE] dg2_g11 dg2_g12 */
+   if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) ||
+   IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
+   wa_masked_field_set(wal, VF_PREEMPTION, 
PREEMPTION_VERTEX_COUNT, 0x4000);
 }
 
 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
-- 
2.34.1

[Intel-gfx] [PATCH v2] drm/i915/dg2: add Wa_14014947963

[clinton . a . taylor]

From: Clint Taylor 

BSPEC: 46123
v2: Address review feedback [MattR]
Cc: Matt Roper 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
 drivers/gpu/drm/i915/i915_reg.h | 2 ++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b146a393cd79..c6b78529d149 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -689,6 +689,11 @@ static void dg2_ctx_workarounds_init(struct 
intel_engine_cs *engine,
IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0))
wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
 DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA);
+
+   /* wa_14014947963: DG2 G10 [B0..NONE] G11 [ALL] */
+   if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) ||
+   IS_DG2_G11(engine->i915))
+   wa_masked_field_set(wal, VF_PREEMPTION, 
PREEMPTION_VERTEX_COUNT, 0x4000);
 }
 
 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 87c92314ee26..bfbeebe57725 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9928,4 +9928,6 @@ enum skl_power_gate {
 #define CLKGATE_DIS_MISC   _MMIO(0x46534)
 #define  CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)
 
+#define VF_PREEMPTION  _MMIO(0x83a4)
+#define  PREEMPTION_VERTEX_COUNT   REG_GENMASK(15, 0)
 #endif /* _I915_REG_H_ */
-- 
2.34.1

[Intel-gfx] [PATCH] drm/i915/dg2: add Wa_14015023722

[clinton . a . taylor]

From: Clint Taylor 

BSPEC: 46123
Cc: Matt Roper 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
 drivers/gpu/drm/i915/i915_reg.h | 4 
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 6a4372c3a3c5..5cdacfa8aefc 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -688,6 +688,11 @@ static void dg2_ctx_workarounds_init(struct 
intel_engine_cs *engine,
IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0))
wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
 DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA);
+
+   /* wa_14015023722: DG2 G11 [B0..NONE] */
+   if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_B0, STEP_FOREVER))
+   wa_masked_en(wal, VF_PREEMPTION, PREEMPTION_VERTEX_4000);
+
 }
 
 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ef6bc8180073..5805a45920b3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11934,4 +11934,8 @@ enum skl_power_gate {
 #define SLICE_COMMON_ECO_CHICKEN1  _MMIO(0x731C)
 #define   MSC_MSAA_REODER_BUF_BYPASS_DISABLE   REG_BIT(14)
 
+#define VF_PREEMPTION  _MMIO(0x83a4)
+#define  PREEMPTION_VERTEX_COUNT   REG_GENMASK(15, 0)
+#define  PREEMPTION_VERTEX_4000
REG_FIELD_PREP(PREEMPTION_VERTEX_COUNT, 0x4000)
+
 #endif /* _I915_REG_H_ */
-- 
2.34.1

[Intel-gfx] [PATCH] drm/i915/snps: vswing value refined for SNPS phys

[clinton . a . taylor]

From: Clint Taylor 

Updated new values from BSPEC.

BSPEC: 53920

Cc: Jani Nikula 
Cc: José Roberto de Souza 
Cc: Imre Deak 
Signed-off-by: Clint Taylor 
---
 .../drm/i915/display/intel_ddi_buf_trans.c| 42 +--
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c 
b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 1e689d573512..09d6ab13536c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -985,15 +985,15 @@ static const struct intel_ddi_buf_trans 
adlp_dkl_phy_trans_dp_hbr2_hbr3 = {
 };
 
 static const union intel_ddi_buf_trans_entry _dg2_snps_trans[] = {
-   { .snps = { 26, 0, 0 } },   /* VS 0, pre-emph 0 */
-   { .snps = { 33, 0, 6 } },   /* VS 0, pre-emph 1 */
-   { .snps = { 38, 0, 12 } },  /* VS 0, pre-emph 2 */
-   { .snps = { 43, 0, 19 } },  /* VS 0, pre-emph 3 */
-   { .snps = { 39, 0, 0 } },   /* VS 1, pre-emph 0 */
-   { .snps = { 44, 0, 8 } },   /* VS 1, pre-emph 1 */
-   { .snps = { 47, 0, 15 } },  /* VS 1, pre-emph 2 */
-   { .snps = { 52, 0, 0 } },   /* VS 2, pre-emph 0 */
-   { .snps = { 51, 0, 10 } },  /* VS 2, pre-emph 1 */
+   { .snps = { 25, 0, 0 } },   /* VS 0, pre-emph 0 */
+   { .snps = { 32, 0, 6 } },   /* VS 0, pre-emph 1 */
+   { .snps = { 35, 0, 10 } },  /* VS 0, pre-emph 2 */
+   { .snps = { 43, 0, 17 } },  /* VS 0, pre-emph 3 */
+   { .snps = { 35, 0, 0 } },   /* VS 1, pre-emph 0 */
+   { .snps = { 45, 0, 8 } },   /* VS 1, pre-emph 1 */
+   { .snps = { 48, 0, 14 } },  /* VS 1, pre-emph 2 */
+   { .snps = { 47, 0, 0 } },   /* VS 2, pre-emph 0 */
+   { .snps = { 55, 0, 7 } },   /* VS 2, pre-emph 1 */
{ .snps = { 62, 0, 0 } },   /* VS 3, pre-emph 0 */
 };
 
@@ -1005,21 +1005,21 @@ static const struct intel_ddi_buf_trans dg2_snps_trans 
= {
 
 static const union intel_ddi_buf_trans_entry _dg2_snps_trans_uhbr[] = {
{ .snps = { 62, 0, 0 } },   /* preset 0 */
-   { .snps = { 56, 0, 6 } },   /* preset 1 */
-   { .snps = { 51, 0, 11 } },  /* preset 2 */
-   { .snps = { 48, 0, 14 } },  /* preset 3 */
-   { .snps = { 43, 0, 19 } },  /* preset 4 */
+   { .snps = { 55, 0, 7 } },   /* preset 1 */
+   { .snps = { 50, 0, 12 } },  /* preset 2 */
+   { .snps = { 44, 0, 18 } },  /* preset 3 */
+   { .snps = { 35, 0, 21 } },  /* preset 4 */
{ .snps = { 59, 3, 0 } },   /* preset 5 */
{ .snps = { 53, 3, 6 } },   /* preset 6 */
-   { .snps = { 49, 3, 10 } },  /* preset 7 */
-   { .snps = { 45, 3, 14 } },  /* preset 8 */
-   { .snps = { 42, 3, 17 } },  /* preset 9 */
+   { .snps = { 48, 3, 11 } },  /* preset 7 */
+   { .snps = { 42, 5, 15 } },  /* preset 8 */
+   { .snps = { 37, 5, 20 } },  /* preset 9 */
{ .snps = { 56, 6, 0 } },   /* preset 10 */
-   { .snps = { 50, 6, 6 } },   /* preset 11 */
-   { .snps = { 47, 6, 9 } },   /* preset 12 */
-   { .snps = { 42, 6, 14 } },  /* preset 13 */
-   { .snps = { 46, 8, 8 } },   /* preset 14 */
-   { .snps = { 56, 3, 3 } },   /* preset 15 */
+   { .snps = { 48, 7, 7 } },   /* preset 11 */
+   { .snps = { 45, 7, 10 } },  /* preset 12 */
+   { .snps = { 39, 8, 15 } },  /* preset 13 */
+   { .snps = { 48, 14, 0 } },  /* preset 14 */
+   { .snps = { 45, 4, 4 } },   /* preset 15 */
 };
 
 static const struct intel_ddi_buf_trans dg2_snps_trans_uhbr = {
-- 
2.34.1

[Intel-gfx] [PATCH v2] drm/i915/adlp: Remove require_force_probe protection

[clinton . a . taylor]

From: Clint Taylor 

Remove force probe protection from ADL_P platform. Did not obsevre
warnings, errors, flickering or any visual defects while doing ordinary
tasks like browsing and editing documents in a two monitor setup.

For more info drm-tip idle run results :
https://intel-gfx-ci.01.org/tree/drm-tip/drmtip.html?

Cc: Rodrigo Vivi 
Acked-by: Jon Bloomfield 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_pci.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f01cba4ec283..0ba516838b02 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -977,7 +977,6 @@ static const struct intel_device_info adl_p_info = {
GEN12_FEATURES,
XE_LPD_FEATURES,
PLATFORM(INTEL_ALDERLAKE_P),
-   .require_force_probe = 1,
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
   BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
   BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
-- 
2.33.1

[Intel-gfx] [PATCH] drm/i915/adlp: Remove require_force_probe protection

[clinton . a . taylor]

From: Clint Taylor 

drm/i915/adlp: Remove require_force_probe protection

Removing force probe protection from ADL_P platform. Did
not observe warnings, errors, flickering or any visual
defects while doing ordinary tasks like browsing and
editing documents in a two monitor setup.

For more info drm-tip idle run results :
https://intel-gfx-ci.01.org/tree/drm-tip/drmtip.html?

Cc: Rodrigo Vivi 

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_pci.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 4c7fcc5f9a97..af9f4988bd88 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -970,7 +970,6 @@ static const struct intel_device_info adl_p_info = {
GEN12_FEATURES,
XE_LPD_FEATURES,
PLATFORM(INTEL_ALDERLAKE_P),
-   .require_force_probe = 1,
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
   BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
   BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
-- 
2.33.1

[Intel-gfx] [PATCH v2] drm/i915/adl_p: Add initial ADL_P Workarounds

[clinton . a . taylor]

From: Clint Taylor 

Most of the context WA are already implemented.
Adding adl_p platform tag to reflect so.

v2: adjust comments for clarity (MattR)

BSpec: 54369
Cc: Matt Roper 
Cc: Aditya Swarup 
Reviewed-by: Matt Roper 
Signed-off-by: Radhakrishna Sripada 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Madhumitha Tolakanahalli Pradeep 

Signed-off-by: José Roberto de Souza 
Signed-off-by: Swathi Dhanavanthri 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  4 +-
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 39 ++-
 drivers/gpu/drm/i915/intel_pm.c   |  8 ++--
 4 files changed, 29 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 71ac57670043..882bfd499e55 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2667,7 +2667,7 @@ static bool cnl_ddi_hdmi_pll_dividers(struct 
intel_crtc_state *crtc_state)
 }
 
 /*
- * Display WA #22010492432: ehl, tgl
+ * Display WA #22010492432: ehl, tgl, adl-p
  * Program half of the nominal DCO divider fraction value.
  */
 static bool
@@ -2675,7 +2675,7 @@ ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private 
*i915)
 {
return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
 IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER)) ||
-IS_TIGERLAKE(i915)) &&
+IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&
 i915->dpll.ref_clks.nssc == 38400;
 }
 
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 94e0a5669f90..87b06572fd2e 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -208,7 +208,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
flags |= PIPE_CONTROL_FLUSH_L3;
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
-   /* Wa_1409600907:tgl */
+   /* Wa_1409600907:tgl,adl-p */
flags |= PIPE_CONTROL_DEPTH_STALL;
flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
flags |= PIPE_CONTROL_FLUSH_ENABLE;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b62d1e31a645..977a76e648e0 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -640,15 +640,16 @@ static void gen12_ctx_workarounds_init(struct 
intel_engine_cs *engine,
gen12_ctx_gt_tuning_init(engine, wal);
 
/*
-* Wa_1409142259:tgl
-* Wa_1409347922:tgl
-* Wa_1409252684:tgl
-* Wa_1409217633:tgl
-* Wa_1409207793:tgl
-* Wa_1409178076:tgl
-* Wa_1408979724:tgl
-* Wa_14010443199:rkl
-* Wa_14010698770:rkl
+* Wa_1409142259:tgl,dg1,adl-p
+* Wa_1409347922:tgl,dg1,adl-p
+* Wa_1409252684:tgl,dg1,adl-p
+* Wa_1409217633:tgl,dg1,adl-p
+* Wa_1409207793:tgl,dg1,adl-p
+* Wa_1409178076:tgl,dg1,adl-p
+* Wa_1408979724:tgl,dg1,adl-p
+* Wa_14010443199:tgl,rkl,dg1,adl-p
+* Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p
+* Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p
 */
wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
@@ -1113,7 +1114,7 @@ gen12_gt_workarounds_init(struct drm_i915_private *i915,
 {
wa_init_mcr(i915, wal);
 
-   /* Wa_14011060649:tgl,rkl,dg1,adls */
+   /* Wa_14011060649:tgl,rkl,dg1,adls,adl-p */
wa_14011060649(i915, wal);
 }
 
@@ -1633,38 +1634,40 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, 
struct i915_wa_list *wal)
GEN7_DISABLE_SAMPLER_PREFETCH);
}
 
-   if (IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
+   if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
-   /* Wa_1606931601:tgl,rkl,dg1,adl-s */
+   /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
 
/*
 * Wa_1407928979:tgl A*
 * Wa_18011464164:tgl[B0+],dg1[B0+]
 * Wa_22010931296:tgl[B0+],dg1[B0+]
-* Wa_14010919138:rkl,dg1,adl-s
+* Wa_14010919138:rkl,dg1,adl-s,adl-p
 */
wa_write_or(wal, GEN7_FF_THREAD_MODE,
GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
 
/*
-* Wa_1606700617:tgl,dg1
-* Wa_22010271021:tgl,rkl,dg1, adl-s
+* Wa_1606700617:tgl,dg1,adl-p
+* 

[Intel-gfx] [PATCH] drm/i915/adl_p: Add initial ADL_P Workarounds

[clinton . a . taylor]

From: Clint Taylor 

Most of the context WA are already implemented.
Adding adl_p platform tag to reflect so.

BSpec: 54369
Cc: Matt Roper 
Cc: Aditya Swarup 
Signed-off-by: Radhakrishna Sripada 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Madhumitha Tolakanahalli Pradeep 

Signed-off-by: José Roberto de Souza 
Signed-off-by: Swathi Dhanavanthri 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  2 +-
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 39 ++-
 drivers/gpu/drm/i915/intel_pm.c   |  8 ++--
 4 files changed, 28 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 71ac57670043..79746d5c1378 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2675,7 +2675,7 @@ ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private 
*i915)
 {
return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
 IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER)) ||
-IS_TIGERLAKE(i915)) &&
+IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&
 i915->dpll.ref_clks.nssc == 38400;
 }
 
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 94e0a5669f90..87b06572fd2e 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -208,7 +208,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
flags |= PIPE_CONTROL_FLUSH_L3;
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
-   /* Wa_1409600907:tgl */
+   /* Wa_1409600907:tgl,adl-p */
flags |= PIPE_CONTROL_DEPTH_STALL;
flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
flags |= PIPE_CONTROL_FLUSH_ENABLE;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b62d1e31a645..e62cadb3fcd8 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -640,15 +640,16 @@ static void gen12_ctx_workarounds_init(struct 
intel_engine_cs *engine,
gen12_ctx_gt_tuning_init(engine, wal);
 
/*
-* Wa_1409142259:tgl
-* Wa_1409347922:tgl
-* Wa_1409252684:tgl
-* Wa_1409217633:tgl
-* Wa_1409207793:tgl
-* Wa_1409178076:tgl
-* Wa_1408979724:tgl
-* Wa_14010443199:rkl
-* Wa_14010698770:rkl
+* Wa_1409142259:tgl,adl-p
+* Wa_1409347922:tgl,adl-p
+* Wa_1409252684:tgl,adl-p
+* Wa_1409217633:tgl,adl-p
+* Wa_1409207793:tgl,adl-p
+* Wa_1409178076:tgl,adl-p
+* Wa_1408979724:tgl,adl-p
+* Wa_14010443199:rkl,adl-p
+* Wa_14010698770:rkl,adl-p
+* Wa_1409342910:adl-p
 */
wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
@@ -1113,7 +1114,7 @@ gen12_gt_workarounds_init(struct drm_i915_private *i915,
 {
wa_init_mcr(i915, wal);
 
-   /* Wa_14011060649:tgl,rkl,dg1,adls */
+   /* Wa_14011060649:tgl,rkl,dg1,adls,adl-p */
wa_14011060649(i915, wal);
 }
 
@@ -1633,38 +1634,40 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, 
struct i915_wa_list *wal)
GEN7_DISABLE_SAMPLER_PREFETCH);
}
 
-   if (IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
+   if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
-   /* Wa_1606931601:tgl,rkl,dg1,adl-s */
+   /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
 
/*
 * Wa_1407928979:tgl A*
 * Wa_18011464164:tgl[B0+],dg1[B0+]
 * Wa_22010931296:tgl[B0+],dg1[B0+]
-* Wa_14010919138:rkl,dg1,adl-s
+* Wa_14010919138:rkl,dg1,adl-s,adl-p
 */
wa_write_or(wal, GEN7_FF_THREAD_MODE,
GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
 
/*
-* Wa_1606700617:tgl,dg1
-* Wa_22010271021:tgl,rkl,dg1, adl-s
+* Wa_1606700617:tgl,dg1,adl-p
+* Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p
+* Wa_14010826681:tgl,dg1,rkl,adl-p
 */
wa_masked_en(wal,
 GEN9_CS_DEBUG_MODE1,
 FF_DOP_CLOCK_GATE_DISABLE);
}
 
-   if (IS_ALDERLAKE_S(i915) || IS_DG1_REVID(i915, DG1_REVID_A0, 
DG1_REVID_A0) ||
+   if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
+   

[Intel-gfx] [PATCH] drm/i915/display: support ddr5 mem types

[clinton . a . taylor]

From: Clint Taylor 

Add DDR5 and LPDDR5 return values from punit fw.

BSPEC: 54023
Cc: Matt Roper 
Cc: José Roberto de Souza 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/display/intel_bw.c | 12 +++-
 drivers/gpu/drm/i915/i915_drv.h |  4 +++-
 drivers/gpu/drm/i915/intel_dram.c   |  6 ++
 3 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
b/drivers/gpu/drm/i915/display/intel_bw.c
index ba9e713585e7..d122b9965532 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -78,7 +78,17 @@ static int icl_get_qgv_points(struct drm_i915_private 
*dev_priv,
qi->num_points = dram_info->num_qgv_points;
 
if (IS_GEN(dev_priv, 12))
-   qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 16;
+   switch (dram_info->type) {
+   case INTEL_DRAM_DDR4:
+   qi->t_bl = 4;
+   break;
+   case INTEL_DRAM_DDR5:
+   qi->t_bl = 8;
+   break;
+   default:
+   qi->t_bl = 16;
+   break;
+   }
else if (IS_GEN(dev_priv, 11))
qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a2fd7e5039b3..8083a50908bf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1136,7 +1136,9 @@ struct drm_i915_private {
INTEL_DRAM_DDR3,
INTEL_DRAM_DDR4,
INTEL_DRAM_LPDDR3,
-   INTEL_DRAM_LPDDR4
+   INTEL_DRAM_LPDDR4,
+   INTEL_DRAM_DDR5,
+   INTEL_DRAM_LPDDR5,
} type;
u8 num_qgv_points;
} dram_info;
diff --git a/drivers/gpu/drm/i915/intel_dram.c 
b/drivers/gpu/drm/i915/intel_dram.c
index 73d256fc6830..1e53c017c30d 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -427,6 +427,12 @@ static int icl_pcode_read_mem_global_info(struct 
drm_i915_private *dev_priv)
case 0:
dram_info->type = INTEL_DRAM_DDR4;
break;
+   case 1:
+   dram_info->type = INTEL_DRAM_DDR5;
+   break;
+   case 2:
+   dram_info->type = INTEL_DRAM_LPDDR5;
+   break;
case 3:
dram_info->type = INTEL_DRAM_LPDDR4;
break;
-- 
2.29.2

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[Intel-gfx] [PATCH v4] drm/i915/gt: Implement WA_1406941453

[clinton . a . taylor]

From: Clint Taylor 

Enable HW Default flip for small PL.

bspec: 52890
bspec: 53508
bspec: 53273

v2: rebase to drm-tip
v3: move from ctx to gt workarounds. Remove whitelist.
v4: move to rcs WA init

Cc: Matt Atwood 
Cc: Matt Roper 
Cc: José Roberto de Souza 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a3f72b75c61e..b0a7cb056633 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1725,6 +1725,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, 
struct i915_wa_list *wal)
 FF_DOP_CLOCK_GATE_DISABLE);
}
 
+   if (IS_GEN(i915, 12)) {
+   /* Wa_1406941453:gen12 */
+   wa_masked_en(wal,
+GEN10_SAMPLER_MODE,
+ENABLE_SMALLPL);
+   }
+
if (IS_GEN(i915, 11)) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ac691927e29d..ab4b1abd4364 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9315,6 +9315,7 @@ enum {
 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC  (1 << 7)
 
 #define GEN10_SAMPLER_MODE _MMIO(0xE18C)
+#define   ENABLE_SMALLPL   REG_BIT(15)
 #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSGREG_BIT(5)
 
 /* IVYBRIDGE DPF */
-- 
2.28.0

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[Intel-gfx] [PATCH v3] drm/i915/gt: Implement WA_1406941453

[clinton . a . taylor]

From: Clint Taylor 

Enable HW Default flip for small PL.

bspec: 52890
bspec: 53508
bspec: 53273

v2: rebase to drm-tip
v3: move from ctx to gt workarounds. Remove whitelist.

Cc: Matt Atwood 
Cc: Matt Roper 
Cc: José Roberto de Souza 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a3f72b75c61e..0aecb97fd41c 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1211,6 +1211,9 @@ gen12_gt_workarounds_init(struct drm_i915_private *i915,
  struct i915_wa_list *wal)
 {
wa_init_mcr(i915, wal);
+
+   /* Wa_1406941453:gen12 */
+   WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE, ENABLE_SMALLPL);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ac691927e29d..ab4b1abd4364 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9315,6 +9315,7 @@ enum {
 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC  (1 << 7)
 
 #define GEN10_SAMPLER_MODE _MMIO(0xE18C)
+#define   ENABLE_SMALLPL   REG_BIT(15)
 #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSGREG_BIT(5)
 
 /* IVYBRIDGE DPF */
-- 
2.28.0

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[Intel-gfx] [PATCH v2] drm/i915/gt: Implement WA_1406941453

[clinton . a . taylor]

From: Clint Taylor 

Enable HW Default flip for small PL.

bspec: 52890
bspec: 53508
bspec: 53273

v2: rebase to drm-tip
Reviewed-by: Matt Atwood 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index cef1c122696f..cb02813c5e92 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -639,6 +639,9 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs 
*engine,
   FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK,
   FF_MODE2_GS_TIMER_224  | FF_MODE2_TDS_TIMER_128,
   0);
+
+   /* Wa_1406941453:gen12 */
+   WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE, ENABLE_SMALLPL);
 }
 
 static void
@@ -1522,6 +1525,9 @@ static void icl_whitelist_build(struct intel_engine_cs 
*engine)
whitelist_reg_ext(w, PS_INVOCATION_COUNT,
  RING_FORCE_TO_NONPRIV_ACCESS_RD |
  RING_FORCE_TO_NONPRIV_RANGE_4);
+
+   /* Wa_1406941453:gen12 */
+   whitelist_reg(w, GEN10_SAMPLER_MODE);
break;
 
case VIDEO_DECODE_CLASS:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2b403df03404..494b2e1e358e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9314,6 +9314,7 @@ enum {
 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC  (1 << 7)
 
 #define GEN10_SAMPLER_MODE _MMIO(0xE18C)
+#define   ENABLE_SMALLPL   REG_BIT(15)
 #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSGREG_BIT(5)
 
 /* IVYBRIDGE DPF */
-- 
2.27.0

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[Intel-gfx] [PATCH] drm/i915/gt: Implement WA_1406941453

[clinton . a . taylor]

From: Clint Taylor 

Enable HW Default flip for small PL.

bspec: 52890
bspec: 53508
bspec: 53273

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 2da366821dda..0b9091c05e06 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -628,6 +628,9 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs 
*engine,
WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
GEN9_PREEMPT_GPGPU_LEVEL_MASK,
GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
+
+   /* Wa_1406941453:gen12 */
+   WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE, ENABLE_SMALLPL);
 }
 
 static void
@@ -1500,6 +1503,9 @@ static void icl_whitelist_build(struct intel_engine_cs 
*engine)
whitelist_reg_ext(w, PS_INVOCATION_COUNT,
  RING_FORCE_TO_NONPRIV_ACCESS_RD |
  RING_FORCE_TO_NONPRIV_RANGE_4);
+
+   /* Wa_1406941453:gen12 */
+   whitelist_reg(w, GEN10_SAMPLER_MODE);
break;
 
case VIDEO_DECODE_CLASS:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 19e1fed198c3..fbb095a94b3a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9223,6 +9223,7 @@ enum {
 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC  (1 << 7)
 
 #define GEN10_SAMPLER_MODE _MMIO(0xE18C)
+#define   ENABLE_SMALLPL   REG_BIT(15)
 #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSGREG_BIT(5)
 
 /* IVYBRIDGE DPF */
-- 
2.26.0

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[Intel-gfx] [PATCH v2] drm/i915/tgl: Implement WA_16011163337

[clinton . a . taylor]

From: Clint Taylor 

Set GS Timer to 224. Combine with Wa_1604555607 due to register FF_MODE2
not being able to be read.

V2: Math issue fixed

Cc: Chris Wilson 
Cc: Caz Yokoyama 
Cc: Matt Atwood 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 
 drivers/gpu/drm/i915/i915_reg.h | 2 ++
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 30cd798b9664..a2d5624e5542 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -609,11 +609,11 @@ static void tgl_ctx_workarounds_init(struct 
intel_engine_cs *engine,
 * Wa_1604555607:gen12 and Wa_1608008084:gen12
 * FF_MODE2 register will return the wrong value when read. The default
 * value for this register is zero for all fields and there are no bit
-* masks. So instead of doing a RMW we should just write the TDS timer
-* value for Wa_1604555607.
+* masks. So instead of doing a RMW we should just write the GS Timer
+* and TDS timer values for Wa_1604555607 and Wa_16011163337.
 */
-   wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
-  FF_MODE2_TDS_TIMER_128, 0);
+   wa_add(wal, FF_MODE2, FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK,
+  FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128, 0);
 
/* WaDisableGPGPUMidThreadPreemption:tgl */
WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 578cfe11cbb9..96d351fbeebb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8004,6 +8004,8 @@ enum {
 #define   PER_PIXEL_ALPHA_BYPASS_EN(1 << 7)
 
 #define FF_MODE2   _MMIO(0x6604)
+#define   FF_MODE2_GS_TIMER_MASK   REG_GENMASK(31, 24)
+#define   FF_MODE2_GS_TIMER_224
REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
 #define   FF_MODE2_TDS_TIMER_MASK  REG_GENMASK(23, 16)
 #define   FF_MODE2_TDS_TIMER_128   REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 
4)
 
-- 
2.26.0

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[Intel-gfx] [PATCH] drm/i915/tgl: Implement WA_16011163337

[clinton . a . taylor]

From: Clint Taylor 

Set GS Timer to 224. Combine with Wa_1604555607 due to register FF_MODE2
not being able to be read.

Cc: Caz Yokoyama 
Cc: Matt Atwood 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 
 drivers/gpu/drm/i915/i915_reg.h | 2 ++
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index fa1e15657663..7bc6474cce0e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -594,11 +594,11 @@ static void tgl_ctx_workarounds_init(struct 
intel_engine_cs *engine,
 * Wa_1604555607:gen12 and Wa_1608008084:gen12
 * FF_MODE2 register will return the wrong value when read. The default
 * value for this register is zero for all fields and there are no bit
-* masks. So instead of doing a RMW we should just write the TDS timer
-* value for Wa_1604555607.
+* masks. So instead of doing a RMW we should just write the GS Timer
+* and TDS timer values for Wa_1604555607 and Wa_16011163337.
 */
-   wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
-  FF_MODE2_TDS_TIMER_128, 0);
+   wa_add(wal, FF_MODE2, FF_MODE2_GS_TIMER_MASK & FF_MODE2_TDS_TIMER_MASK,
+  FF_MODE2_GS_TIMER_224 & FF_MODE2_TDS_TIMER_128, 0);
 
/* WaDisableGPGPUMidThreadPreemption:tgl */
WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 578cfe11cbb9..96d351fbeebb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8004,6 +8004,8 @@ enum {
 #define   PER_PIXEL_ALPHA_BYPASS_EN(1 << 7)
 
 #define FF_MODE2   _MMIO(0x6604)
+#define   FF_MODE2_GS_TIMER_MASK   REG_GENMASK(31, 24)
+#define   FF_MODE2_GS_TIMER_224
REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
 #define   FF_MODE2_TDS_TIMER_MASK  REG_GENMASK(23, 16)
 #define   FF_MODE2_TDS_TIMER_128   REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 
4)
 
-- 
2.26.0

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[Intel-gfx] [PATCH v3] drm/i915: Disable display interrupts during display IRQ handler

[clinton . a . taylor]

From: Clint Taylor 

During the Display Interrupt Service routine the Display Interrupt
Enable bit must be disabled, The interrupts handled, then the
Display Interrupt Enable bit must be set to prevent possible missed
interrupts.

Bspec: 49212
V2: Change Title to remove SDE reference.
V3: Fix TAB spacing.

Cc: Lucas De Marchi 
Cc: Aditya Swarup 

Reviewed-by: Matt Roper 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_irq.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dae00f7dd7df..8b338744eddf 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2484,7 +2484,11 @@ __gen11_irq_handler(struct drm_i915_private * const i915,
 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
 * for the display related bits.
 */
+   raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
gen8_de_irq_handler(i915, disp_ctl);
+   raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
+ GEN11_DISPLAY_IRQ_ENABLE);
+
enable_rpm_wakeref_asserts(>runtime_pm);
}
 
-- 
2.19.1

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[Intel-gfx] [PATCH] drm/i915: Disable display interrupts during display IRQ handler

[clinton . a . taylor]

From: Clint Taylor 

During the Display Interrupt Service routine the Display Interrupt
Enable bit must be disabled, The interrupts handled, then the
Display Interrupt Enable bit must be set to prevent possible missed
interrupts.

Bspec: 49212
Cc: Lucas De Marchi 
Cc: Aditya Swarup 

Reviewed-by: Matt Roper 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_irq.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dae00f7dd7df..43434273a08a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2484,7 +2484,11 @@ __gen11_irq_handler(struct drm_i915_private * const i915,
 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
 * for the display related bits.
 */
+   raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
gen8_de_irq_handler(i915, disp_ctl);
+   raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
+ GEN11_DISPLAY_IRQ_ENABLE);
+
enable_rpm_wakeref_asserts(>runtime_pm);
}
 
-- 
2.19.1

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[Intel-gfx] [PATCH] drm/i915: Disable display interrupts during SDE IRQ handler

[clinton . a . taylor]

From: Clint Taylor 

During the Display Interrupt Service routine the Display Interrupt
Enable bit must be disabled, The interrupts handled, then the
Display Interrupt Enable bit must be set to prevent possible missed
interrupts.

Bspec: 49212
Cc: Lucas De Marchi 
Cc: Aditya Swarup 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_irq.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dae00f7dd7df..43434273a08a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2484,7 +2484,11 @@ __gen11_irq_handler(struct drm_i915_private * const i915,
 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
 * for the display related bits.
 */
+   raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
gen8_de_irq_handler(i915, disp_ctl);
+   raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
+ GEN11_DISPLAY_IRQ_ENABLE);
+
enable_rpm_wakeref_asserts(>runtime_pm);
}
 
-- 
2.19.1

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[Intel-gfx] [PATCH] drm/i915/ehl: Add port_cl_dw10 to combo phy vswing sequence

[clinton . a . taylor]

From: Clint Taylor 

Elkhart Lake has additional bits in port_cl_dw10 that should be set
during vswing programming. According to BSPEC these bits should be set
based on OEM selection. Since VBT does not contain a definition for
these bits we will currently clear them until VBT is updated to give
OEMs the ability to set them.

bspec: 21257
Cc: Matt Roper 
Cc: Jose Roberto de Souza 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 8 
 drivers/gpu/drm/i915/i915_reg.h  | 4 
 2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 7925a176f900..6bde92a4041a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2430,6 +2430,14 @@ static void icl_ddi_combo_vswing_program(struct 
drm_i915_private *dev_priv,
level = n_entries - 1;
}
 
+   /* set PORT_CL_DW10 */
+   if (IS_ELKHARTLAKE(dev_priv)) {
+   val = I915_READ(ICL_PORT_CL_DW10(port));
+   val &= ~(O_EDP4K2K_MODE_OVRD_EN | O_EDP4K2K_MODE_OVRD_VAL |
+   O_RTERM100EN_H_OVRD_EN | O_RTERM100EN_H_OVRD_VAL);
+   I915_WRITE(ICL_PORT_CL_DW10(port), val);
+   }
+
/* Set PORT_TX_DW5 */
val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7e6009cefb18..ce8602442480 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1819,6 +1819,10 @@ enum i915_power_well_id {
 #define  PWR_DOWN_LN_3_1_0 (0xb << 4)
 #define  PWR_DOWN_LN_MASK  (0xf << 4)
 #define  PWR_DOWN_LN_SHIFT 4
+#define  O_EDP4K2K_MODE_OVRD_EN(1 << 3)
+#define  O_EDP4K2K_MODE_OVRD_VAL   (1 << 2)
+#define  O_RTERM100EN_H_OVRD_EN(1 << 1)
+#define  O_RTERM100EN_H_OVRD_VAL   (1 << 0)
 
 #define ICL_PORT_CL_DW12(port) _MMIO(_ICL_PORT_CL_DW(12, port))
 #define   ICL_LANE_ENABLE_AUX  (1 << 0)
-- 
2.19.1

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[Intel-gfx] [PATCH] drm/i915/icl: Prevent possibe de-reference in skl_check_pipe_max_pixel_clock.

[clinton . a . taylor]

From: Clint Taylor 

Add protections to prevent NULL de-reference for a couple variables used
in skl_check_pipe_max_pixel_clock to prevent GP exception from occurring
during some IGT tests.

References: https://bugs.freedesktop.org/show_bug.cgi?id=109084

Cc: Rodrigo Vivi 
Cc: Martin Peres 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_display.c | 4 
 drivers/gpu/drm/i915/intel_pm.c  | 3 +++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 3bd40a4a6739..945861cef520 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11377,6 +11377,10 @@ static int intel_crtc_atomic_check(struct drm_crtc 
*crtc,
 
if (!ret)
ret = icl_check_nv12_planes(pipe_config);
+
+   if (WARN_ON(!intel_crtc))
+   return -EINVAL;
+
if (!ret)
ret = skl_check_pipe_max_pixel_rate(intel_crtc,
pipe_config);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7357bddf9ad9..df5d01d4345b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4160,6 +4160,9 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc 
*intel_crtc,
uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8);
int bpp;
 
+   if (WARN_ON(!pstate))
+   return -EINVAL;
+
if (!intel_wm_plane_visible(cstate,
to_intel_plane_state(pstate)))
continue;
-- 
2.19.1

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[Intel-gfx] [PATCH v5] drm/i915/icl: combo port vswing programming changes per BSPEC

[clinton . a . taylor]

From: Clint Taylor 

In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence. Restrict combo phy to
HBR max rate unless eDP panel is connected to port.

v2: remove debug code that Imre found
v3: simplify translation table if-else
v4: edp translation table now based on link rate and low_swing
v5: Misc review comments + r-b
BSpec: 21257
Cc: Ville Syrjälä 
Cc: Imre Deak 
Cc: Rodrigo Vivi 
Reviewed-by: Imre Deak 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_reg.h  |   4 +
 drivers/gpu/drm/i915/intel_ddi.c | 238 ++-
 drivers/gpu/drm/i915/intel_dp.c  |   4 +-
 3 files changed, 93 insertions(+), 153 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0796526..02af9b5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1884,6 +1884,10 @@ enum i915_power_well_id {
 
 #define CNL_PORT_TX_DW7_GRP(port)  _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
 #define CNL_PORT_TX_DW7_LN0(port)  _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
+#define ICL_PORT_TX_DW7_AUX(port)  _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
+#define ICL_PORT_TX_DW7_GRP(port)  _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
+#define ICL_PORT_TX_DW7_LN0(port)  _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
+#define ICL_PORT_TX_DW7_LN(port, ln)   _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
 #define   N_SCALAR(x)  ((x) << 24)
 #define   N_SCALAR_MASK(0x7F << 24)
 
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 92c0bf7..dfd3582 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -494,103 +494,58 @@ struct cnl_ddi_buf_trans {
{ 0x2, 0x7F, 0x3F, 0x00, 0x00 },/* 400   400  0.0   */
 };
 
-struct icl_combo_phy_ddi_buf_trans {
-   u32 dw2_swing_select;
-   u32 dw2_swing_scalar;
-   u32 dw4_scaling;
-};
-
-/* Voltage Swing Programming for VccIO 0.85V for DP */
-static const struct icl_combo_phy_ddi_buf_trans 
icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
-   /* Voltage mV  db*/
-   { 0x2, 0x98, 0x0018 },  /* 400 0.0   */
-   { 0x2, 0x98, 0x3015 },  /* 400 3.5   */
-   { 0x2, 0x98, 0x6012 },  /* 400 6.0   */
-   { 0x2, 0x98, 0x900F },  /* 400 9.5   */
-   { 0xB, 0x70, 0x0018 },  /* 600 0.0   */
-   { 0xB, 0x70, 0x3015 },  /* 600 3.5   */
-   { 0xB, 0x70, 0x6012 },  /* 600 6.0   */
-   { 0x5, 0x00, 0x0018 },  /* 800 0.0   */
-   { 0x5, 0x00, 0x3015 },  /* 800 3.5   */
-   { 0x6, 0x98, 0x0018 },  /* 12000.0   */
-};
-
-/* FIXME - After table is updated in Bspec */
-/* Voltage Swing Programming for VccIO 0.85V for eDP */
-static const struct icl_combo_phy_ddi_buf_trans 
icl_combo_phy_ddi_translations_edp_0_85V[] = {
-   /* Voltage mV  db*/
-   { 0x0, 0x00, 0x00 },/* 200 0.0   */
-   { 0x0, 0x00, 0x00 },/* 200 1.5   */
-   { 0x0, 0x00, 0x00 },/* 200 4.0   */
-   { 0x0, 0x00, 0x00 },/* 200 6.0   */
-   { 0x0, 0x00, 0x00 },/* 250 0.0   */
-   { 0x0, 0x00, 0x00 },/* 250 1.5   */
-   { 0x0, 0x00, 0x00 },/* 250 4.0   */
-   { 0x0, 0x00, 0x00 },/* 300 0.0   */
-   { 0x0, 0x00, 0x00 },/* 300 1.5   */
-   { 0x0, 0x00, 0x00 },/* 350 0.0   */
-};
-
-/* Voltage Swing Programming for VccIO 0.95V for DP */
-static const struct icl_combo_phy_ddi_buf_trans 
icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
-   /* Voltage mV  db*/
-   { 0x2, 0x98, 0x0018 },  /* 400 0.0   */
-   { 0x2, 0x98, 0x3015 },  /* 400 3.5   */
-   { 0x2, 0x98, 0x6012 },  /* 400 6.0   */
-   { 0x2, 0x98, 0x900F },  /* 400 9.5   */
-   { 0x4, 0x98, 0x0018 },  /* 600 0.0   */
-   { 0x4, 0x98, 0x3015 },  /* 600 3.5   */
-   { 0x4, 0x98, 0x6012 },  /* 600 6.0   */
-   { 0x5, 0x76, 0x0018 },  /* 800 0.0   */
-   { 0x5, 0x76, 0x3015 },  /* 800 3.5   */
-   { 0x6, 0x98, 0x0018 },  /* 12000.0   */
+/* icl_combo_phy_ddi_translations */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] 
= {
+   /* NT mV Trans mV db*/
+   { 0xA, 0x35, 0x3F, 0x00, 0x00 },/* 350   350  0.0   */
+   { 0xA, 0x4F, 0x37, 0x00, 0x08 },/* 350   500  3.1   */
+   { 0xC, 0x71, 0x2F, 0x00, 0x10 },/* 350   700  6.0   */
+   { 0x6, 0x7F, 0x2B, 0x00, 0x14 },/* 350   900  8.2   */
+   { 0xA, 0x4C, 0x3F, 0x00, 0x00 },/* 500   500  0.0   */
+   { 0xC, 0x73, 0x34, 0x00, 0x0B },/* 500   

[Intel-gfx] [PATCH] drm/i915/dsi: Add PORT_TX_DW7 programming to DSI vswing sequence

[clinton . a . taylor]

From: Clint Taylor 

Program PORT_TX_DW7 to the value specified in the DDI Buffer section of the
BSPEC.

BSEPC: 21257
Cc: Madhav Chauhan 
Cc: Jani Nikula 
Cc: Imre Deak 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/icl_dsi.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 4dd793b..f57aa0d 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -236,6 +236,16 @@ static void dsi_program_swing_and_deemphasis(struct 
intel_encoder *encoder)
tmp |= RCOMP_SCALAR(0x98);
I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
 
+   tmp = I915_READ(ICL_PORT_TX_DW7_LN0(port));
+   tmp &= ~(N_SCALAR_MASK);
+   tmp |= N_SCALAR(0x7f);
+   I915_WRITE(ICL_PORT_TX_DW7_GRP(port), tmp);
+
+   tmp = I915_READ(ICL_PORT_TX_DW7_AUX(port));
+   tmp &= ~(N_SCALAR_MASK);
+   tmp |= N_SCALAR(0x7f);
+   I915_WRITE(ICL_PORT_TX_DW7_AUX(port), tmp);
+
tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
 CURSOR_COEFF_MASK);
-- 
1.9.1

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[Intel-gfx] [PATCH v4] drm/i915/icl: combo port vswing programming changes per BSPEC

[clinton . a . taylor]

From: Clint Taylor 

In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence. Restrict combo phy to
HBR max rate unless eDP panel is connected to port.

v2: remove debug code that Imre found
v3: simplify translation table if-else
v4: edp translation table now based on link rate and low_swing
BSpec: 21257
Cc: Ville Syrjälä 
Cc: Imre Deak 
Cc: Rodrigo Vivi 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_reg.h  |   4 +
 drivers/gpu/drm/i915/intel_ddi.c | 240 ++-
 drivers/gpu/drm/i915/intel_dp.c  |   4 +-
 3 files changed, 95 insertions(+), 153 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a7d605..29acdb9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1866,6 +1866,10 @@ enum i915_power_well_id {
 
 #define CNL_PORT_TX_DW7_GRP(port)  _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
 #define CNL_PORT_TX_DW7_LN0(port)  _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
+#define ICL_PORT_TX_DW7_AUX(port)  _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
+#define ICL_PORT_TX_DW7_GRP(port)  _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
+#define ICL_PORT_TX_DW7_LN0(port)  _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
+#define ICL_PORT_TX_DW7_LN(port, ln)   _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
 #define   N_SCALAR(x)  ((x) << 24)
 #define   N_SCALAR_MASK(0x7F << 24)
 
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f3e1d6a..33bf77b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -494,103 +494,58 @@ struct cnl_ddi_buf_trans {
{ 0x2, 0x7F, 0x3F, 0x00, 0x00 },/* 400   400  0.0   */
 };
 
-struct icl_combo_phy_ddi_buf_trans {
-   u32 dw2_swing_select;
-   u32 dw2_swing_scalar;
-   u32 dw4_scaling;
-};
-
-/* Voltage Swing Programming for VccIO 0.85V for DP */
-static const struct icl_combo_phy_ddi_buf_trans 
icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
-   /* Voltage mV  db*/
-   { 0x2, 0x98, 0x0018 },  /* 400 0.0   */
-   { 0x2, 0x98, 0x3015 },  /* 400 3.5   */
-   { 0x2, 0x98, 0x6012 },  /* 400 6.0   */
-   { 0x2, 0x98, 0x900F },  /* 400 9.5   */
-   { 0xB, 0x70, 0x0018 },  /* 600 0.0   */
-   { 0xB, 0x70, 0x3015 },  /* 600 3.5   */
-   { 0xB, 0x70, 0x6012 },  /* 600 6.0   */
-   { 0x5, 0x00, 0x0018 },  /* 800 0.0   */
-   { 0x5, 0x00, 0x3015 },  /* 800 3.5   */
-   { 0x6, 0x98, 0x0018 },  /* 12000.0   */
-};
-
-/* FIXME - After table is updated in Bspec */
-/* Voltage Swing Programming for VccIO 0.85V for eDP */
-static const struct icl_combo_phy_ddi_buf_trans 
icl_combo_phy_ddi_translations_edp_0_85V[] = {
-   /* Voltage mV  db*/
-   { 0x0, 0x00, 0x00 },/* 200 0.0   */
-   { 0x0, 0x00, 0x00 },/* 200 1.5   */
-   { 0x0, 0x00, 0x00 },/* 200 4.0   */
-   { 0x0, 0x00, 0x00 },/* 200 6.0   */
-   { 0x0, 0x00, 0x00 },/* 250 0.0   */
-   { 0x0, 0x00, 0x00 },/* 250 1.5   */
-   { 0x0, 0x00, 0x00 },/* 250 4.0   */
-   { 0x0, 0x00, 0x00 },/* 300 0.0   */
-   { 0x0, 0x00, 0x00 },/* 300 1.5   */
-   { 0x0, 0x00, 0x00 },/* 350 0.0   */
-};
-
-/* Voltage Swing Programming for VccIO 0.95V for DP */
-static const struct icl_combo_phy_ddi_buf_trans 
icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
-   /* Voltage mV  db*/
-   { 0x2, 0x98, 0x0018 },  /* 400 0.0   */
-   { 0x2, 0x98, 0x3015 },  /* 400 3.5   */
-   { 0x2, 0x98, 0x6012 },  /* 400 6.0   */
-   { 0x2, 0x98, 0x900F },  /* 400 9.5   */
-   { 0x4, 0x98, 0x0018 },  /* 600 0.0   */
-   { 0x4, 0x98, 0x3015 },  /* 600 3.5   */
-   { 0x4, 0x98, 0x6012 },  /* 600 6.0   */
-   { 0x5, 0x76, 0x0018 },  /* 800 0.0   */
-   { 0x5, 0x76, 0x3015 },  /* 800 3.5   */
-   { 0x6, 0x98, 0x0018 },  /* 12000.0   */
+/* icl_combo_phy_ddi_translations */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] 
= {
+   /* NT mV Trans mV db*/
+   { 0xA, 0x35, 0x3F, 0x00, 0x00 },/* 350   350  0.0   */
+   { 0xA, 0x4F, 0x37, 0x00, 0x08 },/* 350   500  3.1   */
+   { 0xC, 0x71, 0x2F, 0x00, 0x10 },/* 350   700  6.0   */
+   { 0x6, 0x7F, 0x2B, 0x00, 0x14 },/* 350   900  8.2   */
+   { 0xA, 0x4C, 0x3F, 0x00, 0x00 },/* 500   500  0.0   */
+   { 0xC, 0x73, 0x34, 0x00, 0x0B },/* 500   700  2.9   */
+   { 0x6, 0x7F, 0x2F, 0x00, 

[Intel-gfx] [PATCH v3] /drm/i915/hdmi: SCDC Scrambling enable without CTS mode

[clinton . a . taylor]

From: Clint Taylor 

Setting the SCDC scrambling CTS mode causes HDMI Link Layer protocol tests
HF1-12 and HF1-13 to fail.

V2: Removed "Source Shall" entries to a new patch
V3: Rebase to drm-tip
Cc: Ville Syrjälä 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107895
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107896
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_ddi.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f3e1d6a..92c0bf7 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1880,7 +1880,7 @@ void intel_ddi_enable_transcoder_func(const struct 
intel_crtc_state *crtc_state)
temp |= TRANS_DDI_MODE_SELECT_DVI;
 
if (crtc_state->hdmi_scrambling)
-   temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
+   temp |= TRANS_DDI_HDMI_SCRAMBLING;
if (crtc_state->hdmi_high_tmds_clock_ratio)
temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
@@ -3793,8 +3793,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
if (intel_dig_port->infoframe_enabled(encoder, pipe_config))
pipe_config->has_infoframe = true;
 
-   if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
-   TRANS_DDI_HDMI_SCRAMBLING_MASK)
+   if (temp & TRANS_DDI_HDMI_SCRAMBLING)
pipe_config->hdmi_scrambling = true;
if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
pipe_config->hdmi_high_tmds_clock_ratio = true;
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3] drm/i915/icl: combo port vswing programming changes per BSPEC

[clinton . a . taylor]

From: Clint Taylor 

In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence.

v2: remove debug code that Imre found
v3: simplify translation table if-else

BSpec: 21257
Cc: Ville Syrjälä 
Cc: Imre Deak 
Cc: Rodrigo Vivi 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_reg.h  |   4 +
 drivers/gpu/drm/i915/intel_ddi.c | 224 ++-
 2 files changed, 85 insertions(+), 143 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a7d605..29acdb9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1866,6 +1866,10 @@ enum i915_power_well_id {
 
 #define CNL_PORT_TX_DW7_GRP(port)  _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
 #define CNL_PORT_TX_DW7_LN0(port)  _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
+#define ICL_PORT_TX_DW7_AUX(port)  _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
+#define ICL_PORT_TX_DW7_GRP(port)  _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
+#define ICL_PORT_TX_DW7_LN0(port)  _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
+#define ICL_PORT_TX_DW7_LN(port, ln)   _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
 #define   N_SCALAR(x)  ((x) << 24)
 #define   N_SCALAR_MASK(0x7F << 24)
 
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f3e1d6a..d78ec17 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -494,103 +494,63 @@ struct cnl_ddi_buf_trans {
{ 0x2, 0x7F, 0x3F, 0x00, 0x00 },/* 400   400  0.0   */
 };
 
-struct icl_combo_phy_ddi_buf_trans {
-   u32 dw2_swing_select;
-   u32 dw2_swing_scalar;
-   u32 dw4_scaling;
-};
-
-/* Voltage Swing Programming for VccIO 0.85V for DP */
-static const struct icl_combo_phy_ddi_buf_trans 
icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
-   /* Voltage mV  db*/
-   { 0x2, 0x98, 0x0018 },  /* 400 0.0   */
-   { 0x2, 0x98, 0x3015 },  /* 400 3.5   */
-   { 0x2, 0x98, 0x6012 },  /* 400 6.0   */
-   { 0x2, 0x98, 0x900F },  /* 400 9.5   */
-   { 0xB, 0x70, 0x0018 },  /* 600 0.0   */
-   { 0xB, 0x70, 0x3015 },  /* 600 3.5   */
-   { 0xB, 0x70, 0x6012 },  /* 600 6.0   */
-   { 0x5, 0x00, 0x0018 },  /* 800 0.0   */
-   { 0x5, 0x00, 0x3015 },  /* 800 3.5   */
-   { 0x6, 0x98, 0x0018 },  /* 12000.0   */
-};
-
-/* FIXME - After table is updated in Bspec */
-/* Voltage Swing Programming for VccIO 0.85V for eDP */
-static const struct icl_combo_phy_ddi_buf_trans 
icl_combo_phy_ddi_translations_edp_0_85V[] = {
-   /* Voltage mV  db*/
-   { 0x0, 0x00, 0x00 },/* 200 0.0   */
-   { 0x0, 0x00, 0x00 },/* 200 1.5   */
-   { 0x0, 0x00, 0x00 },/* 200 4.0   */
-   { 0x0, 0x00, 0x00 },/* 200 6.0   */
-   { 0x0, 0x00, 0x00 },/* 250 0.0   */
-   { 0x0, 0x00, 0x00 },/* 250 1.5   */
-   { 0x0, 0x00, 0x00 },/* 250 4.0   */
-   { 0x0, 0x00, 0x00 },/* 300 0.0   */
-   { 0x0, 0x00, 0x00 },/* 300 1.5   */
-   { 0x0, 0x00, 0x00 },/* 350 0.0   */
+/* icl_combo_phy_ddi_translations */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp[] = {
+   /* NT mV Trans mV db*/
+   { 0xA, 0x35, 0x3F, 0x00, 0x00 },/* 350   350  0.0   */
+   { 0xA, 0x4F, 0x37, 0x00, 0x08 },/* 350   500  3.1   */
+   { 0xC, 0x71, 0x2F, 0x00, 0x10 },/* 350   700  6.0   */
+   { 0x6, 0x7F, 0x2B, 0x00, 0x14 },/* 350   900  8.2   */
+   { 0xA, 0x4C, 0x3F, 0x00, 0x00 },/* 500   500  0.0   */
+   { 0xC, 0x73, 0x34, 0x00, 0x0B },/* 500   700  2.9   */
+   { 0x6, 0x7F, 0x2F, 0x00, 0x10 },/* 500   900  5.1   */
+   { 0xC, 0x6C, 0x3C, 0x00, 0x03 },/* 650   705  0.6   */
+   { 0x6, 0x7F, 0x35, 0x00, 0x0A },/* 600   900  3.5   */
+   { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900   900  0.0   */
 };
 
-/* Voltage Swing Programming for VccIO 0.95V for DP */
-static const struct icl_combo_phy_ddi_buf_trans 
icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
-   /* Voltage mV  db*/
-   { 0x2, 0x98, 0x0018 },  /* 400 0.0   */
-   { 0x2, 0x98, 0x3015 },  /* 400 3.5   */
-   { 0x2, 0x98, 0x6012 },  /* 400 6.0   */
-   { 0x2, 0x98, 0x900F },  /* 400 9.5   */
-   { 0x4, 0x98, 0x0018 },  /* 600 0.0   */
-   { 0x4, 0x98, 0x3015 },  /* 600 3.5   */
-   { 0x4, 0x98, 0x6012 },  /* 600 6.0   */
-   { 0x5, 0x76, 0x0018 },  /* 800 0.0   */
-   { 0x5, 0x76, 0x3015 },  

[Intel-gfx] [PATCH v2] drm/i915/icl: combo port vswing programming changes per BSPEC

[clinton . a . taylor]

From: Clint Taylor 

In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence.

v2: remove debug code that Imre found

BSpec: 21257
Cc: Ville Syrjälä 
Cc: Imre Deak 
Cc: Rodrigo Vivi 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_reg.h  |   4 +
 drivers/gpu/drm/i915/intel_ddi.c | 223 ++-
 2 files changed, 86 insertions(+), 141 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d3ef979..e632e99 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1866,6 +1866,10 @@ enum i915_power_well_id {
 
 #define CNL_PORT_TX_DW7_GRP(port)  _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
 #define CNL_PORT_TX_DW7_LN0(port)  _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
+#define ICL_PORT_TX_DW7_AUX(port)  _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
+#define ICL_PORT_TX_DW7_GRP(port)  _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
+#define ICL_PORT_TX_DW7_LN0(port)  _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
+#define ICL_PORT_TX_DW7_LN(port, ln)   _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
 #define   N_SCALAR(x)  ((x) << 24)
 #define   N_SCALAR_MASK(0x7F << 24)
 
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 61d7145..219464e9 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -493,103 +493,63 @@ struct cnl_ddi_buf_trans {
{ 0x2, 0x7F, 0x3F, 0x00, 0x00 },/* 400   400  0.0   */
 };
 
-struct icl_combo_phy_ddi_buf_trans {
-   u32 dw2_swing_select;
-   u32 dw2_swing_scalar;
-   u32 dw4_scaling;
-};
-
-/* Voltage Swing Programming for VccIO 0.85V for DP */
-static const struct icl_combo_phy_ddi_buf_trans 
icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
-   /* Voltage mV  db*/
-   { 0x2, 0x98, 0x0018 },  /* 400 0.0   */
-   { 0x2, 0x98, 0x3015 },  /* 400 3.5   */
-   { 0x2, 0x98, 0x6012 },  /* 400 6.0   */
-   { 0x2, 0x98, 0x900F },  /* 400 9.5   */
-   { 0xB, 0x70, 0x0018 },  /* 600 0.0   */
-   { 0xB, 0x70, 0x3015 },  /* 600 3.5   */
-   { 0xB, 0x70, 0x6012 },  /* 600 6.0   */
-   { 0x5, 0x00, 0x0018 },  /* 800 0.0   */
-   { 0x5, 0x00, 0x3015 },  /* 800 3.5   */
-   { 0x6, 0x98, 0x0018 },  /* 12000.0   */
-};
-
-/* FIXME - After table is updated in Bspec */
-/* Voltage Swing Programming for VccIO 0.85V for eDP */
-static const struct icl_combo_phy_ddi_buf_trans 
icl_combo_phy_ddi_translations_edp_0_85V[] = {
-   /* Voltage mV  db*/
-   { 0x0, 0x00, 0x00 },/* 200 0.0   */
-   { 0x0, 0x00, 0x00 },/* 200 1.5   */
-   { 0x0, 0x00, 0x00 },/* 200 4.0   */
-   { 0x0, 0x00, 0x00 },/* 200 6.0   */
-   { 0x0, 0x00, 0x00 },/* 250 0.0   */
-   { 0x0, 0x00, 0x00 },/* 250 1.5   */
-   { 0x0, 0x00, 0x00 },/* 250 4.0   */
-   { 0x0, 0x00, 0x00 },/* 300 0.0   */
-   { 0x0, 0x00, 0x00 },/* 300 1.5   */
-   { 0x0, 0x00, 0x00 },/* 350 0.0   */
+/* icl_combo_phy_ddi_translations */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp[] = {
+   /* NT mV Trans mV db*/
+   { 0xA, 0x35, 0x3F, 0x00, 0x00 },/* 350   350  0.0   */
+   { 0xA, 0x4F, 0x37, 0x00, 0x08 },/* 350   500  3.1   */
+   { 0xC, 0x71, 0x2F, 0x00, 0x10 },/* 350   700  6.0   */
+   { 0x6, 0x7F, 0x2B, 0x00, 0x14 },/* 350   900  8.2   */
+   { 0xA, 0x4C, 0x3F, 0x00, 0x00 },/* 500   500  0.0   */
+   { 0xC, 0x73, 0x34, 0x00, 0x0B },/* 500   700  2.9   */
+   { 0x6, 0x7F, 0x2F, 0x00, 0x10 },/* 500   900  5.1   */
+   { 0xC, 0x6C, 0x3C, 0x00, 0x03 },/* 650   705  0.6   */
+   { 0x6, 0x7F, 0x35, 0x00, 0x0A },/* 600   900  3.5   */
+   { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900   900  0.0   */
 };
 
-/* Voltage Swing Programming for VccIO 0.95V for DP */
-static const struct icl_combo_phy_ddi_buf_trans 
icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
-   /* Voltage mV  db*/
-   { 0x2, 0x98, 0x0018 },  /* 400 0.0   */
-   { 0x2, 0x98, 0x3015 },  /* 400 3.5   */
-   { 0x2, 0x98, 0x6012 },  /* 400 6.0   */
-   { 0x2, 0x98, 0x900F },  /* 400 9.5   */
-   { 0x4, 0x98, 0x0018 },  /* 600 0.0   */
-   { 0x4, 0x98, 0x3015 },  /* 600 3.5   */
-   { 0x4, 0x98, 0x6012 },  /* 600 6.0   */
-   { 0x5, 0x76, 0x0018 },  /* 800 0.0   */
-   { 0x5, 0x76, 0x3015 },  /* 800 3.5   */
-   { 0x6, 

[Intel-gfx] [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC

[clinton . a . taylor]

From: Clint Taylor 

In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence.

BSpec: 21257
Cc: Ville Syrjälä 
Cc: Imre Deak 
Cc: Rodrigo Vivi 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_reg.h  |   4 +
 drivers/gpu/drm/i915/intel_ddi.c | 223 +--
 drivers/gpu/drm/i915/intel_display.c |   3 -
 3 files changed, 86 insertions(+), 144 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d3ef979..e632e99 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1866,6 +1866,10 @@ enum i915_power_well_id {
 
 #define CNL_PORT_TX_DW7_GRP(port)  _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
 #define CNL_PORT_TX_DW7_LN0(port)  _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
+#define ICL_PORT_TX_DW7_AUX(port)  _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
+#define ICL_PORT_TX_DW7_GRP(port)  _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
+#define ICL_PORT_TX_DW7_LN0(port)  _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
+#define ICL_PORT_TX_DW7_LN(port, ln)   _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
 #define   N_SCALAR(x)  ((x) << 24)
 #define   N_SCALAR_MASK(0x7F << 24)
 
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 61d7145..219464e9 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -493,103 +493,63 @@ struct cnl_ddi_buf_trans {
{ 0x2, 0x7F, 0x3F, 0x00, 0x00 },/* 400   400  0.0   */
 };
 
-struct icl_combo_phy_ddi_buf_trans {
-   u32 dw2_swing_select;
-   u32 dw2_swing_scalar;
-   u32 dw4_scaling;
-};
-
-/* Voltage Swing Programming for VccIO 0.85V for DP */
-static const struct icl_combo_phy_ddi_buf_trans 
icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
-   /* Voltage mV  db*/
-   { 0x2, 0x98, 0x0018 },  /* 400 0.0   */
-   { 0x2, 0x98, 0x3015 },  /* 400 3.5   */
-   { 0x2, 0x98, 0x6012 },  /* 400 6.0   */
-   { 0x2, 0x98, 0x900F },  /* 400 9.5   */
-   { 0xB, 0x70, 0x0018 },  /* 600 0.0   */
-   { 0xB, 0x70, 0x3015 },  /* 600 3.5   */
-   { 0xB, 0x70, 0x6012 },  /* 600 6.0   */
-   { 0x5, 0x00, 0x0018 },  /* 800 0.0   */
-   { 0x5, 0x00, 0x3015 },  /* 800 3.5   */
-   { 0x6, 0x98, 0x0018 },  /* 12000.0   */
-};
-
-/* FIXME - After table is updated in Bspec */
-/* Voltage Swing Programming for VccIO 0.85V for eDP */
-static const struct icl_combo_phy_ddi_buf_trans 
icl_combo_phy_ddi_translations_edp_0_85V[] = {
-   /* Voltage mV  db*/
-   { 0x0, 0x00, 0x00 },/* 200 0.0   */
-   { 0x0, 0x00, 0x00 },/* 200 1.5   */
-   { 0x0, 0x00, 0x00 },/* 200 4.0   */
-   { 0x0, 0x00, 0x00 },/* 200 6.0   */
-   { 0x0, 0x00, 0x00 },/* 250 0.0   */
-   { 0x0, 0x00, 0x00 },/* 250 1.5   */
-   { 0x0, 0x00, 0x00 },/* 250 4.0   */
-   { 0x0, 0x00, 0x00 },/* 300 0.0   */
-   { 0x0, 0x00, 0x00 },/* 300 1.5   */
-   { 0x0, 0x00, 0x00 },/* 350 0.0   */
+/* icl_combo_phy_ddi_translations */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp[] = {
+   /* NT mV Trans mV db*/
+   { 0xA, 0x35, 0x3F, 0x00, 0x00 },/* 350   350  0.0   */
+   { 0xA, 0x4F, 0x37, 0x00, 0x08 },/* 350   500  3.1   */
+   { 0xC, 0x71, 0x2F, 0x00, 0x10 },/* 350   700  6.0   */
+   { 0x6, 0x7F, 0x2B, 0x00, 0x14 },/* 350   900  8.2   */
+   { 0xA, 0x4C, 0x3F, 0x00, 0x00 },/* 500   500  0.0   */
+   { 0xC, 0x73, 0x34, 0x00, 0x0B },/* 500   700  2.9   */
+   { 0x6, 0x7F, 0x2F, 0x00, 0x10 },/* 500   900  5.1   */
+   { 0xC, 0x6C, 0x3C, 0x00, 0x03 },/* 650   705  0.6   */
+   { 0x6, 0x7F, 0x35, 0x00, 0x0A },/* 600   900  3.5   */
+   { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900   900  0.0   */
 };
 
-/* Voltage Swing Programming for VccIO 0.95V for DP */
-static const struct icl_combo_phy_ddi_buf_trans 
icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
-   /* Voltage mV  db*/
-   { 0x2, 0x98, 0x0018 },  /* 400 0.0   */
-   { 0x2, 0x98, 0x3015 },  /* 400 3.5   */
-   { 0x2, 0x98, 0x6012 },  /* 400 6.0   */
-   { 0x2, 0x98, 0x900F },  /* 400 9.5   */
-   { 0x4, 0x98, 0x0018 },  /* 600 0.0   */
-   { 0x4, 0x98, 0x3015 },  /* 600 3.5   */
-   { 0x4, 0x98, 0x6012 },  /* 600 6.0   */
-   { 0x5, 0x76, 0x0018 },  /* 800 0.0   */
-   { 0x5, 0x76, 0x3015 },  /* 800 3.5   */
-

[Intel-gfx] [PATCH] drm/i915/glk: Use cached RCOMP value when re-enabling DPIO Phy

[clinton . a . taylor]

From: Clint Taylor 

The calibration RCOMP value in PORT_TX_DW6 in stored in dev_priv during
driver init. Use this value instead of reading the register again as the
power well for PORTA RCOMP register may not be enabled and will return
0x instead of the computed value.

Cc: Ville Syrjälä 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_dpio_phy.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c 
b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 3c7f10d..7cee57f 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -422,8 +422,12 @@ static void _bxt_ddi_phy_init(struct drm_i915_private 
*dev_priv,
 * the corresponding calibrated value from PHY1, and disable
 * the automatic calibration on PHY0.
 */
-   val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
- phy_info->rcomp_phy);
+   if (!dev_priv->bxt_phy_grc)
+   val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
+ 
phy_info->rcomp_phy);
+   else
+   val = dev_priv->bxt_phy_grc;
+
grc_code = val << GRC_CODE_FAST_SHIFT |
   val << GRC_CODE_SLOW_SHIFT |
   val;
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3] drm/i915/hdmi: Reorder structure to match specification

[clinton . a . taylor]

From: Clint Taylor 

reorder structure of 297, 594 N values to group Audio Sample Frequencies
together to make updating from HDMI specification easier.

V2: Match patch 1/2 version
V3: Arrange by sample freq, then pixel clock.

Cc: Jani Nikula 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_audio.c | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index ccd88da..ae55a68 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -153,32 +153,32 @@ struct dp_aud_n_m {
int n;
int cts;
 } hdmi_aud_ncts[] = {
-   { 44100, TMDS_296M, 4459, 234375 },
-   { 44100, TMDS_297M, 4704, 247500 },
-   { 48000, TMDS_296M, 5824, 281250 },
-   { 48000, TMDS_297M, 5120, 247500 },
{ 32000, TMDS_296M, 5824, 421875 },
{ 32000, TMDS_297M, 3072, 222750 },
+   { 32000, TMDS_593M, 5824, 843750 },
+   { 32000, TMDS_594M, 3072, 445500 },
+   { 44100, TMDS_296M, 4459, 234375 },
+   { 44100, TMDS_297M, 4704, 247500 },
+   { 44100, TMDS_593M, 8918, 937500 },
+   { 44100, TMDS_594M, 9408, 99 },
{ 88200, TMDS_296M, 8918, 234375 },
{ 88200, TMDS_297M, 9408, 247500 },
-   { 96000, TMDS_296M, 11648, 281250 },
-   { 96000, TMDS_297M, 10240, 247500 },
+   { 88200, TMDS_593M, 17836, 937500 },
+   { 88200, TMDS_594M, 18816, 99 },
{ 176400, TMDS_296M, 17836, 234375 },
{ 176400, TMDS_297M, 18816, 247500 },
-   { 192000, TMDS_296M, 23296, 281250 },
-   { 192000, TMDS_297M, 20480, 247500 },
-   { 44100, TMDS_593M, 8918, 937500 },
-   { 44100, TMDS_594M, 9408, 99 },
+   { 176400, TMDS_593M, 35672, 937500 },
+   { 176400, TMDS_594M, 37632, 99 },
+   { 48000, TMDS_296M, 5824, 281250 },
+   { 48000, TMDS_297M, 5120, 247500 },
{ 48000, TMDS_593M, 5824, 562500 },
{ 48000, TMDS_594M, 6144, 594000 },
-   { 32000, TMDS_593M, 5824, 843750 },
-   { 32000, TMDS_594M, 3072, 445500 },
-   { 88200, TMDS_593M, 17836, 937500 },
-   { 88200, TMDS_594M, 18816, 99 },
+   { 96000, TMDS_296M, 11648, 281250 },
+   { 96000, TMDS_297M, 10240, 247500 },
{ 96000, TMDS_593M, 11648, 562500 },
{ 96000, TMDS_594M, 12288, 594000 },
-   { 176400, TMDS_593M, 35672, 937500 },
-   { 176400, TMDS_594M, 37632, 99 },
+   { 192000, TMDS_296M, 23296, 281250 },
+   { 192000, TMDS_297M, 20480, 247500 },
{ 192000, TMDS_593M, 23296, 562500 },
{ 192000, TMDS_594M, 24576, 594000 },
 };
-- 
1.9.1

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[Intel-gfx] [PATCH v2 2/2] drm/i915/hdmi: Reorder structure to match specification

[clinton . a . taylor]

From: Clint Taylor 

reorder structure of 297, 594 N values to group Audio Sample Frequencies
together to make updating from HDMI specification easier.

V2: Match patch 1/2 version

Cc: Jani Nikula 
Cc: sta...@vger.kernel.org

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_audio.c | 24 
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index ee3ca2d..47caecb 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -153,32 +153,32 @@ struct dp_aud_n_m {
int n;
int cts;
 } hdmi_aud_ncts[] = {
-   { 44100, TMDS_296M, 4459, 234375 },
-   { 44100, TMDS_297M, 4704, 247500 },
-   { 48000, TMDS_296M, 5824, 281250 },
-   { 48000, TMDS_297M, 5120, 247500 },
{ 32000, TMDS_296M, 5824, 421875 },
{ 32000, TMDS_297M, 3072, 222750 },
+   { 44100, TMDS_296M, 4459, 234375 },
+   { 44100, TMDS_297M, 4704, 247500 },
{ 88200, TMDS_296M, 8918, 234375 },
{ 88200, TMDS_297M, 9408, 247500 },
-   { 96000, TMDS_296M, 11648, 281250 },
-   { 96000, TMDS_297M, 10240, 247500 },
{ 176400, TMDS_296M, 17836, 234375 },
{ 176400, TMDS_297M, 18816, 247500 },
+   { 48000, TMDS_296M, 5824, 281250 },
+   { 48000, TMDS_297M, 5120, 247500 },
+   { 96000, TMDS_296M, 11648, 281250 },
+   { 96000, TMDS_297M, 10240, 247500 },
{ 192000, TMDS_296M, 23296, 281250 },
{ 192000, TMDS_297M, 20480, 247500 },
-   { 44100, TMDS_593M, 8918, 937500 },
-   { 44100, TMDS_594M, 9408, 99 },
-   { 48000, TMDS_593M, 5824, 562500 },
-   { 48000, TMDS_594M, 6144, 594000 },
{ 32000, TMDS_593M, 5824, 843750 },
{ 32000, TMDS_594M, 3072, 445500 },
+   { 44100, TMDS_593M, 8918, 937500 },
+   { 44100, TMDS_594M, 9408, 99 },
{ 88200, TMDS_593M, 17836, 937500 },
{ 88200, TMDS_594M, 18816, 99 },
-   { 96000, TMDS_593M, 11648, 562500 },
-   { 96000, TMDS_594M, 12288, 594000 },
{ 176400, TMDS_593M, 35672, 937500 },
{ 176400, TMDS_594M, 37632, 99 },
+   { 48000, TMDS_593M, 5824, 562500 },
+   { 48000, TMDS_594M, 6144, 594000 },
+   { 96000, TMDS_593M, 11648, 562500 },
+   { 96000, TMDS_594M, 12288, 594000 },
{ 192000, TMDS_593M, 23296, 562500 },
{ 192000, TMDS_594M, 24576, 594000 },
 };
-- 
1.9.1

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[Intel-gfx] [PATCH 0/2] HDMI 2.0 clock recovery values

[clinton . a . taylor]

From: Clint Taylor 

Added HDMI 2.0 N and CTS values for 594 Pixel clock modes. Reorganized
structure to group by Audio Sample Frequency

Clint Taylor (2):
  drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values
  drm/i915/hdmi: Reorder structure to match specification

 drivers/gpu/drm/i915/intel_audio.c | 29 +++--
 1 file changed, 23 insertions(+), 6 deletions(-)

-- 
1.9.1

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[Intel-gfx] [PATCH v2 1/2] drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values

[clinton . a . taylor]

From: Clint Taylor 

HDMI 2.0 594Mhz modes were incorrectly selecting 25.200Mhz Automatic N value
mode instead of HDMI specification values.

V2: Fix 88.2 Hz N value

Cc: Jani Nikula 
Cc: sta...@vger.kernel.org
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_audio.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index 769f3f5..ee3ca2d 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -144,6 +144,9 @@ struct dp_aud_n_m {
 /* HDMI N/CTS table */
 #define TMDS_297M 297000
 #define TMDS_296M 296703
+#define TMDS_594M 594000
+#define TMDS_593M 593407
+
 static const struct {
int sample_rate;
int clock;
@@ -164,6 +167,20 @@ struct dp_aud_n_m {
{ 176400, TMDS_297M, 18816, 247500 },
{ 192000, TMDS_296M, 23296, 281250 },
{ 192000, TMDS_297M, 20480, 247500 },
+   { 44100, TMDS_593M, 8918, 937500 },
+   { 44100, TMDS_594M, 9408, 99 },
+   { 48000, TMDS_593M, 5824, 562500 },
+   { 48000, TMDS_594M, 6144, 594000 },
+   { 32000, TMDS_593M, 5824, 843750 },
+   { 32000, TMDS_594M, 3072, 445500 },
+   { 88200, TMDS_593M, 17836, 937500 },
+   { 88200, TMDS_594M, 18816, 99 },
+   { 96000, TMDS_593M, 11648, 562500 },
+   { 96000, TMDS_594M, 12288, 594000 },
+   { 176400, TMDS_593M, 35672, 937500 },
+   { 176400, TMDS_594M, 37632, 99 },
+   { 192000, TMDS_593M, 23296, 562500 },
+   { 192000, TMDS_594M, 24576, 594000 },
 };
 
 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
-- 
1.9.1

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[Intel-gfx] [PATCH v2] drm/i915/hdmi: Detect HDMI 2.0 monitors using multiple EDID capabilities

[clinton . a . taylor]

From: Clint Taylor 

HDMI 2.0 monitors may not support SCDC and still be able to accept VICs
above 63. Use multiple EDID capbilities to determine if the SINK is
actually an HDMI 2.0 device. The QD980B HDMI 2.0 Analyzer generates unique
EDIDs during CTS tests that don't contain a HDMI Forum VSDB if the block is
not used during the test. The current HDMI AVI infoframe code only uses the
SCDC supported information in the HDMI Forum VSDB to determine if the sink
is HDMI 2.0. This patch adds a check for YCbCr420 present in the EDID
supported formats as well as the existing SCDC supported check.

HDMI 2.0 CTS HF1-51 test fails on the QD980B.

V2: Make check for display_info->color formats == YCbCR420 and SCDC

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107894
Cc: Ville Syrjälä 
Cc: Shashank Sharma 

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_hdmi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 89d5e39..eca0a3e 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -466,7 +466,8 @@ static void intel_hdmi_set_avi_infoframe(struct 
intel_encoder *encoder,
const struct drm_display_mode *adjusted_mode =
_state->base.adjusted_mode;
struct drm_connector *connector = _hdmi->attached_connector->base;
-   bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported;
+   bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported ||
+  connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
union hdmi_infoframe frame;
int ret;
 
-- 
1.9.1

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[Intel-gfx] [PATCH] drm/i915/hdmi: Detect HDMI 2.0 monitors using multiple EDID capabilities

[clinton . a . taylor]

From: Clint Taylor 

HDMI 2.0 monitors may not support SCDC and still be able to accept VICs
above 63. Use multiple EDID capbilities to determine if the SINK is
actually an HDMI 2.0 device. The QD980B HDMI 2.0 Analyzer generates unique
EDIDs during CTS tests that don't contain a HDMI Forum VSDB if the block is
not used during the test. The current HDMI AVI infoframe code only uses the
SCDC supported information in the HDMI Forum VSDB to determine if the sink
is HDMI 2.0. This patch adds checks for YCbCr420 Deep Color, YCbCR420 VDB,
YCBCR420 CMDB capabilities, and pipe is YCbCr420 to the existing SCDC
supported check to Infer SINK is HDMI 2.0.

HDMI 2.0 CTS HF1-51 test fails on the QD980B.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107894
Cc: Ville Syrjälä 
Cc: Shashank Sharma 

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_hdmi.c | 32 +++-
 1 file changed, 31 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 2c53efc..6913806 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -458,6 +458,34 @@ static void intel_write_infoframe(struct intel_encoder 
*encoder,
frame->any.type, buffer, len);
 }
 
+static bool is_hdmi2(const struct drm_connector *connector,
+   const struct intel_crtc_state *crtc_state)
+{
+   bool hdmi2 = false;
+   bool vdb_mode = false;
+   bool cmdb_mode = false;
+   int i = 0;
+
+   /* check VDB bits for HDMI 2.0 mode */
+   for (i = 0; i < BITS_TO_LONGS(128); i++)
+   if (connector->display_info.hdmi.y420_vdb_modes[i])
+   vdb_mode = true;
+
+   /* check CMDB bits for HDMI 2.0 mode */
+   for (i = 0; i < BITS_TO_LONGS(128); i++)
+   if (connector->display_info.hdmi.y420_cmdb_modes[i])
+   cmdb_mode = true;
+
+   if (connector->display_info.hdmi.scdc.supported ||
+   connector->display_info.hdmi.y420_dc_modes ||
+   crtc_state->ycbcr420 || vdb_mode || cmdb_mode) {
+   DRM_DEBUG_KMS("Inferred HDMI2 sink present\n");
+   hdmi2 = true;
+   }
+
+   return hdmi2;
+}
+
 static void intel_hdmi_set_avi_infoframe(struct intel_encoder *encoder,
 const struct intel_crtc_state 
*crtc_state,
 const struct drm_connector_state 
*conn_state)
@@ -466,10 +494,12 @@ static void intel_hdmi_set_avi_infoframe(struct 
intel_encoder *encoder,
const struct drm_display_mode *adjusted_mode =
_state->base.adjusted_mode;
struct drm_connector *connector = _hdmi->attached_connector->base;
-   bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported;
+   bool is_hdmi2_sink = false;
union hdmi_infoframe frame;
int ret;
 
+   is_hdmi2_sink = is_hdmi2(connector, crtc_state);
+
ret = drm_hdmi_avi_infoframe_from_display_mode(,
   adjusted_mode,
   is_hdmi2_sink);
-- 
1.9.1

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[Intel-gfx] [PATCH] drm/i915/hdmi: Initialize SCDC registers according to spec

[clinton . a . taylor]

From: Clint Taylor 

Initialize SCDC Source Version and TDMS_Config_0 registers to nominal
values during intel_hdmi_detect(). The i915 driver currently doesn't
implement features that require polling of the status update bits. Once
FRL, DSC, or Source Test is enabled in the driver the status flags will
need to be read by the source according to specification.

Cc: Ville Syrjälä 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_hdmi.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 2c53efc..ab3eac5 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1910,6 +1910,8 @@ bool intel_hdmi_compute_config(struct intel_encoder 
*encoder,
struct drm_i915_private *dev_priv = to_i915(connector->dev);
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
struct intel_encoder *encoder = _to_dig_port(intel_hdmi)->base;
+   struct i2c_adapter *adapter =
+   intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
 
DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  connector->base.id, connector->name);
@@ -1925,6 +1927,16 @@ bool intel_hdmi_compute_config(struct intel_encoder 
*encoder,
if (intel_hdmi_set_edid(connector))
status = connector_status_connected;
 
+   if (connector->display_info.hdmi.scdc.supported) {
+   /* SCDC source version HDMI 2.1 Sec. 10.4.1.2 */
+   if (drm_scdc_writeb(adapter, SCDC_SOURCE_VERSION, 0x01) < 0)
+   DRM_DEBUG_KMS("Unable to set SCDC Source Version 
register\n");
+
+   /* Clear SCDC CONFIG_0 HDMI 2.1 Sec. 10.4.1.6 - RR_Enable 
Polling Only */
+   if (drm_scdc_writeb(adapter, SCDC_CONFIG_0, 0x00) < 0)
+   DRM_DEBUG_KMS("Unable to set SCDC CONFIG_0 register\n");
+   }
+
 out:
intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
 
-- 
1.9.1

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[Intel-gfx] [PATCH v2] /drm/i915/hdmi: SCDC Scrambling enable without CTS mode

[clinton . a . taylor]

From: Clint Taylor 

Setting the SCDC scrambling CTS mode causes HDMI Link Layer protocol tests
HF1-12 and HF1-13 to fail.

V2: Removed "Source Shall" entries to a new patch
Cc: Ville Syrjälä 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107895
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107896
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_ddi.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 47960c9..a148684 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1872,7 +1872,7 @@ void intel_ddi_enable_transcoder_func(const struct 
intel_crtc_state *crtc_state)
temp |= TRANS_DDI_MODE_SELECT_DVI;
 
if (crtc_state->hdmi_scrambling)
-   temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
+   temp |= TRANS_DDI_HDMI_SCRAMBLING;
if (crtc_state->hdmi_high_tmds_clock_ratio)
temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
@@ -3394,8 +3394,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
if (intel_dig_port->infoframe_enabled(encoder, pipe_config))
pipe_config->has_infoframe = true;
 
-   if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
-   TRANS_DDI_HDMI_SCRAMBLING_MASK)
+   if (temp & TRANS_DDI_HDMI_SCRAMBLING)
pipe_config->hdmi_scrambling = true;
if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
pipe_config->hdmi_high_tmds_clock_ratio = true;
-- 
1.9.1

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[Intel-gfx] [PATCH] drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values

[clinton . a . taylor]

From: Clint Taylor 

HDMI 2.0 594Mhz modes were incorrectly selecting 25.200Mhz Automatic N
value mode instead of HDMI specification values.

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_audio.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index 769f3f5..4b8f6f6 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -144,6 +144,8 @@ struct dp_aud_n_m {
 /* HDMI N/CTS table */
 #define TMDS_297M 297000
 #define TMDS_296M 296703
+#define TMDS_594M 594000
+#define TMDS_593M 593407
 static const struct {
int sample_rate;
int clock;
@@ -164,6 +166,20 @@ struct dp_aud_n_m {
{ 176400, TMDS_297M, 18816, 247500 },
{ 192000, TMDS_296M, 23296, 281250 },
{ 192000, TMDS_297M, 20480, 247500 },
+   { 44100, TMDS_593M, 8918, 937500 },
+   { 44100, TMDS_594M, 9408, 99 },
+   { 48000, TMDS_593M, 5824, 562500 },
+   { 48000, TMDS_594M, 6144, 594000 },
+   { 32000, TMDS_593M, 5824, 843750 },
+   { 32000, TMDS_594M, 3072, 445500 },
+   { 88200, TMDS_593M, 17836, 937500 },
+   { 88200, TMDS_594M, 9408, 99 },
+   { 96000, TMDS_593M, 11648, 562500 },
+   { 96000, TMDS_594M, 12288, 594000 },
+   { 176400, TMDS_593M, 35672, 937500 },
+   { 176400, TMDS_594M, 37632, 99 },
+   { 192000, TMDS_593M, 23296, 562500 },
+   { 192000, TMDS_594M, 24576, 594000 },
 };
 
 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
-- 
1.9.1

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[Intel-gfx] [PATCH] /drm/i915/hdmi: SCDC Scrambling enable without CTS mode

[clinton . a . taylor]

From: Clint Taylor 

Setting the SCDC scrambling CTS mode causes HDMI Link Layer protocol tests
HF1-12 and HF1-13 to fail. Added "Source Shall" entries from SCDC
section before enabling scrambling.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107895
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107896
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_ddi.c  | 6 +++---
 drivers/gpu/drm/i915/intel_hdmi.c | 8 
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9e82281..a1b877f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1872,7 +1872,7 @@ void intel_ddi_enable_transcoder_func(const struct 
intel_crtc_state *crtc_state)
temp |= TRANS_DDI_MODE_SELECT_DVI;
 
if (crtc_state->hdmi_scrambling)
-   temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
+   temp |= TRANS_DDI_HDMI_SCRAMBLING;
if (crtc_state->hdmi_high_tmds_clock_ratio)
temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
@@ -3394,8 +3394,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
if (intel_dig_port->infoframe_enabled(encoder, pipe_config))
pipe_config->has_infoframe = true;
 
-   if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
-   TRANS_DDI_HDMI_SCRAMBLING_MASK)
+   if ((temp & TRANS_DDI_HDMI_SCRAMBLING) ==
+   TRANS_DDI_HDMI_SCRAMBLING)
pipe_config->hdmi_scrambling = true;
if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
pipe_config->hdmi_high_tmds_clock_ratio = true;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 454f570..d181d67 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2148,6 +2148,14 @@ bool intel_hdmi_handle_sink_scrambling(struct 
intel_encoder *encoder,
  connector->base.id, connector->name,
  yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
 
+   /* SCDC source version 10.4.1.2 */
+   if (drm_scdc_writeb(adapter, SCDC_SOURCE_VERSION, 0x01) < 0)
+   DRM_DEBUG_KMS("Unable to set SCDC Source Version register\n");
+
+   /* Clear SCDC CONFIG_0 10.4.1.6 - RR_Enable Polling Only */
+   if (drm_scdc_writeb(adapter, SCDC_CONFIG_0, 0x00) < 0)
+   DRM_DEBUG_KMS("Unable to set SCDC CONFIG_0 register\n");
+
/* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable 
scrambling */
return drm_scdc_set_high_tmds_clock_ratio(adapter,
  high_tmds_clock_ratio) &&
-- 
1.9.1

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[Intel-gfx] [PATCH v4] drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.

[clinton . a . taylor]

From: Clint Taylor 

On GLK NUC platforms the HDMI retiming buffer needs additional disabled
time to correctly sync to a faster incoming signal.

When measured on a scope the highspeed lines of the HDMI clock turn off
 for ~400uS during a normal resolution change. The HDMI retimer on the
 GLK NUC appears to require at least a full frame of quiet time before a
new faster clock can be correctly sync'd. Wait 100ms due to msleep
inaccuracies while waiting for a completed frame. Add a quirk to the
driver for GLK boards that use ITE66317 HDMI retimers.

V2: Add more devices to the quirk list
V3: Delay increased to 100ms, check to confirm crtc type is HDMI.
V4: crtc type check extended to include _DDI and whitespace fixes

Cc: Imre Deak 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105887
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_ddi.c | 18 +++---
 drivers/gpu/drm/i915/intel_display.c | 20 +++-
 drivers/gpu/drm/i915/intel_drv.h |  3 +--
 4 files changed, 36 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2cefe4c..c1526ea 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -650,6 +650,7 @@ enum intel_sbi_destination {
 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
 #define QUIRK_INCREASE_T12_DELAY (1<<6)
+#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
 
 struct intel_fbdev;
 struct intel_fbc_work;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0319825..6d33010 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1807,15 +1807,27 @@ void intel_ddi_enable_transcoder_func(const struct 
intel_crtc_state *crtc_state)
I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
 }
 
-void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
-  enum transcoder cpu_transcoder)
+/* Quirk time at 100ms for reliable operation */
+#define DDI_DISABLED_QUIRK_TIME 100
+
+void intel_ddi_disable_transcoder_func(const struct intel_crtc_state 
*crtc_state)
 {
+   struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+   enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
uint32_t val = I915_READ(reg);
-
val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | 
TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
val |= TRANS_DDI_PORT_NONE;
I915_WRITE(reg, val);
+
+   if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
+   (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
+intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DDI))) {
+   DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
+   msleep(DDI_DISABLED_QUIRK_TIME);
+   }
 }
 
 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 681e071..8d31ff3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5837,7 +5837,7 @@ static void haswell_crtc_disable(struct intel_crtc_state 
*old_crtc_state,
intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
 
if (!transcoder_is_dsi(cpu_transcoder))
-   intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
+   intel_ddi_disable_transcoder_func(old_crtc_state);
 
if (INTEL_GEN(dev_priv) >= 9)
skylake_scaler_disable(intel_crtc);
@@ -14847,6 +14847,17 @@ static void quirk_increase_t12_delay(struct drm_device 
*dev)
DRM_INFO("Applying T12 delay quirk\n");
 }
 
+/* GeminiLake NUC HDMI outputs require additional off time
+ * this allows the onboard retimer to correctly sync to signal
+ */
+static void quirk_increase_ddi_disabled_time(struct drm_device *dev)
+{
+   struct drm_i915_private *dev_priv = to_i915(dev);
+
+   dev_priv->quirks |= QUIRK_INCREASE_DDI_DISABLED_TIME;
+   DRM_INFO("Applying Increase DDI Disabled quirk\n");
+}
+
 struct intel_quirk {
int device;
int subsystem_vendor;
@@ -14933,6 +14944,13 @@ static int intel_dmi_reverse_brightness(const struct 
dmi_system_id *id)
 
/* Toshiba Satellite P50-C-18C */
{ 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
+
+   /* GeminiLake NUC */
+   { 0x3185, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
+   { 0x3184, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
+   /* ASRock ITX*/
+   { 0x3185, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
+   { 0x3184, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
 };
 
 static void intel_init_quirks(struct drm_device *dev)
diff 

[Intel-gfx] [PATCH v3] drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.

[clinton . a . taylor]

From: Clint Taylor 

On GLK NUC platforms the HDMI retiming buffer needs additional disabled
time to correctly sync to a faster incoming signal.

When measured on a scope the highspeed lines of the HDMI clock turn off
 for ~400uS during a normal resolution change. The HDMI retimer on the
 GLK NUC appears to require at least a full frame of quiet time before a
new faster clock can be correctly sync'd. Wait 100ms due to msleep
inaccuracies while waiting for a completed frame. Add a quirk to the
driver for GLK boards that use ITE66317 HDMI retimers.

V2: Add more devices to the quirk list
V3: Delay increased to 100ms, check to confirm crtc type is HDMI.

Cc: Imre Deak 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105887
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_ddi.c | 16 ++--
 drivers/gpu/drm/i915/intel_display.c | 21 -
 drivers/gpu/drm/i915/intel_drv.h |  3 +--
 4 files changed, 36 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2b684f4..6c5a679 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -655,6 +655,7 @@ enum intel_sbi_destination {
 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
 #define QUIRK_INCREASE_T12_DELAY (1<<6)
+#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
 
 struct intel_fbdev;
 struct intel_fbc_work;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0319825..89bb5ce 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1807,15 +1807,27 @@ void intel_ddi_enable_transcoder_func(const struct 
intel_crtc_state *crtc_state)
I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
 }
 
-void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
-  enum transcoder cpu_transcoder)
+/* Quirk time at 100ms for reliable operation */
+#define DDI_DISABLED_QUIRK_TIME 100
+
+void intel_ddi_disable_transcoder_func(const struct intel_crtc_state 
*crtc_state)
 {
+   struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+   enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
uint32_t val = I915_READ(reg);
 
val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | 
TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
val |= TRANS_DDI_PORT_NONE;
I915_WRITE(reg, val);
+
+   if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
+   intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+   msleep(DDI_DISABLED_QUIRK_TIME);
+   DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
+   }
 }
 
 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index eaa0663..ff42268 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5837,7 +5837,7 @@ static void haswell_crtc_disable(struct intel_crtc_state 
*old_crtc_state,
intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
 
if (!transcoder_is_dsi(cpu_transcoder))
-   intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
+   intel_ddi_disable_transcoder_func(old_crtc_state);
 
if (INTEL_GEN(dev_priv) >= 9)
skylake_scaler_disable(intel_crtc);
@@ -14852,6 +14852,17 @@ static void quirk_increase_t12_delay(struct drm_device 
*dev)
DRM_INFO("Applying T12 delay quirk\n");
 }
 
+/* GeminiLake NUC HDMI outputs require additional off time
+ * this allows the onboard retimer to correctly sync to signal
+ */
+static void quirk_increase_ddi_disabled_time(struct drm_device *dev)
+{
+   struct drm_i915_private *dev_priv = to_i915(dev);
+
+   dev_priv->quirks |= QUIRK_INCREASE_DDI_DISABLED_TIME;
+   DRM_INFO("Applying Increase DDI Disabled quirk\n");
+}
+
 struct intel_quirk {
int device;
int subsystem_vendor;
@@ -14938,6 +14949,14 @@ static int intel_dmi_reverse_brightness(const struct 
dmi_system_id *id)
 
/* Toshiba Satellite P50-C-18C */
{ 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
+
+   /* GeminiLake NUC */
+   { 0x3185, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
+   { 0x3184, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
+   /* ASRock ITX*/
+   { 0x3185, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
+   { 0x3184, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
+
 };
 
 static void intel_init_quirks(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a6ff260..9c3a3d6 100644
--- 

[Intel-gfx] [PATCH V2] drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.

[clinton . a . taylor]

From: Clint Taylor 

On GLK NUC platforms the HDMI retiming buffer needs additional disabled
time to correctly sync to a faster incoming signal.

When measured on a scope the highspeed lines of the HDMI clock turn off
 for ~400uS during a normal resolution change. The HDMI retimer on the
 GLK NUC appears to require at least a full frame of quiet time before a
new faster clock can be correctly sync'd. The worst case scenario appears
to be 23.98Hz modes which requires a wait of 41.25ms. Add a quirk to the
driver for GLK NUC that waits 42ms.

V2: Add more devices to the quirk list

Cc: Imre Deak 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105887
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_ddi.c |  8 
 drivers/gpu/drm/i915/intel_display.c | 19 +++
 3 files changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index be8c2f0..da196b4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -656,6 +656,7 @@ enum intel_sbi_destination {
 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
 #define QUIRK_INCREASE_T12_DELAY (1<<6)
+#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
 
 struct intel_fbdev;
 struct intel_fbc_work;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ca73387..bc3d012 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1791,6 +1791,9 @@ void intel_ddi_enable_transcoder_func(const struct 
intel_crtc_state *crtc_state)
I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
 }
 
+/* Quirk time computed based on 24fps frame time of 41.25ms */
+#define DDI_DISABLED_QUIRK_TIME 42
+
 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
   enum transcoder cpu_transcoder)
 {
@@ -1800,6 +1803,11 @@ void intel_ddi_disable_transcoder_func(struct 
drm_i915_private *dev_priv,
val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | 
TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
val |= TRANS_DDI_PORT_NONE;
I915_WRITE(reg, val);
+
+   if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME) {
+   msleep(DDI_DISABLED_QUIRK_TIME);
+   DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
+   }
 }
 
 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 8251e18..40e0306 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14749,6 +14749,17 @@ static void quirk_increase_t12_delay(struct drm_device 
*dev)
DRM_INFO("Applying T12 delay quirk\n");
 }
 
+/* GeminiLake NUC HDMI outputs require additional off time
+ * this allows the onboard retimer to correctly sync to signal
+ */
+static void quirk_increase_ddi_disabled_time(struct drm_device *dev)
+{
+   struct drm_i915_private *dev_priv = to_i915(dev);
+
+   dev_priv->quirks |= QUIRK_INCREASE_DDI_DISABLED_TIME;
+   DRM_INFO("Applying Increase DDI Disabled quirk\n");
+}
+
 struct intel_quirk {
int device;
int subsystem_vendor;
@@ -14835,6 +14846,14 @@ static int intel_dmi_reverse_brightness(const struct 
dmi_system_id *id)
 
/* Toshiba Satellite P50-C-18C */
{ 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
+
+   /* GeminiLake NUC */
+   { 0x3185, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
+   { 0x3184, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
+   /* ASRock ITX*/
+   { 0x3185, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
+   { 0x3184, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
+
 };
 
 static void intel_init_quirks(struct drm_device *dev)
-- 
1.9.1

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[Intel-gfx] [PATCH] drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.

[clinton . a . taylor]

From: Clint Taylor 

On GLK NUC platforms the HDMI retiming buffer needs additional disabled
time to correctly sync to a faster incoming signal.

When measured on a scope the highspeed lines of the HDMI clock turn off
 for ~400uS during a normal resolution change. The HDMI retimer on the
 GLK NUC appears to require at least a full frame of quiet time before a
new faster clock can be correctly sync'd. The worst case scenario appears
to be 23.98Hz modes which requires a wait of 41.25ms. Add a quirk to the
driver for GLK NUC that waits 42ms.

Cc: Imre Deak 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105887
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_ddi.c |  8 
 drivers/gpu/drm/i915/intel_display.c | 14 ++
 3 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c407366..628491d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -645,6 +645,7 @@ enum intel_sbi_destination {
 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
 #define QUIRK_INCREASE_T12_DELAY (1<<6)
+#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
 
 struct intel_fbdev;
 struct intel_fbc_work;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index b344e0f..61b41c3 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1784,6 +1784,9 @@ void intel_ddi_enable_transcoder_func(const struct 
intel_crtc_state *crtc_state)
I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
 }
 
+/* Quirk time computed based on 24fps frame time of 41.25ms */
+#define DDI_DISABLED_QUIRK_TIME 42
+
 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
   enum transcoder cpu_transcoder)
 {
@@ -1793,6 +1796,11 @@ void intel_ddi_disable_transcoder_func(struct 
drm_i915_private *dev_priv,
val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | 
TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
val |= TRANS_DDI_PORT_NONE;
I915_WRITE(reg, val);
+
+   if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME) {
+   msleep(DDI_DISABLED_QUIRK_TIME);
+   DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
+   }
 }
 
 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index ed29219..0d07c37 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14740,6 +14740,17 @@ static void quirk_increase_t12_delay(struct drm_device 
*dev)
DRM_INFO("Applying T12 delay quirk\n");
 }
 
+/* GeminiLake NUC HDMI outputs require additional off time
+ * this allows the onboard retimer to correctly sync to signal
+ */
+static void quirk_increase_ddi_disabled_time(struct drm_device *dev)
+{
+   struct drm_i915_private *dev_priv = to_i915(dev);
+
+   dev_priv->quirks |= QUIRK_INCREASE_DDI_DISABLED_TIME;
+   DRM_INFO("Applying Increase DDI Disabled quirk\n");
+}
+
 struct intel_quirk {
int device;
int subsystem_vendor;
@@ -14826,6 +14837,9 @@ static int intel_dmi_reverse_brightness(const struct 
dmi_system_id *id)
 
/* Toshiba Satellite P50-C-18C */
{ 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
+
+   /* GeminiLake NUC */
+   { 0x3185, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
 };
 
 static void intel_init_quirks(struct drm_device *dev)
-- 
1.9.1

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[Intel-gfx] [PATCH V3] drn/i915/edp: Only use alternate fixed mode when requested

[clinton . a . taylor]

From: Clint Taylor 

In commit dc911f5bd8aa ("drm/i915/edp: Allow alternate fixed mode for eDP
if available."), the patch was always selecting the alternate refresh rate
even though user space was asking for the higher rate. This patch confirms
the alt mode setup time meets requirements and only uses the alt mode if
psr is enable for the platform.

V2: use clock instead of vrefresh for compare.
V3: Confirm PSR is enabled and alt mode setup time is valid

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105469

Cc: Jani Nikula 
Cc: Rodrigo Vivi 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_dp.c  |  4 +++-
 drivers/gpu/drm/i915/intel_drv.h |  2 ++
 drivers/gpu/drm/i915/intel_psr.c | 35 +++
 3 files changed, 28 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 83da50b..59b8a5c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1864,7 +1864,9 @@ static bool intel_edp_compare_alt_mode(struct 
drm_display_mode *m1,
intel_connector->panel.alt_fixed_mode;
struct drm_display_mode *req_mode = _config->base.mode;
 
-   if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
+   if ((!intel_edp_compare_alt_mode(req_mode, panel_mode) &&
+   intel_psr_setup_time_valid(intel_dp, req_mode)) ||
+   (!i915_modparams.enable_psr))
panel_mode = intel_connector->panel.fixed_mode;
 
drm_mode_debug_printmodeline(panel_mode);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 11a1932..e69ce10 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1908,6 +1908,8 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
 void intel_psr_init(struct drm_i915_private *dev_priv);
 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
   unsigned frontbuffer_bits);
+bool intel_psr_setup_time_valid(struct intel_dp *intel_dp,
+   const struct drm_display_mode *mode);
 void intel_psr_compute_config(struct intel_dp *intel_dp,
  struct intel_crtc_state *crtc_state);
 void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 6233a32..9cc4109 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -578,6 +578,27 @@ static bool intel_psr2_config_valid(struct intel_dp 
*intel_dp,
return true;
 }
 
+bool intel_psr_setup_time_valid(struct intel_dp *intel_dp, const struct 
drm_display_mode *mode)
+{
+   int psr_setup_time = 0;
+
+   psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
+   if (psr_setup_time < 0) {
+   DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time 
(0x%02x)\n",
+ intel_dp->psr_dpcd[1]);
+   return false;
+   }
+
+   if (intel_usecs_to_scanlines(mode, psr_setup_time) >
+   mode->crtc_vtotal - mode->crtc_vdisplay - 1) {
+   DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too 
long\n",
+ psr_setup_time);
+   return false;
+   }
+
+   return true;
+}
+
 void intel_psr_compute_config(struct intel_dp *intel_dp,
  struct intel_crtc_state *crtc_state)
 {
@@ -585,7 +606,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
_state->base.adjusted_mode;
-   int psr_setup_time;
 
if (!CAN_PSR(dev_priv))
return;
@@ -626,17 +646,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
return;
}
 
-   psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
-   if (psr_setup_time < 0) {
-   DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time 
(0x%02x)\n",
- intel_dp->psr_dpcd[1]);
-   return;
-   }
-
-   if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
-   adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
-   DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too 
long\n",
- psr_setup_time);
+   if (!intel_psr_setup_time_valid(intel_dp, adjusted_mode)) {
+   DRM_DEBUG_KMS("PSR Setup invalid\n");
return;
}
 
-- 
1.9.1

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[Intel-gfx] [PATCH] drm/i915/edp: Only use alternate fixed mode when requested

[clinton . a . taylor]

From: Clint Taylor 

In commit dc911f5bd8aa ("drm/i915/edp: Allow alternate fixed mode for eDP
if available."), the patch was always selecting the alternate refresh rate
even though user space was asking for the higher rate. This patch adds a
check for vrefresh rate as well as the rest of the mode geometry.

V2: use clock instead of vrefresh for compare.

Fixes: dc911f5bd8aac ("Allow alternate fixed mode for eDP if available.")
Cc: David Weinehall 
Cc: Rodrigo Vivi 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_dp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 62f82c4..6a2e256 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1681,7 +1681,8 @@ static bool intel_edp_compare_alt_mode(struct 
drm_display_mode *m1,
m1->vdisplay == m2->vdisplay &&
m1->vsync_start == m2->vsync_start &&
m1->vsync_end == m2->vsync_end &&
-   m1->vtotal == m2->vtotal);
+   m1->vtotal == m2->vtotal &&
+   m1->clock == m2->clock);
return bres;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH] drm/i915/edp: Only use alternate fixed mode when requested

[clinton . a . taylor]

From: Clint Taylor 

In commit dc911f5bd8aa ("drm/i915/edp: Allow alternate fixed mode for eDP
if available."), the patch was always selecting the alternate refresh rate
even though user space was asking for the higher rate. This patch adds a
check for vrefresh rate as well as the rest of the mode geometry.

Fixes: dc911f5bd8aac ("Allow alternate fixed mode for eDP if available.")
Cc: David Weinehall 
Cc: Rodrigo Vivi 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_dp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 62f82c4..c4c0e79 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1681,7 +1681,8 @@ static bool intel_edp_compare_alt_mode(struct 
drm_display_mode *m1,
m1->vdisplay == m2->vdisplay &&
m1->vsync_start == m2->vsync_start &&
m1->vsync_end == m2->vsync_end &&
-   m1->vtotal == m2->vtotal);
+   m1->vtotal == m2->vtotal &&
+   m1->vrefresh == m2->vrefresh);
return bres;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH] drm/i915: Register definitions for DP Phy compiance

[clinton . a . taylor]

From: Clint Taylor 

DisplayPort Phy compliance test patterns register definitions.

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_reg.h | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 95a2e51..91152c9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8702,6 +8702,24 @@ enum skl_power_gate {
 #define  DDI_BUF_BALANCE_LEG_ENABLE(1 << 31)
 #define DDI_BUF_TRANS_HI(port, i)  _MMIO(_PORT(port, _DDI_BUF_TRANS_A, 
_DDI_BUF_TRANS_B) + (i) * 8 + 4)
 
+/* DDI DP Compliance Control */
+#define DDI_DP_COMP_CTL_A  0x640F0
+#define DDI_DP_COMP_CTL_B  0x641F0
+#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, 
DDI_DP_COMP_CTL_B)
+#define  DDI_DP_COMP_CTL_ENABLE(1 << 31)
+#define  DDI_DP_COMP_CTL_D10_2 (0 << 28)
+#define  DDI_DP_COMP_CTL_SCRAMBLED_0   (1 << 28)
+#define  DDI_DP_COMP_CTL_PRBS7 (2 << 28)
+#define  DDI_DP_COMP_CTL_CUSTOM80  (3 << 28)
+#define  DDI_DP_COMP_CTL_HBR2  (4 << 28)
+#define  DDI_DP_COMP_CTL_SCRAMBLED_1   (5 << 28)
+#define  DDI_DP_COMP_CTL_HBR2_RESET(0xFC << 0)
+
+/* DDI DP Compliance Pattern */
+#define DDI_DP_COMP_PAT_A  0x640f4
+#define DDI_DP_COMP_PAT_B  0x641f4
+#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, 
DDI_DP_COMP_PAT_B) + (i) * 4) /* 3 dwords */
+
 /* Sideband Interface (SBI) is programmed indirectly, via
  * SBI_ADDR, which contains the register offset; and SBI_DATA,
  * which contains the payload */
-- 
1.9.1

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[Intel-gfx] [PATCH v4 i-g-t] tests/kms: increase max threshold time for edid read

[clinton . a . taylor]

From: Clint Taylor 

Current 50ms max threshold timing for an EDID read is very close to the
actual time for a 2 block HDMI EDID read. Adjust the timings base on
connector type as DP reads are at 1 MBit and HDMI at 100K bit. If an LSPcon
is connected to device under test the -l option should be passed to update
the threshold timing to allow the LSPcon to read the EDID at the HDMI
timing. The -l option should be used when LSPcon is on the motherboard or
if a USB_C->HDMI converter is present

V2: Adjust timings based on connector type, EDID size, and Add an option to
specify if an LSPcon is present.
V3: Add bugzilla to commit message
V4: remove edid_size check from HDMI multiplier. Fixes DVI on HDMI.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100047

Cc: Daniel Vetter 
Cc: Marta Lofstedt 
Signed-off-by: Clint Taylor 
---
 tests/kms_sysfs_edid_timing.c | 74 +++
 1 file changed, 60 insertions(+), 14 deletions(-)

diff --git a/tests/kms_sysfs_edid_timing.c b/tests/kms_sysfs_edid_timing.c
index 1201388..0382610 100644
--- a/tests/kms_sysfs_edid_timing.c
+++ b/tests/kms_sysfs_edid_timing.c
@@ -26,21 +26,46 @@
 #include 
 #include 
 
-#define THRESHOLD_PER_CONNECTOR10
-#define THRESHOLD_TOTAL50
-#define CHECK_TIMES15
+#define THRESHOLD_FOR_EMPTY_CONNECTOR  10
+#define THRESHOLD_PER_EDID_BLOCK   5
+#define HDMI_THRESHOLD_MULTIPLIER  10
+#define CHECK_TIMES10
 
 IGT_TEST_DESCRIPTION("This check the time we take to read the content of all "
 "the possible connectors. Without the edid -ENXIO patch "
 
"(http://permalink.gmane.org/gmane.comp.video.dri.devel/62083), "
-"we sometimes take a *really* long time. "
-"So let's just check for some reasonable timing here");
+"we sometimes take a *really* long time. So let's check "
+"an approximate time per edid block based on connector "
+"type. The -l option adjusts DP timing to reflect HDMI 
read "
+"timings from LSPcon.");
+
+/* The -l option has been added to correctly handle timings when an LSPcon is
+ * present. This could be on the platform itself or in a USB_C->HDMI converter.
+ * With LSPCon EDID read timing will need to change from the 1 Mbit AUX
+ * bus speed to the 100 Kbit HDMI DDC bus speed
+ */
+bool lspcon_present;
 
+static int opt_handler(int opt, int opt_index, void *data)
+{
+   if (opt == 'l') {
+   lspcon_present = true;
+   igt_info("set LSPcon present on DP ports\n");
+   }
 
-igt_simple_main
+   return 0;
+}
+
+int main(int argc, char **argv)
 {
DIR *dirp;
struct dirent *de;
+   lspcon_present = false;
+
+   igt_simple_init_parse_opts(, argv, "l", NULL, NULL,
+ opt_handler, NULL);
+
+   igt_skip_on_simulation();
 
dirp = opendir("/sys/class/drm");
igt_assert(dirp != NULL);
@@ -49,17 +74,34 @@ igt_simple_main
struct igt_mean mean = {};
struct stat st;
char path[PATH_MAX];
-   int i;
+   char edid_path[PATH_MAX];
+   char edid[512]; /* enough for 4 block edid */
+   unsigned long edid_size = 0;
+   int i, fd_edid;
+   unsigned int threshold = 0;
 
if (*de->d_name == '.')
continue;;
 
snprintf(path, sizeof(path), "/sys/class/drm/%s/status",
de->d_name);
+   snprintf(edid_path, sizeof(edid_path), "/sys/class/drm/%s/edid",
+   de->d_name);
 
if (stat(path, ))
continue;
 
+   fd_edid = open(edid_path, O_RDONLY);
+   if (fd_edid == -1) {
+   igt_warn("Read Error EDID\n");
+   continue;
+   }
+
+   edid_size = read(fd_edid, edid, 512);
+   threshold = THRESHOLD_PER_EDID_BLOCK * (edid_size / 128);
+   if (lspcon_present || !strncmp(de->d_name, "card0-HDMI", 10))
+   threshold *= HDMI_THRESHOLD_MULTIPLIER;
+
igt_mean_init();
for (i = 0; i < CHECK_TIMES; i++) {
struct timespec ts = {};
@@ -76,22 +118,26 @@ igt_simple_main
}
 
igt_debug("%s: mean.max %.2fns, %.2fus, %.2fms, "
- "mean.avg %.2fns, %.2fus, %.2fms\n",
+ "mean.avg %.2fns, %.2fus, %.2fms, "
+ "edid_size %lu, threshold %d\n",
  de->d_name,
  mean.max, mean.max / 1e3, 

[Intel-gfx] [PATCH v3 i-g-t] tests/kms: increase max threshold time for edid read

[clinton . a . taylor]

From: Clint Taylor 

Current 50ms max threshold timing for an EDID read is very close to the
actual time for a 2 block HDMI EDID read. Adjust the timings base on
connector type as DP reads are at 1 MBit and HDMI at 100K bit. If an LSPcon
is connected to device under test the -l option should be passed to update
the threshold timing to allow the LSPcon to read the EDID at the HDMI
timing. The -l option should be used when LSPcon is on the motherboard or
if a USB_C->HDMI converter is present

V2: Adjust timings based on connector type, EDID size, and Add an option to
specify if an LSPcon is present.
V3: added bugzilla to commit message

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100047

Cc: Daniel Vetter 
Cc: Marta Lofstedt 
Signed-off-by: Clint Taylor 
---
 tests/kms_sysfs_edid_timing.c | 76 +++
 1 file changed, 62 insertions(+), 14 deletions(-)

diff --git a/tests/kms_sysfs_edid_timing.c b/tests/kms_sysfs_edid_timing.c
index 1201388..441dfee 100644
--- a/tests/kms_sysfs_edid_timing.c
+++ b/tests/kms_sysfs_edid_timing.c
@@ -26,21 +26,46 @@
 #include 
 #include 
 
-#define THRESHOLD_PER_CONNECTOR10
-#define THRESHOLD_TOTAL50
-#define CHECK_TIMES15
+#define THRESHOLD_FOR_EMPTY_CONNECTOR  10
+#define THRESHOLD_PER_EDID_BLOCK   5
+#define HDMI_THRESHOLD_MULTIPLIER  10
+#define CHECK_TIMES10
 
 IGT_TEST_DESCRIPTION("This check the time we take to read the content of all "
 "the possible connectors. Without the edid -ENXIO patch "
 
"(http://permalink.gmane.org/gmane.comp.video.dri.devel/62083), "
-"we sometimes take a *really* long time. "
-"So let's just check for some reasonable timing here");
+"we sometimes take a *really* long time. So let's check "
+"an approximate time per edid block based on connector "
+"type. The -l option adjusts DP timing to reflect HDMI 
read "
+"timings from LSPcon.");
+
+/* The -l option has been added to correctly handle timings when an LSPcon is
+ * present. This could be on the platform itself or in a USB_C->HDMI converter.
+ * With LSPCon EDID read timing will need to change from the 1 Mbit AUX
+ * bus speed to the 100 Kbit HDMI DDC bus speed
+ */
+bool lspcon_present;
 
+static int opt_handler(int opt, int opt_index, void *data)
+{
+   if (opt == 'l') {
+   lspcon_present = true;
+   igt_info("set LSPcon present on DP ports\n");
+   }
 
-igt_simple_main
+   return 0;
+}
+
+int main(int argc, char **argv)
 {
DIR *dirp;
struct dirent *de;
+   lspcon_present = false;
+
+   igt_simple_init_parse_opts(, argv, "l", NULL, NULL,
+ opt_handler, NULL);
+
+   igt_skip_on_simulation();
 
dirp = opendir("/sys/class/drm");
igt_assert(dirp != NULL);
@@ -49,17 +74,36 @@ igt_simple_main
struct igt_mean mean = {};
struct stat st;
char path[PATH_MAX];
-   int i;
+   char edid_path[PATH_MAX];
+   char edid[512]; /* enough for 4 block edid */
+   unsigned long edid_size = 0;
+   int i, fd_edid;
+   unsigned int threshold = 0;
 
if (*de->d_name == '.')
continue;;
 
snprintf(path, sizeof(path), "/sys/class/drm/%s/status",
de->d_name);
+   snprintf(edid_path, sizeof(edid_path), "/sys/class/drm/%s/edid",
+   de->d_name);
 
if (stat(path, ))
continue;
 
+   fd_edid = open(edid_path, O_RDONLY);
+   if (fd_edid == -1) {
+   igt_warn("Read Error EDID\n");
+   continue;
+   }
+
+   edid_size = read(fd_edid, edid, 512);
+   threshold = THRESHOLD_PER_EDID_BLOCK * (edid_size / 128);
+   if (lspcon_present || (edid_size > 128 &&
+   !strncmp(de->d_name, "card0-HDMI", 10))) {
+   threshold *= HDMI_THRESHOLD_MULTIPLIER;
+   }
+
igt_mean_init();
for (i = 0; i < CHECK_TIMES; i++) {
struct timespec ts = {};
@@ -76,22 +120,26 @@ igt_simple_main
}
 
igt_debug("%s: mean.max %.2fns, %.2fus, %.2fms, "
- "mean.avg %.2fns, %.2fus, %.2fms\n",
+ "mean.avg %.2fns, %.2fus, %.2fms, "
+ "edid_size %lu, threshold %d\n",
  de->d_name,
  mean.max, mean.max / 1e3, mean.max / 

[Intel-gfx] [PATCH v2 i-g-t] tests/kms: increase max threshold time for edid read

[clinton . a . taylor]

From: Clint Taylor 

Current 50ms max threshold timing for an EDID read is very close to the
actual time for a 2 block HDMI EDID read. Adjust the timings base on
connector type as DP reads are at 1 MBit and HDMI at 100K bit. If an LSPcon
is connected to device under test the -l option should be passed to update
the threshold timing to allow the LSPcon to read the EDID at the HDMI
timing. The -l option should be used when LSPcon is on the motherboard or
if a USB_C->HDMI converter is present

V2: Adjust timings based on connector type, EDID size, and Add an option to
specify if an LSPcon is present.

Cc: Daniel Vetter 
Cc: Marta Lofstedt 
Signed-off-by: Clint Taylor 
---
 tests/kms_sysfs_edid_timing.c | 76 +++
 1 file changed, 62 insertions(+), 14 deletions(-)

diff --git a/tests/kms_sysfs_edid_timing.c b/tests/kms_sysfs_edid_timing.c
index 1201388..441dfee 100644
--- a/tests/kms_sysfs_edid_timing.c
+++ b/tests/kms_sysfs_edid_timing.c
@@ -26,21 +26,46 @@
 #include 
 #include 
 
-#define THRESHOLD_PER_CONNECTOR10
-#define THRESHOLD_TOTAL50
-#define CHECK_TIMES15
+#define THRESHOLD_FOR_EMPTY_CONNECTOR  10
+#define THRESHOLD_PER_EDID_BLOCK   5
+#define HDMI_THRESHOLD_MULTIPLIER  10
+#define CHECK_TIMES10
 
 IGT_TEST_DESCRIPTION("This check the time we take to read the content of all "
 "the possible connectors. Without the edid -ENXIO patch "
 
"(http://permalink.gmane.org/gmane.comp.video.dri.devel/62083), "
-"we sometimes take a *really* long time. "
-"So let's just check for some reasonable timing here");
+"we sometimes take a *really* long time. So let's check "
+"an approximate time per edid block based on connector "
+"type. The -l option adjusts DP timing to reflect HDMI 
read "
+"timings from LSPcon.");
+
+/* The -l option has been added to correctly handle timings when an LSPcon is
+ * present. This could be on the platform itself or in a USB_C->HDMI converter.
+ * With LSPCon EDID read timing will need to change from the 1 Mbit AUX
+ * bus speed to the 100 Kbit HDMI DDC bus speed
+ */
+bool lspcon_present;
 
+static int opt_handler(int opt, int opt_index, void *data)
+{
+   if (opt == 'l') {
+   lspcon_present = true;
+   igt_info("set LSPcon present on DP ports\n");
+   }
 
-igt_simple_main
+   return 0;
+}
+
+int main(int argc, char **argv)
 {
DIR *dirp;
struct dirent *de;
+   lspcon_present = false;
+
+   igt_simple_init_parse_opts(, argv, "l", NULL, NULL,
+ opt_handler, NULL);
+
+   igt_skip_on_simulation();
 
dirp = opendir("/sys/class/drm");
igt_assert(dirp != NULL);
@@ -49,17 +74,36 @@ igt_simple_main
struct igt_mean mean = {};
struct stat st;
char path[PATH_MAX];
-   int i;
+   char edid_path[PATH_MAX];
+   char edid[512]; /* enough for 4 block edid */
+   unsigned long edid_size = 0;
+   int i, fd_edid;
+   unsigned int threshold = 0;
 
if (*de->d_name == '.')
continue;;
 
snprintf(path, sizeof(path), "/sys/class/drm/%s/status",
de->d_name);
+   snprintf(edid_path, sizeof(edid_path), "/sys/class/drm/%s/edid",
+   de->d_name);
 
if (stat(path, ))
continue;
 
+   fd_edid = open(edid_path, O_RDONLY);
+   if (fd_edid == -1) {
+   igt_warn("Read Error EDID\n");
+   continue;
+   }
+
+   edid_size = read(fd_edid, edid, 512);
+   threshold = THRESHOLD_PER_EDID_BLOCK * (edid_size / 128);
+   if (lspcon_present || (edid_size > 128 &&
+   !strncmp(de->d_name, "card0-HDMI", 10))) {
+   threshold *= HDMI_THRESHOLD_MULTIPLIER;
+   }
+
igt_mean_init();
for (i = 0; i < CHECK_TIMES; i++) {
struct timespec ts = {};
@@ -76,22 +120,26 @@ igt_simple_main
}
 
igt_debug("%s: mean.max %.2fns, %.2fus, %.2fms, "
- "mean.avg %.2fns, %.2fus, %.2fms\n",
+ "mean.avg %.2fns, %.2fus, %.2fms, "
+ "edid_size %lu, threshold %d\n",
  de->d_name,
  mean.max, mean.max / 1e3, mean.max / 1e6,
- mean.mean, mean.mean / 1e3, mean.mean / 1e6);
+  

[Intel-gfx] [PATCH i-g-t] tests/kms: increase max threshold time for edid read

[clinton . a . taylor]

From: Clint Taylor 

Current 50ms max threshold timing for an EDID read is very close to the
actual time for a 2 block HDMI EDID read of 48ms. Any delay like a clock
stretch by the EDID eeprom will cause this test to fail. A 4 block HDMI
EDID read takes approximately 88ms under nominal conditions, making the max
threshold 95ms will allow this test to pass regardless of monitor attached.

Signed-off-by: Clint Taylor 
---
 tests/kms_sysfs_edid_timing.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/tests/kms_sysfs_edid_timing.c b/tests/kms_sysfs_edid_timing.c
index 1201388..b45e080 100644
--- a/tests/kms_sysfs_edid_timing.c
+++ b/tests/kms_sysfs_edid_timing.c
@@ -27,14 +27,14 @@
 #include 
 
 #define THRESHOLD_PER_CONNECTOR10
-#define THRESHOLD_TOTAL50
+#define THRESHOLD_TOTAL95
 #define CHECK_TIMES15
 
 IGT_TEST_DESCRIPTION("This check the time we take to read the content of all "
 "the possible connectors. Without the edid -ENXIO patch "
 
"(http://permalink.gmane.org/gmane.comp.video.dri.devel/62083), "
-"we sometimes take a *really* long time. "
-"So let's just check for some reasonable timing here");
+"we sometimes take a *really* long time. So let's just "
+"check an approximate HDMI 4 block edid read timing here");
 
 
 igt_simple_main
-- 
1.9.1

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[Intel-gfx] [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode

[clinton . a . taylor]

From: Clint Taylor 

DDIA Lane capability control 4 lane bit is not being set by firmware during
clone mode boot. This occurs when multiple monitors are connected during
boot. The driver will configure the port for 2 lane maximum width if this
bit is not set.

Once DDIA/E lane split is supported in vbt and the i915 driver we will need
to revisit this code.

Cc: Rodrigo Vivi 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_ddi.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 494fbe0..e7644b4 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2713,9 +2713,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, 
enum port port)
 * configuration so that we use the proper lane count for our
 * calculations.
 */
-   if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
+   if ((IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
+   port == PORT_A) {
if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
-   DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for 
port A; fixing\n");
+   DRM_DEBUG_KMS("BIOS forgot to set DDI_A_4_LANES for 
port A\n");
intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
max_lanes = 4;
}
-- 
1.9.1

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[Intel-gfx] [PATCH] drm/i915/glk: RGB565 planes now allow 90/270 rotation

[clinton . a . taylor]

From: Clint Taylor 

RGB565 Pixel format planes can now be rotated at 90 and 270 degrees

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_atomic_plane.c | 11 ---
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c 
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 4325cb0..9a7a7ea 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -144,19 +144,16 @@ int intel_plane_atomic_check_with_state(struct 
intel_crtc_state *crtc_state,
 
/*
 * 90/270 is not allowed with RGB64 16:16:16:16,
-* RGB 16-bit 5:6:5, and Indexed 8-bit.
+* RGB 16-bit 5:6:5 (prior to gen 9 LP), and Indexed 8-bit.
 * TBD: Add RGB64 case once its added in supported format list.
 */
-   switch (state->fb->format->format) {
-   case DRM_FORMAT_C8:
-   case DRM_FORMAT_RGB565:
+   if ((state->fb->format->format == DRM_FORMAT_C8) ||
+   (state->fb->format->format == DRM_FORMAT_RGB565 &&
+!IS_GEN9_LP(dev_priv) )) {
DRM_DEBUG_KMS("Unsupported pixel format %s for 
90/270!\n",
  
drm_get_format_name(state->fb->format->format,
  _name));
return -EINVAL;
-
-   default:
-   break;
}
}
 
-- 
1.9.1

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[Intel-gfx] [PATCH] drm/i915: Detect USB-C specific dongles before reducing M and N

[clinton . a . taylor]

From: Clint Taylor 

The Analogix 7737 DP to HDMI converter requires reduced N and M values when
to operate correctly at HBR2. Detect this IC by its OUI value of 0x0022B9.

Cc: Jani Nikula 
Cc: Dhinakaran Pandiyan 

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_drv.h  |  3 ++-
 drivers/gpu/drm/i915/intel_display.c | 22 ++
 drivers/gpu/drm/i915/intel_dp.c  | 22 --
 drivers/gpu/drm/i915/intel_dp_mst.c  |  3 ++-
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 5 files changed, 39 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 74dffbe..492e47e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -563,7 +563,8 @@ struct intel_link_m_n {
 
 void intel_link_compute_m_n(int bpp, int nlanes,
int pixel_clock, int link_clock,
-   struct intel_link_m_n *m_n);
+   struct intel_link_m_n *m_n,
+   bool reduce_m_n);
 
 /* Interface history:
  *
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 7bcc604..8920a99 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6104,7 +6104,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc 
*intel_crtc,
pipe_config->fdi_lanes = lane;
 
intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
-  link_bw, _config->fdi_m_n);
+  link_bw, _config->fdi_m_n, false);
 
ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
@@ -6280,7 +6280,8 @@ static int intel_crtc_compute_config(struct intel_crtc 
*crtc,
 }
 
 static void compute_m_n(unsigned int m, unsigned int n,
-   uint32_t *ret_m, uint32_t *ret_n)
+   uint32_t *ret_m, uint32_t *ret_n,
+  bool reduce_m_n)
 {
/*
 * Reduce M/N as much as possible without loss in precision. Several DP
@@ -6288,9 +6289,11 @@ static void compute_m_n(unsigned int m, unsigned int n,
 * values. The passed in values are more likely to have the least
 * significant bits zero than M after rounding below, so do this first.
 */
-   while ((m & 1) == 0 && (n & 1) == 0) {
-   m >>= 1;
-   n >>= 1;
+   if (reduce_m_n) {
+   while ((m & 1) == 0 && (n & 1) == 0) {
+   m >>= 1;
+   n >>= 1;
+   }
}
 
*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
@@ -6301,16 +6304,19 @@ static void compute_m_n(unsigned int m, unsigned int n,
 void
 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
   int pixel_clock, int link_clock,
-  struct intel_link_m_n *m_n)
+  struct intel_link_m_n *m_n,
+ bool reduce_m_n)
 {
m_n->tu = 64;
 
compute_m_n(bits_per_pixel * pixel_clock,
link_clock * nlanes * 8,
-   _n->gmch_m, _n->gmch_n);
+   _n->gmch_m, _n->gmch_n,
+   reduce_m_n);
 
compute_m_n(pixel_clock, link_clock,
-   _n->link_m, _n->link_n);
+   _n->link_m, _n->link_n,
+   reduce_m_n);
 }
 
 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4a6feb6..f4c0582 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1548,6 +1548,20 @@ static void intel_dp_print_rates(struct intel_dp 
*intel_dp)
DRM_DEBUG_KMS("common rates: %s\n", str);
 }
 
+bool __intel_reduced_m_n(struct intel_dp *intel_dp)
+{
+   struct intel_dp_desc *desc = _dp->desc;
+   bool ret = false;
+
+   /* Analogix 7737 needs reduced N and M at HBR2 link rates */
+   if (desc->oui[0] == 0x00 &&
+   desc->oui[1] == 0x22 &&
+   desc->oui[2] == 0xb9)
+   ret = true;
+
+   return ret;
+}
+
 bool
 __intel_dp_read_desc(struct intel_dp *intel_dp, struct intel_dp_desc *desc)
 {
@@ -1568,6 +1582,8 @@ bool intel_dp_read_desc(struct intel_dp *intel_dp)
if (!__intel_dp_read_desc(intel_dp, desc))
return false;
 
+   intel_dp->reduce_m_n = __intel_reduced_m_n(intel_dp);
+
dev_id_len = strnlen(desc->device_id, sizeof(desc->device_id));
DRM_DEBUG_KMS("DP %s: OUI %*phD%s dev-ID %*pE HW-rev %d.%d SW-rev 
%d.%d\n",
  drm_dp_is_branch(intel_dp->dpcd) ? "branch" : "sink",
@@ -1790,7 +1806,8 @@ static int 

[Intel-gfx] [PATCH v8 1/3] drm_fourcc: Add new P010, P016 video format

[clinton . a . taylor]

From: Clint Taylor 

P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
channel video format.

P012 is a planar 4:2:0 YUV 12 bits per channel

P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
channel video format.

V3: Added P012 and fixed cpp for P010
V4: format definition refined per review
V5: Format comment block for each new pixel format
V6: reversed Cb/Cr order in comments
v7: reversed Cb/Cr order in comments of header files, remove
the wrong part of commit message.
V8: reversed V7 changes except commit message and rebased.

Cc: Daniel Stone 
Cc: Ville Syrjälä 

Signed-off-by: Randy Li 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/drm_fourcc.c  |3 +++
 include/uapi/drm/drm_fourcc.h |   21 +
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 9c0152d..6101520 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -173,6 +173,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY,.depth = 0,  
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_VYUY,.depth = 0,  
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_AYUV,.depth = 0,  
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+   { .format = DRM_FORMAT_P010,.depth = 0,  
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+   { .format = DRM_FORMAT_P012,.depth = 0,  
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+   { .format = DRM_FORMAT_P016,.depth = 0,  
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
};
 
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 995c8f9..c995cc4 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -142,6 +142,27 @@
 #define DRM_FORMAT_NV42fourcc_code('N', 'V', '4', '2') /* 
non-subsampled Cb:Cr plane */
 
 /*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y:x [10:6] little endian
+ * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
+ */
+#define DRM_FORMAT_P010fourcc_code('P', '0', '1', '0') /* 2x2 
subsampled Cr:Cb plane 10 bits per channel */
+
+/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y:x [12:4] little endian
+ * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
+ */
+#define DRM_FORMAT_P012fourcc_code('P', '0', '1', '2') /* 2x2 
subsampled Cr:Cb plane 12 bits per channel */
+
+/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y little endian
+ * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
+ */
+#define DRM_FORMAT_P016fourcc_code('P', '0', '1', '6') /* 2x2 
subsampled Cr:Cb plane 16 bits per channel */
+
+/*
  * 3 plane YCbCr
  * index 0: Y plane, [7:0] Y
  * index 1: Cb plane, [7:0] Cb
-- 
1.7.9.5

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[Intel-gfx] [PATCH v2] drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters

[clinton . a . taylor]

From: Clint Taylor 

Several major vendor USB-C->HDMI converters fail to recover a 5.4 GHz 1 lane
signal if the Data Link N is greater than 0x8.
Patch detects when 1 lane 5.4 GHz signal is being used and makes the maximum
value 20 bit instead of the maximum specification supported 24 bit value.

v2: Detect specific device that exhibits the issue.

Cc: Dhinakaran Pandiyan 
Cc: Jani Nikula 
Cc: Anusha Srivatsa 

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93578

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_drv.h  |3 ++-
 drivers/gpu/drm/i915/i915_reg.h  |2 ++
 drivers/gpu/drm/i915/intel_display.c |   20 ++--
 drivers/gpu/drm/i915/intel_dp.c  |   14 --
 drivers/gpu/drm/i915/intel_dp_mst.c  |3 ++-
 5 files changed, 32 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a5947a4..6869df9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -580,7 +580,8 @@ struct intel_link_m_n {
 
 void intel_link_compute_m_n(int bpp, int nlanes,
int pixel_clock, int link_clock,
-   struct intel_link_m_n *m_n);
+   struct intel_link_m_n *m_n,
+   bool reduced_n);
 
 /* Interface history:
  *
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 04c8f69..838d8d5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4869,6 +4869,8 @@ enum {
 
 #define  DATA_LINK_M_N_MASK(0xff)
 #define  DATA_LINK_N_MAX   (0x80)
+/* Maximum N value useable on some DP->HDMI converters */
+#define  DATA_LINK_REDUCED_N_MAX (0x8)
 
 #define _PIPEA_DATA_N_G4X  0x70054
 #define _PIPEB_DATA_N_G4X  0x71054
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 010e5dd..143c7ac 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6139,7 +6139,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc 
*intel_crtc,
pipe_config->fdi_lanes = lane;
 
intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
-  link_bw, _config->fdi_m_n);
+  link_bw, _config->fdi_m_n, false);
 
ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
@@ -6315,9 +6315,10 @@ static int intel_crtc_compute_config(struct intel_crtc 
*crtc,
 }
 
 static void compute_m_n(unsigned int m, unsigned int n,
-   uint32_t *ret_m, uint32_t *ret_n)
+   uint32_t *ret_m, uint32_t *ret_n,
+   uint32_t max_link_n)
 {
-   *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
+   *ret_n = min_t(unsigned int, roundup_pow_of_two(n), max_link_n);
*ret_m = div_u64((uint64_t) m * *ret_n, n);
intel_reduce_m_n_ratio(ret_m, ret_n);
 }
@@ -6325,16 +6326,23 @@ static void compute_m_n(unsigned int m, unsigned int n,
 void
 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
   int pixel_clock, int link_clock,
-  struct intel_link_m_n *m_n)
+  struct intel_link_m_n *m_n,
+  bool reduced_n)
 {
+   uint32_t max_link_n = DATA_LINK_N_MAX;
m_n->tu = 64;
 
+   if ((reduced_n) && (nlanes == 1) && (link_clock >= 54))
+   max_link_n = DATA_LINK_REDUCED_N_MAX;
+
compute_m_n(bits_per_pixel * pixel_clock,
link_clock * nlanes * 8,
-   _n->gmch_m, _n->gmch_n);
+   _n->gmch_m, _n->gmch_n,
+   max_link_n);
 
compute_m_n(pixel_clock, link_clock,
-   _n->link_m, _n->link_n);
+   _n->link_m, _n->link_n,
+   max_link_n);
 }
 
 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fd96a6c..9c96f5f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1624,6 +1624,8 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
int common_rates[DP_MAX_SUPPORTED_RATES] = {};
int common_len;
uint8_t link_bw, rate_select;
+   char id[6];
+   bool reduced_n = false;
 
common_len = intel_dp_common_rates(intel_dp, common_rates);
 
@@ -1750,10 +1752,17 @@ static int intel_dp_compute_bpp(struct intel_dp 
*intel_dp,
DRM_DEBUG_KMS("DP link bw required %i available %i\n",
  mode_rate, link_avail);
 
+   /* Quirk to detect DP->HDMI converter */
+   

[Intel-gfx] [PATCH] drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters

[clinton . a . taylor]

From: Clint Taylor 

Several major vendor USB-C->HDMI converters fail to recover a 5.4 GHz 1 lane
signal if the Data Link N is greater than 0x8.
Patch detects when 1 lane 5.4 GHz signal is being used and makes the maximum
value 20 bit instead of the maximum specification supported 24 bit value.

Cc: Jani Nikula 
Cc: Anusha Srivatsa 

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_reg.h  |2 ++
 drivers/gpu/drm/i915/intel_display.c |   15 +++
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 04c8f69..838d8d5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4869,6 +4869,8 @@ enum {
 
 #define  DATA_LINK_M_N_MASK(0xff)
 #define  DATA_LINK_N_MAX   (0x80)
+/* Maximum N value useable on some DP->HDMI converters */
+#define  DATA_LINK_REDUCED_N_MAX (0x8)
 
 #define _PIPEA_DATA_N_G4X  0x70054
 #define _PIPEB_DATA_N_G4X  0x71054
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 010e5dd..6e1fdd2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6315,9 +6315,10 @@ static int intel_crtc_compute_config(struct intel_crtc 
*crtc,
 }
 
 static void compute_m_n(unsigned int m, unsigned int n,
-   uint32_t *ret_m, uint32_t *ret_n)
+   uint32_t *ret_m, uint32_t *ret_n,
+   uint32_t max_link_n)
 {
-   *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
+   *ret_n = min_t(unsigned int, roundup_pow_of_two(n), max_link_n);
*ret_m = div_u64((uint64_t) m * *ret_n, n);
intel_reduce_m_n_ratio(ret_m, ret_n);
 }
@@ -6327,14 +6328,20 @@ static void compute_m_n(unsigned int m, unsigned int n,
   int pixel_clock, int link_clock,
   struct intel_link_m_n *m_n)
 {
+   uint32_t max_link_n = DATA_LINK_N_MAX;
m_n->tu = 64;
 
+   if ((nlanes==1) && (link_clock >= 54))
+   max_link_n = DATA_LINK_REDUCED_N_MAX;
+
compute_m_n(bits_per_pixel * pixel_clock,
link_clock * nlanes * 8,
-   _n->gmch_m, _n->gmch_n);
+   _n->gmch_m, _n->gmch_n,
+   max_link_n);
 
compute_m_n(pixel_clock, link_clock,
-   _n->link_m, _n->link_n);
+   _n->link_m, _n->link_n,
+   max_link_n);
 }
 
 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
-- 
1.7.9.5

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[Intel-gfx] [PATCH v2] drm/i915: prevent crash with .disable_display parameter

[clinton . a . taylor]

From: Clint Taylor 

The .disable_display parameter was causing a fatal crash when fbdev
was dereferenced during driver init.

V1: protection in i915_drv.c
V2: Moved protection to intel_fbdev.c

Cc: Chris Wilson 

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_fbdev.c |3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_fbdev.c 
b/drivers/gpu/drm/i915/intel_fbdev.c
index bdefa61..bb0e9bf 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -742,6 +742,9 @@ void intel_fbdev_initial_config_async(struct drm_device 
*dev)
 {
struct intel_fbdev *ifbdev = to_i915(dev)->fbdev;
 
+   if (!ifbdev)
+   return;
+
ifbdev->cookie = async_schedule(intel_fbdev_initial_config, ifbdev);
 }
 
-- 
1.7.9.5

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[Intel-gfx] [PATCH] drm/i915: prevent crash with .disable_display parameter

[clinton . a . taylor]

From: Clint Taylor 

The .disable_display parameter was causing a fatal crash when fbdev was
dereferenced during driver init.

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_drv.c |4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4e5ea58..b2a9195 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1140,7 +1140,9 @@ static void i915_driver_register(struct drm_i915_private 
*dev_priv)
 * irqs are fully enabled. We do it last so that the async config
 * cannot run before the connectors are registered.
 */
-   intel_fbdev_initial_config_async(dev);
+   if (dev_priv->fbdev) {
+   intel_fbdev_initial_config_async(dev);
+   }
 }
 
 /**
-- 
1.7.9.5

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[Intel-gfx] [PATCH i-g-t] tools/intel_reg: enable quiet option for mmio

[clinton . a . taylor]

From: Clint Taylor 

Skip decode options and formatting when the quiet option is used during
mmio reads. Makes intel_reg usable by scripts to return MMIO values.

Signed-off-by: Clint Taylor 
---
 tools/intel_reg.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/tools/intel_reg.c b/tools/intel_reg.c
index 73fbd6d..e869292 100644
--- a/tools/intel_reg.c
+++ b/tools/intel_reg.c
@@ -202,7 +202,9 @@ static void dump_decode(struct config *config, struct reg 
*reg, uint32_t val)
 
if (reg->port_desc.port == PORT_MMIO) {
/* Omit port name for MMIO, optionally include MMIO offset. */
-   if (reg->mmio_offset)
+   if (config->verbosity < 0)
+   printf("0x%08x\n", val);
+   else if (reg->mmio_offset)
printf("%24s (0x%08x:0x%08x): 0x%08x%s",
   reg->name ?: "",
   reg->mmio_offset, reg->addr,
@@ -706,6 +708,9 @@ static int read_reg_spec(struct config *config)
struct stat st;
int r;
 
+   if (config->verbosity < 0)
+   goto builtin;
+
path = config->specfile;
if (!path)
path = getenv("INTEL_REG_SPEC");
-- 
2.1.2

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[Intel-gfx] [PATCH v2] drm/i915/bxt: Enable PSR platform support for BXT

[clinton . a . taylor]

From: Clint Taylor 

Add IS_BROXTON() to the HAS_PSR() MACRO. Tested with a Sharp 2560x1440
panel that claims PSR is enable and in progress.

v2:rebase to latest nightly

CC: Imre Deak 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_drv.h |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7c81757..3e411f0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2823,7 +2823,8 @@ struct drm_i915_cmd_table {
 #define HAS_FPGA_DBG_UNCLAIMED(dev)(INTEL_INFO(dev)->has_fpga_dbg)
 #define HAS_PSR(dev)   (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
-IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
+IS_SKYLAKE(dev) || IS_KABYLAKE(dev) || \
+IS_BROXTON(dev))
 #define HAS_RUNTIME_PM(dev)(IS_GEN6(dev) || IS_HASWELL(dev) || \
 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
-- 
1.7.9.5

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[Intel-gfx] [PATCH] drm/i915/bxt: Enable PSR platform support for BXT

[clinton . a . taylor]

From: Clint Taylor 

Add IS_BROXTON() to the HAS_PSR() MACRO. Tested with a Sharp 2560x1440
panel that claims PSR is enable and in progress.

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_drv.h |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 78d38c2..1407ff1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2796,7 +2796,8 @@ struct drm_i915_cmd_table {
 #define HAS_FPGA_DBG_UNCLAIMED(dev)(INTEL_INFO(dev)->has_fpga_dbg)
 #define HAS_PSR(dev)   (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
-IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
+IS_SKYLAKE(dev) || IS_KABYLAKE(dev) || \
+IS_BROXTON(dev))
 #define HAS_RUNTIME_PM(dev)(IS_GEN6(dev) || IS_HASWELL(dev) || \
 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
-- 
1.7.9.5

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[Intel-gfx] [PATCH V11] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

[clinton . a . taylor]

From: Clint Taylor 

WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
is enabled when the cdclk is less then required. DP connected to DDI2
and HPD on either port works correctly.

Set cdclk based on the max required pixel clock based on VCO
selected. Track boot vco instead of boot cdclk.

The vco is now tracked at the atomic level and all CRTCs updated if
the required vco is changed. Not tested with eDP v1.4 panels that
require 8640 vco due to availability.

V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.
V4: track target vco is atomic state. modeset all CRTCs if vco changes
V5: rename atomic variable, cleaner if/else logic, use existing vco if
  encoder does not return a new vco value. check_patch.pl cleanup
V6: simplify logic in intel_modeset_checks.
V7: reorder an IF for readability and whitespace fix.
V8: use dev_cdclk for tracking new cdclk during atomic
V9: correctly handle vco 8640 when crtcs==0
V10: Clean up if else in crtcs==0
V11: Rebase for new intel_dpll_mgr.c

Reviewed-by: Ville Syrjälä 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_drv.h   |2 +-
 drivers/gpu/drm/i915/intel_display.c  |  111 -
 drivers/gpu/drm/i915/intel_dpll_mgr.c |9 +--
 drivers/gpu/drm/i915/intel_drv.h  |5 ++
 4 files changed, 106 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 80b14f1..bf87e62 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1759,7 +1759,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 
unsigned int fsb_freq, mem_freq, is_ddr3;
-   unsigned int skl_boot_cdclk;
+   unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int rawclk_freq;
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index ce55f0b..fc5268c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5584,7 +5584,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
return (freq - 1000) / 500;
 }
 
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
 {
unsigned int i;
 
@@ -5742,17 +5742,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 
 void skl_init_cdclk(struct drm_i915_private *dev_priv)
 {
-   unsigned int required_vco;
+   unsigned int cdclk;
 
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
-   required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
-   skl_dpll0_enable(dev_priv, required_vco);
+   if (dev_priv->skl_vco_freq != 8640)
+   dev_priv->skl_vco_freq = 8100;
+   skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
+   cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
+   } else {
+   cdclk = dev_priv->cdclk_freq;
}
 
-   /* set CDCLK to the frequency the BIOS chose */
-   skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+   /* set CDCLK to the lowest frequency, Modeset follows */
+   skl_set_cdclk(dev_priv, cdclk);
 
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5768,7 +5772,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 {
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
-   int freq = dev_priv->skl_boot_cdclk;
+   int freq = dev_priv->cdclk_freq;
 
/*
 * check if the pre-os intialized the display
@@ -5792,11 +5796,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
/* All well; nothing to sanitize */
return false;
 sanitize:
-   /*
-* As of now initialize with max cdclk till
-* we get dynamic cdclk support
-* */
-   dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
+
skl_init_cdclk(dev_priv);
 
/* we did have to sanitize */
@@ -9753,6 +9753,73 @@ static void broadwell_modeset_commit_cdclk(struct 
drm_atomic_state *old_state)
broadwell_set_cdclk(dev, req_cdclk);
 }
 
+static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+   struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+   struct drm_i915_private *dev_priv = to_i915(state->dev);
+   const int max_pixclk = 

[Intel-gfx] [PATCH V10] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

[clinton . a . taylor]

From: Clint Taylor 

WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
is enabled when the cdclk is less then required. DP connected to DDI2
and HPD on either port works correctly.

Set cdclk based on the max required pixel clock based on VCO
selected. Track boot vco instead of boot cdclk.

The vco is now tracked at the atomic level and all CRTCs updated if
the required vco is changed. Not tested with eDP v1.4 panels that
require 8640 vco due to availability.

V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.
V4: track target vco is atomic state. modeset all CRTCs if vco changes
V5: rename atomic variable, cleaner if/else logic, use existing vco if
  encoder does not return a new vco value. check_patch.pl cleanup
V6: simplify logic in intel_modeset_checks.
V7: reorder an IF for readability and whitespace fix.
V8: use dev_cdclk for tracking new cdclk during atomic
V9: correctly handle vco 8640 when crtcs==0
V10: Clean up if else in crtcs==0

Reviewed-by: Ville Syrjälä 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_drv.h  |2 +-
 drivers/gpu/drm/i915/intel_ddi.c |2 +-
 drivers/gpu/drm/i915/intel_display.c |  111 +-
 drivers/gpu/drm/i915/intel_dp.c  |5 ++
 drivers/gpu/drm/i915/intel_drv.h |5 ++
 5 files changed, 107 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f37ac12..83bb3fd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1833,7 +1833,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 
unsigned int fsb_freq, mem_freq, is_ddr3;
-   unsigned int skl_boot_cdclk;
+   unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int rawclk_freq;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 62de9f4..f628647 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3003,7 +3003,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
int cdclk_freq;
 
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
-   dev_priv->skl_boot_cdclk = cdclk_freq;
+   dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
if (skl_sanitize_cdclk(dev_priv))
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 62d36a7..6f2d429 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5811,7 +5811,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
return (freq - 1000) / 500;
 }
 
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
 {
unsigned int i;
 
@@ -5969,17 +5969,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 
 void skl_init_cdclk(struct drm_i915_private *dev_priv)
 {
-   unsigned int required_vco;
+   unsigned int cdclk;
 
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
-   required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
-   skl_dpll0_enable(dev_priv, required_vco);
+   if (dev_priv->skl_vco_freq != 8640)
+   dev_priv->skl_vco_freq = 8100;
+   skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
+   cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
+   } else {
+   cdclk = dev_priv->cdclk_freq;
}
 
-   /* set CDCLK to the frequency the BIOS chose */
-   skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+   /* set CDCLK to the lowest frequency, Modeset follows */
+   skl_set_cdclk(dev_priv, cdclk);
 
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5995,7 +5999,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 {
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
-   int freq = dev_priv->skl_boot_cdclk;
+   int freq = dev_priv->cdclk_freq;
 
/*
 * check if the pre-os intialized the display
@@ -6019,11 +6023,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
/* All well; nothing to sanitize */

[Intel-gfx] [PATCH V9] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

[clinton . a . taylor]

From: Clint Taylor 

WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
is enabled when the cdclk is less then required. DP connected to DDI2
and HPD on either port works correctly.

Set cdclk based on the max required pixel clock based on VCO
selected. Track boot vco instead of boot cdclk.

The vco is now tracked at the atomic level and all CRTCs updated if
the required vco is changed. Not tested with eDP v1.4 panels that
require 8640 vco due to availability.

V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.
V4: track target vco is atomic state. modeset all CRTCs if vco changes
V5: rename atomic variable, cleaner if/else logic, use existing vco if
  encoder does not return a new vco value. check_patch.pl cleanup
V6: simplify logic in intel_modeset_checks.
V7: reorder an IF for readability and whitespace fix.
V8: use dev_cdclk for tracking new cdclk during atomic
V9: correctly handle vco 8640 when crtcs==0

Reviewed-by: Ville Syrjälä 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_drv.h  |2 +-
 drivers/gpu/drm/i915/intel_ddi.c |2 +-
 drivers/gpu/drm/i915/intel_display.c |  113 +-
 drivers/gpu/drm/i915/intel_dp.c  |5 ++
 drivers/gpu/drm/i915/intel_drv.h |5 ++
 5 files changed, 109 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f37ac12..83bb3fd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1833,7 +1833,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 
unsigned int fsb_freq, mem_freq, is_ddr3;
-   unsigned int skl_boot_cdclk;
+   unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int rawclk_freq;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 62de9f4..f628647 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3003,7 +3003,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
int cdclk_freq;
 
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
-   dev_priv->skl_boot_cdclk = cdclk_freq;
+   dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
if (skl_sanitize_cdclk(dev_priv))
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 62d36a7..b8c7c5e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5811,7 +5811,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
return (freq - 1000) / 500;
 }
 
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
 {
unsigned int i;
 
@@ -5969,17 +5969,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 
 void skl_init_cdclk(struct drm_i915_private *dev_priv)
 {
-   unsigned int required_vco;
+   unsigned int cdclk;
 
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
-   required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
-   skl_dpll0_enable(dev_priv, required_vco);
+   if (dev_priv->skl_vco_freq != 8640)
+   dev_priv->skl_vco_freq = 8100;
+   skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
+   cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
+   } else {
+   cdclk = dev_priv->cdclk_freq;
}
 
-   /* set CDCLK to the frequency the BIOS chose */
-   skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+   /* set CDCLK to the lowest frequency, Modeset follows */
+   skl_set_cdclk(dev_priv, cdclk);
 
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5995,7 +5999,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 {
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
-   int freq = dev_priv->skl_boot_cdclk;
+   int freq = dev_priv->cdclk_freq;
 
/*
 * check if the pre-os intialized the display
@@ -6019,11 +6023,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
/* All well; nothing to sanitize */
return false;
 sanitize:
-   /*

[Intel-gfx] [PATCH V8] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

[clinton . a . taylor]

From: Clint Taylor 

WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
is enabled when the cdclk is less then required. DP connected to DDI2
and HPD on either port works correctly.

Set cdclk based on the max required pixel clock based on VCO
selected. Track boot vco instead of boot cdclk.

The vco is now tracked at the atomic level and all CRTCs updated if
the required vco is changed. Not tested with eDP v1.4 panels that
require 8640 vco due to availability.

V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.
V4: track target vco is atomic state. modeset all CRTCs if vco changes
V5: rename atomic variable, cleaner if/else logic, use existing vco if
  encoder does not return a new vco value. check_patch.pl cleanup
V6: simplify logic in intel_modeset_checks.
V7: reorder an IF for readability and whitespace fix.
V8: use dev_cdclk for tracking new cdclk during atomic

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_drv.h  |2 +-
 drivers/gpu/drm/i915/intel_ddi.c |2 +-
 drivers/gpu/drm/i915/intel_display.c |  109 +-
 drivers/gpu/drm/i915/intel_dp.c  |5 ++
 drivers/gpu/drm/i915/intel_drv.h |5 ++
 5 files changed, 105 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f37ac12..83bb3fd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1833,7 +1833,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 
unsigned int fsb_freq, mem_freq, is_ddr3;
-   unsigned int skl_boot_cdclk;
+   unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int rawclk_freq;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 62de9f4..f628647 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3003,7 +3003,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
int cdclk_freq;
 
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
-   dev_priv->skl_boot_cdclk = cdclk_freq;
+   dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
if (skl_sanitize_cdclk(dev_priv))
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 62d36a7..10cdeb7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5811,7 +5811,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
return (freq - 1000) / 500;
 }
 
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
 {
unsigned int i;
 
@@ -5969,17 +5969,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 
 void skl_init_cdclk(struct drm_i915_private *dev_priv)
 {
-   unsigned int required_vco;
+   unsigned int cdclk;
 
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
-   required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
-   skl_dpll0_enable(dev_priv, required_vco);
+   if (dev_priv->skl_vco_freq != 8640)
+   dev_priv->skl_vco_freq = 8100;
+   skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
+   cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
+   } else {
+   cdclk = dev_priv->cdclk_freq;
}
 
-   /* set CDCLK to the frequency the BIOS chose */
-   skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+   /* set CDCLK to the lowest frequency, Modeset follows */
+   skl_set_cdclk(dev_priv, cdclk);
 
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5995,7 +5999,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 {
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
-   int freq = dev_priv->skl_boot_cdclk;
+   int freq = dev_priv->cdclk_freq;
 
/*
 * check if the pre-os intialized the display
@@ -6019,11 +6023,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
/* All well; nothing to sanitize */
return false;
 sanitize:
-   /*
-* As of now initialize with max cdclk till
-* we get dynamic cdclk support
-* 

[Intel-gfx] [PATCH V7] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

[clinton . a . taylor]

From: Clint Taylor 

Set cdclk based on the max required pixel clock based on VCO
selected. Track boot vco instead of boot cdclk.

The vco is now tracked at the atomic level and all CRTCs updated if
the required vco is changed. Not tested with eDP v1.4 panels that
require 8640 vco due to availability.

V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.
V4: track target vco is atomic state. modeset all CRTCs if vco changes
V5: rename atomic variable, cleaner if/else logic, use existing vco if
encoder does not return a new vco value. check_patch.pl cleanup
V6: simplify logic in intel_modeset_checks.
V7: reorder an IF for readability and whitespace fix.

Signed-off-by: Clint Taylor 
Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= 
---
 drivers/gpu/drm/i915/i915_drv.h  |2 +-
 drivers/gpu/drm/i915/intel_ddi.c |2 +-
 drivers/gpu/drm/i915/intel_display.c |  102 +-
 drivers/gpu/drm/i915/intel_dp.c  |6 +-
 drivers/gpu/drm/i915/intel_drv.h |4 ++
 5 files changed, 99 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8216665..f65dd1a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1822,7 +1822,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 
unsigned int fsb_freq, mem_freq, is_ddr3;
-   unsigned int skl_boot_cdclk;
+   unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int hpll_freq;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6d5b09f..285adab 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
int cdclk_freq;
 
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
-   dev_priv->skl_boot_cdclk = cdclk_freq;
+   dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
if (skl_sanitize_cdclk(dev_priv))
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 9e2273b..e118ce0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
return (freq - 1000) / 500;
 }
 
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
 {
unsigned int i;
 
@@ -5821,17 +5821,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 
 void skl_init_cdclk(struct drm_i915_private *dev_priv)
 {
-   unsigned int required_vco;
+   unsigned int cdclk;
 
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
-   required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
-   skl_dpll0_enable(dev_priv, required_vco);
+   if (dev_priv->skl_vco_freq != 8640)
+   dev_priv->skl_vco_freq = 8100;
+   skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
+   cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
+   } else {
+   cdclk = dev_priv->cdclk_freq;
}
 
-   /* set CDCLK to the frequency the BIOS chose */
-   skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+   /* set CDCLK to the lowest frequency, Modeset follows */
+   skl_set_cdclk(dev_priv, cdclk);
 
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5847,7 +5851,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 {
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
-   int freq = dev_priv->skl_boot_cdclk;
+   int freq = dev_priv->cdclk_freq;
 
/*
 * check if the pre-os intialized the display
@@ -5871,11 +5875,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
/* All well; nothing to sanitize */
return false;
 sanitize:
-   /*
-* As of now initialize with max cdclk till
-* we get dynamic cdclk support
-* */
-   dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
+
skl_init_cdclk(dev_priv);
 
/* we did have to sanitize */
@@ -9845,6 +9845,68 @@ static void broadwell_modeset_commit_cdclk(struct 
drm_atomic_state *old_state)
   

[Intel-gfx] [PATCH V6] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

[clinton . a . taylor]

From: Clint Taylor 

Set cdclk based on the max required pixel clock based on VCO
selected. Track boot vco instead of boot cdclk.

The vco is now tracked at the atomic level and all CRTCs updated if
the required vco is changed. Not tested with eDP v1.4 panels that
require 8640 vco due to availability.

V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.
V4: track target vco is atomic state. modeset all CRTCs if vco changes
V5: rename atomic variable, cleaner if/else logic, use existing vco if
encoder does not return a new vco value. check_patch.pl cleanup
V6: simplify logic in intel_modeset_checks.

Signed-off-by: Clint Taylor 
Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= 
---
 drivers/gpu/drm/i915/i915_drv.h  |2 +-
 drivers/gpu/drm/i915/intel_ddi.c |2 +-
 drivers/gpu/drm/i915/intel_display.c |  102 +-
 drivers/gpu/drm/i915/intel_dp.c  |6 +-
 drivers/gpu/drm/i915/intel_drv.h |4 ++
 5 files changed, 99 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8216665..f65dd1a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1822,7 +1822,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 
unsigned int fsb_freq, mem_freq, is_ddr3;
-   unsigned int skl_boot_cdclk;
+   unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int hpll_freq;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6d5b09f..285adab 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
int cdclk_freq;
 
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
-   dev_priv->skl_boot_cdclk = cdclk_freq;
+   dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
if (skl_sanitize_cdclk(dev_priv))
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 9e2273b..124cc4c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
return (freq - 1000) / 500;
 }
 
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
 {
unsigned int i;
 
@@ -5821,17 +5821,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 
 void skl_init_cdclk(struct drm_i915_private *dev_priv)
 {
-   unsigned int required_vco;
+   unsigned int cdclk;
 
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
-   required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
-   skl_dpll0_enable(dev_priv, required_vco);
+   if (dev_priv->skl_vco_freq != 8640)
+   dev_priv->skl_vco_freq = 8100;
+   skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
+   cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
+   } else {
+   cdclk = dev_priv->cdclk_freq;
}
 
-   /* set CDCLK to the frequency the BIOS chose */
-   skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+   /* set CDCLK to the lowest frequency, Modeset follows */
+   skl_set_cdclk(dev_priv, cdclk);
 
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5847,7 +5851,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 {
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
-   int freq = dev_priv->skl_boot_cdclk;
+   int freq = dev_priv->cdclk_freq;
 
/*
 * check if the pre-os intialized the display
@@ -5871,11 +5875,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
/* All well; nothing to sanitize */
return false;
 sanitize:
-   /*
-* As of now initialize with max cdclk till
-* we get dynamic cdclk support
-* */
-   dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
+
skl_init_cdclk(dev_priv);
 
/* we did have to sanitize */
@@ -9845,6 +9845,68 @@ static void broadwell_modeset_commit_cdclk(struct 
drm_atomic_state *old_state)
broadwell_set_cdclk(dev, req_cdclk);
 }
 

[Intel-gfx] [PATCH V5] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

[clinton . a . taylor]

From: Clint Taylor 

Set cdclk based on the max required pixel clock based on VCO
selected. Track boot vco instead of boot cdclk.

The vco is now tracked at the atomic level and all CRTCs updated if
the required vco is changed. Not tested with eDP v1.4 panels that
require 8640 vco due to availability.

V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.
V4: track target vco is atomic state. modeset all CRTCs if vco changes
V5: rename atomic variable, cleaner if/else logic, use existing vco if
encoder does not return a new vco value. check_patch.pl cleanup

Signed-off-by: Clint Taylor 
Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= 
---
 drivers/gpu/drm/i915/i915_drv.h  |2 +-
 drivers/gpu/drm/i915/intel_ddi.c |2 +-
 drivers/gpu/drm/i915/intel_display.c |  114 +-
 drivers/gpu/drm/i915/intel_dp.c  |6 +-
 drivers/gpu/drm/i915/intel_drv.h |4 ++
 5 files changed, 111 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8216665..f65dd1a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1822,7 +1822,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 
unsigned int fsb_freq, mem_freq, is_ddr3;
-   unsigned int skl_boot_cdclk;
+   unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int hpll_freq;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6d5b09f..285adab 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
int cdclk_freq;
 
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
-   dev_priv->skl_boot_cdclk = cdclk_freq;
+   dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
if (skl_sanitize_cdclk(dev_priv))
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 9e2273b..c283abd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
return (freq - 1000) / 500;
 }
 
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
 {
unsigned int i;
 
@@ -5821,17 +5821,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 
 void skl_init_cdclk(struct drm_i915_private *dev_priv)
 {
-   unsigned int required_vco;
+   unsigned int cdclk;
 
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
-   required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
-   skl_dpll0_enable(dev_priv, required_vco);
+   if (dev_priv->skl_vco_freq != 8640)
+   dev_priv->skl_vco_freq = 8100;
+   skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
+   cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
+   } else {
+   cdclk = dev_priv->cdclk_freq;
}
 
-   /* set CDCLK to the frequency the BIOS chose */
-   skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+   /* set CDCLK to the lowest frequency, Modeset follows */
+   skl_set_cdclk(dev_priv, cdclk);
 
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5847,7 +5851,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 {
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
-   int freq = dev_priv->skl_boot_cdclk;
+   int freq = dev_priv->cdclk_freq;
 
/*
 * check if the pre-os intialized the display
@@ -5871,11 +5875,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
/* All well; nothing to sanitize */
return false;
 sanitize:
-   /*
-* As of now initialize with max cdclk till
-* we get dynamic cdclk support
-* */
-   dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
+
skl_init_cdclk(dev_priv);
 
/* we did have to sanitize */
@@ -9845,6 +9845,70 @@ static void broadwell_modeset_commit_cdclk(struct 
drm_atomic_state *old_state)
broadwell_set_cdclk(dev, req_cdclk);
 }
 
+static int skl_modeset_calc_cdclk(struct 

[Intel-gfx] [PATCH V4] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

[clinton . a . taylor]

From: Clint Taylor 

Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
to set cdclk based on the max required pixel clock based on VCO
selected.

The vco should be tracked at the atomic level and all CRTCs updated if
the required vco is changed. At this time the eDP pll is configured
inside the encoder which has no visibility into the atomic state. When
eDP v1.4 panel that require the 8640 vco are available this may need
to be investigated.

V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.
V4: track target vco is atomic state. modeset all CRTCs if vco changes

Signed-off-by: Clint Taylor 
Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= 
---
 drivers/gpu/drm/i915/i915_drv.h  |2 +-
 drivers/gpu/drm/i915/intel_ddi.c |2 +-
 drivers/gpu/drm/i915/intel_display.c |   97 +-
 drivers/gpu/drm/i915/intel_dp.c  |   10 ++--
 drivers/gpu/drm/i915/intel_drv.h |4 ++
 5 files changed, 97 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8216665..f65dd1a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1822,7 +1822,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 
unsigned int fsb_freq, mem_freq, is_ddr3;
-   unsigned int skl_boot_cdclk;
+   unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int hpll_freq;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6d5b09f..285adab 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
int cdclk_freq;
 
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
-   dev_priv->skl_boot_cdclk = cdclk_freq;
+   dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
if (skl_sanitize_cdclk(dev_priv))
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 9e2273b..ef4ac34 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
return (freq - 1000) / 500;
 }
 
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
 {
unsigned int i;
 
@@ -5821,17 +5821,17 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 
 void skl_init_cdclk(struct drm_i915_private *dev_priv)
 {
-   unsigned int required_vco;
-
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
-   required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
-   skl_dpll0_enable(dev_priv, required_vco);
+   if (dev_priv->skl_vco_freq != 8640) {
+   dev_priv->skl_vco_freq = 8100;
+   }
+   skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
}
 
/* set CDCLK to the frequency the BIOS chose */
-   skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+   skl_set_cdclk(dev_priv, (dev_priv->skl_vco_freq == 8100) ? 337500 : 
308570 );
 
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5847,7 +5847,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 {
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
-   int freq = dev_priv->skl_boot_cdclk;
+   int freq = dev_priv->cdclk_freq;
 
/*
 * check if the pre-os intialized the display
@@ -5871,11 +5871,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
/* All well; nothing to sanitize */
return false;
 sanitize:
-   /*
-* As of now initialize with max cdclk till
-* we get dynamic cdclk support
-* */
-   dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
+   
skl_init_cdclk(dev_priv);
 
/* we did have to sanitize */
@@ -9845,6 +9841,68 @@ static void broadwell_modeset_commit_cdclk(struct 
drm_atomic_state *old_state)
broadwell_set_cdclk(dev, req_cdclk);
 }
 
+static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+   struct drm_i915_private *dev_priv = to_i915(state->dev);
+   int max_pixclk = 

[Intel-gfx] [PATCH V3] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

[clinton . a . taylor]

From: Clint Taylor 

Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
to set cdclk based on the max required pixel clock based on VCO
selected.

The vco should be tracked at the atomic level and all CRTCs updated if
the required vco is changed. At this time the eDP pll is configured
inside the encoder which has no visibility into the atomic state. When
eDP v1.4 panel that require the 8640 vco are available this may need
to be investigated.

V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.

Signed-off-by: Clint Taylor 
Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= 

---
 drivers/gpu/drm/i915/i915_drv.h  |2 +-
 drivers/gpu/drm/i915/intel_ddi.c |2 +-
 drivers/gpu/drm/i915/intel_display.c |   83 +-
 drivers/gpu/drm/i915/intel_dp.c  |9 +++-
 drivers/gpu/drm/i915/intel_drv.h |1 +
 5 files changed, 81 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8216665..f65dd1a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1822,7 +1822,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 
unsigned int fsb_freq, mem_freq, is_ddr3;
-   unsigned int skl_boot_cdclk;
+   unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int hpll_freq;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6d5b09f..285adab 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
int cdclk_freq;
 
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
-   dev_priv->skl_boot_cdclk = cdclk_freq;
+   dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
if (skl_sanitize_cdclk(dev_priv))
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 9e2273b..372a68f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
return (freq - 1000) / 500;
 }
 
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
 {
unsigned int i;
 
@@ -5821,17 +5821,17 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 
 void skl_init_cdclk(struct drm_i915_private *dev_priv)
 {
-   unsigned int required_vco;
-
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
-   required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
-   skl_dpll0_enable(dev_priv, required_vco);
+   if (dev_priv->skl_vco_freq != 8640) {
+   dev_priv->skl_vco_freq = 8100;
+   }
+   skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
}
 
/* set CDCLK to the frequency the BIOS chose */
-   skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+   skl_set_cdclk(dev_priv, (dev_priv->skl_vco_freq == 8100) ? 337500 : 
308570 );
 
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5847,7 +5847,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 {
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
-   int freq = dev_priv->skl_boot_cdclk;
+   int freq = dev_priv->cdclk_freq;
 
/*
 * check if the pre-os intialized the display
@@ -5871,11 +5871,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
/* All well; nothing to sanitize */
return false;
 sanitize:
-   /*
-* As of now initialize with max cdclk till
-* we get dynamic cdclk support
-* */
-   dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
+   
skl_init_cdclk(dev_priv);
 
/* we did have to sanitize */
@@ -9845,6 +9841,64 @@ static void broadwell_modeset_commit_cdclk(struct 
drm_atomic_state *old_state)
broadwell_set_cdclk(dev, req_cdclk);
 }
 
+static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+   struct drm_i915_private *dev_priv = to_i915(state->dev);
+   int max_pixclk = ilk_max_pixel_rate(state);
+   int cdclk;
+   
+   /*
+   * FIXME should also 

[Intel-gfx] [PATCH] drm/i915: reboot notifier delay for eDP panels

[clinton . a . taylor]

From: Clint Taylor 

Add reboot notifier for all platforms. This guarantees T12 delay
compliance during reboot cycles when pre-os enables the panel within
500ms.

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_dp.c |   11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 796e3d3..dbbd27a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -126,6 +126,7 @@ static struct intel_dp *intel_attached_dp(struct 
drm_connector *connector)
 static void intel_dp_link_down(struct intel_dp *intel_dp);
 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
+static void edp_panel_off(struct intel_dp *intel_dp);
 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 static void vlv_steal_power_sequencer(struct drm_device *dev,
  enum pipe pipe);
@@ -596,6 +597,10 @@ static int edp_notify_handler(struct notifier_block *this, 
unsigned long code,
I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
msleep(intel_dp->panel_power_cycle_delay);
}
+   else
+   {
+   edp_panel_off(intel_dp);
+   }
 
pps_unlock(intel_dp);
 
@@ -5796,10 +5801,10 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
}
mutex_unlock(>mode_config.mutex);
 
-   if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
-   intel_dp->edp_notifier.notifier_call = edp_notify_handler;
-   register_reboot_notifier(_dp->edp_notifier);
+   intel_dp->edp_notifier.notifier_call = edp_notify_handler;
+   register_reboot_notifier(_dp->edp_notifier);
 
+   if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
/*
 * Figure out the current pipe for the initial backlight setup.
 * If the current pipe isn't valid, try the PPS pipe, and if 
that
-- 
1.7.9.5

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[Intel-gfx] [PATCH] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

[clinton . a . taylor]

From: Clint Taylor 

Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
to set cdclk based on the max required pixel clock based on VCO
selected.

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/i915_drv.h  |2 +-
 drivers/gpu/drm/i915/intel_ddi.c |2 +-
 drivers/gpu/drm/i915/intel_display.c |   83 +-
 drivers/gpu/drm/i915/intel_dp.c  |9 +++-
 drivers/gpu/drm/i915/intel_drv.h |1 +
 5 files changed, 81 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f1a8a53..3ff5abd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1777,7 +1777,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 
unsigned int fsb_freq, mem_freq, is_ddr3;
-   unsigned int skl_boot_cdclk;
+   unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int hpll_freq;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 5d20c64..b787d02 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3019,7 +3019,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
int cdclk_freq;
 
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
-   dev_priv->skl_boot_cdclk = cdclk_freq;
+   dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
if (skl_sanitize_cdclk(dev_priv))
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 2e8d1a8..852dd08 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5671,7 +5671,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
return (freq - 1000) / 500;
 }
 
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
 {
unsigned int i;
 
@@ -5829,17 +5829,17 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 
 void skl_init_cdclk(struct drm_i915_private *dev_priv)
 {
-   unsigned int required_vco;
-
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
-   required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
-   skl_dpll0_enable(dev_priv, required_vco);
+   if (dev_priv->skl_vco_freq != 8640) {
+   dev_priv->skl_vco_freq = 8100;
+   }
+   skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
}
 
/* set CDCLK to the frequency the BIOS chose */
-   skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+   skl_set_cdclk(dev_priv, (dev_priv->skl_vco_freq == 8100) ? 337500 : 
308570 );
 
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5855,7 +5855,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 {
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
-   int freq = dev_priv->skl_boot_cdclk;
+   int freq = dev_priv->cdclk_freq;
 
/*
 * check if the pre-os intialized the display
@@ -5879,11 +5879,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
/* All well; nothing to sanitize */
return false;
 sanitize:
-   /*
-* As of now initialize with max cdclk till
-* we get dynamic cdclk support
-* */
-   dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
+
skl_init_cdclk(dev_priv);
 
/* we did have to sanitize */
@@ -9805,6 +9801,64 @@ static void broadwell_modeset_commit_cdclk(struct 
drm_atomic_state *old_state)
broadwell_set_cdclk(dev, req_cdclk);
 }
 
+static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+   struct drm_i915_private *dev_priv = to_i915(state->dev);
+   int max_pixclk = ilk_max_pixel_rate(state);
+   int cdclk;
+   
+   /*
+   * FIXME should also account for plane ratio
+   * once 64bpp pixel formats are supported.
+   */
+
+   if (dev_priv->skl_vco_freq == 8640) {
+   /* vco 8640 */
+   if (max_pixclk > 54)
+   cdclk = 617140;
+   else if (max_pixclk > 432000)
+   cdclk = 54;
+   else if (max_pixclk > 308570)
+   cdclk = 432000;
+   else
+   cdclk = 308570;
+   }
+   else {
+   /* VCO 8100 */
+   if (max_pixclk > 

[Intel-gfx] [PATCH] drm/i915/skl: CDCLK change during modeset based on VCO in use.

[clinton . a . taylor]

From: Clint Taylor 

Add SKL and KBL cdclk changes during modeset. Taking into account new
linkrates available using 8640 VCO.

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_display.c |   68 ++
 1 file changed, 68 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 2d7ea95..bed03cb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9727,6 +9727,69 @@ static void broadwell_modeset_commit_cdclk(struct 
drm_atomic_state *old_state)
broadwell_set_cdclk(dev, req_cdclk);
 }
 
+static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+   struct drm_i915_private *dev_priv = to_i915(state->dev);
+   int max_pixclk = ilk_max_pixel_rate(state);
+   int cdclk;
+   uint32_t linkrate;
+
+   linkrate = (I915_READ(DPLL_CTRL1) &
+   DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
+
+   /*
+   * FIXME should also account for plane ratio
+   * once 64bpp pixel formats are supported.
+   */
+
+   if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
+   linkrate == DPLL_CTRL1_LINK_RATE_1080) {
+   /* vco 8640 */
+   if (max_pixclk > 54)
+   cdclk = 617140;
+   else if (max_pixclk > 432000)
+   cdclk = 54;
+   else if (max_pixclk > 308570)
+   cdclk = 432000;
+   else
+   cdclk = 308570;
+   }
+   else {
+   /* VCO 8100 */
+   if (max_pixclk > 54)
+   cdclk = 675000;
+   else if (max_pixclk > 45)
+   cdclk = 54;
+   else if (max_pixclk > 337500)
+   cdclk = 45;
+   else
+   cdclk = 337500;
+   }
+
+   /*
+* FIXME move the cdclk caclulation to
+* compute_config() so we can fail gracefully.
+*/
+   if (cdclk > dev_priv->max_cdclk_freq) {
+   DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
+ cdclk, dev_priv->max_cdclk_freq);
+   cdclk = dev_priv->max_cdclk_freq;
+   }
+
+   to_intel_atomic_state(state)->cdclk = cdclk;
+
+   return 0;
+}
+
+static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
+{
+   struct drm_device *dev = old_state->dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
+
+   skl_set_cdclk(dev_priv, req_cdclk);
+}
+
 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
  struct intel_crtc_state *crtc_state)
 {
@@ -14831,6 +14894,11 @@ static void intel_init_display(struct drm_device *dev)
broxton_modeset_commit_cdclk;
dev_priv->display.modeset_calc_cdclk =
broxton_modeset_calc_cdclk;
+   } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
+   dev_priv->display.modeset_commit_cdclk =
+   skl_modeset_commit_cdclk;
+   dev_priv->display.modeset_calc_cdclk =
+   skl_modeset_calc_cdclk;
}
 
switch (INTEL_INFO(dev)->gen) {
-- 
1.7.9.5

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[Intel-gfx] [PATCH] drm/i915: 4K audio N value incorrect at 29.97 and 23.98 refresh rate

[clinton . a . taylor]

From: Clint Taylor 

The TMDS_296M define was computing as 296704 but the mode->clock is
296700 as defined by EDID. Adjusted define to allow correct detection
of the need to program the correct N value for 29.97 and 23.98 refresh
rate.

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_audio.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index 56c2f54..419c979 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -75,7 +75,7 @@ static const struct {
 
 /* HDMI N/CTS table */
 #define TMDS_297M 297000
-#define TMDS_296M DIV_ROUND_UP(297000 * 1000, 1001)
+#define TMDS_296M 296700
 static const struct {
int sample_rate;
int clock;
-- 
1.7.9.5

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[Intel-gfx] [PATCH] drm/i915: Allow minimum brightness upon backlight enable

[clinton . a . taylor]

From: Clint Taylor 

backlight minimum is a valid value so you don't need to set maximum.

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_panel.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_panel.c 
b/drivers/gpu/drm/i915/intel_panel.c
index 4d28c7b..d509904 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1069,7 +1069,7 @@ void intel_panel_enable_backlight(struct intel_connector 
*connector)
 
WARN_ON(panel->backlight.max == 0);
 
-   if (panel->backlight.level <= panel->backlight.min) {
+   if (panel->backlight.level < panel->backlight.min) {
panel->backlight.level = panel->backlight.max;
if (panel->backlight.device)
panel->backlight.device->props.brightness =
-- 
1.7.9.5

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[Intel-gfx] [PATCH] drm/i915: eDP HPD connected check to reduce T3 time

[clinton . a . taylor]

From: Clint Taylor 

To reduce eDP T3 time check for digital port connected instead of
msleep. Maintain VBT time if HPD is not asserted on the port.

Current eDP T3 time is an msleep for the panel_power_up time specified
in VBT. The eDP specification allows maximum T3 time of 200ms.
Typically panels raise HPD from 70ms-105ms and are ready for AUX traffic
 and training. Reading HPD will reduce power-on and resume times by over
100ms on systems with eDP HPD connected.

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/intel_dp.c |   13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 77e4115..7caf3ab 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -129,6 +129,8 @@ static void edp_panel_vdd_off(struct intel_dp *intel_dp, 
bool sync);
 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 static void vlv_steal_power_sequencer(struct drm_device *dev,
  enum pipe pipe);
+static bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
+struct intel_digital_port *port);
 
 static unsigned int intel_dp_unused_lane_mask(int lane_count)
 {
@@ -1772,6 +1774,7 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
u32 pp;
u32 pp_stat_reg, pp_ctrl_reg;
bool need_to_disable = !intel_dp->want_panel_vdd;
+   int i, step = 0;
 
lockdep_assert_held(_priv->pps_mutex);
 
@@ -1809,7 +1812,15 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
if (!edp_have_panel_power(intel_dp)) {
DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
  port_name(intel_dig_port->port));
-   msleep(intel_dp->panel_power_up_delay);
+   step = intel_dp->panel_power_up_delay / 10;
+   for (i=0; i < intel_dp->panel_power_up_delay; i+=step) {
+   if (intel_digital_port_connected(dev_priv, 
intel_dig_port)) {
+   DRM_DEBUG_KMS("Port %c HPD detected\n",
+ port_name(intel_dig_port->port));
+   break;
+   }
+   msleep(10);
+   }
}
 
return need_to_disable;
-- 
1.7.9.5

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[Intel-gfx] [PATCH] drm/i915/chv: Remove DPIO force latency causing interpair skew issue

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

Latest version of the CHV DPIO programming notes no longer requires writes
to TX DW 11 to fix a +2UI interpair skew issue. The current code from
April 2014 was actually causing additional skew issues between all
TMDS pairs.

Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
---
 drivers/gpu/drm/i915/intel_hdmi.c |5 -
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 26222e6..3cef326 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1515,11 +1515,6 @@ static void chv_hdmi_pre_enable(struct intel_encoder 
*encoder)
 
/* Program Tx latency optimal setting */
for (i = 0; i  4; i++) {
-   /* Set the latency optimal bit */
-   data = (i == 1) ? 0x0 : 0x6;
-   vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
-   data  DPIO_FRC_LATENCY_SHFIT);
-
/* Set the upar bit */
data = (i == 1) ? 0x0 : 0x1;
vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
-- 
1.7.9.5

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[Intel-gfx] [PATCH v2] drm/i915/chv: Remove DPIO force latency causing interpair skew issue

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

Latest version of the CHV DPIO programming notes no longer requires writes
to TX DW 11 to fix a +2UI interpair skew issue. The current code from
April 2014 was actually causing additional skew issues between all
TMDS pairs.

ver2: added same treatment to intel_dp.c based on Ville's testing.

Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= ville.syrj...@linux.intel.com
Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
---
 drivers/gpu/drm/i915/intel_dp.c   |5 -
 drivers/gpu/drm/i915/intel_hdmi.c |5 -
 2 files changed, 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1b87969..f106763 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2740,11 +2740,6 @@ static void chv_pre_enable_dp(struct intel_encoder 
*encoder)
 
/* Program Tx lane latency optimal setting*/
for (i = 0; i  4; i++) {
-   /* Set the latency optimal bit */
-   data = (i == 1) ? 0x0 : 0x6;
-   vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
-   data  DPIO_FRC_LATENCY_SHFIT);
-
/* Set the upar bit */
data = (i == 1) ? 0x0 : 0x1;
vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 26222e6..3cef326 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1515,11 +1515,6 @@ static void chv_hdmi_pre_enable(struct intel_encoder 
*encoder)
 
/* Program Tx latency optimal setting */
for (i = 0; i  4; i++) {
-   /* Set the latency optimal bit */
-   data = (i == 1) ? 0x0 : 0x6;
-   vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
-   data  DPIO_FRC_LATENCY_SHFIT);
-
/* Set the upar bit */
data = (i == 1) ? 0x0 : 0x1;
vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
-- 
1.7.9.5

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[Intel-gfx] [PATCH] drm/i915/chv: Enable HDMI Clock recovery for Pipe C

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

Added PIPE C register support for CHV audio programming.

Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
---
 drivers/gpu/drm/i915/i915_reg.h |   18 --
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dc03fac..3d5813a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6189,14 +6189,18 @@ enum punit_power_well {
 
 #define _VLV_HDMIW_HDMIEDID_A  (VLV_DISPLAY_BASE + 0x62050)
 #define _VLV_HDMIW_HDMIEDID_B  (VLV_DISPLAY_BASE + 0x62150)
-#define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
+#define _CHV_HDMIW_HDMIEDID_C  (VLV_DISPLAY_BASE + 0x62250)
+#define VLV_HDMIW_HDMIEDID(pipe) _PIPE3(pipe, \
_VLV_HDMIW_HDMIEDID_A, \
-   _VLV_HDMIW_HDMIEDID_B)
+   _VLV_HDMIW_HDMIEDID_B, \
+   _CHV_HDMIW_HDMIEDID_C)
 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
-#define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
+#define _CHV_AUD_CNTL_ST_C (VLV_DISPLAY_BASE + 0x622B4)
+#define VLV_AUD_CNTL_ST(pipe) _PIPE3(pipe, \
_VLV_AUD_CNTL_ST_A, \
-   _VLV_AUD_CNTL_ST_B)
+   _VLV_AUD_CNTL_ST_B, \
+   _CHV_AUD_CNTL_ST_C)
 #define VLV_AUD_CNTL_ST2   (VLV_DISPLAY_BASE + 0x620C0)
 
 /* These are the 4 32-bit write offset registers for each stream
@@ -6217,9 +6221,11 @@ enum punit_power_well {
_CPT_AUD_CONFIG_B)
 #define _VLV_AUD_CONFIG_A  (VLV_DISPLAY_BASE + 0x62000)
 #define _VLV_AUD_CONFIG_B  (VLV_DISPLAY_BASE + 0x62100)
-#define VLV_AUD_CFG(pipe) _PIPE(pipe, \
+#define _CHV_AUD_CONFIG_C  (VLV_DISPLAY_BASE + 0x62200)
+#define VLV_AUD_CFG(pipe) _PIPE3(pipe, \
_VLV_AUD_CONFIG_A, \
-   _VLV_AUD_CONFIG_B)
+   _VLV_AUD_CONFIG_B, \
+   _CHV_AUD_CONFIG_C)
 
 #define   AUD_CONFIG_N_VALUE_INDEX (1  29)
 #define   AUD_CONFIG_N_PROG_ENABLE (1  28)
-- 
1.7.9.5

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[Intel-gfx] [PATCH] drm/i915/chv: Enable AVI, SPD and HDMI infoframes for CHV.

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

CHV infoframes were not being enabled.

Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
---
 drivers/gpu/drm/i915/intel_hdmi.c |7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index ec87333..3abc200 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1461,10 +1461,13 @@ static void chv_hdmi_post_disable(struct intel_encoder 
*encoder)
 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
 {
struct intel_digital_port *dport = enc_to_dig_port(encoder-base);
+   struct intel_hdmi *intel_hdmi = dport-hdmi;
struct drm_device *dev = encoder-base.dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc =
to_intel_crtc(encoder-base.crtc);
+   struct drm_display_mode *adjusted_mode =
+   intel_crtc-config.adjusted_mode;
enum dpio_channel ch = vlv_dport_to_channel(dport);
int pipe = intel_crtc-pipe;
int data, i;
@@ -1589,6 +1592,10 @@ static void chv_hdmi_pre_enable(struct intel_encoder 
*encoder)
 
mutex_unlock(dev_priv-dpio_lock);
 
+   intel_hdmi-set_infoframes(encoder-base,
+  intel_crtc-config.has_hdmi_sink,
+  adjusted_mode);
+
intel_enable_hdmi(encoder);
 
vlv_wait_port_ready(dev_priv, dport);
-- 
1.7.9.5

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[Intel-gfx] [PATCH v4] drm/i915: Enable pixel replicated modes on BDW and HSW.

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

Haswell and later silicon has added a new pixel replication register
to the pipe timings for each transcoder. Now in addition to the
DPLL_A_MD register for the pixel clock double, we also need to write
to the TRANS_MULT_n (0x6002c) register to double the pixel data. Writing
to the DPLL only double the pixel clock.

ver2: Macro name change from MULTIPLY to PIPE_MULTI. (Daniel)
ver3: Do not set pixel multiplier if transcoder is eDP (Ville)
ver4: Macro name change to PIPE_MULT and default else pixel_multiplier

Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= ville.syrj...@linux.intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Jani Nikula jani.nik...@intel.com

Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
---
 drivers/gpu/drm/i915/i915_reg.h  |3 +++
 drivers/gpu/drm/i915/intel_display.c |   13 -
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ad8179b..d428f7a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2443,6 +2443,7 @@ enum punit_power_well {
 #define _PIPEASRC  0x6001c
 #define _BCLRPAT_A 0x60020
 #define _VSYNCSHIFT_A  0x60028
+#define _PIPE_MULT_A   0x6002c
 
 /* Pipe B timing regs */
 #define _HTOTAL_B  0x61000
@@ -2454,6 +2455,7 @@ enum punit_power_well {
 #define _PIPEBSRC  0x6101c
 #define _BCLRPAT_B 0x61020
 #define _VSYNCSHIFT_B  0x61028
+#define _PIPE_MULT_B   0x6102c
 
 #define TRANSCODER_A_OFFSET 0x6
 #define TRANSCODER_B_OFFSET 0x61000
@@ -2474,6 +2476,7 @@ enum punit_power_well {
 #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
 #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
 #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
+#define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A)
 
 /* HSW+ eDP PSR registers */
 #define EDP_PSR_BASE(dev)   (IS_HASWELL(dev) ? 0x64800 : 
0x6f800)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 858011d..617dad6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4168,6 +4168,11 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 
intel_set_pipe_timings(intel_crtc);
 
+   if (intel_crtc-config.cpu_transcoder != TRANSCODER_EDP) {
+   I915_WRITE(PIPE_MULT(intel_crtc-config.cpu_transcoder),
+   intel_crtc-config.pixel_multiplier - 1);
+   }
+
if (intel_crtc-config.has_pch_encoder) {
intel_cpu_transcoder_set_m_n(intel_crtc,
 intel_crtc-config.fdi_m_n, NULL);
@@ -7853,7 +7858,13 @@ static bool haswell_get_pipe_config(struct intel_crtc 
*crtc,
pipe_config-ips_enabled = hsw_crtc_supports_ips(crtc) 
(I915_READ(IPS_CTL)  IPS_ENABLE);
 
-   pipe_config-pixel_multiplier = 1;
+   if (pipe_config-cpu_transcoder != TRANSCODER_EDP) {
+   pipe_config-pixel_multiplier =
+   I915_READ(PIPE_MULT(pipe_config-cpu_transcoder)) + 1;
+   }
+   else {
+   pipe_config-pixel_multiplier = 1;
+   }
 
return true;
 }
-- 
1.7.9.5

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[Intel-gfx] [PATCH] drm/edid: Add missing interlaced flag to 576i@100 modes.

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

CEA VICs 44 and 45 were missing DRM_MODE_FLAG_INTERLACE.

Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
---
 drivers/gpu/drm/drm_edid.c |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 1bdbfd0..3bf9991 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -841,13 +841,13 @@ static const struct drm_display_mode edid_cea_modes[] = {
{ DRM_MODE(720x576i, DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
   795, 864, 0, 576, 580, 586, 625, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
-   DRM_MODE_FLAG_DBLCLK),
+   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
/* 45 - 720(1440)x576i@100Hz */
{ DRM_MODE(720x576i, DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
   795, 864, 0, 576, 580, 586, 625, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
-   DRM_MODE_FLAG_DBLCLK),
+   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
/* 46 - 1920x1080i@120Hz */
{ DRM_MODE(1920x1080i, DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
-- 
1.7.9.5

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[Intel-gfx] [PATCH v2] drm/i915: Audio N value computed for pixel doubled modes

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

HDMI audio clock config was incorrectly choosing the default for
pixel doubled interlaced modes. The table was missing pixel clock
values 13.500 (27.000) and 13.513 (27.027). Luckily the default N
value for 25.200 is the same N value for both 27MHz pixel clocks,
a warning message was being printed with drm.debug set.

ver2: Use 13500 * 1001 / 1000 instead of 13513 constant.

Cc: Jani Nikula jani.nikula at intel.com

Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
---
 drivers/gpu/drm/i915/intel_display.c |2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 858011d..e76a4106 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7872,6 +7872,8 @@ static struct {
{ 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
{ DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 
},
{ 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
+   { 13500, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
+   { 13500 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
 };
 
 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
-- 
1.7.9.5

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[Intel-gfx] [PATCH v3] drm/i915: Enable pixel replicated modes on BDW and HSW.

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

Haswell and later silicon has added a new pixel replication register
to the pipe timings for each transcoder. Now in addition to the
DPLL_A_MD register for the pixel clock double, we also need to write
to the TRANS_MULT_n (0x6002c) register to double the pixel data. Writing
to the DPLL only double the pixel clock.

ver2: Macro name change from MULTIPLY to PIPE_MULTI. (Daniel)
ver3: Do not set pixel multiplier if transcoder is eDP (Ville)

Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= ville.syrj...@linux.intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Jani Nikula jani.nik...@intel.com

Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
---
 drivers/gpu/drm/i915/i915_reg.h  |3 +++
 drivers/gpu/drm/i915/intel_display.c |   10 +-
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ad8179b..035d58c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2443,6 +2443,7 @@ enum punit_power_well {
 #define _PIPEASRC  0x6001c
 #define _BCLRPAT_A 0x60020
 #define _VSYNCSHIFT_A  0x60028
+#define _MULTIPLY_A0x6002c
 
 /* Pipe B timing regs */
 #define _HTOTAL_B  0x61000
@@ -2454,6 +2455,7 @@ enum punit_power_well {
 #define _PIPEBSRC  0x6101c
 #define _BCLRPAT_B 0x61020
 #define _VSYNCSHIFT_B  0x61028
+#define _MULTIPLY_B0x6102c
 
 #define TRANSCODER_A_OFFSET 0x6
 #define TRANSCODER_B_OFFSET 0x61000
@@ -2474,6 +2476,7 @@ enum punit_power_well {
 #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
 #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
 #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
+#define PIPE_MULTI(trans) _TRANSCODER2(trans, _MULTIPLY_A)
 
 /* HSW+ eDP PSR registers */
 #define EDP_PSR_BASE(dev)   (IS_HASWELL(dev) ? 0x64800 : 
0x6f800)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 858011d..f8c1f11 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4168,6 +4168,11 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 
intel_set_pipe_timings(intel_crtc);
 
+   if (intel_crtc-config.cpu_transcoder != TRANSCODER_EDP) {
+   I915_WRITE(PIPE_MULTI(intel_crtc-config.cpu_transcoder),
+   intel_crtc-config.pixel_multiplier - 1);
+   }
+
if (intel_crtc-config.has_pch_encoder) {
intel_cpu_transcoder_set_m_n(intel_crtc,
 intel_crtc-config.fdi_m_n, NULL);
@@ -7853,7 +7858,10 @@ static bool haswell_get_pipe_config(struct intel_crtc 
*crtc,
pipe_config-ips_enabled = hsw_crtc_supports_ips(crtc) 
(I915_READ(IPS_CTL)  IPS_ENABLE);
 
-   pipe_config-pixel_multiplier = 1;
+   if (pipe_config-cpu_transcoder != TRANSCODER_EDP) {
+   pipe_config-pixel_multiplier =
+   I915_READ(PIPE_MULTI(pipe_config-cpu_transcoder)) + 1;
+   }
 
return true;
 }
-- 
1.7.9.5

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[Intel-gfx] [PATCH] drm/i915: Audio N value computed for pixel doubled modes

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

HDMI audio clock config was incorrectly choosing the default for
pixel doubled interlaced modes. The table was missing pixel clock
values 13.500 (27.000) and 13.513 (27.027). Luckily the default N
value for 25.200 is the same N value for both 27MHz pixel clocks,
a warning message was being printed with drm.debug set.

Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
---
 drivers/gpu/drm/i915/intel_display.c |2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 858011d..6625eb5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7872,6 +7872,8 @@ static struct {
{ 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
{ DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 
},
{ 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
+   { 13500, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
+   { 13513, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
 };
 
 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
-- 
1.7.9.5

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[Intel-gfx] [PATCH] drm/i915/hdmi: Compute port_clock for 27.027 pixel replicated modes

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

port_clock was being incorrectly computed and WRPLL was incorrectly
programmed for pixel doubled modes using a 27.027MHz pixel clock.
port_clock was set to 27.026 resulting in an output pixel clock
matching 27.000MHz. Since there is no way to correctly half the 27.027
frequency as an integer just set port_clock to 27027 for these modes.

Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
---
 drivers/gpu/drm/i915/intel_hdmi.c |5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 29ec153..a0786d6 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -933,6 +933,11 @@ bool intel_hdmi_compute_config(struct intel_encoder 
*encoder,
 
if (adjusted_mode-flags  DRM_MODE_FLAG_DBLCLK) {
pipe_config-pixel_multiplier = 2;
+
+   /* Fix up port_clock since 27027 is not divisible by 2 */
+   if (pipe_config-adjusted_mode.crtc_clock == 13513) {
+   pipe_config-port_clock = 27027;
+   }
}
 
if (intel_hdmi-color_range)
-- 
1.7.9.5

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[Intel-gfx] [PATCH v2] drm/i915: Enable pixel replicated modes on BDW and HSW.

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

Haswell and later silicon has added a new pixel replication register
to the pipe timings for each transcoder. Now in addition to the
DPLL_A_MD register for the pixel clock double, we also need to write
to the TRANS_MULT_n (0x6002c) register to double the pixel data. Writing
to the DPLL only double the pixel clock.

ver2: Macro name change from MULTIPLY to PIPE_MULTI. (Daniel)

Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Jani Nikula jani.nik...@intel.com

Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
---
 drivers/gpu/drm/i915/i915_reg.h  |3 +++
 drivers/gpu/drm/i915/intel_display.c |6 +-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ad8179b..035d58c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2443,6 +2443,7 @@ enum punit_power_well {
 #define _PIPEASRC  0x6001c
 #define _BCLRPAT_A 0x60020
 #define _VSYNCSHIFT_A  0x60028
+#define _MULTIPLY_A0x6002c
 
 /* Pipe B timing regs */
 #define _HTOTAL_B  0x61000
@@ -2454,6 +2455,7 @@ enum punit_power_well {
 #define _PIPEBSRC  0x6101c
 #define _BCLRPAT_B 0x61020
 #define _VSYNCSHIFT_B  0x61028
+#define _MULTIPLY_B0x6102c
 
 #define TRANSCODER_A_OFFSET 0x6
 #define TRANSCODER_B_OFFSET 0x61000
@@ -2474,6 +2476,7 @@ enum punit_power_well {
 #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
 #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
 #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
+#define PIPE_MULTI(trans) _TRANSCODER2(trans, _MULTIPLY_A)
 
 /* HSW+ eDP PSR registers */
 #define EDP_PSR_BASE(dev)   (IS_HASWELL(dev) ? 0x64800 : 
0x6f800)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 858011d..49eced4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4168,6 +4168,9 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 
intel_set_pipe_timings(intel_crtc);
 
+   I915_WRITE(PIPE_MULTI(intel_crtc-config.cpu_transcoder),
+   intel_crtc-config.pixel_multiplier - 1);
+
if (intel_crtc-config.has_pch_encoder) {
intel_cpu_transcoder_set_m_n(intel_crtc,
 intel_crtc-config.fdi_m_n, NULL);
@@ -7853,7 +7856,8 @@ static bool haswell_get_pipe_config(struct intel_crtc 
*crtc,
pipe_config-ips_enabled = hsw_crtc_supports_ips(crtc) 
(I915_READ(IPS_CTL)  IPS_ENABLE);
 
-   pipe_config-pixel_multiplier = 1;
+   pipe_config-pixel_multiplier =
+   I915_READ(PIPE_MULTI(pipe_config-cpu_transcoder)) + 1;
 
return true;
 }
-- 
1.7.9.5

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[Intel-gfx] [PATCH] drm/i915: Enable pixel replicated modes on BDW and HSW.

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

Haswell and later silicon has added a new pixel replication register
to the pipe timings for each transcoder. Now in addition to the
DPLL_A_MD register for the pixel clock double, we also need to write to
the TRANS_MULT_n (0x6002c) register to double the pixel data. Writing
to the DPLL only double the pixel clock.

Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
---
 drivers/gpu/drm/i915/i915_reg.h  |3 +++
 drivers/gpu/drm/i915/intel_display.c |6 +-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 15c0eaa..7c078d9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2431,6 +2431,7 @@ enum punit_power_well {
 #define _PIPEASRC  0x6001c
 #define _BCLRPAT_A 0x60020
 #define _VSYNCSHIFT_A  0x60028
+#define _MULTIPLY_A0x6002c
 
 /* Pipe B timing regs */
 #define _HTOTAL_B  0x61000
@@ -2442,6 +2443,7 @@ enum punit_power_well {
 #define _PIPEBSRC  0x6101c
 #define _BCLRPAT_B 0x61020
 #define _VSYNCSHIFT_B  0x61028
+#define _MULTIPLY_B0x6102c
 
 #define TRANSCODER_A_OFFSET 0x6
 #define TRANSCODER_B_OFFSET 0x61000
@@ -2462,6 +2464,7 @@ enum punit_power_well {
 #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
 #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
 #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
+#define MULTIPLY(trans) _TRANSCODER2(trans, _MULTIPLY_A)
 
 /* HSW+ eDP PSR registers */
 #define EDP_PSR_BASE(dev)   (IS_HASWELL(dev) ? 0x64800 : 
0x6f800)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index c092ff4..e58fcde 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4152,6 +4152,9 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 
intel_set_pipe_timings(intel_crtc);
 
+   I915_WRITE(MULTIPLY(intel_crtc-config.cpu_transcoder),
+   intel_crtc-config.pixel_multiplier - 1);
+
if (intel_crtc-config.has_pch_encoder) {
intel_cpu_transcoder_set_m_n(intel_crtc,
 intel_crtc-config.fdi_m_n, NULL);
@@ -7811,7 +7814,8 @@ static bool haswell_get_pipe_config(struct intel_crtc 
*crtc,
pipe_config-ips_enabled = hsw_crtc_supports_ips(crtc) 
(I915_READ(IPS_CTL)  IPS_ENABLE);
 
-   pipe_config-pixel_multiplier = 1;
+   pipe_config-pixel_multiplier =
+   I915_READ(MULTIPLY(pipe_config-cpu_transcoder)) + 1;
 
return true;
 }
-- 
1.7.9.5

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[Intel-gfx] [PATCH 2/2] drm/i915/hdmi: Enable pipe pixel replication for SD interlaced modes

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

Enable 2x pixel replication for modes the mode flag DBLCLK to double
horizontal timings and pixel clock across TMDS.

Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 drivers/gpu/drm/i915/intel_hdmi.c |   15 ---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 9169786..9695768 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -864,10 +864,15 @@ static enum drm_mode_status
 intel_hdmi_mode_valid(struct drm_connector *connector,
  struct drm_display_mode *mode)
 {
-   if (mode-clock  hdmi_portclock_limit(intel_attached_hdmi(connector),
-  true))
+   int clock = mode-clock;
+
+   if (mode-flags  DRM_MODE_FLAG_DBLCLK)
+   clock *= 2;
+
+   if (clock  hdmi_portclock_limit(intel_attached_hdmi(connector),
+true))
return MODE_CLOCK_HIGH;
-   if (mode-clock  2)
+   if (clock  2)
return MODE_CLOCK_LOW;
 
if (mode-flags  DRM_MODE_FLAG_DBLSCAN)
@@ -921,6 +926,10 @@ bool intel_hdmi_compute_config(struct intel_encoder 
*encoder,
intel_hdmi-color_range = 0;
}
 
+   if (adjusted_mode-flags  DRM_MODE_FLAG_DBLCLK) {
+   pipe_config-pixel_multiplier = 2;
+   }
+
if (intel_hdmi-color_range)
pipe_config-limited_color_range = true;
 
-- 
1.7.9.5

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[Intel-gfx] [PATCH 0/2] drm/edid: Reduce horizontal timings for pixel

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

Split original drm_edid.c changes and intel_hdmi.c HDMI pixel
replciation changes into separate patches.   

Clint Taylor (2):
  drm/edid: Reduce horizontal timings for pixel replicated modes
  drm/i915/hdmi: Enable pipe pixel replication for SD interlaced modes

 drivers/gpu/drm/drm_edid.c|   96 ++---
 drivers/gpu/drm/i915/intel_hdmi.c |   15 --
 2 files changed, 60 insertions(+), 51 deletions(-)

-- 
1.7.9.5

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[Intel-gfx] [PATCH 1/2] drm/edid: Reduce horizontal timings for pixel replicated modes

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

Pixel replicated modes should be non-2x horizontal timings and pixel
replicated by the HW across the HDMI cable at 2X pixel clock. Current
horizontal resolution of 1440 does not allow pixel duplication to
occur and scaling artifacts occur on the TV. HDMI certification
7-26 currently fails for all pixel replicated modes. This change will
allow HDMI certification with 480i/576i modes once pixel replication
is turned on.

Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 drivers/gpu/drm/drm_edid.c |   96 ++--
 1 file changed, 48 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index daf3cd8..1bdbfd0 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -632,27 +632,27 @@ static const struct drm_display_mode edid_cea_modes[] = {
   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
DRM_MODE_FLAG_INTERLACE),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 6 - 1440x480i@60Hz */
-   { DRM_MODE(1440x480i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
-  1602, 1716, 0, 480, 488, 494, 525, 0,
+   /* 6 - 720(1440)x480i@60Hz */
+   { DRM_MODE(720x480i, DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
+  801, 858, 0, 480, 488, 494, 525, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
-   /* 7 - 1440x480i@60Hz */
-   { DRM_MODE(1440x480i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
-  1602, 1716, 0, 480, 488, 494, 525, 0,
+   /* 7 - 720(1440)x480i@60Hz */
+   { DRM_MODE(720x480i, DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
+  801, 858, 0, 480, 488, 494, 525, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 8 - 1440x240@60Hz */
-   { DRM_MODE(1440x240, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
-  1602, 1716, 0, 240, 244, 247, 262, 0,
+   /* 8 - 720(1440)x240@60Hz */
+   { DRM_MODE(720x240, DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
+  801, 858, 0, 240, 244, 247, 262, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
-   /* 9 - 1440x240@60Hz */
-   { DRM_MODE(1440x240, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
-  1602, 1716, 0, 240, 244, 247, 262, 0,
+   /* 9 - 720(1440)x240@60Hz */
+   { DRM_MODE(720x240, DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
+  801, 858, 0, 240, 244, 247, 262, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
@@ -714,27 +714,27 @@ static const struct drm_display_mode edid_cea_modes[] = {
   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
DRM_MODE_FLAG_INTERLACE),
  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 21 - 1440x576i@50Hz */
-   { DRM_MODE(1440x576i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
-  1590, 1728, 0, 576, 580, 586, 625, 0,
+   /* 21 - 720(1440)x576i@50Hz */
+   { DRM_MODE(720x576i, DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
+  795, 864, 0, 576, 580, 586, 625, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
-   /* 22 - 1440x576i@50Hz */
-   { DRM_MODE(1440x576i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
-  1590, 1728, 0, 576, 580, 586, 625, 0,
+   /* 22 - 720(1440)x576i@50Hz */
+   { DRM_MODE(720x576i, DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
+  795, 864, 0, 576, 580, 586, 625, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 23 - 1440x288@50Hz */
-   { DRM_MODE(1440x288, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
-  1590, 1728, 0, 288, 290, 293, 312, 0,
+   /* 23 - 720(1440)x288@50Hz */
+   { DRM_MODE(720x288, DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
+  795, 864, 0, 288, 

[Intel-gfx] [PATCH] drm/edid: Reduce horizontal timings for pixel replicated modes

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

Pixel replicated modes should be 720 horizontal pixel and pixel
replicated by the HW across the HDMI cable at 2X pixel clock. Current
horizontal resolution of 1440 does not allow pixel duplication to
occur and scaling artifacts occur on the TV. HDMI certification
7-26 currently fails for all pixel replicated modes. This change fizes
the HDMI certification issues with 480i/576i.

V2: Removed interlace flag from VICs 44 and 45. Will be submitted in
another patch. Various other formatting fixes.

V3: 576i@200 htotal fixed. Check min and max pixel clocks.

Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
---
 drivers/gpu/drm/drm_edid.c|   96 ++---
 drivers/gpu/drm/i915/intel_hdmi.c |   15 --
 2 files changed, 60 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index f905c63..dc25999 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -632,27 +632,27 @@ static const struct drm_display_mode edid_cea_modes[] = {
   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
DRM_MODE_FLAG_INTERLACE),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 6 - 1440x480i@60Hz */
-   { DRM_MODE(1440x480i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
-  1602, 1716, 0, 480, 488, 494, 525, 0,
+   /* 6 - 720(1440)x480i@60Hz */
+   { DRM_MODE(720x480i, DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
+  801, 858, 0, 480, 488, 494, 525, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
-   /* 7 - 1440x480i@60Hz */
-   { DRM_MODE(1440x480i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
-  1602, 1716, 0, 480, 488, 494, 525, 0,
+   /* 7 - 720(1440)x480i@60Hz */
+   { DRM_MODE(720x480i, DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
+  801, 858, 0, 480, 488, 494, 525, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 8 - 1440x240@60Hz */
-   { DRM_MODE(1440x240, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
-  1602, 1716, 0, 240, 244, 247, 262, 0,
+   /* 8 - 720(1440)x240@60Hz */
+   { DRM_MODE(720x240, DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
+  801, 858, 0, 240, 244, 247, 262, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
-   /* 9 - 1440x240@60Hz */
-   { DRM_MODE(1440x240, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
-  1602, 1716, 0, 240, 244, 247, 262, 0,
+   /* 9 - 720(1440)x240@60Hz */
+   { DRM_MODE(720x240, DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
+  801, 858, 0, 240, 244, 247, 262, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
@@ -714,27 +714,27 @@ static const struct drm_display_mode edid_cea_modes[] = {
   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
DRM_MODE_FLAG_INTERLACE),
  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 21 - 1440x576i@50Hz */
-   { DRM_MODE(1440x576i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
-  1590, 1728, 0, 576, 580, 586, 625, 0,
+   /* 21 - 720(1440)x576i@50Hz */
+   { DRM_MODE(720x576i, DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
+  795, 864, 0, 576, 580, 586, 625, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
-   /* 22 - 1440x576i@50Hz */
-   { DRM_MODE(1440x576i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
-  1590, 1728, 0, 576, 580, 586, 625, 0,
+   /* 22 - 720(1440)x576i@50Hz */
+   { DRM_MODE(720x576i, DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
+  795, 864, 0, 576, 580, 586, 625, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 23 - 1440x288@50Hz */
-   { DRM_MODE(1440x288, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
-  1590, 1728, 0, 288, 290, 293, 312, 0,
+   /* 23 - 720(1440)x288@50Hz */
+   { DRM_MODE(720x288, DRM_MODE_TYPE_DRIVER, 13500, 720, 

[Intel-gfx] [PATCH] drm/i915/dp: Backlight PWM enable before BL Enable assert

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

Backlight on delay uses PWM enable time to seperate PWM to
backlight enable assert. Previous time difference used timing
from VDD enable which occur several seconds before resulting
in PWM starting 5ms after backlight enable. Changes to backlight
 duty cycle take affect at the end of the current PWM cycle.
Measured time for the PWM cycle is 5ms. 5 additional ms must be
added to the backlight_on_delay to get correct VBT timing of
PWM to backlight enable assert.

V2: Rebase to Jani Nikula backlight power patch 1/4

Change-Id: I2982f9785d92e8d64c04ca25c8bd4c5d1dc8067c
Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
---
 drivers/gpu/drm/i915/intel_dp.c  | 6 --
 drivers/gpu/drm/i915/intel_drv.h | 1 +
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d8baf60..aed923b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1141,7 +1141,7 @@ static void wait_panel_power_cycle(struct intel_dp 
*intel_dp)
 
 static void wait_backlight_on(struct intel_dp *intel_dp)
 {
-   wait_remaining_ms_from_jiffies(intel_dp-last_power_on,
+   wait_remaining_ms_from_jiffies(intel_dp-last_backlight_on,
   intel_dp-backlight_on_delay);
 }
 
@@ -1418,6 +1418,7 @@ void intel_edp_backlight_on(struct intel_dp *intel_dp)
DRM_DEBUG_KMS(\n);
 
intel_panel_enable_backlight(intel_dp-attached_connector);
+   intel_dp-last_backlight_on = jiffies;
_intel_edp_backlight_on(intel_dp);
 }
 
@@ -4256,9 +4257,10 @@ intel_dp_init_panel_power_sequencer(struct drm_device 
*dev,
assign_final(t11_t12);
 #undef assign_final
 
+#define PWM_CYCLE_DELAY 5
 #define get_delay(field)   (DIV_ROUND_UP(final.field, 10))
intel_dp-panel_power_up_delay = get_delay(t1_t3);
-   intel_dp-backlight_on_delay = get_delay(t8);
+   intel_dp-backlight_on_delay = get_delay(t8) + PWM_CYCLE_DELAY;
intel_dp-backlight_off_delay = get_delay(t9);
intel_dp-panel_power_down_delay = get_delay(t10);
intel_dp-panel_power_cycle_delay = get_delay(t11_t12);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3abc915..ad6fcc1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -556,6 +556,7 @@ struct intel_dp {
bool want_panel_vdd;
unsigned long last_power_cycle;
unsigned long last_power_on;
+   unsigned long last_backlight_on;
unsigned long last_backlight_off;
 
struct notifier_block edp_notifier;
-- 
1.8.3.2

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[Intel-gfx] [PATCH] drm/edid: Reduce horizontal timings for pixel replicated modes

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

Pixel replicated modes should be 720 horizontal pixel and pixel
replicated by the HW across the HDMI cable at 2X pixel clock. Current
horizontal resolution of 1440 does not allow pixel duplication to
occur and scaling artifacts occur on the TV. HDMI certification
7-26 currently fails for all pixel replicated modes. This change fizes
the HDMI certification issues with 480i/576i.

V2: Removed interlace flag from VICs 44 and 45. Will be submitted in
another patch. Various other formatting fixes.

Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
---
 drivers/gpu/drm/drm_edid.c|   96 ++---
 drivers/gpu/drm/i915/intel_hdmi.c |   10 +++-
 2 files changed, 57 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index f905c63..412c525 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -632,27 +632,27 @@ static const struct drm_display_mode edid_cea_modes[] = {
   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
DRM_MODE_FLAG_INTERLACE),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 6 - 1440x480i@60Hz */
-   { DRM_MODE(1440x480i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
-  1602, 1716, 0, 480, 488, 494, 525, 0,
+   /* 6 - 720(1440)x480i@60Hz */
+   { DRM_MODE(720x480i, DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
+  801, 858, 0, 480, 488, 494, 525, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
-   /* 7 - 1440x480i@60Hz */
-   { DRM_MODE(1440x480i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
-  1602, 1716, 0, 480, 488, 494, 525, 0,
+   /* 7 - 720(1440)x480i@60Hz */
+   { DRM_MODE(720x480i, DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
+  801, 858, 0, 480, 488, 494, 525, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 8 - 1440x240@60Hz */
-   { DRM_MODE(1440x240, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
-  1602, 1716, 0, 240, 244, 247, 262, 0,
+   /* 8 - 720(1440)x240@60Hz */
+   { DRM_MODE(720x240, DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
+  801, 858, 0, 240, 244, 247, 262, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
-   /* 9 - 1440x240@60Hz */
-   { DRM_MODE(1440x240, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
-  1602, 1716, 0, 240, 244, 247, 262, 0,
+   /* 9 - 720(1440)x240@60Hz */
+   { DRM_MODE(720x240, DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
+  801, 858, 0, 240, 244, 247, 262, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
@@ -714,27 +714,27 @@ static const struct drm_display_mode edid_cea_modes[] = {
   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
DRM_MODE_FLAG_INTERLACE),
  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 21 - 1440x576i@50Hz */
-   { DRM_MODE(1440x576i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
-  1590, 1728, 0, 576, 580, 586, 625, 0,
+   /* 21 - 720(1440)x576i@50Hz */
+   { DRM_MODE(720x576i, DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
+  795, 864, 0, 576, 580, 586, 625, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
-   /* 22 - 1440x576i@50Hz */
-   { DRM_MODE(1440x576i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
-  1590, 1728, 0, 576, 580, 586, 625, 0,
+   /* 22 - 720(1440)x576i@50Hz */
+   { DRM_MODE(720x576i, DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
+  795, 864, 0, 576, 580, 586, 625, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 23 - 1440x288@50Hz */
-   { DRM_MODE(1440x288, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
-  1590, 1728, 0, 288, 290, 293, 312, 0,
+   /* 23 - 720(1440)x288@50Hz */
+   { DRM_MODE(720x288, DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
+  795, 864, 0, 288, 290, 293, 312, 0,
  

[Intel-gfx] [PATCH] drm/edid: Reduce horizontal timings for pixel replicated modes

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

Pixel replicated modes should be 720 horizontal pixel and pixel
replicated by the HW across the HDMI cable at 2X pixel clock. Current
horizontal resolution of 1440 does not allow pixel duplication to
occur and scaling artifacts occur on the TV. HDMI certification
7-26 currently fails for all pixel replicated modes. This change fizes
the HDMI certification issues with 480i/576i.

Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
---
 drivers/gpu/drm/drm_edid.c|  100 ++---
 drivers/gpu/drm/i915/intel_hdmi.c |   14 +-
 2 files changed, 63 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index f905c63..c7a26a7 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -632,27 +632,27 @@ static const struct drm_display_mode edid_cea_modes[] = {
   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
DRM_MODE_FLAG_INTERLACE),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 6 - 1440x480i@60Hz */
-   { DRM_MODE(1440x480i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
-  1602, 1716, 0, 480, 488, 494, 525, 0,
+   /* 6 - 720(1440)x480i@60Hz */
+   { DRM_MODE(720x480i, DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
+  801, 858, 0, 480, 488, 494, 525, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
-   /* 7 - 1440x480i@60Hz */
-   { DRM_MODE(1440x480i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
-  1602, 1716, 0, 480, 488, 494, 525, 0,
+   /* 7 - 720(1440)x480i@60Hz */
+   { DRM_MODE(720x480i, DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
+  801, 858, 0, 480, 488, 494, 525, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 8 - 1440x240@60Hz */
-   { DRM_MODE(1440x240, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
-  1602, 1716, 0, 240, 244, 247, 262, 0,
+   /* 8 - 720(1440)x240@60Hz */
+   { DRM_MODE(720x240, DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
+  801, 858, 0, 240, 244, 247, 262, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
-   /* 9 - 1440x240@60Hz */
-   { DRM_MODE(1440x240, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
-  1602, 1716, 0, 240, 244, 247, 262, 0,
+   /* 9 - 720(1440)x240@60Hz */
+   { DRM_MODE(720x240, DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
+  801, 858, 0, 240, 244, 247, 262, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
@@ -714,27 +714,27 @@ static const struct drm_display_mode edid_cea_modes[] = {
   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
DRM_MODE_FLAG_INTERLACE),
  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 21 - 1440x576i@50Hz */
-   { DRM_MODE(1440x576i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
-  1590, 1728, 0, 576, 580, 586, 625, 0,
+   /* 21 - 720(1440)x576i@50Hz */
+   { DRM_MODE(720x576i, DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
+  795, 864, 0, 576, 580, 586, 625, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
-   /* 22 - 1440x576i@50Hz */
-   { DRM_MODE(1440x576i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
-  1590, 1728, 0, 576, 580, 586, 625, 0,
+   /* 22 - 720(1440)x576i@50Hz */
+   { DRM_MODE(720x576i, DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
+  795, 864, 0, 576, 580, 586, 625, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 23 - 1440x288@50Hz */
-   { DRM_MODE(1440x288, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
-  1590, 1728, 0, 288, 290, 293, 312, 0,
+   /* 23 - 720(1440)x288@50Hz */
+   { DRM_MODE(720x288, DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
+  795, 864, 0, 288, 290, 293, 312, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_DBLCLK),
 

[Intel-gfx] [PATCH] drm/i915/dp: Backlight PWM enable before BL Enable assert

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

Backlight on delay uses PWM enable time to seperate PWM to
backlight enable assert. Previous time difference used timing
from VDD enable which occur several seconds before resulting
in PWM starting 5ms after backlight enable. Changes to backlight
 duty cycle take affect at the end of the current PWM cycle.
Measured time for the PWM cycle is 5ms. 5 additional ms must be
added to the backlight_on_delay to get correct VBT timing of
PWM to backlight enable assert.

Change-Id: I484999a597fd84dacf4cf99a168ec9ba4bb6ff11
Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
---
 drivers/gpu/drm/i915/intel_dp.c  | 6 --
 drivers/gpu/drm/i915/intel_drv.h | 1 +
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e5ada4f..c59ccdb 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1141,7 +1141,7 @@ static void wait_panel_power_cycle(struct intel_dp 
*intel_dp)
 
 static void wait_backlight_on(struct intel_dp *intel_dp)
 {
-   wait_remaining_ms_from_jiffies(intel_dp-last_power_on,
+   wait_remaining_ms_from_jiffies(intel_dp-last_backlight_on,
   intel_dp-backlight_on_delay);
 }
 
@@ -1398,6 +1398,7 @@ void intel_edp_backlight_on(struct intel_dp *intel_dp)
DRM_DEBUG_KMS(\n);
 
intel_panel_enable_backlight(intel_dp-attached_connector);
+   intel_dp-last_backlight_on = jiffies;
 
/*
 * If we enable the backlight right away following a panel power
@@ -4243,9 +4244,10 @@ intel_dp_init_panel_power_sequencer(struct drm_device 
*dev,
assign_final(t11_t12);
 #undef assign_final
 
+#define PWM_CYCLE_DELAY 5
 #define get_delay(field)   (DIV_ROUND_UP(final.field, 10))
intel_dp-panel_power_up_delay = get_delay(t1_t3);
-   intel_dp-backlight_on_delay = get_delay(t8);
+   intel_dp-backlight_on_delay = get_delay(t8) + PWM_CYCLE_DELAY;
intel_dp-backlight_off_delay = get_delay(t9);
intel_dp-panel_power_down_delay = get_delay(t10);
intel_dp-panel_power_cycle_delay = get_delay(t11_t12);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3abc915..ad6fcc1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -556,6 +556,7 @@ struct intel_dp {
bool want_panel_vdd;
unsigned long last_power_cycle;
unsigned long last_power_on;
+   unsigned long last_backlight_on;
unsigned long last_backlight_off;
 
struct notifier_block edp_notifier;
-- 
1.8.3.2

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[Intel-gfx] [PATCH] drm/i915: remove pixel doubled HDMI modes from valid modes list

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

Intel HDMI does not correctly configure pixel replicated HDMI modes
480i and 576i. Remove support for these modes until DRM has been
changed to correctly identify SD interlaced modes by reporting there
true horizontal resolution 720 instead of the pre-pixel doubled 1440.

Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
---
 drivers/gpu/drm/i915/intel_hdmi.c |3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 5f47d35..ab32523 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -873,6 +873,9 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
if (mode-flags  DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
 
+   if (mode-flags  DRM_MODE_FLAG_DBLCLK)
+   return MODE_NO_INTERLACE;
+
return MODE_OK;
 }
 
-- 
1.7.9.5

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[Intel-gfx] [PATCH] drm: HDMI pixel replication modes now hactive of 720 for pixel replication

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

CEA SD interlaced modes use a horizontal 720 pixels that are pixel replicated 
to 1440. The current driver reports 1440 pixel to the OS and does not set pixel 
replicated modes.

Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
---
 drivers/gpu/drm/drm_edid.c|   68 ++---
 drivers/gpu/drm/i915/intel_hdmi.c |   13 +++
 2 files changed, 47 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index dfa9769..5233f4c 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -632,26 +632,26 @@ static const struct drm_display_mode edid_cea_modes[] = {
   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
DRM_MODE_FLAG_INTERLACE),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 6 - 1440x480i@60Hz */
-   { DRM_MODE(1440x480i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
+   /* 6 - 720(1440)x480i@60Hz */
+   { DRM_MODE(720x480i, DRM_MODE_TYPE_DRIVER, 27000, 720, 1478,
   1602, 1716, 0, 480, 488, 494, 525, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
-   /* 7 - 1440x480i@60Hz */
-   { DRM_MODE(1440x480i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
+   /* 7 - 720(1440)x480i@60Hz */
+   { DRM_MODE(720x480i, DRM_MODE_TYPE_DRIVER, 27000, 720, 1478,
   1602, 1716, 0, 480, 488, 494, 525, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 8 - 1440x240@60Hz */
-   { DRM_MODE(1440x240, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
+   /* 8 - 720(1440)x240@60Hz */
+   { DRM_MODE(720x240, DRM_MODE_TYPE_DRIVER, 27000, 720, 1478,
   1602, 1716, 0, 240, 244, 247, 262, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
-   /* 9 - 1440x240@60Hz */
-   { DRM_MODE(1440x240, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
+   /* 9 - 720(1440)x240@60Hz */
+   { DRM_MODE(720x240, DRM_MODE_TYPE_DRIVER, 27000, 720, 1478,
   1602, 1716, 0, 240, 244, 247, 262, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_DBLCLK),
@@ -714,26 +714,26 @@ static const struct drm_display_mode edid_cea_modes[] = {
   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
DRM_MODE_FLAG_INTERLACE),
  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 21 - 1440x576i@50Hz */
-   { DRM_MODE(1440x576i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
+   /* 21 - 720(1440)x576i@50Hz */
+   { DRM_MODE(720x576i, DRM_MODE_TYPE_DRIVER, 27000, 720, 1464,
   1590, 1728, 0, 576, 580, 586, 625, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
-   /* 22 - 1440x576i@50Hz */
-   { DRM_MODE(1440x576i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
+   /* 22 - 720(1440)x576i@50Hz */
+   { DRM_MODE(720x576i, DRM_MODE_TYPE_DRIVER, 27000, 720, 1464,
   1590, 1728, 0, 576, 580, 586, 625, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
-   /* 23 - 1440x288@50Hz */
-   { DRM_MODE(1440x288, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
+   /* 23 - 720(1440)x288@50Hz */
+   { DRM_MODE(720x288, DRM_MODE_TYPE_DRIVER, 27000, 720, 1464,
   1590, 1728, 0, 288, 290, 293, 312, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_DBLCLK),
  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
-   /* 24 - 1440x288@50Hz */
-   { DRM_MODE(1440x288, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
+   /* 24 - 720(1440)x288@50Hz */
+   { DRM_MODE(720x288, DRM_MODE_TYPE_DRIVER, 27000, 720, 1464,
   1590, 1728, 0, 288, 290, 293, 312, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
DRM_MODE_FLAG_DBLCLK),
@@ -837,17 +837,17 @@ static const struct drm_display_mode edid_cea_modes[] = {
   796, 864, 0, 576, 581, 586, 625, 0,
   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  

[Intel-gfx] [PATCH 01/11] CHROMIUM: drm/i915: add backlight assertion funcs for PWM status

[clinton . a . taylor]

From: Jesse Barnes jbar...@virtuousgeek.org

Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Wayne Boyer wayne.bo...@intel.com

Change-Id: I0838b7c84f1913e1026ad98b8b2e79eb133d17e3
Reviewed-on: https://chromium-review.googlesource.com/192468
Reviewed-by: Stéphane Marchesin marc...@chromium.org
Reviewed-by: Aaron Durbin adur...@chromium.org
Tested-by: Wayne Boyer wayne.bo...@intel.com
Commit-Queue: Wayne Boyer wayne.bo...@intel.com

Conflicts:
drivers/gpu/drm/i915/intel_dp.c
---
 drivers/gpu/drm/i915/intel_dp.c |   22 ++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2adb727..90b24f6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -369,6 +369,21 @@ static int edp_notify_handler(struct notifier_block *this, 
unsigned long code,
return 0;
 }
 
+static void assert_pwm(struct drm_i915_private *dev_priv,
+  struct intel_connector *connector,
+  bool expected_state)
+{
+   bool state;
+
+   state = dev_priv-display.get_backlight(connector);
+
+   WARN(state != expected_state, pwm state failure, expected %d, found 
+%d\n, expected_state, state);
+}
+
+#define assert_pwm_enabled(d, p) assert_pwm((d), (p), true)
+#define assert_pwm_disabled(d, p) assert_pwm((d), (p), false)
+
 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 {
struct drm_device *dev = intel_dp_to_dev(intel_dp);
@@ -1351,6 +1366,8 @@ void intel_edp_panel_off(struct intel_dp *intel_dp)
 
WARN(!intel_dp-want_panel_vdd, Need VDD to turn off panel\n);
 
+   assert_pwm_disabled(dev_priv, intel_dp-attached_connector);
+
pp = ironlake_get_pp_control(intel_dp);
/* We need to switch off panel power _and_ force vdd, for otherwise some
 * panels get very unhappy and cease to work. */
@@ -1387,6 +1404,8 @@ void intel_edp_backlight_on(struct intel_dp *intel_dp)
 
intel_panel_enable_backlight(intel_dp-attached_connector);
 
+   assert_pwm_disabled(dev_priv, intel_dp-attached_connector);
+
/*
 * If we enable the backlight right away following a panel power
 * on, we may see slight flicker as the panel syncs with the eDP
@@ -1415,6 +1434,9 @@ void intel_edp_backlight_off(struct intel_dp *intel_dp)
 
DRM_DEBUG_KMS(\n);
pp = ironlake_get_pp_control(intel_dp);
+
+   assert_pwm_enabled(dev_priv, intel_dp-attached_connector);
+
pp = ~EDP_BLC_ENABLE;
 
pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
-- 
1.7.9.5

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[Intel-gfx] [PATCH 00/11] drm/i915: backlight scaling and timing changes from chromium.

[clinton . a . taylor]

From: Clint Taylor clinton.a.tay...@intel.com

Upstreaming Chromium backlight related patches which including minimum duty 
cycle and 0..max_brightness scaling of the sysfs requested brightness level. 

Ben Widawsky (5):
  CHROMIUM: drm/i915/vlv: Initialize pipe B backlight to A's value
  CHROMIUM: drm/i915: Provide valleyview backlight fallback value
  CHROMIUM: drm/i915/vlv: Scale backlight to min duty ratio
  CHROMIUM: drm/i915/vlv: Check BLC enable for pwm invariant
  CHROMIUM: drm/i915/vlv: Prefer VBT to set PWM

Jani Nikula (1):
  CHROMIUM: drm/i915: parse backlight modulation frequency from the
BIOS VBT

Jesse Barnes (4):
  CHROMIUM: drm/i915: add backlight assertion funcs for PWM status
  CHROMIUM: drm/i915: do not explicitly disable backlight in panel_off
  CHROMIUM: drm/i915: use backlight wrapper functions instead of direct
calls
  CHROMIUM: drm/i915: change order of PWM enable vs BLC enable

Kevin Strasser (1):
  CHROMIUM: drm/i915/vlv: Fix BLM_PWM_ENABLE check in pwm invariant

 drivers/gpu/drm/i915/i915_drv.h|   10 ++
 drivers/gpu/drm/i915/intel_bios.c  |   35 +++-
 drivers/gpu/drm/i915/intel_dp.c|   36 ++---
 drivers/gpu/drm/i915/intel_drv.h   |1 +
 drivers/gpu/drm/i915/intel_panel.c |   62 ++--
 5 files changed, 123 insertions(+), 21 deletions(-)

-- 
1.7.9.5

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