Re: [Intel-gfx] [PATCH v2 6/6] drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv
On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gu...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
For disabling L3 clock gating we need to set bit 25 of MMIO
register 940c. Earlier this was being done by just writing 1
into bit 25 and resetting all other bits.
This patch modifies the routine to read-modify-write of the
register, so that the values of other bits are not destroyed.
v2: Modifying the comments and the patch commit message (Chris)
Signed-off-by: Akash Goel akash.g...@intel.com
Signed-off-by: Sourab Gupta sourab.gu...@intel.com
Apart from the multiline comment format and the second line not aligned
with the '(' as we usually do:
Reviewed-by: Damien Lespiau damien.lesp...@intel.com
--
Damien
---
drivers/gpu/drm/i915/intel_pm.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c3a8554..af4bb8e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5093,8 +5093,11 @@ static void valleyview_init_clock_gating(struct
drm_device *dev)
I915_WRITE(GEN6_UCGCTL2,
GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
- /* WaDisableL3Bank2xClockGate:vlv */
- I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
+ /* WaDisableL3Bank2xClockGate:vlv
+ * Disabling L3 clock gating- MMIO 940c[25] = 1
+ * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
+ I915_WRITE(GEN7_UCGCTL4,
+ I915_READ(GEN7_UCGCTL4) |
GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
--
1.8.5.1
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Re: [Intel-gfx] [PATCH v2 6/6] drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv
On Tue, May 27, 2014 at 03:27:23PM +0100, Damien Lespiau wrote:
On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gu...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
For disabling L3 clock gating we need to set bit 25 of MMIO
register 940c. Earlier this was being done by just writing 1
into bit 25 and resetting all other bits.
This patch modifies the routine to read-modify-write of the
register, so that the values of other bits are not destroyed.
v2: Modifying the comments and the patch commit message (Chris)
Signed-off-by: Akash Goel akash.g...@intel.com
Signed-off-by: Sourab Gupta sourab.gu...@intel.com
Apart from the multiline comment format and the second line not aligned
with the '(' as we usually do:
Fixed.
Reviewed-by: Damien Lespiau damien.lesp...@intel.com
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH v2 6/6] drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv
On Mon, 2014-04-14 at 10:22 +, Gupta, Sourab wrote: On Tue, 2014-04-01 at 10:53 +0530, sourab gupta wrote: On Tue, 2014-03-25 at 12:23 +0530, sourab gupta wrote: On Mon, 2014-03-24 at 17:56 +, Lespiau, Damien wrote: On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gu...@intel.com wrote: From: Akash Goel akash.g...@intel.com For disabling L3 clock gating we need to set bit 25 of MMIO register 940c. Earlier this was being done by just writing 1 into bit 25 and resetting all other bits. This patch modifies the routine to read-modify-write of the register, so that the values of other bits are not destroyed. v2: Modifying the comments and the patch commit message (Chris) This patch commit message lacks the most important information: which bit are we setting back to 0 and we shouldn't, and why is that important? We do direct writes to other registers in that function (for instance (MI_ARB_VLV just below). Hi Damien, The reset value of the register is 0x00F80003. Therefore, if we directly set only bit 25 to 1, without caring about other bits, the following reg bits will be affected (bits 1:0, bits 23:19). This doesn't seem to be the case with other regs where we are writing directly (MI_ARB_VLV ) whose default value is 0. So, by this commit we're just trying to set only the bit which we really want to change. Regards, Sourab Hi Damien, Please provide your comments on the above explanation. I'll add more information to the commit message regarding the same, if it is okay. Thanks, Sourab Hi Damien, Waiting for feedback on the patch and the explanation. Can you please let us know if the explained reason is good enough for the patch to be considered. If so, it can be added to the commit message. Regards, Sourab Hi, Can you please review this patch. Waiting for the feedback. Thanks, Sourab ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 6/6] drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv
On Tue, 2014-04-01 at 10:53 +0530, sourab gupta wrote: On Tue, 2014-03-25 at 12:23 +0530, sourab gupta wrote: On Mon, 2014-03-24 at 17:56 +, Lespiau, Damien wrote: On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gu...@intel.com wrote: From: Akash Goel akash.g...@intel.com For disabling L3 clock gating we need to set bit 25 of MMIO register 940c. Earlier this was being done by just writing 1 into bit 25 and resetting all other bits. This patch modifies the routine to read-modify-write of the register, so that the values of other bits are not destroyed. v2: Modifying the comments and the patch commit message (Chris) This patch commit message lacks the most important information: which bit are we setting back to 0 and we shouldn't, and why is that important? We do direct writes to other registers in that function (for instance (MI_ARB_VLV just below). Hi Damien, The reset value of the register is 0x00F80003. Therefore, if we directly set only bit 25 to 1, without caring about other bits, the following reg bits will be affected (bits 1:0, bits 23:19). This doesn't seem to be the case with other regs where we are writing directly (MI_ARB_VLV ) whose default value is 0. So, by this commit we're just trying to set only the bit which we really want to change. Regards, Sourab Hi Damien, Please provide your comments on the above explanation. I'll add more information to the commit message regarding the same, if it is okay. Thanks, Sourab Hi Damien, Waiting for feedback on the patch and the explanation. Can you please let us know if the explained reason is good enough for the patch to be considered. If so, it can be added to the commit message. Regards, Sourab ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 6/6] drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv
On Tue, 2014-03-25 at 12:23 +0530, sourab gupta wrote: On Mon, 2014-03-24 at 17:56 +, Lespiau, Damien wrote: On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gu...@intel.com wrote: From: Akash Goel akash.g...@intel.com For disabling L3 clock gating we need to set bit 25 of MMIO register 940c. Earlier this was being done by just writing 1 into bit 25 and resetting all other bits. This patch modifies the routine to read-modify-write of the register, so that the values of other bits are not destroyed. v2: Modifying the comments and the patch commit message (Chris) This patch commit message lacks the most important information: which bit are we setting back to 0 and we shouldn't, and why is that important? We do direct writes to other registers in that function (for instance (MI_ARB_VLV just below). Hi Damien, The reset value of the register is 0x00F80003. Therefore, if we directly set only bit 25 to 1, without caring about other bits, the following reg bits will be affected (bits 1:0, bits 23:19). This doesn't seem to be the case with other regs where we are writing directly (MI_ARB_VLV ) whose default value is 0. So, by this commit we're just trying to set only the bit which we really want to change. Regards, Sourab Hi Damien, Please provide your comments on the above explanation. I'll add more information to the commit message regarding the same, if it is okay. Thanks, Sourab ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 6/6] drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv
On Mon, 2014-03-24 at 17:56 +, Lespiau, Damien wrote: On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gu...@intel.com wrote: From: Akash Goel akash.g...@intel.com For disabling L3 clock gating we need to set bit 25 of MMIO register 940c. Earlier this was being done by just writing 1 into bit 25 and resetting all other bits. This patch modifies the routine to read-modify-write of the register, so that the values of other bits are not destroyed. v2: Modifying the comments and the patch commit message (Chris) This patch commit message lacks the most important information: which bit are we setting back to 0 and we shouldn't, and why is that important? We do direct writes to other registers in that function (for instance (MI_ARB_VLV just below). Hi Damien, The reset value of the register is 0x00F80003. Therefore, if we directly set only bit 25 to 1, without caring about other bits, the following reg bits will be affected (bits 1:0, bits 23:19). This doesn't seem to be the case with other regs where we are writing directly (MI_ARB_VLV ) whose default value is 0. So, by this commit we're just trying to set only the bit which we really want to change. Regards, Sourab ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 6/6] drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv
From: Akash Goel akash.g...@intel.com For disabling L3 clock gating we need to set bit 25 of MMIO register 940c. Earlier this was being done by just writing 1 into bit 25 and resetting all other bits. This patch modifies the routine to read-modify-write of the register, so that the values of other bits are not destroyed. v2: Modifying the comments and the patch commit message (Chris) Signed-off-by: Akash Goel akash.g...@intel.com Signed-off-by: Sourab Gupta sourab.gu...@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index c3a8554..af4bb8e 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5093,8 +5093,11 @@ static void valleyview_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); - /* WaDisableL3Bank2xClockGate:vlv */ - I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); + /* WaDisableL3Bank2xClockGate:vlv +* Disabling L3 clock gating- MMIO 940c[25] = 1 +* Set bit 25, to disable L3_BANK_2x_CLK_GATING */ + I915_WRITE(GEN7_UCGCTL4, + I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); -- 1.8.5.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 6/6] drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv
On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gu...@intel.com wrote: From: Akash Goel akash.g...@intel.com For disabling L3 clock gating we need to set bit 25 of MMIO register 940c. Earlier this was being done by just writing 1 into bit 25 and resetting all other bits. This patch modifies the routine to read-modify-write of the register, so that the values of other bits are not destroyed. v2: Modifying the comments and the patch commit message (Chris) This patch commit message lacks the most important information: which bit are we setting back to 0 and we shouldn't, and why is that important? We do direct writes to other registers in that function (for instance (MI_ARB_VLV just below). -- Damien ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
