Re: Make BRAM/DRAM from FPGA accessible to Jailhouse on ZCU102

[Giovani Gracioli]

Em quinta-feira, 24 de maio de 2018 14:57:18 UTC-4, J. Kiszka  escreveu:
> On 2018-05-24 16:50, Giovani Gracioli wrote:
> > Em quinta-feira, 24 de maio de 2018 10:44:10 UTC-4, J. Kiszka  escreveu:
> >> On 2018-05-24 16:27, Giovani Gracioli wrote:
>  On 2018-05-24 15:59, Giovani Gracioli wrote:
> > Not sure about MMU on Erika.
> >
> > Yes, the fault is reported as well. This address is just another 
> > memory. 0xA00.. is the BRAM and 0x500.. is the DRAM. Both have the same 
> > faulty behavior when the size is 2MB.
> 
>  You see the issue also when mapping some arbitrary DRAM region with a
>  size of 2MB? Can you reproduce this with an IVSHMEM region as well? What
>  if you increase the size beyond 2M, to 3M e.g.?
> 
>  Jan
> 
>  -- 
>  Siemens AG, Corporate Technology, CT RDA IOT SES-DE
>  Corporate Competence Center Embedded Linux
> >>>
> >>> DRAM: works with 1MB, 3MB, and 32MB.
> >>>   does not work with 2MB.
> >>>
> >>> BRAM (is limited to 2MB): works with 1MB, does not with 2MB.
> >>>
> >>> IVSHMEM: tested with 1 and 2MB and worked in both cases.
> >>>
> >>
> >> That's not a consistent pattern yet because IVSHMEM and DRAM is just the
> >> same, use the same flags etc.
> >>
> >> Can you send a config that demonstrates the DRAM issue? Ideally very
> >> close to the upstream zynqmp-zcu102 configs.
> >>
> >> Thanks,
> >> Jan
> >>
> >> -- 
> >> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> >> Corporate Competence Center Embedded Linux
> > 
> > Just tested these two attached and got:
> > 
> > Unhandled data write at 0x5(4)
> > 
> > FATAL: unhandled trap (exception class 0x24)
> > Cell state before exception:
> >  pc: 6944   lr: 6944 spsr: 6005 EL1
> >  sp: 6870  esr: 24 1 1970045
> >  x0:    x1: 9670   x2: 
> >  x3: 0004   x4: 27b8   x5: 
> >  x6:    x7: 0080   x8: 68b0
> >  x9: 23e0  x10:   x11: 9292
> > x12:   x13:   x14: 0020
> > x15:   x16:   x17: 
> > x18:   x19: 1118  x20: 92cf
> > x21: 00080070  x22: 0005  x23: 000a
> > x24:   x25:   x26: 
> > x27:   x28:   x29: 
> > 
> > Parking CPU 1 (Cell: "nfer")
> > 
> 
> OK, good news, I've reproduced something very strange, and that even
> inside qemu. Debugging...
> 
> Jan
> 
> -- 
> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> Corporate Competence Center Embedded Linux

Let me know if you want me to test on the real hardware once you have figure it 
out.

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Re: Make BRAM/DRAM from FPGA accessible to Jailhouse on ZCU102

[Jan Kiszka]

On 2018-05-24 16:50, Giovani Gracioli wrote:
> Em quinta-feira, 24 de maio de 2018 10:44:10 UTC-4, J. Kiszka  escreveu:
>> On 2018-05-24 16:27, Giovani Gracioli wrote:
 On 2018-05-24 15:59, Giovani Gracioli wrote:
> Not sure about MMU on Erika.
>
> Yes, the fault is reported as well. This address is just another memory. 
> 0xA00.. is the BRAM and 0x500.. is the DRAM. Both have the same faulty 
> behavior when the size is 2MB.

 You see the issue also when mapping some arbitrary DRAM region with a
 size of 2MB? Can you reproduce this with an IVSHMEM region as well? What
 if you increase the size beyond 2M, to 3M e.g.?

 Jan

 -- 
 Siemens AG, Corporate Technology, CT RDA IOT SES-DE
 Corporate Competence Center Embedded Linux
>>>
>>> DRAM: works with 1MB, 3MB, and 32MB.
>>>   does not work with 2MB.
>>>
>>> BRAM (is limited to 2MB): works with 1MB, does not with 2MB.
>>>
>>> IVSHMEM: tested with 1 and 2MB and worked in both cases.
>>>
>>
>> That's not a consistent pattern yet because IVSHMEM and DRAM is just the
>> same, use the same flags etc.
>>
>> Can you send a config that demonstrates the DRAM issue? Ideally very
>> close to the upstream zynqmp-zcu102 configs.
>>
>> Thanks,
>> Jan
>>
>> -- 
>> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
>> Corporate Competence Center Embedded Linux
> 
> Just tested these two attached and got:
> 
> Unhandled data write at 0x5(4)
> 
> FATAL: unhandled trap (exception class 0x24)
> Cell state before exception:
>  pc: 6944   lr: 6944 spsr: 6005 EL1
>  sp: 6870  esr: 24 1 1970045
>  x0:    x1: 9670   x2: 
>  x3: 0004   x4: 27b8   x5: 
>  x6:    x7: 0080   x8: 68b0
>  x9: 23e0  x10:   x11: 9292
> x12:   x13:   x14: 0020
> x15:   x16:   x17: 
> x18:   x19: 1118  x20: 92cf
> x21: 00080070  x22: 0005  x23: 000a
> x24:   x25:   x26: 
> x27:   x28:   x29: 
> 
> Parking CPU 1 (Cell: "nfer")
> 

OK, good news, I've reproduced something very strange, and that even
inside qemu. Debugging...

Jan

-- 
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux

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Re: Make BRAM/DRAM from FPGA accessible to Jailhouse on ZCU102

[Giovani Gracioli]

Em quinta-feira, 24 de maio de 2018 10:44:10 UTC-4, J. Kiszka  escreveu:
> On 2018-05-24 16:27, Giovani Gracioli wrote:
> >> On 2018-05-24 15:59, Giovani Gracioli wrote:
> >>> Not sure about MMU on Erika.
> >>>
> >>> Yes, the fault is reported as well. This address is just another memory. 
> >>> 0xA00.. is the BRAM and 0x500.. is the DRAM. Both have the same faulty 
> >>> behavior when the size is 2MB.
> >>
> >> You see the issue also when mapping some arbitrary DRAM region with a
> >> size of 2MB? Can you reproduce this with an IVSHMEM region as well? What
> >> if you increase the size beyond 2M, to 3M e.g.?
> >>
> >> Jan
> >>
> >> -- 
> >> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> >> Corporate Competence Center Embedded Linux
> > 
> > DRAM: works with 1MB, 3MB, and 32MB.
> >   does not work with 2MB.
> > 
> > BRAM (is limited to 2MB): works with 1MB, does not with 2MB.
> > 
> > IVSHMEM: tested with 1 and 2MB and worked in both cases.
> > 
> 
> That's not a consistent pattern yet because IVSHMEM and DRAM is just the
> same, use the same flags etc.
> 
> Can you send a config that demonstrates the DRAM issue? Ideally very
> close to the upstream zynqmp-zcu102 configs.
> 
> Thanks,
> Jan
> 
> -- 
> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> Corporate Competence Center Embedded Linux

Just tested these two attached and got:

Unhandled data write at 0x5(4)

FATAL: unhandled trap (exception class 0x24)
Cell state before exception:
 pc: 6944   lr: 6944 spsr: 6005 EL1
 sp: 6870  esr: 24 1 1970045
 x0:    x1: 9670   x2: 
 x3: 0004   x4: 27b8   x5: 
 x6:    x7: 0080   x8: 68b0
 x9: 23e0  x10:   x11: 9292
x12:   x13:   x14: 0020
x15:   x16:   x17: 
x18:   x19: 1118  x20: 92cf
x21: 00080070  x22: 0005  x23: 000a
x24:   x25:   x26: 
x27:   x28:   x29: 

Parking CPU 1 (Cell: "nfer")

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/*
 * Jailhouse, a Linux-based partitioning hypervisor
 *
 * Configuration for Xilinx ZynqMP ZCU102 eval board
 *
 * Copyright (c) Siemens AG, 2016
 *
 * Authors:
 *  Jan Kiszka 
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 * Reservation via device tree: 0x8..0x83fff
 */

#include 
#include 

#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))

struct {
	struct jailhouse_system header;
	__u64 cpus[1];
	struct jailhouse_memory mem_regions[7];
	struct jailhouse_irqchip irqchips[1];
	struct jailhouse_pci_device pci_devices[3];
} __attribute__((packed)) config = {
	.header = {
		.signature = JAILHOUSE_SYSTEM_SIGNATURE,
		.revision = JAILHOUSE_CONFIG_REVISION,
		.hypervisor_memory = {
			.phys_start = 0x8,
			.size =   0x00040,
		},
		.debug_console = {
			.address = 0xff00,
			.size = 0x1000,
			.flags = JAILHOUSE_CON1_TYPE_XUARTPS |
 JAILHOUSE_CON1_ACCESS_MMIO |
 JAILHOUSE_CON1_REGDIST_4 |
 JAILHOUSE_CON2_TYPE_ROOTPAGE,
		},
		.platform_info = {
			.pci_mmconfig_base = 0xfc00,
			.pci_mmconfig_end_bus = 0,
			.pci_is_virtual = 1,
			.arm = {
.gic_version = 2,
.gicd_base = 0xf901,
.gicc_base = 0xf902f000,
.gich_base = 0xf904,
.gicv_base = 0xf906f000,
.maintenance_irq = 25,
			},
		},
		.root_cell = {
			.name = "ZynqMP-ZCU102",

			.cpu_set_size = sizeof(config.cpus),
			.num_memory_regions = ARRAY_SIZE(config.mem_regions),
			.num_irqchips = ARRAY_SIZE(config.irqchips),
			.num_pci_devices = ARRAY_SIZE(config.pci_devices),

			.vpci_irq_base = 136-32,
		},
	},

	.cpus = {
		0xf,
	},

	.mem_regions = {
		/* MMIO (permissive) */ {
			.phys_start = 0xfd00,
			.virt_start = 0xfd00,
			.size =	  0x0300,
			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
		},
		/* RAM */ {
			.phys_start = 0x0,
			.virt_start = 0x0,
			.size = 0x8000,
			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE,
		},
		/* RAM */ {
			.phys_start = 0x80060,
			.virt_start = 0x80060,
			.size = 0x7fa0,
			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE,
		},
		/* IVSHMEM shared memory region for 00:00.0 */ {
			.phys_start = 0x80040,
			.virt_start = 0x80040,
			.size = 0x10,
			.flags = 

Re: Make BRAM/DRAM from FPGA accessible to Jailhouse on ZCU102

[Jan Kiszka]

On 2018-05-24 16:27, Giovani Gracioli wrote:
>> On 2018-05-24 15:59, Giovani Gracioli wrote:
>>> Not sure about MMU on Erika.
>>>
>>> Yes, the fault is reported as well. This address is just another memory. 
>>> 0xA00.. is the BRAM and 0x500.. is the DRAM. Both have the same faulty 
>>> behavior when the size is 2MB.
>>
>> You see the issue also when mapping some arbitrary DRAM region with a
>> size of 2MB? Can you reproduce this with an IVSHMEM region as well? What
>> if you increase the size beyond 2M, to 3M e.g.?
>>
>> Jan
>>
>> -- 
>> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
>> Corporate Competence Center Embedded Linux
> 
> DRAM: works with 1MB, 3MB, and 32MB.
>   does not work with 2MB.
> 
> BRAM (is limited to 2MB): works with 1MB, does not with 2MB.
> 
> IVSHMEM: tested with 1 and 2MB and worked in both cases.
> 

That's not a consistent pattern yet because IVSHMEM and DRAM is just the
same, use the same flags etc.

Can you send a config that demonstrates the DRAM issue? Ideally very
close to the upstream zynqmp-zcu102 configs.

Thanks,
Jan

-- 
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux

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Re: Make BRAM/DRAM from FPGA accessible to Jailhouse on ZCU102

[Giovani Gracioli]

> On 2018-05-24 15:59, Giovani Gracioli wrote:
> > Not sure about MMU on Erika.
> > 
> > Yes, the fault is reported as well. This address is just another memory. 
> > 0xA00.. is the BRAM and 0x500.. is the DRAM. Both have the same faulty 
> > behavior when the size is 2MB.
> 
> You see the issue also when mapping some arbitrary DRAM region with a
> size of 2MB? Can you reproduce this with an IVSHMEM region as well? What
> if you increase the size beyond 2M, to 3M e.g.?
> 
> Jan
> 
> -- 
> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> Corporate Competence Center Embedded Linux

DRAM: works with 1MB, 3MB, and 32MB.
  does not work with 2MB.

BRAM (is limited to 2MB): works with 1MB, does not with 2MB.

IVSHMEM: tested with 1 and 2MB and worked in both cases.

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Re: Make BRAM/DRAM from FPGA accessible to Jailhouse on ZCU102

[Giovani Gracioli]

Not sure about MMU on Erika.

Yes, the fault is reported as well. This address is just another memory. 
0xA00.. is the BRAM and 0x500.. is the DRAM. Both have the same faulty behavior 
when the size is 2MB.

> > Hi,
> > 
> > The configs are attached. I am running Erika on the non-root cell.
> 
> Does Erika enable the MMU? Is it prepared to map memory from higher
> addresses?
> 
> I'm now seeing in your configs that you map a region at 0x5 - Is
> the access fault reported for that address as well?
> 
> Jan
> 
> -- 
> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> Corporate Competence Center Embedded Linux

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Re: Make BRAM/DRAM from FPGA accessible to Jailhouse on ZCU102

[Jan Kiszka]

On 2018-05-24 15:44, Giovani Gracioli wrote:
> Hi,
> 
> The configs are attached. I am running Erika on the non-root cell.

Does Erika enable the MMU? Is it prepared to map memory from higher
addresses?

I'm now seeing in your configs that you map a region at 0x5 - Is
the access fault reported for that address as well?

Jan

-- 
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux

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Re: Make BRAM/DRAM from FPGA accessible to Jailhouse on ZCU102

[Giovani Gracioli]

Hi,

The configs are attached. I am running Erika on the non-root cell.

> > Don't know exactly why, but if I change the size for 1MB instead of 2MB, it 
> > works.
> > 
> > Is this because of this line in the mmu_cell.c?
> > 
> > size = MIN(region_size, NUM_TEMPORARY_PAGES * PAGE_SIZE);
> > 
> > Thus, is the maximum size of any memory region 1MB?
> > 
> 
> No, the minimum size is 4K on all supported architectures.
> 
> Without the configs you were using, it's hard to say where the mistake is.
> 
> Also, what kind of inmate are you booting in the non-root cell?
> 
> Jan
> 
> >> Hi,
> >>
> >> I checked the array sizes and they are correct. num_memory_regions uses 
> >> the ARRAY_SIZE macro:
> >>
> >> .num_memory_regions = ARRAY_SIZE(config.mem_regions)
> >>
> >> In Linux I can mmap and access the mapped region without errors.
> >>
> >> Any other thought?
> >>
> >>>
> >>> Maybe the region was not properly registered. Did you increase the
> >>> mem_regions array size? Did you change num_memory_regions so that it
> >>> requires manual updates? That's better discussed over the full config.
> >>>
> >>> Note that, if you want to share a region between root and non-root cell,
> >>> the latter also needs JAILHOUSE_MEM_ROOTSHARED.
> >>>
> >>> Jan
> 
> -- 
> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> Corporate Competence Center Embedded Linux

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/*
 * Jailhouse, a Linux-based partitioning hypervisor
 *
 * Configuration for Xilinx ZynqMP ZCU102 eval board
 *
 * Copyright (c) Siemens AG, 2016
 *
 * Authors:
 *  Jan Kiszka 
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 * Reservation via device tree: 0x8..0x83fff
 */

#include 
#include 

#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))

struct {
	struct jailhouse_system header;
	__u64 cpus[1];
	struct jailhouse_memory mem_regions[7];
	struct jailhouse_irqchip irqchips[1];
	struct jailhouse_pci_device pci_devices[3];
} __attribute__((packed)) config = {
	.header = {
		.signature = JAILHOUSE_SYSTEM_SIGNATURE,
		.revision = JAILHOUSE_CONFIG_REVISION,
		.hypervisor_memory = {
			.phys_start = 0x8,
			.size =   0x00040,
		},
		.debug_console = {
			.address = 0xff00,
			.size = 0x1000,
			.flags = JAILHOUSE_CON1_TYPE_XUARTPS |
 JAILHOUSE_CON1_ACCESS_MMIO |
 JAILHOUSE_CON1_REGDIST_4 |
 JAILHOUSE_CON2_TYPE_ROOTPAGE,
		},
		.platform_info = {
			.pci_mmconfig_base = 0xfc00,
			.pci_mmconfig_end_bus = 0,
			.pci_is_virtual = 1,
			.arm = {
.gic_version = 2,
.gicd_base = 0xf901,
.gicc_base = 0xf902f000,
.gich_base = 0xf904,
.gicv_base = 0xf906f000,
.maintenance_irq = 25,
			},
		},
		.root_cell = {
			.name = "ZynqMP-ZCU102",

			.cpu_set_size = sizeof(config.cpus),
			.num_memory_regions = ARRAY_SIZE(config.mem_regions),
			.num_irqchips = ARRAY_SIZE(config.irqchips),
			.num_pci_devices = ARRAY_SIZE(config.pci_devices),

			.vpci_irq_base = 136-32,
		},
	},

	.cpus = {
		0xf,
	},

	.mem_regions = {
		/* MMIO (permissive) */ {
			.phys_start = 0xfd00,
			.virt_start = 0xfd00,
			.size =	  0x0300,
			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
		},
		/* RAM */ {
			.phys_start = 0x0,
			.virt_start = 0x0,
			.size = 0x8000,
			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE,
		},
		/* RAM */ {
			.phys_start = 0x80060,
			.virt_start = 0x80060,
			.size = 0x7fa0,
			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE,
		},
		/* IVSHMEM shared memory region for 00:00.0 */ {
			.phys_start = 0x80040,
			.virt_start = 0x80040,
			.size = 0x10,
			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
		},
		/* IVSHMEM shared memory region for 00:02.0 */ {
			.phys_start = 0x80080,
			.virt_start = 0x80080,
			.size = 0x10,
			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
		},
		/* IVSHMEM shared memory region for 00:01.0 */ {
			.phys_start = 0x80070,
			.virt_start = 0x80070,
			.size = 0x10,
			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
		},
		/* BRAM */ {
			.phys_start = 0x5,
			.virt_start = 0x5,
			.size = 0x10, //1MB
			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
		},
	},

	.irqchips = {
		/* GIC */ {
			.address = 0xf901,
			.pin_base = 32,
			.pin_bitmap = {
0x, 0x, 0x, 0x,
			},
		},
	},

	.pci_devices = {
		/* 00:00.0 */ {
			.type = JAILHOUSE_PCI_TYPE_IVSHMEM,
			.bdf = 0,
			.bar_mask = {
0xff00, 0x, 0x,
0x, 0x, 0x,
			

Re: Make BRAM/DRAM from FPGA accessible to Jailhouse on ZCU102

[Jan Kiszka]

On 2018-05-23 20:53, Giovani Gracioli wrote:
> Don't know exactly why, but if I change the size for 1MB instead of 2MB, it 
> works.
> 
> Is this because of this line in the mmu_cell.c?
> 
> size = MIN(region_size, NUM_TEMPORARY_PAGES * PAGE_SIZE);
> 
> Thus, is the maximum size of any memory region 1MB?
> 

No, the minimum size is 4K on all supported architectures.

Without the configs you were using, it's hard to say where the mistake is.

Also, what kind of inmate are you booting in the non-root cell?

Jan

>> Hi,
>>
>> I checked the array sizes and they are correct. num_memory_regions uses the 
>> ARRAY_SIZE macro:
>>
>> .num_memory_regions = ARRAY_SIZE(config.mem_regions)
>>
>> In Linux I can mmap and access the mapped region without errors.
>>
>> Any other thought?
>>
>>>
>>> Maybe the region was not properly registered. Did you increase the
>>> mem_regions array size? Did you change num_memory_regions so that it
>>> requires manual updates? That's better discussed over the full config.
>>>
>>> Note that, if you want to share a region between root and non-root cell,
>>> the latter also needs JAILHOUSE_MEM_ROOTSHARED.
>>>
>>> Jan

-- 
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux

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Re: Make BRAM/DRAM from FPGA accessible to Jailhouse on ZCU102

[Giovani Gracioli]

Don't know exactly why, but if I change the size for 1MB instead of 2MB, it 
works.

Is this because of this line in the mmu_cell.c?

size = MIN(region_size, NUM_TEMPORARY_PAGES * PAGE_SIZE);

Thus, is the maximum size of any memory region 1MB?

> Hi,
> 
> I checked the array sizes and they are correct. num_memory_regions uses the 
> ARRAY_SIZE macro:
> 
> .num_memory_regions = ARRAY_SIZE(config.mem_regions)
> 
> In Linux I can mmap and access the mapped region without errors.
> 
> Any other thought?
> 
> > 
> > Maybe the region was not properly registered. Did you increase the
> > mem_regions array size? Did you change num_memory_regions so that it
> > requires manual updates? That's better discussed over the full config.
> > 
> > Note that, if you want to share a region between root and non-root cell,
> > the latter also needs JAILHOUSE_MEM_ROOTSHARED.
> > 
> > Jan

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Re: Make BRAM/DRAM from FPGA accessible to Jailhouse on ZCU102

[Giovani Gracioli]

Hi,

I checked the array sizes and they are correct. num_memory_regions uses the 
ARRAY_SIZE macro:

.num_memory_regions = ARRAY_SIZE(config.mem_regions)

In Linux I can mmap and access the mapped region without errors.

Any other thought?

> 
> Maybe the region was not properly registered. Did you increase the
> mem_regions array size? Did you change num_memory_regions so that it
> requires manual updates? That's better discussed over the full config.
> 
> Note that, if you want to share a region between root and non-root cell,
> the latter also needs JAILHOUSE_MEM_ROOTSHARED.
> 
> Jan

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Re: Make BRAM/DRAM from FPGA accessible to Jailhouse on ZCU102

[Jan Kiszka]

On 2018-05-18 20:50, Giovani Gracioli wrote:
> Hello,
> 
> I have a BRAM and DRAM blocks available on the FPGA side of the ZCU102 
> platform.
> 
> I would like to make them accessible for jailhouse cells. For instance, a 
> BRAM block is mapped to the 0xa000 address.
> 
> To do that, I inserted this address into the root and non-root cell 
> configurations as mem regions:
> 
> Non-root:
> 
> {
> .phys_start = 0x00A000,
> .virt_start = 0x00A000,
> .size = 0x20, //2MB
> .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE 
> },
> 
> Root:
> 
> {
> .phys_start = 0x00A000,
> .virt_start = 0x00A000,
> .size = 0x20, //2MB
> .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_EXECUTE,
> },
> 
> When I run the non-root cell and try to write into the address:
> 
> int *bram_ptr = (int *) 0x00A000;
> *bram_ptr = 10;
> 
> I got an unhandled data write at 0xa000. What am I missing here in the 
> configs?

Maybe the region was not properly registered. Did you increase the
mem_regions array size? Did you change num_memory_regions so that it
requires manual updates? That's better discussed over the full config.

Note that, if you want to share a region between root and non-root cell,
the latter also needs JAILHOUSE_MEM_ROOTSHARED.

Jan

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