Re: [Kicad-developers] Bug 1754130
Please table this conversation until we start talking about the new constraint management system as part of v6 development. I don't really have time right now an I would rather not loose any valuable input. I will open up the discussion once we have an initial draft in place. Cheers, Wayne On 1/14/19 5:31 PM, mdoes...@xs4all.nl wrote: > Hallo Wayne, > > Sorry for the repeat message, but I never managed to subscribe to the > mailing list using my usual e-mail account. > > I would be glad to elaborate on that. But the main point is that for > power electronics a net clearance is not all that usefull. The simplest > example is when you have a DC-DC converter which is supposed to have 4kV > isolation between input and output, but both the primary and secondary > circuits are 12V. > > Another example is a high voltage half bridge. You have for example the > 1kV and the 0V rail, and a switching node which is either 1kV or 0V. This > switching node has a gate driver attached to it which is low voltage (for > example 12V) within itself and needs only 0.2mm clearance. The gate driver > group of nets needs 3.2mm clearance from both the 1kV and 0V rail however. > > What Eagle does is that you can have 32 netclasses (I need more please > ;-) ). A clearance matrix gives the clearance between the netclasses > (and within the netclass itself on the diagonal), obviously this matrix > is symmetric. > > regards, > > Mark > > Wayne Stambaugh wrote: > > Hey Mark, > > Will do. This will give us a chance to better understand how to even > map this over to KiCad. I'm still no sure I even understand what is > meant by netclass to netclass clearance. > > Cheers, > > Wayne > ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] Bug 1754130
Hallo Wayne, Sorry for the repeat message, but I never managed to subscribe to the mailing list using my usual e-mail account. I would be glad to elaborate on that. But the main point is that for power electronics a net clearance is not all that usefull. The simplest example is when you have a DC-DC converter which is supposed to have 4kV isolation between input and output, but both the primary and secondary circuits are 12V. Another example is a high voltage half bridge. You have for example the 1kV and the 0V rail, and a switching node which is either 1kV or 0V. This switching node has a gate driver attached to it which is low voltage (for example 12V) within itself and needs only 0.2mm clearance. The gate driver group of nets needs 3.2mm clearance from both the 1kV and 0V rail however. What Eagle does is that you can have 32 netclasses (I need more please ;-) ). A clearance matrix gives the clearance between the netclasses (and within the netclass itself on the diagonal), obviously this matrix is symmetric. regards, Mark Wayne Stambaugh wrote: Hey Mark, Will do. This will give us a chance to better understand how to even map this over to KiCad. I'm still no sure I even understand what is meant by netclass to netclass clearance. Cheers, Wayne ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] Bug 1754130
While this is tangential to the thurst of this conversation, a comprehensive constraint system is incredibly important for many projects and I'm very happy to share and contribute on this topic if it can be of value. So, here we go... Netclass to netclass clearance would be a distance that all nets in one class should be kept from all nets in another class. For example, let's say I have an offline power supply delivering 24V output. I may create these net classes: Line: AC line Neut: AC neutral Pri_Gnd: Reference for primary circuits after AC rectification Pri_High: Rectified primary voltage Sec_Gnd: Reference for all secondary circuits Sec_24V: Secondary voltages more than 15V away from Sec_Gnd This might be a bit contrived and leaves out a lot of details, but I think it will shows the concept. Also, it would be common to use a flyback power supply in this example but we will ignore any fly back spikes that result in higher-than-nominal voltages that complicates things. We can know the distances required based on the design target of the product. IPC-2221 and UL 60065 are two documents which specify creepage distance based on voltage potential and are common points of reference when setting up constraints. So... there are a few ways to break down the distances required. By domain (primary domain and secondary domain): - Line, Neut, and all Pri_* classes must be kept at least 5mm from any Sec_* netclasses for creepage. - Sec_Gnd is a special case that requires less clearance from any Pri_* or AC mains voltage net. By netclass within domain: - I will need to keep Line and Neut some specified distance from each other. - Pri_Gnd and Pri_High must also be some specific distance from each other depending on the AC input voltage range my product will accept. - Sec_Gnd and Sec_24V will need to be some small distance away from each other. This is probably much easier to explain graphically for the uninitiated, but unfortunately I don't have anything handy. I can make something (and so can many others) or dig around online to see if there's something nice and descriptive if that would be helpful. On Mon, Jan 14, 2019 at 9:04 AM Wayne Stambaugh wrote: > Hey Mark, > > Will do. This will give us a chance to better understand how to even > map this over to KiCad. I'm still no sure I even understand what is > meant by netclass to netclass clearance. > > Cheers, > > Wayne > > On 1/14/2019 11:42 AM, mdoes...@xs4all.nl wrote: > > Hello Wayne, > > > > Please consider it on hold for now. Once kicad supports netclass to > > netclass clearances I will have another look. The dimensions are not > > copied yet, since I stopped working on it once I found out that all > > the unnamed nets lost their netclass after the first update from the > > schematic. This may be easy to fix or not, but at that point I decided > > to simply forget it. > > > > regards, > > > > Mark > > > > Wayne Stambaugh wrote: > > > > Hey Mark, > > > > On 1/11/2019 5:11 AM, mdoes...@xs4all.nl wrote: > > > Here's a patch to import the netclasses from eagle. > > > > There are a few minor coding policy issues. We now have clang > > formatting available when you perform a git commit if you would > prefer > > not to have to remember KiCad's formatting. You just have to > enable it > > in your git repo if that is your preference. > > > > It looks like there is some left over debugging code (using > std::cerr) > > that needs to be removed. If you want leave debugging support in > your > > code, please use wxLogTrace[1]. > > > > I looks like you are translating Eagle units directly to kicad's > pcb > > units. Is this valid? I don't know what internal units Eagle > uses for > > boards but KiCad uses 1nm. If Eagle doesn't use 1nm, then your > unit > > conversions are wrong. > > > > > > > > As already mentioned, all nets without a label are in the default > > > netclass. The clearances are ignored because I have no idea what > clearance > > > to use. The trackwidths are ignored, I've never used that and > saw no > > > reason to fix this since the patch isn't that usefull anyway. > > > > Does Eagle specify a default net clearance? If so, we should be > using > > that instead of the KiCad default net clearance for the nets not > > assigned to a netclass. > > > > Would our resident Eagle file format expert please take a look at > this > > patch to see if it makes sense? I'm not terribly familiar with the > > Eagle file format. > > > > Cheers, > > > > Wayne > > > > [1]: > > > https://docs.wxwidgets.org/3.0/group__group__funcmacro__log.html#gae28a46b220921cd87a6f75f0842294c5 > > > > > > > > regards, > > > > > > Mark. > > > > > > Seth Hillbrand wrote: > > > > > > Hi Mark- dir="auto">That would be great, thanks! dir="auto">-Seth > >
Re: [Kicad-developers] Bug 1754130
Hey Mark, Will do. This will give us a chance to better understand how to even map this over to KiCad. I'm still no sure I even understand what is meant by netclass to netclass clearance. Cheers, Wayne On 1/14/2019 11:42 AM, mdoes...@xs4all.nl wrote: > Hello Wayne, > > Please consider it on hold for now. Once kicad supports netclass to > netclass clearances I will have another look. The dimensions are not > copied yet, since I stopped working on it once I found out that all > the unnamed nets lost their netclass after the first update from the > schematic. This may be easy to fix or not, but at that point I decided > to simply forget it. > > regards, > > Mark > > Wayne Stambaugh wrote: > > Hey Mark, > > On 1/11/2019 5:11 AM, mdoes...@xs4all.nl wrote: > > Here's a patch to import the netclasses from eagle. > > There are a few minor coding policy issues. We now have clang > formatting available when you perform a git commit if you would prefer > not to have to remember KiCad's formatting. You just have to enable it > in your git repo if that is your preference. > > It looks like there is some left over debugging code (using std::cerr) > that needs to be removed. If you want leave debugging support in your > code, please use wxLogTrace[1]. > > I looks like you are translating Eagle units directly to kicad's pcb > units. Is this valid? I don't know what internal units Eagle uses for > boards but KiCad uses 1nm. If Eagle doesn't use 1nm, then your unit > conversions are wrong. > > > > > As already mentioned, all nets without a label are in the default > > netclass. The clearances are ignored because I have no idea what > clearance > > to use. The trackwidths are ignored, I've never used that and saw no > > reason to fix this since the patch isn't that usefull anyway. > > Does Eagle specify a default net clearance? If so, we should be using > that instead of the KiCad default net clearance for the nets not > assigned to a netclass. > > Would our resident Eagle file format expert please take a look at this > patch to see if it makes sense? I'm not terribly familiar with the > Eagle file format. > > Cheers, > > Wayne > > [1]: > > https://docs.wxwidgets.org/3.0/group__group__funcmacro__log.html#gae28a46b220921cd87a6f75f0842294c5 > > > > > regards, > > > > Mark. > > > > Seth Hillbrand wrote: > > > > Hi Mark- dir="auto">That would be great, thanks! dir="auto">-Seth > > > > > > ___ > > Mailing list: https://launchpad.net/~kicad-developers > > Post to : kicad-developers@lists.launchpad.net > > Unsubscribe : https://launchpad.net/~kicad-developers > > More help : https://help.launchpad.net/ListHelp > > > > ___ > Mailing list: https://launchpad.net/~kicad-developers > Post to : kicad-developers@lists.launchpad.net > Unsubscribe : https://launchpad.net/~kicad-developers > More help : https://help.launchpad.net/ListHelp > ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] Bug 1754130
Hello Wayne, Please consider it on hold for now. Once kicad supports netclass to netclass clearances I will have another look. The dimensions are not copied yet, since I stopped working on it once I found out that all the unnamed nets lost their netclass after the first update from the schematic. This may be easy to fix or not, but at that point I decided to simply forget it. regards, Mark Wayne Stambaugh wrote: Hey Mark, On 1/11/2019 5:11 AM, mdoes...@xs4all.nl wrote: > Here's a patch to import the netclasses from eagle. There are a few minor coding policy issues. We now have clang formatting available when you perform a git commit if you would prefer not to have to remember KiCad's formatting. You just have to enable it in your git repo if that is your preference. It looks like there is some left over debugging code (using std::cerr) that needs to be removed. If you want leave debugging support in your code, please use wxLogTrace[1]. I looks like you are translating Eagle units directly to kicad's pcb units. Is this valid? I don't know what internal units Eagle uses for boards but KiCad uses 1nm. If Eagle doesn't use 1nm, then your unit conversions are wrong. > > As already mentioned, all nets without a label are in the default > netclass. The clearances are ignored because I have no idea what clearance > to use. The trackwidths are ignored, I've never used that and saw no > reason to fix this since the patch isn't that usefull anyway. Does Eagle specify a default net clearance? If so, we should be using that instead of the KiCad default net clearance for the nets not assigned to a netclass. Would our resident Eagle file format expert please take a look at this patch to see if it makes sense? I'm not terribly familiar with the Eagle file format. Cheers, Wayne [1]: https://docs.wxwidgets.org/3.0/group__group__funcmacro__log.html#gae28a46b220921cd87a6f75f0842294c5 > > regards, > > Mark. > > Seth Hillbrand wrote: > > Hi Mark-That would be great, thanks!-Seth > > > ___ > Mailing list: https://launchpad.net/~kicad-developers > Post to : kicad-developers@lists.launchpad.net > Unsubscribe : https://launchpad.net/~kicad-developers > More help : https://help.launchpad.net/ListHelp > ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] Bug 1754130
Hey Mark, On 1/11/2019 5:11 AM, mdoes...@xs4all.nl wrote: > Here's a patch to import the netclasses from eagle. There are a few minor coding policy issues. We now have clang formatting available when you perform a git commit if you would prefer not to have to remember KiCad's formatting. You just have to enable it in your git repo if that is your preference. It looks like there is some left over debugging code (using std::cerr) that needs to be removed. If you want leave debugging support in your code, please use wxLogTrace[1]. I looks like you are translating Eagle units directly to kicad's pcb units. Is this valid? I don't know what internal units Eagle uses for boards but KiCad uses 1nm. If Eagle doesn't use 1nm, then your unit conversions are wrong. > > As already mentioned, all nets without a label are in the default > netclass. The clearances are ignored because I have no idea what clearance > to use. The trackwidths are ignored, I've never used that and saw no > reason to fix this since the patch isn't that usefull anyway. Does Eagle specify a default net clearance? If so, we should be using that instead of the KiCad default net clearance for the nets not assigned to a netclass. Would our resident Eagle file format expert please take a look at this patch to see if it makes sense? I'm not terribly familiar with the Eagle file format. Cheers, Wayne [1]: https://docs.wxwidgets.org/3.0/group__group__funcmacro__log.html#gae28a46b220921cd87a6f75f0842294c5 > > regards, > > Mark. > > Seth Hillbrand wrote: > > Hi Mark-That > would be great, thanks! dir="auto">-Seth > > > ___ > Mailing list: https://launchpad.net/~kicad-developers > Post to : kicad-developers@lists.launchpad.net > Unsubscribe : https://launchpad.net/~kicad-developers > More help : https://help.launchpad.net/ListHelp > ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] Bug 1754130
Here's a patch to import the netclasses from eagle.
As already mentioned, all nets without a label are in the default
netclass. The clearances are ignored because I have no idea what clearance
to use. The trackwidths are ignored, I've never used that and saw no
reason to fix this since the patch isn't that usefull anyway.
regards,
Mark.
Seth Hillbrand wrote:
Hi Mark-That
would be great, thanks!-Seth
>From c5f78b33f2020ac78b0fb7b40f457b7e73bbd4db Mon Sep 17 00:00:00 2001
From: Mark van Doesburg
Date: Fri, 13 Jul 2018 09:31:13 +0200
Subject: [PATCH] Copy netclasses during eagle import.
---
pcbnew/eagle_plugin.cpp | 51 +
pcbnew/eagle_plugin.h | 19 +++
2 files changed, 65 insertions(+), 5 deletions(-)
diff --git a/pcbnew/eagle_plugin.cpp b/pcbnew/eagle_plugin.cpp
index b676bad50..e9bd51e77 100644
--- a/pcbnew/eagle_plugin.cpp
+++ b/pcbnew/eagle_plugin.cpp
@@ -171,7 +171,6 @@ void ERULES::parse( wxXmlNode* aRules )
}
}
-
EAGLE_PLUGIN::EAGLE_PLUGIN() :
m_rules( new ERULES() ),
m_xpath( new XPATH() ),
@@ -341,6 +340,9 @@ void EAGLE_PLUGIN::loadAllSections( wxXmlNode* aDoc )
wxXmlNode* designrules = boardChildren["designrules"];
loadDesignRules( designrules );
+wxXmlNode* net_classes = boardChildren["classes"];
+loadNetClasses( net_classes );
+
m_xpath->pop();
}
@@ -385,6 +387,40 @@ void EAGLE_PLUGIN::loadDesignRules( wxXmlNode*
aDesignRules )
}
}
+void EAGLE_PLUGIN::loadNetClasses( wxXmlNode* NetClasses )
+{
+m_xpath->push( "classes" );
+auto stod = []( wxString i ) { return std::stod( static_cast(
i ) ); };
+auto stoul = []( wxString i ) { return std::stoul(
static_cast( i ) ); };
+for( wxXmlNode* child = NetClasses->GetChildren(); child; child =
child->GetNext() )
+{
+if( child->GetName() != "class" )
+continue;
+auto name = child->GetAttribute( "name" );
+auto number = stoul( child->GetAttribute( "number" ) );
+auto width = stod( child->GetAttribute( "width" ) );
+auto drill = stod( child->GetAttribute( "drill" ) );
+if( m_classes.size() <= number )
+m_classes.resize( number + 1 );
+m_classes[number] = ECLASS( name, number, width, drill );
+std::cerr << "Netclass " << name << " " << number << " " << width << "
" << drill
+ << std::endl;
+for( auto& p : m_classes )
+p.clearance.resize( m_classes.size() );
+/* Doesn't work ?
+ for(wxXmlNode* clearance = child->GetChildren(); clearance; clearance =
clearance->GetNext()) {
+ if(clearance->GetName() != "clearance")
+ continue;
+ auto other=stoi(child->GetAttribute("class"));
+ auto value=stod(child->GetAttribute("value"));
+ m_classes[number].clearance[other]=value;
+ }
+ */
+m_classes[number].ptr = std::make_shared( name );
+m_board->GetDesignSettings().m_NetClasses.Add( m_classes[number].ptr );
+}
+m_xpath->pop(); // "classes"
+}
void EAGLE_PLUGIN::loadLayerDefs( wxXmlNode* aLayers )
{
@@ -843,7 +879,6 @@ void EAGLE_PLUGIN::loadLibraries( wxXmlNode* aLibs )
m_xpath->pop();
}
-
void EAGLE_PLUGIN::loadElements( wxXmlNode* aElements )
{
if( !aElements )
@@ -1903,8 +1938,15 @@ void EAGLE_PLUGIN::loadSignals( wxXmlNode* aSignals )
zones.clear();
const wxString& netName = escapeName( net->GetAttribute( "name" ) );
+
m_board->Add( new NETINFO_ITEM( m_board, netName, netCode ) );
+ auto netClass = net -> GetAttribute( "class" );
+ if( netClass.length() )
+ {
+ m_classes[std::stoi( static_cast( netClass )
)].ptr->Add( netName );
+ }
+
m_xpath->Value( netName.c_str() );
// Get the first net item and iterate
@@ -1996,7 +2038,6 @@ void EAGLE_PLUGIN::loadSignals( wxXmlNode* aSignals )
m_xpath->pop();
}
-
else if( itemName == "via" )
{
m_xpath->push( "via" );
@@ -2064,7 +2105,6 @@ void EAGLE_PLUGIN::loadSignals( wxXmlNode* aSignals )
m_xpath->pop();
}
-
else if( itemName == "contactref" )
{
m_xpath->push( "contactref" );
@@ -2082,7 +2122,6 @@ void EAGLE_PLUGIN::loadSignals( wxXmlNode* aSignals )
sawPad = true;
}
-
else if( itemName == "polygon" )
{
m_xpath->push( "polygon" );
@@ -2117,6 +2156,8 @@ void EAGLE_PLUGIN::loadSignals( wxXmlNode* aSignals )
// Get next signal
net = net->GetNext();
}
+m_board->SynchronizeNetsAndNetClasses();
+
m_xpath->pop(); // "signals.signal"
}
diff --git a/pcbnew/eagle_plugin.h b/pcbnew/eagle_plugin.h
index e3df6d535..0a7b0605f 100644
--- a/pcbnew/eagle_plugin.h
+++
Re: [Kicad-developers] Bug 1754130
Eagle is also very limited in that regard. But at least they can create a 32x32 matrix with clearances. Converting a PCB with contraints works (except the clearance matrix), but unfortunately many of the nets in the design I converted were unnamed nets. At the first conversion from the schematic all those nets lost their netclass. I'll cleanup the patch I have, hopefully tomorrow. regards, Mark. Maciej Suminski wrote: Hi Mark, I do not remember exactly how net classes work in Eagle, but if you can specify there anything that is supported by KiCad (track width, via size, etc.) then it makes sense to handle at least that part. We can implement the remaining settings as soon as the DRC receives the planned upgrade. Cheers, Orson On 1/10/19 3:56 PM, Wayne Stambaugh wrote: > Hi Mark, > > Thanks for the information. Part of version 6 development is to design > a better constraint system which netclass to netclass clearance will > most likely be included. At that point, importing this form Eagle will > make sense assuming your assessment is correct. This obviously requires > a file format change which which would violate the project policy of not > making file format changes during a stable version series. I will > change the bug report milestone to v6 unless someone else can think of a > reason to not change it. > > Cheers, > > Wayne > > On 1/10/2019 1:42 AM, mdoes...@xs4all.nl wrote: >> I just had a look at the pending buglist and saw #1754130 Eagle import >> ignores net class and net class settings. >> >> I have a patch for that, but the reason I did not post it, is because >> it is pretty useless (for me at least). Kicad does not support setting >> netclass to netclass clearances, but eagle does. Also the netnames are >> changed at the first conversion from schematic to PCB. >> >> If there still interest in this patch, I can (clean it up and) post it. >> >> regards, >> >> Mark. >> >> ___ >> Mailing list: https://launchpad.net/~kicad-developers >> Post to : kicad-developers@lists.launchpad.net >> Unsubscribe : https://launchpad.net/~kicad-developers >> More help : https://help.launchpad.net/ListHelp >> > > ___ > Mailing list: https://launchpad.net/~kicad-developers > Post to : kicad-developers@lists.launchpad.net > Unsubscribe : https://launchpad.net/~kicad-developers > More help : https://help.launchpad.net/ListHelp > ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] Bug 1754130
I agree that we should preserve as much information as possible. So for net classes that would be clearance, track width, via diameter, via drill, uvia diameter, uvia drill, and all associated nets. Everything else will have to wait until our constraint system is in place. If the patch handles that, then it's something that would be worth looking at. Cheers, Wayne On 1/10/2019 11:26 AM, Maciej Suminski wrote: > Hi Mark, > > I do not remember exactly how net classes work in Eagle, but if you can > specify there anything that is supported by KiCad (track width, via > size, etc.) then it makes sense to handle at least that part. We can > implement the remaining settings as soon as the DRC receives the planned > upgrade. > > Cheers, > Orson > > On 1/10/19 3:56 PM, Wayne Stambaugh wrote: >> Hi Mark, >> >> Thanks for the information. Part of version 6 development is to design >> a better constraint system which netclass to netclass clearance will >> most likely be included. At that point, importing this form Eagle will >> make sense assuming your assessment is correct. This obviously requires >> a file format change which which would violate the project policy of not >> making file format changes during a stable version series. I will >> change the bug report milestone to v6 unless someone else can think of a >> reason to not change it. >> >> Cheers, >> >> Wayne >> >> On 1/10/2019 1:42 AM, mdoes...@xs4all.nl wrote: >>> I just had a look at the pending buglist and saw #1754130 Eagle import >>> ignores net class and net class settings. >>> >>> I have a patch for that, but the reason I did not post it, is because >>> it is pretty useless (for me at least). Kicad does not support setting >>> netclass to netclass clearances, but eagle does. Also the netnames are >>> changed at the first conversion from schematic to PCB. >>> >>> If there still interest in this patch, I can (clean it up and) post it. >>> >>> regards, >>> >>> Mark. >>> >>> ___ >>> Mailing list: https://launchpad.net/~kicad-developers >>> Post to : kicad-developers@lists.launchpad.net >>> Unsubscribe : https://launchpad.net/~kicad-developers >>> More help : https://help.launchpad.net/ListHelp >>> >> >> ___ >> Mailing list: https://launchpad.net/~kicad-developers >> Post to : kicad-developers@lists.launchpad.net >> Unsubscribe : https://launchpad.net/~kicad-developers >> More help : https://help.launchpad.net/ListHelp >> > > > ___ > Mailing list: https://launchpad.net/~kicad-developers > Post to : kicad-developers@lists.launchpad.net > Unsubscribe : https://launchpad.net/~kicad-developers > More help : https://help.launchpad.net/ListHelp > ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] Bug 1754130
Hi Mark, I do not remember exactly how net classes work in Eagle, but if you can specify there anything that is supported by KiCad (track width, via size, etc.) then it makes sense to handle at least that part. We can implement the remaining settings as soon as the DRC receives the planned upgrade. Cheers, Orson On 1/10/19 3:56 PM, Wayne Stambaugh wrote: > Hi Mark, > > Thanks for the information. Part of version 6 development is to design > a better constraint system which netclass to netclass clearance will > most likely be included. At that point, importing this form Eagle will > make sense assuming your assessment is correct. This obviously requires > a file format change which which would violate the project policy of not > making file format changes during a stable version series. I will > change the bug report milestone to v6 unless someone else can think of a > reason to not change it. > > Cheers, > > Wayne > > On 1/10/2019 1:42 AM, mdoes...@xs4all.nl wrote: >> I just had a look at the pending buglist and saw #1754130 Eagle import >> ignores net class and net class settings. >> >> I have a patch for that, but the reason I did not post it, is because >> it is pretty useless (for me at least). Kicad does not support setting >> netclass to netclass clearances, but eagle does. Also the netnames are >> changed at the first conversion from schematic to PCB. >> >> If there still interest in this patch, I can (clean it up and) post it. >> >> regards, >> >> Mark. >> >> ___ >> Mailing list: https://launchpad.net/~kicad-developers >> Post to : kicad-developers@lists.launchpad.net >> Unsubscribe : https://launchpad.net/~kicad-developers >> More help : https://help.launchpad.net/ListHelp >> > > ___ > Mailing list: https://launchpad.net/~kicad-developers > Post to : kicad-developers@lists.launchpad.net > Unsubscribe : https://launchpad.net/~kicad-developers > More help : https://help.launchpad.net/ListHelp > signature.asc Description: OpenPGP digital signature ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] Bug 1754130
Hi Mark, Thanks for the information. Part of version 6 development is to design a better constraint system which netclass to netclass clearance will most likely be included. At that point, importing this form Eagle will make sense assuming your assessment is correct. This obviously requires a file format change which which would violate the project policy of not making file format changes during a stable version series. I will change the bug report milestone to v6 unless someone else can think of a reason to not change it. Cheers, Wayne On 1/10/2019 1:42 AM, mdoes...@xs4all.nl wrote: > I just had a look at the pending buglist and saw #1754130 Eagle import > ignores net class and net class settings. > > I have a patch for that, but the reason I did not post it, is because > it is pretty useless (for me at least). Kicad does not support setting > netclass to netclass clearances, but eagle does. Also the netnames are > changed at the first conversion from schematic to PCB. > > If there still interest in this patch, I can (clean it up and) post it. > > regards, > > Mark. > > ___ > Mailing list: https://launchpad.net/~kicad-developers > Post to : kicad-developers@lists.launchpad.net > Unsubscribe : https://launchpad.net/~kicad-developers > More help : https://help.launchpad.net/ListHelp > ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] Bug 1754130
Hi Mark-That would be great, thanks!-Seth___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
[Kicad-developers] Bug 1754130
I just had a look at the pending buglist and saw #1754130 Eagle import ignores net class and net class settings. I have a patch for that, but the reason I did not post it, is because it is pretty useless (for me at least). Kicad does not support setting netclass to netclass clearances, but eagle does. Also the netnames are changed at the first conversion from schematic to PCB. If there still interest in this patch, I can (clean it up and) post it. regards, Mark. ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
