RE: [PATCH 0/2] OMAP3: cpuidle: prevent CORE pwrdm from entering low-power state when DSS active
-Original Message-
From: ext Paul Walmsley [mailto:p...@pwsan.com]
Sent: 02 March, 2011 00:49
To: linux-omap@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
Kristo Tero (Nokia-MS/Tampere)
Subject: [PATCH 0/2] OMAP3: cpuidle: prevent CORE pwrdm from entering
low-power state when DSS active
This series prevents the OMAP3 CPUIdle code from programming the CORE
powerdomain to enter any power state lower than ON when the DSS power
domain
is ON. (The assumption is that in this case, the DSS is active, DMA'ing
lines from RAM and displaying them somewhere.)
Tero, please don't hesitate to comment on the patch from you if I got
the
commit message wrong.
Hi Paul,
It looks good to me.
- Paul
---
Tero Kristo (1):
OMAP3: cpuidle: prevent CORE power domain from going to RET or OFF
when DSS is on
Paul Walmsley (1):
OMAP3: cpuidle: add more details to the DSS-related CORE power
domain state restriction
arch/arm/mach-omap2/cpuidle34xx.c | 36
++--
1 files changed, 34 insertions(+), 2 deletions(-)
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RE: [PATCH 6/7] OMAP: Serial: Allow UART parameters to be configured from board file
Hi,
-Original Message-
From: Govindraj [mailto:govindraj...@gmail.com]
Sent: Wednesday, March 02, 2011 1:11 PM
To: Sricharan R
Cc: Govindraj.R; linux-omap@vger.kernel.org;
linux-ser...@vger.kernel.org;
linux-arm-ker...@lists.infradead.org; Jon Hunter; Tony Lindgren; Benoit
Cousson; Kevin Hilman; Paul Walmsley; Rajendra Nayak; Deepak Kattungal
Subject: Re: [PATCH 6/7] OMAP: Serial: Allow UART parameters to be
configured from board file
On Wed, Mar 2, 2011 at 12:46 AM, Sricharan R r.sricha...@ti.com wrote:
Hi,
diff --git a/arch/arm/mach-omap2/serial.c
b/arch/arm/mach-omap2/serial.c
index 755f4aa..530e9e3 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -44,6 +44,15 @@
static int omap_uart_con_id __initdata = -1;
+static struct omap_uart_port_info omap_serial_default_info[] = {
+ {
+ .dma_enabled = 0,
+ .dma_rx_buf_size = DEFAULT_RXDMA_BUFSIZE,
+ .dma_rx_timeout = DEFAULT_RXDMA_TIMEOUT,
+ .idle_timeout = DEFAULT_IDLE_TIMEOUT,
+ },
+};
+
static int uart_idle_hwmod(struct omap_device *od)
{
omap_hwmod_idle(od-hwmods[0]);
@@ -66,6 +75,54 @@ static struct omap_device_pm_latency
omap_uart_latency[]
= {
},
};
+#ifdef CONFIG_OMAP_MUX
+static struct omap_device_pad default_serial0_pads[] __initdata = {
+ {
+ .name = uart1_rx.uart1_rx,
+ .flags = OMAP_DEVICE_PAD_REMUX |
OMAP_DEVICE_PAD_WAKEUP,
+ .enable = OMAP_MUX_MODE0,
+ },
+};
+
+static struct omap_device_pad default_serial1_pads[] __initdata = {
+ {
+ .name = uart2_rx.uart2_rx,
+ .flags = OMAP_DEVICE_PAD_REMUX |
OMAP_DEVICE_PAD_WAKEUP,
+ .enable = OMAP_MUX_MODE0,
+ },
+};
+
+static struct omap_device_pad default_serial2_pads[] __initdata = {
+ {
+ .name = uart3_rx_irrx.uart3_rx_irrx,
+ .flags = OMAP_DEVICE_PAD_REMUX |
OMAP_DEVICE_PAD_WAKEUP,
+ .enable = OMAP_MUX_MODE0,
+ },
+};
+
+static struct omap_device_pad default_omap36xx_serial3_pads[]
__initdata
=
{
+ {
+ .name = gpmc_wait3.uart4_rx,
+ .flags = OMAP_DEVICE_PAD_REMUX |
OMAP_DEVICE_PAD_WAKEUP,
+ .enable = OMAP_MUX_MODE2,
+ },
+};
+
+static struct omap_device_pad default_omap4_serial3_pads[] __initdata
=
{
+ {
+ .name = uart4_rx.uart4_rx,
+ .flags = OMAP_DEVICE_PAD_REMUX |
OMAP_DEVICE_PAD_WAKEUP,
+ .enable = OMAP_MUX_MODE0,
+ },
+};
Here only the UART RX pins are muxed, so what about the cts, rts, tx
pins?
The intention here is to enable wakeup capabilities for uart rx pad.
AFAIK most of the boards are currently dependent on bootloader for
uart-muxing if any board is not dependent on bootloader then we
can use omap_serial_init_port along with board_mux_info from board.
Yes. The idea is to be independent of the bootloaders for mux settings.
Prior to this change uart wakeup is based on rx_pad and we were
populating
offset and using omap_ctrl api's to read/write which is cleaned up now.
Most of boards are dependent on uart-rx wakeup to avoid breaking any
board support we
are using omap_serial_init by filling default values, which provides
us with same
environment but with right approach towards handling mux data with a
handshake with
hwmod framework.
Now, in this change only the RX pin is configured. So if some board uses
omap_serial_init then only the RX is going to be configured.
How will they configure the rest of the pins?
They cannot call omap_serial_init_port after this just to configure the
rest of the mux pins( cts, rts, tx).
So data which is passed from omap_serial_init should have the
configuration
for all the pins, and this default data should be consistent across
atleast
some boards, so that they can use this. This will reduce the data
duplication across board files.
If this is not true, then all the pads can be configured from the board
files itself using omap_serial_init_port and you can set the required
RX wakeup capability there as well.
So if any board needs specific mux they can go ahead and add required
mux data in
board file and use map_serial_init_port instead of current
omap_serial_init.
Is it consistent that across all socs that only UART3 would have
UART/IRDA
functions capability so that serial2 pads can always be called
rx_irxx
?.
Yes from OMAP2420 to OMAP4430 uart3 can used as irda.
Ok.
--
Thanks,
Govindraj.R
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[PATCH] HACK: OMAP: DSS2: Fix OMAP2_DSS_USE_DSI_PLL
When using OMAP2_DSS_USE_DSI_PLL, which selects DSI PLL as source clock
for DISPC, the DSI needs the vdds_dsi regulator. Latest regulator
changes broke this, causing the the code to not acquire the regulator
when using OMAP2_DSS_USE_DSI_PLL.
This patch acquires the vdds_dsi regulator in dsi_pll_init(), fixing the
issue. This is is just a quick hack to get the OMAP2_DSS_USE_DSI_PLL
option working. There shouldn't be any other downside in this solution
than some extra lines of code.
OMAP2_DSS_USE_DSI_PLL is itself a big hack, and should be removed, and
the feature itself should be implemented in a more sane way. However,
the solution is not trivial, and people are using DSI PLL to get more
exact pixel clocks, so this hack is an acceptable temporary solution for
the time being.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
drivers/video/omap2/dss/dsi.c | 20
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index c3019d9..6f4f19d 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -1105,6 +1105,26 @@ int dsi_pll_init(struct omap_dss_device *dssdev, bool
enable_hsclk,
DSSDBG(PLL init\n);
+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
+ /*
+* HACK: this is just a quick hack to get the USE_DSI_PLL
+* option working. USE_DSI_PLL is itself a big hack, and
+* should be removed.
+*/
+ if (dsi.vdds_dsi_reg == NULL) {
+ struct regulator *vdds_dsi;
+
+ vdds_dsi = regulator_get(dsi.pdev-dev, vdds_dsi);
+
+ if (IS_ERR(vdds_dsi)) {
+ DSSERR(can't get VDDS_DSI regulator\n);
+ return PTR_ERR(vdds_dsi);
+ }
+
+ dsi.vdds_dsi_reg = vdds_dsi;
+ }
+#endif
+
enable_clocks(1);
dsi_enable_pll_clock(1);
--
1.7.1
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Re: linux-next: manual merge of the usb tree with the omap tree
On Wed, Mar 02, 2011 at 04:57:46PM +1100, Stephen Rothwell wrote:
Hi Greg,
Today's linux-next merge of the usb tree got a conflict in
drivers/usb/musb/musb_core.h between commit
59b479e0985f0b795d68331d6443a7f89c47768d (omap: Start using
CONFIG_SOC_OMAP) from the omap tree and commit
da68ccec210c45eb99e461ad31b499b4e7043c41 (usb: musb: Remove platform
context save/restore API) from the usb tree.
The latter removed the code modified by the former, so I did that.
Yeah, I was about to send a resolution to Tony. Here's what I came up
with (too big though):
commit d12f1cd19b7e79087df1ea197ffe81b0b67f2bc3
Merge: abba63e 53689ac
Author: Felipe Balbi ba...@ti.com
Date: Tue Mar 1 17:14:26 2011 +0200
Merge branch 'for-next' into tst
Conflicts:
arch/arm/mach-omap2/board-4430sdp.c
arch/arm/mach-omap2/board-omap3evm.c
arch/arm/mach-omap2/usb-musb.c
arch/arm/plat-omap/include/plat/usb.h
drivers/usb/musb/musb_core.h
Signed-off-by: Felipe Balbi ba...@ti.com
diff --cc arch/arm/mach-omap2/board-3430sdp.c
index 8950ecc,7542ba5..d7aa25f
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@@ -801,10 -813,10 +801,10 @@@ static void __init omap_3430sdp_init(vo
omap_serial_init();
usb_musb_init(musb_board_data);
board_smc91x_init();
- board_flash_init(sdp_flash_partitions, chip_sel_3430);
+ board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
sdp3430_display_init();
enable_board_wakeup_source();
- usb_ehci_init(ehci_pdata);
+ usbhs_init(usbhs_bdata);
}
MACHINE_START(OMAP_3430SDP, OMAP3430 3430SDP board)
diff --cc arch/arm/mach-omap2/board-3630sdp.c
index 8d1c435,deed2db..d474697
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@@ -209,9 -209,9 +209,9 @@@ static void __init omap_sdp_init(void
zoom_peripherals_init();
zoom_display_init();
board_smc91x_init();
- board_flash_init(sdp_flash_partitions, chip_sel_sdp);
+ board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16);
enable_board_wakeup_source();
- usb_ehci_init(ehci_pdata);
+ usbhs_init(usbhs_bdata);
}
MACHINE_START(OMAP_3630SDP, OMAP 3630SDP board)
diff --cc arch/arm/mach-omap2/board-am3517crane.c
index ae3a83d,e3a194f..36bff55
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@@ -56,12 -56,13 +56,12 @@@ static void __init am3517_crane_init_ea
omap2_init_common_infrastructure();
omap2_init_common_devices(NULL, NULL);
- omap_init_irq();
}
- static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
- .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
- .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
- .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+ static struct usbhs_omap_board_data usbhs_bdata __initdata = {
+ .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
.phy_reset = true,
.reset_gpio_port[0] = GPIO_USB_NRESET,
diff --cc arch/arm/mach-omap2/board-igep0020.c
index 54e6318,f9f5344..0d3b0ad
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@@ -685,10 -697,9 +685,10 @@@ static void __init igep2_init(void
/* Register I2C busses and drivers */
igep2_i2c_init();
platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices));
+ omap_display_init(igep2_dss_data);
omap_serial_init();
usb_musb_init(musb_board_data);
- usb_ehci_init(ehci_pdata);
+ usbhs_init(usbhs_bdata);
igep2_flash_init();
igep2_leds_init();
diff --cc arch/arm/mach-omap2/board-omap3evm.c
index 7341f96,38a2d91..e307fa4
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@@ -733,13 -631,18 +733,13 @@@ static void __init omap3_evm_init_early
omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
omap2_init_common_infrastructure();
omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
- omap_init_irq();
}
- static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
-static struct platform_device *omap3_evm_devices[] __initdata = {
- omap3_evm_dss_device,
-};
-
+ static struct usbhs_omap_board_data usbhs_bdata __initdata = {
- .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
- .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
- .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+ .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+ .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
.phy_reset = true,
/* PHY reset GPIO will be runtime programmed based on EVM version */
diff --cc arch/arm/mach-omap2/board-omap4panda.c
index
Re: [PATCH] HACK: OMAP: DSS2: Fix OMAP2_DSS_USE_DSI_PLL
On Wed, Mar 2, 2011 at 1:50 PM, Tomi Valkeinen tomi.valkei...@ti.com wrote:
When using OMAP2_DSS_USE_DSI_PLL, which selects DSI PLL as source clock
for DISPC, the DSI needs the vdds_dsi regulator. Latest regulator
changes broke this, causing the the code to not acquire the regulator
when using OMAP2_DSS_USE_DSI_PLL.
This patch acquires the vdds_dsi regulator in dsi_pll_init(), fixing the
issue. This is is just a quick hack to get the OMAP2_DSS_USE_DSI_PLL
option working. There shouldn't be any other downside in this solution
than some extra lines of code.
OMAP2_DSS_USE_DSI_PLL is itself a big hack, and should be removed, and
the feature itself should be implemented in a more sane way. However,
the solution is not trivial, and people are using DSI PLL to get more
exact pixel clocks, so this hack is an acceptable temporary solution for
the time being.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
drivers/video/omap2/dss/dsi.c | 20
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index c3019d9..6f4f19d 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -1105,6 +1105,26 @@ int dsi_pll_init(struct omap_dss_device *dssdev, bool
enable_hsclk,
DSSDBG(PLL init\n);
+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
+ /*
+ * HACK: this is just a quick hack to get the USE_DSI_PLL
+ * option working. USE_DSI_PLL is itself a big hack, and
+ * should be removed.
+ */
+ if (dsi.vdds_dsi_reg == NULL) {
+ struct regulator *vdds_dsi;
+
+ vdds_dsi = regulator_get(dsi.pdev-dev, vdds_dsi);
+
+ if (IS_ERR(vdds_dsi)) {
+ DSSERR(can't get VDDS_DSI regulator\n);
+ return PTR_ERR(vdds_dsi);
+ }
+
+ dsi.vdds_dsi_reg = vdds_dsi;
+ }
+#endif
+
enable_clocks(1);
dsi_enable_pll_clock(1);
The hack might be temporarily acceptable.
But I think there should be a matching regulator_put in dsi_pll_uinit.
--
1.7.1
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Re: [PATCH] HACK: OMAP: DSS2: Fix OMAP2_DSS_USE_DSI_PLL
On Wed, 2011-03-02 at 02:30 -0600, John S wrote:
On Wed, Mar 2, 2011 at 1:50 PM, Tomi Valkeinen tomi.valkei...@ti.com wrote:
When using OMAP2_DSS_USE_DSI_PLL, which selects DSI PLL as source clock
for DISPC, the DSI needs the vdds_dsi regulator. Latest regulator
changes broke this, causing the the code to not acquire the regulator
when using OMAP2_DSS_USE_DSI_PLL.
This patch acquires the vdds_dsi regulator in dsi_pll_init(), fixing the
issue. This is is just a quick hack to get the OMAP2_DSS_USE_DSI_PLL
option working. There shouldn't be any other downside in this solution
than some extra lines of code.
OMAP2_DSS_USE_DSI_PLL is itself a big hack, and should be removed, and
the feature itself should be implemented in a more sane way. However,
the solution is not trivial, and people are using DSI PLL to get more
exact pixel clocks, so this hack is an acceptable temporary solution for
the time being.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
drivers/video/omap2/dss/dsi.c | 20
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index c3019d9..6f4f19d 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -1105,6 +1105,26 @@ int dsi_pll_init(struct omap_dss_device *dssdev,
bool enable_hsclk,
DSSDBG(PLL init\n);
+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
+ /*
+* HACK: this is just a quick hack to get the USE_DSI_PLL
+* option working. USE_DSI_PLL is itself a big hack, and
+* should be removed.
+*/
+ if (dsi.vdds_dsi_reg == NULL) {
+ struct regulator *vdds_dsi;
+
+ vdds_dsi = regulator_get(dsi.pdev-dev, vdds_dsi);
+
+ if (IS_ERR(vdds_dsi)) {
+ DSSERR(can't get VDDS_DSI regulator\n);
+ return PTR_ERR(vdds_dsi);
+ }
+
+ dsi.vdds_dsi_reg = vdds_dsi;
+ }
+#endif
+
enable_clocks(1);
dsi_enable_pll_clock(1);
The hack might be temporarily acceptable.
But I think there should be a matching regulator_put in dsi_pll_uinit.
The regulator_put() is in dsi_exit().
The reasoning here is that we only want to get the regulator if the DSI
is actually used. Otherwise every board file should define all the
regulators, even if the board in question wouldn't even use DSI. Thus we
cannot regulator_get() in the probe of DSI driver, but only later when a
display actually uses DSI.
But when we have the regulator, we keep a reference to it until the DSI
driver is unloaded (dsi_exit). It is asymmetric, but I don't see any
reason to release the regulator when, for example, the display is
blanked.
Tomi
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Re: [PATCH 6/7] OMAP: Serial: Allow UART parameters to be configured from board file
On Wed, Mar 2, 2011 at 1:49 PM, Sricharan R r.sricha...@ti.com wrote:
Hi,
-Original Message-
From: Govindraj [mailto:govindraj...@gmail.com]
Sent: Wednesday, March 02, 2011 1:11 PM
To: Sricharan R
Cc: Govindraj.R; linux-omap@vger.kernel.org;
linux-ser...@vger.kernel.org;
linux-arm-ker...@lists.infradead.org; Jon Hunter; Tony Lindgren; Benoit
Cousson; Kevin Hilman; Paul Walmsley; Rajendra Nayak; Deepak Kattungal
Subject: Re: [PATCH 6/7] OMAP: Serial: Allow UART parameters to be
configured from board file
On Wed, Mar 2, 2011 at 12:46 AM, Sricharan R r.sricha...@ti.com wrote:
Hi,
diff --git a/arch/arm/mach-omap2/serial.c
b/arch/arm/mach-omap2/serial.c
index 755f4aa..530e9e3 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -44,6 +44,15 @@
static int omap_uart_con_id __initdata = -1;
+static struct omap_uart_port_info omap_serial_default_info[] = {
+ {
+ .dma_enabled = 0,
+ .dma_rx_buf_size = DEFAULT_RXDMA_BUFSIZE,
+ .dma_rx_timeout = DEFAULT_RXDMA_TIMEOUT,
+ .idle_timeout = DEFAULT_IDLE_TIMEOUT,
+ },
+};
+
static int uart_idle_hwmod(struct omap_device *od)
{
omap_hwmod_idle(od-hwmods[0]);
@@ -66,6 +75,54 @@ static struct omap_device_pm_latency
omap_uart_latency[]
= {
},
};
+#ifdef CONFIG_OMAP_MUX
+static struct omap_device_pad default_serial0_pads[] __initdata = {
+ {
+ .name = uart1_rx.uart1_rx,
+ .flags = OMAP_DEVICE_PAD_REMUX |
OMAP_DEVICE_PAD_WAKEUP,
+ .enable = OMAP_MUX_MODE0,
+ },
+};
+
+static struct omap_device_pad default_serial1_pads[] __initdata = {
+ {
+ .name = uart2_rx.uart2_rx,
+ .flags = OMAP_DEVICE_PAD_REMUX |
OMAP_DEVICE_PAD_WAKEUP,
+ .enable = OMAP_MUX_MODE0,
+ },
+};
+
+static struct omap_device_pad default_serial2_pads[] __initdata = {
+ {
+ .name = uart3_rx_irrx.uart3_rx_irrx,
+ .flags = OMAP_DEVICE_PAD_REMUX |
OMAP_DEVICE_PAD_WAKEUP,
+ .enable = OMAP_MUX_MODE0,
+ },
+};
+
+static struct omap_device_pad default_omap36xx_serial3_pads[]
__initdata
=
{
+ {
+ .name = gpmc_wait3.uart4_rx,
+ .flags = OMAP_DEVICE_PAD_REMUX |
OMAP_DEVICE_PAD_WAKEUP,
+ .enable = OMAP_MUX_MODE2,
+ },
+};
+
+static struct omap_device_pad default_omap4_serial3_pads[] __initdata
=
{
+ {
+ .name = uart4_rx.uart4_rx,
+ .flags = OMAP_DEVICE_PAD_REMUX |
OMAP_DEVICE_PAD_WAKEUP,
+ .enable = OMAP_MUX_MODE0,
+ },
+};
Here only the UART RX pins are muxed, so what about the cts, rts, tx
pins?
The intention here is to enable wakeup capabilities for uart rx pad.
AFAIK most of the boards are currently dependent on bootloader for
uart-muxing if any board is not dependent on bootloader then we
can use omap_serial_init_port along with board_mux_info from board.
Yes. The idea is to be independent of the bootloaders for mux settings.
Prior to this change uart wakeup is based on rx_pad and we were
populating
offset and using omap_ctrl api's to read/write which is cleaned up now.
Most of boards are dependent on uart-rx wakeup to avoid breaking any
board support we
are using omap_serial_init by filling default values, which provides
us with same
environment but with right approach towards handling mux data with a
handshake with
hwmod framework.
Now, in this change only the RX pin is configured. So if some board uses
omap_serial_init then only the RX is going to be configured.
How will they configure the rest of the pins?
They should call omap_serial_init_port to configure each individual uart with
mux_info filled and not use omap_serial_init.
If any board is not dependent for mux from u-boot then they use above said
init_port func.
They cannot call omap_serial_init_port after this just to configure the
rest of the mux pins( cts, rts, tx).
No. You need to use either omap_serial_init_port or omap_serial_init
you cannot call both apis from board file please refer to both func
documentation.
Also please note i am not configuring all uart pins for pullups and pull downs
with this patch series and its not related to this patch series.
I am only enabling wakeup-enable pin for rx as it was done before.
So data which is passed from omap_serial_init should have the
configuration
for all the pins, and this default data should be consistent across
atleast
some boards, so that they can use this. This will reduce the data
duplication across board files.
If this is not true, then all the pads can be configured from the board
files itself using omap_serial_init_port and you can set the required
RX wakeup capability there as well.
Yes that be done but currently but that is not in my intention here
with my patch
I just want to retain rx wakeup by default to avoid breaking support
for any board.
Adding pin mux for each
Re: [PATCH 0/2 v5] twl4030-madc driver
Hi Keerthy, On Tue, Mar 01, 2011 at 07:12:06PM +0530, Keerthy wrote: MADC(Monitoring ADC) driver enables monitoring analog signals using analog-to-digital conversion (ADC) on the input source. The previous discussion concluded in keeping the generic ADC functionality and the hwmon separate. The discussion can be found here: http://www.mail-archive.com/linux-omap@vger.kernel.org/msg41805.html Thanks a lot, I applied those 2 patches. Cheers, Samuel. -- Intel Open Source Technology Centre http://oss.intel.com/ -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/7] OMAP2+: mux: Enable wakeup for wakeup enable requested pads
On Wed, Mar 2, 2011 at 10:19 AM, Varadarajan, Charulatha ch...@ti.com wrote:
Govind,
Couple of minor comments.
On Mon, Feb 28, 2011 at 20:09, Govindraj.R govindraj.r...@ti.com wrote:
For device pads which have OMAP_DEVICE_PAD_WAKEUP set (which means they
are wakeup capable) enable the IO-daisy wakeup capability.
During re-muxing avoid direct write with val as this can disturb if any
mux done at bootloader level so read the pad then write back.
Also add a api to fetch the wake-up status bit is set for given omap-hwmod
%s/a api/an API/
device using available mux info which is added during omap_hwmod_mux_init.
Wakeup status bit is needed for uart_resume_idle call from sram_idle path
based on wake-up event has occurred for given uart we can enable clocks back.
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Govindraj.R govindraj.r...@ti.com
---
arch/arm/mach-omap2/mux.c | 23 +++
arch/arm/mach-omap2/mux.h | 13 +
arch/arm/mach-omap2/omap_hwmod.c | 13 +
arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 +
4 files changed, 50 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 98148b6..5338b93 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -317,6 +317,24 @@ err1:
return NULL;
}
+/* Gets the wakeup status of given pad from omap-hwmod */
+int omap_hwmod_mux_wakeup(struct omap_hwmod_mux_info *hmux)
+{
+ int i;
+ unsigned int val = -EINVAL;
+
+ for (i = 0; i hmux-nr_pads; i++) {
+ struct omap_device_pad *pad = hmux-pads[i];
+
+ val = omap_mux_read(pad-partition, pad-mux-reg_offset);
+ }
+
+ if (val 0 val OMAP_WAKEUP_EVENT)
+ return 1;
+ else
No need of else here.
Yes correct.
I am resending this patch with some more modifications
to fix one more issue in the above loop.
--
Thanks,
Govindraj.R
SNIP
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[PATCH 2/7] OMAP2+: mux: Enable wakeup for wakeup enable requested pads
For device pads which have OMAP_DEVICE_PAD_WAKEUP set (which means they
are wakeup capable) enable the IO-daisy wakeup capability.
During re-muxing avoid direct write with val as this can disturb if any
mux done at bootloader level so read the pad then write back.
Also add an API to fetch the wake-up status bit is set for given omap-hwmod
device using available mux info which is added during omap_hwmod_mux_init.
Wakeup status bit is needed for uart_resume_idle call from sram_idle path
based on wake-up event has occurred for given uart we can enable clocks back.
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Govindraj.R govindraj.r...@ti.com
---
arch/arm/mach-omap2/mux.c| 28 ++
arch/arm/mach-omap2/mux.h| 13
arch/arm/mach-omap2/omap_hwmod.c | 13
arch/arm/plat-omap/include/plat/omap_hwmod.h |1 +
4 files changed, 55 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 98148b6..50edcea 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -317,6 +317,29 @@ err1:
return NULL;
}
+/* Gets the wakeup status of given pad from omap-hwmod */
+int omap_hwmod_mux_wakeup(struct omap_hwmod_mux_info *hmux)
+{
+ int i;
+ unsigned int val;
+ u8 ret = 0;
+
+ for (i = 0; i hmux-nr_pads; i++) {
+ struct omap_device_pad *pad = hmux-pads[i];
+
+ if (pad-flags OMAP_DEVICE_PAD_WAKEUP) {
+ val = omap_mux_read(pad-partition,
+ pad-mux-reg_offset);
+ if (val OMAP_WAKEUP_EVENT) {
+ ret = 1;
+ break;
+ }
+ }
+ }
+
+ return ret;
+}
+
/* Assumes the calling function takes care of locking */
void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
{
@@ -342,6 +365,9 @@ void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8
state)
break;
flags = ~OMAP_DEVICE_PAD_ENABLED;
val = pad-idle;
+ if (flags OMAP_DEVICE_PAD_WAKEUP)
+ val |= OMAP_WAKEUP_EN;
+
pr_debug(%s: Idling %s %x\n, __func__,
pad-name, val);
break;
@@ -358,6 +384,8 @@ void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8
state)
};
if (val = 0) {
+ val |= omap_mux_read(pad-partition,
+ pad-mux-reg_offset);
omap_mux_write(pad-partition, val,
pad-mux-reg_offset);
pad-flags = flags;
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index a4ab17a..84a8fc2 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -220,8 +220,21 @@ omap_hwmod_mux_init(struct omap_device_pad *bpads, int
nr_pads);
*/
void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state);
+
+/**
+ * omap_hwmod_mux_wakeup - omap hwmod check given pad had wakeup event
+ * @hmux: Pads for a hwmod
+ *
+ * Called only from omap_hwmod.c, do not use.
+ */
+int omap_hwmod_mux_wakeup(struct omap_hwmod_mux_info *hmux);
#else
+static inline int omap_hwmod_mux_wakeup(struct omap_hwmod_mux_info *hmux)
+{
+ return 0;
+}
+
static inline int omap_mux_init_gpio(int gpio, int val)
{
return 0;
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 9e89a58..893dae1 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2239,3 +2239,16 @@ u32 omap_hwmod_get_context_loss_count(struct omap_hwmod
*oh)
return ret;
}
+
+/**
+ * omap_hwmod_pad_wakeup_status - get pad wakeup status if mux is available.
+ * @oh: struct omap_hwmod *
+ *
+ * Returns the wake_up status bit of available pad mux pin.
+ */
+int omap_hmwod_pad_wakeup_status(struct omap_hwmod *oh)
+{
+ if (oh-mux)
+ return omap_hwmod_mux_wakeup(oh-mux);
+ return -EINVAL;
+}
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h
b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index fedd829..4100be0 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -588,6 +588,7 @@ int omap_hwmod_for_each_by_class(const char *classname,
int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
+int omap_hmwod_pad_wakeup_status(struct omap_hwmod *oh);
/*
* Chip variant-specific hwmod init routines - XXX should be converted
* to use initcalls once the initial boot ordering is straightened out
--
1.7.1
--
To
[PATCH v2 00/18] OMAP3+: PM: introduce SR class 1.5
Hi, This series intends to introduce SmartReflex AVS Class 1.5 support which is now the recommended AVS class for usage in OMAP3630, OMAP4 and potentially in later generation of silicon as well. Smartreflex class 1.5 is a software controlled hardware calibration mechanism designed to improve dvfs latencies and system performance as well as helping bring in additional benefits to the system from h/w perspective. The corresponding patch has details on this class and the implementation as well. The series eventually results in OMAP343x based platforms using class3 and OMAP3630, OMAP4 platforms using class1.5 automatically without modifications or additions to board files. This series is Based on: a) k.org 2.6.38-rc7 (b2.6.38-rc7) b) The following branches Kevin Hilman's tree: (pm-base-v2) 'pm/for_2.6.38/pm-fixes', 'pm/for_2.6.39/pm-misc' and 'pm/pm-wip/cpufreq' http://git.kernel.org/?p=linux/kernel/git/khilman/linux-omap-pm.git;a=summary Rationale: there are some sr-cleanups done here which makes at least 1 patch create a minor conflict (kasprintf for sr name), but should reasonably apply to k.org as well, and since this series is targeted for 39-rc1, builds on previously accepted patches. Some good fixes needed are here (optional): c) sr-fixes: (sr-baseline-v2) http://marc.info/?l=linux-omapm=129783708019505w=2 http://marc.info/?l=linux-omapm=129679846322563w=2 Other interesting series: i) http://marc.info/?t=12982544513r=1w=2 cleanups of voltage.c - rebase should be minor effort ii) http://marc.info/?l=linux-omapm=129783700319445w=2 fixes for omap4 - might conflict on macro cleanup with (i) - should not conflict with the current series. This series is also available at: git://gitorious.org/linux-omap-nm-sr/linux-omap-sr.git Branch: sr-1.5-v2 Note: There is also a branch dvfs-test-v2 in my tree which contains the test version of code for OMAP3 based on Vishwa's DVFS series which is currently being revamped. if run on OMAP4, it just throws up a bit of warnings, but wont crash. The series contains a bunch of bugfixes and improvements needed to introduce Smartreflex class 1.5. Changes in v2 since v1: * I dropped patch 2/19 for 3630 ES revision, based on the discussion in: http://marc.info/?t=12981171033r=1w=2 NOTE: 3630 ES revision fixes need to be cleanly done at a later point, and there is not much use doing a temporary hackup job just for SR. Since it ain't broke atm for higher ES revs for SR, I will leave it alone. * Fixed the bug exposed by bootloaders which setup an OPP which is not enabled in kernel http://marc.info/?t=129811710500010r=1w=2 - parameter checks were necessary, impacted patches 5 and 17 * Documentation update following the explanation required for http://marc.info/?t=12981171037r=1w=2 for patch 5 - example provided in the discussion is useful for reviewer perspective in commit message Comments not incorporated from v1: * http://marc.info/?t=12981171057r=1w=2 - there is no reason to allow sr notifiers after class has been deinitialized, so not allowing it. * http://marc.info/?t=12981171034r=1w=2 - the omap2_init_voltage fix is not the intent of this series. infact handling of mpurate and omap2_init_voltage needs to be merged in at some future point of time. v1: http://marc.info/?l=linux-omapm=129811693118173w=2 Nishanth Menon (18): omap3: hwmod: add smartreflex irqs omap3+: voltage: remove initial voltage omap3+: voltage: remove spurious pr_notice for debugfs omap3+: voltage: use IS_ERR_OR_NULL omap3+: voltage: use volt_data pointer instead values omap3+: voltage: add transdone apis omap3+: sr: make notify independent of class omap3+: sr: introduce class init,deinit and priv data omap3+: sr: fix cosmetic indentation omap3+: sr: call handler with interrupt disabled omap3+: sr: disable interrupt by default omap3+: sr: enable/disable SR only on need omap3+: sr: introduce notifiers flags omap3+: sr: introduce notifier_control omap3+: sr: disable spamming interrupts omap3+: sr: make enable path use volt_data pointer omap3630+: sr: add support for class 1.5 omap3430: sr: class3: restrict cpu to run on arch/arm/mach-omap2/Makefile |1 + arch/arm/mach-omap2/omap_hwmod_3xxx_data.c| 17 + arch/arm/mach-omap2/pm.c |3 +- arch/arm/mach-omap2/smartreflex-class1p5.c| 582 + arch/arm/mach-omap2/smartreflex-class3.c | 21 +- arch/arm/mach-omap2/smartreflex.c | 249 +-- arch/arm/mach-omap2/voltage.c | 251 --- arch/arm/plat-omap/Kconfig| 17 + arch/arm/plat-omap/include/plat/smartreflex.h | 42 ++- arch/arm/plat-omap/include/plat/voltage.h | 36 ++- 10 files changed, 1097 insertions(+), 122 deletions(-) create mode 100644 arch/arm/mach-omap2/smartreflex-class1p5.c Testing performed:
[PATCH v2 02/18] omap3+: voltage: remove initial voltage
omap2_set_init_voltage should setup the curr_volt based on which OPP the system is functioning at. Blindly setting a 1.2v setting in the initial structure may not even match the default voltages stored in the voltage table which are supported for the domain. For example, OMAP3430 core domain does not use 1.2v and ends up generating a warning on the first transition. Signed-off-by: Nishanth Menon n...@ti.com --- arch/arm/mach-omap2/voltage.c |2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c index 12be525..280ee12 100644 --- a/arch/arm/mach-omap2/voltage.c +++ b/arch/arm/mach-omap2/voltage.c @@ -863,7 +863,6 @@ static int __init omap3_vdd_data_configure(struct omap_vdd_info *vdd) sys_clk_speed /= 1000; /* Generic voltage parameters */ - vdd-curr_volt = 120; vdd-ocp_mod = OCP_MOD; vdd-prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET; vdd-read_reg = omap3_voltage_read_reg; @@ -1054,7 +1053,6 @@ static int __init omap4_vdd_data_configure(struct omap_vdd_info *vdd) sys_clk_speed /= 1000; /* Generic voltage parameters */ - vdd-curr_volt = 120; vdd-ocp_mod = OMAP4430_PRM_OCP_SOCKET_INST; vdd-read_reg = omap4_voltage_read_reg; vdd-write_reg = omap4_voltage_write_reg; -- 1.7.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 03/18] omap3+: voltage: remove spurious pr_notice for debugfs
cat of debugfs entry for vp_volt provides voltage. The additional pr_notice
is just spam on console and provides no additional information.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/voltage.c |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 280ee12..992b383 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -347,7 +347,6 @@ static int vp_volt_debug_get(void *data, u64 *val)
}
vsel = vdd-read_reg(vdd-vp_reg.prm_mod, vdd-vp_offs.voltage);
- pr_notice(curr_vsel = %x\n, vsel);
if (!vdd-pmic_info-vsel_to_uv) {
pr_warning(PMIC function to convert vsel to voltage
--
1.7.1
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[PATCH v2 01/18] omap3: hwmod: add smartreflex irqs
OMAP3 smartreflex irqs in hwmod structures with the same naming as
present in OMAP4. Without these IRQs being registered, SmartReflex
driver will be unable to get the irq numbers to handle notifications
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 17 +
1 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 8d81813..ea1f49a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -265,6 +265,15 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+
+static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
+ {.name = sr1_irq, .irq = 18},
+};
+
+static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
+ {.name = sr2_irq, .irq = 19},
+};
+
/* L4 CORE - SR1 interface */
static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
{
@@ -1289,6 +1298,8 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
CHIP_IS_OMAP3430ES3_0 |
CHIP_IS_OMAP3430ES3_1),
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
+ .mpu_irqs = omap3_smartreflex_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3_smartreflex_mpu_irqs),
};
static struct omap_hwmod omap36xx_sr1_hwmod = {
@@ -1308,6 +1319,8 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
.slaves = omap3_sr1_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
+ .mpu_irqs = omap3_smartreflex_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3_smartreflex_mpu_irqs),
};
/* SR2 */
@@ -1335,6 +1348,8 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
CHIP_IS_OMAP3430ES3_0 |
CHIP_IS_OMAP3430ES3_1),
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
+ .mpu_irqs = omap3_smartreflex_core_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3_smartreflex_core_irqs),
};
static struct omap_hwmod omap36xx_sr2_hwmod = {
@@ -1354,6 +1369,8 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
.slaves = omap3_sr2_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
+ .mpu_irqs = omap3_smartreflex_core_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3_smartreflex_core_irqs),
};
static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
--
1.7.1
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[PATCH v2 04/18] omap3+: voltage: use IS_ERR_OR_NULL
Use IS_ERR_OR_NULL macro instead of just IS_ERR or !xyz || IS_ERR(xyz)
style usage.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/voltage.c | 28 ++--
1 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 992b383..3ee8a80 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -471,7 +471,7 @@ static void __init vdd_debugfs_init(struct omap_vdd_info
*vdd)
vdd-debug_dir = debugfs_create_dir(name, voltage_dir);
kfree(name);
- if (IS_ERR(vdd-debug_dir)) {
+ if (IS_ERR_OR_NULL(vdd-debug_dir)) {
pr_warning(%s: Unable to create debugfs directory for
vdd_%s\n, __func__, vdd-voltdm.name);
vdd-debug_dir = NULL;
@@ -851,7 +851,7 @@ static int __init omap3_vdd_data_configure(struct
omap_vdd_info *vdd)
* smpswaittimemin and smpswaittimemax.
*/
sys_ck = clk_get(NULL, sys_ck);
- if (IS_ERR(sys_ck)) {
+ if (IS_ERR_OR_NULL(sys_ck)) {
pr_warning(%s: Could not get the sys clk to calculate
various vdd_%s params\n, __func__, vdd-voltdm.name);
return -EINVAL;
@@ -1041,7 +1041,7 @@ static int __init omap4_vdd_data_configure(struct
omap_vdd_info *vdd)
* smpswaittimemin and smpswaittimemax.
*/
sys_ck = clk_get(NULL, sys_clkin_ck);
- if (IS_ERR(sys_ck)) {
+ if (IS_ERR_OR_NULL(sys_ck)) {
pr_warning(%s: Could not get the sys clk to calculate
various vdd_%s params\n, __func__, vdd-voltdm.name);
return -EINVAL;
@@ -1125,7 +1125,7 @@ unsigned long omap_voltage_get_nom_volt(struct
voltagedomain *voltdm)
{
struct omap_vdd_info *vdd;
- if (!voltdm || IS_ERR(voltdm)) {
+ if (IS_ERR_OR_NULL(voltdm)) {
pr_warning(%s: VDD specified does not exist!\n, __func__);
return 0;
}
@@ -1146,7 +1146,7 @@ unsigned long omap_vp_get_curr_volt(struct voltagedomain
*voltdm)
struct omap_vdd_info *vdd;
u8 curr_vsel;
- if (!voltdm || IS_ERR(voltdm)) {
+ if (IS_ERR_OR_NULL(voltdm)) {
pr_warning(%s: VDD specified does not exist!\n, __func__);
return 0;
}
@@ -1183,7 +1183,7 @@ void omap_vp_enable(struct voltagedomain *voltdm)
u32 vpconfig;
u16 mod;
- if (!voltdm || IS_ERR(voltdm)) {
+ if (IS_ERR_OR_NULL(voltdm)) {
pr_warning(%s: VDD specified does not exist!\n, __func__);
return;
}
@@ -1224,7 +1224,7 @@ void omap_vp_disable(struct voltagedomain *voltdm)
u16 mod;
int timeout;
- if (!voltdm || IS_ERR(voltdm)) {
+ if (IS_ERR_OR_NULL(voltdm)) {
pr_warning(%s: VDD specified does not exist!\n, __func__);
return;
}
@@ -1308,7 +1308,7 @@ void omap_voltage_reset(struct voltagedomain *voltdm)
{
unsigned long target_uvdc;
- if (!voltdm || IS_ERR(voltdm)) {
+ if (IS_ERR_OR_NULL(voltdm)) {
pr_warning(%s: VDD specified does not exist!\n, __func__);
return;
}
@@ -1340,7 +1340,7 @@ void omap_voltage_get_volttable(struct voltagedomain
*voltdm,
{
struct omap_vdd_info *vdd;
- if (!voltdm || IS_ERR(voltdm)) {
+ if (IS_ERR_OR_NULL(voltdm)) {
pr_warning(%s: VDD specified does not exist!\n, __func__);
return;
}
@@ -1371,7 +1371,7 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct
voltagedomain *voltdm,
struct omap_vdd_info *vdd;
int i;
- if (!voltdm || IS_ERR(voltdm)) {
+ if (IS_ERR_OR_NULL(voltdm)) {
pr_warning(%s: VDD specified does not exist!\n, __func__);
return ERR_PTR(-EINVAL);
}
@@ -1409,7 +1409,7 @@ int omap_voltage_register_pmic(struct voltagedomain
*voltdm,
{
struct omap_vdd_info *vdd;
- if (!voltdm || IS_ERR(voltdm)) {
+ if (IS_ERR_OR_NULL(voltdm)) {
pr_warning(%s: VDD specified does not exist!\n, __func__);
return -EINVAL;
}
@@ -1436,7 +1436,7 @@ struct dentry *omap_voltage_get_dbgdir(struct
voltagedomain *voltdm)
{
struct omap_vdd_info *vdd;
- if (!voltdm || IS_ERR(voltdm)) {
+ if (IS_ERR_OR_NULL(voltdm)) {
pr_warning(%s: VDD specified does not exist!\n, __func__);
return NULL;
}
@@ -1461,7 +1461,7 @@ void omap_change_voltscale_method(struct voltagedomain
*voltdm,
{
struct omap_vdd_info *vdd;
- if (!voltdm || IS_ERR(voltdm)) {
+ if (IS_ERR_OR_NULL(voltdm)) {
pr_warning(%s: VDD specified does not exist!\n, __func__);
return;
}
@@ -1531,7 +1531,7 @@ int __init omap_voltage_late_init(void)
[PATCH v2 05/18] omap3+: voltage: use volt_data pointer instead values
Voltage values can get confusing in meaning with various Smartreflex
classes being active. Depending on the class used, the actual voltage
selected might be a variant. For example:
with SmartReflex AVS class 3:
a) if we dont have SR enabled, we will go to volt_nominal
b) if have SR enabled, we go to volt_nominal, then enable SR and
expect it to adjust voltage. We dont really care about the
resultant voltage
Essentially, when we ask voltage layer to scale to voltage x for OPP
y, it always means x is the nominal voltage for OPP y.
Now, once we introduce SmartReflex AVS class 1.5:
a) If you are booting for the first time OR if you never enable SR
before, we always go to volt_nominal
b) If you enable SR and the OPP is calibrated, we will not enable SR
again when that OPP is accessed anymore, but when we set voltage for
an OPP, the voltage achieved will be volt_calibrated
c) If recalibration timeout triggers,or SR is disabled after a
calibration, the calibrated values are not valid anymore, at this point,
setting the voltage will mean volt_dynamic_nominal.
So, depending on which state the system is at, voltage for that OPP
we are setting has not 1 single value anymore, but 3 possible valid
values.
For upper layers(dvfs/cpufreq OMAP SoC layers) to use voltage values, it
will need to know which type of voltage AVS strategy is being used and
the corresponding system state from voltage layer perspective. This
would replicate the role of voltage layer, SmartReflex AVS in the upper
layers and make the corresponding implementations complex.
Since each voltage domain contains a set of volt_data structs representing
a voltage point that is supported for that domain, volt_data is a more
accurate representation of the voltage point we are interested in going to,
and the actual translation of this voltage point to the voltage value is
done inside the voltage layer. Doing this allows the users of the voltage
layer to be blissfully ignorant of any complexity of the underneath
layers and simplify the implementation of dependent layers.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/pm.c |3 +-
arch/arm/mach-omap2/smartreflex-class3.c |3 +-
arch/arm/mach-omap2/voltage.c | 77 -
arch/arm/plat-omap/include/plat/voltage.h | 13 -
4 files changed, 58 insertions(+), 38 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index d5a102c..669998b 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -209,7 +209,8 @@ static int __init omap2_set_init_voltage(char *vdd_name,
char *clk_name,
goto exit;
}
- omap_voltage_scale_vdd(voltdm, bootup_volt);
+ omap_voltage_scale_vdd(voltdm,
+ omap_voltage_get_voltdata(voltdm, bootup_volt));
return 0;
exit:
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c
b/arch/arm/mach-omap2/smartreflex-class3.c
index 60e7055..2195668 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -15,7 +15,8 @@
static int sr_class3_enable(struct voltagedomain *voltdm)
{
- unsigned long volt = omap_voltage_get_nom_volt(voltdm);
+ unsigned long volt = omap_get_operation_voltage(
+ omap_voltage_get_nom_volt(voltdm));
if (!volt) {
pr_warning(%s: Curr voltage unknown. Cannot enable sr_%s\n,
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 3ee8a80..50a6913 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -146,14 +146,14 @@ struct omap_vdd_info {
struct vc_reg_info vc_reg;
struct voltagedomain voltdm;
struct dentry *debug_dir;
- u32 curr_volt;
+ struct omap_volt_data *curr_volt;
u16 ocp_mod;
u8 prm_irqst_reg;
bool vp_enabled;
u32 (*read_reg) (u16 mod, u8 offset);
void (*write_reg) (u32 val, u16 mod, u8 offset);
int (*volt_scale) (struct omap_vdd_info *vdd,
- unsigned long target_volt);
+ struct omap_volt_data *target_volt);
};
static struct omap_vdd_info *vdd_info;
@@ -361,13 +361,20 @@ static int vp_volt_debug_get(void *data, u64 *val)
static int nom_volt_debug_get(void *data, u64 *val)
{
struct omap_vdd_info *vdd = (struct omap_vdd_info *) data;
+ struct omap_volt_data *volt_data;
if (!vdd) {
pr_warning(Wrong paramater passed\n);
return -EINVAL;
}
- *val = omap_voltage_get_nom_volt(vdd-voltdm);
+ volt_data = omap_voltage_get_nom_volt(vdd-voltdm);
+ if (IS_ERR_OR_NULL(volt_data)) {
+ pr_warning(%s: No voltage/domain?\n, __func__);
+ return -ENODEV;
+ }
+
+ *val = volt_data-volt_nominal;
return 0;
}
@@ -382,7 +389,8 @@ static void vp_latch_vsel(struct omap_vdd_info *vdd)
[PATCH v2 06/18] omap3+: voltage: add transdone apis
Transdone event in Voltage processor gives us fine grained status on
the current status of the voltage communication with the PMIC.
Unfortunately, irq generation by VP is based on the start of the
transmission to VC from VP, not at the end (or the completion of
the voltage setting). Hence any users of voltage layer who need
to know fine grained information such as confirmation if the voltage
is actually send to PMIC, needs to depend on this status.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/voltage.c | 64 ++---
arch/arm/plat-omap/include/plat/voltage.h |2 +
2 files changed, 51 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 50a6913..3cbe450 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -644,8 +644,8 @@ static int vp_forceupdate_scale_voltage(struct
omap_vdd_info *vdd,
struct omap_volt_data *target_volt)
{
u32 vpconfig;
- u16 mod, ocp_mod;
- u8 target_vsel, current_vsel, prm_irqst_reg;
+ u16 mod;
+ u8 target_vsel, current_vsel;
int ret, timeout = 0;
ret = _pre_volt_scale(vdd, target_volt, target_vsel, current_vsel);
@@ -653,18 +653,13 @@ static int vp_forceupdate_scale_voltage(struct
omap_vdd_info *vdd,
return ret;
mod = vdd-vp_reg.prm_mod;
- ocp_mod = vdd-ocp_mod;
- prm_irqst_reg = vdd-prm_irqst_reg;
-
/*
* Clear all pending TransactionDone interrupt/status. Typical latency
* is 3us
*/
while (timeout++ VP_TRANXDONE_TIMEOUT) {
- vdd-write_reg(vdd-vp_reg.tranxdone_status,
- ocp_mod, prm_irqst_reg);
- if (!(vdd-read_reg(ocp_mod, prm_irqst_reg)
- vdd-vp_reg.tranxdone_status))
+ omap_vp_clear_transdone(vdd-voltdm);
+ if (!omap_vp_is_transdone(vdd-voltdm))
break;
udelay(1);
}
@@ -696,7 +691,7 @@ static int vp_forceupdate_scale_voltage(struct
omap_vdd_info *vdd,
* Depends on SMPSWAITTIMEMIN/MAX and voltage change
*/
timeout = 0;
- omap_test_timeout((vdd-read_reg(ocp_mod, prm_irqst_reg)
+ omap_test_timeout((vdd-read_reg(vdd-ocp_mod, vdd-prm_irqst_reg)
vdd-vp_reg.tranxdone_status),
VP_TRANXDONE_TIMEOUT, timeout);
if (timeout = VP_TRANXDONE_TIMEOUT)
@@ -712,11 +707,9 @@ static int vp_forceupdate_scale_voltage(struct
omap_vdd_info *vdd,
*/
timeout = 0;
while (timeout++ VP_TRANXDONE_TIMEOUT) {
- vdd-write_reg(vdd-vp_reg.tranxdone_status,
- ocp_mod, prm_irqst_reg);
- if (!(vdd-read_reg(ocp_mod, prm_irqst_reg)
- vdd-vp_reg.tranxdone_status))
- break;
+ omap_vp_clear_transdone(vdd-voltdm);
+ if (!omap_vp_is_transdone(vdd-voltdm))
+ break;
udelay(1);
}
@@ -1274,6 +1267,47 @@ void omap_vp_disable(struct voltagedomain *voltdm)
}
/**
+ * omap_vp_is_transdone() - is voltage transfer done on vp?
+ * @voltdm:pointer to the VDD which is to be scaled.
+ *
+ * VP's transdone bit is the only way to ensure that the transfer
+ * of the voltage value has actually been send over to the PMIC
+ * This is hence useful for all users of voltage domain to precisely
+ * identify once the PMIC voltage has been set by the voltage processor
+ */
+bool omap_vp_is_transdone(struct voltagedomain *voltdm)
+{
+ struct omap_vdd_info *vdd;
+
+ if (IS_ERR_OR_NULL(voltdm)) {
+ pr_warning(%s: Bad Params vdm=%p\n, __func__, voltdm);
+ return false;
+ }
+
+ vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+ return (vdd-read_reg(vdd-ocp_mod, vdd-prm_irqst_reg)
+ vdd-vp_reg.tranxdone_status) ? true : false;
+}
+
+/**
+ * omap_vp_clear_transdone() - clear voltage transfer done status on vp
+ * @voltdm:pointer to the VDD which is to be scaled.
+ */
+bool omap_vp_clear_transdone(struct voltagedomain *voltdm)
+{
+ struct omap_vdd_info *vdd;
+
+ if (IS_ERR_OR_NULL(voltdm)) {
+ pr_warning(%s: Bad Params vdm=%p\n, __func__, voltdm);
+ return false;
+ }
+
+ vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+ vdd-write_reg(vdd-vp_reg.tranxdone_status,
+ vdd-ocp_mod, vdd-prm_irqst_reg);
+ return true;
+}
+/**
* omap_voltage_scale_vdd() - API to scale voltage of a particular
* voltage domain.
* @voltdm:pointer to the VDD which is to be scaled.
diff --git a/arch/arm/plat-omap/include/plat/voltage.h
b/arch/arm/plat-omap/include/plat/voltage.h
[PATCH v2 07/18] omap3+: sr: make notify independent of class
Interrupt notification mechanism of SmartReflex can be used by the
choice of implementation of the class driver. For example, Class 2 and
Class 1.5 of SmartReflex can both use the interrupt notification to
identify the transition of voltage or other events.
Hence, the actual class does not matter for notifier. Let the class
driver's handling decide how it should be used. smartreflex driver
should provide just the primitives.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/smartreflex.c |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
index a1f532e..08e1ee4 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -142,7 +142,7 @@ static irqreturn_t sr_interrupt(int irq, void *data)
sr_write_reg(sr_info, IRQSTATUS, status);
}
- if (sr_class-class_type == SR_CLASS2 sr_class-notify)
+ if (sr_class-notify)
sr_class-notify(sr_info-voltdm, status);
return IRQ_HANDLED;
@@ -257,9 +257,7 @@ static int sr_late_init(struct omap_sr *sr_info)
struct resource *mem;
int ret = 0;
- if (sr_class-class_type == SR_CLASS2
- sr_class-notify_flags sr_info-irq) {
-
+ if (sr_class-notify sr_class-notify_flags sr_info-irq) {
name = kasprintf(GFP_KERNEL, sr_%s, sr_info-voltdm-name);
if (name == NULL) {
ret = -ENOMEM;
--
1.7.1
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[PATCH v2 08/18] omap3+: sr: introduce class init,deinit and priv data
Certain class drivers such as class 1.5 drivers, will need specific
notification that they have to be started up or stopped independent
of smart reflex operation. They also may need private data to be
used for operations of their own, provide the same.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/smartreflex.c | 14 ++
arch/arm/plat-omap/include/plat/smartreflex.h |7 +++
2 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
index 08e1ee4..35658a2 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -220,6 +220,13 @@ static void sr_start_vddautocomp(struct omap_sr *sr)
return;
}
+ if (sr_class-class_init
+ sr_class-class_init(sr-voltdm, sr_class-class_priv_data)) {
+ dev_err(sr-pdev-dev,
+ %s: SRClass initialization failed\n, __func__);
+ return;
+ }
+
if (!sr_class-enable(sr-voltdm))
sr-autocomp_active = true;
}
@@ -235,6 +242,13 @@ static void sr_stop_vddautocomp(struct omap_sr *sr)
if (sr-autocomp_active) {
sr_class-disable(sr-voltdm, 1);
+ if (sr_class-class_deinit
+ sr_class-class_deinit(sr-voltdm,
+ sr_class-class_priv_data)) {
+ dev_err(sr-pdev-dev,
+ %s: SR[%d]Class deinitialization failed\n,
+ __func__, sr-srid);
+ }
sr-autocomp_active = false;
}
}
diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h
b/arch/arm/plat-omap/include/plat/smartreflex.h
index 6568c88..8b6ecd9 100644
--- a/arch/arm/plat-omap/include/plat/smartreflex.h
+++ b/arch/arm/plat-omap/include/plat/smartreflex.h
@@ -167,6 +167,8 @@ struct omap_sr_pmic_data {
*
* @enable:API to enable a particular class smaartreflex.
* @disable: API to disable a particular class smartreflex.
+ * @class_init:API to do class specific initialization
(optional)
+ * @class_deinit: API to do class specific initialization (optional)
* @configure: API to configure a particular class smartreflex.
* @notify:API to notify the class driver about an event in SR.
* Not needed for class3.
@@ -174,14 +176,19 @@ struct omap_sr_pmic_data {
* @class_type:specify which smartreflex class.
* Can be used by the SR driver to take any class
* based decisions.
+ * @class_priv_data: Class specific private data (optional)
*/
struct omap_sr_class_data {
int (*enable)(struct voltagedomain *voltdm);
int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
+ int (*class_init)(struct voltagedomain *voltdm, void *class_priv_data);
+ int (*class_deinit)(struct voltagedomain *voltdm,
+ void *class_priv_data);
int (*configure)(struct voltagedomain *voltdm);
int (*notify)(struct voltagedomain *voltdm, u32 status);
u8 notify_flags;
u8 class_type;
+ void *class_priv_data;
};
/**
--
1.7.1
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[PATCH v2 09/18] omap3+: sr: fix cosmetic indentation
Error label case seems to have a 2 tab indentation when just 1 is necessary. Signed-off-by: Nishanth Menon n...@ti.com --- arch/arm/mach-omap2/smartreflex.c | 18 +- 1 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index 35658a2..99e4c4f 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -289,15 +289,15 @@ static int sr_late_init(struct omap_sr *sr_info) return ret; error: - iounmap(sr_info-base); - mem = platform_get_resource(sr_info-pdev, IORESOURCE_MEM, 0); - release_mem_region(mem-start, resource_size(mem)); - list_del(sr_info-node); - dev_err(sr_info-pdev-dev, %s: ERROR in registering - interrupt handler. Smartreflex will - not function as desired\n, __func__); - kfree(sr_info); - return ret; + iounmap(sr_info-base); + mem = platform_get_resource(sr_info-pdev, IORESOURCE_MEM, 0); + release_mem_region(mem-start, resource_size(mem)); + list_del(sr_info-node); + dev_err(sr_info-pdev-dev, %s: ERROR in registering + interrupt handler. Smartreflex will + not function as desired\n, __func__); + kfree(sr_info); + return ret; } static void sr_v1_disable(struct omap_sr *sr) -- 1.7.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 10/18] omap3+: sr: call handler with interrupt disabled
Request the handler irq such that there is no nesting for calls. the notifiers are not expected to be nested, further the interrupt events for status change should be handled prior to the next event else there is a risk of loosing events. Signed-off-by: Nishanth Menon n...@ti.com --- arch/arm/mach-omap2/smartreflex.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index 99e4c4f..a4e9f2d 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -278,7 +278,7 @@ static int sr_late_init(struct omap_sr *sr_info) goto error; } ret = request_irq(sr_info-irq, sr_interrupt, - 0, name, (void *)sr_info); + IRQF_DISABLED, name, (void *)sr_info); if (ret) goto error; } -- 1.7.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 11/18] omap3+: sr: disable interrupt by default
We will enable and disable interrupt on a need basis in the class driver. we need to keep the irq disabled by default else the forceupdate or vcbypass events could trigger events that we dont need/expect to handle. Signed-off-by: Nishanth Menon n...@ti.com --- arch/arm/mach-omap2/smartreflex.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index a4e9f2d..8cad92d 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -281,6 +281,7 @@ static int sr_late_init(struct omap_sr *sr_info) IRQF_DISABLED, name, (void *)sr_info); if (ret) goto error; + disable_irq(sr_info-irq); } if (pdata pdata-enable_on_init) -- 1.7.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 12/18] omap3+: sr: enable/disable SR only on need
Since we already know the state of the autocomp enablement, we can
see if the requested state is different from the current state and
enable/disable SR only on the need basis.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/smartreflex.c | 11 +++
1 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
index 8cad92d..4fc679e 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -819,10 +819,13 @@ static int omap_sr_autocomp_store(void *data, u64 val)
return -EINVAL;
}
- if (!val)
- sr_stop_vddautocomp(sr_info);
- else
- sr_start_vddautocomp(sr_info);
+ /* control enable/disable only if there is a delta in value */
+ if (sr_info-autocomp_active ^ val) {
+ if (!val)
+ sr_stop_vddautocomp(sr_info);
+ else
+ sr_start_vddautocomp(sr_info);
+ }
return 0;
}
--
1.7.1
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[PATCH v2 13/18] omap3+: sr: introduce notifiers flags
SmartReflex IP v1 and v2 have different registers and offsets.
Currently, we pass the status as is to the class driver. However,
since we dont pass the version of the underlying SR hardware
to the Class driver, it will not be unable to make consistent
sense of the status bits coming over to it.
A class driver should be able to function without dependency
on the exact IP version it is actually running on. We hence
introduce our own translation in s/w level for a generic
notification flag.
As part of this change, we will now call the notifier iff we get
a match with the notifier flags that the class driver requested.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/smartreflex.c | 73 -
arch/arm/plat-omap/include/plat/smartreflex.h |6 ++
2 files changed, 76 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
index 4fc679e..2657ba1 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -123,27 +123,94 @@ static struct omap_sr *_sr_lookup(struct voltagedomain
*voltdm)
return ERR_PTR(-ENODATA);
}
+static inline u32 notifier_to_irqen_v1(u8 notify_flags)
+{
+ u32 val;
+ val = (notify_flags SR_NOTIFY_MCUACCUM) ?
+ ERRCONFIG_MCUACCUMINTEN : 0;
+ val |= (notify_flags SR_NOTIFY_MCUVALID) ?
+ ERRCONFIG_MCUVALIDINTEN : 0;
+ val |= (notify_flags SR_NOTIFY_MCUBOUND) ?
+ ERRCONFIG_MCUBOUNDINTEN : 0;
+ val |= (notify_flags SR_NOTIFY_MCUDISACK) ?
+ ERRCONFIG_MCUDISACKINTEN : 0;
+ return val;
+}
+
+static inline u32 notifier_to_irqen_v2(u8 notify_flags)
+{
+ u32 val;
+ val = (notify_flags SR_NOTIFY_MCUACCUM) ?
+ IRQENABLE_MCUACCUMINT : 0;
+ val |= (notify_flags SR_NOTIFY_MCUVALID) ?
+ IRQENABLE_MCUVALIDINT : 0;
+ val |= (notify_flags SR_NOTIFY_MCUBOUND) ?
+ IRQENABLE_MCUBOUNDSINT : 0;
+ val |= (notify_flags SR_NOTIFY_MCUDISACK) ?
+ IRQENABLE_MCUDISABLEACKINT : 0;
+ return val;
+}
+
+static inline u8 irqstat_to_notifier_v1(u32 status)
+{
+ u8 val;
+ val = (status ERRCONFIG_MCUACCUMINTST) ?
+ SR_NOTIFY_MCUACCUM : 0;
+ val |= (status ERRCONFIG_MCUVALIDINTEN) ?
+ SR_NOTIFY_MCUVALID : 0;
+ val |= (status ERRCONFIG_MCUBOUNDINTEN) ?
+ SR_NOTIFY_MCUBOUND : 0;
+ val |= (status ERRCONFIG_MCUDISACKINTEN) ?
+ SR_NOTIFY_MCUDISACK : 0;
+ return val;
+}
+
+static inline u8 irqstat_to_notifier_v2(u32 status)
+{
+ u8 val;
+ val = (status IRQENABLE_MCUACCUMINT) ?
+ SR_NOTIFY_MCUACCUM : 0;
+ val |= (status IRQENABLE_MCUVALIDINT) ?
+ SR_NOTIFY_MCUVALID : 0;
+ val |= (status IRQENABLE_MCUBOUNDSINT) ?
+ SR_NOTIFY_MCUBOUND : 0;
+ val |= (status IRQENABLE_MCUDISABLEACKINT) ?
+ SR_NOTIFY_MCUDISACK : 0;
+ return val;
+}
+
+
static irqreturn_t sr_interrupt(int irq, void *data)
{
struct omap_sr *sr_info = (struct omap_sr *)data;
u32 status = 0;
+ u32 value = 0;
if (sr_info-ip_type == SR_TYPE_V1) {
+ /* Status bits are one bit before enable bits in v1 */
+ value = notifier_to_irqen_v1(sr_class-notify_flags) 1;
+
/* Read the status bits */
status = sr_read_reg(sr_info, ERRCONFIG_V1);
+ status = value;
/* Clear them by writing back */
- sr_write_reg(sr_info, ERRCONFIG_V1, status);
+ sr_modify_reg(sr_info, ERRCONFIG_V1, value, status);
+
+ value = irqstat_to_notifier_v1(status);
} else if (sr_info-ip_type == SR_TYPE_V2) {
+ value = notifier_to_irqen_v2(sr_class-notify_flags);
/* Read the status bits */
- sr_read_reg(sr_info, IRQSTATUS);
+ status = sr_read_reg(sr_info, IRQSTATUS);
+ status = value;
/* Clear them by writing back */
sr_write_reg(sr_info, IRQSTATUS, status);
+ value = irqstat_to_notifier_v2(status);
}
if (sr_class-notify)
- sr_class-notify(sr_info-voltdm, status);
+ sr_class-notify(sr_info-voltdm, value);
return IRQ_HANDLED;
}
diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h
b/arch/arm/plat-omap/include/plat/smartreflex.h
index 8b6ecd9..ff07d1e 100644
--- a/arch/arm/plat-omap/include/plat/smartreflex.h
+++ b/arch/arm/plat-omap/include/plat/smartreflex.h
@@ -141,6 +141,12 @@
#define OMAP3430_SR_ERRWEIGHT 0x04
#define OMAP3430_SR_ERRMAXLIMIT0x02
+/* Smart reflex notifiers for class drivers to use */
+#define SR_NOTIFY_MCUACCUM (0x1 0)
+#define SR_NOTIFY_MCUVALID (0x1 1)
+#define SR_NOTIFY_MCUBOUND
[PATCH v2 14/18] omap3+: sr: introduce notifier_control
We need some mechanism from class drivers to control when notifiers
should be triggered and when not, currently we have none, which makes
Class driver usage of the interrupt events almost impossible.
Introduce an smartreflex driver api for doing the same.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/smartreflex.c | 57 +
arch/arm/plat-omap/include/plat/smartreflex.h |8
2 files changed, 65 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
index 2657ba1..49a04ea 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -704,6 +704,63 @@ void sr_disable(struct voltagedomain *voltdm)
}
/**
+ * sr_notifier_control() - control the notifier mechanism
+ * @voltdm:VDD pointer to which the SR module to be configured belongs to.
+ * @enable:true to enable notifiers and false to disable the same
+ *
+ * SR modules allow an MCU interrupt mechanism that vary based on the IP
+ * revision, we allow the system to generate interrupt if the class driver
+ * has capability to handle the same. it is upto the class driver to ensure
+ * the proper sequencing and handling for a clean implementation. returns
+ * 0 if all goes fine, else returns failure results
+ */
+int sr_notifier_control(struct voltagedomain *voltdm, bool enable)
+{
+ struct omap_sr *sr = _sr_lookup(voltdm);
+ u32 value = 0;
+ if (IS_ERR_OR_NULL(sr)) {
+ pr_warning(%s: sr corresponding to domain not found\n,
+ __func__);
+ return -EINVAL;
+ }
+ if (!sr-autocomp_active)
+ return -EINVAL;
+
+ /* if I could never register an isr, why bother?? */
+ if (!(sr_class sr_class-notify sr_class-notify_flags
+ sr-irq)) {
+ dev_warn(sr-pdev-dev,
+ %s: unable to setup irq without handling mechanism\n,
+ __func__);
+ return -EINVAL;
+ }
+
+ switch (sr-ip_type) {
+ case SR_TYPE_V1:
+ value = notifier_to_irqen_v1(sr_class-notify_flags);
+ sr_modify_reg(sr, ERRCONFIG_V1, value,
+ (enable) ? value : 0);
+ break;
+ case SR_TYPE_V2:
+ value = notifier_to_irqen_v2(sr_class-notify_flags);
+ sr_write_reg(sr, (enable) ? IRQENABLE_SET : IRQENABLE_CLR,
+ value);
+ break;
+ default:
+dev_warn(sr-pdev-dev, %s: unknown type of sr??\n,
+__func__);
+ return -EINVAL;
+ }
+
+ if (enable)
+ enable_irq(sr-irq);
+ else
+ disable_irq_nosync(sr-irq);
+
+ return 0;
+}
+
+/**
* sr_register_class() - API to register a smartreflex class parameters.
* @class_data:The structure containing various sr class specific data.
*
diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h
b/arch/arm/plat-omap/include/plat/smartreflex.h
index ff07d1e..d420f44 100644
--- a/arch/arm/plat-omap/include/plat/smartreflex.h
+++ b/arch/arm/plat-omap/include/plat/smartreflex.h
@@ -242,6 +242,7 @@ void omap_sr_register_pmic(struct omap_sr_pmic_data
*pmic_data);
/* Smartreflex driver hooks to be called from Smartreflex class driver */
int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
void sr_disable(struct voltagedomain *voltdm);
+int sr_notifier_control(struct voltagedomain *voltdm, bool enable);
int sr_configure_errgen(struct voltagedomain *voltdm);
int sr_configure_minmax(struct voltagedomain *voltdm);
@@ -250,6 +251,13 @@ int sr_register_class(struct omap_sr_class_data
*class_data);
#else
static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
+
+static inline int sr_notifier_control(struct voltagedomain *voltdm,
+ bool enable)
+{
+ return -EINVAL;
+}
+
static inline void omap_sr_disable_reset_volt(
struct voltagedomain *voltdm) {}
static inline void omap_sr_register_pmic(
--
1.7.1
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[PATCH v2 15/18] omap3+: sr: disable spamming interrupts
At times with bad SR configurations especially during silicon bringups,
we could get continuous spurious interrupts which end up hanging the
platform in the form of an ISR call for status bits that are
automatically enabled by the h/w without any s/w clearing option.
If we detect scenarios where isr was called without the corresponding
notification bit being set, instead of hanging up the system,
we will disable interrupt after noting the event in the system log
to try and keep system sanity and allow developer to debug and fix
the condition.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/smartreflex.c | 12 ++--
1 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
index 49a04ea..d62da3d 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -209,8 +209,16 @@ static irqreturn_t sr_interrupt(int irq, void *data)
value = irqstat_to_notifier_v2(status);
}
- if (sr_class-notify)
- sr_class-notify(sr_info-voltdm, value);
+ /* Attempt some resemblence of recovery! */
+ if (!value) {
+ dev_err(sr_info-pdev-dev, %s: Spurious interrupt!
+ status = 0x%08x. Disabling to prevent spamming!!\n,
+ __func__, status);
+ disable_irq_nosync(sr_info-irq);
+ } else {
+ if (sr_class-notify)
+ sr_class-notify(sr_info-voltdm, value);
+ }
return IRQ_HANDLED;
}
--
1.7.1
--
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[PATCH v2 16/18] omap3+: sr: make enable path use volt_data pointer
Passing the volt_data pointers accross allows us to save us the effort
of looking up the voltage data pointer from the voltage value at
multiple layers, we need to look at the voltage data in dvfs layer
for further processing, so modify the APIs to pass the voltage data
pointer all the way through to lower layers to the smartreflex class
drivers.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/smartreflex-class3.c | 13 +++--
arch/arm/mach-omap2/smartreflex.c | 25 -
arch/arm/plat-omap/include/plat/smartreflex.h |8 +---
3 files changed, 20 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c
b/arch/arm/mach-omap2/smartreflex-class3.c
index 2195668..7ac88da 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -13,19 +13,12 @@
#include plat/smartreflex.h
-static int sr_class3_enable(struct voltagedomain *voltdm)
+static int sr_class3_enable(struct voltagedomain *voltdm,
+ struct omap_volt_data *volt_data)
{
- unsigned long volt = omap_get_operation_voltage(
- omap_voltage_get_nom_volt(voltdm));
-
- if (!volt) {
- pr_warning(%s: Curr voltage unknown. Cannot enable sr_%s\n,
- __func__, voltdm-name);
- return -ENODATA;
- }
omap_vp_enable(voltdm);
- return sr_enable(voltdm, volt);
+ return sr_enable(voltdm, volt_data);
}
static int sr_class3_disable(struct voltagedomain *voltdm, int is_volt_reset)
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
index d62da3d..9b9d380 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -302,7 +302,8 @@ static void sr_start_vddautocomp(struct omap_sr *sr)
return;
}
- if (!sr_class-enable(sr-voltdm))
+ if (!sr_class-enable(sr-voltdm,
+ omap_voltage_get_nom_volt(sr-voltdm)))
sr-autocomp_active = true;
}
@@ -618,7 +619,7 @@ int sr_configure_minmax(struct voltagedomain *voltdm)
/**
* sr_enable() - Enables the smartreflex module.
* @voltdm:VDD pointer to which the SR module to be configured belongs to.
- * @volt: The voltage at which the Voltage domain associated with
+ * @volt_data: The voltage at which the Voltage domain associated with
* the smartreflex module is operating at.
* This is required only to program the correct Ntarget value.
*
@@ -626,10 +627,9 @@ int sr_configure_minmax(struct voltagedomain *voltdm)
* enable a smartreflex module. Returns 0 on success. Returns error
* value if the voltage passed is wrong or if ntarget value is wrong.
*/
-int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
+int sr_enable(struct voltagedomain *voltdm, struct omap_volt_data *volt_data)
{
u32 nvalue_reciprocal;
- struct omap_volt_data *volt_data;
struct omap_sr *sr = _sr_lookup(voltdm);
int ret;
@@ -639,19 +639,16 @@ int sr_enable(struct voltagedomain *voltdm, unsigned long
volt)
return -EINVAL;
}
- volt_data = omap_voltage_get_voltdata(sr-voltdm, volt);
-
- if (IS_ERR(volt_data)) {
- dev_warn(sr-pdev-dev, %s: Unable to get voltage table
- for nominal voltage %ld\n, __func__, volt);
- return -ENODATA;
+ if (IS_ERR_OR_NULL(volt_data)) {
+ dev_warn(sr-pdev-dev, %s: bad voltage data\n, __func__);
+ return -EINVAL;
}
nvalue_reciprocal = sr_retrieve_nvalue(sr, volt_data-sr_efuse_offs);
if (!nvalue_reciprocal) {
dev_warn(sr-pdev-dev, %s: NVALUE = 0 at voltage %ld\n,
- __func__, volt);
+ __func__, omap_get_operation_voltage(volt_data));
return -ENODATA;
}
@@ -808,13 +805,15 @@ int sr_register_class(struct omap_sr_class_data
*class_data)
* omap_sr_enable() - API to enable SR clocks and to call into the
* registered smartreflex class enable API.
* @voltdm:VDD pointer to which the SR module to be configured belongs to.
+ * @volt_data: Voltage data to go to
*
* This API is to be called from the kernel in order to enable
* a particular smartreflex module. This API will do the initial
* configurations to turn on the smartreflex module and in turn call
* into the registered smartreflex class enable API.
*/
-void omap_sr_enable(struct voltagedomain *voltdm)
+void omap_sr_enable(struct voltagedomain *voltdm,
+ struct omap_volt_data *volt_data)
{
struct omap_sr *sr = _sr_lookup(voltdm);
@@ -833,7 +832,7 @@ void omap_sr_enable(struct voltagedomain *voltdm)
return;
}
- sr_class-enable(voltdm);
+ sr_class-enable(voltdm,
[patch v2 3/3] arm: omap4: support pmu
From: Ming Lei tom.leim...@gmail.com
This patch supports pmu irq routed from CTI, so
make pmu/perf working on OMAP4.
The idea is from Woodruff Richard in the disscussion
about Oprofile on Pandaboard / Omap4 on pandabo...@googlegroups.com.
Cc: Woodruff Richard r-woodru...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: linux-omap@vger.kernel.org
Signed-off-by: Ming Lei tom.leim...@gmail.com
---
arch/arm/mach-omap2/dbg44xx.h | 18 +
arch/arm/mach-omap2/devices.c | 83 +++-
2 files changed, 98 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/mach-omap2/dbg44xx.h
diff --git a/arch/arm/mach-omap2/dbg44xx.h b/arch/arm/mach-omap2/dbg44xx.h
new file mode 100644
index 000..e447ad5
--- /dev/null
+++ b/arch/arm/mach-omap2/dbg44xx.h
@@ -0,0 +1,18 @@
+/*
+ * OMAP44xx on-chip debug support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX This file needs to be updated to align on one of OMAP4, OMAP44XX,
+ * or OMAP4430.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_DBG44XX_H
+#define __ARCH_ARM_MACH_OMAP2_DBG44XX_H
+
+#define OMAP44XX_CTI0_BASE 0x54148000
+#define OMAP44XX_CTI1_BASE 0x54149000
+
+#endif
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index d216976..bae02d5 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -22,6 +22,7 @@
#include asm/mach-types.h
#include asm/mach/map.h
#include asm/pmu.h
+#include asm/cti.h
#include plat/tc.h
#include plat/board.h
@@ -35,6 +36,7 @@
#include mux.h
#include control.h
+#include dbg44xx.h
#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
@@ -322,20 +324,95 @@ static struct resource omap3_pmu_resource = {
.flags = IORESOURCE_IRQ,
};
+static struct resource omap4_pmu_resource[] = {
+ {
+ .start = OMAP44XX_IRQ_CTI0,
+ .end= OMAP44XX_IRQ_CTI0,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = OMAP44XX_IRQ_CTI1,
+ .end= OMAP44XX_IRQ_CTI1,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
static struct platform_device omap_pmu_device = {
.name = arm-pmu,
.id = ARM_PMU_DEVICE_CPU,
.num_resources = 1,
};
+static struct arm_pmu_platdata omap4_pmu_data;
+static struct cti omap4_cti[2];
+
+static void omap4_enable_cti(int irq)
+{
+ if (irq == OMAP44XX_IRQ_CTI0)
+ cti_enable(omap4_cti[0]);
+ else if (irq == OMAP44XX_IRQ_CTI1)
+ cti_enable(omap4_cti[1]);
+}
+
+static void omap4_disable_cti(int irq)
+{
+ if (irq == OMAP44XX_IRQ_CTI0)
+ cti_disable(omap4_cti[0]);
+ else if (irq == OMAP44XX_IRQ_CTI1)
+ cti_disable(omap4_cti[1]);
+}
+
+static irqreturn_t omap4_pmu_handler(int irq, void *dev, irq_handler_t handler)
+{
+ if (irq == OMAP44XX_IRQ_CTI0)
+ cti_irq_ack(omap4_cti[0]);
+ else if (irq == OMAP44XX_IRQ_CTI1)
+ cti_irq_ack(omap4_cti[1]);
+
+ return handler(irq, dev);
+}
+
+static void omap4_configure_pmu_irq(void)
+{
+ void *base0;
+ void *base1;
+
+ base0 = ioremap(OMAP44XX_CTI0_BASE, 4096);
+ base1 = ioremap(OMAP44XX_CTI1_BASE, 4096);
+ if (!base0 !base1) {
+ pr_err(ioremap for omap4 CTI failed\n);
+ return;
+ }
+
+ /*configure CTI0 for pmu irq routing*/
+ cti_init(omap4_cti[0], base0, OMAP44XX_IRQ_CTI0, 6);
+ cti_unlock(omap4_cti[0]);
+ cti_map_trigger(omap4_cti[0], 1, 6, 2);
+
+ /*configure CTI1 for pmu irq routing*/
+ cti_init(omap4_cti[1], base1, OMAP44XX_IRQ_CTI1, 6);
+ cti_unlock(omap4_cti[1]);
+ cti_map_trigger(omap4_cti[1], 1, 6, 2);
+
+ omap4_pmu_data.handle_irq = omap4_pmu_handler;
+ omap4_pmu_data.enable_irq = omap4_enable_cti;
+ omap4_pmu_data.disable_irq = omap4_disable_cti;
+}
+
static void omap_init_pmu(void)
{
- if (cpu_is_omap24xx())
+ if (cpu_is_omap24xx()) {
omap_pmu_device.resource = omap2_pmu_resource;
- else if (cpu_is_omap34xx())
+ } else if (cpu_is_omap34xx()) {
omap_pmu_device.resource = omap3_pmu_resource;
- else
+ } else if (cpu_is_omap44xx()) {
+ omap_pmu_device.resource = omap4_pmu_resource;
+ omap_pmu_device.num_resources = 2;
+ omap_pmu_device.dev.platform_data = omap4_pmu_data;
+ omap4_configure_pmu_irq();
+ } else {
return;
+ }
platform_device_register(omap_pmu_device);
}
--
1.7.3
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[PATCH v2 17/18] omap3630+: sr: add support for class 1.5
Traditional SmartReflex AVS(Automatic Voltage Scaling) classes are: * Class 0 - Product test calibration Silicon is calibration at production floor and fused with voltages for each OPP * Class 1 - Boot time calibration Silicon is calibrated once at boot time and voltages are stored for the lifetime of operation. * Class 2 - continuous s/w calibration SR module notifies s/w for any change in the system which is desired and the s/w makes runtime decisions in terms of setting the voltage, this mechanism could be used in the system which does not have PMIC capable of SR without using the voltage controller and voltage processor blocks. * Class 3 - continuous h/w calibration SR module is switch on after reaching a voltage level and SR continuously monitors the system and makes runtime adjustments without s/w involvement. OMAP3430 has used SmartReflex AVS and with a a PMIC which understands the SR protocol, Class 3 has been used. With OMAP3630 onwards, a new SmartReflex AVS class of operation Class 1.5 was introduced. * Class 1.5 - periodic s/w calibration This uses the h/w calibration loop and at the end of calibration stores the voltages to be used run time, periodic recalibration is performed as well. The operational mode is describes as the following: * SmartReflex AVS h/w calibration loop is essential to identify the optimal voltage for a given OPP. * Once this optimal voltage is detected, SmartReflex AVS loop is disabled in class 1.5 mode of operation. * Until there is a need for a recalibration, any further transition to an OPP voltage which is calibrated can use the calibrated voltage and does not require enabling the SR AVS h/w loop. * On a periodic basis (recommendation being once approximately every 24 hours), software is expected to perform a recalibration to find a new optimal voltage which is compensated for device aging. - For performing this recalibration, the start voltage does not need to be the nominal voltage anymore. instead, the system can start with a voltage which is 50mV higher than the previously calibrated voltage to identify the new optimal voltage as the aging factor within a period of 1 day is not going to be anywhere close to 50mV. - This new starting point for recalibration is called a dynamic nominal voltage for that voltage point. In short, with the introduction of SmartReflex class 1.5, there are three new voltages possible in a system's dvfs transition: * Nominal Voltage - The maximum voltage needed for a worst possible device in the worst possible conditions. This is the voltage we choose as the starting point for the h/w loop to optimize for the first time calibration on system bootup. * Dynamic Nominal Voltage - Worst case voltage for a specific device in considering the system aging on the worst process device. * Calibrated Voltage - Best voltage for the current device at a given point of time. In terms of the implementation, doing calibration involves waiting for the smartreflex h/w loop to settle down, and doing this as part of the dvfs flow itself is to increase the latency of dvfs transition when there is a need to calibrate that opp. instead, the calibration is performed out of path using a workqueue statemachine. The workqueue waits for the system stabilization, then enables VP interrupts to monitor for system instability interms of voltage oscillations that are reported back to the system as interrupts, in case of prolonged system oscillations, nominal voltage is chosen as a safe voltage and this event is logged in the system log for developer debug and fixing. For the recalibration, a common workqueue for all domains is started at the start of the class initialization and it resets the calibrated voltages on a periodic basis. For distros that may choose not to do the recommended periodic recalibration, instead choose to perform boot time calibration, kconfig configuration option is provided to do so. TODO: a) Cpuidle and suspend paths are not integrated with SmartReflex driver at this point. b) Since the SR registers are accessed and controlled in parallel to DVFS some sort of mechanism is necessary to be introduced along with OMAP dvfs layer to ensure mutual exclusivity c) Additional debug interfaces for vmin analysis for platform characterization and addition of system margin needs to be introduced from smartreflex perspective. This implementation also includes the following contributors: Tony Lindgren for suggestion on using interrupt based mechanism instead of polling to detect voltage oscillations. Peter 'p2' De Schrijver for debating alternatives on recalibration mechanisms Paul Walmsey, Eduardo Valentin, Ambresh K, Igor Dmitriev and quiet a few others for patient review,
[PATCH v2 18/18] omap3430: sr: class3: restrict cpu to run on
Use SmartReflex AVS Class3 initialization only for OMAP343x family of
processors.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/smartreflex-class3.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c
b/arch/arm/mach-omap2/smartreflex-class3.c
index 5f7a33e..f99e517 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -11,6 +11,7 @@
* published by the Free Software Foundation.
*/
+#include plat/cpu.h
#include plat/smartreflex.h
static int sr_class3_enable(struct voltagedomain *voltdm,
@@ -49,6 +50,10 @@ static struct omap_sr_class_data class3_data = {
/* Smartreflex Class3 init API to be called from board file */
static int __init sr_class3_init(void)
{
+ /* Enable this class only for OMAP343x */
+ if (!cpu_is_omap343x())
+ return -EINVAL;
+
pr_info(SmartReflex Class3 initialized\n);
return sr_register_class(class3_data);
}
--
1.7.1
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Re: [PATCH 3/3] OMAP4: Enable Turbo and Nitro OPP for OMAP4
On Wed, Feb 16, 2011 at 11:48, Shweta Gulati shweta.gul...@ti.com wrote:
All OMAP4 boards support OPP-Turbo (800M) and OPP-Nitro (1G).
s/All OMAP4/Almost all/ - there are a minority of boards that use
OMAP4430-800 device instead of the OMAP4430-1000 device.
Also please use the full term 1GHz instead of 1G
Enable them by default in OPPTable. For 800Mhz devices where
s/For 800Mhz/For the small minority of boards which use OMAP4430-800
(800MHz device),
OPP-Nitro is not supported, OPP-Nitro should be disabled
from board file.
even though the TI documentation terminology is Turbo, Nitro etc.., I
suggest using frequencies to better map things historically.
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
arch/arm/mach-omap2/opp4xxx_data.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c
b/arch/arm/mach-omap2/opp4xxx_data.c
index 705fe9a..48d79e5 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -31,9 +31,9 @@ static struct omap_opp_def __initdata
omap44xx_opp_def_list[] = {
/* MPU OPP2 - OPP100 */
OPP_INITIALIZER(mpu, true, 6, OMAP4430_VDD_MPU_OPP100_UV),
/* MPU OPP3 - OPP-Turbo */
- OPP_INITIALIZER(mpu, false, 8,
OMAP4430_VDD_MPU_OPPTURBO_UV),
+ OPP_INITIALIZER(mpu, true, 8, OMAP4430_VDD_MPU_OPPTURBO_UV),
/* MPU OPP4 - OPP-SB */
- OPP_INITIALIZER(mpu, false, 100800,
OMAP4430_VDD_MPU_OPPNITRO_UV),
+ OPP_INITIALIZER(mpu, true, 100800,
OMAP4430_VDD_MPU_OPPNITRO_UV),
/* L3 OPP1 - OPP50 */
OPP_INITIALIZER(l3_main_1, true, 1,
OMAP4430_VDD_CORE_OPP50_UV),
/* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
--
1.7.0.4
I am ok with the overall patch - with the minor suggestions above.
Regards,
Nishanth Menon
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Re: [PATCH 2/3] OMAP2+: Replace Voltage values with Macros.
2011/2/16 Shweta Gulati shweta.gul...@ti.com:
From: Vishwanath BS vishwanath...@ti.com
Currently voltage values on opp tables are hardcoded. As these voltage values
are anyway defined in voltage.h as macros, opp table can reuse these values.
This will avoid opp table and voltage layer having conflicting values.
Acked-by: Nishanth Menon n...@ti.com
Warning: with the cleanups that Paul is doing in
http://marc.info/?l=linux-arm-kernelm=129867019501257w=2
There can be some sets of minor conflicts.
Regards,
Nishanth Menon
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
arch/arm/mach-omap2/opp3xxx_data.c | 47 ++-
arch/arm/mach-omap2/opp4xxx_data.c | 13 +
2 files changed, 31 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c
b/arch/arm/mach-omap2/opp3xxx_data.c
index fd3a1af..e3ea9ba 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -19,21 +19,22 @@
#include linux/module.h
#include plat/cpu.h
+#include plat/voltage.h
#include omap_opp_data.h
#include pm.h
static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
/* MPU OPP1 */
- OPP_INITIALIZER(mpu, true, 12500, 975000),
+ OPP_INITIALIZER(mpu, true, 12500, OMAP3430_VDD_MPU_OPP1_UV),
/* MPU OPP2 */
- OPP_INITIALIZER(mpu, true, 25000, 1075000),
+ OPP_INITIALIZER(mpu, true, 25000, OMAP3430_VDD_MPU_OPP2_UV),
/* MPU OPP3 */
- OPP_INITIALIZER(mpu, true, 5, 120),
+ OPP_INITIALIZER(mpu, true, 5, OMAP3430_VDD_MPU_OPP3_UV),
/* MPU OPP4 */
- OPP_INITIALIZER(mpu, true, 55000, 127),
+ OPP_INITIALIZER(mpu, true, 55000, OMAP3430_VDD_MPU_OPP4_UV),
/* MPU OPP5 */
- OPP_INITIALIZER(mpu, true, 6, 135),
+ OPP_INITIALIZER(mpu, true, 6, OMAP3430_VDD_MPU_OPP5_UV),
/*
* L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is
@@ -43,47 +44,47 @@ static struct omap_opp_def __initdata
omap34xx_opp_def_list[] = {
* impact that frequency will do to the MPU and the whole system in
* general.
*/
- OPP_INITIALIZER(l3_main, false, 4150, 975000),
+ OPP_INITIALIZER(l3_main, false, 4150,
OMAP3430_VDD_CORE_OPP1_UV),
/* L3 OPP2 */
- OPP_INITIALIZER(l3_main, true, 8300, 105),
+ OPP_INITIALIZER(l3_main, true, 8300, OMAP3430_VDD_CORE_OPP2_UV),
/* L3 OPP3 */
- OPP_INITIALIZER(l3_main, true, 16600, 115),
+ OPP_INITIALIZER(l3_main, true, 16600,
OMAP3430_VDD_CORE_OPP3_UV),
/* DSP OPP1 */
- OPP_INITIALIZER(iva, true, 9000, 975000),
+ OPP_INITIALIZER(iva, true, 9000, OMAP3430_VDD_MPU_OPP1_UV),
/* DSP OPP2 */
- OPP_INITIALIZER(iva, true, 18000, 1075000),
+ OPP_INITIALIZER(iva, true, 18000, OMAP3430_VDD_MPU_OPP2_UV),
/* DSP OPP3 */
- OPP_INITIALIZER(iva, true, 36000, 120),
+ OPP_INITIALIZER(iva, true, 36000, OMAP3430_VDD_MPU_OPP3_UV),
/* DSP OPP4 */
- OPP_INITIALIZER(iva, true, 4, 127),
+ OPP_INITIALIZER(iva, true, 4, OMAP3430_VDD_MPU_OPP4_UV),
/* DSP OPP5 */
- OPP_INITIALIZER(iva, true, 43000, 135),
+ OPP_INITIALIZER(iva, true, 43000, OMAP3430_VDD_MPU_OPP5_UV),
};
static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {
/* MPU OPP1 - OPP50 */
- OPP_INITIALIZER(mpu, true, 3, 1012500),
+ OPP_INITIALIZER(mpu, true, 3, OMAP3630_VDD_MPU_OPP50_UV),
/* MPU OPP2 - OPP100 */
- OPP_INITIALIZER(mpu, true, 6, 120),
+ OPP_INITIALIZER(mpu, true, 6, OMAP3630_VDD_MPU_OPP100_UV),
/* MPU OPP3 - OPP-Turbo */
- OPP_INITIALIZER(mpu, false, 8, 1325000),
+ OPP_INITIALIZER(mpu, false, 8, OMAP3630_VDD_MPU_OPP120_UV),
/* MPU OPP4 - OPP-SB */
- OPP_INITIALIZER(mpu, false, 10, 1375000),
+ OPP_INITIALIZER(mpu, false, 10, OMAP3630_VDD_MPU_OPP1G_UV),
/* L3 OPP1 - OPP50 */
- OPP_INITIALIZER(l3_main, true, 1, 100),
+ OPP_INITIALIZER(l3_main, true, 1,
OMAP3630_VDD_CORE_OPP50_UV),
/* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
- OPP_INITIALIZER(l3_main, true, 2, 120),
+ OPP_INITIALIZER(l3_main, true, 2,
OMAP3630_VDD_CORE_OPP100_UV),
/* DSP OPP1 - OPP50 */
- OPP_INITIALIZER(iva, true, 26000, 1012500),
+ OPP_INITIALIZER(iva, true, 26000, OMAP3630_VDD_MPU_OPP50_UV),
/* DSP OPP2 - OPP100 */
- OPP_INITIALIZER(iva, true, 52000, 120),
+ OPP_INITIALIZER(iva, true, 52000, OMAP3630_VDD_MPU_OPP100_UV),
/* DSP OPP3 -
Re: [PATCH] omap:iommu-added cache flushing operation for L2 cache
Hi,
On Tue, Mar 1, 2011 at 9:46 PM, Fernando Guzman Lugo
fernando.l...@ti.com wrote:
From: Ramesh Gupta grgu...@ti.com
No patch body description at all?
Can we get at least something here?
Regards,
David
Signed-off-by: Ramesh Gupta grgu...@ti.com
Signed-off-by: Hari Kanigeri h-kanige...@ti.com
---
arch/arm/plat-omap/iommu.c | 22 --
1 files changed, 8 insertions(+), 14 deletions(-)
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index e3eb038..aeb2c33 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -471,22 +471,15 @@ EXPORT_SYMBOL_GPL(foreach_iommu_device);
*/
static void flush_iopgd_range(u32 *first, u32 *last)
{
- /* FIXME: L2 cache should be taken care of if it exists */
- do {
- asm(mcr p15, 0, %0, c7, c10, 1 @ flush_pgd
- : : r (first));
- first += L1_CACHE_BYTES / sizeof(*first);
- } while (first = last);
+ dmac_flush_range(first, last);
+ outer_flush_range(virt_to_phys(first), virt_to_phys(last));
}
+
static void flush_iopte_range(u32 *first, u32 *last)
{
- /* FIXME: L2 cache should be taken care of if it exists */
- do {
- asm(mcr p15, 0, %0, c7, c10, 1 @ flush_pte
- : : r (first));
- first += L1_CACHE_BYTES / sizeof(*first);
- } while (first = last);
+ dmac_flush_range(first, last);
+ outer_flush_range(virt_to_phys(first), virt_to_phys(last));
}
static void iopte_free(u32 *iopte)
@@ -750,7 +743,7 @@ size_t iopgtable_clear_entry(struct iommu *obj, u32 da)
}
EXPORT_SYMBOL_GPL(iopgtable_clear_entry);
-static void iopgtable_clear_entry_all(struct iommu *obj)
+void iopgtable_clear_entry_all(struct iommu *obj)
{
int i;
@@ -777,7 +770,7 @@ static void iopgtable_clear_entry_all(struct iommu *obj)
spin_unlock(obj-page_table_lock);
}
-
+EXPORT_SYMBOL_GPL(iopgtable_clear_entry_all);
/*
* Device IOMMU generic operations
*/
@@ -1068,6 +1061,7 @@ static void iopte_cachep_ctor(void *iopte)
clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
}
+
static int __init omap_iommu_init(void)
{
struct kmem_cache *p;
--
1.7.0.4
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Re: [PATCH] OMAP:iommu - pgd and pte entries weren't getting flushed out
Hi,
On Tue, Mar 1, 2011 at 9:46 PM, Fernando Guzman Lugo
fernando.l...@ti.com wrote:
From: Hari Kanigeri h-kanige...@ti.com
pgd and pte entries weren't getting flushed out leading to MMU faults.
May I ask you to add to the patch body description why it's wrong and
why your solution is necessary?
Br,
David
Signed-off-by: Hari Kanigeri h-kanige...@ti.com
---
arch/arm/plat-omap/iommu.c | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index aeb2c33..e9473ff 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -508,7 +508,7 @@ static u32 *iopte_alloc(struct iommu *obj, u32 *iopgd,
u32 da)
return ERR_PTR(-ENOMEM);
*iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
- flush_iopgd_range(iopgd, iopgd);
+ flush_iopgd_range(iopgd, iopgd + 1);
dev_vdbg(obj-dev, %s: a new pte:%p\n, __func__, iopte);
} else {
@@ -537,7 +537,7 @@ static int iopgd_alloc_section(struct iommu *obj, u32 da,
u32 pa, u32 prot)
}
*iopgd = (pa IOSECTION_MASK) | prot | IOPGD_SECTION;
- flush_iopgd_range(iopgd, iopgd);
+ flush_iopgd_range(iopgd, iopgd + 1);
return 0;
}
@@ -554,7 +554,7 @@ static int iopgd_alloc_super(struct iommu *obj, u32 da,
u32 pa, u32 prot)
for (i = 0; i 16; i++)
*(iopgd + i) = (pa IOSUPER_MASK) | prot | IOPGD_SUPER;
- flush_iopgd_range(iopgd, iopgd + 15);
+ flush_iopgd_range(iopgd, iopgd + 16);
return 0;
}
@@ -567,7 +567,7 @@ static int iopte_alloc_page(struct iommu *obj, u32 da,
u32 pa, u32 prot)
return PTR_ERR(iopte);
*iopte = (pa IOPAGE_MASK) | prot | IOPTE_SMALL;
- flush_iopte_range(iopte, iopte);
+ flush_iopte_range(iopte, iopte + 1);
dev_vdbg(obj-dev, %s: da:%08x pa:%08x pte:%p *pte:%08x\n,
__func__, da, pa, iopte, *iopte);
@@ -592,7 +592,7 @@ static int iopte_alloc_large(struct iommu *obj, u32 da,
u32 pa, u32 prot)
for (i = 0; i 16; i++)
*(iopte + i) = (pa IOLARGE_MASK) | prot | IOPTE_LARGE;
- flush_iopte_range(iopte, iopte + 15);
+ flush_iopte_range(iopte, iopte + 16);
return 0;
}
@@ -763,7 +763,7 @@ void iopgtable_clear_entry_all(struct iommu *obj)
iopte_free(iopte_offset(iopgd, 0));
*iopgd = 0;
- flush_iopgd_range(iopgd, iopgd);
+ flush_iopgd_range(iopgd, iopgd + 1);
}
flush_iotlb_all(obj);
--
1.7.0.4
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RE: [patch v2 3/3] arm: omap4: support pmu
Tom,
-Original Message-
From: linux-arm-kernel-boun...@lists.infradead.org [mailto:linux-
arm-kernel-boun...@lists.infradead.org] On Behalf Of
tom.leim...@gmail.com
Sent: Wednesday, March 02, 2011 4:27 PM
To: li...@arm.linux.org.uk
Cc: Woodruff Richard; Tony Lindgren; Ming Lei; will.dea...@arm.com;
linux-omap@vger.kernel.org; linux-arm-ker...@lists.infradead.org
Subject: [patch v2 3/3] arm: omap4: support pmu
From: Ming Lei tom.leim...@gmail.com
This patch supports pmu irq routed from CTI, so
make pmu/perf working on OMAP4.
The idea is from Woodruff Richard in the disscussion
about Oprofile on Pandaboard / Omap4 on
pandabo...@googlegroups.com.
Cc: Woodruff Richard r-woodru...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: linux-omap@vger.kernel.org
Signed-off-by: Ming Lei tom.leim...@gmail.com
---
Few comments.
arch/arm/mach-omap2/dbg44xx.h | 18 +
arch/arm/mach-omap2/devices.c | 83
+++-
2 files changed, 98 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/mach-omap2/dbg44xx.h
diff --git a/arch/arm/mach-omap2/dbg44xx.h b/arch/arm/mach-
omap2/dbg44xx.h
new file mode 100644
index 000..e447ad5
--- /dev/null
+++ b/arch/arm/mach-omap2/dbg44xx.h
@@ -0,0 +1,18 @@
+/*
+ * OMAP44xx on-chip debug support
+ *
+ * This program is free software; you can redistribute it and/or
modify
+ * it under the terms of the GNU General Public License version 2
as
+ * published by the Free Software Foundation.
+ *
+ * XXX This file needs to be updated to align on one of OMAP4,
OMAP44XX,
+ * or OMAP4430.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_DBG44XX_H
+#define __ARCH_ARM_MACH_OMAP2_DBG44XX_H
+
+#define OMAP44XX_CTI0_BASE 0x54148000
+#define OMAP44XX_CTI1_BASE 0x54149000
+
+#endif
You don't need this file. Move this base addresses to
arch/arm/plat-omap/include/plat/omap44xx.h
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-
omap2/devices.c
index d216976..bae02d5 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -22,6 +22,7 @@
#include asm/mach-types.h
#include asm/mach/map.h
#include asm/pmu.h
+#include asm/cti.h
#include plat/tc.h
#include plat/board.h
@@ -35,6 +36,7 @@
#include mux.h
#include control.h
+#include dbg44xx.h
#if defined(CONFIG_VIDEO_OMAP2) ||
defined(CONFIG_VIDEO_OMAP2_MODULE)
@@ -322,20 +324,95 @@ static struct resource omap3_pmu_resource = {
.flags = IORESOURCE_IRQ,
};
+static struct resource omap4_pmu_resource[] = {
+ {
+ .start = OMAP44XX_IRQ_CTI0,
+ .end= OMAP44XX_IRQ_CTI0,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = OMAP44XX_IRQ_CTI1,
+ .end= OMAP44XX_IRQ_CTI1,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
static struct platform_device omap_pmu_device = {
.name = arm-pmu,
.id = ARM_PMU_DEVICE_CPU,
.num_resources = 1,
};
+static struct arm_pmu_platdata omap4_pmu_data;
+static struct cti omap4_cti[2];
+
+static void omap4_enable_cti(int irq)
+{
+ if (irq == OMAP44XX_IRQ_CTI0)
+ cti_enable(omap4_cti[0]);
+ else if (irq == OMAP44XX_IRQ_CTI1)
+ cti_enable(omap4_cti[1]);
+}
+
+static void omap4_disable_cti(int irq)
+{
+ if (irq == OMAP44XX_IRQ_CTI0)
+ cti_disable(omap4_cti[0]);
+ else if (irq == OMAP44XX_IRQ_CTI1)
+ cti_disable(omap4_cti[1]);
+}
+
+static irqreturn_t omap4_pmu_handler(int irq, void *dev,
irq_handler_t handler)
+{
+ if (irq == OMAP44XX_IRQ_CTI0)
+ cti_irq_ack(omap4_cti[0]);
+ else if (irq == OMAP44XX_IRQ_CTI1)
+ cti_irq_ack(omap4_cti[1]);
+
+ return handler(irq, dev);
+}
+
+static void omap4_configure_pmu_irq(void)
+{
+ void *base0;
+ void *base1;
s/ void *base/ void __iomem *base
+
+ base0 = ioremap(OMAP44XX_CTI0_BASE, 4096);
s/4096/SZ_4K
+ base1 = ioremap(OMAP44XX_CTI1_BASE, 4096);
+ if (!base0 !base1) {
+ pr_err(ioremap for omap4 CTI failed\n);
s/omap4/OMAP4
+ return;
+ }
+
+ /*configure CTI0 for pmu irq routing*/
+ cti_init(omap4_cti[0], base0, OMAP44XX_IRQ_CTI0, 6);
+ cti_unlock(omap4_cti[0]);
+ cti_map_trigger(omap4_cti[0], 1, 6, 2);
+
+ /*configure CTI1 for pmu irq routing*/
+ cti_init(omap4_cti[1], base1, OMAP44XX_IRQ_CTI1, 6);
+ cti_unlock(omap4_cti[1]);
+ cti_map_trigger(omap4_cti[1], 1, 6, 2);
+
+ omap4_pmu_data.handle_irq = omap4_pmu_handler;
+ omap4_pmu_data.enable_irq = omap4_enable_cti;
+ omap4_pmu_data.disable_irq = omap4_disable_cti;
+}
+
static void omap_init_pmu(void)
{
- if (cpu_is_omap24xx())
+ if (cpu_is_omap24xx()) {
omap_pmu_device.resource = omap2_pmu_resource;
- else if (cpu_is_omap34xx())
+ } else if
RE: [PATCH] omap:iommu-added cache flushing operation for L2 cache
Hello,
-Original Message-
From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap-
ow...@vger.kernel.org] On Behalf Of Fernando Guzman Lugo
Sent: Wednesday, March 02, 2011 1:17 AM
To: hiroshi.d...@nokia.com
Cc: t...@atomide.com; li...@arm.linux.org.uk; linux-
o...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
ker...@vger.kernel.org; Ramesh Gupta; Hari Kanigeri
Subject: [PATCH] omap:iommu-added cache flushing operation for L2
cache
From: Ramesh Gupta grgu...@ti.com
Signed-off-by: Ramesh Gupta grgu...@ti.com
Signed-off-by: Hari Kanigeri h-kanige...@ti.com
---
arch/arm/plat-omap/iommu.c | 22 --
1 files changed, 8 insertions(+), 14 deletions(-)
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index e3eb038..aeb2c33 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -471,22 +471,15 @@ EXPORT_SYMBOL_GPL(foreach_iommu_device);
*/
static void flush_iopgd_range(u32 *first, u32 *last)
{
- /* FIXME: L2 cache should be taken care of if it exists */
- do {
- asm(mcrp15, 0, %0, c7, c10, 1 @ flush_pgd
- : : r (first));
- first += L1_CACHE_BYTES / sizeof(*first);
- } while (first = last);
+ dmac_flush_range(first, last);
There is note just above this API.
/*
* These are private to the dma-mapping API. Do not use directly.
* Their sole purpose is to ensure that data held in the cache
* is visible to DMA, or data written by DMA to system memory is
* visible to the CPU.
*/
#define dmac_map_area cpu_cache.dma_map_area
#define dmac_unmap_area cpu_cache.dma_unmap_area
#define dmac_flush_rangecpu_cache.dma_flush_range
+ outer_flush_range(virt_to_phys(first), virt_to_phys(last));
}
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[PATCH 1/2] omap: Remove unnecessary twl4030_codec_audio settings from board files
twl4030_codec_audio and twl4030_codec_vibra_data has unused field.
In order to remove it, corresponding settings needs to be removed
from board files.
Signed-off-by: Ilkka Koskinen ilkka.koski...@nokia.com
---
arch/arm/mach-omap2/board-3430sdp.c |4 +---
arch/arm/mach-omap2/board-devkit8000.c |4 +---
arch/arm/mach-omap2/board-igep0020.c |4 +---
arch/arm/mach-omap2/board-omap3beagle.c |4 +---
arch/arm/mach-omap2/board-omap3evm.c |4 +---
arch/arm/mach-omap2/board-omap3pandora.c |4 +---
arch/arm/mach-omap2/board-omap3stalker.c |4 +---
arch/arm/mach-omap2/board-omap3touchbook.c |4 +---
arch/arm/mach-omap2/board-overo.c|4 +---
arch/arm/mach-omap2/board-zoom-peripherals.c |4 +---
10 files changed, 10 insertions(+), 30 deletions(-)
diff --git a/arch/arm/mach-omap2/board-3430sdp.c
b/arch/arm/mach-omap2/board-3430sdp.c
index d4e41ef..4722ffa 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -567,9 +567,7 @@ static struct regulator_init_data sdp3430_vpll2 = {
.consumer_supplies = sdp3430_vpll2_supplies,
};
-static struct twl4030_codec_audio_data sdp3430_audio = {
- .audio_mclk = 2600,
-};
+static struct twl4030_codec_audio_data sdp3430_audio;
static struct twl4030_codec_data sdp3430_codec = {
.audio_mclk = 2600,
diff --git a/arch/arm/mach-omap2/board-devkit8000.c
b/arch/arm/mach-omap2/board-devkit8000.c
index 00bb1fc..755f63a 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -346,9 +346,7 @@ static struct twl4030_usb_data devkit8000_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
-static struct twl4030_codec_audio_data devkit8000_audio_data = {
- .audio_mclk = 2600,
-};
+static struct twl4030_codec_audio_data devkit8000_audio_data;
static struct twl4030_codec_data devkit8000_codec_data = {
.audio_mclk = 2600,
diff --git a/arch/arm/mach-omap2/board-igep0020.c
b/arch/arm/mach-omap2/board-igep0020.c
index 3be85a1..6022990 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -533,9 +533,7 @@ static void __init igep2_init_irq(void)
omap_init_irq();
}
-static struct twl4030_codec_audio_data igep2_audio_data = {
- .audio_mclk = 2600,
-};
+static struct twl4030_codec_audio_data igep2_audio_data;
static struct twl4030_codec_data igep2_codec_data = {
.audio_mclk = 2600,
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c
b/arch/arm/mach-omap2/board-omap3beagle.c
index 46d814a..164b4c3 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -435,9 +435,7 @@ static struct twl4030_usb_data beagle_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
-static struct twl4030_codec_audio_data beagle_audio_data = {
- .audio_mclk = 2600,
-};
+static struct twl4030_codec_audio_data beagle_audio_data;
static struct twl4030_codec_data beagle_codec_data = {
.audio_mclk = 2600,
diff --git a/arch/arm/mach-omap2/board-omap3evm.c
b/arch/arm/mach-omap2/board-omap3evm.c
index 323c380..db147d7 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -491,9 +491,7 @@ static struct twl4030_madc_platform_data omap3evm_madc_data
= {
.irq_line = 1,
};
-static struct twl4030_codec_audio_data omap3evm_audio_data = {
- .audio_mclk = 2600,
-};
+static struct twl4030_codec_audio_data omap3evm_audio_data;
static struct twl4030_codec_data omap3evm_codec_data = {
.audio_mclk = 2600,
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c
b/arch/arm/mach-omap2/board-omap3pandora.c
index 0b34bed..51e8c20 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -524,9 +524,7 @@ static struct twl4030_usb_data omap3pandora_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
-static struct twl4030_codec_audio_data omap3pandora_audio_data = {
- .audio_mclk = 2600,
-};
+static struct twl4030_codec_audio_data omap3pandora_audio_data;
static struct twl4030_codec_data omap3pandora_codec_data = {
.audio_mclk = 2600,
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c
b/arch/arm/mach-omap2/board-omap3stalker.c
index 2a2dad4..2572f71 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -439,9 +439,7 @@ static struct twl4030_madc_platform_data
omap3stalker_madc_data = {
.irq_line = 1,
};
-static struct twl4030_codec_audio_data omap3stalker_audio_data = {
- .audio_mclk = 2600,
-};
+static struct twl4030_codec_audio_data omap3stalker_audio_data;
static struct twl4030_codec_data omap3stalker_codec_data = {
.audio_mclk = 2600,
diff --git
[PATCH 2/2] mfd: twl4030_codec: Remove unused and duplicate audio_mclk fields
audio_mclk can be queried from mfd driver. Therefore, it is not
needed in twl4030_codec_audio_data or in twl4030_codec_vibra_data
anymore.
Signed-off-by: Ilkka Koskinen ilkka.koski...@nokia.com
---
include/linux/i2c/twl.h |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
index 61b9609..9d88b71 100644
--- a/include/linux/i2c/twl.h
+++ b/include/linux/i2c/twl.h
@@ -637,7 +637,6 @@ extern void twl4030_power_init(struct twl4030_power_data
*triton2_scripts);
extern int twl4030_remove_script(u8 flags);
struct twl4030_codec_audio_data {
- unsigned int audio_mclk; /* not used, will be removed */
unsigned int digimic_delay; /* in ms */
unsigned int ramp_delay_value;
unsigned int offset_cncl_path;
@@ -648,7 +647,6 @@ struct twl4030_codec_audio_data {
};
struct twl4030_codec_vibra_data {
- unsigned intaudio_mclk;
unsigned intcoexist;
};
--
1.7.0.4
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[PATCH 0/2] twl4030_codec cleanup
This series of patches removes duplicate audio_mclk fields from twl4030_codec driver. The patches have been compiled on sound-2.6/for-2.6.39 branch. I haven't tested them on any target board though. Ilkka Koskinen (2): omap: Remove unnecessary twl4030_codec_audio settings from board files mfd: twl4030_codec: Remove unused and duplicate audio_mclk fields arch/arm/mach-omap2/board-3430sdp.c |4 +--- arch/arm/mach-omap2/board-devkit8000.c |4 +--- arch/arm/mach-omap2/board-igep0020.c |4 +--- arch/arm/mach-omap2/board-omap3beagle.c |4 +--- arch/arm/mach-omap2/board-omap3evm.c |4 +--- arch/arm/mach-omap2/board-omap3pandora.c |4 +--- arch/arm/mach-omap2/board-omap3stalker.c |4 +--- arch/arm/mach-omap2/board-omap3touchbook.c |4 +--- arch/arm/mach-omap2/board-overo.c|4 +--- arch/arm/mach-omap2/board-zoom-peripherals.c |4 +--- include/linux/i2c/twl.h |2 -- 11 files changed, 10 insertions(+), 32 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/2] twl4030_codec cleanup
On 03/02/11 15:24, Ilkka Koskinen wrote: This series of patches removes duplicate audio_mclk fields from twl4030_codec driver. The patches have been compiled on sound-2.6/for-2.6.39 branch. I haven't tested them on any target board though. Ilkka Koskinen (2): omap: Remove unnecessary twl4030_codec_audio settings from board files mfd: twl4030_codec: Remove unused and duplicate audio_mclk fields arch/arm/mach-omap2/board-3430sdp.c |4 +--- arch/arm/mach-omap2/board-devkit8000.c |4 +--- arch/arm/mach-omap2/board-igep0020.c |4 +--- arch/arm/mach-omap2/board-omap3beagle.c |4 +--- arch/arm/mach-omap2/board-omap3evm.c |4 +--- arch/arm/mach-omap2/board-omap3pandora.c |4 +--- arch/arm/mach-omap2/board-omap3stalker.c |4 +--- arch/arm/mach-omap2/board-omap3touchbook.c |4 +--- arch/arm/mach-omap2/board-overo.c|4 +--- arch/arm/mach-omap2/board-zoom-peripherals.c |4 +--- include/linux/i2c/twl.h |2 -- 11 files changed, 10 insertions(+), 32 deletions(-) Thanks Ilkka! This was in my to do list, now I can remove this item. All: Acked-by: Peter Ujfalusi peter.ujfal...@nokia.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v8 2/7] omap3: pm: Correct the warning print during script loading
Correcting the if condition check for printing the warning,
if wakeup script is not updated before updating the sleep script.
Since the flag 'order' is set to '1' while updating the wakeup script for P1P2,
the condition checking for printing the warning should be if(!order)
(ie: print the warning if wakeup script is not updated before updating the
sleep script)
Signed-off-by: Lesly A M lesl...@ti.com
Cc: Nishanth Menon n...@ti.com
Cc: David Derrick dderr...@ti.com
Cc: Samuel Ortiz sa...@linux.intel.com
---
drivers/mfd/twl4030-power.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/mfd/twl4030-power.c b/drivers/mfd/twl4030-power.c
index 2c0d4d1..8373d79 100644
--- a/drivers/mfd/twl4030-power.c
+++ b/drivers/mfd/twl4030-power.c
@@ -448,7 +448,7 @@ static int __init load_twl4030_script(struct twl4030_script
*tscript,
goto out;
}
if (tscript-flags TWL4030_SLEEP_SCRIPT) {
- if (order)
+ if (!order)
pr_warning(TWL4030: Bad order of scripts (sleep \
script before wakeup) Leads to boot\
failure on some boards\n);
--
1.7.1
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[PATCH v8 1/7] omap3: pm: Fix for the TRITON sleep/wakeup sequence
Only configure sleep script when the flag is TWL4030_SLEEP_SCRIPT.
Adding the missing brackets for fixing the issue.
Signed-off-by: Lesly A M lesl...@ti.com
Cc: Nishanth Menon n...@ti.com
Cc: David Derrick dderr...@ti.com
Cc: Samuel Ortiz sa...@linux.intel.com
---
drivers/mfd/twl4030-power.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/drivers/mfd/twl4030-power.c b/drivers/mfd/twl4030-power.c
index 16422de..2c0d4d1 100644
--- a/drivers/mfd/twl4030-power.c
+++ b/drivers/mfd/twl4030-power.c
@@ -447,12 +447,13 @@ static int __init load_twl4030_script(struct
twl4030_script *tscript,
if (err)
goto out;
}
- if (tscript-flags TWL4030_SLEEP_SCRIPT)
+ if (tscript-flags TWL4030_SLEEP_SCRIPT) {
if (order)
pr_warning(TWL4030: Bad order of scripts (sleep \
script before wakeup) Leads to boot\
failure on some boards\n);
err = twl4030_config_sleep_sequence(address);
+ }
out:
return err;
}
--
1.7.1
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[PATCH v8 0/8] omap3: pm: TWL4030 power scripts and workaround for TWL errata 27
Patch series for TWL4030 power scripts and workaround for TWL errata 27. Changes for implementing TWL4030 power scripts recommended by hardware team. Introduced a new TWL4030 power script file, which can be used by different OMAP3 board with the power companion chip TWL4030. Updated the changes for TWL4030 errata 27 28, and modified the TWL4030 power script. Workaround for TWL4030 errata 27 28 is required for Si version less than or equal to TWL5030 ES1.1. TWL4030 script changes rebased on Kevin's PM tree in pm branch. Changes in v7: changes to fix Nishanth Menon's comments i) Added the TWL4030 Errata 27 fix split the first patch in v6 i) fix for twl4030 script load ii) correct the warning print during script loading Added new patch files i) changing sys_off signal polarity Changes in v8: updated the change logs moving the TWL IDCODE checking to twl-core.c Since the voltage layer is evolving to a new design, the voltage dependant changes required for the TRITON script are not incorporated in the patch series. So this TRITON script patch series can be tested with a separate patch for voltage layer changes. lnk: http://pastebin.mozilla.org/1118306 This changes are tested on OMAP3430 OMAP3630 SDP with off mode enabled in suspend path. Tested with suspend/resume script, which will test system suspend in a loop. Tested for more than 1000 iterations. Cc: Nishanth Menon n...@ti.com Cc: David Derrick dderr...@ti.com Cc: Samuel Ortiz sa...@linux.intel.com --- Lesly A M (7): omap3: pm: Fix for the TRITON sleep/wakeup sequence omap3: pm: Correct the warning print during script loading omap3: pm: TWL4030 power scripts for OMAP3 boards omap3: pm: TWL5030 version checking mfd: TWL4030: changes for TRITON Errata 27 workaround omap3430: Updating the board file to use TWL4030 scripts omap3630: Updating the board file to use TWL4030 scripts arch/arm/mach-omap2/Makefile | 12 +- arch/arm/mach-omap2/board-3430sdp.c | 93 +- arch/arm/mach-omap2/board-zoom-peripherals.c |2 + arch/arm/mach-omap2/twl4030.c| 259 ++ arch/arm/mach-omap2/twl4030.h| 20 ++ drivers/mfd/twl-core.c | 61 ++ drivers/mfd/twl4030-power.c | 69 +++- include/linux/i2c/twl.h | 51 +- 8 files changed, 466 insertions(+), 101 deletions(-) create mode 100644 arch/arm/mach-omap2/twl4030.c create mode 100644 arch/arm/mach-omap2/twl4030.h -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v8 3/7] omap3: pm: TWL4030 power scripts for OMAP3 boards
Power bus message sequence for TWL4030 to enter sleep/wakeup/warm_reset.
TWL4030 power scripts which can be used by different OMAP3 boards
with the power companion chip (TWL4030 series).
The twl4030 generic script is exported and can be used by any other
boardfile to update the power data in twl4030_platform_data.
http://omapedia.org/wiki/TWL4030_power_scripts
Signed-off-by: Lesly A M lesl...@ti.com
Cc: Nishanth Menon n...@ti.com
Cc: David Derrick dderr...@ti.com
Cc: Samuel Ortiz sa...@linux.intel.com
---
arch/arm/mach-omap2/twl4030.c | 145 +
arch/arm/mach-omap2/twl4030.h | 20 ++
include/linux/i2c/twl.h | 33 +-
3 files changed, 195 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/mach-omap2/twl4030.c
create mode 100644 arch/arm/mach-omap2/twl4030.h
diff --git a/arch/arm/mach-omap2/twl4030.c b/arch/arm/mach-omap2/twl4030.c
new file mode 100644
index 000..ff344b3
--- /dev/null
+++ b/arch/arm/mach-omap2/twl4030.c
@@ -0,0 +1,145 @@
+/*
+ * OMAP power script for PMIC TWL4030
+ *
+ * Author: Lesly A M lesl...@ti.com
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Lesly A M lesl...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifdef CONFIG_TWL4030_POWER
+
+#include twl4030.h
+
+/*
+ * Sequence to control the TRITON Power resources,
+ * when the system goes into sleep.
+ * Executed upon P1_P2/P3 transition for sleep.
+ */
+static struct twl4030_ins __initdata sleep_on_seq[] = {
+ /* Broadcast message to put res to sleep */
+ {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R1,
+ RES_STATE_SLEEP), 2},
+ {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R2,
+ RES_STATE_SLEEP), 2},
+};
+
+static struct twl4030_script sleep_on_script __initdata = {
+ .script = sleep_on_seq,
+ .size = ARRAY_SIZE(sleep_on_seq),
+ .flags = TWL4030_SLEEP_SCRIPT,
+};
+
+/*
+ * Sequence to control the TRITON Power resources,
+ * when the system wakeup from sleep.
+ * Executed upon P1_P2 transition for wakeup.
+ */
+static struct twl4030_ins wakeup_p12_seq[] __initdata = {
+ /* Broadcast message to put res to active */
+ {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R1,
+ RES_STATE_ACTIVE), 2},
+};
+
+static struct twl4030_script wakeup_p12_script __initdata = {
+ .script = wakeup_p12_seq,
+ .size = ARRAY_SIZE(wakeup_p12_seq),
+ .flags = TWL4030_WAKEUP12_SCRIPT,
+};
+
+/*
+ * Sequence to control the TRITON Power resources,
+ * when the system wakeup from sleep.
+ * Executed upon P3 transition for wakeup.
+ */
+static struct twl4030_ins wakeup_p3_seq[] __initdata = {
+ /* Broadcast message to put res to active */
+ {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R2,
+ RES_STATE_ACTIVE), 2},
+};
+
+static struct twl4030_script wakeup_p3_script __initdata = {
+ .script = wakeup_p3_seq,
+ .size = ARRAY_SIZE(wakeup_p3_seq),
+ .flags = TWL4030_WAKEUP3_SCRIPT,
+};
+
+/*
+ * Sequence to reset the TRITON Power resources,
+ * when the system gets warm reset.
+ * Executed upon warm reset signal.
+ */
+static struct twl4030_ins wrst_seq[] __initdata = {
+/*
+ * Reset twl4030.
+ * Reset Main_Ref.
+ * Reset All type2_group2.
+ * Reset VUSB_3v1.
+ * Reset All type2_group1.
+ * Reset RC.
+ * Reenable twl4030.
+ */
+ {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_OFF), 2},
+ {MSG_SINGULAR(DEV_GRP_NULL, RES_Main_Ref, RES_STATE_WRST), 2},
+ {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R2,
+ RES_STATE_WRST), 2},
+ {MSG_SINGULAR(DEV_GRP_NULL, RES_VUSB_3V1, RES_STATE_WRST), 2},
+ {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R1,
+ RES_STATE_WRST), 2},
+ {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_RC, RES_TYPE_ALL, RES_TYPE2_R0,
+ RES_STATE_WRST), 2},
+ {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_ACTIVE), 2},
+};
+
+static struct twl4030_script wrst_script __initdata = {
+ .script = wrst_seq,
+ .size = ARRAY_SIZE(wrst_seq),
+ .flags = TWL4030_WRST_SCRIPT,
+};
+
+/* TRITON script for sleep, wakeup warm_reset */
+static struct twl4030_script *twl4030_scripts[] __initdata = {
+ wakeup_p12_script,
+ wakeup_p3_script,
+ sleep_on_script,
+ wrst_script,
+};
+
+static struct twl4030_resconfig twl4030_rconfig[] = {
+ { .resource = RES_VPLL1,
[PATCH v8 7/7] omap3630: Updating the board file to use TWL4030 scripts
Using TWL4030 power scripts to control the LDOs and DCDC regulators
while going to low power mode.
Signed-off-by: Lesly A M lesl...@ti.com
Cc: Nishanth Menon n...@ti.com
Cc: David Derrick dderr...@ti.com
Cc: Samuel Ortiz sa...@linux.intel.com
---
arch/arm/mach-omap2/Makefile |9 ++---
arch/arm/mach-omap2/board-zoom-peripherals.c |2 ++
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index bb11329..e6d5d27 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -191,18 +191,21 @@ obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom.o
\
board-zoom-display.o \
board-flash.o \
hsmmc.o \
- board-zoom-debugboard.o
+ board-zoom-debugboard.o \
+ twl4030.o
obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom.o \
board-zoom-peripherals.o \
board-zoom-display.o \
board-flash.o \
hsmmc.o \
- board-zoom-debugboard.o
+ board-zoom-debugboard.o \
+ twl4030.o
obj-$(CONFIG_MACH_OMAP_3630SDP)+= board-3630sdp.o \
board-zoom-peripherals.o \
board-zoom-display.o \
board-flash.o \
- hsmmc.o
+ hsmmc.o \
+ twl4030.o
obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \
hsmmc.o
obj-$(CONFIG_MACH_CM_T3517)+= board-cm-t3517.o
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c
b/arch/arm/mach-omap2/board-zoom-peripherals.c
index e0e040f..f978f73 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -31,6 +31,7 @@
#include mux.h
#include hsmmc.h
+#include twl4030.h
#define OMAP_ZOOM_WLAN_PMENA_GPIO (101)
#define OMAP_ZOOM_WLAN_IRQ_GPIO(162)
@@ -341,6 +342,7 @@ static struct twl4030_platform_data zoom_twldata = {
.usb= zoom_usb_data,
.gpio = zoom_gpio_data,
.keypad = zoom_kp_twl4030_data,
+ .power = twl4030_generic_script,
.codec = zoom_codec_data,
.vmmc1 = zoom_vmmc1,
.vmmc2 = zoom_vmmc2,
--
1.7.1
--
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[PATCH v8 6/7] omap3430: Updating the board file to use TWL4030 scripts
Using TWL4030 power scripts to control the LDOs and DCDC regulators
while going to low power mode.
Signed-off-by: Lesly A M lesl...@ti.com
Cc: Nishanth Menon n...@ti.com
Cc: David Derrick dderr...@ti.com
Cc: Samuel Ortiz sa...@linux.intel.com
---
arch/arm/mach-omap2/Makefile|3 +-
arch/arm/mach-omap2/board-3430sdp.c | 93 +--
2 files changed, 4 insertions(+), 92 deletions(-)
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 742ca67..bb11329 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -175,7 +175,8 @@ obj-$(CONFIG_MACH_OMAP3_PANDORA)+= board-omap3pandora.o
\
hsmmc.o
obj-$(CONFIG_MACH_OMAP_3430SDP)+= board-3430sdp.o \
hsmmc.o \
- board-flash.o
+ board-flash.o \
+ twl4030.o
obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
obj-$(CONFIG_MACH_NOKIA_RM680) += board-rm680.o \
sdram-nokia.o \
diff --git a/arch/arm/mach-omap2/board-3430sdp.c
b/arch/arm/mach-omap2/board-3430sdp.c
index 813893b..a0bb530 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -46,6 +46,7 @@
#include mux.h
#include sdram-qimonda-hyb18m512160af-6.h
#include hsmmc.h
+#include twl4030.h
#include pm.h
#include control.h
@@ -425,96 +426,6 @@ static struct twl4030_madc_platform_data sdp3430_madc_data
= {
.irq_line = 1,
};
-
-static struct twl4030_ins __initdata sleep_on_seq[] = {
- /* Turn off HFCLKOUT */
- {MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_OFF), 2},
- /* Turn OFF VDD1 */
- {MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 2},
- /* Turn OFF VDD2 */
- {MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_OFF), 2},
- /* Turn OFF VPLL1 */
- {MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_OFF), 2},
-};
-
-static struct twl4030_script sleep_on_script __initdata = {
- .script = sleep_on_seq,
- .size = ARRAY_SIZE(sleep_on_seq),
- .flags = TWL4030_SLEEP_SCRIPT,
-};
-
-static struct twl4030_ins wakeup_p12_seq[] __initdata = {
- /* Turn on HFCLKOUT */
- {MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 2},
- /* Turn ON VDD1 */
- {MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 2},
- /* Turn ON VDD2 */
- {MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 2},
- /* Turn ON VPLL1 */
- {MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_ACTIVE), 2},
-};
-
-static struct twl4030_script wakeup_p12_script __initdata = {
- .script = wakeup_p12_seq,
- .size = ARRAY_SIZE(wakeup_p12_seq),
- .flags = TWL4030_WAKEUP12_SCRIPT,
-};
-
-static struct twl4030_ins wakeup_p3_seq[] __initdata = {
- {MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 2},
-};
-
-static struct twl4030_script wakeup_p3_script __initdata = {
- .script = wakeup_p3_seq,
- .size = ARRAY_SIZE(wakeup_p3_seq),
- .flags = TWL4030_WAKEUP3_SCRIPT,
-};
-
-static struct twl4030_ins wrst_seq[] __initdata = {
-/*
- * Reset twl4030.
- * Reset VDD1 regulator.
- * Reset VDD2 regulator.
- * Reset VPLL1 regulator.
- * Enable sysclk output.
- * Reenable twl4030.
- */
- {MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_OFF), 2},
- {MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_WRST), 15},
- {MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_WRST), 15},
- {MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_WRST), 0x60},
- {MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 2},
- {MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_ACTIVE), 2},
-};
-static struct twl4030_script wrst_script __initdata = {
- .script = wrst_seq,
- .size = ARRAY_SIZE(wrst_seq),
- .flags = TWL4030_WRST_SCRIPT,
-};
-
-static struct twl4030_script *twl4030_scripts[] __initdata = {
- sleep_on_script,
- wakeup_p12_script,
- wakeup_p3_script,
- wrst_script,
-};
-
-static struct twl4030_resconfig twl4030_rconfig[] = {
- { .resource = RES_HFCLKOUT, .devgroup = DEV_GRP_P3, .type = -1,
- .type2 = -1 },
- { .resource = RES_VDD1, .devgroup = DEV_GRP_P1, .type = -1,
- .type2 = -1 },
- { .resource = RES_VDD2, .devgroup = DEV_GRP_P1, .type = -1,
- .type2 = -1 },
- { 0, 0},
-};
-
-static struct twl4030_power_data sdp3430_t2scripts_data __initdata = {
- .scripts= twl4030_scripts,
- .num= ARRAY_SIZE(twl4030_scripts),
- .resource_config = twl4030_rconfig,
-};
-
/*
* Apply all the fixed voltages since most versions of U-Boot
* don't bother with that initialization.
@@ -673,8 +584,8 @@ static struct twl4030_platform_data sdp3430_twldata = {
.gpio = sdp3430_gpio_data,
.madc =
[PATCH v8 4/7] omap3: pm: TWL5030 version checking
Added api to get the TWL5030 Si version from the IDCODE register.
It is used for enabling the workaround for TWL errata 27.
Signed-off-by: Lesly A M lesl...@ti.com
Cc: Nishanth Menon n...@ti.com
Cc: David Derrick dderr...@ti.com
Cc: Samuel Ortiz sa...@linux.intel.com
---
drivers/mfd/twl-core.c | 61 +++
include/linux/i2c/twl.h | 17 -
2 files changed, 77 insertions(+), 1 deletions(-)
diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index a35fa7d..5e706d7 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -229,6 +229,9 @@
/* is driver active, bound to a chip? */
static bool inuse;
+/* TWL IDCODE Register value */
+static u32 twl_idcode;
+
static unsigned int twl_id;
unsigned int twl_rev(void)
{
@@ -487,6 +490,61 @@ EXPORT_SYMBOL(twl_i2c_read_u8);
/*--*/
+/**
+ * twl_read_idcode_register - api to read the IDCODE register.
+ * @value: returns 32 bit IDCODE register value.
+ *
+ * Unlocks the IDCODE register and read the 32 bit value.
+ */
+int twl_read_idcode_register(void)
+{
+ int err;
+
+ err = twl_i2c_write_u8(TWL4030_MODULE_INTBR, TWL_EEPROM_R_UNLOCK,
+ REG_UNLOCK_TEST_REG);
+ if (err) {
+ pr_err(TWL4030 Unable to unlock IDCODE registers\n);
+ goto fail;
+ }
+
+ err = twl_i2c_read(TWL4030_MODULE_INTBR, (u8 *)(twl_idcode),
+ REG_IDCODE_7_0, 4);
+ if (err) {
+ pr_err(TWL4030: unable to read IDCODE -%d\n, err);
+ goto fail;
+ }
+
+ err = twl_i2c_write_u8(TWL4030_MODULE_INTBR, 0x0, REG_UNLOCK_TEST_REG);
+ if (err) {
+ pr_err(TWL4030 Unable to relock IDCODE registers\n);
+ goto fail;
+ }
+fail:
+ return err;
+}
+
+/**
+ * twl_get_si_type - api to get TWL Si type.
+ *
+ * Api to get the TWL Si type from IDCODE value.
+ */
+int twl_get_si_type(void)
+{
+ return TWL_SIL_TYPE(twl_idcode);
+}
+EXPORT_SYMBOL(twl_get_si_type);
+
+/**
+ * twl_get_si_version - api to get TWL Si version.
+ *
+ * Api to get the TWL Si version from IDCODE value.
+ */
+int twl_get_si_version(void)
+{
+ return TWL_SIL_REV(twl_idcode);
+}
+EXPORT_SYMBOL(twl_get_si_version);
+
static struct device *
add_numbered_child(unsigned chip, const char *name, int num,
void *pdata, unsigned pdata_len,
@@ -1056,6 +1114,9 @@ twl_probe(struct i2c_client *client, const struct
i2c_device_id *id)
/* setup clock framework */
clocks_init(client-dev, pdata-clock);
+ /* read TWL IDCODE Register */
+ twl_read_idcode_register();
+
/* load power event scripts */
if (twl_has_power() pdata-power)
twl4030_power_init(pdata-power);
diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
index f4bd475..d3cc2ac 100644
--- a/include/linux/i2c/twl.h
+++ b/include/linux/i2c/twl.h
@@ -150,7 +150,12 @@
#define MMC_PU (0x1 3)
#define MMC_PD (0x1 2)
-
+#define TWL_SIL_TYPE(rev) ((rev) 0x00FF)
+#define TWL_SIL_REV(rev) ((rev) 24)
+#define TWL_SIL_5030 0x09002F
+#define TWL5030_REV_1_00x00
+#define TWL5030_REV_1_10x10
+#define TWL5030_REV_1_20x30
#define TWL4030_CLASS_ID 0x4030
#define TWL6030_CLASS_ID 0x6030
@@ -180,6 +185,9 @@ int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg);
int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
+int twl_get_si_type(void);
+int twl_get_si_version(void);
+
int twl6030_interrupt_unmask(u8 bit_mask, u8 offset);
int twl6030_interrupt_mask(u8 bit_mask, u8 offset);
@@ -279,7 +287,12 @@ static inline int twl6030_mmc_card_detect(struct device
*dev, int slot)
*(Use TWL_4030_MODULE_INTBR)
*/
+#define REG_IDCODE_7_0 0x00
+#define REG_IDCODE_15_80x01
+#define REG_IDCODE_16_23 0x02
+#define REG_IDCODE_31_24 0x03
#define REG_GPPUPDCTR1 0x0F
+#define REG_UNLOCK_TEST_REG0x12
/*I2C1 and I2C4(SR) SDA/SCL pull-up control bits */
@@ -288,6 +301,8 @@ static inline int twl6030_mmc_card_detect(struct device
*dev, int slot)
#define SR_I2C_SCL_CTRL_PU BIT(4)
#define SR_I2C_SDA_CTRL_PU BIT(6)
+#define TWL_EEPROM_R_UNLOCK0x49
+
/*--*/
/*
--
1.7.1
--
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[PATCH v8 5/7] mfd: TWL4030: changes for TRITON Errata 27 workaround
Workaround for TWL5030 Silicon Errata 27 28:
27 - VDD1, VDD2, may have glitches when their output value is updated.
28 - VDD1 and / or VDD2 DCDC clock may stop working when internal clock
is switched from internal to external.
Errata 27:
If the DCDC regulators is running on their internal oscillator,
negative glitches may occur on VDD1, VDD2 output when voltage is
changed.
The OMAP device may reboot if the VDD1 or VDD2 go below the
core minimum operating voltage.
WORKAROUND
Set up the TWL5030 DC-DC power supplies to use the HFCLKIN instead of
the internal oscillator.
Errata 28:
VDD1/VDD2 clock system may hang during switching the clock source from
internal oscillator to external. VDD1/VDD2 output voltages may collapse
if clock stops.
WORKAROUND
If HFCLK is disabled in OFFMODE, modify the sleep/wakeup sequence and
setuptimes to make sure the switching will happen only when HFCLKIN is
stable.
Also use the TWL5030 watchdog to safeguard the first switching from
internal oscillator to HFCLKIN during the TWL5030 init.
IMPACT
power sequence is changed.
sleep/wakeup time values will be changed.
The workaround changes are called from twl4030_power_init(), since we have to
make some i2c_read calls to check the TRITON version the i2c will not be
initialized in the early stage.
This workaround is required for TWL5030 Silicon version less than ES1.2
The power script setup time changes are recommended by TI HW team.
http://omapedia.org/wiki/TWL4030_power_scripts
Changes taken from TRITON Errata27 workaround patch by Nishanth Menon.
Signed-off-by: Lesly A M lesl...@ti.com
Cc: Nishanth Menon n...@ti.com
Cc: David Derrick dderr...@ti.com
Cc: Samuel Ortiz sa...@linux.intel.com
---
arch/arm/mach-omap2/twl4030.c | 114 +
drivers/mfd/twl4030-power.c | 64 +++
include/linux/i2c/twl.h |1 +
3 files changed, 179 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/twl4030.c b/arch/arm/mach-omap2/twl4030.c
index ff344b3..87de049 100644
--- a/arch/arm/mach-omap2/twl4030.c
+++ b/arch/arm/mach-omap2/twl4030.c
@@ -137,9 +137,123 @@ static struct twl4030_resconfig twl4030_rconfig[] = {
{ 0, 0},
};
+/*
+ * Active to Sleep sequence, which is executed upon P1/P2/P3
+ * transition for sleep.
+ *
+ * The sleep sequence is adjusted to do the switching of VDD1/VDD2/VIO OSC from
+ * HFCLKIN to internal oscillator when the HFCLKIN is stable.
+ */
+static struct twl4030_ins __initdata sleep_on_seq_errata27[] = {
+ /*
+* Singular message to disable HCLKOUT.
+* Wait for ~488.32 uS to do the switching of VDD1/VDD2/VIO OSC from
+* HFCLKIN to internal oscillator before disabling HFCLKIN.
+*/
+ {MSG_SINGULAR(DEV_GRP_NULL, RES_HFCLKOUT, RES_STATE_SLEEP), 20},
+ /* Broadcast message to put res(TYPE2 = 1) to sleep */
+ {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R1,
+ RES_STATE_SLEEP), 2},
+ /* Broadcast message to put res(TYPE2 = 2) to sleep, disable HFCLKIN */
+ {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R2,
+ RES_STATE_SLEEP), 2},
+};
+
+static struct twl4030_script sleep_on_script_errata27 __initdata = {
+ .script = sleep_on_seq_errata27,
+ .size = ARRAY_SIZE(sleep_on_seq_errata27),
+ .flags = TWL4030_SLEEP_SCRIPT,
+};
+
+/*
+ * Sleep to Active sequence, which is executed upon P1/P2/P3
+ * transition for wakeup.
+ *
+ * The wakeup sequence is adjusted to do the VDD1/VDD2 voltage rampup
+ * only after HFCLKIN is stabilized and the HFCLKOUT is enabled.
+ */
+static struct twl4030_ins wakeup_seq_errata27[] __initdata = {
+ /*
+* Broadcast message to put res(TYPE2 = 2) to active.
+* Wait for ~10 mS (rampup time for OSC on the board)
+* after HFCLKIN is enabled
+*/
+ {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R2,
+ RES_STATE_ACTIVE), 55},
+ {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R2,
+ RES_STATE_ACTIVE), 55},
+ {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R2,
+ RES_STATE_ACTIVE), 54},
+ {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R2,
+ RES_STATE_ACTIVE), 1},
+ /* Singular message to enable HCLKOUT after HFCLKIN is stabilized */
+ {MSG_SINGULAR(DEV_GRP_NULL, RES_HFCLKOUT, RES_STATE_ACTIVE), 1},
+ /*
+* Broadcast message to put res(TYPE2 = 1) to active.
Re: [alsa-devel] [PATCH 0/2] twl4030_codec cleanup
On Wed, Mar 02, 2011 at 03:24:04PM +0200, Ilkka Koskinen wrote: Ilkka Koskinen (2): omap: Remove unnecessary twl4030_codec_audio settings from board files mfd: twl4030_codec: Remove unused and duplicate audio_mclk fields Acked-by: Mark Brown broo...@opensource.wolfsonmicro.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 10/18] omap3+: sr: call handler with interrupt disabled
Hello. On 02-03-2011 13:55, Nishanth Menon wrote: Request the handler irq such that there is no nesting for calls. the notifiers are not expected to be nested, further the interrupt events for status change should be handled prior to the next event else there is a risk of loosing events. Signed-off-by: Nishanth Menonn...@ti.com --- arch/arm/mach-omap2/smartreflex.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index 99e4c4f..a4e9f2d 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -278,7 +278,7 @@ static int sr_late_init(struct omap_sr *sr_info) goto error; } ret = request_irq(sr_info-irq, sr_interrupt, - 0, name, (void *)sr_info); + IRQF_DISABLED, name, (void *)sr_info); Isn't this flag a nop now? WBR, Sergei -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 15/18] omap3+: sr: disable spamming interrupts
Hello. On 02-03-2011 13:55, Nishanth Menon wrote: At times with bad SR configurations especially during silicon bringups, we could get continuous spurious interrupts which end up hanging the platform in the form of an ISR call for status bits that are automatically enabled by the h/w without any s/w clearing option. If we detect scenarios where isr was called without the corresponding notification bit being set, instead of hanging up the system, we will disable interrupt after noting the event in the system log to try and keep system sanity and allow developer to debug and fix the condition. Signed-off-by: Nishanth Menonn...@ti.com --- arch/arm/mach-omap2/smartreflex.c | 12 ++-- 1 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index 49a04ea..d62da3d 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -209,8 +209,16 @@ static irqreturn_t sr_interrupt(int irq, void *data) value = irqstat_to_notifier_v2(status); } - if (sr_class-notify) - sr_class-notify(sr_info-voltdm, value); + /* Attempt some resemblence of recovery! */ Resemblance? WBR, Sergei -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: linux-next: manual merge of the usb tree with the omap tree
On Wed, Mar 02, 2011 at 04:57:46PM +1100, Stephen Rothwell wrote: Hi Greg, Today's linux-next merge of the usb tree got a conflict in drivers/usb/musb/musb_core.h between commit 59b479e0985f0b795d68331d6443a7f89c47768d (omap: Start using CONFIG_SOC_OMAP) from the omap tree and commit da68ccec210c45eb99e461ad31b499b4e7043c41 (usb: musb: Remove platform context save/restore API) from the usb tree. The latter removed the code modified by the former, so I did that. Thanks. I'll let Felipe handle all of these omap merge issues, as I thought the reason I was going to take these patches from him was to prevent issues like this from happening :) greg k-h -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/2] twl4030_codec cleanup
Hi Ilkka, On Wed, Mar 02, 2011 at 03:24:04PM +0200, Ilkka Koskinen wrote: This series of patches removes duplicate audio_mclk fields from twl4030_codec driver. The patches have been compiled on sound-2.6/for-2.6.39 branch. I haven't tested them on any target board though. I'm fine with the twl.h changes, but I think it would make sense for Tony to take this patchset. Tony, is that ok with you ? Cheers, Samuel. -- Intel Open Source Technology Centre http://oss.intel.com/ -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] mfd: twl4030_codec: Remove unused and duplicate audio_mclk fields
Hi Ilkka, On Wed, Mar 02, 2011 at 03:24:06PM +0200, Ilkka Koskinen wrote: audio_mclk can be queried from mfd driver. Therefore, it is not needed in twl4030_codec_audio_data or in twl4030_codec_vibra_data anymore. Signed-off-by: Ilkka Koskinen ilkka.koski...@nokia.com Acked-by: Samuel Ortiz sa...@linux.intel.com Cheers, Samuel. -- Intel Open Source Technology Centre http://oss.intel.com/ -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] OMAP4: Enable Turbo and Nitro OPP for OMAP4
Menon, Nishanth n...@ti.com writes:
On Wed, Feb 16, 2011 at 11:48, Shweta Gulati shweta.gul...@ti.com wrote:
All OMAP4 boards support OPP-Turbo (800M) and OPP-Nitro (1G).
s/All OMAP4/Almost all/ - there are a minority of boards that use
OMAP4430-800 device instead of the OMAP4430-1000 device.
Also please use the full term 1GHz instead of 1G
Enable them by default in OPPTable. For 800Mhz devices where
s/For 800Mhz/For the small minority of boards which use OMAP4430-800
(800MHz device),
OPP-Nitro is not supported, OPP-Nitro should be disabled
from board file.
even though the TI documentation terminology is Turbo, Nitro etc.., I
suggest using frequencies to better map things historically.
I agree, IMO the Turbo Nitro names are useless.
Kevin
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
arch/arm/mach-omap2/opp4xxx_data.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c
b/arch/arm/mach-omap2/opp4xxx_data.c
index 705fe9a..48d79e5 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -31,9 +31,9 @@ static struct omap_opp_def __initdata
omap44xx_opp_def_list[] = {
/* MPU OPP2 - OPP100 */
OPP_INITIALIZER(mpu, true, 6, OMAP4430_VDD_MPU_OPP100_UV),
/* MPU OPP3 - OPP-Turbo */
- OPP_INITIALIZER(mpu, false, 8,
OMAP4430_VDD_MPU_OPPTURBO_UV),
+ OPP_INITIALIZER(mpu, true, 8,
OMAP4430_VDD_MPU_OPPTURBO_UV),
/* MPU OPP4 - OPP-SB */
- OPP_INITIALIZER(mpu, false, 100800,
OMAP4430_VDD_MPU_OPPNITRO_UV),
+ OPP_INITIALIZER(mpu, true, 100800,
OMAP4430_VDD_MPU_OPPNITRO_UV),
/* L3 OPP1 - OPP50 */
OPP_INITIALIZER(l3_main_1, true, 1,
OMAP4430_VDD_CORE_OPP50_UV),
/* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
--
1.7.0.4
I am ok with the overall patch - with the minor suggestions above.
Regards,
Nishanth Menon
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[RFC 0/3] omap3+: sr: Minor fix and cleanups
Hi I found a minor issue from smartreflex that it allows to enable multiple times smartreflex class driver from userspace. Then two cleanups. Nishant: I think this will conflict with your class 1.5 set. I think my 1/3 is worth to fix now and for 2-3/3 I don't have any particular priority. I can rebase them on top of yours, you could take them with your set etc. -- Jarkko -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC 1/3] omap3+: sr: Prevent multiple smartreflex class driver enable calls
Currently it is possible to enable multiple times the smartreflex class
driver from userspace via ../smartreflex/autocomp debugfs entry. Fix this
by checking the autocomp_active state in sr_start_vddautocomp.
Signed-off-by: Jarkko Nikula jhnik...@gmail.com
---
Not known to cause any problems at the moment with class3 driver.
---
arch/arm/mach-omap2/smartreflex.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
index 95ac336..d94894a 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -213,6 +213,9 @@ static void sr_set_regfields(struct omap_sr *sr)
static void sr_start_vddautocomp(struct omap_sr *sr)
{
+ if (sr-autocomp_active)
+ return;
+
if (!sr_class || !(sr_class-enable) || !(sr_class-configure)) {
dev_warn(sr-pdev-dev,
%s: smartreflex class driver not registered\n,
--
1.7.2.3
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[RFC 2/3] omap3+: sr: Sync sr_stop_vddautocomp implementation with sr_start_vddautocomp
This is mostly preparation for another patch that takes these functions into
use from omap_sr_enable and omap_sr_disable.
Signed-off-by: Jarkko Nikula jhnik...@gmail.com
---
arch/arm/mach-omap2/smartreflex.c |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
index d94894a..11741d8 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -229,6 +229,9 @@ static void sr_start_vddautocomp(struct omap_sr *sr)
static void sr_stop_vddautocomp(struct omap_sr *sr)
{
+ if (!sr-autocomp_active)
+ return;
+
if (!sr_class || !(sr_class-disable)) {
dev_warn(sr-pdev-dev,
%s: smartreflex class driver not registered\n,
@@ -236,10 +239,8 @@ static void sr_stop_vddautocomp(struct omap_sr *sr)
return;
}
- if (sr-autocomp_active) {
- sr_class-disable(sr-voltdm, 1);
+ if (!sr_class-disable(sr-voltdm, 1))
sr-autocomp_active = false;
- }
}
/*
--
1.7.2.3
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[RFC 3/3] omap3+: sr: Reuse sr_[start|stop]_vddautocomp functions
sr_start_vddautocomp and sr_stop_autocomp functions can be reused from
omap_sr_enable, omap_sr_disable and omap_sr_disable_reset_volt and by
adding one additional argument sr_stop_autocomp.
Signed-off-by: Jarkko Nikula jhnik...@gmail.com
---
arch/arm/mach-omap2/smartreflex.c | 41 ++--
1 files changed, 7 insertions(+), 34 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
index 11741d8..7e6002f 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -227,7 +227,7 @@ static void sr_start_vddautocomp(struct omap_sr *sr)
sr-autocomp_active = true;
}
-static void sr_stop_vddautocomp(struct omap_sr *sr)
+static void sr_stop_vddautocomp(struct omap_sr *sr, int is_volt_reset)
{
if (!sr-autocomp_active)
return;
@@ -239,7 +239,7 @@ static void sr_stop_vddautocomp(struct omap_sr *sr)
return;
}
- if (!sr_class-disable(sr-voltdm, 1))
+ if (!sr_class-disable(sr-voltdm, is_volt_reset))
sr-autocomp_active = false;
}
@@ -681,16 +681,7 @@ void omap_sr_enable(struct voltagedomain *voltdm)
return;
}
- if (!sr-autocomp_active)
- return;
-
- if (!sr_class || !(sr_class-enable) || !(sr_class-configure)) {
- dev_warn(sr-pdev-dev, %s: smartreflex class driver not
- registered\n, __func__);
- return;
- }
-
- sr_class-enable(voltdm);
+ sr_start_vddautocomp(sr);
}
/**
@@ -714,16 +705,7 @@ void omap_sr_disable(struct voltagedomain *voltdm)
return;
}
- if (!sr-autocomp_active)
- return;
-
- if (!sr_class || !(sr_class-disable)) {
- dev_warn(sr-pdev-dev, %s: smartreflex class driver not
- registered\n, __func__);
- return;
- }
-
- sr_class-disable(voltdm, 0);
+ sr_stop_vddautocomp(sr, 0);
}
/**
@@ -747,16 +729,7 @@ void omap_sr_disable_reset_volt(struct voltagedomain
*voltdm)
return;
}
- if (!sr-autocomp_active)
- return;
-
- if (!sr_class || !(sr_class-disable)) {
- dev_warn(sr-pdev-dev, %s: smartreflex class driver not
- registered\n, __func__);
- return;
- }
-
- sr_class-disable(voltdm, 1);
+ sr_stop_vddautocomp(sr, 1);
}
/**
@@ -809,7 +782,7 @@ static int omap_sr_autocomp_store(void *data, u64 val)
}
if (!val)
- sr_stop_vddautocomp(sr_info);
+ sr_stop_vddautocomp(sr_info, 1);
else
sr_start_vddautocomp(sr_info);
@@ -976,7 +949,7 @@ static int __devexit omap_sr_remove(struct platform_device
*pdev)
}
if (sr_info-autocomp_active)
- sr_stop_vddautocomp(sr_info);
+ sr_stop_vddautocomp(sr_info, 1);
list_del(sr_info-node);
iounmap(sr_info-base);
--
1.7.2.3
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[PATCH] cbus-retu-wdt: Make the watchdog driver fully preemptible
Make the WDT driver fully preemptible.
This is required in order to apply a locking fix to retu_write_reg.
It also improves power management by using round_relative_jiffies().
Signed-off-by: Michael Buesch m...@bu3sch.de
---
Tony, thanks for the report on this issue.
You may apply the locking fix on to of this.
Index: linux-2.6.38-rc6/drivers/cbus/retu-wdt.c
===
--- linux-2.6.38-rc6.orig/drivers/cbus/retu-wdt.c 2011-03-02
16:08:59.022211654 +0100
+++ linux-2.6.38-rc6/drivers/cbus/retu-wdt.c2011-03-02 16:29:43.215284501
+0100
@@ -58,13 +58,11 @@ struct retu_wdt_dev {
struct device *dev;
int users;
struct miscdevice retu_wdt_miscdev;
- struct timer_list ping_timer;
+ struct delayed_work ping_work;
};
static struct retu_wdt_dev *retu_wdt;
-static void retu_wdt_set_ping_timer(unsigned long enable);
-
static int _retu_modify_counter(unsigned int new)
{
if (retu_wdt)
@@ -86,6 +84,31 @@ static int retu_modify_counter(unsigned
return 0;
}
+/*
+ * Since retu watchdog cannot be disabled in hardware, we must kick it
+ * with a timer until userspace watchdog software takes over. Do this
+ * unless /dev/watchdog is open or CONFIG_WATCHDOG_NOWAYOUT is set.
+ */
+static void retu_wdt_ping_enable(struct retu_wdt_dev *wdev)
+{
+ _retu_modify_counter(RETU_WDT_MAX_TIMER);
+ schedule_delayed_work(wdev-ping_work,
+ round_jiffies_relative(RETU_WDT_DEFAULT_TIMER *
HZ));
+}
+
+static void retu_wdt_ping_disable(struct retu_wdt_dev *wdev)
+{
+ _retu_modify_counter(RETU_WDT_MAX_TIMER);
+ cancel_delayed_work_sync(wdev-ping_work);
+}
+
+static void retu_wdt_ping_work(struct work_struct *work)
+{
+ struct retu_wdt_dev *wdev = container_of(to_delayed_work(work),
+ struct retu_wdt_dev, ping_work);
+ retu_wdt_ping_enable(wdev);
+}
+
static ssize_t retu_wdt_period_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
@@ -105,7 +128,7 @@ static ssize_t retu_wdt_period_store(str
int ret;
#ifdef CONFIG_WATCHDOG_NOWAYOUT
- retu_wdt_set_ping_timer(0);
+ retu_wdt_ping_disable(retu_wdt);
#endif
if (sscanf(buf, %u, new_period) != 1) {
@@ -136,30 +159,13 @@ static DEVICE_ATTR(period, S_IRUGO | S_I
retu_wdt_period_store);
static DEVICE_ATTR(counter, S_IRUGO, retu_wdt_counter_show, NULL);
-/**/
-
-/*
- * Since retu watchdog cannot be disabled in hardware, we must kick it
- * with a timer until userspace watchdog software takes over. Do this
- * unless /dev/watchdog is open or CONFIG_WATCHDOG_NOWAYOUT is set.
- */
-static void retu_wdt_set_ping_timer(unsigned long enable)
-{
- _retu_modify_counter(RETU_WDT_MAX_TIMER);
- if (enable)
- mod_timer(retu_wdt-ping_timer,
- jiffies + RETU_WDT_DEFAULT_TIMER * HZ);
- else
- del_timer_sync(retu_wdt-ping_timer);
-}
-
static int retu_wdt_open(struct inode *inode, struct file *file)
{
if (test_and_set_bit(1, (unsigned long *)(retu_wdt-users)))
return -EBUSY;
file-private_data = (void *)retu_wdt;
- retu_wdt_set_ping_timer(0);
+ retu_wdt_ping_disable(retu_wdt);
return nonseekable_open(inode, file);
}
@@ -169,7 +175,7 @@ static int retu_wdt_release(struct inode
struct retu_wdt_dev *wdev = file-private_data;
#ifndef CONFIG_WATCHDOG_NOWAYOUT
- retu_wdt_set_ping_timer(1);
+ retu_wdt_ping_enable(retu_wdt);
#endif
wdev-users = 0;
@@ -232,7 +238,7 @@ static int __devinit retu_wdt_ping(void)
#ifdef CONFIG_WATCHDOG_NOWAYOUT
retu_modify_counter(RETU_WDT_MAX_TIMER);
#else
- retu_wdt_set_ping_timer(1);
+ retu_wdt_ping_enable(retu_wdt);
#endif
return 0;
@@ -283,7 +289,7 @@ static int __init retu_wdt_probe(struct
if (ret)
goto free3;
- setup_timer(wdev-ping_timer, retu_wdt_set_ping_timer, 1);
+ INIT_DELAYED_WORK(wdev-ping_work, retu_wdt_ping_work);
/* passed as module parameter? */
ret = retu_modify_counter(counter_param);
@@ -326,6 +332,7 @@ static int __devexit retu_wdt_remove(str
misc_deregister(wdev-retu_wdt_miscdev);
device_remove_file(pdev-dev, dev_attr_period);
device_remove_file(pdev-dev, dev_attr_counter);
+ cancel_delayed_work_sync(wdev-ping_work);
kfree(wdev);
return 0;
--
Greetings, Michael.
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[PATCH] cbus-retu-wdt: Fix bitfield access
An unsigned int pointer must not be casted to an unsigned
long pointer before use. Convert the bitfield to unsigned long
to fix this.
Also use clear_bit() in the release path.
Signed-off-by: Michael Buesch m...@bu3sch.de
---
Index: linux-2.6.38-rc6/drivers/cbus/retu-wdt.c
===
--- linux-2.6.38-rc6.orig/drivers/cbus/retu-wdt.c 2011-03-02
16:46:24.574676092 +0100
+++ linux-2.6.38-rc6/drivers/cbus/retu-wdt.c2011-03-02 16:48:17.469807413
+0100
@@ -56,7 +56,7 @@ static int counter_param = RETU_WDT_MAX_
struct retu_wdt_dev {
struct device *dev;
- int users;
+ unsigned long users;
struct miscdevice retu_wdt_miscdev;
struct delayed_work ping_work;
};
@@ -161,7 +161,7 @@ static DEVICE_ATTR(counter, S_IRUGO, ret
static int retu_wdt_open(struct inode *inode, struct file *file)
{
- if (test_and_set_bit(1, (unsigned long *)(retu_wdt-users)))
+ if (test_and_set_bit(0, retu_wdt-users))
return -EBUSY;
file-private_data = (void *)retu_wdt;
@@ -177,7 +177,7 @@ static int retu_wdt_release(struct inode
#ifndef CONFIG_WATCHDOG_NOWAYOUT
retu_wdt_ping_enable(retu_wdt);
#endif
- wdev-users = 0;
+ clear_bit(0, retu_wdt-users);
return 0;
}
@@ -264,7 +264,6 @@ static int __init retu_wdt_probe(struct
return -ENOMEM;
wdev-dev = pdev-dev;
- wdev-users = 0;
ret = device_create_file(pdev-dev, dev_attr_period);
if (ret) {
--
Greetings, Michael.
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[PATCH] cbus-retu-wdt: Remove unused nonstandard interfaces
This removes nonstandard interfaces from the WDT driver.
/dev/watchdog should be used to access the watchdog, only.
It removes the sysfs interface.
It also removes the counter_param module parameter, which
currently is broken anyway (doesn't work, because the value
is overridden right away).
Signed-off-by: Michael Buesch m...@bu3sch.de
---
Index: linux-2.6.38-rc6/drivers/cbus/retu-wdt.c
===
--- linux-2.6.38-rc6.orig/drivers/cbus/retu-wdt.c 2011-03-02
16:49:51.231863891 +0100
+++ linux-2.6.38-rc6/drivers/cbus/retu-wdt.c2011-03-02 16:53:47.189454637
+0100
@@ -52,7 +52,6 @@ static DEFINE_MUTEX(retu_wdt_mutex);
/* Current period of watchdog */
static unsigned int period_val = RETU_WDT_DEFAULT_TIMER;
-static int counter_param = RETU_WDT_MAX_TIMER;
struct retu_wdt_dev {
struct device *dev;
@@ -109,56 +108,6 @@ static void retu_wdt_ping_work(struct wo
retu_wdt_ping_enable(wdev);
}
-static ssize_t retu_wdt_period_show(struct device *dev,
- struct device_attribute *attr, char *buf)
-{
- /* Show current max counter */
- return sprintf(buf, %u\n, (u16)period_val);
-}
-
-/*
- * Note: This inteface is non-standard and likely to disappear!
- * Use /dev/watchdog instead, that's the standard.
- */
-static ssize_t retu_wdt_period_store(struct device *dev,
- struct device_attribute *attr,
- const char *buf, size_t count)
-{
- unsigned int new_period;
- int ret;
-
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
- retu_wdt_ping_disable(retu_wdt);
-#endif
-
- if (sscanf(buf, %u, new_period) != 1) {
- printk(KERN_ALERT retu_wdt_period_store: Invalid input\n);
- return -EINVAL;
- }
-
- ret = retu_modify_counter(new_period);
- if (ret 0)
- return ret;
-
- return strnlen(buf, count);
-}
-
-static ssize_t retu_wdt_counter_show(struct device *dev,
- struct device_attribute *attr, char *buf)
-{
- u16 counter;
-
- /* Show current value in watchdog counter */
- counter = retu_read_reg(dev, RETU_REG_WATCHDOG);
-
- /* Only the 5 LSB are important */
- return snprintf(buf, PAGE_SIZE, %u\n, (counter 0x3F));
-}
-
-static DEVICE_ATTR(period, S_IRUGO | S_IWUSR, retu_wdt_period_show, \
- retu_wdt_period_store);
-static DEVICE_ATTR(counter, S_IRUGO, retu_wdt_counter_show, NULL);
-
static int retu_wdt_open(struct inode *inode, struct file *file)
{
if (test_and_set_bit(0, retu_wdt-users))
@@ -175,9 +124,9 @@ static int retu_wdt_release(struct inode
struct retu_wdt_dev *wdev = file-private_data;
#ifndef CONFIG_WATCHDOG_NOWAYOUT
- retu_wdt_ping_enable(retu_wdt);
+ retu_wdt_ping_enable(wdev);
#endif
- clear_bit(0, retu_wdt-users);
+ clear_bit(0, wdev-users);
return 0;
}
@@ -232,18 +181,6 @@ static long retu_wdt_ioctl(struct file *
return 0;
}
-/* Start kicking retu watchdog until user space starts doing the kicking */
-static int __devinit retu_wdt_ping(void)
-{
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
- retu_modify_counter(RETU_WDT_MAX_TIMER);
-#else
- retu_wdt_ping_enable(retu_wdt);
-#endif
-
- return 0;
-}
-
static const struct file_operations retu_wdt_fops = {
.owner = THIS_MODULE,
.write = retu_wdt_write,
@@ -252,8 +189,6 @@ static const struct file_operations retu
.release= retu_wdt_release,
};
-/**/
-
static int __init retu_wdt_probe(struct platform_device *pdev)
{
struct retu_wdt_dev *wdev;
@@ -265,18 +200,6 @@ static int __init retu_wdt_probe(struct
wdev-dev = pdev-dev;
- ret = device_create_file(pdev-dev, dev_attr_period);
- if (ret) {
- dev_err(pdev-dev, Error creating sysfs period\n);
- goto free1;
- }
-
- ret = device_create_file(pdev-dev, dev_attr_counter);
- if (ret) {
- dev_err(pdev-dev, Error creating sysfs counter\n);
- goto free2;
- }
-
platform_set_drvdata(pdev, wdev);
retu_wdt = wdev;
wdev-retu_wdt_miscdev.parent = pdev-dev;
@@ -286,38 +209,21 @@ static int __init retu_wdt_probe(struct
ret = misc_register((wdev-retu_wdt_miscdev));
if (ret)
- goto free3;
+ goto err_free_wdev;
INIT_DELAYED_WORK(wdev-ping_work, retu_wdt_ping_work);
- /* passed as module parameter? */
- ret = retu_modify_counter(counter_param);
- if (ret == -EINVAL) {
- ret = retu_modify_counter(RETU_WDT_DEFAULT_TIMER);
- dev_dbg(pdev-dev, Initializing to default value\n);
- }
-
- /* Kick the watchdog for kernel booting to finish */
+
Re: [PATCH] omap:iommu-added cache flushing operation for L2 cache
Hi Santosh,
On Wed, Mar 2, 2011 at 6:48 AM, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
Hello,
-Original Message-
From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap-
ow...@vger.kernel.org] On Behalf Of Fernando Guzman Lugo
Sent: Wednesday, March 02, 2011 1:17 AM
To: hiroshi.d...@nokia.com
Cc: t...@atomide.com; li...@arm.linux.org.uk; linux-
o...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
ker...@vger.kernel.org; Ramesh Gupta; Hari Kanigeri
Subject: [PATCH] omap:iommu-added cache flushing operation for L2
cache
From: Ramesh Gupta grgu...@ti.com
Signed-off-by: Ramesh Gupta grgu...@ti.com
Signed-off-by: Hari Kanigeri h-kanige...@ti.com
---
arch/arm/plat-omap/iommu.c | 22 --
1 files changed, 8 insertions(+), 14 deletions(-)
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index e3eb038..aeb2c33 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -471,22 +471,15 @@ EXPORT_SYMBOL_GPL(foreach_iommu_device);
*/
static void flush_iopgd_range(u32 *first, u32 *last)
{
- /* FIXME: L2 cache should be taken care of if it exists */
- do {
- asm(mcr p15, 0, %0, c7, c10, 1 @ flush_pgd
- : : r (first));
- first += L1_CACHE_BYTES / sizeof(*first);
- } while (first = last);
+ dmac_flush_range(first, last);
There is note just above this API.
Thank you for your inputs. I agree, I will send an updated patch with
proper apis.
regards
Ramesh Gupta G
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Re: [PATCH] omap:iommu-added cache flushing operation for L2 cache
David, On Wed, Mar 2, 2011 at 5:58 AM, David Cohen daco...@gmail.com wrote: Hi, On Tue, Mar 1, 2011 at 9:46 PM, Fernando Guzman Lugo fernando.l...@ti.com wrote: From: Ramesh Gupta grgu...@ti.com No patch body description at all? Can we get at least something here? My apologies, I will be sending an updated patch with description. regards Ramesh Gupta G -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL] OMAP PM fixes for 2.6.38-rc
Tony, Kevin Hilman khil...@ti.com writes: Here's a final batch of PM fixes for the 2.6.38-rc cycle. I just noticed that a couple of these were already queued in your last pull request to Linus. Here's an updated pull request based on .38-rc7. Kevin The following changes since commit dd9c1549edef02290edced639f67b54a25abbe0e: Linux 2.6.38-rc7 (2011-03-01 13:55:12 -0800) are available in the git repository at: ssh://master.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git for_2.6.38/pm-fixes Aaro Koskinen (1): arm: mach-omap2: smartreflex: fix another memory leak Shweta Gulati (1): OMAP2+: PM: SmartReflex: fix memory leaks in Smartreflex driver arch/arm/mach-omap2/smartreflex.c | 33 +++-- 1 files changed, 15 insertions(+), 18 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC 1/3] omap3+: sr: Prevent multiple smartreflex class driver enable calls
Jarkko Nikula wrote, on 03/02/2011 09:27 PM:
Currently it is possible to enable multiple times the smartreflex class
driver from userspace via ../smartreflex/autocomp debugfs entry. Fix this
by checking the autocomp_active state in sr_start_vddautocomp.
Signed-off-by: Jarkko Nikulajhnik...@gmail.com
---
Not known to cause any problems at the moment with class3 driver.
---
arch/arm/mach-omap2/smartreflex.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
index 95ac336..d94894a 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -213,6 +213,9 @@ static void sr_set_regfields(struct omap_sr *sr)
static void sr_start_vddautocomp(struct omap_sr *sr)
{
+ if (sr-autocomp_active)
+ return;
+
if (!sr_class || !(sr_class-enable) || !(sr_class-configure)) {
dev_warn(sr-pdev-dev,
%s: smartreflex class driver not registered\n,
is'nt:
http://marc.info/?l=linux-omapm=129906344711663w=2
better since the issue with userspace access - debugfs?
--
Regards,
Nishanth Menon
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Re: [PATCH v2 15/18] omap3+: sr: disable spamming interrupts
Sergei Shtylyov wrote, on 03/02/2011 07:15 PM: [...] diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index 49a04ea..d62da3d 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -209,8 +209,16 @@ static irqreturn_t sr_interrupt(int irq, void *data) value = irqstat_to_notifier_v2(status); } - if (sr_class-notify) - sr_class-notify(sr_info-voltdm, value); + /* Attempt some resemblence of recovery! */ Resemblance? arrgh.. thanks for catching :) -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 1/3] OMAP3 PM: Deny clock gating only for safe state
Kevin,
-Original Message-
From: Kevin Hilman [mailto:khil...@ti.com]
Sent: Wednesday, March 02, 2011 2:32 AM
To: Vishwanath BS
Cc: linux-omap@vger.kernel.org; patc...@linaro.org
Subject: Re: [PATCH 1/3] OMAP3 PM: Deny clock gating only for safe
state
Vishwanath BS vishwanath...@ti.com writes:
Currently clock gating for MPU and core are denied whenever C1 state
is
selected.
Yes, that is the definition of C1.
It should be denied only when safe state is selected.
Why?
Clock gating in C1 will reduce overall power consumption and it should not
impact any functionality as well.
This changes the definition and behavior of C1 depending on how it is
entered. Not a good idea IMO.
I thought of adding a new C state, keeping C1 definition unchanged. Then
we will not get the real power benefit since in case of C1, clock gating
will be prevented. Let me know if you have some suggestion.
Vishwa
Kevin
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/cpuidle34xx.c | 20 ++--
1 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-
omap2/cpuidle34xx.c
index f8e35b3..1e4ec7f 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -139,19 +139,9 @@ static int omap3_enter_idle(struct
cpuidle_device *dev,
if (omap_irq_pending() || need_resched())
goto return_sleep_time;
- if (cx-type == OMAP3_STATE_C1) {
- pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
- pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
- }
-
/* Execute ARM wfi */
omap_sram_idle();
- if (cx-type == OMAP3_STATE_C1) {
- pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
- pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
- }
-
return_sleep_time:
getnstimeofday(ts_postidle);
ts_idle = timespec_sub(ts_postidle, ts_preidle);
@@ -315,8 +305,18 @@ static int omap3_enter_idle_bm(struct
cpuidle_device *dev,
select_state:
dev-last_state = new_state;
+
+ if (new_state == dev-safe_state) {
+ pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
+ pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
+ }
ret = omap3_enter_idle(dev, new_state);
+ if (new_state == dev-safe_state) {
+ pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
+ pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
+ }
+
/* Restore original PER state if it was modified */
if (per_next_state != per_saved_state)
pwrdm_set_next_pwrst(per_pd, per_saved_state);
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Re: [PATCH v2 10/18] omap3+: sr: call handler with interrupt disabled
Sergei Shtylyov wrote, on 03/02/2011 07:08 PM: Hello. On 02-03-2011 13:55, Nishanth Menon wrote: Request the handler irq such that there is no nesting for calls. the notifiers are not expected to be nested, further the interrupt events for status change should be handled prior to the next event else there is a risk of loosing events. Signed-off-by: Nishanth Menonn...@ti.com --- arch/arm/mach-omap2/smartreflex.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index 99e4c4f..a4e9f2d 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -278,7 +278,7 @@ static int sr_late_init(struct omap_sr *sr_info) goto error; } ret = request_irq(sr_info-irq, sr_interrupt, - 0, name, (void *)sr_info); + IRQF_DISABLED, name, (void *)sr_info); Isn't this flag a nop now? thanks. hmm... Documentation/feature-removal-schedule.txt says so as well.. I guess I was just being paranoid (again?). -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 3/3] OMAP36xx PM: Updated C state latencies for OMAP3630
-Original Message-
From: Kevin Hilman [mailto:khil...@ti.com]
Sent: Wednesday, March 02, 2011 3:15 AM
To: Vishwanath BS
Cc: linux-omap@vger.kernel.org; patc...@linaro.org
Subject: Re: [PATCH 3/3] OMAP36xx PM: Updated C state latencies for
OMAP3630
Vishwanath BS vishwanath...@ti.com writes:
This patch has changes to update the C state latencies for OMAP3630
and
disables the useless C-States, keeping only the optimized ones with
their
corresponding measured latencies.
I think useless vs. optimized here are not the right words, and
doesn't summarize the problem being solved.
If I understood Nicole and Vincent's summary it was that there is no
significant power savings between some of the states, so they are not
necessary.
Yes, also some of the C states were consuming more power than deeper C
state.
Also, I believe Nicole Vincent's research applies to both 34xx and
36xx.
I need to check. AFAIK, the experiments were done on OMAP3630 boards.
Only 4 C-states are kept instead of 7
C-States:
* C1 . MPU WFI clock gated + Core autogating
* C3 . MPU CSWR + Core inactive
* C5 . MPU CSWR + Core CSWR
* C7 . MPU OFF + Core OFF
Thanks to Nicole Chaloubn-chalh...@ti.com and Vincent Bour v-
b...@ti.com
for their investigation.
Tested on ZOOM3 board using latest pm branch.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/board-3630sdp.c | 19
+++
arch/arm/mach-omap2/board-zoom.c| 19
+++
Why are these added as board-specific changes?
If these are to be the default 3630 CPUidle states, add a default 36xx
cpuidle_params_table along side the 34xx one and have CPUidle pick the
right one at runtime.
Yes, I can do that.
Vishwa
Kevin
2 files changed, 38 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-
omap2/board-3630sdp.c
index 6264564..8d05fc9
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -25,6 +25,24 @@
#include board-flash.h
#include mux.h
#include sdram-hynix-h8mbx00u0mer-0em.h
+#include pm.h
+
+static struct cpuidle_params omap36xx_cpuidle_params_table[] = {
+ /* C1 */
+ {1, 74, 78, 152},
+ /* C2 */
+ {0, 165, 90, 255},
+ /* C3 */
+ {1, 163, 180, 345},
+ /* C4 */
+ {0, 2852, 605, 3457},
+ /* C5 */
+ {1, 800, 366, 2120},
+ /* C6 */
+ {0, 4080, 801, 4881},
+ /* C7 */
+ {1, 4300, 8794, 159000},
+};
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
@@ -212,6 +230,7 @@ static void __init omap_sdp_init(void)
board_flash_init(sdp_flash_partitions, chip_sel_sdp);
enable_board_wakeup_source();
usb_ehci_init(ehci_pdata);
+ omap3_pm_init_cpuidle(omap36xx_cpuidle_params_table);
}
MACHINE_START(OMAP_3630SDP, OMAP 3630SDP board)
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-
omap2/board-zoom.c
index e26754c..6bd364a
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -30,6 +30,24 @@
#include mux.h
#include sdram-micron-mt46h32m32lf-6.h
#include sdram-hynix-h8mbx00u0mer-0em.h
+#include pm.h
+
+static struct cpuidle_params omap36xx_cpuidle_params_table[] = {
+ /* C1 */
+ {1, 74, 78, 152},
+ /* C2 */
+ {0, 165, 90, 255},
+ /* C3 */
+ {1, 163, 180, 345},
+ /* C4 */
+ {0, 2852, 605, 3457},
+ /* C5 */
+ {1, 800, 366, 2120},
+ /* C6 */
+ {0, 4080, 801, 4881},
+ /* C7 */
+ {1, 4300, 8794, 159000},
+};
#define ZOOM3_EHCI_RESET_GPIO 64
@@ -126,6 +144,7 @@ static void __init omap_zoom_init(void)
usb_ehci_init(ehci_pdata);
}
+ omap3_pm_init_cpuidle(omap36xx_cpuidle_params_table);
board_nand_init(zoom_nand_partitions,
ARRAY_SIZE(zoom_nand_partitions),
ZOOM_NAND_CS);
zoom_debugboard_init();
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Re: [PATCH 0/2] twl4030_codec cleanup
Hi Samuel, * Samuel Ortiz sa...@linux.intel.com [110302 06:32]: Hi Ilkka, On Wed, Mar 02, 2011 at 03:24:04PM +0200, Ilkka Koskinen wrote: This series of patches removes duplicate audio_mclk fields from twl4030_codec driver. The patches have been compiled on sound-2.6/for-2.6.39 branch. I haven't tested them on any target board though. I'm fine with the twl.h changes, but I think it would make sense for Tony to take this patchset. Tony, is that ok with you ? Sure if you prefer that. Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH resend] omap: Fix linker error in drivers/video/omap/lcd_2430sdp.c
* Tomi Valkeinen tomi.valkei...@ti.com [110228 22:27]: On Mon, 2011-02-28 at 19:39 -0600, Tony Lindgren wrote: * Tomi Valkeinen tomi.valkei...@ti.com [110228 07:07]: Well, it's a bit ugly, but I'm fine with it. It's for the old omapfb, which hopefully nobody uses anymore (right =), and there's no simple way to make it modular and neat. How about let's make mach-omap2 boards all use the new code? That way the old code can be omap1 only. That has been my long term plan, but I've never had time to start working on it. Some (many?) of the old panel drivers are trivial to port, needs just copying the panel timings. OK, that will probably make things a lot easier in the long run. Some are much more complex, and porting them without having the hardware may be a bit of a guesswork. But perhaps we can find testers for those after the code has been ported. Sure, once we get one working others should be easy.. Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 10/18] omap3+: sr: call handler with interrupt disabled
I wrote: Request the handler irq such that there is no nesting for calls. the notifiers are not expected to be nested, further the interrupt events for status change should be handled prior to the next event else there is a risk of loosing events. Signed-off-by: Nishanth Menonn...@ti.com --- arch/arm/mach-omap2/smartreflex.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index 99e4c4f..a4e9f2d 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -278,7 +278,7 @@ static int sr_late_init(struct omap_sr *sr_info) goto error; } ret = request_irq(sr_info-irq, sr_interrupt, -0, name, (void *)sr_info); +IRQF_DISABLED, name, (void *)sr_info); Isn't this flag a nop now? Indeed, it is, according to the comment in linux/interrupt.h. So what does this patch really achieve? WBR, Sergei -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 10/18] omap3+: sr: call handler with interrupt disabled
Sergei Shtylyov wrote, on 03/02/2011 11:09 PM: I wrote: Request the handler irq such that there is no nesting for calls. the notifiers are not expected to be nested, further the interrupt events for status change should be handled prior to the next event else there is a risk of loosing events. Signed-off-by: Nishanth Menonn...@ti.com --- arch/arm/mach-omap2/smartreflex.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index 99e4c4f..a4e9f2d 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -278,7 +278,7 @@ static int sr_late_init(struct omap_sr *sr_info) goto error; } ret = request_irq(sr_info-irq, sr_interrupt, - 0, name, (void *)sr_info); + IRQF_DISABLED, name, (void *)sr_info); Isn't this flag a nop now? Indeed, it is, according to the comment in linux/interrupt.h. So what does this patch really achieve? Carry over since I had implemented this driver originally on an ancient kernel and other than the showing off the obvious fact that I am not reading lwn.net enough, I dont think it achieved anything much :( The original intent was as following: since bootloaders may have used the same h/w logic which could generate pending interrupt status, I wanted to explicitly flag that requesting the irq should also ensure the IRQ is in disabled status before I get a chance to clean things up. -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] omap2plus: Remove auto selection on PMICs
* Premi, Sanjeev pr...@ti.com [110226 00:27]: -Original Message- From: Tony Lindgren [mailto:t...@atomide.com] Sent: Friday, February 25, 2011 11:47 PM To: Premi, Sanjeev Cc: linux-omap@vger.kernel.org Subject: Re: [PATCH] omap2plus: Remove auto selection on PMICs * Sanjeev Premi pr...@ti.com [110223 04:11]: The current implementation almost assumes that only TWL4030/TWL5030/TWl6030 are (or can be) used with the OMAP processors. This is, however, not true. If selecting these on platforms that don't have twl causes problems the problem should be fixed. You can disable CONFIG_ARCH_OMAP2PLUS_TYPICAL, and then these don't get selected. [sp] But this means MUTLI_OMAP breaks. And same uImage won't run on the AM3517 EVM. If I remember, the problem is caused due to twl specific functions called even if it isn't present. And there is implicit assumption on TWL in most of code. Then let's fix that problem instead. The TWL functions should not get called (or at least they should not do anything) unless the TWL chip is there. [sp] I will be away from work for next week; may not be able to try this; but don't you think dependency on ARM is too generic? And this should still be fixed.. - depends on TWL4030_CORE ARM + depends on TWL4030_CORE (ARCH_OMAP3 || ARCH_OMAP4) Well in theory all the drivers should just build on whatever platform. I don't know if changing that really improves things, we should improve the driver instead. Note for example how the tps65010.c driver also builds on x86. That allows people doing Linux generic changes to build test those changes: $git log --pretty=oneline drivers/mfd/tps65010.c 77b22897da093e80c40f03e8d83bf23e756b9fba mfd: Include linux/gpio.h instead of afdb32f2e463a195c104555ac9a8cdd39a2b6561 mfd: update workqueue usages fbae3fb1546e199ab0cd185348f8124411a1ca9d i2c: Remove all i2c_set_clientdata(clie f322d5f009743bfd92b47258ee997c889263 mfd: Fix dangling pointersRegards, ... So instead of breakage for the tps65010 driver we instead got the above changes compile tested as an extra bonus. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] omap-mmc: Fix possible NULL pointer deref
* Michael Buesch m...@bu3sch.de [110227 03:36]: Either OMAP_MMC_STAT_CARD_ERR or OMAP_MMC_STAT_END_OF_CMD might fire if there is no host-cmd pointer. Check for a valid host-cmd pointer before calling mmc_omap_cmd_done(). Signed-off-by: Michael Buesch m...@bu3sch.de Can you please resend this to the MMC list? Acked-by: Tony Lindgren t...@atomide.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] omap-mmc: Fix possible NULL pointer deref
Either OMAP_MMC_STAT_CARD_ERR or OMAP_MMC_STAT_END_OF_CMD might
fire if there is no host-cmd pointer.
Check for a valid host-cmd pointer before calling mmc_omap_cmd_done().
Signed-off-by: Michael Buesch m...@bu3sch.de
Acked-by: Tony Lindgren t...@atomide.com
---
Fixes
[3.814483] Unable to handle kernel NULL pointer dereference at virtual
address 0018
...
[3.841247] CPU: 0Not tainted (2.6.38-rc6 #5)
[3.846374] PC is at mmc_omap_cmd_done+0x1c/0x154
[3.851379] LR is at mmc_omap_cmd_done+0x1c/0x154
...
[4.140014] [c0234af0] (mmc_omap_cmd_done+0x1c/0x154) from [c0234ea4]
(mmc_omap_irq+0x27c/0x32c)
[4.149749] [c0234ea4] (mmc_omap_irq+0x27c/0x32c) from [c008645c]
(handle_IRQ_event+0x24/0xe4)
[4.159332] [c008645c] (handle_IRQ_event+0x24/0xe4) from [c0087dac]
(handle_level_irq+0xbc/0x13c)
[4.169158] [c0087dac] (handle_level_irq+0xbc/0x13c) from [c002b070]
(asm_do_IRQ+0x70/0x94)
[4.178466] [c002b070] (asm_do_IRQ+0x70/0x94) from [c003016c]
(__irq_svc+0x4c/0xb8)
Index: linux-omap-2.6/drivers/mmc/host/omap.c
===
--- linux-omap-2.6.orig/drivers/mmc/host/omap.c 2011-02-27 12:32:03.051061690
+0100
+++ linux-omap-2.6/drivers/mmc/host/omap.c 2011-02-27 12:32:27.622530875
+0100
@@ -832,7 +832,7 @@
return IRQ_HANDLED;
}
- if (end_command)
+ if (end_command host-cmd)
mmc_omap_cmd_done(host, host-cmd);
if (host-data != NULL) {
if (transfer_error)
--
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Re: [PATCH 6/7] OMAP: Serial: Allow UART parameters to be configured from board file
* Govindraj govindraj...@gmail.com [110302 02:05]:
+static struct omap_device_pad default_serial1_pads[] __initdata = {
+ {
+ .name = uart2_rx.uart2_rx,
+ .flags = OMAP_DEVICE_PAD_REMUX |
OMAP_DEVICE_PAD_WAKEUP,
+ .enable = OMAP_MUX_MODE0,
+ },
...
AFAIK you should only need the OMAP_DEVICE_PAD_REMUX option for
omap24xx. And if you use that option, you also need the .idle
value.
Tony
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Re: Nokia n810 LCD (MIPID/blizzard) on 2.6.38
* Michael Buesch m...@bu3sch.de [110228 12:43]: The hwmod code performs a soft-reset on the GPIO module. The first GPIO module carries the MIPID nreset line, which is toggled due to the hwmod soft reset. This resets Blizzard and breaks it, because it assumes the LCD was left in the state that the bootloader initialized it to: The long term solution is to allow passing options to the hwmod framework to not reset pins from both board-*.c files and from cmdline. For this case it would be nice to pass info from the board-*.c file to hwmod so it knows to skip reset only for this GPIO. For booting Linux from other OS, something like hwmod.reset_disable=all is needed to keep the LCD on. Regrads, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: State of SDP4430 platform
Balaji, On Mon, 7 Feb 2011, Paul Walmsley wrote: On Wed, 19 Jan 2011, Paul Walmsley wrote: On Wed, 19 Jan 2011, Paul Walmsley wrote: On Wed, 19 Jan 2011, Krishnamoorthy, Balaji T wrote: in ES1, timeouts were observed only with RTC. I2C burst access to IRQ registers and bq24156 were OK Was an errata generated for this bug? er, erratum, pardon me... Is an erratum present for this bug? Also, will you generate a patch for this to at least warn the user when this situation occurs? Still waiting for a response to this. - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] OMAP3 PM: Deny clock gating only for safe state
Vishwanath Sripathy vishwanath...@ti.com writes: Kevin, -Original Message- From: Kevin Hilman [mailto:khil...@ti.com] Sent: Wednesday, March 02, 2011 2:32 AM To: Vishwanath BS Cc: linux-omap@vger.kernel.org; patc...@linaro.org Subject: Re: [PATCH 1/3] OMAP3 PM: Deny clock gating only for safe state Vishwanath BS vishwanath...@ti.com writes: Currently clock gating for MPU and core are denied whenever C1 state is selected. Yes, that is the definition of C1. It should be denied only when safe state is selected. Why? Clock gating in C1 will reduce overall power consumption and it should not impact any functionality as well. Clock gating changes latencies. This changes the definition and behavior of C1 depending on how it is entered. Not a good idea IMO. I thought of adding a new C state, keeping C1 definition unchanged. Then we will not get the real power benefit since in case of C1, clock gating will be prevented. Let me know if you have some suggestion. My problem with this patch is that you make C1 have different behavior depending on whether it is selected directly by the governor or it is entered due to the safe state. The motiviation for this change is not at all described in the changelog. Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 0/8] OMAP: HSMMC: hwmod adaptation
Kishore Kadiyala kishore.kadiy...@ti.com writes: Adding hwmod data for hsmmc device on OMAP2430/OMAP3/OMAP4. Adapting the omap_hsmmc driver to hwmod framework. Looks OK to me. Reviewed-by: Kevin Hilman khil...@ti.com Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 01/17] omap4: pm: Add omap WakeupGen module support
Hi Santosh, Santosh Shilimkar santosh.shilim...@ti.com writes: This patch adds OMAP WakeupGen support. The WakeupGen unit is responsible for generating wakeup event from the incoming interrupts and enable bits. The WakeupGen is implemented in MPU Always-On power domain. During normal operation, WakeupGen delivers external interrupts directly to the GIC. When the CPUx asserts StandbyWFI, indicating it wants to enter lowpower state, the Standby Controller checks with the WakeupGen unit using the idlereq/idleack handshake to make sure there is no incoming interrupts. The GIC and WakeupGen needs to be kept in synchronisation for proper interrupt functioning. Hence this patch hooks up the omap WakeupGen mask/unmask along with GIC using architecture specific hooks. Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com Reviewed-by: Kevin Hilman khil...@ti.com A few comments below... --- arch/arm/mach-omap2/Makefile |3 +- arch/arm/mach-omap2/include/mach/omap-wakeupgen.h | 40 arch/arm/mach-omap2/omap-wakeupgen.c | 213 + arch/arm/mach-omap2/omap4-common.c|3 + 4 files changed, 258 insertions(+), 1 deletions(-) create mode 100644 arch/arm/mach-omap2/include/mach/omap-wakeupgen.h create mode 100644 arch/arm/mach-omap2/omap-wakeupgen.c diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 72f2891..54ff219 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -24,7 +24,8 @@ obj-$(CONFIG_TWL4030_CORE) += omap_twl.o obj-$(CONFIG_SMP)+= omap-smp.o omap-headsmp.o obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o obj-$(CONFIG_HOTPLUG_CPU)+= omap-hotplug.o -obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o +obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o \ +omap-wakeupgen.o plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_omap-headsmp.o:=-Wa,-march=armv7-a$(plus_sec) diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h new file mode 100644 index 000..f10d106 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h @@ -0,0 +1,40 @@ +/* + * OMAP WakeupGen header file + * + * Copyright (C) 2011 Texas Instruments, Inc. + * Written by Santosh Shilimkar santosh.shilim...@ti.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef OMAP_ARCH_WAKEUPGEN_H +#define OMAP_ARCH_WAKEUPGEN_H + +#define OMAP_WKG_CONTROL_0 0x00 +#define OMAP_WKG_ENB_A_0 0x10 +#define OMAP_WKG_ENB_B_0 0x14 +#define OMAP_WKG_ENB_C_0 0x18 +#define OMAP_WKG_ENB_D_0 0x1c +#define OMAP_WKG_ENB_SECURE_A_0 0x20 +#define OMAP_WKG_ENB_SECURE_B_0 0x24 +#define OMAP_WKG_ENB_SECURE_C_0 0x28 +#define OMAP_WKG_ENB_SECURE_D_0 0x2c +#define OMAP_WKG_ENB_A_1 0x410 +#define OMAP_WKG_ENB_B_1 0x414 +#define OMAP_WKG_ENB_C_1 0x418 +#define OMAP_WKG_ENB_D_1 0x41c +#define OMAP_WKG_ENB_SECURE_A_1 0x420 +#define OMAP_WKG_ENB_SECURE_B_1 0x424 +#define OMAP_WKG_ENB_SECURE_C_1 0x428 +#define OMAP_WKG_ENB_SECURE_D_1 0x42c +#define OMAP_AUX_CORE_BOOT_0 0x800 +#define OMAP_AUX_CORE_BOOT_1 0x804 +#define OMAP_PTMSYNCREQ_MASK 0xc00 +#define OMAP_PTMSYNCREQ_EN 0xc04 +#define OMAP_TIMESTAMPCYCLELO0xc08 +#define OMAP_TIMESTAMPCYCLEHI0xc0c + +extern int __init omap_wakeupgen_init(void); +extern void omap_wakeupgen_irqmask_all(unsigned int cpu, unsigned int set); +#endif diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c new file mode 100644 index 000..e26a0ed --- /dev/null +++ b/arch/arm/mach-omap2/omap-wakeupgen.c @@ -0,0 +1,213 @@ +/* + * OMAP WakeupGen Source file + * + * The WakeupGen unit is responsible for generating wakeup event from the + * incoming interrupts and enable bits. The WakeupGen is implemented in MPU + * always-On power domain. The WakeupGen consists of two sub-units, one for + * each CPU and manages only SPI interrupts. Hardware requirements is that + * the GIC and WakeupGen should be kept in sync for proper operation. + * + * Copyright (C) 2011 Texas Instruments, Inc. + * Written by Santosh Shilimkar santosh.shilim...@ti.com + * + * This
Re: [PATCH 02/17] omap4: pm: Add SAR RAM support
Santosh Shilimkar santosh.shilim...@ti.com writes:
This patch adds SAR RAM support on OMAP4430. SAR RAM used to save
and restore the HW context in low power modes.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/omap4-common.c | 25 -
arch/arm/mach-omap2/omap4-sar-layout.h | 24
arch/arm/plat-omap/include/plat/omap44xx.h |1 +
3 files changed, 49 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap2/omap4-sar-layout.h
diff --git a/arch/arm/mach-omap2/omap4-common.c
b/arch/arm/mach-omap2/omap4-common.c
index 559d227..48484a5 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -23,12 +23,14 @@
#include mach/omap4-common.h
#include mach/omap-wakeupgen.h
+#include omap4-sar-layout.h
+
#ifdef CONFIG_CACHE_L2X0
void __iomem *l2cache_base;
#endif
void __iomem *gic_dist_base_addr;
-
+void __iomem *sar_ram_base;
void __init gic_init_irq(void)
{
@@ -107,3 +109,24 @@ static int __init omap_l2_cache_init(void)
}
early_initcall(omap_l2_cache_init);
#endif
+
+/*
+ * SAR RAM used to save and restore the HW
+ * context in low power modes
+ */
+static int __init omap4_sar_ram_init(void)
+{
+ /*
+ * To avoid code running on other OMAPs in
+ * multi-omap builds
+ */
+ if (!cpu_is_omap44xx())
+ return -ENODEV;
+
+ /* Static mapping, never released */
+ sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_8K);
+ BUG_ON(!sar_ram_base);
Again, a BUG is not approprate here.
Instead, other code needs to properly handle when sar_ram_base == NULL
+ return 0;
+}
+early_initcall(omap4_sar_ram_init);
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h
b/arch/arm/mach-omap2/omap4-sar-layout.h
new file mode 100644
index 000..bb66816
--- /dev/null
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -0,0 +1,24 @@
+/*
+ * omap4-sar-layout.h: OMAP4 SAR RAM layout header file
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Santosh Shilimkar santosh.shilim...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H
+#define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
+
+/*
+ * SAR BANK offsets from base address OMAP44XX_SAR_RAM_BASE
+ */
+#define SAR_BANK1_OFFSET 0x
+#define SAR_BANK2_OFFSET 0x1000
+#define SAR_BANK3_OFFSET 0x2000
+#define SAR_BANK4_OFFSET 0x3000
+
+extern void __iomem *sar_ram_base;
This patch creates this as global, but has no global users.
Also, personally, I don't like these 'base address as global pointer'
that are appearing throughout the OMAP4 code. This one is continuing
the pattern of some others (gic_dist_base_addr, gic_cpu_base) etc., but
I'm not crazy about them. BTW, the gic* ones also suffer from the BUG
problem and do not properly handle error conditions.
It would be much cleaner to keep this base address static (and local)
and just create some sar_read/write helpers that can be used from other
code.
Hmm, I see the assembly code uses this base address to. For that, a
helper function to get the base address could be created.
Kevin
+#endif
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h
b/arch/arm/plat-omap/include/plat/omap44xx.h
index ea2b8a6..c0d478e 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -45,6 +45,7 @@
#define OMAP44XX_WKUPGEN_BASE0x48281000
#define OMAP44XX_MCPDM_BASE 0x40132000
#define OMAP44XX_MCPDM_L3_BASE 0x49032000
+#define OMAP44XX_SAR_RAM_BASE0x4a326000
#define OMAP44XX_MAILBOX_BASE(L4_44XX_BASE + 0xF4000)
#define OMAP44XX_HSUSB_OTG_BASE (L4_44XX_BASE + 0xAB000)
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[PATCHv2] omap:mailbox: resolve hang issue
From: Hari Kanigeri h-kanige...@ti.com
omap4 interrupt disable bits is different. On rx kfifo full, the mbox rx
interrupts wasn't getting disabled, and this is causing the rcm stress tests
to hang.
Signed-off-by: Hari Kanigeri h-kanige...@ti.com
Signed-off-by: Armando Uribe x0095...@ti.com
Signed-off-by: Fernando Guzman Lugo fernando.l...@ti.com
---
arch/arm/mach-omap2/mailbox.c | 10 ++
1 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 394413d..011ca50 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -193,10 +193,12 @@ static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq)
{
struct omap_mbox2_priv *p = mbox-priv;
- u32 l, bit = (irq == IRQ_TX) ? p-notfull_bit : p-newmsg_bit;
- l = mbox_read_reg(p-irqdisable);
- l = ~bit;
- mbox_write_reg(l, p-irqdisable);
+ u32 bit = (irq == IRQ_TX) ? p-notfull_bit : p-newmsg_bit;
+
+ if (!cpu_is_omap44xx())
+ bit = mbox_read_reg(p-irqdisable) ~bit;
+
+ mbox_write_reg(bit, p-irqdisable);
}
static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
--
1.7.0.4
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Re: [PATCH 03/17] omap4: Export scu base address
Santosh Shilimkar santosh.shilim...@ti.com writes: The scu base address needs to be accessed in cpu hotplug for power management. Hence export the same As with previous patch, rather than export the base address itself, it should export a helper function to get the base address Kevin Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com Reviewed-by: Kevin Hilman khil...@ti.com --- arch/arm/mach-omap2/include/mach/omap4-common.h |4 arch/arm/mach-omap2/omap-smp.c |2 +- 2 files changed, 5 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h index 5b0270b..0e5edd8 100644 --- a/arch/arm/mach-omap2/include/mach/omap4-common.h +++ b/arch/arm/mach-omap2/include/mach/omap4-common.h @@ -26,6 +26,10 @@ extern void __iomem *l2cache_base; extern void __iomem *gic_dist_base_addr; +#ifdef CONFIG_SMP +extern void __iomem *scu_base; +#endif + extern void __init gic_init_irq(void); extern void omap_smc1(u32 fn, u32 arg); diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index b66cfe8..b105a29 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -26,7 +26,7 @@ #include mach/omap4-common.h /* SCU base address */ -static void __iomem *scu_base; +void __iomem *scu_base; static DEFINE_SPINLOCK(boot_lock); -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 07/17] omap4: pm: CPU1 wakeup workaround form Low power modes
Santosh Shilimkar santosh.shilim...@ti.com writes:
The SGI(Software Generated Interrupts) are not wakeup capable from
low power states. This is known limitation on OMAP4 and needs to be
worked around by using software forced clockdomain wake-up. CPU0 forces
the CPU1 clockdomain to software force wakeup. After the wakeup, CPU1
restores its clockdomain hardware supervised mode.
More details can be found in OMAP4430 TRM - Version J
Section :
4.3.4.2 Power States of CPU0 and CPU1
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/omap-hotplug.c |9 +
arch/arm/mach-omap2/omap-smp.c | 27 ++-
2 files changed, 35 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/omap-hotplug.c
b/arch/arm/mach-omap2/omap-hotplug.c
index 9f8f097..cf4ab15 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -23,6 +23,7 @@
#include mach/omap-wakeupgen.h
#include powerdomain.h
+#include clockdomain.h
int platform_cpu_kill(unsigned int cpu)
{
@@ -36,6 +37,11 @@ int platform_cpu_kill(unsigned int cpu)
void platform_cpu_die(unsigned int cpu)
{
unsigned int this_cpu;
+ static struct clockdomain *cpu1_clkdm;
+
+ /* To avoid cpu1 clockdomain lookup every time */
minor: comment doesn't really match code and could just be removed
+ if (!cpu1_clkdm)
+ cpu1_clkdm = clkdm_lookup(mpu1_clkdm);
flush_cache_all();
dsb();
@@ -59,6 +65,9 @@ void platform_cpu_die(unsigned int cpu)
* OK, proper wakeup, we're done
*/
omap_wakeupgen_irqmask_all(this_cpu, 0);
+
+ /* Restore clockdomain to hardware supervised */
+ clkdm_allow_idle(cpu1_clkdm);
break;
}
pr_debug(CPU%u: spurious wakeup call\n, cpu);
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index b105a29..31c9b79 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -25,6 +25,8 @@
#include mach/hardware.h
#include mach/omap4-common.h
+#include clockdomain.h
+
/* SCU base address */
void __iomem *scu_base;
@@ -48,6 +50,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
{
+ static struct clockdomain *cpu1_clkdm;
+ static bool booted;
/*
* Set synchronisation state between this boot processor
* and the secondary one
@@ -63,7 +67,28 @@ int __cpuinit boot_secondary(unsigned int cpu, struct
task_struct *idle)
omap_modify_auxcoreboot0(0x200, 0xfdff);
flush_cache_all();
smp_wmb();
- smp_cross_call(cpumask_of(cpu), 1);
+
+ /* To avoid cpu1 clockdomain lookup every time */
ditto
+ if (!cpu1_clkdm)
+ cpu1_clkdm = clkdm_lookup(mpu1_clkdm);
+
+ /*
+ * The SGI(Software Generated Interrupts) are not wakeup capable
+ * from low power states. This is known limitation on OMAP4 and
+ * needs to be worked around by using software forced clockdomain
+ * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
+ * software force wakeup. After the wakeup, CPU1 restores its
+ * clockdomain hardware supervised mode.
+ * More details can be found in OMAP4430 TRM - Version J
+ * Section :
+ * 4.3.4.2 Power States of CPU0 and CPU1
+ */
+ if (booted) {
+ clkdm_wakeup(cpu1_clkdm);
+ } else {
+ dsb_sev();
+ booted = true;
+ }
/*
* Now the secondary core is starting up let it run its
--
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Re: [PATCH 08/17] omap4: pm: Add GIC save/restore support
Santosh Shilimkar santosh.shilim...@ti.com writes:
On OMAP4 when attempting MPU off-mode or OSWR, the GIC context is
lost. This patch adds GIC context save and restore support.
The context save is done by software and restore is done by
ROM code from predefined SAR locations where the context suppose
s/suppose/supposed/
to be saved. Refer to ROM code specs for the GIC layout details.
Does this doc have a name? I've never seen such a thing and would
really like to.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/omap-hotplug.c |4 +
arch/arm/mach-omap2/omap4-mpuss-lowpower.c | 176
+++-
arch/arm/mach-omap2/omap4-sar-layout.h | 20 +++
3 files changed, 199 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/omap-hotplug.c
b/arch/arm/mach-omap2/omap-hotplug.c
index cf4ab15..deab389 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -19,6 +19,8 @@
#include linux/smp.h
#include asm/cacheflush.h
+#include asm/hardware/gic.h
+
#include mach/omap4-common.h
#include mach/omap-wakeupgen.h
@@ -58,6 +60,7 @@ void platform_cpu_die(unsigned int cpu)
* clear all interrupt wakeup sources
*/
omap_wakeupgen_irqmask_all(cpu, 1);
+ gic_secondary_set(0, true);
omap4_enter_lowpower(cpu, PWRDM_POWER_OFF);
this_cpu = hard_smp_processor_id();
if (omap_read_auxcoreboot0() == this_cpu) {
@@ -65,6 +68,7 @@ void platform_cpu_die(unsigned int cpu)
* OK, proper wakeup, we're done
*/
omap_wakeupgen_irqmask_all(this_cpu, 0);
+ gic_secondary_set(0, false);
/* Restore clockdomain to hardware supervised */
clkdm_allow_idle(cpu1_clkdm);
diff --git a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
index c0f358d..4140251 100644
--- a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
@@ -47,6 +47,8 @@
#include asm/tlbflush.h
#include asm/smp_scu.h
#include asm/system.h
+#include asm/irq.h
+#include asm/hardware/gic.h
#include plat/omap44xx.h
#include mach/omap4-common.h
@@ -59,6 +61,19 @@
#define CPU0_ID 0x0
#define CPU1_ID 0x1
+#define GIC_MASK_ALL 0x0
+#define GIC_ISR_NON_SECURE 0x
+#define SPI_ENABLE_SET_OFFSET0x04
+#define PPI_PRI_OFFSET 0x1c
+#define SPI_PRI_OFFSET 0x20
+#define SPI_TARGET_OFFSET0x20
+#define SPI_CONFIG_OFFSET0x20
+
+/* GIC save SAR bank base */
+static struct powerdomain *mpuss_pd;
+
+/* Variables to store maximum spi(Shared Peripheral Interrupts) registers. */
+static u32 max_spi_irq, max_spi_reg;
struct omap4_cpu_pm_info {
struct powerdomain *pwrdm;
@@ -67,6 +82,17 @@ struct omap4_cpu_pm_info {
static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
+/* Helper functions */
+static inline void sar_writel(u32 val, u32 offset, u8 idx)
+{
+ __raw_writel(val, sar_ram_base + offset + 4 * idx);
+}
aha, this is what I was thinking of in the earlier SAR patch.
Something like this should be part of the SAR code, not here.
+static inline u32 gic_readl(u32 offset, u8 idx)
+{
+ return __raw_readl(gic_dist_base_addr + offset + 4 * idx);
+}
Similarily, it would be nice tos see this as part of GIC code so
this code doesn't have to access a global base address pointer.
/*
* Set the CPUx powerdomain's previous power state
*/
@@ -124,6 +150,85 @@ static void scu_pwrst_prepare(unsigned int cpu_id,
unsigned int cpu_state)
}
/*
+ * Save GIC context in SAR RAM. Restore is done by ROM code
+ * GIC is lost only when MPU hits OSWR or OFF. It consists
+ * of a distributor and a per-CPU interface module. The GIC
+ * save restore is optimised to save only necessary registers.
+ */
+static void gic_save_context(void)
+{
+ u8 i;
+ u32 val;
+
+ /*
+ * Interrupt Clear Enable registers are inverse of set enable
+ * and hence not needed to be saved. ROM code programs it
+ * based on Set Enable register values.
+ */
+
+ /* Save CPU 0 Interrupt Set Enable register */
+ val = gic_readl(GIC_DIST_ENABLE_SET, 0);
+ sar_writel(val, ICDISER_CPU0_OFFSET, 0);
+
+ /* Disable interrupts on CPU1 */
+ sar_writel(GIC_MASK_ALL, ICDISER_CPU1_OFFSET, 0);
+
+ /* Save all SPI Set Enable register */
+ for (i = 0; i max_spi_reg; i++) {
+ val = gic_readl(GIC_DIST_ENABLE_SET + SPI_ENABLE_SET_OFFSET, i);
+ sar_writel(val, ICDISER_SPI_OFFSET, i);
+
Re: [PATCH 11/17] omap4: suspend: Add MPUSS RET and OFF support
Santosh Shilimkar santosh.shilim...@ti.com writes:
This patch adds MPUSS(MPU Sub System) RET and OFF mode support
to suspend path. For both MPUSS RET and OFF support, CPUs are
programmed to OFF state.
Only MPUSS RET and OFF supported at this point of time. CORE RET
will be added subsequently.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/omap4-mpuss-lowpower.c |8 ++-
arch/arm/mach-omap2/pm-debug.c |2 +
arch/arm/mach-omap2/pm.h |1 +
arch/arm/mach-omap2/pm44xx.c | 88
++--
4 files changed, 93 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
index bff768f..ab2e101 100644
--- a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
@@ -25,7 +25,7 @@
* ON(Inactive)OFF ON(Inactive)
* OFF OFF CSWR
* OFF OFF OSWR (*TBD)
- * OFF OFF OFF* (*TBD)
+ * OFF OFF OFF
* --
*
* Note: CPU0 is the master core and it is the last CPU to go down
@@ -291,6 +291,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int
power_state)
* Check MPUSS next state and save GIC if needed
* GIC lost during MPU OFF and OSWR
*/
+ pwrdm_clear_all_prev_pwrst(mpuss_pd);
if (pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_OFF) {
omap_wakeupgen_save();
gic_save_context();
@@ -357,6 +358,8 @@ int __init omap4_mpuss_init(void)
pr_err(Lookup failed for CPU0 pwrdm\n);
return -ENODEV;
}
+ /* Clear CPU previous power domain state */
+ pwrdm_clear_all_prev_pwrst(pm_info-pwrdm);
? duplicate of lines immediately following.
/* Clear CPU previous power domain state */
pwrdm_clear_all_prev_pwrst(pm_info-pwrdm);
@@ -394,6 +397,9 @@ int __init omap4_mpuss_init(void)
return -ENODEV;
}
+ /* Clear CPU previous power domain state */
+ pwrdm_clear_all_prev_pwrst(mpuss_pd);
+
/*
* Find out how many interrupts are supported.
* OMAP4 supports max of 128 SPIs where as GIC can support
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 125f565..9b46b3e 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -588,6 +588,8 @@ static int option_set(void *data, u64 val)
omap_pm_disable_off_mode();
if (cpu_is_omap34xx())
omap3_pm_off_mode_enable(val);
+ else if (cpu_is_omap44xx())
+ omap4_pm_off_mode_enable(val);
}
return 0;
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 1c1b0ab..f557407 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -17,6 +17,7 @@
extern void *omap3_secure_ram_storage;
extern void omap3_pm_off_mode_enable(int);
+extern void omap4_pm_off_mode_enable(int);
extern void omap_sram_idle(void);
extern int omap3_can_sleep(void);
extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 9a9dc41..f527e33 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -1,8 +1,9 @@
/*
* OMAP4 Power Management Routines
*
- * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010-2011 Texas Instruments, Inc.
* Rajendra Nayak rna...@ti.com
+ * Santosh Shilimkar santosh.shilim...@ti.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -21,6 +22,7 @@
#include powerdomain.h
#include clockdomain.h
+#include pm.h
struct power_state {
struct powerdomain *pwrdm;
@@ -36,7 +38,50 @@ static LIST_HEAD(pwrst_list);
#ifdef CONFIG_SUSPEND
static int omap4_pm_suspend(void)
{
- do_wfi();
+ struct power_state *pwrst;
+ int state, ret = 0;
+ u32 cpu_id = smp_processor_id();
+
+ /* Save current powerdomain state */
+ list_for_each_entry(pwrst, pwrst_list, node) {
+ pwrst-saved_state = pwrdm_read_next_pwrst(pwrst-pwrdm);
+ }
+
+ /* Set targeted power domain states by suspend */
+ list_for_each_entry(pwrst, pwrst_list, node) {
+ /* FIXME: Remove this check when CORE retention is supported */
+ if (!strcmp(pwrst-pwrdm-name, mpu_pwrdm))
+ omap_set_pwrdm_state(pwrst-pwrdm, pwrst-next_state);
+ }
pwrst_list is the list of powerdomains to that will be changed during
suspend.
Rather than doing this
Re: [PATCH 12/17] omap4: pm-debug: Add wakeup timer and debug counters
Santosh Shilimkar santosh.shilim...@ti.com writes:
This patch adds configurable wakeup timer support in suspend. Also
for statistics pm counter support is added.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/omap4-mpuss-lowpower.c |8
arch/arm/mach-omap2/pm-debug.c |6 --
arch/arm/mach-omap2/pm44xx.c |5 +
3 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
index ab2e101..5e0141e 100644
--- a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
@@ -287,6 +287,10 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int
power_state)
if (cpu)
goto cpu_prepare;
+#ifdef CONFIG_PM_DEBUG
+ pwrdm_pre_transition();
+#endif
Why the #ifdef?
/*
* Check MPUSS next state and save GIC if needed
* GIC lost during MPU OFF and OSWR
@@ -332,6 +336,10 @@ cpu_prepare:
gic_dist_set(CPU0_ID, 1);
}
+#ifdef CONFIG_PM_DEBUG
+ pwrdm_post_transition();
+#endif
+
ret:
return 0;
}
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 9b46b3e..7d6dd5b 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -606,9 +606,11 @@ static int __init pm_dbg_init(void)
if (pm_dbg_init_done)
return 0;
- if (cpu_is_omap34xx())
+ if (cpu_is_omap34xx()) {
pm_dbg_reg_modules = omap3_pm_reg_modules;
- else {
+ } else if (cpu_is_omap44xx()) {
+ /* Allow pm_dbg_init on OMAP4. */
Doing this will cause crashes if the 'registers/*' debugfs file is
accessed.
Since there are no 'reg_modules' created, you should also prevent the
creation of the 'registers' debugfs entries.
Kevin
+ } else {
printk(KERN_ERR %s: only OMAP3 supported\n, __func__);
return -ENODEV;
}
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index f527e33..8e57b42 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -42,6 +42,11 @@ static int omap4_pm_suspend(void)
int state, ret = 0;
u32 cpu_id = smp_processor_id();
+ /* Wakeup timer from suspend */
+ if (wakeup_timer_seconds || wakeup_timer_milliseconds)
+ omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
+ wakeup_timer_milliseconds);
+
/* Save current powerdomain state */
list_for_each_entry(pwrst, pwrst_list, node) {
pwrst-saved_state = pwrdm_read_next_pwrst(pwrst-pwrdm);
--
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Re: [PATCH 13/17] omap4: cpuidle: Basic CPUidle support
Santosh Shilimkar santosh.shilim...@ti.com writes:
From: Rajendra Nayak rna...@ti.com
The patch adds a basic CPUidle driver for OMAP4. Just
one C state is registered for both CPU cores which
does a wfi.
s/wfi/WFI/
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Kevin Hilman khil...@ti.com
Mostly minor nits below...
---
arch/arm/mach-omap2/Makefile |3 +-
arch/arm/mach-omap2/cpuidle44xx.c | 165
+
arch/arm/mach-omap2/pm.h |1 +
arch/arm/mach-omap2/pm44xx.c |2 +
4 files changed, 170 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap2/cpuidle44xx.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 5d94f7e..2b4fe44 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -64,7 +64,8 @@ obj-$(CONFIG_ARCH_OMAP2)+= sleep24xx.o pm_bus.o
voltage.o
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o voltage.o \
cpuidle34xx.o pm_bus.o
obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o voltage.o pm_bus.o \
-omap4-mpuss-lowpower.o sleep44xx.o
+omap4-mpuss-lowpower.o sleep44xx.o \
+cpuidle44xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)+= smartreflex-class3.o
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c
b/arch/arm/mach-omap2/cpuidle44xx.c
new file mode 100644
index 000..6c3c69d
--- /dev/null
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -0,0 +1,165 @@
+/*
+ * OMAP4 CPU IDLE Routines
s/IDLE/idle/
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Rajendra Nayak rna...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/sched.h
+#include linux/cpuidle.h
+
+#include asm/proc-fns.h
+
+#include mach/omap4-common.h
+
+#include pm.h
+
+#ifdef CONFIG_CPU_IDLE
+
+#define OMAP4_MAX_STATES 1
+/* C1 - CPUx wfi + MPU inactive + CORE inactive */
s/wfi/WFI/
+#define OMAP4_STATE_C1 0
+
+struct omap4_processor_cx {
+ u8 valid;
+ u8 type;
+ u32 sleep_latency;
+ u32 wakeup_latency;
+ u32 cpu0_state;
+ u32 cpu1_state;
+ u32 mpu_state;
+ u32 core_state;
+ u32 threshold;
+ u32 flags;
+};
+
+struct omap4_processor_cx omap4_power_states[OMAP4_MAX_STATES];
+struct omap4_processor_cx current_cx_state;
+
+static struct cpuidle_params cpuidle_params_table[] = {
+ /* C1 */
+ {1, 2, 2, 5},
+};
+
+/**
+ * omap4_enter_idle - Programs OMAP4 to enter the specified state
+ * @dev: cpuidle device
+ * @state: The target state to be programmed
+ *
+ * Called from the CPUidle framework to program the device to the
+ * specified low power state selected by the governor.
+ * Returns the amount of time spent in the low power state.
+ */
+static int omap4_enter_idle(struct cpuidle_device *dev,
+ struct cpuidle_state *state)
+{
+ struct timespec ts_preidle, ts_postidle, ts_idle;
+
+ /* Used to keep track of the total time in idle */
+ getnstimeofday(ts_preidle);
+
+ local_irq_disable();
+ local_fiq_disable();
+
+ cpu_do_idle();
+
+ getnstimeofday(ts_postidle);
+ ts_idle = timespec_sub(ts_postidle, ts_preidle);
+
+ local_irq_enable();
+ local_fiq_enable();
+
+ return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
+}
+
+DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
+
+/**
+ * omap4_init_power_states - Initialises the OMAP4 specific C states.
+ *
+ * Below is the desciption of each C state.
+ * C1 : CPUx wfi + MPU inative + Core inactive
+ */
+void omap_init_power_states(void)
+{
+ /* C1 . CPUx wfi + MPU inactive + Core inactive */
+ omap4_power_states[OMAP4_STATE_C1].valid =
+ cpuidle_params_table[OMAP4_STATE_C1].valid;
+ omap4_power_states[OMAP4_STATE_C1].type = OMAP4_STATE_C1;
+ omap4_power_states[OMAP4_STATE_C1].sleep_latency =
+ cpuidle_params_table[OMAP4_STATE_C1].sleep_latency;
+ omap4_power_states[OMAP4_STATE_C1].wakeup_latency =
+ cpuidle_params_table[OMAP4_STATE_C1].wake_latency;
+ omap4_power_states[OMAP4_STATE_C1].threshold =
+ cpuidle_params_table[OMAP4_STATE_C1].threshold;
+ omap4_power_states[OMAP4_STATE_C1].mpu_state = PWRDM_POWER_ON;
+ omap4_power_states[OMAP4_STATE_C1].core_state = PWRDM_POWER_ON;
+ omap4_power_states[OMAP4_STATE_C1].flags =
Re: [PATCH 16/17] omap4: cpuidle: Allow debugfs control through enable_off_mode
Santosh Shilimkar santosh.shilim...@ti.com writes:
Only MPU OFF and RET is controllable. CORE state is blocked
at ON state till the CORE RET support is added.
-ECONFUSED
None of the C-states currently have CORE != ON:
./cpuidle44xx.c:219:omap4_power_states[OMAP4_STATE_C1].core_state =
PWRDM_POWER_ON;
./cpuidle44xx.c:240:omap4_power_states[OMAP4_STATE_C2].core_state =
PWRDM_POWER_ON;
./cpuidle44xx.c:262:omap4_power_states[OMAP4_STATE_C3].core_state =
PWRDM_POWER_ON;
./cpuidle44xx.c:284:omap4_power_states[OMAP4_STATE_C4].core_state =
PWRDM_POWER_ON;
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/cpuidle44xx.c | 30 ++
arch/arm/mach-omap2/pm.h |1 +
arch/arm/mach-omap2/pm44xx.c |4
3 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c
b/arch/arm/mach-omap2/cpuidle44xx.c
index e887eb5..4207862 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -170,6 +170,31 @@ static int omap4_enter_idle_bm(struct cpuidle_device
*dev,
}
/**
+ * omap4_cpuidle_update_states() - Update the cpuidle states
+ * @mpu_deepest_state: Enable states upto and including this for mpu domain
+ * @core_deepest_state: Enable states upto and including this for core domain
+ *
+ * This goes through the list of states available and enables and disables
the
+ * validity of C states based on deepest state that can be achieved for the
+ * variable domain
+ */
+void omap4_cpuidle_update_states(u32 mpu_deepest_state, u32
core_deepest_state)
+{
+ int i;
+
+ for (i = OMAP4_STATE_C1; i OMAP4_MAX_STATES; i++) {
+ struct omap4_processor_cx *cx = omap4_power_states[i];
+
+ if ((cx-mpu_state = mpu_deepest_state)
+ (cx-core_state = core_deepest_state)) {
+ cx-valid = 1;
+ } else {
+ cx-valid = 0;
+ }
+ }
+}
Also, as mentioned in a previous patch, for OMAP4 I'd like to move away
from this approach to updating the states and rather use the -prepare
hook along with the ignore flag.
+/**
* omap4_init_power_states - Initialises the OMAP4 specific C states.
*
*/
@@ -325,6 +350,11 @@ int __init omap4_idle_init(void)
}
}
+ if (enable_off_mode)
+ omap4_cpuidle_update_states(PWRDM_POWER_OFF, PWRDM_POWER_OFF);
+ else
+ omap4_cpuidle_update_states(PWRDM_POWER_RET, PWRDM_POWER_RET);
+
return 0;
}
#else
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index ce848b0..4df89d1 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -77,6 +77,7 @@ extern u32 sleep_while_idle;
#if defined(CONFIG_CPU_IDLE)
extern void omap3_cpuidle_update_states(u32, u32);
+extern void omap4_cpuidle_update_states(u32, u32);
#endif
#if defined(CONFIG_PM_DEBUG) defined(CONFIG_DEBUG_FS)
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 628242d..6244ab2 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -183,6 +183,10 @@ void omap4_pm_off_mode_enable(int enable)
else
state = PWRDM_POWER_RET;
+#ifdef CONFIG_CPU_IDLE
+ omap4_cpuidle_update_states(state, PWRDM_POWER_ON);
+#endif
+
list_for_each_entry(pwrst, pwrst_list, node) {
/* FIXME: Remove this check when core retention is supported */
if (!strcmp(pwrst-pwrdm-name, mpu_pwrdm)) {
--
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Re: [PATCH 07/17] omap4: pm: CPU1 wakeup workaround form Low power modes
Santosh Shilimkar santosh.shilim...@ti.com writes: The SGI(Software Generated Interrupts) are not wakeup capable from low power states. This is known limitation on OMAP4 and needs to be worked around by using software forced clockdomain wake-up. CPU0 forces the CPU1 clockdomain to software force wakeup. After the wakeup, CPU1 restores its clockdomain hardware supervised mode. More details can be found in OMAP4430 TRM - Version J Section : 4.3.4.2 Power States of CPU0 and CPU1 Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com Reviewed-by: Kevin Hilman khil...@ti.com One other thing... in subject: s/form/from/ Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/17] omap4: pm: suspend, hotplug and cpuilde support
Santosh Shilimkar santosh.shilim...@ti.com writes: This series adds OMAP4 suspend and cpuidle support till MPU subsystem (MPUSS) off-mode. The suspend on SMP machines uses cpu-hotplug infrastructure to take down the non-boot CPUs. We put secondary CPU(CPU1 in OMAP4) to OFF state via cpu-hotplug. In cpuidle too, low power states are attempted only when the CPU1 is put to OFF state via cpu-hotplug because of hardware constraints. Minor nit on patch subjects: both OMAP and PM are acronyms, please capitalize. Also, can you rebase this on Paul's integration-2.6.39 branch? There are several things in this series that conflict with changes there. Thanks, Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 01/19] omap3: hwmod: add smartreflex irqs
Nishanth Menon n...@ti.com writes:
OMAP3 smartreflex irqs in hwmod structures with the same naming as
present in OMAP4. Without these IRQs being registered, SmartReflex
driver will be unable to get the irq numbers to handle notifications
Signed-off-by: Nishanth Menon n...@ti.com
minor: IRQ is an acronym, please capitalize consistenly throughout.
I know we haven't been too consitent about this but OMAP is also an
acronym, please capitialize (c.f. $SUBJECT). This goes for the whole
series.
Otherwise patch looks fine.
Kevin
---
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 17 +
1 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 8d81813..ea1f49a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -265,6 +265,15 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+
+static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
+ {.name = sr1_irq, .irq = 18},
+};
+
+static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
+ {.name = sr2_irq, .irq = 19},
+};
+
/* L4 CORE - SR1 interface */
static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
{
@@ -1289,6 +1298,8 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
CHIP_IS_OMAP3430ES3_0 |
CHIP_IS_OMAP3430ES3_1),
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
+ .mpu_irqs = omap3_smartreflex_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3_smartreflex_mpu_irqs),
};
static struct omap_hwmod omap36xx_sr1_hwmod = {
@@ -1308,6 +1319,8 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
.slaves = omap3_sr1_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
+ .mpu_irqs = omap3_smartreflex_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3_smartreflex_mpu_irqs),
};
/* SR2 */
@@ -1335,6 +1348,8 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
CHIP_IS_OMAP3430ES3_0 |
CHIP_IS_OMAP3430ES3_1),
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
+ .mpu_irqs = omap3_smartreflex_core_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3_smartreflex_core_irqs),
};
static struct omap_hwmod omap36xx_sr2_hwmod = {
@@ -1354,6 +1369,8 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
.slaves = omap3_sr2_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
+ .mpu_irqs = omap3_smartreflex_core_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3_smartreflex_core_irqs),
};
static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
--
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Re: [PATCH 03/19] omap3+: voltage: remove initial voltage
Menon, Nishanth n...@ti.com writes: On Wed, Feb 23, 2011 at 14:29, Vishwanath Sripathy vishwanath...@ti.com wrote: -Original Message- From: Menon, Nishanth [mailto:n...@ti.com] Sent: Wednesday, February 23, 2011 1:48 PM To: Vishwanath Sripathy Cc: linux-omap; Tony Lindgren; Kevin Hilman Subject: Re: [PATCH 03/19] omap3+: voltage: remove initial voltage Wed, Feb 23, 2011 at 12:24, Vishwanath Sripathy vishwanath...@ti.com wrote: -Original Message- From: Nishanth Menon [mailto:n...@ti.com] Sent: Sunday, February 20, 2011 10:42 AM To: Vishwanath Sripathy Cc: linux-omap; Tony Lindgren; Kevin Hilman Subject: Re: [PATCH 03/19] omap3+: voltage: remove initial voltage Vishwanath Sripathy wrote, on 02/19/2011 06:54 PM: [..] omap2_set_init_voltage should setup the curr_volt based on which OPP the system is functioning at. Blindly setting a 1.2v setting in the initial structure may not even match the default voltages stored in the voltage table which are supported for the domain. For example, OMAP3430 core domain does not use 1.2v and ends up generating a warning on the first transition. [..] diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach- omap2/voltage.c index 12be525..280ee12 100644 --- a/arch/arm/mach-omap2/voltage.c +++ b/arch/arm/mach-omap2/voltage.c [..] /* Generic voltage parameters */ - vdd-curr_volt = 120; Where do you update this parameter upon initialization? Shouldn't you read the VP register and find the actual current voltage and update this param? The sequence is as follows: a) omapx_vdd_data configure is called as part of sr init sequence. And the curr_volt with this patch is not updated at this stage. b) somewhere down in the boot sequence, pm.c's omap2_set_init_voltage starts up. This looks up the current clk frequency from clock layer of the parent device for the domain, picks up the nominal voltages stored in the opp layer, then does a omap_voltage_scale_vdd to that voltage. In omap_voltage_scale_vdd, The current voltage is merely picked off the vp (in _pre_volt_scale). the last step it does is to setup vdd-curr_volt. This can then be used by dvfs layer etc to make appropriate decisions. So, No, I dont think I need to update it here, it should happen as part of the pm init sequence. Could you explain what problem do you foresee by doing this? What if omap_voltage_scale_vdd fails when called from omap2_set_init_voltage? Or omap2_set_init_voltage returns error even before calling omap_voltage_scale_vdd because it could not find the matching voltage for the frequency set by bootloader? Your assumption that curr_volt is always set by omap2_set_init_voltage need not be true always. set_init_voltage's job is to set the initial voltage. if it is incapable of doing it, I say fix that instead of hacking in some random number as curr_volt. I never said to use random numbers. All I suggested was that instead of relying on some others function's behavior, read the VP register to fill in the right values. If set_init_voltage succeeds, it will anyway update with right voltage. OK, lets take this argument for a moment. Q: which voltage to set as curr_volt? a) what if the update was done over vcbypass by bootloader? Cannot trust the vp register for the value. b) what if the voltage was updated over i2c1 to the PMIC by bootloader? cant trust vp register again. c) use some number like 1.2v - which we are aligned is wrong. in short, what should we do for a accurate curr_volt? vp register may not be correct, instead, the right steps to do: find my current freq, check the OPP table for the voltage needed, setup the voltage for it, update curr_volt for it. this is trust worthy, rest are not. This is what set_init_voltage does, replicating that logic in voltage.c makes no sense again to me. Agreed. Please update the changelog with a summary of how curr_volt is properly updated so it's clear that you're not removing something that isn't updated elsewhere. Thanks, Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 08/19] omap3+: sr: make notify independent of class
Nishanth Menon n...@ti.com writes:
Interrupt notification mechanism of SmartReflex can be used by the
choice of implementation of the class driver. For example, Class 2 and
Class 1.5 of SmartReflex can both use the interrupt notification to
identify the transition of voltage or other events.
Hence, the actual class does not matter for notifier. Let the class
driver's handling decide how it should be used. smartreflex driver
should provide just the primitives.
Signed-off-by: Nishanth Menon n...@ti.com
Thanks, queueing for 2.6.39 after capitalizing OMAP SR in subject.
Kevin
---
arch/arm/mach-omap2/smartreflex.c |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
index eba90a4..6f0c7d0 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -142,7 +142,7 @@ static irqreturn_t sr_interrupt(int irq, void *data)
sr_write_reg(sr_info, IRQSTATUS, status);
}
- if (sr_class-class_type == SR_CLASS2 sr_class-notify)
+ if (sr_class-notify)
sr_class-notify(sr_info-voltdm, status);
return IRQ_HANDLED;
@@ -257,9 +257,7 @@ static int sr_late_init(struct omap_sr *sr_info)
struct resource *mem;
int ret = 0;
- if (sr_class-class_type == SR_CLASS2
- sr_class-notify_flags sr_info-irq) {
-
+ if (sr_class-notify sr_class-notify_flags sr_info-irq) {
name = kasprintf(GFP_KERNEL, sr_%s, sr_info-voltdm-name);
if (name == NULL) {
ret = -ENOMEM;
--
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Re: [PATCH 10/19] omap3+: sr: fix cosmetic indentation
Nishanth Menon n...@ti.com writes: Error label case seems to have a 2 tab indentation when just 1 is necessary. Signed-off-by: Nishanth Menon n...@ti.com Thanks, queueing for 2.6.39 after capitalizing OMAP and SR in subject. Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 11/19] omap3+: sr: call handler with interrupt disabled
Nishanth Menon n...@ti.com writes: Request the handler irq such that there is no nesting for calls. the notifiers are not expected to be nested, further the interrupt events for status change should be handled prior to the next event else there is a risk of loosing events. Signed-off-by: Nishanth Menon n...@ti.com IRQs disabled interrupt handlers are soon to disappear in the kernel. This kind of thing should be handled using locking, most likely IRQs disabled spinlocks. Kevin --- arch/arm/mach-omap2/smartreflex.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index 1fe8b95..7931fcd 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -278,7 +278,7 @@ static int sr_late_init(struct omap_sr *sr_info) goto error; } ret = request_irq(sr_info-irq, sr_interrupt, - 0, name, (void *)sr_info); + IRQF_DISABLED, name, (void *)sr_info); if (ret) goto error; } -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 12/19] omap3+: sr: disable interrupt by default
Nishanth Menon n...@ti.com writes: We will enable and disable interrupt on a need basis in the class driver. we need to keep the irq disabled by default else the forceupdate or vcbypass events could trigger events that we dont need/expect to handle. It's not clear from the patch where the IRQ is re-enabled. For example, without knowing better, I would expect a corresponding change to the Class 3 driver to enable/disable the IRQ as needed. Kevin Signed-off-by: Nishanth Menon n...@ti.com --- arch/arm/mach-omap2/smartreflex.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index 7931fcd..9c61ab0 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -281,6 +281,7 @@ static int sr_late_init(struct omap_sr *sr_info) IRQF_DISABLED, name, (void *)sr_info); if (ret) goto error; + disable_irq(sr_info-irq); } if (pdata pdata-enable_on_init) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
