Re: BUG: TI CPSW driver hanging up when setting mac-address to early
On Thursday 17 December 2015 01:39 PM, Pascal Speck (Iktek) wrote:
> Hi Mugunthan,
> please see my comments below:
>
> Am 17.12.2015 um 07:08 schrieb Mugunthan V N:
>> On Tuesday 08 December 2015 09:55 PM, Tony Lindgren wrote:
>>> * ker...@iktek.de <ker...@iktek.de> [151207 09:17]:
>>>> Hi Tony,
>>>>
>>>> there are two ethernet interfaces ( dual-emac-configuration ) used.
>>>> One is connected to another 100mbit switch-ic ( refclk should come from
>>>> switch ic ) via rmii, the other one is connected to a 1gbit fpga rgmii
>>>> interface ( where the clock is served from the fpga ).
>> This means you have both the interfaces with MAC-to-MAC interface. Is
>> MDIO is active or did you disabled it as it is not needed (because of no
>> phy present in the system)?
> Yes, both interfaces are mac-to-mac. The mdio-node is available in the
> dt, but the pinmux has been commented out as the pins are not used.
> These are the relevant parts of the dt:
>
> ---snip---
>
> davinci_mdio_default: davinci_mdio_default {
> pinctrl-single,pins = <
> /* MDIO */
> /* 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST |
> MUX_MODE0)*/ /* mdio_data.mdio_data */
> /* 0x14c (PIN_OUTPUT_PULLUP |
> MUX_MODE0) */ /* mdio_clk.mdio_clk */
> >;
> };
>
> ---snip---
>
> _emac0 {
> phy-mode = "rgmii";
> dual_emac_res_vlan = <1>;
> /* fixed-link = <1 1000 0 0>; */
> fixed-link {
> speed = <1000>;
> full-duplex;
> };
> };
>
> _emac1 {
> phy-mode = "rmii";
> dual_emac_res_vlan = <2>;
> /* fixed-link = <1 100 0 0>; */
> fixed-link {
> speed = <100>;
> full-duplex;
> };
> };
>
>
> _sel {
> rmii-clock-ext;
> };
>
> {
> pinctrl-names = "default", "sleep";
> pinctrl-0 = <_default>;
> pinctrl-1 = <_sleep>;
> status = "okay";
> dual_emac;
> };
>
> _mdio {
> pinctrl-names = "default";
> pinctrl-0 = <_mdio_default>;
> pinctrl-1 = <_mdio_sleep>;
> status = "okay";
> };
>
> ---snip---
>
>>>> On both interfaces it may happen that the clock isn't present while the
>>>> mac-address is set (fpga may not have been inited, switch chip could be
>>>> held in reset), but this was the same behaviour with previous kernel
>>>> (3.14 with cpsw patched from ti tree) where this configuration worked.
>>>> As the hardware is in field now there is no chance to change hardware.
>>>>
>>>> On the other hand: when not setting the mac of the interface that
>>>> early,
>>>> the cpsw seems to init proberly but a ping to the outer world does not
>>>> work either, so something else may be different on the new kernel.
>>> Maybe Mugunthan has some ideas what's going on here.
>>>
>> If MDIO is disabled and CPSW is not brought up then CPSW clocks are
>> gated and when you try to set the mac address the system will crash as
>> the driver try to access CPSW registers with CPSW clocks gated. Can you
>> try below options and see what happens
>>
>> * Instead of setting the mac address using *ip link set address*, try to
>> use u-boot env variable (ethaddr/ath1addr) to set the mac address.
>>
>> * You must be storing the MAC address in EEPROM or somewhere, just try
>> to implement the mac address reading mechanism in
>> drivers/net/ethernet/ti/cpsw-common.c file to avoid setting of mac
>> address from userspace.
> I'll try this as soon as possible ( unfortunately this would be
> beginning of next year probably as I'm very busy the last days of the
> year ).
> As the eeprom layout has not been setup by myself, it could take a while
> to reimplement this in kernelspace.
> Would it be a good deal to check somehow if the clocks have been enabled
> before allowing this options to be set by userspace?
You can try accessing the cpsw register space using memtool from userspace.
Even if mdio is enabled in DT, if CPSW is not probed then CPSW clocks
will be in gates state which will cause a crash while accessing its
registers.
Regards
Mugunthan V N
>>
> Thanks for the good opinions. I appreciate your help.
> Regards Pascal
>
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Re: BUG: TI CPSW driver hanging up when setting mac-address to early
On Tuesday 08 December 2015 09:55 PM, Tony Lindgren wrote: > * ker...@iktek.de <ker...@iktek.de> [151207 09:17]: >> Hi Tony, >> >> there are two ethernet interfaces ( dual-emac-configuration ) used. >> One is connected to another 100mbit switch-ic ( refclk should come from >> switch ic ) via rmii, the other one is connected to a 1gbit fpga rgmii >> interface ( where the clock is served from the fpga ). This means you have both the interfaces with MAC-to-MAC interface. Is MDIO is active or did you disabled it as it is not needed (because of no phy present in the system)? >> >> On both interfaces it may happen that the clock isn't present while the >> mac-address is set (fpga may not have been inited, switch chip could be >> held in reset), but this was the same behaviour with previous kernel >> (3.14 with cpsw patched from ti tree) where this configuration worked. >> As the hardware is in field now there is no chance to change hardware. >> >> On the other hand: when not setting the mac of the interface that early, >> the cpsw seems to init proberly but a ping to the outer world does not >> work either, so something else may be different on the new kernel. > > Maybe Mugunthan has some ideas what's going on here. > If MDIO is disabled and CPSW is not brought up then CPSW clocks are gated and when you try to set the mac address the system will crash as the driver try to access CPSW registers with CPSW clocks gated. Can you try below options and see what happens * Instead of setting the mac address using *ip link set address*, try to use u-boot env variable (ethaddr/ath1addr) to set the mac address. * You must be storing the MAC address in EEPROM or somewhere, just try to implement the mac address reading mechanism in drivers/net/ethernet/ti/cpsw-common.c file to avoid setting of mac address from userspace. Regards Mugunthan V N -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 06/14] ARM: am437x: cm-t43: dts: add dual emac support
On Tuesday 24 November 2015 06:49 PM, Nikita Kiryanov wrote: > CM-T43 comes with 2 ethernet ports connected to the cpsw subsystem, which > has 2 modes of operation: switch mode and dual emac mode. > Add the relevant muxing and set it up to work in dual emac mode by > default. > > Signed-off-by: Nikita Kiryanov <nik...@compulab.co.il> > Cc: Tony Lindgren <t...@atomide.com> > Cc: Igor Grinberg <grinb...@compulab.co.il> > Cc: Dmitry Lifshitz <lifsh...@compulab.co.il> > Cc: Ian Campbell <ijc+devicet...@hellion.org.uk> Acked-by: Mugunthan V N <mugunthan...@ti.com> Regards Mugunthan V N -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] net: cpsw: Fix ethernet regression for dm814x
On Thursday 19 November 2015 06:57 AM, Tony Lindgren wrote:
> Commit b6745f6e4e63 ("drivers: net: cpsw: davinci_emac: move reading mac
> id to common file") started using of_machine_is_compatible for detecting
> type but missed at dm8148 causing Ethernet to stop working.
>
> Let's fix the issue by adding handling for dm814x.
>
> Cc: Mugunthan V N <mugunthan...@ti.com>
> Signed-off-by: Tony Lindgren <t...@atomide.com>
Acked-by: Mugunthnan V N <mugunthan...@ti.com>
Regards
Mugunthan V N
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[PATCH 0/2] adding spi alias for qspi
Adding missed spi alias for qspi which helps probe the qspi device in U-Boot. Mugunthan V N (2): dts: dra7: add spi alias for qspi arm: dts: am4372: add spi alias for qspi arch/arm/boot/dts/am4372.dtsi | 1 + arch/arm/boot/dts/dra7.dtsi | 1 + 2 files changed, 2 insertions(+) -- 2.6.2.280.g74301d6 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] dts: dra7: add spi alias for qspi
Set the alias for qspi to spi0
Signed-off-by: Mugunthan V N <mugunthan...@ti.com>
---
arch/arm/boot/dts/dra7.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index bc672fb..b2badf9 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -41,6 +41,7 @@
ethernet1 = _emac1;
d_can0 =
d_can1 =
+ spi0 =
};
timer {
--
2.6.2.280.g74301d6
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[PATCH 2/2] arm: dts: am4372: add spi alias for qspi
Set the alias for qspi to spi0
Signed-off-by: Mugunthan V N <mugunthan...@ti.com>
---
arch/arm/boot/dts/am4372.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index d83ff9c..bb03b80 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -30,6 +30,7 @@
serial5 =
ethernet0 = _emac0;
ethernet1 = _emac1;
+ spi0 =
};
cpus {
--
2.6.2.280.g74301d6
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Re: [PATCH] drivers: net: cpsw: Add support for fixed-link PHY
On Wednesday 04 November 2015 02:39 AM, Markus Brunner wrote: > Add support for a fixed-link devicetree sub-node in case the the > cpsw MAC is directly connected to a non-mdio PHY/device. > > Signed-off-by: Markus Brunner <systemprogrammierung.brun...@gmail.com> Looks good to me. Acked-by: Mugunthan V N <mugunthan...@ti.com> Regards Mugunthan V N -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/6] ARM: OMAP2+: dts: cm-t335: add support for network device
On Tuesday 27 October 2015 05:44 PM, Uri Mashiach wrote: > From: Ilya Ledvich <i...@compulab.co.il> > > Add pinmux configurations for RGMII1 based CPSW Ethernet pins and > MDIO pins: > - default configuration required for module in active state, > - sleep configuration required for module in inactive state. > Add mac node with single slave device. Add nodes for davinci_mdio and > cpsw_emac0. > > Acked-by: Igor Grinberg <grinb...@compulab.co.il> > Signed-off-by: Ilya Ledvich <i...@compulab.co.il> > Signed-off-by: Uri Mashiach <uri.mashi...@compulab.co.il> Acked-by: Mugunthan V N <mugunthan...@ti.com> Regards Mugunthan V N -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [net-next PATCH] driver: net: cpsw: add no_bd_ram dt parsing
On Friday 09 October 2015 03:36 PM, Mugunthan V N wrote: > cpdma is capable of placing the dma descriptors in ddr using > dma_alloc_coherent() when the internal bd ram size is not enough. > To utilize this feature pass the DT parameter "no_bd_ram" and > increase bd_ram_size and number of rx descriptors. > > Signed-off-by: Mugunthan V N <mugunthan...@ti.com> Dave Please drop this patch as it is not working on AM437x platform. Will send a v2 after fixing it. Regards Mugunthan V N -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/3] Fix mmc/sd card detect gpio dt definition
The mmc/sd card detect gpio definition in DT is not defined as per hardware design, the card detect gpio is an active low signal. As per MMC/SD device tree binding documentation, the card detect signal should be an active low signal and when ever a hardware is designed with an active high card detect gpio then "cd-inverted" dt parameter should be used to detect the actual status for the card. This was not captured till now because gpio is used as interrupt source and mmc_rescan task is scheduled. The value of the gpio is not used to determine card presence. Pushed a branch [1] for testing and tested this patch series on am335x bone black [2], am437x-gp evm [3] and dra72x evm [4]. [1]: git://git.ti.com/~mugunthanvnm/ti-linux-kernel/linux.git mmc-cd-gpio-fix [2]: http://pastebin.ubuntu.com/12762164/ [3]: http://pastebin.ubuntu.com/12762168/ [4]: http://pastebin.ubuntu.com/12762169/ Mugunthan V N (3): ARM: DTS: am335x: fix cd-gpios definition as per hardware design and dt binding docs ARM: DTS: am43xx: fix cd-gpios definition as per hardware design and dt binding docs ARM: DTS: dra7xx: am57xx: fix cd-gpios definition as per hardware design and dt binding docs arch/arm/boot/dts/am335x-bone-common.dtsi | 3 +-- arch/arm/boot/dts/am335x-evm.dts | 2 +- arch/arm/boot/dts/am335x-evmsk.dts| 2 +- arch/arm/boot/dts/am437x-gp-evm.dts | 2 +- arch/arm/boot/dts/am437x-idk-evm.dts | 2 +- arch/arm/boot/dts/am437x-sk-evm.dts | 2 +- arch/arm/boot/dts/am43x-epos-evm.dts | 2 +- arch/arm/boot/dts/am57xx-beagle-x15.dts | 2 +- arch/arm/boot/dts/dra7-evm.dts| 2 +- arch/arm/boot/dts/dra72-evm.dts | 2 +- 10 files changed, 10 insertions(+), 11 deletions(-) -- 2.6.1.133.gf5b6079 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] ARM: DTS: am43xx: fix cd-gpios definition as per hardware design and dt binding docs
As per mmc device tree binding documentation card detect gpio has
to be active low signal. When a hardware is designed with active
high card detect, gpio polarity has to be changed with
cd-inverted dt property.
In AM43xx the card detect gpio is designed as active low gpio.
So correcting the dt card detect gpio definition.
Signed-off-by: Mugunthan V N <mugunthan...@ti.com>
---
arch/arm/boot/dts/am437x-gp-evm.dts | 2 +-
arch/arm/boot/dts/am437x-idk-evm.dts | 2 +-
arch/arm/boot/dts/am437x-sk-evm.dts | 2 +-
arch/arm/boot/dts/am43x-epos-evm.dts | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 22038f2..81de3a1 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -689,7 +689,7 @@
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <_pins>;
- cd-gpios = < 6 GPIO_ACTIVE_HIGH>;
+ cd-gpios = < 6 GPIO_ACTIVE_LOW>;
};
/* eMMC sits on mmc2 */
diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts
b/arch/arm/boot/dts/am437x-idk-evm.dts
index af25801..337fb91 100644
--- a/arch/arm/boot/dts/am437x-idk-evm.dts
+++ b/arch/arm/boot/dts/am437x-idk-evm.dts
@@ -325,7 +325,7 @@
pinctrl-1 = <_pins_sleep>;
vmmc-supply = <_3d>;
bus-width = <4>;
- cd-gpios = < 6 GPIO_ACTIVE_HIGH>;
+ cd-gpios = < 6 GPIO_ACTIVE_LOW>;
};
{
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts
b/arch/arm/boot/dts/am437x-sk-evm.dts
index 7da7c2d..1582fdb 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -563,7 +563,7 @@
vmmc-supply = <>;
bus-width = <4>;
- cd-gpios = < 6 GPIO_ACTIVE_HIGH>;
+ cd-gpios = < 6 GPIO_ACTIVE_LOW>;
};
_phy1 {
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index 86c2dfb..47954ed 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -376,7 +376,7 @@
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <_pins>;
- cd-gpios = < 6 GPIO_ACTIVE_HIGH>;
+ cd-gpios = < 6 GPIO_ACTIVE_LOW>;
};
{
--
2.6.1.133.gf5b6079
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[PATCH 3/3] ARM: DTS: dra7xx: am57xx: fix cd-gpios definition as per hardware design and dt binding docs
As per mmc device tree binding documentation card detect gpio has
to be active low signal. When a hardware is designed with active
high card detect, gpio polarity has to be changed with
cd-inverted dt property.
In DRA74x, DRA72x and AM57xx EVMs the card detect gpio is
designed as active low gpio. So correcting the dt card detect
gpio definition.
Signed-off-by: Mugunthan V N <mugunthan...@ti.com>
---
arch/arm/boot/dts/am57xx-beagle-x15.dts | 2 +-
arch/arm/boot/dts/dra7-evm.dts | 2 +-
arch/arm/boot/dts/dra72-evm.dts | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts
b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 568adf5..e554596 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -585,7 +585,7 @@
vmmc-supply = <_reg>;
bus-width = <4>;
- cd-gpios = < 27 0>; /* gpio 219 */
+ cd-gpios = < 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
};
{
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index a6c82e5..4379277 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -479,7 +479,7 @@
* SDCD signal is not being used here - using the fact that GPIO mode
* is always hardwired.
*/
- cd-gpios = < 27 0>;
+ cd-gpios = < 27 GPIO_ACTIVE_LOW>;
};
{
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 6f6bd98..d4aca5a1 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -514,7 +514,7 @@
* SDCD signal is not being used here - using the fact that GPIO mode
* is a viable alternative
*/
- cd-gpios = < 27 0>;
+ cd-gpios = < 27 GPIO_ACTIVE_LOW>;
max-frequency = <19200>;
};
--
2.6.1.133.gf5b6079
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[PATCH 1/3] ARM: DTS: am335x: fix cd-gpios definition as per hardware design and dt binding docs
As per mmc device tree binding documentation card detect gpio has
to be active low signal. When a hardware is designed with active
high card detect, gpio polarity has to be changed with
cd-inverted dt property.
In AM335x the card detect gpio is designed as active low gpio.
So correcting the dt card detect gpio definition.
Signed-off-by: Mugunthan V N <mugunthan...@ti.com>
---
arch/arm/boot/dts/am335x-bone-common.dtsi | 3 +--
arch/arm/boot/dts/am335x-evm.dts | 2 +-
arch/arm/boot/dts/am335x-evmsk.dts| 2 +-
3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi
b/arch/arm/boot/dts/am335x-bone-common.dtsi
index fec7834..5d370d5 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -383,8 +383,7 @@
bus-width = <0x4>;
pinctrl-names = "default";
pinctrl-0 = <_pins>;
- cd-gpios = < 6 GPIO_ACTIVE_HIGH>;
- cd-inverted;
+ cd-gpios = < 6 GPIO_ACTIVE_LOW>;
};
{
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 1942a5c..d9d00ab 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -737,7 +737,7 @@
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <_pins>;
- cd-gpios = < 6 GPIO_ACTIVE_HIGH>;
+ cd-gpios = < 6 GPIO_ACTIVE_LOW>;
};
{
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index 315bb02..89442e9 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -647,7 +647,7 @@
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <_pins>;
- cd-gpios = < 6 GPIO_ACTIVE_HIGH>;
+ cd-gpios = < 6 GPIO_ACTIVE_LOW>;
};
{
--
2.6.1.133.gf5b6079
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[net-next PATCH] driver: net: cpsw: add no_bd_ram dt parsing
cpdma is capable of placing the dma descriptors in ddr using
dma_alloc_coherent() when the internal bd ram size is not enough.
To utilize this feature pass the DT parameter "no_bd_ram" and
increase bd_ram_size and number of rx descriptors.
Signed-off-by: Mugunthan V N <mugunthan...@ti.com>
---
drivers/net/ethernet/ti/cpsw.c | 4
drivers/net/ethernet/ti/cpsw.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 8fc90f1..cf1a625 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -1987,6 +1987,8 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data,
}
data->ale_entries = prop;
+ data->no_bd_ram = of_property_read_bool(node, "no_bd_ram");
+
if (of_property_read_u32(node, "bd_ram_size", )) {
dev_err(>dev, "Missing bd_ram_size property in the
DT.\n");
return -EINVAL;
@@ -2358,6 +2360,8 @@ static int cpsw_probe(struct platform_device *pdev)
dma_params.desc_mem_size= data->bd_ram_size;
dma_params.desc_align = 16;
dma_params.has_ext_regs = true;
+ if (data->no_bd_ram)
+ dma_params.desc_mem_phys = 0;
dma_params.desc_hw_addr = dma_params.desc_mem_phys;
priv->dma = cpdma_ctlr_create(_params);
diff --git a/drivers/net/ethernet/ti/cpsw.h b/drivers/net/ethernet/ti/cpsw.h
index ca90efa..b654ac2 100644
--- a/drivers/net/ethernet/ti/cpsw.h
+++ b/drivers/net/ethernet/ti/cpsw.h
@@ -33,6 +33,7 @@ struct cpsw_platform_data {
u32 cpts_clock_mult; /* convert input clock ticks to nanoseconds */
u32 cpts_clock_shift; /* convert input clock ticks to nanoseconds */
u32 ale_entries;/* ale table size */
+ boolno_bd_ram; /* set if cpsw bd ram should not be used */
u32 bd_ram_size; /*buffer descriptor ram size */
u32 rx_descs; /* Number of Rx Descriptios */
u32 mac_control;/* Mac control register */
--
2.6.1.133.gf5b6079
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[PATCH 1/1] ARM: DTS: dra72-evm: remove cpsw gpio hogging and add select-slave-gpio
Since GPIO hogging fails to through error when booting with
gpio-pcf857x as module and NFS root filesystem. So by having
mode-gpio, it throw error to user so that the used can make
gpio-pcf857x as inbuilt for NFS. When using mmc/ramdisk as root
fs, cpsw will probe defer and re-probes again when gpio-pcf857x
module is inserted and ethernet becomes operational.
Signed-off-by: Mugunthan V N <mugunthan...@ti.com>
---
The driver patch is applied to net-next branch (also present in
linux-next) with commit '1d147ccbfc35 ("drivers: net: cpsw: Add
support to drive gpios for ethernet to be functional") and logs
[1] also pushed a branch [2] for testing.
[1]: http://pastebin.ubuntu.com/12306224/
[2]: git://git.ti.com/~mugunthanvnm/ti-linux-kernel/linux.git
cpsw-gpio-optional-v3
---
arch/arm/boot/dts/dra72-evm.dts | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index c11ccb1..b7eca13 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -353,12 +353,6 @@
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
-
- cpsw_sel_s0 {
- gpio-hog;
- gpios = <4 GPIO_ACTIVE_HIGH>;
- output-low;
- };
};
};
@@ -590,6 +584,7 @@
pinctrl-0 = <_default>;
pinctrl-1 = <_sleep>;
slaves = <1>;
+ mode-gpios = <_gpio_21 4 GPIO_ACTIVE_HIGH>;
};
_emac0 {
--
2.6.0.rc2.10.gf4d9753
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[net-next PATCH 4/4] arm: dts: am4372: add syscon phandle to cpsw node
There are 2 MACIDs stored in the control module of the am4372.
These are read by the cpsw driver if no valid MACID was found
in the devicetree.
Signed-off-by: Mugunthan V N <mugunthan...@ti.com>
---
arch/arm/boot/dts/am4372.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 0447c04a..d83ff9c 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -591,6 +591,7 @@
cpts_clock_mult = <0x8000>;
cpts_clock_shift = <29>;
ranges;
+ syscon = <_conf>;
davinci_mdio: mdio@4a101000 {
compatible = "ti,am4372-mdio","ti,davinci_mdio";
--
2.6.0.rc2.10.gf4d9753
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[net-next PATCH 0/4] Add support for reading macid when DT macid not found
Did a boot test on dra7-evm [1] and am437x-gp-evm [2]. Pushed a branch [3] for others to test the patch. [1]: http://pastebin.ubuntu.com/12513420/ [2]: http://pastebin.ubuntu.com/12513428/ [3]: git://git.ti.com/~mugunthanvnm/ti-linux-kernel/linux.git cpsw-macid-read-support Mugunthan V N (4): drivers: net: cpsw: davinci_emac: move reading mac id to common file drivers: net: cpsw-common: add support for reading mac address for dra7 and am437x platforms arm: dts: dra7: add syscon phandle to cpsw node arm: dts: am4372: add syscon phandle to cpsw node arch/arm/boot/dts/am4372.dtsi | 1 + arch/arm/boot/dts/dra7.dtsi| 1 + drivers/net/ethernet/ti/cpsw-common.c | 64 +- drivers/net/ethernet/ti/cpsw.c | 11 +++--- drivers/net/ethernet/ti/cpsw.h | 3 +- drivers/net/ethernet/ti/davinci_emac.c | 44 ++- 6 files changed, 65 insertions(+), 59 deletions(-) -- 2.6.0.rc2.10.gf4d9753 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[net-next PATCH 3/4] arm: dts: dra7: add syscon phandle to cpsw node
There are 2 MACIDs stored in the control module of the dra7.
These are read by the cpsw driver if no valid MACID was found
in the devicetree.
Signed-off-by: Mugunthan V N <mugunthan...@ti.com>
---
arch/arm/boot/dts/dra7.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 5d65db9..76c739d 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1447,6 +1447,7 @@
,
;
ranges;
+ syscon = <_conf>;
status = "disabled";
davinci_mdio: mdio@48485000 {
--
2.6.0.rc2.10.gf4d9753
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[net-next PATCH 2/4] drivers: net: cpsw-common: add support for reading mac address for dra7 and am437x platforms
Adding support for reading mac address using syscon driver for
dra7 and am437x platforms
Signed-off-by: Mugunthan V N <mugunthan...@ti.com>
---
drivers/net/ethernet/ti/cpsw-common.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/ethernet/ti/cpsw-common.c
b/drivers/net/ethernet/ti/cpsw-common.c
index c70417c..c08be62 100644
--- a/drivers/net/ethernet/ti/cpsw-common.c
+++ b/drivers/net/ethernet/ti/cpsw-common.c
@@ -87,6 +87,12 @@ int ti_cm_get_macid(struct device *dev, int slave, u8
*mac_addr)
if (of_device_is_compatible(dev->of_node, "ti,dm816-emac"))
return cpsw_am33xx_cm_get_macid(dev, 0x30, slave, mac_addr);
+ if (of_machine_is_compatible("ti,am4372"))
+ return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
+
+ if (of_machine_is_compatible("ti,dra7"))
+ return davinci_emac_3517_get_macid(dev, 0x514, slave, mac_addr);
+
dev_err(dev, "incompatible machine/device type for reading mac
address\n");
return -ENOENT;
}
--
2.6.0.rc2.10.gf4d9753
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[net-next PATCH 1/4] drivers: net: cpsw: davinci_emac: move reading mac id to common file
Moving mac address reading from ethernet driver to common
file for better maintenance and for code reusable.
Signed-off-by: Mugunthan V N <mugunthan...@ti.com>
---
drivers/net/ethernet/ti/cpsw-common.c | 58 --
drivers/net/ethernet/ti/cpsw.c | 11 +++
drivers/net/ethernet/ti/cpsw.h | 3 +-
drivers/net/ethernet/ti/davinci_emac.c | 44 ++
4 files changed, 57 insertions(+), 59 deletions(-)
diff --git a/drivers/net/ethernet/ti/cpsw-common.c
b/drivers/net/ethernet/ti/cpsw-common.c
index f595094..c70417c 100644
--- a/drivers/net/ethernet/ti/cpsw-common.c
+++ b/drivers/net/ethernet/ti/cpsw-common.c
@@ -19,11 +19,38 @@
#include "cpsw.h"
-#define AM33XX_CTRL_MAC_LO_REG(offset, id) ((offset) + 0x8 * (id))
-#define AM33XX_CTRL_MAC_HI_REG(offset, id) ((offset) + 0x8 * (id) + 0x4)
+#define CTRL_MAC_LO_REG(offset, id) ((offset) + 0x8 * (id))
+#define CTRL_MAC_HI_REG(offset, id) ((offset) + 0x8 * (id) + 0x4)
-int cpsw_am33xx_cm_get_macid(struct device *dev, u16 offset, int slave,
-u8 *mac_addr)
+static int davinci_emac_3517_get_macid(struct device *dev, u16 offset,
+ int slave, u8 *mac_addr)
+{
+ u32 macid_lsb;
+ u32 macid_msb;
+ struct regmap *syscon;
+
+ syscon = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");
+ if (IS_ERR(syscon)) {
+ if (PTR_ERR(syscon) == -ENODEV)
+ return 0;
+ return PTR_ERR(syscon);
+ }
+
+ regmap_read(syscon, CTRL_MAC_LO_REG(offset, slave), _lsb);
+ regmap_read(syscon, CTRL_MAC_HI_REG(offset, slave), _msb);
+
+ mac_addr[0] = (macid_msb >> 16) & 0xff;
+ mac_addr[1] = (macid_msb >> 8) & 0xff;
+ mac_addr[2] = macid_msb & 0xff;
+ mac_addr[3] = (macid_lsb >> 16) & 0xff;
+ mac_addr[4] = (macid_lsb >> 8) & 0xff;
+ mac_addr[5] = macid_lsb & 0xff;
+
+ return 0;
+}
+
+static int cpsw_am33xx_cm_get_macid(struct device *dev, u16 offset, int slave,
+ u8 *mac_addr)
{
u32 macid_lo;
u32 macid_hi;
@@ -36,10 +63,8 @@ int cpsw_am33xx_cm_get_macid(struct device *dev, u16 offset,
int slave,
return PTR_ERR(syscon);
}
- regmap_read(syscon, AM33XX_CTRL_MAC_LO_REG(offset, slave),
- _lo);
- regmap_read(syscon, AM33XX_CTRL_MAC_HI_REG(offset, slave),
- _hi);
+ regmap_read(syscon, CTRL_MAC_LO_REG(offset, slave), _lo);
+ regmap_read(syscon, CTRL_MAC_HI_REG(offset, slave), _hi);
mac_addr[5] = (macid_lo >> 8) & 0xff;
mac_addr[4] = macid_lo & 0xff;
@@ -50,6 +75,21 @@ int cpsw_am33xx_cm_get_macid(struct device *dev, u16 offset,
int slave,
return 0;
}
-EXPORT_SYMBOL_GPL(cpsw_am33xx_cm_get_macid);
+
+int ti_cm_get_macid(struct device *dev, int slave, u8 *mac_addr)
+{
+ if (of_machine_is_compatible("ti,am33xx"))
+ return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
+
+ if (of_device_is_compatible(dev->of_node, "ti,am3517-emac"))
+ return davinci_emac_3517_get_macid(dev, 0x110, slave, mac_addr);
+
+ if (of_device_is_compatible(dev->of_node, "ti,dm816-emac"))
+ return cpsw_am33xx_cm_get_macid(dev, 0x30, slave, mac_addr);
+
+ dev_err(dev, "incompatible machine/device type for reading mac
address\n");
+ return -ENOENT;
+}
+EXPORT_SYMBOL_GPL(ti_cm_get_macid);
MODULE_LICENSE("GPL");
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index c670317..75584cc 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -2058,13 +2058,10 @@ no_phy_slave:
if (mac_addr) {
memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
} else {
- if (of_machine_is_compatible("ti,am33xx")) {
- ret = cpsw_am33xx_cm_get_macid(>dev,
- 0x630, i,
- slave_data->mac_addr);
- if (ret)
- return ret;
- }
+ ret = ti_cm_get_macid(>dev, i,
+ slave_data->mac_addr);
+ if (ret)
+ return ret;
}
if (data->dual_emac) {
if (of_property_read_u32(slave_node,
"dual_emac_res_vlan",
diff --git a/drivers/net/ethernet/ti/cpsw.h b/drivers/net/ethernet/ti/cpsw.h
index ca90efa..442a703 100644
--- a/drivers/net/ethernet/ti/cpsw.h
+++ b/driv
[PATCH v2 1/1] ARM: DTS: dra72-evm: remove cpsw gpio hogging and add mode-gpios
With the current implementation of GPIO hogging and with
gpio-pcf857x is built as module, ethernet doesn't work on boot
and doesn't throw any error/warning to user. Ethernet becomes
operational when inserting gpio-pcf857x module, even this time
there is no error/warning logs to user that ethernet is
operational.
When using with NFS rootfs and gpio-pcf857x as module, board
doesn't boot as it doesn't get any ip address and doesn't throw
any error/warning. To over come this, now cpsw driver tries to
get mode-gpios. When gpio-pcf857x is built as module it will
throw error, so that user can decide either to built in
gpio-pcf857x to continue with nfs boot or choose alternate rootfs
filesystem like sd/ramdisk.
When using mmc/ramdisk as root fs, cpsw will probe defer and
re-probes again when gpio-pcf857x module is inserted and ethernet
becomes operational.
Signed-off-by: Mugunthan V N <mugunthan...@ti.com>
---
The driver patch is applied to net-next branch (also present in
linux-next) with commit: '1d147ccbfc35 ("drivers: net: cpsw: Add
support to drive gpios for ethernet to be functional")
Tested on DRA72x EVM, logs [1] and pushed a branch [2] for testing
[1]: http://pastebin.ubuntu.com/12514591/
[2]: git://git.ti.com/~mugunthanvnm/ti-linux-kernel/linux.git
cpsw-mode-gpios-dt
Changes from initial version:
* Modified the commit message to add more information
---
arch/arm/boot/dts/dra72-evm.dts | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 6f6bd98..a12c6f4 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -353,12 +353,6 @@
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
-
- cpsw_sel_s0 {
- gpio-hog;
- gpios = <4 GPIO_ACTIVE_HIGH>;
- output-low;
- };
};
};
@@ -590,6 +584,7 @@
pinctrl-0 = <_default>;
pinctrl-1 = <_sleep>;
slaves = <1>;
+ mode-gpios = <_gpio_21 4 GPIO_ACTIVE_HIGH>;
};
_emac0 {
--
2.6.0.rc2.10.gf4d9753
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Re: [PATCH 1/1] ARM: DTS: dra72-evm: remove cpsw gpio hogging and add select-slave-gpio
On Monday 21 September 2015 01:34 PM, Mugunthan V N wrote: > Since GPIO hogging fails to through error when booting with > gpio-pcf857x as module and NFS root filesystem. So by having > mode-gpio, it throw error to user so that the used can make > gpio-pcf857x as inbuilt for NFS. When using mmc/ramdisk as root > fs, cpsw will probe defer and re-probes again when gpio-pcf857x > module is inserted and ethernet becomes operational. > > Signed-off-by: Mugunthan V N <mugunthan...@ti.com> There is some typo error. Will submit a v2 ASAP Regards Mugunthan V N -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[net-next PATCH v3] drivers: net: cpsw: Add support to drive gpios for ethernet to be functional
In DRA72x EVM, by default slave 1 is connected to the onboard
phy, but slave 2 pins are also muxed with video input module
which is controlled by pcf857x gpio and currently to select slave
0 to connect to phy gpio hogging is used, but with
omap2plus_defconfig the pcf857x gpio is built as module. So when
using NFS on DRA72x EVM, board doesn't boot as gpio hogging do
not set proper gpio state to connect slave 0 to phy as it is
built as module and you do not see any errors for not setting
gpio and just mentions dhcp reply not got.
To solve this issue, introducing "mode-gpios" in DT when gpio
based muxing is required. This will throw a warning when gpio
get fails and returns probe defer. When gpio-pcf857x module is
installed, cpsw probes again and ethernet becomes functional.
Verified this on DRA72x with pcf as module and ramdisk.
Signed-off-by: Mugunthan V N <mugunthan...@ti.com>
---
Changes from v2:
* Used mode-gpios, so that the driver is generic enough to handle
multiple gpios
This patch is tested on DRA72x, Logs [1] and pushed a branch [2]
[1]: http://pastebin.ubuntu.com/12306224/
[2]: git://git.ti.com/~mugunthanvnm/ti-linux-kernel/linux.git
cpsw-gpio-optional-v3
---
Documentation/devicetree/bindings/net/cpsw.txt | 7 +++
drivers/net/ethernet/ti/cpsw.c | 9 +
2 files changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/cpsw.txt
b/Documentation/devicetree/bindings/net/cpsw.txt
index a9df21a..676ecf6 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -30,6 +30,13 @@ Optional properties:
- dual_emac: Specifies Switch to act as Dual EMAC
- syscon : Phandle to the system control device node, which is
the control module device of the am33x
+- mode-gpios : Should be added if one/multiple gpio lines are
+ required to be driven so that cpsw data lines
+ can be connected to the phy via selective mux.
+ For example in dra72x-evm, pcf gpio has to be
+ driven low so that cpsw slave 0 and phy data
+ lines are connected via mux.
+
Slave Properties:
Required properties:
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 8fc90f1..c670317 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -2207,6 +2208,7 @@ static int cpsw_probe(struct platform_device *pdev)
void __iomem*ss_regs;
struct resource *res, *ss_res;
const struct of_device_id *of_id;
+ struct gpio_descs *mode;
u32 slave_offset, sliver_offset, slave_size;
int ret = 0, i;
int irq;
@@ -2232,6 +2234,13 @@ static int cpsw_probe(struct platform_device *pdev)
goto clean_ndev_ret;
}
+ mode = devm_gpiod_get_array_optional(>dev, "mode", GPIOD_OUT_LOW);
+ if (IS_ERR(mode)) {
+ ret = PTR_ERR(mode);
+ dev_err(>dev, "gpio request failed, ret %d\n", ret);
+ goto clean_ndev_ret;
+ }
+
/*
* This may be required here for child devices.
*/
--
2.6.0.rc0.24.gec371ff
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[net-next PATCH v2] drivers: net: cpsw: Add support to make gpio drive which slave connected to phy
In DRA72x EVM, by default slave 1 is connected to the onboard
phy, but slave 2 pins are also muxed with video input module
which is controlled by pcf857x gpio and currently to select slave
0 to connect to phy gpio hogging is used, but with
omap2plus_defconfig the pcf857x gpio is built as module. So when
using NFS on DRA72x EVM, board doesn't boot as gpio hogging do
not set proper gpio state to connect slave 0 to phy as it is
built as module and you do not see any errors for not setting
gpio and just mentions dhcp reply not got.
To solve this issue, introducing "mode-gpio" in DT when gpio
based muxing is required. This will throw a warning when gpio
get fails and returns probe defer. When gpio-pcf857x module is
installed, cpsw probes again and ethernet becomes functional.
Verified this on DRA72x with pcf as module and ramdisk.
Signed-off-by: Mugunthan V N <mugunthan...@ti.com>
---
Changes from initial version:
* Updated the gpio dt naming to be more generic.
This patch is texted on DRA72x, Logs [1] and pushed a branch [2]
[1]: http://pastebin.ubuntu.com/12260767/
[2]: git://git.ti.com/~mugunthanvnm/ti-linux-kernel/linux.git
cpsw-gpio-optional-v2
---
Documentation/devicetree/bindings/net/cpsw.txt | 7 +++
drivers/net/ethernet/ti/cpsw.c | 9 +
2 files changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/cpsw.txt
b/Documentation/devicetree/bindings/net/cpsw.txt
index 33fe846..dfe3e0b 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -26,6 +26,13 @@ Optional properties:
- dual_emac: Specifies Switch to act as Dual EMAC
- syscon : Phandle to the system control device node, which is
the control module device of the am33x
+- mode-gpio: Should be added if a gpio line is required to
+ be driven so that cpsw data lines can be
+ connected to the phy via selective mux. For
+ example in dra72x-evm, pcf gpio has to be
+ driven low so that cpsw slave 0 and phy
+ data lines are connected via mux.
+
Slave Properties:
Required properties:
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 8fc90f1..90ae3f9 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -2207,6 +2208,7 @@ static int cpsw_probe(struct platform_device *pdev)
void __iomem*ss_regs;
struct resource *res, *ss_res;
const struct of_device_id *of_id;
+ struct gpio_desc*mode;
u32 slave_offset, sliver_offset, slave_size;
int ret = 0, i;
int irq;
@@ -2232,6 +2234,13 @@ static int cpsw_probe(struct platform_device *pdev)
goto clean_ndev_ret;
}
+ mode = devm_gpiod_get_optional(>dev, "mode", GPIOD_OUT_LOW);
+ if (IS_ERR(mode)) {
+ ret = PTR_ERR(mode);
+ dev_err(>dev, "gpio request failed, ret %d\n", ret);
+ goto clean_ndev_ret;
+ }
+
/*
* This may be required here for child devices.
*/
--
2.5.1.522.g7aa67f6
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Re: [net-next PATCH] drivers: net: cpsw: Add support to make gpio drive which slave connected to phy
On Tuesday 01 September 2015 09:06 PM, Tony Lindgren wrote: > * Mugunthan V N <mugunthan...@ti.com> [150901 04:28]: >> --- a/Documentation/devicetree/bindings/net/cpsw.txt >> +++ b/Documentation/devicetree/bindings/net/cpsw.txt >> @@ -26,6 +26,9 @@ Optional properties: >> - dual_emac : Specifies Switch to act as Dual EMAC >> - syscon: Phandle to the system control device node, which is >>the control module device of the am33x >> +- select-slave-gpio : Should be added if a gpio line is required to >> + select which slave is connected to phy >> + > > How about using something more generic here for the name? > Something like mode-gpios? > Yeah, agreed, for DRA72x it is used for connecting to phy, if some other board wanted to drive a GPIO for something else we can use this node to drive GPIO. Will submit a v2 with name change Regards Mugunthan V N -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: DTS: dra72-evm: remove cpsw gpio hogging and add select-slave-gpio
Since GPIO hogging fails to through error when booting with
gpio-pcf857x as module and NFS root filesystem. So by having
select-slave-gpio, it throw error to user so that the used can
make gpio-pcf857x as inbuilt for NFS. When using mmc/ramdisk as
root fs, cpsw will probe defer and re-probes again when
gpio-pcf857x module is inserted and ethernet becomes operational.
Signed-off-by: Mugunthan V N <mugunthan...@ti.com>
---
This patch depends on driver changes [1] and tested on DRA72x, logs [2]
[1]: http://patchwork.ozlabs.org/patch/512783/
[2]: http://pastebin.ubuntu.com/12244652/
---
arch/arm/boot/dts/dra72-evm.dts | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index be9a89b..96d1bd3 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -343,12 +343,6 @@
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
-
- cpsw_sel_s0 {
- gpio-hog;
- gpios = <4 GPIO_ACTIVE_HIGH>;
- output-low;
- };
};
};
@@ -578,6 +572,7 @@
pinctrl-0 = <_default>;
pinctrl-1 = <_sleep>;
slaves = <1>;
+ select-slave-gpio = <_gpio_21 4 GPIO_ACTIVE_HIGH>;
};
_emac0 {
--
2.5.0.474.g3a9835b
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[net-next PATCH] drivers: net: cpsw: Add support to make gpio drive which slave connected to phy
In DRA72x EVM, by default slave 1 is connected to the onboard
phy, but slave 2 pins are also muxed with video input module
which is controlled by pcf857x gpio and currently to select slave
0 to connect to phy gpio hogging is used, but with
omap2plus_defconfig the pcf857x gpio is built as module. So when
using NFS on DRA72x EVM, board doesn't boot as gpio hogging do
not set proper gpio state to connect slave 0 to phy as it is
built as module and you do not see any errors for not setting
gpio and just mentions dhcp reply not got.
To solve this issue, introducing "select-slave-gpio" in DT when
gpio based muxing is required. This will through a warning when
vgpio get fails and returns probe defer. When gpio-pcf857x module
is installed, cpsw probes again and ethernet becomes functional.
Verified this on DRA72x with pcf as module and ramdisk [1]
Signed-off-by: Mugunthan V N <mugunthan...@ti.com>
---
This patch is texted on DRA72x, Logs [1] and pushed a branch [2]
[1]: http://pastebin.ubuntu.com/12244652/
[2]: git://git.ti.com/~mugunthanvnm/ti-linux-kernel/linux.git cpsw-gpio-optional
---
Documentation/devicetree/bindings/net/cpsw.txt | 3 +++
drivers/net/ethernet/ti/cpsw.c | 10 ++
2 files changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/cpsw.txt
b/Documentation/devicetree/bindings/net/cpsw.txt
index 33fe846..cb693aa 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -26,6 +26,9 @@ Optional properties:
- dual_emac: Specifies Switch to act as Dual EMAC
- syscon : Phandle to the system control device node, which is
the control module device of the am33x
+- select-slave-gpio: Should be added if a gpio line is required to
+ select which slave is connected to phy
+
Slave Properties:
Required properties:
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 8fc90f1..ce965ad 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -2207,6 +2208,7 @@ static int cpsw_probe(struct platform_device *pdev)
void __iomem*ss_regs;
struct resource *res, *ss_res;
const struct of_device_id *of_id;
+ struct gpio_desc*select_slave;
u32 slave_offset, sliver_offset, slave_size;
int ret = 0, i;
int irq;
@@ -2232,6 +2234,14 @@ static int cpsw_probe(struct platform_device *pdev)
goto clean_ndev_ret;
}
+ select_slave = devm_gpiod_get_optional(>dev, "select-slave",
+ GPIOD_OUT_LOW);
+ if (IS_ERR(select_slave)) {
+ ret = PTR_ERR(select_slave);
+ dev_err(>dev, "gpio request failed, ret %d\n", ret);
+ goto clean_ndev_ret;
+ }
+
/*
* This may be required here for child devices.
*/
--
2.5.0.474.g3a9835b
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[PATCH] Documentation: DT: cpsw: document missing compatible
CPSW driver has multiple compatibles for errata implentations but not
documented, add necessary documentation.
Signed-off-by: Mugunthan V N <mugunthan...@ti.com>
---
The compatibles are added in the commit 7da1160002f1 ('drivers:
net: cpsw: add am335x errata workarround for interrutps') which
is present in linux-next/master
---
Documentation/devicetree/bindings/net/cpsw.txt | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/cpsw.txt
b/Documentation/devicetree/bindings/net/cpsw.txt
index 33fe846..a9df21a 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -2,7 +2,11 @@ TI SoC Ethernet Switch Controller Device Tree Bindings
--
Required properties:
-- compatible : Should be "ti,cpsw"
+- compatible : Should be one of the below:-
+ "ti,cpsw" for backward compatible
+ "ti,am335x-cpsw" for AM335x controllers
+ "ti,am4372-cpsw" for AM437x controllers
+ "ti,dra7-cpsw" for DRA7x controllers
- reg : physical base address and size of the cpsw
registers map
- interrupts : property with a value describing the interrupt
--
2.5.0.474.g3a9835b
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Re: [net-next PATCH 1/3] drivers: net: cpsw: add am335x errata workarround for interrutps
On Monday 24 August 2015 03:34 PM, Sekhar Nori wrote:
Hi Mugunthan,
On Wednesday 12 August 2015 03:22 PM, Mugunthan V N wrote:
+static const struct of_device_id cpsw_of_mtable[] = {
+ { .compatible = ti,cpsw, .data = cpsw_devtype[CPSW], },
+ { .compatible = ti,am335x-cpsw, .data = cpsw_devtype[AM335X_CPSW], },
+ { .compatible = ti,am4372-cpsw, .data = cpsw_devtype[AM4372_CPSW], },
+ { .compatible = ti,dra7-cpsw, .data = cpsw_devtype[DRA7_CPSW], },
I do not see documentation added for these compatibles. Since the series
is already applied, can you send additional patches adding documentation?
Will submit a patch ASAP
Regards
Mugunthan V N
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[net-next PATCH 2/3] ARM: dts: dra7: update cpsw compatible
CPSW driver has been updated with compatibles for enabling errata
workarounds. So updating cpsw compatibles.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 8f1e25b..b4fdd10 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1398,7 +1398,7 @@
};
mac: ethernet@4a10 {
- compatible = ti,cpsw;
+ compatible = ti,dra7-cpsw,ti,cpsw;
ti,hwmods = gmac;
clocks = dpll_gmac_ck, gmac_gmii_ref_clk_div;
clock-names = fck, cpts;
--
2.5.0.234.gefc8a62
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[net-next PATCH 1/3] drivers: net: cpsw: add am335x errata workarround for interrutps
As per Am335x Errata [1] Advisory 1.0.9, The CPSW C0_TX_PEND and
C0_RX_PEND interrupt outputs provide a single transmit interrupt
that combines transmit channel interrupts TXPEND[7:0] and a
single receive interrupt that combines receive channel interrupts
RXPEND[7:0]. The TXPEND[0] and RXPEND[0] interrupt outputs are
connected to the ARM Cortex-A8 interrupt controller (INTC) rather
than the C0_TX_PEND and C0_RX_PEND interrupt outputs. So even
though CPSW interrupt is cleared by writing appropriate values to
EOI register the interrupt is not cleared in IRQ controller. So
interrupt is still pending and CPU is struck in ISR, the
workaround is to disable the interrupts in ARM irq controller.
[1] http://www.ti.com/lit/er/sprz360f/sprz360f.pdf
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
drivers/net/ethernet/ti/cpsw.c | 83 +++---
1 file changed, 77 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 3b81b39..8fc90f1 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -387,6 +387,9 @@ struct cpsw_priv {
struct cpsw_ale *ale;
boolrx_pause;
booltx_pause;
+ boolquirk_irq;
+ boolrx_irq_disabled;
+ booltx_irq_disabled;
/* snapshot of IRQ numbers */
u32 irqs_table[4];
u32 num_irqs;
@@ -755,6 +758,11 @@ static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
writel(0, priv-wr_regs-tx_en);
cpdma_ctlr_eoi(priv-dma, CPDMA_EOI_TX);
+ if (priv-quirk_irq) {
+ disable_irq_nosync(priv-irqs_table[1]);
+ priv-tx_irq_disabled = true;
+ }
+
napi_schedule(priv-napi_tx);
return IRQ_HANDLED;
}
@@ -766,6 +774,11 @@ static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
cpdma_ctlr_eoi(priv-dma, CPDMA_EOI_RX);
writel(0, priv-wr_regs-rx_en);
+ if (priv-quirk_irq) {
+ disable_irq_nosync(priv-irqs_table[0]);
+ priv-rx_irq_disabled = true;
+ }
+
napi_schedule(priv-napi_rx);
return IRQ_HANDLED;
}
@@ -779,6 +792,10 @@ static int cpsw_tx_poll(struct napi_struct *napi_tx, int
budget)
if (num_tx budget) {
napi_complete(napi_tx);
writel(0xff, priv-wr_regs-tx_en);
+ if (priv-quirk_irq priv-tx_irq_disabled) {
+ priv-tx_irq_disabled = false;
+ enable_irq(priv-irqs_table[1]);
+ }
}
if (num_tx)
@@ -796,6 +813,10 @@ static int cpsw_rx_poll(struct napi_struct *napi_rx, int
budget)
if (num_rx budget) {
napi_complete(napi_rx);
writel(0xff, priv-wr_regs-rx_en);
+ if (priv-quirk_irq priv-rx_irq_disabled) {
+ priv-rx_irq_disabled = false;
+ enable_irq(priv-irqs_table[0]);
+ }
}
if (num_rx)
@@ -1267,6 +1288,16 @@ static int cpsw_ndo_open(struct net_device *ndev)
napi_enable(priv_sl0-napi_rx);
napi_enable(priv_sl0-napi_tx);
+ if (priv_sl0-tx_irq_disabled) {
+ priv_sl0-tx_irq_disabled = false;
+ enable_irq(priv-irqs_table[1]);
+ }
+
+ if (priv_sl0-rx_irq_disabled) {
+ priv_sl0-rx_irq_disabled = false;
+ enable_irq(priv-irqs_table[0]);
+ }
+
if (WARN_ON(!priv-data.rx_descs))
priv-data.rx_descs = 128;
@@ -2128,6 +2159,44 @@ static int cpsw_probe_dual_emac(struct platform_device
*pdev,
return ret;
}
+#define CPSW_QUIRK_IRQ BIT(0)
+
+static struct platform_device_id cpsw_devtype[] = {
+ {
+ /* keep it for existing comaptibles */
+ .name = cpsw,
+ .driver_data = CPSW_QUIRK_IRQ,
+ }, {
+ .name = am335x-cpsw,
+ .driver_data = CPSW_QUIRK_IRQ,
+ }, {
+ .name = am4372-cpsw,
+ .driver_data = 0,
+ }, {
+ .name = dra7-cpsw,
+ .driver_data = 0,
+ }, {
+ /* sentinel */
+ }
+};
+MODULE_DEVICE_TABLE(platform, cpsw_devtype);
+
+enum ti_cpsw_type {
+ CPSW = 0,
+ AM335X_CPSW,
+ AM4372_CPSW,
+ DRA7_CPSW,
+};
+
+static const struct of_device_id cpsw_of_mtable[] = {
+ { .compatible = ti,cpsw, .data = cpsw_devtype[CPSW], },
+ { .compatible = ti,am335x-cpsw, .data = cpsw_devtype[AM335X_CPSW], },
+ { .compatible = ti,am4372-cpsw, .data = cpsw_devtype[AM4372_CPSW], },
+ { .compatible = ti,dra7-cpsw, .data = cpsw_devtype[DRA7_CPSW], },
+ { /* sentinel
[net-next PATCH 3/3] ARM: dts: am33xx: update cpsw compatible
CPSW driver has been updated with compatibles for enabling errata
workarounds. So updating cpsw compatibles.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/am33xx.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 21fcc44..8b59c86 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -700,7 +700,7 @@
};
mac: ethernet@4a10 {
- compatible = ti,cpsw;
+ compatible = ti,am335x-cpsw,ti,cpsw;
ti,hwmods = cpgmac0;
clocks = cpsw_125mhz_gclk, cpsw_cpts_rft_clk;
clock-names = fck, cpts;
--
2.5.0.234.gefc8a62
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[net-next PATCH 0/3] Add AM335x PG1.0 CPSW errata workaround
With commit 870915feabdc (drivers: net: cpsw: remove disable_irq/enable_irq as irq can be masked from cpsw itself), CPSW on AM335x beagle bone white is broken as there is a errata for AM335x PG1.0. This patch series implements the workaround by disabling the interrupts from ARM IRQ controller for AM335x SoC in addition to the masking of interrupts in CPSW. Mugunthan V N (3): drivers: net: cpsw: add am335x errata workarround for interrutps ARM: dts: dra7: update cpsw compatible ARM: dts: am33xx: update cpsw compatible arch/arm/boot/dts/am33xx.dtsi | 2 +- arch/arm/boot/dts/dra7.dtsi| 2 +- drivers/net/ethernet/ti/cpsw.c | 83 +++--- 3 files changed, 79 insertions(+), 8 deletions(-) -- 2.5.0.234.gefc8a62 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/4] ARM: omap2plus_defconfig: enable support for TI CPTS
On Wednesday 08 July 2015 08:57 PM, Sekhar Nori wrote: CPTS module of CPSW IP enables timestamp synchronization using PTP. Enable CPTS feature of CPSW driver. Available on AM335x, AM437x and DRA7x SoCs. Signed-off-by: Sekhar Nori nsek...@ti.com Acked-by: Mugunthan V N mugunthan...@ti.com Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/1] arm: dts: am43xx-clock: Add qspi clock node.
From: Sourav Poddar sourav.pod...@ti.com
Add clock node for qspi controller driver on am437x.
Cc: Keerthy j-keer...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/am4372.dtsi| 2 ++
arch/arm/boot/dts/am43xx-clocks.dtsi | 8
2 files changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 649e7b9..8ab7831 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -903,6 +903,8 @@
#address-cells = 1;
#size-cells = 0;
ti,hwmods = qspi;
+ clocks = qspi_fclk;
+ clock-names = fck;
interrupts = 0 138 0x4;
num-cs = 4;
status = disabled;
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi
b/arch/arm/boot/dts/am43xx-clocks.dtsi
index cc88728..1506585 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -763,4 +763,12 @@
ti,bit-shift = 8;
reg = 0x8a68;
};
+
+ qspi_fclk: qspi_fclk {
+ #clock-cells = 0;
+ compatible = ti,fixed-factor-clock;
+ clocks = dpll_per_m2_div4_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
};
--
2.4.2.387.gf86f31a
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[PATCH 1/1] ARM: dts: DRA72: switch to cpsw slave0 for ethernet
From: Vignesh R vigne...@ti.com
On DRA72 EVM, cpsw slave1 is muxed with VIN2A, hence switch to cpsw
slave0 for ethernet. Add gpio hog entry to pcf_gpio_21 in order to
select cpsw slave0.
Signed-off-by: Vignesh R vigne...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/dra72-evm.dts | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index ce0390f..b05d123 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -274,6 +274,12 @@
interrupts = 11 IRQ_TYPE_EDGE_FALLING;
interrupt-controller;
#interrupt-cells = 2;
+
+ cpsw_sel_s0 {
+ gpio-hog;
+ gpios = 4 GPIO_ACTIVE_HIGH;
+ output-low;
+ };
};
};
@@ -481,9 +487,10 @@
pinctrl-names = default, sleep;
pinctrl-0 = cpsw_default;
pinctrl-1 = cpsw_sleep;
+ slaves = 1;
};
-cpsw_emac1 {
+cpsw_emac0 {
phy_id = davinci_mdio, 3;
phy-mode = rgmii;
};
@@ -492,7 +499,6 @@
pinctrl-names = default, sleep;
pinctrl-0 = davinci_mdio_default;
pinctrl-1 = davinci_mdio_sleep;
- active_slave = 1;
};
dcan1 {
--
2.4.2.387.gf86f31a
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Re: [PATCH 0/2] CLK: TI: add dpll_clksel_mac_clk node
On Thursday 18 June 2015 01:31 PM, Keerthy wrote: The series adds the missing clock node needed for cpsw. Keerthy (2): CLK: TI: add dpll_clksel_mac_clk node ARM: dts: am4372: Set the default clock rate for dpll_clksel_mac_clk clock arch/arm/boot/dts/am4372.dtsi| 7 +-- arch/arm/boot/dts/am43xx-clocks.dtsi | 9 + drivers/clk/ti/clk-43xx.c| 1 + 3 files changed, 15 insertions(+), 2 deletions(-) Tested-by: Mugunthan V N mugunthan...@ti.com Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [BUG?] drivers: net:ethernet: cpsw: add support for VLAN
On Thursday 23 April 2015 03:58 AM, Christoph Fritz wrote: Hi, has commit 3b72c2fe0c6bbec42e (drivers: net:ethernet: cpsw: add support for VLAN) introduced a bug by defining CPSW_VLAN_AWARE as BIT(1) instead of BIT(2)? +#define CPSW_VLAN_AWARE BIT(1) snip /* switch to vlan unaware mode */ - cpsw_ale_control_set(priv-ale, 0, ALE_VLAN_AWARE, 0); + cpsw_ale_control_set(priv-ale, priv-host_port, ALE_VLAN_AWARE, + CPSW_ALE_VLAN_AWARE); + control_reg = readl(priv-regs-control); + control_reg |= CPSW_VLAN_AWARE; + writel(control_reg, priv-regs-control); See TRM [1] page 1980 (14.5.1.2 CONTROL Register), there bit CPSW_VLAN_AWARE is number 2. I didn't do any tests, just stumbled upon. [1]: http://www.ti.com/lit/ug/spruh73l/spruh73l.pdf Its bug in TRM, will check with TRM team and update here. Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/1] ARM: dts: dra72-evm: Add qspi device
These add device tree entry for qspi device on dra72-evm.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
This patch is tested on linux-next and the boot logs is here [1]
[1] - http://pastebin.ubuntu.com/9783555/
---
arch/arm/boot/dts/dra72-evm.dts | 77 +
1 file changed, 77 insertions(+)
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 89085d0..cacddd7 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -121,6 +121,18 @@
0x418 (MUX_MODE15)/* wakeup0.off */
;
};
+
+ qspi1_pins: pinmux_qspi1_pins {
+ pinctrl-single,pins =
+ 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk
*/
+ 0x78 (PIN_INPUT | MUX_MODE1)/* gpmc_a14.qspi1_d3 */
+ 0x7c (PIN_INPUT | MUX_MODE1)/* gpmc_a15.qspi1_d2 */
+ 0x80 (PIN_INPUT | MUX_MODE1)/* gpmc_a16.qspi1_d1 */
+ 0x84 (PIN_INPUT | MUX_MODE1)/* gpmc_a17.qspi1_d0 */
+ 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk
*/
+ 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
+ ;
+ };
};
i2c1 {
@@ -461,3 +473,68 @@
pinctrl-0 = dcan1_pins_default;
pinctrl-1 = dcan1_pins_sleep;
};
+
+qspi {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = qspi1_pins;
+
+ spi-max-frequency = 4800;
+ m25p80@0 {
+ compatible = s25fl256s1;
+ spi-max-frequency = 4800;
+ reg = 0;
+ spi-tx-bus-width = 1;
+ spi-rx-bus-width = 4;
+ spi-cpol;
+ spi-cpha;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ /* MTD partition table.
+* The ROM checks the first four physical blocks
+* for a valid file to boot and the flash here is
+* 64KiB block size.
+*/
+ partition@0 {
+ label = QSPI.SPL;
+ reg = 0x 0x1;
+ };
+ partition@1 {
+ label = QSPI.SPL.backup1;
+ reg = 0x0001 0x0001;
+ };
+ partition@2 {
+ label = QSPI.SPL.backup2;
+ reg = 0x0002 0x0001;
+ };
+ partition@3 {
+ label = QSPI.SPL.backup3;
+ reg = 0x0003 0x0001;
+ };
+ partition@4 {
+ label = QSPI.u-boot;
+ reg = 0x0004 0x0010;
+ };
+ partition@5 {
+ label = QSPI.u-boot-spl-os;
+ reg = 0x0014 0x0008;
+ };
+ partition@6 {
+ label = QSPI.u-boot-env;
+ reg = 0x001c 0x0001;
+ };
+ partition@7 {
+ label = QSPI.u-boot-env.backup1;
+ reg = 0x001d 0x001;
+ };
+ partition@8 {
+ label = QSPI.kernel;
+ reg = 0x001e 0x080;
+ };
+ partition@9 {
+ label = QSPI.file-system;
+ reg = 0x009e 0x0162;
+ };
+ };
+};
--
2.2.1.62.g3f15098
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Re: [patch-net-next v2 3/3] net: ethernet: cpsw: don't requests IRQs we don't use
On Wednesday 14 January 2015 10:28 PM, Felipe Balbi wrote: CPSW never uses RX_THRESHOLD or MISC interrupts. In fact, they are always kept masked in their appropriate IRQ Enable register. Instead of allocating an IRQ that never fires, it's best to remove that code altogether and let future patches implement it if anybody needs those. Signed-off-by: Felipe Balbi ba...@ti.com Instead of introducing dummy ISR in previous patch and then removing in this patch, both can be squashed into a single patch. Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/1] ARM: dts: dra7-evm: fix qspi device tree partition size
64KiB is allocated for qspi dtb partition which is not
sufficient, so updating the partition table size to 512KiB
for device tree partition.
This also aligns the QSPI partition definitions between
kernel and U-Boot.
Fixes: dc2dd5b8 (ARM: dts: dra7: Add qspi device)
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
This patch is tested on Linux next and the boot logs at [1]
[1] - http://pastebin.ubuntu.com/9567672/
---
arch/arm/boot/dts/dra7-evm.dts | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 736092b..235d001 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -499,23 +499,23 @@
};
partition@5 {
label = QSPI.u-boot-spl-os;
- reg = 0x0014 0x0001;
+ reg = 0x0014 0x0008;
};
partition@6 {
label = QSPI.u-boot-env;
- reg = 0x0015 0x0001;
+ reg = 0x001c 0x0001;
};
partition@7 {
label = QSPI.u-boot-env.backup1;
- reg = 0x0016 0x001;
+ reg = 0x001d 0x001;
};
partition@8 {
label = QSPI.kernel;
- reg = 0x0017 0x080;
+ reg = 0x001e 0x080;
};
partition@9 {
label = QSPI.file-system;
- reg = 0x0097 0x0169;
+ reg = 0x009e 0x0162;
};
};
};
--
2.2.1.62.g3f15098
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Re: [PATCH v2] drivers: net : cpsw: Update Kconfig for CPSW
On Thursday 04 December 2014 10:24 AM, Lokesh Vutla wrote: CPSW is present in AM33xx, AM43xx, DRA7xx. Updating the Kconfig to depend on ARCH_OMAP2PLUS instead of listing all SoC's. Signed-off-by: Lokesh Vutla lokeshvu...@ti.com Acked-by: Mugunthan V N mugunthan...@ti.com Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 0/2] Add DRA7xx CPSW Ethernet support in Device Tree
Tony On Monday 03 November 2014 09:57 PM, Felipe Balbi wrote: On Tue, Oct 21, 2014 at 12:22:23PM -0500, Nishanth Menon wrote: On 15:37-20141021, Mugunthan V N wrote: Nishanth On Tuesday 21 October 2014 03:30 PM, Mugunthan V N wrote: Adding device tree entry for CPSW to make it work in Dual EMAC mode. These patches were tested with DRA7 hwmod patches on top of linux-next. Patches are tested on top of Nishanth's PM tree for v3.17 [1] and pushed my tree to [2]. Did a boot test with CPSW and ping test with suspend/resume, the boot logs on DRA7xx EVM are posted at [3] [1] git://github.com/nmenon/linux-2.6-playground.git testing/v3.17/cpu-idle-suspend-dra7-omap5-framework [2] git://git.ti.com/~mugunthanvnm/ti-linux-kernel/linux.git v3.17/dra7-evm-cpsw-v3 [3] http://pastebin.ubuntu.com/8613072/ Changes from v2: * Changed pinctrl comments to hold mode0-name.mode-selected-name * Changes slave numbers in the pinctrl comments * Added cpsw and cpts clocks I have not added support for dra72x-evm as it has only slave no 2 pinned out and having issues with bringing up the interface, need some more time to submit the patch, in the mean time I have submitted dra7-evm support only so that people can use dra7-evm on linux-next. Quickly tested as well: http://slexy.org/raw/s2vISJxYrR Please feel free to add: Tested-by: Nishanth Menon n...@ti.com Acked-by: Nishanth Menon n...@ti.com I've used these patches with X15 (DRA7xx-based yet-to-be-released board) with v3.18-rc2. Tested-by: Felipe Balbi ba...@ti.com Ping on this Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/1] ARM: dts: dra72x-evm: Enable CPSW and MDIO
Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active and
sleep states and enable them in board evm dts file.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
Adding device tree entry for CPSW to make it work in Switch mode.
Patches are tested on top of Nishanth's PM tree for v3.17 [1] and pushed
my tree to [2].
Did a boot test with CPSW and ping test with suspend/resume, the boot logs
on DRA72x EVM are posted at [3]
This patch depends on the DRA7xx CPSW support patch series [4] and one driver
patch (47276fc drivers: net:cpsw: fix probe_dt when only slave 1 is pinned out)
which is already present in linux-next
[1] git://github.com/nmenon/linux-2.6-playground.git
testing/v3.17/cpu-idle-suspend-dra7-omap5-framework
[2] git://git.ti.com/~mugunthanvnm/ti-linux-kernel/linux.git
for-v3.19/dra72-evm-cpsw
[3] http://pastebin.ubuntu.com/8800549/
[4] http://comments.gmane.org/gmane.linux.kernel/1810171
---
arch/arm/boot/dts/dra72-evm.dts | 73 +
1 file changed, 73 insertions(+)
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 5147023..b8ebf89 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -22,3 +22,76 @@
uart1 {
status = okay;
};
+
+dra7_pmx_core {
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins =
+ /* Slave 2 */
+ 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc
*/
+ 0x19c (PIN_OUTPUT | MUX_MODE3) /*
vin2a_d13.rgmii1_tctl */
+ 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3
*/
+ 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2
*/
+ 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1
*/
+ 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0
*/
+ 0x1b0 (PIN_INPUT | MUX_MODE3) /*
vin2a_d18.rgmii1_rclk */
+ 0x1b4 (PIN_INPUT | MUX_MODE3) /*
vin2a_d19.rgmii1_rctl */
+ 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3
*/
+ 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2
*/
+ 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1
*/
+ 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0
*/
+ ;
+
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins =
+ /* Slave 2 */
+ 0x198 (MUX_MODE15)
+ 0x19c (MUX_MODE15)
+ 0x1a0 (MUX_MODE15)
+ 0x1a4 (MUX_MODE15)
+ 0x1a8 (MUX_MODE15)
+ 0x1ac (MUX_MODE15)
+ 0x1b0 (MUX_MODE15)
+ 0x1b4 (MUX_MODE15)
+ 0x1b8 (MUX_MODE15)
+ 0x1bc (MUX_MODE15)
+ 0x1c0 (MUX_MODE15)
+ 0x1c4 (MUX_MODE15)
+ ;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins =
+ /* MDIO */
+ 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /*
mdio_d.mdio_d */
+ 0x240 (PIN_INPUT_PULLUP | MUX_MODE0)/*
mdio_clk.mdio_clk */
+ ;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins =
+ 0x23c (MUX_MODE15)
+ 0x240 (MUX_MODE15)
+ ;
+ };
+};
+
+mac {
+ status = okay;
+ pinctrl-names = default, sleep;
+ pinctrl-0 = cpsw_default;
+ pinctrl-1 = cpsw_sleep;
+};
+
+cpsw_emac1 {
+ phy_id = davinci_mdio, 3;
+ phy-mode = rgmii;
+};
+
+davinci_mdio {
+ pinctrl-names = default, sleep;
+ pinctrl-0 = davinci_mdio_default;
+ pinctrl-1 = davinci_mdio_sleep;
+ active_slave = 1;
+};
--
2.1.2.484.g13da0fc
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[PATCH v3 0/2] Add DRA7xx CPSW Ethernet support in Device Tree
Adding device tree entry for CPSW to make it work in Dual EMAC mode. These patches were tested with DRA7 hwmod patches on top of linux-next. Patches are tested on top of Nishanth's PM tree for v3.17 [1] and pushed my tree to [2]. Did a boot test with CPSW and ping test with suspend/resume, the boot logs on DRA7xx EVM are posted at [3] [1] git://github.com/nmenon/linux-2.6-playground.git testing/v3.17/cpu-idle-suspend-dra7-omap5-framework [2] git://git.ti.com/~mugunthanvnm/ti-linux-kernel/linux.git v3.17/dra7-evm-cpsw-v3 [3] http://pastebin.ubuntu.com/8613072/ Changes from v2: * Changed pinctrl comments to hold mode0-name.mode-selected-name * Changes slave numbers in the pinctrl comments * Added cpsw and cpts clocks Changes from initial version: * Dropped patch for pinoff states * Changed pinoff state to mode15 Mugunthan V N (2): ARM: dts: dra7: Add CPSW and MDIO module nodes for dra7 ARM: dts: dra7-evm: Enable CPSW and MDIO for dra7xx EVM arch/arm/boot/dts/dra7-evm.dts | 106 + arch/arm/boot/dts/dra7.dtsi| 61 2 files changed, 167 insertions(+) -- 2.1.2.484.g13da0fc -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 2/2] ARM: dts: dra7-evm: Enable CPSW and MDIO for dra7xx EVM
Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active and
sleep states and enable them in board evm dts file.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 106 +
1 file changed, 106 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 518a6c0..3be2630 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -171,6 +171,86 @@
0xd0(PIN_OUTPUT | MUX_MODE0)/*
gpmc_be0n_cle */
;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins =
+ /* Slave 1 */
+ 0x250 (PIN_OUTPUT | MUX_MODE0) /*
rgmii0_txc.rgmii0_txc */
+ 0x254 (PIN_OUTPUT | MUX_MODE0) /*
rgmii0_txctl.rgmii0_txctl */
+ 0x258 (PIN_OUTPUT | MUX_MODE0) /*
rgmii0_td3.rgmii0_txd3 */
+ 0x25c (PIN_OUTPUT | MUX_MODE0) /*
rgmii0_txd2.rgmii0_txd2 */
+ 0x260 (PIN_OUTPUT | MUX_MODE0) /*
rgmii0_txd1.rgmii0_txd1 */
+ 0x264 (PIN_OUTPUT | MUX_MODE0) /*
rgmii0_txd0.rgmii0_txd0 */
+ 0x268 (PIN_INPUT | MUX_MODE0) /*
rgmii0_rxc.rgmii0_rxc */
+ 0x26c (PIN_INPUT | MUX_MODE0) /*
rgmii0_rxctl.rgmii0_rxctl */
+ 0x270 (PIN_INPUT | MUX_MODE0) /*
rgmii0_rxd3.rgmii0_rxd3 */
+ 0x274 (PIN_INPUT | MUX_MODE0) /*
rgmii0_rxd2.rgmii0_rxd2 */
+ 0x278 (PIN_INPUT | MUX_MODE0) /*
rgmii0_rxd1.rgmii0_rxd1 */
+ 0x27c (PIN_INPUT | MUX_MODE0) /*
rgmii0_rxd0.rgmii0_rxd0 */
+
+ /* Slave 2 */
+ 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc
*/
+ 0x19c (PIN_OUTPUT | MUX_MODE3) /*
vin2a_d13.rgmii1_tctl */
+ 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3
*/
+ 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2
*/
+ 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1
*/
+ 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0
*/
+ 0x1b0 (PIN_INPUT | MUX_MODE3) /*
vin2a_d18.rgmii1_rclk */
+ 0x1b4 (PIN_INPUT | MUX_MODE3) /*
vin2a_d19.rgmii1_rctl */
+ 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3
*/
+ 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2
*/
+ 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1
*/
+ 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0
*/
+ ;
+
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins =
+ /* Slave 1 */
+ 0x250 (MUX_MODE15)
+ 0x254 (MUX_MODE15)
+ 0x258 (MUX_MODE15)
+ 0x25c (MUX_MODE15)
+ 0x260 (MUX_MODE15)
+ 0x264 (MUX_MODE15)
+ 0x268 (MUX_MODE15)
+ 0x26c (MUX_MODE15)
+ 0x270 (MUX_MODE15)
+ 0x274 (MUX_MODE15)
+ 0x278 (MUX_MODE15)
+ 0x27c (MUX_MODE15)
+
+ /* Slave 2 */
+ 0x198 (MUX_MODE15)
+ 0x19c (MUX_MODE15)
+ 0x1a0 (MUX_MODE15)
+ 0x1a4 (MUX_MODE15)
+ 0x1a8 (MUX_MODE15)
+ 0x1ac (MUX_MODE15)
+ 0x1b0 (MUX_MODE15)
+ 0x1b4 (MUX_MODE15)
+ 0x1b8 (MUX_MODE15)
+ 0x1bc (MUX_MODE15)
+ 0x1c0 (MUX_MODE15)
+ 0x1c4 (MUX_MODE15)
+ ;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins =
+ 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /*
mdio_d.mdio_d */
+ 0x240 (PIN_INPUT_PULLUP | MUX_MODE0)/*
mdio_clk.mdio_clk */
+ ;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins =
+ 0x23c (MUX_MODE15)
+ 0x240 (MUX_MODE15)
+ ;
+ };
+
};
i2c1 {
@@ -528,3 +608,29 @@
ti,no-reset-on-init;
ti,no-idle-on-init;
};
+
+mac {
+ status = okay;
+ pinctrl-names = default, sleep;
+ pinctrl-0 = cpsw_default;
+ pinctrl-1 = cpsw_sleep;
+ dual_emac;
+};
+
+cpsw_emac0 {
+ phy_id = davinci_mdio, 2;
+ phy-mode = rgmii;
+ dual_emac_res_vlan = 1;
+};
+
+cpsw_emac1 {
+ phy_id = davinci_mdio, 3;
+ phy
[PATCH v3 1/2] ARM: dts: dra7: Add CPSW and MDIO module nodes for dra7
Add CPSW and MDIO related device tree data for DRA7XX and made as status
disabled. Phy-id, pinmux for active and sleep state needs to be added in
board dts files and enable the CPSW device.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 61 +
1 file changed, 61 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 9cc9843..56f5275 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -34,6 +34,8 @@
serial3 = uart4;
serial4 = uart5;
serial5 = uart6;
+ ethernet0 = cpsw_emac0;
+ ethernet1 = cpsw_emac1;
};
timer {
@@ -1265,6 +1267,65 @@
ti,irqs-skip = 10 133 139 140;
ti,irqs-safe-map = 0;
};
+
+ mac: ethernet@4a10 {
+ compatible = ti,cpsw;
+ ti,hwmods = gmac;
+ clocks = dpll_gmac_ck, gmac_gmii_ref_clk_div;
+ clock-names = fck, cpts;
+ cpdma_channels = 8;
+ ale_entries = 1024;
+ bd_ram_size = 0x2000;
+ no_bd_ram = 0;
+ rx_descs = 64;
+ mac_control = 0x20;
+ slaves = 2;
+ active_slave = 0;
+ cpts_clock_mult = 0x8000;
+ cpts_clock_shift = 29;
+ reg = 0x48484000 0x1000
+ 0x48485200 0x2E00;
+ #address-cells = 1;
+ #size-cells = 1;
+ /*
+* rx_thresh_pend
+* rx_pend
+* tx_pend
+* misc_pend
+*/
+ interrupts = GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH;
+ ranges;
+ status = disabled;
+
+ davinci_mdio: mdio@48485000 {
+ compatible = ti,davinci_mdio;
+ #address-cells = 1;
+ #size-cells = 0;
+ ti,hwmods = davinci_mdio;
+ bus_freq = 100;
+ reg = 0x48485000 0x100;
+ };
+
+ cpsw_emac0: slave@48480200 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ cpsw_emac1: slave@48480300 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ phy_sel: cpsw-phy-sel@4a002554 {
+ compatible = ti,dra7xx-cpsw-phy-sel;
+ reg= 0x4a002554 0x4;
+ reg-names = gmii-sel;
+ };
+ };
+
};
};
--
2.1.2.484.g13da0fc
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Re: [PATCH v3 0/2] Add DRA7xx CPSW Ethernet support in Device Tree
Nishanth On Tuesday 21 October 2014 03:30 PM, Mugunthan V N wrote: Adding device tree entry for CPSW to make it work in Dual EMAC mode. These patches were tested with DRA7 hwmod patches on top of linux-next. Patches are tested on top of Nishanth's PM tree for v3.17 [1] and pushed my tree to [2]. Did a boot test with CPSW and ping test with suspend/resume, the boot logs on DRA7xx EVM are posted at [3] [1] git://github.com/nmenon/linux-2.6-playground.git testing/v3.17/cpu-idle-suspend-dra7-omap5-framework [2] git://git.ti.com/~mugunthanvnm/ti-linux-kernel/linux.git v3.17/dra7-evm-cpsw-v3 [3] http://pastebin.ubuntu.com/8613072/ Changes from v2: * Changed pinctrl comments to hold mode0-name.mode-selected-name * Changes slave numbers in the pinctrl comments * Added cpsw and cpts clocks I have not added support for dra72x-evm as it has only slave no 2 pinned out and having issues with bringing up the interface, need some more time to submit the patch, in the mean time I have submitted dra7-evm support only so that people can use dra7-evm on linux-next. Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: CPSW bug with AM437x SK
On Friday 03 October 2014 06:34 AM, Felipe Balbi wrote: [ 261.177168] [c0648d48] (skb_panic) from [c0565edc] (skb_put+0x5c/0x60) [ 261.184415] [c0565edc] (skb_put) from [c0605aac] (unix_stream_sendmsg+0x164/0x390) [ 261.192712] [c0605aac] (unix_stream_sendmsg) from [c055b364] (sock_aio_write+0xdc/0xfc) [ 261.201475] [c055b364] (sock_aio_write) from [c014c42c] (do_sync_write+0x8c/0xb4) [ 261.209697] [c014c42c] (do_sync_write) from [c014cf70] (vfs_write+0x118/0x1c0) [ 261.217652] [c014cf70] (vfs_write) from [c014d564] (SyS_write+0x4c/0xa0) [ 261.225054] [c014d564] (SyS_write) from [c000ed40] (ret_fast_syscall+0x0/0x48) [ 261.232988] Code: e58d4008 e58de00c e59f0008 ebfff48e (e7f001f2) [ 261.239378] ---[ end trace d64258d586f40104 ]--- The BT shows that the warn came from a unix socket interface, so this cannot be a CPSW bug, its a bug in unix socket. Are you not seeing this issue with file system in any other media? I will try to reproduce this locally with my AM437x EVMsk. Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RESEND v6 0/7] net: cpsw: Support for am335x chip MACIDs
On Monday 29 September 2014 12:23 PM, Markus Pargmann wrote: Hi, Another resend of this series to add the netdev list. This series adds support to the cpsw driver to read the MACIDs of the am335x chip and use them as fallback. These addresses are only used if there are no mac addresses in the devicetree, for example set by a bootloader. Best regards, Markus Markus Pargmann (7): DT doc: net: cpsw mac-address is optional net: cpsw: Add missing return value net: cpsw: header, Add missing include net: cpsw: Replace pr_err by dev_err net: cpsw: Add am33xx MACID readout am33xx: define syscon control module device node arm: dts: am33xx, Add syscon phandle to cpsw node Documentation/devicetree/bindings/net/cpsw.txt | 6 +++- arch/arm/boot/dts/am33xx.dtsi | 6 drivers/net/ethernet/ti/Kconfig| 2 ++ drivers/net/ethernet/ti/cpsw.c | 45 -- drivers/net/ethernet/ti/cpsw.h | 1 + 5 files changed, 57 insertions(+), 3 deletions(-) Acked-by: Mugunthan V N mugunthan...@gmail.com Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/2] ARM: dts: dra7: Add CPSW and MDIO module nodes for dra7
On Friday 12 September 2014 02:59 AM, Lennart Sorensen wrote: I have the mac but I don't want to use both ports on the 2 port switch. In fact in our case ethernet1 is a pru_eth interface. Can a board dts override the alias for ethernet1 or is that a syntax error? I don't think I tried that yet. You can override it in board dts file Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/2] ARM: dts: dra7-evm: Enable CPSW and MDIO for dra7xx EVM
On Wednesday 10 September 2014 07:26 PM, Nishanth Menon wrote:
On 09/10/2014 08:37 AM, Mugunthan V N wrote:
Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active and
sleep states and enable them in board evm dts file.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 107
+
1 file changed, 107 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 50f8022..e5c4e33 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -151,6 +151,87 @@
0xd0(PIN_OUTPUT | MUX_MODE0)/*
gpmc_be0n_cle */
;
};
+
+cpsw_default: cpsw_default {
+pinctrl-single,pins =
+/* Slave 1 */
+0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */
+0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */
+0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */
+0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */
+0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */
+0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */
+0x268 (PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */
+0x26c (PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */
+0x270 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */
+0x274 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */
+0x278 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */
+0x27c (PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */
Cant we do this based on emac0 and emac1?
Cant because CPSW is a single ethernet device and dual EMAC is just a
feature done by register two network device.
+
+/* Slave 2 */
+0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
NAK. reason comment style - we use the style:
/* mode0_name.mode3_name */
Will fix this in next version
+0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
+0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
+0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
+0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
+0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
+0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
+0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
+0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
+0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
+0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
+0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
+;
+
+};
+
+cpsw_sleep: cpsw_sleep {
+pinctrl-single,pins =
+/* Slave 1 */
+0x250 (MUX_MODE15)
+0x254 (MUX_MODE15)
+0x258 (MUX_MODE15)
+0x25c (MUX_MODE15)
+0x260 (MUX_MODE15)
+0x264 (MUX_MODE15)
+0x268 (MUX_MODE15)
+0x26c (MUX_MODE15)
+0x270 (MUX_MODE15)
+0x274 (MUX_MODE15)
+0x278 (MUX_MODE15)
+0x27c (MUX_MODE15)
+
+/* Slave 1 */
^^ Slave 1?
Will fix this in next version
+0x198 (MUX_MODE15)
+0x19c (MUX_MODE15)
+0x1a0 (MUX_MODE15)
+0x1a4 (MUX_MODE15)
+0x1a8 (MUX_MODE15)
+0x1ac (MUX_MODE15)
+0x1b0 (MUX_MODE15)
+0x1b4 (MUX_MODE15)
+0x1b8 (MUX_MODE15)
+0x1bc (MUX_MODE15)
+0x1c0 (MUX_MODE15)
+0x1c4 (MUX_MODE15)
+;
+};
+
+davinci_mdio_default: davinci_mdio_default {
+pinctrl-single,pins =
+/* MDIO */
^^ you can drop the comment. it is redundant.
Will remove this in next version
+0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_data */
+0x240 (PIN_INPUT_PULLUP | MUX_MODE0)/* mdio_clk */
+;
+};
+
+davinci_mdio_sleep: davinci_mdio_sleep {
+pinctrl-single,pins =
+0x23c (MUX_MODE15)
+0x240 (MUX_MODE15)
+;
+};
+
};
i2c1 {
@@ -504,3 +585,29 @@
usb2_phy2 {
phy-supply = ldousb_reg;
};
+
+mac {
+status = okay;
+pinctrl-names = default, sleep;
+pinctrl-0 = cpsw_default;
+pinctrl-1 = cpsw_sleep;
+dual_emac;
+};
+
+cpsw_emac0 {
+phy_id = davinci_mdio, 2;
+phy-mode = rgmii
Re: [PATCH v2 0/2] Add DRA7xx CPSW Ethernet support in Device Tree
On Wednesday 10 September 2014 07:31 PM, Nishanth Menon wrote: On 09/10/2014 08:37 AM, Mugunthan V N wrote: Adding device tree entry for CPSW to make it work in Dual EMAC mode. These patches were tested with DRA7 hwmod patches on top of linux-next. Patches are tested on top of Nishanth's PM tree for v3.17 [1] and pushed my tree to [2]. Did a boot test with CPSW and ping test with suspend/resume, the boot logs on DRA7xx EVM are posted at [3] [1] git://github.com/nmenon/linux-2.6-playground.git testing/v3.17/cpu-idle-suspend-dra7-omap5-framework [2] git://git.ti.com/~mugunthanvnm/ti-linux-kernel/linux.git v3.17/dra7-evm-cpsw [3] http://pastebin.ubuntu.com/8309289/ Changes from initial version: * Dropped patch for pinoff states * Changed pinoff state to mode15 Mugunthan V N (2): ARM: dts: dra7: Add CPSW and MDIO module nodes for dra7 ARM: dts: dra7-evm: Enable CPSW and MDIO for dra7xx EVM arch/arm/boot/dts/dra7-evm.dts | 107 + arch/arm/boot/dts/dra7.dtsi| 59 +++ 2 files changed, 166 insertions(+) I did apply these on Tony's omap-for-v3.18/dt 6e55426 Merge branch .. they do apply. However: why are we not sending dra72-evm.dts changes in the same series since we claim it to be dra7xx support? Will add dra72x support and submit the next version. Also, in your tests (http://pastebin.ubuntu.com/8309289/) echo -n 20/sys/kernel/debug/pm_debug/wakeup_timer_seconds ping 172.24.188.1 (or even better do a transfer of large file in background) echo mem /sys/power/state transfer/ping should resume seamlessly. (only thing you should be careful is that the server should not timeout for 20 second inactivity).. ping will resume seamlessly will try tftp and update on my next version submission. Will add ping test across suspend resume with both ports while posting my next version Regards Mugunthan V N It is a valid test to verify peripheral activity after resume, BUT, equally important is to verify suspend-resume in the middle of activity. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/2] ARM: dts: dra7: Add CPSW and MDIO module nodes for dra7
On Thursday 11 September 2014 07:08 AM, Lennart Sorensen wrote:
On Wed, Sep 10, 2014 at 07:07:26PM +0530, Mugunthan V N wrote:
Add CPSW and MDIO related device tree data for DRA7XX and made as status
disabled. Phy-id, pinmux for active and sleep state needs to be added in
board dts files and enable the CPSW device.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 59
+
1 file changed, 59 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d678152..8d79321 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -34,6 +34,8 @@
serial3 = uart4;
serial4 = uart5;
serial5 = uart6;
+ethernet0 = cpsw_emac0;
+ethernet1 = cpsw_emac1;
};
timer {
@@ -1262,6 +1264,63 @@
ti,irqs-skip = 10 133 139 140;
ti,irqs-safe-map = 0;
};
+
+mac: ethernet@4a10 {
+compatible = ti,cpsw;
+ti,hwmods = gmac;
+cpdma_channels = 8;
+ale_entries = 1024;
+bd_ram_size = 0x2000;
+no_bd_ram = 0;
+rx_descs = 64;
+mac_control = 0x20;
+slaves = 2;
How am I supposed to override this in the board dtb when my board only
uses 1 slave?
slaves = 1;
+active_slave = 0;
+cpts_clock_mult = 0x8000;
+cpts_clock_shift = 29;
+reg = 0x48484000 0x1000
+ 0x48485200 0x2E00;
+#address-cells = 1;
+#size-cells = 1;
+/*
+ * rx_thresh_pend
+ * rx_pend
+ * tx_pend
+ * misc_pend
+ */
+interrupts = GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH,
+ GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH,
+ GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH,
+ GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH;
+ranges;
+status = disabled;
+
+davinci_mdio: mdio@48485000 {
+compatible = ti,davinci_mdio;
+#address-cells = 1;
+#size-cells = 0;
+ti,hwmods = davinci_mdio;
+bus_freq = 100;
+reg = 0x48485000 0x100;
+};
+
+cpsw_emac0: slave@48480200 {
+/* Filled in by U-Boot */
+mac-address = [ 00 00 00 00 00 00 ];
+};
+
+cpsw_emac1: slave@48480300 {
+/* Filled in by U-Boot */
+mac-address = [ 00 00 00 00 00 00 ];
+};
Should I then be setting this to disabled from my board file? Or does
the disabled for the ethernet overall take care of that?
overall disable takes care of this
+phy_sel: cpsw-phy-sel@4a002554 {
+compatible = ti,dra7xx-cpsw-phy-sel;
+reg= 0x4a002554 0x4;
+reg-names = gmii-sel;
+};
I guess the board file would have to disable that too (we won't have a
phy given we are connecting to a switch chip).
Will add disabled in next version.
Regards
Mugunthan V N
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Re: [PATCH v2 1/2] ARM: dts: dra7: Add CPSW and MDIO module nodes for dra7
On Wednesday 10 September 2014 07:20 PM, Nishanth Menon wrote:
On 09/10/2014 08:37 AM, Mugunthan V N wrote:
Add CPSW and MDIO related device tree data for DRA7XX and made as status
disabled. Phy-id, pinmux for active and sleep state needs to be added in
board dts files and enable the CPSW device.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 59
+
1 file changed, 59 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d678152..8d79321 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -34,6 +34,8 @@
serial3 = uart4;
serial4 = uart5;
serial5 = uart6;
+ethernet0 = cpsw_emac0;
+ethernet1 = cpsw_emac1;
should this rather be in board dts?
This should be here as the MAC address is filled in uboot with ethernet0
and ethernet1, moving this to dts, the ordering of the ethernet can go
for toss when they have other ethernet devices other than cpsw.
};
timer {
@@ -1262,6 +1264,63 @@
ti,irqs-skip = 10 133 139 140;
ti,irqs-safe-map = 0;
};
+
+mac: ethernet@4a10 {
+compatible = ti,cpsw;
+ti,hwmods = gmac;
+cpdma_channels = 8;
+ale_entries = 1024;
+bd_ram_size = 0x2000;
+no_bd_ram = 0;
+rx_descs = 64;
+mac_control = 0x20;
+slaves = 2;
+active_slave = 0;
+cpts_clock_mult = 0x8000;
+cpts_clock_shift = 29;
+reg = 0x48484000 0x1000
+ 0x48485200 0x2E00;
+#address-cells = 1;
+#size-cells = 1;
+/*
+ * rx_thresh_pend
+ * rx_pend
+ * tx_pend
+ * misc_pend
+ */
+interrupts = GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH,
+ GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH,
+ GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH,
+ GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH;
+ranges;
+status = disabled;
+
+davinci_mdio: mdio@48485000 {
+compatible = ti,davinci_mdio;
+#address-cells = 1;
+#size-cells = 0;
+ti,hwmods = davinci_mdio;
+bus_freq = 100;
+reg = 0x48485000 0x100;
+};
+
+cpsw_emac0: slave@48480200 {
+/* Filled in by U-Boot */
+mac-address = [ 00 00 00 00 00 00 ];
should be disabled? what about platforms that do not have both emac ports?
the mac node is already disabled, so platforms which doesn't have emac
should not enable this which in-turn emac node will be disabled.
Regards
Mugunthan V N
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[PATCH v2 0/2] Add DRA7xx CPSW Ethernet support in Device Tree
Adding device tree entry for CPSW to make it work in Dual EMAC mode. These patches were tested with DRA7 hwmod patches on top of linux-next. Patches are tested on top of Nishanth's PM tree for v3.17 [1] and pushed my tree to [2]. Did a boot test with CPSW and ping test with suspend/resume, the boot logs on DRA7xx EVM are posted at [3] [1] git://github.com/nmenon/linux-2.6-playground.git testing/v3.17/cpu-idle-suspend-dra7-omap5-framework [2] git://git.ti.com/~mugunthanvnm/ti-linux-kernel/linux.git v3.17/dra7-evm-cpsw [3] http://pastebin.ubuntu.com/8309289/ Changes from initial version: * Dropped patch for pinoff states * Changed pinoff state to mode15 Mugunthan V N (2): ARM: dts: dra7: Add CPSW and MDIO module nodes for dra7 ARM: dts: dra7-evm: Enable CPSW and MDIO for dra7xx EVM arch/arm/boot/dts/dra7-evm.dts | 107 + arch/arm/boot/dts/dra7.dtsi| 59 +++ 2 files changed, 166 insertions(+) -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/2] ARM: dts: dra7-evm: Enable CPSW and MDIO for dra7xx EVM
Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active and
sleep states and enable them in board evm dts file.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 107 +
1 file changed, 107 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 50f8022..e5c4e33 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -151,6 +151,87 @@
0xd0(PIN_OUTPUT | MUX_MODE0)/*
gpmc_be0n_cle */
;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins =
+ /* Slave 1 */
+ 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */
+ 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */
+ 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */
+ 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */
+ 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */
+ 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */
+ 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */
+ 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */
+ 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */
+ 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */
+ 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */
+ 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */
+
+ /* Slave 2 */
+ 0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
+ 0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
+ 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
+ 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
+ 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
+ 0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
+ 0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
+ 0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
+ 0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
+ 0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
+ 0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
+ 0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
+ ;
+
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins =
+ /* Slave 1 */
+ 0x250 (MUX_MODE15)
+ 0x254 (MUX_MODE15)
+ 0x258 (MUX_MODE15)
+ 0x25c (MUX_MODE15)
+ 0x260 (MUX_MODE15)
+ 0x264 (MUX_MODE15)
+ 0x268 (MUX_MODE15)
+ 0x26c (MUX_MODE15)
+ 0x270 (MUX_MODE15)
+ 0x274 (MUX_MODE15)
+ 0x278 (MUX_MODE15)
+ 0x27c (MUX_MODE15)
+
+ /* Slave 1 */
+ 0x198 (MUX_MODE15)
+ 0x19c (MUX_MODE15)
+ 0x1a0 (MUX_MODE15)
+ 0x1a4 (MUX_MODE15)
+ 0x1a8 (MUX_MODE15)
+ 0x1ac (MUX_MODE15)
+ 0x1b0 (MUX_MODE15)
+ 0x1b4 (MUX_MODE15)
+ 0x1b8 (MUX_MODE15)
+ 0x1bc (MUX_MODE15)
+ 0x1c0 (MUX_MODE15)
+ 0x1c4 (MUX_MODE15)
+ ;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins =
+ /* MDIO */
+ 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_data */
+ 0x240 (PIN_INPUT_PULLUP | MUX_MODE0)/* mdio_clk */
+ ;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins =
+ 0x23c (MUX_MODE15)
+ 0x240 (MUX_MODE15)
+ ;
+ };
+
};
i2c1 {
@@ -504,3 +585,29 @@
usb2_phy2 {
phy-supply = ldousb_reg;
};
+
+mac {
+ status = okay;
+ pinctrl-names = default, sleep;
+ pinctrl-0 = cpsw_default;
+ pinctrl-1 = cpsw_sleep;
+ dual_emac;
+};
+
+cpsw_emac0 {
+ phy_id = davinci_mdio, 2;
+ phy-mode = rgmii;
+ dual_emac_res_vlan = 1;
+};
+
+cpsw_emac1 {
+ phy_id = davinci_mdio, 3;
+ phy-mode = rgmii;
+ dual_emac_res_vlan = 2;
+};
+
+davinci_mdio {
+ pinctrl-names = default, sleep;
+ pinctrl-0 = davinci_mdio_default;
+ pinctrl-1 = davinci_mdio_sleep;
+};
--
2.1.0
--
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[PATCH v2 1/2] ARM: dts: dra7: Add CPSW and MDIO module nodes for dra7
Add CPSW and MDIO related device tree data for DRA7XX and made as status
disabled. Phy-id, pinmux for active and sleep state needs to be added in
board dts files and enable the CPSW device.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 59 +
1 file changed, 59 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d678152..8d79321 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -34,6 +34,8 @@
serial3 = uart4;
serial4 = uart5;
serial5 = uart6;
+ ethernet0 = cpsw_emac0;
+ ethernet1 = cpsw_emac1;
};
timer {
@@ -1262,6 +1264,63 @@
ti,irqs-skip = 10 133 139 140;
ti,irqs-safe-map = 0;
};
+
+ mac: ethernet@4a10 {
+ compatible = ti,cpsw;
+ ti,hwmods = gmac;
+ cpdma_channels = 8;
+ ale_entries = 1024;
+ bd_ram_size = 0x2000;
+ no_bd_ram = 0;
+ rx_descs = 64;
+ mac_control = 0x20;
+ slaves = 2;
+ active_slave = 0;
+ cpts_clock_mult = 0x8000;
+ cpts_clock_shift = 29;
+ reg = 0x48484000 0x1000
+ 0x48485200 0x2E00;
+ #address-cells = 1;
+ #size-cells = 1;
+ /*
+* rx_thresh_pend
+* rx_pend
+* tx_pend
+* misc_pend
+*/
+ interrupts = GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH;
+ ranges;
+ status = disabled;
+
+ davinci_mdio: mdio@48485000 {
+ compatible = ti,davinci_mdio;
+ #address-cells = 1;
+ #size-cells = 0;
+ ti,hwmods = davinci_mdio;
+ bus_freq = 100;
+ reg = 0x48485000 0x100;
+ };
+
+ cpsw_emac0: slave@48480200 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ cpsw_emac1: slave@48480300 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ phy_sel: cpsw-phy-sel@4a002554 {
+ compatible = ti,dra7xx-cpsw-phy-sel;
+ reg= 0x4a002554 0x4;
+ reg-names = gmii-sel;
+ };
+ };
+
};
};
--
2.1.0
--
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Re: [resend PATCH 1/3] pinctrl: dra7: dt-bindings: add pin off modes for dra7 SoC
On Tuesday 09 September 2014 01:02 AM, Nishanth Menon wrote: A) There is no OFF mode on DRA7. in sleep state use mode 15 (gated). B) when using this for wakeup - use pinctrl wakeup handling to do the wakeup. Will drop this patch and use mode 15 in sleep mode and submit v2 patch series Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [resend PATCH 0/3] Add DRA7xx CPSW Ethernet support in Device Tree
On Tuesday 09 September 2014 01:04 AM, Nishanth Menon wrote: On 00:49-20140909, Mugunthan V N wrote: Adding device tree entry for CPSW to make it work in Dual EMAC mode. These patches were tested with DRA7 hwmod patches on top of linux-next. The patches were already reviewed [1] and has been waiting for cross bar and hwmod to be pulled in. Now since all dependent patches has already pulled in, so reposting the patches again. Patches are tested on linux-next, the boot logs on DRA7xx EVM [2] [1] https://lkml.org/lkml/2014/5/13/89 [2] http://slexy.org/view/s2YqO0Wj9b Sorry this is now blocked inside TI. could you explain the testing done for sleep state? did you attempt sleep mode before testing this? I have not tested sleep mode, just tested boot and ping test. Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [resend PATCH 0/3] Add DRA7xx CPSW Ethernet support in Device Tree
On Tuesday 09 September 2014 05:45 PM, Nishanth Menon wrote: On Tue, Sep 9, 2014 at 6:29 AM, Mugunthan V N mugunthan...@ti.com wrote: Sorry this is now blocked inside TI. could you explain the testing done for sleep state? did you attempt sleep mode before testing this? I have not tested sleep mode, just tested boot and ping test. I must NAK then for the reason that this is a patch that is just build tested and is not tested for the feature it claims to introduce. Is suspend/resume supported in mainline, i was not able to test it. root@dra7xx-evm:~# echo mem /sys/power/state -sh: echo: write error: Invalid argument I was not able to use rtc wake also as the rtc device is not created. Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[resend PATCH 0/3] Add DRA7xx CPSW Ethernet support in Device Tree
Adding device tree entry for CPSW to make it work in Dual EMAC mode. These patches were tested with DRA7 hwmod patches on top of linux-next. The patches were already reviewed [1] and has been waiting for cross bar and hwmod to be pulled in. Now since all dependent patches has already pulled in, so reposting the patches again. Patches are tested on linux-next, the boot logs on DRA7xx EVM [2] [1] https://lkml.org/lkml/2014/5/13/89 [2] http://slexy.org/view/s2YqO0Wj9b Mugunthan V N (3): pinctrl: dra7: dt-bindings: add pin off modes for dra7 SoC arm/dts: dra7xx: Add CPSW and MDIO module nodes for dra7xx arm/dts: dra7xx: Enable CPSW and MDIO for dra7xx EVM arch/arm/boot/dts/dra7-evm.dts| 107 ++ arch/arm/boot/dts/dra7.dtsi | 59 + include/dt-bindings/pinctrl/dra.h | 8 +++ 3 files changed, 174 insertions(+) -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[resend PATCH 3/3] arm/dts: dra7xx: Enable CPSW and MDIO for dra7xx EVM
Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active and
sleep states and enable them in board evm dts file.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 107 +
1 file changed, 107 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index fd96ced..57e69c4 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -151,6 +151,87 @@
0xd0(PIN_OUTPUT | MUX_MODE0)/*
gpmc_be0n_cle */
;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins =
+ /* Slave 1 */
+ 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */
+ 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */
+ 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */
+ 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */
+ 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */
+ 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */
+ 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */
+ 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */
+ 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */
+ 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */
+ 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */
+ 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */
+
+ /* Slave 2 */
+ 0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
+ 0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
+ 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
+ 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
+ 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
+ 0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
+ 0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
+ 0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
+ 0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
+ 0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
+ 0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
+ 0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
+ ;
+
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins =
+ /* Slave 1 */
+ 0x250 (PIN_OFF_NONE)
+ 0x254 (PIN_OFF_NONE)
+ 0x258 (PIN_OFF_NONE)
+ 0x25c (PIN_OFF_NONE)
+ 0x260 (PIN_OFF_NONE)
+ 0x264 (PIN_OFF_NONE)
+ 0x268 (PIN_OFF_NONE)
+ 0x26c (PIN_OFF_NONE)
+ 0x270 (PIN_OFF_NONE)
+ 0x274 (PIN_OFF_NONE)
+ 0x278 (PIN_OFF_NONE)
+ 0x27c (PIN_OFF_NONE)
+
+ /* Slave 1 */
+ 0x198 (PIN_OFF_NONE)
+ 0x19c (PIN_OFF_NONE)
+ 0x1a0 (PIN_OFF_NONE)
+ 0x1a4 (PIN_OFF_NONE)
+ 0x1a8 (PIN_OFF_NONE)
+ 0x1ac (PIN_OFF_NONE)
+ 0x1b0 (PIN_OFF_NONE)
+ 0x1b4 (PIN_OFF_NONE)
+ 0x1b8 (PIN_OFF_NONE)
+ 0x1bc (PIN_OFF_NONE)
+ 0x1c0 (PIN_OFF_NONE)
+ 0x1c4 (PIN_OFF_NONE)
+ ;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins =
+ /* MDIO */
+ 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_data */
+ 0x240 (PIN_INPUT_PULLUP | MUX_MODE0)/* mdio_clk */
+ ;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins =
+ 0x23c (PIN_OFF_NONE)
+ 0x240 (PIN_OFF_NONE)
+ ;
+ };
+
};
i2c1 {
@@ -503,3 +584,29 @@
usb2_phy2 {
phy-supply = ldousb_reg;
};
+
+mac {
+ status = okay;
+ pinctrl-names = default, sleep;
+ pinctrl-0 = cpsw_default;
+ pinctrl-1 = cpsw_sleep;
+ dual_emac;
+};
+
+cpsw_emac0 {
+ phy_id = davinci_mdio, 2;
+ phy-mode = rgmii;
+ dual_emac_res_vlan = 1;
+};
+
+cpsw_emac1 {
+ phy_id = davinci_mdio, 3;
+ phy-mode = rgmii;
+ dual_emac_res_vlan = 2;
+};
+
+davinci_mdio {
+ pinctrl-names = default, sleep;
+ pinctrl-0 = davinci_mdio_default;
+ pinctrl-1 = davinci_mdio_sleep;
+};
--
2.1.0
--
To unsubscribe from
[resend PATCH 1/3] pinctrl: dra7: dt-bindings: add pin off modes for dra7 SoC
Add pin off modes for dra7 SoC so that during module disable or suspend state it can help saving power Signed-off-by: Mugunthan V N mugunthan...@ti.com --- include/dt-bindings/pinctrl/dra.h | 8 1 file changed, 8 insertions(+) diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h index 002a285..a0ff2d0 100644 --- a/include/dt-bindings/pinctrl/dra.h +++ b/include/dt-bindings/pinctrl/dra.h @@ -46,5 +46,13 @@ #define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) #define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) +/* Off mode states */ +#define PIN_OFF_NONE 0 +#define PIN_OFF_OUTPUT_HIGH(OFF_EN | OFFOUT_EN | OFFOUT_VAL) +#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN) +#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFF_PULL_EN | OFF_PULL_UP) +#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN) +#define PIN_OFF_WAKEUPENABLE WAKEUP_EN + #endif -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[resend PATCH 0/3] Add DRA7xx CPSW Ethernet support in Device Tree
Adding device tree entry for CPSW to make it work in Dual EMAC mode. These patches were tested with DRA7 hwmod patches on top of linux-next. The patches were already reviewed [1] and has been waiting for cross bar and hwmod to be pulled in. Now since all dependent patches has already pulled in, so reposting the patches again. Patches are tested on linux-next, the boot logs on DRA7xx EVM [2] [1] https://lkml.org/lkml/2014/5/13/89 [2] http://slexy.org/view/s2YqO0Wj9b Mugunthan V N (3): pinctrl: dra7: dt-bindings: add pin off modes for dra7 SoC arm/dts: dra7xx: Add CPSW and MDIO module nodes for dra7xx arm/dts: dra7xx: Enable CPSW and MDIO for dra7xx EVM arch/arm/boot/dts/dra7-evm.dts| 107 ++ arch/arm/boot/dts/dra7.dtsi | 59 + include/dt-bindings/pinctrl/dra.h | 8 +++ 3 files changed, 174 insertions(+) -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[resend PATCH 2/3] arm/dts: dra7xx: Add CPSW and MDIO module nodes for dra7xx
Add CPSW and MDIO related device tree data for DRA7XX and made as status
disabled. Phy-id, pinmux for active and sleep state needs to be added in
board dts files and enable the CPSW device.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 59 +
1 file changed, 59 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index b6060d3..d588c1e 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -34,6 +34,8 @@
serial3 = uart4;
serial4 = uart5;
serial5 = uart6;
+ ethernet0 = cpsw_emac0;
+ ethernet1 = cpsw_emac1;
};
timer {
@@ -1134,6 +1136,63 @@
ti,irqs-skip = 10 133 139 140;
ti,irqs-safe-map = 0;
};
+
+ mac: ethernet@4a10 {
+ compatible = ti,cpsw;
+ ti,hwmods = gmac;
+ cpdma_channels = 8;
+ ale_entries = 1024;
+ bd_ram_size = 0x2000;
+ no_bd_ram = 0;
+ rx_descs = 64;
+ mac_control = 0x20;
+ slaves = 2;
+ active_slave = 0;
+ cpts_clock_mult = 0x8000;
+ cpts_clock_shift = 29;
+ reg = 0x48484000 0x1000
+ 0x48485200 0x2E00;
+ #address-cells = 1;
+ #size-cells = 1;
+ /*
+* rx_thresh_pend
+* rx_pend
+* tx_pend
+* misc_pend
+*/
+ interrupts = GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH;
+ ranges;
+ status = disabled;
+
+ davinci_mdio: mdio@48485000 {
+ compatible = ti,davinci_mdio;
+ #address-cells = 1;
+ #size-cells = 0;
+ ti,hwmods = davinci_mdio;
+ bus_freq = 100;
+ reg = 0x48485000 0x100;
+ };
+
+ cpsw_emac0: slave@48480200 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ cpsw_emac1: slave@48480300 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ phy_sel: cpsw-phy-sel@4a002554 {
+ compatible = ti,dra7xx-cpsw-phy-sel;
+ reg= 0x4a002554 0x4;
+ reg-names = gmii-sel;
+ };
+ };
+
};
};
--
2.1.0
--
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Re: [PATCH v4 5/7] net: cpsw: Add am33xx MACID readout
On Thursday 21 August 2014 11:21 AM, Markus Pargmann wrote:
This patch adds a function to get the MACIDs from the am33xx SoC
control module registers which hold unique vendor MACIDs. This is only
used if of_get_mac_address() fails to get a valid mac address.
Signed-off-by: Markus Pargmann m...@pengutronix.de
Reviewed-by: Wolfram Sang w...@the-dreams.de
Tested-by: Steven Rostedt rost...@goodmis.org
---
Documentation/devicetree/bindings/net/cpsw.txt | 4 +++
drivers/net/ethernet/ti/Kconfig| 2 ++
drivers/net/ethernet/ti/cpsw.c | 46
--
3 files changed, 50 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/cpsw.txt
b/Documentation/devicetree/bindings/net/cpsw.txt
index 107caf174a0e..33fe8462edf4 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -24,6 +24,8 @@ Optional properties:
- ti,hwmods : Must be cpgmac0
- no_bd_ram : Must be 0 or 1
- dual_emac : Specifies Switch to act as Dual EMAC
+- syscon : Phandle to the system control device node, which is
+ the control module device of the am33x
Slave Properties:
Required properties:
@@ -57,6 +59,7 @@ Examples:
active_slave = 0;
cpts_clock_mult = 0x8000;
cpts_clock_shift = 29;
+ syscon = cm;
cpsw_emac0: slave@0 {
phy_id = davinci_mdio, 0;
phy-mode = rgmii-txid;
@@ -85,6 +88,7 @@ Examples:
active_slave = 0;
cpts_clock_mult = 0x8000;
cpts_clock_shift = 29;
+ syscon = cm;
cpsw_emac0: slave@0 {
phy_id = davinci_mdio, 0;
phy-mode = rgmii-txid;
diff --git a/drivers/net/ethernet/ti/Kconfig b/drivers/net/ethernet/ti/Kconfig
index 1769700a6070..5d8cb7956113 100644
--- a/drivers/net/ethernet/ti/Kconfig
+++ b/drivers/net/ethernet/ti/Kconfig
@@ -62,6 +62,8 @@ config TI_CPSW
select TI_DAVINCI_CPDMA
select TI_DAVINCI_MDIO
select TI_CPSW_PHY_SEL
+ select MFD_SYSCON
+ select REGMAP
---help---
This driver supports TI's CPSW Ethernet Switch.
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 0bc2c2a2c236..aaf8a42f9633 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -33,6 +33,8 @@
#include linux/of_net.h
#include linux/of_device.h
#include linux/if_vlan.h
+#include linux/mfd/syscon.h
+#include linux/regmap.h
#include linux/pinctrl/consumer.h
@@ -1816,6 +1818,39 @@ static void cpsw_slave_init(struct cpsw_slave *slave,
struct cpsw_priv *priv,
slave-port_vlan = data-dual_emac_res_vlan;
}
+#define AM33XX_CTRL_MAC_LO_REG(id) (0x630 + 0x8 * id)
+#define AM33XX_CTRL_MAC_HI_REG(id) (0x630 + 0x8 * id + 0x4)
+
+static int cpsw_am33xx_cm_get_macid(struct device *dev, int slave,
+ u8 *mac_addr)
+{
+ u32 macid_lo;
+ u32 macid_hi;
+ struct regmap *syscon;
+
+ if (!of_machine_is_compatible(ti,am33xx))
+ return 0;
+
+ syscon = syscon_regmap_lookup_by_phandle(dev-of_node, syscon);
+ if (IS_ERR(syscon)) {
+ if (PTR_ERR(syscon) == -ENODEV)
+ return 0;
+ return PTR_ERR(syscon);
+ }
+
+ regmap_read(syscon, AM33XX_CTRL_MAC_LO_REG(slave), macid_lo);
+ regmap_read(syscon, AM33XX_CTRL_MAC_HI_REG(slave), macid_hi);
+
+ mac_addr[5] = (macid_lo 8) 0xff;
+ mac_addr[4] = macid_lo 0xff;
+ mac_addr[3] = (macid_hi 24) 0xff;
+ mac_addr[2] = (macid_hi 16) 0xff;
+ mac_addr[1] = (macid_hi 8) 0xff;
+ mac_addr[0] = macid_hi 0xff;
+
+ return 0;
+}
+
static int cpsw_probe_dt(struct cpsw_platform_data *data,
struct platform_device *pdev)
{
@@ -1928,8 +1963,15 @@ static int cpsw_probe_dt(struct cpsw_platform_data
*data,
PHY_ID_FMT, mdio-name, phyid);
mac_addr = of_get_mac_address(slave_node);
- if (mac_addr)
- memcpy(slave_data-mac_addr, mac_addr, ETH_ALEN);
+ if (mac_addr) {
+ memcpy(slave_data-mac_addr, mac_addr,
+ ETH_ALEN);
Alignment should match open parenthesis
+ } else {
+ ret = cpsw_am33xx_cm_get_macid(pdev-dev, i,
+ slave_data-mac_addr);
+ if (ret)
+ return ret;
+ }
slave_data-phy_if = of_get_phy_mode(slave_node);
if (slave_data-phy_if 0) {
--
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Re: [PATCH v3 5/7] net: cpsw: Add am33xx MACID readout
On Tuesday 19 August 2014 02:20 PM, Markus Pargmann wrote: Hi, On Tue, Aug 19, 2014 at 12:50:59AM +0200, Javier Martinez Canillas wrote: Hello Mugunthan, On Mon, Aug 18, 2014 at 9:58 PM, Mugunthan V N mugunthan...@ti.com wrote: Thus, for this patchset, as is: Tested-by: Steven Rostedt rost...@goodmis.org This will fail for DRA7xx not in AM33xx cpsw_am33xx_cm_get_macid() checks for of_machine_is_compatible(ti,am33xx) and returns 0 if the machine is not an am33xx. cpsw_probe_dt() only propagates the return value if is not 0 so this patch does not change the semantics for other SoCs besides am33xx. Yes, this patch is only about the am33xx. I don't have the DRA7xx hardware so I am not able to test on that hardware. Mugunthan, perhaps you can supply some followup patches for DRA7xx. I will check on this thursday and update. Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 5/7] net: cpsw: Add am33xx MACID readout
On Saturday 16 August 2014 08:48 PM, Markus Pargmann wrote: + mac_addr[5] = (macid_lo 8) 0xff; + mac_addr[4] = macid_lo 0xff; + mac_addr[3] = (macid_hi 24) 0xff; + mac_addr[2] = (macid_hi 16) 0xff; + mac_addr[1] = (macid_hi 8) 0xff; + mac_addr[0] = macid_hi 0xff; + This will fail incase of DRA74x and DRA72x platforms, please check for u-boot src for parsing logic as TRM is not out yet. Below is the actual code for DRA7 platforms for MAC address parsing mac_addr[0] = (mac_hi 0xFF) 16; mac_addr[1] = (mac_hi 0xFF00) 8; mac_addr[2] = mac_hi 0xFF; mac_addr[3] = (mac_lo 0xFF) 16; mac_addr[4] = (mac_lo 0xFF00) 8; mac_addr[5] = mac_lo 0xFF; Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 5/7] net: cpsw: Add am33xx MACID readout
On Tuesday 19 August 2014 01:11 AM, Steven Rostedt wrote: On Mon, 18 Aug 2014 23:54:26 +0530 Mugunthan V N mugunthan...@ti.com wrote: On Saturday 16 August 2014 08:48 PM, Markus Pargmann wrote: + mac_addr[5] = (macid_lo 8) 0xff; + mac_addr[4] = macid_lo 0xff; + mac_addr[3] = (macid_hi 24) 0xff; + mac_addr[2] = (macid_hi 16) 0xff; + mac_addr[1] = (macid_hi 8) 0xff; + mac_addr[0] = macid_hi 0xff; + This will fail incase of DRA74x and DRA72x platforms, please check for u-boot src for parsing logic as TRM is not out yet. Below is the actual code for DRA7 platforms for MAC address parsing mac_addr[0] = (mac_hi 0xFF) 16; mac_addr[1] = (mac_hi 0xFF00) 8; mac_addr[2] = mac_hi 0xFF; mac_addr[3] = (mac_lo 0xFF) 16; mac_addr[4] = (mac_lo 0xFF00) 8; mac_addr[5] = mac_lo 0xFF; But this fails with my beaglebone white. I tested Markus's patches and it came up with the same ethaddr that U-Boot had. From U-Boot: ethaddr=d4:94:a1:8b:ec:78 With Markus's changes: eth0 Link encap:Ethernet HWaddr D4:94:A1:8B:EC:78 But when I changed the code to match what you wrote, I got this: eth0 Link encap:Ethernet HWaddr CE:5A:8B:0E:44:45 but it also gave me: cpsw 4a10.ethernet: Random MACID = ce:5a:8b:0e:44:45 which means it failed the valid mac test. Here's how I implemented your change: #if 1 mac_addr[0] = (macid_hi 0xFF) 16; mac_addr[1] = (macid_hi 0xFF00) 8; mac_addr[2] = macid_hi 0xFF; mac_addr[3] = (macid_lo 0xFF) 16; mac_addr[4] = (macid_lo 0xFF00) 8; mac_addr[5] = macid_lo 0xFF; #else mac_addr[5] = (macid_lo 8) 0xff; mac_addr[4] = macid_lo 0xff; mac_addr[3] = (macid_hi 24) 0xff; mac_addr[2] = (macid_hi 16) 0xff; mac_addr[1] = (macid_hi 8) 0xff; mac_addr[0] = macid_hi 0xff; #endif Just to be consistent, I updated the code as this too: mac_addr[0] = (macid_hi 16) 0xFF; mac_addr[1] = (macid_hi 8) 0xFF; mac_addr[2] = macid_hi 0xFF; mac_addr[3] = (macid_lo 16) 0xFF; mac_addr[4] = (macid_lo 8) 0xFF; mac_addr[5] = macid_lo 0xFF; With the same affect. Thus, for this patchset, as is: Tested-by: Steven Rostedt rost...@goodmis.org This will fail for DRA7xx not in AM33xx Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/3] Add DRA7xx CPSW Ethernet support in Device Tree
Adding device tree entry for CPSW to make it work in Dual EMAC mode. These patches were tested with DRA7 hwmod patches on top of linux-next. The patches were already reviewed [1] and has been waiting for cross bar and hwmod to be pulled in. Now since all dependent patches has already pulled in, so reposting the patches again. [1] https://lkml.org/lkml/2014/5/13/89 Mugunthan V N (3): pinctrl: dra7: dt-bindings: add pin off modes for dra7 SoC arm/dts: dra7xx: Add CPSW and MDIO module nodes for dra7xx arm/dts: dra7xx: Enable CPSW and MDIO for dra7xx EVM arch/arm/boot/dts/dra7-evm.dts| 105 ++ arch/arm/boot/dts/dra7.dtsi | 58 + include/dt-bindings/pinctrl/dra.h | 8 +++ 3 files changed, 171 insertions(+) -- 2.0.2.673.g9ab0882 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/3] arm/dts: dra7xx: Enable CPSW and MDIO for dra7xx EVM
Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active and
sleep states and enable them in board evm dts file.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 105 +
1 file changed, 105 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 50f8022..743feef 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -149,6 +149,85 @@
0xc4(PIN_OUTPUT | MUX_MODE0)/*
gpmc_advn_ale */
0xc8(PIN_OUTPUT | MUX_MODE0)/* gpmc_oen_ren
*/
0xd0(PIN_OUTPUT | MUX_MODE0)/*
gpmc_be0n_cle */
+;
+ };
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins =
+ /* Slave 1 */
+ 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */
+ 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */
+ 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */
+ 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */
+ 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */
+ 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */
+ 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */
+ 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */
+ 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */
+ 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */
+ 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */
+ 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */
+
+ /* Slave 2 */
+ 0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
+ 0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
+ 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
+ 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
+ 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
+ 0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
+ 0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
+ 0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
+ 0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
+ 0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
+ 0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
+ 0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
+ ;
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins =
+ /* Slave 1 */
+ 0x250 (PIN_OFF_NONE)
+ 0x254 (PIN_OFF_NONE)
+ 0x258 (PIN_OFF_NONE)
+ 0x25c (PIN_OFF_NONE)
+ 0x260 (PIN_OFF_NONE)
+ 0x264 (PIN_OFF_NONE)
+ 0x268 (PIN_OFF_NONE)
+ 0x26c (PIN_OFF_NONE)
+ 0x270 (PIN_OFF_NONE)
+ 0x274 (PIN_OFF_NONE)
+ 0x278 (PIN_OFF_NONE)
+ 0x27c (PIN_OFF_NONE)
+
+ /* Slave 1 */
+ 0x198 (PIN_OFF_NONE)
+ 0x19c (PIN_OFF_NONE)
+ 0x1a0 (PIN_OFF_NONE)
+ 0x1a4 (PIN_OFF_NONE)
+ 0x1a8 (PIN_OFF_NONE)
+ 0x1ac (PIN_OFF_NONE)
+ 0x1b0 (PIN_OFF_NONE)
+ 0x1b4 (PIN_OFF_NONE)
+ 0x1b8 (PIN_OFF_NONE)
+ 0x1bc (PIN_OFF_NONE)
+ 0x1c0 (PIN_OFF_NONE)
+ 0x1c4 (PIN_OFF_NONE)
+ ;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins =
+ /* MDIO */
+ 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_data */
+ 0x240 (PIN_INPUT_PULLUP | MUX_MODE0)/* mdio_clk */
+ ;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins =
+ 0x23c (PIN_OFF_NONE)
+ 0x240 (PIN_OFF_NONE)
;
};
};
@@ -504,3 +583,29 @@
usb2_phy2 {
phy-supply = ldousb_reg;
};
+
+mac {
+ status = okay;
+ pinctrl-names = default, sleep;
+ pinctrl-0 = cpsw_default;
+ pinctrl-1 = cpsw_sleep;
+ dual_emac;
+};
+
+cpsw_emac0 {
+ phy_id = davinci_mdio, 2;
+ phy-mode = rgmii;
+ dual_emac_res_vlan = 1;
+};
+
+cpsw_emac1 {
+ phy_id = davinci_mdio, 3;
+ phy-mode = rgmii;
+ dual_emac_res_vlan = 2;
+};
+
+davinci_mdio
[PATCH 2/3] arm/dts: dra7xx: Add CPSW and MDIO module nodes for dra7xx
Add CPSW and MDIO related device tree data for DRA7XX and made as status
disabled. Phy-id, pinmux for active and sleep state needs to be added in
board dts files and enable the CPSW device.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 58 +
1 file changed, 58 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 6563b98..d576b51 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -34,6 +34,8 @@
serial3 = uart4;
serial4 = uart5;
serial5 = uart6;
+ ethernet0 = cpsw_emac0;
+ ethernet1 = cpsw_emac1;
};
timer {
@@ -1145,6 +1147,62 @@
ti,irqs-skip = 10 133 139 140;
ti,irqs-safe-map = 0;
};
+
+ mac: ethernet@4a10 {
+ compatible = ti,cpsw;
+ ti,hwmods = gmac;
+ cpdma_channels = 8;
+ ale_entries = 1024;
+ bd_ram_size = 0x2000;
+ no_bd_ram = 0;
+ rx_descs = 64;
+ mac_control = 0x20;
+ slaves = 2;
+ active_slave = 0;
+ cpts_clock_mult = 0x8000;
+ cpts_clock_shift = 29;
+ reg = 0x48484000 0x1000
+ 0x48485200 0xE00;
+ #address-cells = 1;
+ #size-cells = 1;
+ /*
+* rx_thresh_pend
+* rx_pend
+* tx_pend
+* misc_pend
+*/
+ interrupts = GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH;
+ ranges;
+ status = disabled;
+
+ davinci_mdio: mdio@48485000 {
+ compatible = ti,davinci_mdio;
+ #address-cells = 1;
+ #size-cells = 0;
+ ti,hwmods = davinci_mdio;
+ bus_freq = 100;
+ reg = 0x48485000 0x100;
+ };
+
+ cpsw_emac0: slave@48480200 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ cpsw_emac1: slave@48480300 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ phy_sel: cpsw-phy-sel@4a002554 {
+ compatible = ti,dra7xx-cpsw-phy-sel;
+ reg= 0x4a002554 0x4;
+ reg-names = gmii-sel;
+ };
+ };
};
};
--
2.0.2.673.g9ab0882
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[PATCH 1/3] pinctrl: dra7: dt-bindings: add pin off modes for dra7 SoC
Add pin off modes for dra7 SoC so that during module disable or suspend state it can help saving power Signed-off-by: Mugunthan V N mugunthan...@ti.com --- include/dt-bindings/pinctrl/dra.h | 8 1 file changed, 8 insertions(+) diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h index 002a285..a0ff2d0 100644 --- a/include/dt-bindings/pinctrl/dra.h +++ b/include/dt-bindings/pinctrl/dra.h @@ -46,5 +46,13 @@ #define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) #define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) +/* Off mode states */ +#define PIN_OFF_NONE 0 +#define PIN_OFF_OUTPUT_HIGH(OFF_EN | OFFOUT_EN | OFFOUT_VAL) +#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN) +#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFF_PULL_EN | OFF_PULL_UP) +#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN) +#define PIN_OFF_WAKEUPENABLE WAKEUP_EN + #endif -- 2.0.2.673.g9ab0882 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [Re-send PATCH 1/1] arm: dra7xx: Add hwmod data for MDIO and CPSW
On Thursday 17 July 2014 01:19 PM, Tony Lindgren wrote: We seem to have this layout WR_SOFT_RESET and WR_CONTROL in the TRM: WR_SOFT_RESET [0] SOFT_RESET WR_CONTROL [3:2] MMR_STDBYMODE 0 = force-idle, 1 = no-standby [1:0] MMR_IDLEMODE0 = force-idle, 1 = no-idle And so it seems to match what am33xx also has for am33xx_cpgmac_sysc and am33xx TRM for 14.5.9 CONTROL register. So as far as I'm concerned: Acked-by: Tony Lindgren t...@atomide.com Paul, Can you pull this patch as Tony acked the patch. Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] arm: dra7xx: Add hwmod data for MDIO and CPSW
On Wednesday 09 July 2014 12:10 AM, Sebastian Andrzej Siewior wrote:
Adding hwmod data for CPSW and MDIO which is present in DRA7xx SoC
Signed-off-by: Mugunthan V N mugunthan...@ti.com
Signed-off-by: Praveen Rao p...@ti.com
Signed-off-by: Sebastian Andrzej Siewior bige...@linutronix.de
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 96
+++
1 file changed, 96 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 20b4398..0fa2c66 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1845,6 +1845,85 @@ static struct omap_hwmod dra7xx_vcp2_hwmod = {
};
/*
+ * 'gmac' class
+ * cpsw/gmac sub system
+ */
+static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x8,
+ .syss_offs = 0x4,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
+ MSTANDBY_NO),
+ .sysc_fields= omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
+ .name = gmac,
+ .sysc = dra7xx_gmac_sysc,
+};
+
+static struct omap_hwmod_irq_info dra7xx_gmac_irqs[] = {
+ { .name = c0_rx_thresh_pend, .irq = 50 + DRA7XX_IRQ_GIC_START, },
+ { .name = c0_rx_pend, .irq = 51 + DRA7XX_IRQ_GIC_START, },
+ { .name = c0_tx_pend, .irq = 52 + DRA7XX_IRQ_GIC_START, },
+ { .name = c0_misc_pend, .irq = 53 + DRA7XX_IRQ_GIC_START, },
+ { .irq = -1 },
+};
This is not proper, NAK
Hwmod is already posted
http://www.spinics.net/lists/linux-omap/msg99039.html
and waiting for Acks and tested-by
Regards
Mugunthan V N
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Re: [PATCH 2/3] arm: dts: dra7: Enable CPSW and MDIO for dra7xx EVM
On Wednesday 09 July 2014 12:10 AM, Sebastian Andrzej Siewior wrote:
From: Mugunthan V N mugunthan...@ti.com
Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active
and sleep states and enable them in board evm dts file.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
[Resolved merge conflict and rebased on 3.8 kernel.
Update the pinmux configuration for CPSW and MDIO by removing the
macro definitons to match the 3.8 implementation.]
Signed-off-by: Praveen Rao p...@ti.com
Signed-off-by: Sebastian Andrzej Siewior bige...@linutronix.de
---
arch/arm/boot/dts/dra7-evm.dts | 61
++
arch/arm/boot/dts/dra7.dtsi| 48 +
2 files changed, 109 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 4adc280..956a7bd 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -94,6 +94,46 @@
;
};
+ cpsw_default_pins: pinmux_cpsw_default_pins {
+ pinctrl-single,pins =
+ /* Slave 1 */
+ 0x250 0x0 /* rgmii1_tclk PIN_OUTPUT | MUX_MODE0 */
+ 0x254 0x0 /* rgmii1_tctl PIN_OUTPUT | MUX_MODE0 */
+ 0x258 0x0 /* rgmii1_td3 PIN_OUTPUT | MUX_MODE0 */
+ 0x25c 0x0 /* rgmii1_td2 PIN_OUTPUT | MUX_MODE0 */
+ 0x260 0x0 /* rgmii1_td1 PIN_OUTPUT | MUX_MODE0 */
+ 0x264 0x0 /* rgmii1_td0 PIN_OUTPUT | MUX_MODE0 */
+ 0x268 0x0004 /* rgmii1_rclk PIN_INPUT | MUX_MODE0
*/
+ 0x26c 0x0004 /* rgmii1_rctl PIN_INPUT | MUX_MODE0
*/
+ 0x270 0x0004 /* rgmii1_rd3 PIN_INPUT | MUX_MODE0
*/
+ 0x274 0x0004 /* rgmii1_rd2 PIN_INPUT | MUX_MODE0
*/
+ 0x278 0x0004 /* rgmii1_rd1 PIN_INPUT | MUX_MODE0
*/
+ 0x27c 0x0004 /* rgmii1_rd0 PIN_INPUT | MUX_MODE0
*/
+
+ /* Slave 2 */
+ 0x198 0x4 /* rgmii2_tclk PIN_OUTPUT | MUX_MODE4 */
+ 0x19c 0x4 /* rgmii2_tctl PIN_OUTPUT | MUX_MODE4 */
+ 0x1a0 0x4 /* rgmii2_td3 PIN_OUTPUT | MUX_MODE4 */
+ 0x1a4 0x4 /* rgmii2_td2 PIN_OUTPUT | MUX_MODE4 */
+ 0x1a8 0x4 /* rgmii2_td1 PIN_OUTPUT | MUX_MODE4 */
+ 0x1ac 0x4 /* rgmii2_td0 PIN_OUTPUT | MUX_MODE4 */
+ 0x1b0 0x00040004 /* rgmii2_rclk PIN_INPUT | MUX_MODE4
*/
+ 0x1b4 0x00040004 /* rgmii2_rctl PIN_INPUT | MUX_MODE4
*/
+ 0x1b8 0x00040004 /* rgmii2_rd3 PIN_INPUT | MUX_MODE4
*/
+ 0x1bc 0x00040004 /* rgmii2_rd2 PIN_INPUT | MUX_MODE4
*/
+ 0x1c0 0x00040004 /* rgmii2_rd1 PIN_INPUT | MUX_MODE4
*/
+ 0x1c4 0x00040004 /* rgmii2_rd0 PIN_INPUT | MUX_MODE4
*/
+ ;
+ };
+
+ davinci_mdio_default_pins: pinmux_davinci_mdio_default_pins {
+ pinctrl-single,pins =
+ /* MDIO */
+ 0x23c 0x3 /* mdio_data PIN_OUTPUT_PULLUP |
MUX_MODE0 */
+ 0x240 0x7 /* mdio_clk PIN_INPUT_PULLUP |
MUX_MODE0 */
+ ;
+ };
+
qspi1_pins: pinmux_qspi1_pins {
pinctrl-single,pins =
0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
@@ -332,6 +372,27 @@
cpu0-supply = smps123_reg;
};
+gmac {
+ status=okay;
+ pinctrl-names = default;
+ pinctrl-0 = cpsw_default_pins;
+};
+
+davinci_mdio {
+ pinctrl-names = default;
+ pinctrl-0 = davinci_mdio_default_pins;
+};
+
+cpsw_emac0 {
+ phy_id = davinci_mdio, 2;
+ phy-mode = rgmii-txid;
+};
+
+cpsw_emac1 {
+ phy_id = davinci_mdio, 3;
+ phy-mode = rgmii-txid;
+};
+
qspi {
status = okay;
pinctrl-names = default;
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index c29945e..daf7d36 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -763,6 +763,54 @@
status = disabled;
};
+ gmac: ethernet@48484000 {
+ compatible = ti,cpsw;
+ ti,hwmods = gmac;
+ cpdma_channels = 8;
+ ale_entries = 1024;
+ bd_ram_size = 0x2000;
+ no_bd_ram = 0;
+ rx_descs = 64;
+ mac_control = 0x20;
+ slaves = 2;
+ active_slave = 0;
+ cpts_clock_mult = 0x8000;
+ cpts_clock_shift = 29;
+ reg = 0x48484000 0x800
[Re-send PATCH 1/1] arm: dra7xx: Add hwmod data for MDIO and CPSW
Adding hwmod data for CPSW and MDIO which is present in DRA7xx SoC
Cc: Rajendra Nayak rna...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
This patch was already send twice on 2013-10-18 and 2014-05-13. Adding
more people in Cc to review the patch.
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 65 +++
1 file changed, 65 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 20b4398..45b5113 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -273,6 +273,56 @@ static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
};
/*
+ * 'gmac' class
+ * cpsw/gmac sub system
+ */
+static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x8,
+ .syss_offs = 0x4,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
+ MSTANDBY_NO),
+ .sysc_fields= omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
+ .name = gmac,
+ .sysc = dra7xx_gmac_sysc,
+};
+
+static struct omap_hwmod dra7xx_gmac_hwmod = {
+ .name = gmac,
+ .class = dra7xx_gmac_hwmod_class,
+ .clkdm_name = gmac_clkdm,
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+ .main_clk = dpll_gmac_ck,
+ .mpu_rt_idx = 1,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'mdio' class
+ */
+static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
+ .name = davinci_mdio,
+};
+
+static struct omap_hwmod dra7xx_mdio_hwmod = {
+ .name = davinci_mdio,
+ .class = dra7xx_mdio_hwmod_class,
+ .clkdm_name = gmac_clkdm,
+ .main_clk = dpll_gmac_ck,
+};
+
+/*
* 'dcan' class
*
*/
@@ -1999,6 +2049,19 @@ static struct omap_hwmod_ocp_if
dra7xx_l4_wkup__ctrl_module_wkup = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
+ .master = dra7xx_l4_per2_hwmod,
+ .slave = dra7xx_gmac_hwmod,
+ .clk= dpll_gmac_ck,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
+ .master = dra7xx_gmac_hwmod,
+ .slave = dra7xx_mdio_hwmod,
+ .user = OCP_USER_MPU,
+};
+
/* l4_wkup - dcan1 */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
.master = dra7xx_l4_wkup_hwmod,
@@ -2642,6 +2705,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[]
__initdata = {
dra7xx_l4_wkup__ctrl_module_wkup,
dra7xx_l4_wkup__dcan1,
dra7xx_l4_per2__dcan2,
+ dra7xx_l4_per2__cpgmac0,
+ dra7xx_gmac__mdio,
dra7xx_l4_cfg__dma_system,
dra7xx_l3_main_1__dss,
dra7xx_l3_main_1__dispc,
--
2.0.0.390.gcb682f8
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Re: [PATCH 1/1] ARM: dts: am437x-gp-evm: Add ethernet support for GP EVM
On Tuesday 13 May 2014 10:50 PM, Tony Lindgren wrote:
* Mugunthan V N mugunthan...@ti.com [140507 02:31]:
Add CPSW ethernet support for AM437x GP EVM which has one slave pinned out
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts | 72
+
1 file changed, 72 insertions(+)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 2e0c636..30ace1b 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -98,6 +98,58 @@
0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /*
spi2_d0.gpio3_22 */
;
};
+
+cpsw_default: cpsw_default {
+pinctrl-single,pins =
+/* Slave 1 */
+0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txen.rgmii1_txen */
+0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxdv.rgmii1_rxctl */
+0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txd1.rgmii1_txd3 */
+0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txd0.rgmii1_txd2 */
+0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txd1.rgmii1_txd1 */
+0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txd0.rgmii1_txd0 */
+0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txclk.rmii1_tclk */
+0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxclk.rmii1_rclk */
+0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxd1.rgmii1_rxd3 */
+0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxd0.rgmii1_rxd2 */
+0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxd1.rgmii1_rxd1 */
+0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxd0.rgmii1_rxd0 */
+;
+};
+
+cpsw_sleep: cpsw_sleep {
+pinctrl-single,pins =
+/* Slave 1 reset value */
+0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+;
+};
Just a nitpick comment to make things more readable. Can you please add
the comments for these pins too so people can cross check them against
the documentation easier?
+davinci_mdio_default: davinci_mdio_default {
+pinctrl-single,pins =
+/* MDIO */
+0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
/* mdio_data.mdio_data */
+0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)
/* mdio_clk.mdio_clk */
+;
+};
+
+davinci_mdio_sleep: davinci_mdio_sleep {
+pinctrl-single,pins =
+/* MDIO reset value */
+0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+;
+};
};
And here too please.
Will add the comments and post the patch again
Regards
Mugunthan V N
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[PATCH 1/1] arm: dra7xx: Add hwmod data for MDIO and CPSW
Adding hwmod data for CPSW and MDIO which is present in DRA7xx SoC
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 65 +++
1 file changed, 65 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 810c205..02ea08f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -273,6 +273,56 @@ static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
};
/*
+ * 'gmac' class
+ * cpsw/gmac sub system
+ */
+static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x8,
+ .syss_offs = 0x4,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
+ MSTANDBY_NO),
+ .sysc_fields= omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
+ .name = gmac,
+ .sysc = dra7xx_gmac_sysc,
+};
+
+static struct omap_hwmod dra7xx_gmac_hwmod = {
+ .name = gmac,
+ .class = dra7xx_gmac_hwmod_class,
+ .clkdm_name = gmac_clkdm,
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+ .main_clk = dpll_gmac_ck,
+ .mpu_rt_idx = 1,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'mdio' class
+ */
+static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
+ .name = davinci_mdio,
+};
+
+static struct omap_hwmod dra7xx_mdio_hwmod = {
+ .name = davinci_mdio,
+ .class = dra7xx_mdio_hwmod_class,
+ .clkdm_name = gmac_clkdm,
+ .main_clk = dpll_gmac_ck,
+};
+
+/*
* 'dcan' class
*
*/
@@ -1999,6 +2049,19 @@ static struct omap_hwmod_ocp_if
dra7xx_l4_wkup__ctrl_module_wkup = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
+ .master = dra7xx_l4_per2_hwmod,
+ .slave = dra7xx_gmac_hwmod,
+ .clk= dpll_gmac_ck,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
+ .master = dra7xx_gmac_hwmod,
+ .slave = dra7xx_mdio_hwmod,
+ .user = OCP_USER_MPU,
+};
+
/* l4_wkup - dcan1 */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
.master = dra7xx_l4_wkup_hwmod,
@@ -2652,6 +2715,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[]
__initdata = {
dra7xx_l4_wkup__ctrl_module_wkup,
dra7xx_l4_wkup__dcan1,
dra7xx_l4_per2__dcan2,
+ dra7xx_l4_per2__cpgmac0,
+ dra7xx_gmac__mdio,
dra7xx_l4_cfg__dma_system,
dra7xx_l3_main_1__dss,
dra7xx_l3_main_1__dispc,
--
1.9.2.459.g68773ac
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[PATCH 0/3] Add DRA7xx CPSW Ethernet support in Device Tree
Adding device tree entry for CPSW to make it work in Dual EMAC mode. DRA7 cpsw phy sel driver patch has been pulled in net-next git with the following commit id *d415fa1b88748d664b7b6a310dd8e699d2686cf7* Mugunthan V N (3): pinctrl: dra7: dt-bindings: add pin off modes for dra7 SoC arm/dts: dra7xx: Add CPSW and MDIO module nodes for dra7xx arm/dts: dra7xx: Enable CPSW and MDIO for dra7xx EVM arch/arm/boot/dts/dra7-evm.dts| 103 ++ arch/arm/boot/dts/dra7.dtsi | 59 ++ include/dt-bindings/pinctrl/dra.h | 8 +++ 3 files changed, 170 insertions(+) -- 1.9.2.459.g68773ac -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] arm/dts: dra7xx: Add CPSW and MDIO module nodes for dra7xx
Add CPSW and MDIO related device tree data for DRA7XX and made as status
disabled. Phy-id, pinmux for active and sleep state needs to be added in
board dts files and enable the CPSW device.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 59 +
1 file changed, 59 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index e550f06..61a5b68 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -31,6 +31,8 @@
serial3 = uart4;
serial4 = uart5;
serial5 = uart6;
+ ethernet0 = cpsw_emac0;
+ ethernet1 = cpsw_emac1;
};
timer {
@@ -785,6 +787,63 @@
interrupts = 0 343 0x4;
status = disabled;
};
+
+ mac: ethernet@4a10 {
+ compatible = ti,cpsw;
+ ti,hwmods = gmac;
+ cpdma_channels = 8;
+ ale_entries = 1024;
+ bd_ram_size = 0x2000;
+ no_bd_ram = 0;
+ rx_descs = 64;
+ mac_control = 0x20;
+ slaves = 2;
+ active_slave = 0;
+ cpts_clock_mult = 0x8000;
+ cpts_clock_shift = 29;
+ reg = 0x48484000 0x800
+ 0x48485200 0x100;
+ #address-cells = 1;
+ #size-cells = 1;
+ /*
+* rx_thresh_pend
+* rx_pend
+* tx_pend
+* misc_pend
+*/
+ interrupts = GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH;
+ ranges;
+ status = disabled;
+
+ davinci_mdio: mdio@48485000 {
+ compatible = ti,davinci_mdio;
+ #address-cells = 1;
+ #size-cells = 0;
+ ti,hwmods = davinci_mdio;
+ bus_freq = 100;
+ reg = 0x48485000 0x100;
+ };
+
+ cpsw_emac0: slave@48480200 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ cpsw_emac1: slave@48480300 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ phy_sel: cpsw-phy-sel@4a002554 {
+ compatible = ti,dra7xx-cpsw-phy-sel;
+ reg= 0x4a002554 0x4;
+ reg-names = gmii-sel;
+ };
+ };
+
};
crossbar_mpu: crossbar@4a02 {
--
1.9.2.459.g68773ac
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[PATCH 1/3] pinctrl: dra7: dt-bindings: add pin off modes for dra7 SoC
Add pin off modes for dra7 SoC so that during module disable or suspend state it can help saving power Signed-off-by: Mugunthan V N mugunthan...@ti.com --- include/dt-bindings/pinctrl/dra.h | 8 1 file changed, 8 insertions(+) diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h index 002a285..a0ff2d0 100644 --- a/include/dt-bindings/pinctrl/dra.h +++ b/include/dt-bindings/pinctrl/dra.h @@ -46,5 +46,13 @@ #define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) #define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) +/* Off mode states */ +#define PIN_OFF_NONE 0 +#define PIN_OFF_OUTPUT_HIGH(OFF_EN | OFFOUT_EN | OFFOUT_VAL) +#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN) +#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFF_PULL_EN | OFF_PULL_UP) +#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN) +#define PIN_OFF_WAKEUPENABLE WAKEUP_EN + #endif -- 1.9.2.459.g68773ac -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/3] arm/dts: dra7xx: Enable CPSW and MDIO for dra7xx EVM
Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active and
sleep states and enable them in board evm dts file.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 103 +
1 file changed, 103 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 5f1f6da..91d5dd8 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -108,6 +108,85 @@
0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_cs3.qspi1_cs1 */
;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins =
+ /* Slave 1 */
+ 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */
+ 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */
+ 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */
+ 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */
+ 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */
+ 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */
+ 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */
+ 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */
+ 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */
+ 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */
+ 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */
+ 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */
+
+ /* Slave 2 */
+ 0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
+ 0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
+ 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
+ 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
+ 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
+ 0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
+ 0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
+ 0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
+ 0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
+ 0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
+ 0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
+ 0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
+ ;
+
+ };
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins =
+ /* Slave 1 */
+ 0x250 (PIN_OFF_NONE)
+ 0x254 (PIN_OFF_NONE)
+ 0x258 (PIN_OFF_NONE)
+ 0x25c (PIN_OFF_NONE)
+ 0x260 (PIN_OFF_NONE)
+ 0x264 (PIN_OFF_NONE)
+ 0x268 (PIN_OFF_NONE)
+ 0x26c (PIN_OFF_NONE)
+ 0x270 (PIN_OFF_NONE)
+ 0x274 (PIN_OFF_NONE)
+ 0x278 (PIN_OFF_NONE)
+ 0x27c (PIN_OFF_NONE)
+
+ /* Slave 1 */
+ 0x198 (PIN_OFF_NONE)
+ 0x19c (PIN_OFF_NONE)
+ 0x1a0 (PIN_OFF_NONE)
+ 0x1a4 (PIN_OFF_NONE)
+ 0x1a8 (PIN_OFF_NONE)
+ 0x1ac (PIN_OFF_NONE)
+ 0x1b0 (PIN_OFF_NONE)
+ 0x1b4 (PIN_OFF_NONE)
+ 0x1b8 (PIN_OFF_NONE)
+ 0x1bc (PIN_OFF_NONE)
+ 0x1c0 (PIN_OFF_NONE)
+ 0x1c4 (PIN_OFF_NONE)
+ ;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins =
+ /* MDIO */
+ 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_data */
+ 0x240 (PIN_INPUT_PULLUP | MUX_MODE0)/* mdio_clk */
+ ;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins =
+ 0x23c (PIN_OFF_NONE)
+ 0x240 (PIN_OFF_NONE)
+ ;
+ };
};
i2c1 {
@@ -353,3 +432,27 @@
};
};
};
+
+mac {
+ status = okay;
+ pinctrl-names = default, sleep;
+ pinctrl-0 = cpsw_default;
+ pinctrl-1 = cpsw_sleep;
+ dual_emac;
+};
+
+cpsw_emac0 {
+ phy_id = davinci_mdio, 2;
+ phy-mode = rgmii;
+};
+
+cpsw_emac1 {
+ phy_id = davinci_mdio, 3;
+ phy-mode = rgmii;
+};
+
+davinci_mdio {
+ pinctrl-names = default, sleep;
+ pinctrl-0 = davinci_mdio_default;
+ pinctrl-1 = davinci_mdio_sleep;
+};
--
1.9.2.459.g68773ac
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[PATCH 0/2] Add AM437x GP EVM cpsw DT node
Add AM437x GP EVM cpsw device tree node Mugunthan V N (2): ARM: dts: am4372: Add cpsw phy sel dt node ARM: dts: am437x-gp-evm: Add ethernet support for GP EVM arch/arm/boot/dts/am4372.dtsi | 6 arch/arm/boot/dts/am437x-gp-evm.dts | 72 + 2 files changed, 78 insertions(+) -- 1.9.2.459.g68773ac -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ARM: dts: am4372: Add cpsw phy sel dt node
Add cpsw phy sel device tree node for selecting phy mode in control module
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/am4372.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index ac37ac9..0ff84cf 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -521,6 +521,12 @@
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
+
+ phy_sel: cpsw-phy-sel@44e10650 {
+ compatible = ti,am43xx-cpsw-phy-sel;
+ reg= 0x44e10650 0x4;
+ reg-names = gmii-sel;
+ };
};
epwmss0: epwmss@4830 {
--
1.9.2.459.g68773ac
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[PATCH 2/2] ARM: dts: am437x-gp-evm: Add ethernet support for GP EVM
Add CPSW ethernet support for AM437x GP EVM which has one slave pinned out
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts | 72 +
1 file changed, 72 insertions(+)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 4e92d9e..8dc1c6e 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -98,6 +98,58 @@
0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /*
spi2_d0.gpio3_22 */
;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins =
+ /* Slave 1 */
+ 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txen.rgmii1_txen */
+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxdv.rgmii1_rxctl */
+ 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txd1.rgmii1_txd3 */
+ 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txd0.rgmii1_txd2 */
+ 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txd1.rgmii1_txd1 */
+ 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txd0.rgmii1_txd0 */
+ 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txclk.rmii1_tclk */
+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxclk.rmii1_rclk */
+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxd1.rgmii1_rxd3 */
+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxd0.rgmii1_rxd2 */
+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxd1.rgmii1_rxd1 */
+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxd0.rgmii1_rxd0 */
+ ;
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins =
+ /* Slave 1 reset value */
+ 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ ;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins =
+ /* MDIO */
+ 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
/* mdio_data.mdio_data */
+ 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)
/* mdio_clk.mdio_clk */
+ ;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins =
+ /* MDIO reset value */
+ 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ ;
+ };
};
i2c0 {
@@ -179,3 +231,23 @@
dr_mode = host;
status = okay;
};
+
+mac {
+ slaves = 1;
+ pinctrl-names = default, sleep;
+ pinctrl-0 = cpsw_default;
+ pinctrl-1 = cpsw_sleep;
+ status = okay;
+};
+
+davinci_mdio {
+ pinctrl-names = default, sleep;
+ pinctrl-0 = davinci_mdio_default;
+ pinctrl-1 = davinci_mdio_sleep;
+ status = okay;
+};
+
+cpsw_emac0 {
+ phy_id = davinci_mdio, 0;
+ phy-mode = rgmii;
+};
--
1.9.2.459.g68773ac
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Re: [PATCH 0/3] Add DRA7xx CPSW Ethernet support in Device Tree
Tony/Benoit On Tuesday 13 May 2014 01:34 PM, Mugunthan V N wrote: Adding device tree entry for CPSW to make it work in Dual EMAC mode. DRA7 cpsw phy sel driver patch has been pulled in net-next git with the following commit id *d415fa1b88748d664b7b6a310dd8e699d2686cf7* Mugunthan V N (3): pinctrl: dra7: dt-bindings: add pin off modes for dra7 SoC arm/dts: dra7xx: Add CPSW and MDIO module nodes for dra7xx arm/dts: dra7xx: Enable CPSW and MDIO for dra7xx EVM arch/arm/boot/dts/dra7-evm.dts| 103 ++ arch/arm/boot/dts/dra7.dtsi | 59 ++ include/dt-bindings/pinctrl/dra.h | 8 +++ 3 files changed, 170 insertions(+) This patch series depends on Cross bar dt patch set http://comments.gmane.org/gmane.linux.drivers.devicetree/73025 Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: AM33XX: fix ethernet and mdio default state
On Thursday 08 May 2014 02:27 PM, Johan Hovold wrote: Make sure ethernet and mdio nodes are disabled by default and enable them explicitly only on boards that actually use them. Signed-off-by: Johan Hovold jhov...@gmail.com Acked-by: Mugunthan V N mugunthan...@ti.com Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/1] ARM: dts: am437x-gp-evm: Add ethernet support for GP EVM
Add CPSW ethernet support for AM437x GP EVM which has one slave pinned out
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts | 72 +
1 file changed, 72 insertions(+)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 2e0c636..30ace1b 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -98,6 +98,58 @@
0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /*
spi2_d0.gpio3_22 */
;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins =
+ /* Slave 1 */
+ 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txen.rgmii1_txen */
+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxdv.rgmii1_rxctl */
+ 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txd1.rgmii1_txd3 */
+ 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txd0.rgmii1_txd2 */
+ 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txd1.rgmii1_txd1 */
+ 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txd0.rgmii1_txd0 */
+ 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txclk.rmii1_tclk */
+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxclk.rmii1_rclk */
+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxd1.rgmii1_rxd3 */
+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxd0.rgmii1_rxd2 */
+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxd1.rgmii1_rxd1 */
+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxd0.rgmii1_rxd0 */
+ ;
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins =
+ /* Slave 1 reset value */
+ 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ ;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins =
+ /* MDIO */
+ 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
/* mdio_data.mdio_data */
+ 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)
/* mdio_clk.mdio_clk */
+ ;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins =
+ /* MDIO reset value */
+ 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ ;
+ };
};
i2c0 {
@@ -174,3 +226,23 @@
dr_mode = host;
status = okay;
};
+
+mac {
+ slaves = 1;
+ pinctrl-names = default, sleep;
+ pinctrl-0 = cpsw_default;
+ pinctrl-1 = cpsw_sleep;
+ status = okay;
+};
+
+davinci_mdio {
+ pinctrl-names = default, sleep;
+ pinctrl-0 = davinci_mdio_default;
+ pinctrl-1 = davinci_mdio_sleep;
+ status = okay;
+};
+
+cpsw_emac0 {
+ phy_id = davinci_mdio, 0;
+ phy-mode = rgmii;
+};
--
1.9.2.459.g68773ac
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Re: [PATCH v2 0/6] Add CPTS support for AM437x
On Friday 02 May 2014 12:01 PM, George Cherian wrote: The series adds CPTS support for AM4372. Patch 1 - DT changes w.r.t clock changes for AM33xx. Patch 2 - CPTS clock name harcoding in the driver is removed. Easier to pass the clock name from dt rather than hardcoding in driver. Also in prepration for DRA7x CPTS support. Patch 3 - Enable the CPTS support for both DRA7x and AM4372 in the driver. Patch 4 - Enable the Annexe F for L2 PTP for AM437x and DRA7x. Patch 5 - Change the default clocksource to dpll_core_m5 Patch 6 - DT changes for AM4372. v1 - v2 Patch 1 and 2 Re-ordering. Seperate TS_BITS define for Hw version V2 and V3 George Cherian (6): ARM: dts: am33xx: Add clock names for cpsw and cpts drivers: net: cpts: Remove hardcoded clock name for CPTS drivers: net: cpsw: Enable CPTS for DRA7xx and AM4372 drivers: net: cpsw: Enable Annexe F Time sync ARM: AM43xx: clk: Change the cpts ref clock source to dpll_core_m5 clk ARM: dts: am4372: Add clock names for cpsw and cpts arch/arm/boot/dts/am33xx.dtsi | 2 ++ arch/arm/boot/dts/am4372.dtsi | 2 ++ drivers/clk/ti/clk-43xx.c | 16 drivers/net/ethernet/ti/cpsw.c | 56 +++--- drivers/net/ethernet/ti/cpts.c | 11 +++-- 5 files changed, 66 insertions(+), 21 deletions(-) Acked-by: Mugunthan V N mugunthan...@ti.com Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC] CPSW: dual standalone emac mode / bonding
On Wednesday 05 March 2014 11:03 PM, Christian Engelmayer wrote: Has anybody successfuly setup ethernet bonding on a TI AM335x based system using the CPSW in dual standalone emac mode? I am running an active-backup test setup - momentarily still running Linux 3.2 - and experience repeated loss of ethernet connectivity. That happens eg. after the board is idle and receives an own ARP request on the backup slave interface. It seems that the corresponding reply does not reach the CPU and I can see via SysFs that the host's address entry got associated with the external backup port. index 2, raw: 1018 31e00669, type: addr(1), addr: 00:18:31:e0:06:69, uctype: persistant(0), port: 0 -- uctype: persistant(0), port: 2 As expected, triggering a unicast from the board or bypassing the ALE recovers It seems that some other system in the network is using the same mac in your EVM or there is a loop detected in your network which leads that ALE is learning that there is system with your MAC and updating the ALE table that the mac is there and which leads your own packet will be forwarded to that port and not to host port. When ever you start a transmission the ALE learns the host port MAC is x and updates ALE table with that port number and so there in your network is working. Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RESEND PATCH 1/1] arm: dts: am33xx: correcting dt node unit address for usb
DT node's unit address should be its own register offset address to make it a
unique across the system. This patch corrects the incorrect USB entries with
correct register offset for unit address.
Cc: Sebastian Andrzej Siewior bige...@linutronix.de
Cc: Felipe Balbi ba...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
This patch was posted long back (Aug. 30, 2013), below is the archive of the
orginal patch.
https://patchwork.kernel.org/patch/2852163/
---
arch/arm/boot/dts/am33xx.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 7073429..9770e35 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -453,7 +453,7 @@
ti,hwmods = usb_otg_hs;
status = disabled;
- usb_ctrl_mod: control@44e1 {
+ usb_ctrl_mod: control@44e10620 {
compatible = ti,am335x-usb-ctrl-module;
reg = 0x44e10620 0x10
0x44e10648 0x4;
@@ -556,7 +556,7 @@
tx14, tx15;
};
- cppi41dma: dma-controller@07402000 {
+ cppi41dma: dma-controller@47402000 {
compatible = ti,am3359-cppi41;
reg = 0x4740 0x1000
0x47402000 0x1000
--
1.9.0
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[PATCH 1/1] net: cpsw: fix cpdma rx descriptor leak on down interface
From: Schuyler Patton spat...@ti.com
This patch fixes a CPDMA RX Descriptor leak that occurs after taking
the interface down when the CPSW is in Dual MAC mode. Previously
the CPSW_ALE port was left open up which causes packets to be received
and processed by the RX interrupt handler and were passed to the
non active network interface where they were ignored.
The fix is for the slave_stop function of the selected interface
to disable the respective CPSW_ALE Port from forwarding packets. This
blocks traffic from being received on the inactive interface.
Signed-off-by: Schuyler Patton spat...@ti.com
Reviewed-by: Felipe Balbi ba...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
drivers/net/ethernet/ti/cpsw.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 651087b..ffd4d12 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -1164,11 +1164,17 @@ static void cpsw_init_host_port(struct cpsw_priv *priv)
static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
{
+ u32 slave_port;
+
+ slave_port = cpsw_get_slave_port(priv, slave-slave_num);
+
if (!slave-phy)
return;
phy_stop(slave-phy);
phy_disconnect(slave-phy);
slave-phy = NULL;
+ cpsw_ale_control_set(priv-ale, slave_port,
+ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
}
static int cpsw_ndo_open(struct net_device *ndev)
--
1.9.0
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[RESEND Patch 6/9] ARM: dts: DRA7: Add device nodes for ABB
From: Nishanth Menon n...@ti.com
Add ABB device nodes for DRA7 family of devices. Data is based on
DRA7 Technical Reference Manual revision I (Sept 2013)
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 132
1 file changed, 132 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 499974a..9e3caf3 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -578,6 +578,138 @@
status = disabled;
};
+ abb_mpu: regulator-abb-mpu {
+ compatible = ti,abb-v3;
+ regulator-name = abb_mpu;
+ #address-cells = 0;
+ #size-cells = 0;
+ clocks = sys_clkin1;
+ ti,settling-time = 50;
+ ti,clock-cycles = 16;
+
+ reg = 0x4ae07ddc 0x4, 0x4ae07de0 0x4,
+ 0x4ae06014 0x4, 0x4a003b20 0x8,
+ 0x4ae0c158 0x4;
+ reg-names = setup-address, control-address,
+ int-address, efuse-address,
+ ldo-address;
+ ti,tranxdone-status-mask = 0x80;
+ /* LDOVBBMPU_FBB_MUX_CTRL */
+ ti,ldovbb-override-mask = 0x400;
+ /* LDOVBBMPU_FBB_VSET_OUT */
+ ti,ldovbb-vset-mask = 0x1F;
+
+ /*
+* NOTE: only FBB mode used but actual vset will
+* determine final biasing
+*/
+ ti,abb_info =
+ /*uVABB efuse rbb_m fbb_m vset_m*/
+ 106 0 0x0 0 0x0200 0x01F0
+ 116 0 0x4 0 0x0200 0x01F0
+ 121 0 0x8 0 0x0200 0x01F0
+ ;
+ };
+
+ abb_ivahd: regulator-abb-ivahd {
+ compatible = ti,abb-v3;
+ regulator-name = abb_ivahd;
+ #address-cells = 0;
+ #size-cells = 0;
+ clocks = sys_clkin1;
+ ti,settling-time = 50;
+ ti,clock-cycles = 16;
+
+ reg = 0x4ae07e34 0x4, 0x4ae07e24 0x4,
+ 0x4ae06010 0x4, 0x4a0025cc 0x8,
+ 0x4a002470 0x4;
+ reg-names = setup-address, control-address,
+ int-address, efuse-address,
+ ldo-address;
+ ti,tranxdone-status-mask = 0x4000;
+ /* LDOVBBIVA_FBB_MUX_CTRL */
+ ti,ldovbb-override-mask = 0x400;
+ /* LDOVBBIVA_FBB_VSET_OUT */
+ ti,ldovbb-vset-mask = 0x1F;
+
+ /*
+* NOTE: only FBB mode used but actual vset will
+* determine final biasing
+*/
+ ti,abb_info =
+ /*uVABB efuse rbb_m fbb_m vset_m*/
+ 1055000 0 0x0 0 0x0200 0x01F0
+ 115 0 0x4 0 0x0200 0x01F0
+ 125 0 0x8 0 0x0200 0x01F0
+ ;
+ };
+
+ abb_dspeve: regulator-abb-dspeve {
+ compatible = ti,abb-v3;
+ regulator-name = abb_dspeve;
+ #address-cells = 0;
+ #size-cells = 0;
+ clocks = sys_clkin1;
+ ti,settling-time = 50;
+ ti,clock-cycles = 16;
+
+ reg = 0x4ae07e30 0x4, 0x4ae07e20 0x4,
+ 0x4ae06010 0x4, 0x4a0025e0 0x8,
+ 0x4a00246c 0x4;
+ reg-names = setup-address, control-address,
+ int-address, efuse-address,
+ ldo-address;
+ ti,tranxdone-status-mask = 0x2000;
+ /* LDOVBBDSPEVE_FBB_MUX_CTRL */
+ ti,ldovbb-override-mask = 0x400;
+ /* LDOVBBDSPEVE_FBB_VSET_OUT */
+ ti,ldovbb-vset-mask = 0x1F;
+
+ /*
+* NOTE: only FBB mode used but actual vset will
+* determine final biasing
[RESEND Patch 9/9] ARM: DTS: DRA7: Add routable-irqs property for gic node
From: Sricharan R r.sricha...@ti.com There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The gic provides the support for such IPs in the form of routable-irqs. So adding the property here to gic node. Cc: Benoit Cousson bcous...@baylibre.com Cc: Santosh Shilimkar santosh.shilim...@ti.com Cc: Rajendra Nayak rna...@ti.com Cc: Tony Lindgren t...@atomide.com Signed-off-by: Sricharan R r.sricha...@ti.com Acked-by: Santosh Shilimkar santosh.shilim...@ti.com Signed-off-by: Mugunthan V N mugunthan...@ti.com --- arch/arm/boot/dts/dra7.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 2bd3a9a..824e316 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -72,6 +72,7 @@ compatible = arm,cortex-a15-gic; interrupt-controller; #interrupt-cells = 3; + arm,routable-irqs = 160; reg = 0x48211000 0x1000, 0x48212000 0x1000, 0x48214000 0x2000, -- 1.9.0 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RESEND Patch 8/9] ARM: DTS: DRA7: Replace peripheral interrupt numbers with crossbar inputs
From: Sricharan R r.sricha...@ti.com
Now with the crossbar IP in picture, the peripherals do not have the
fixed interrupt lines. Instead they rely on the crossbar irqchip to
allocate and map a free interrupt line to its crossbar input. So replacing
all the peripheral interrupt numbers with its fixed crossbar input lines.
Cc: Benoit Cousson bcous...@baylibre.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Tony Lindgren t...@atomide.com
Signed-off-by: Sricharan R r.sricha...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 86 ++---
1 file changed, 43 insertions(+), 43 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 88fc2eb..2bd3a9a 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -166,10 +166,10 @@
sdma: dma-controller@4a056000 {
compatible = ti,omap4430-sdma;
reg = 0x4a056000 0x1000;
- interrupts = GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
#dma-cells = 1;
#dma-channels = 32;
#dma-requests = 127;
@@ -178,7 +178,7 @@
gpio1: gpio@4ae1 {
compatible = ti,omap4-gpio;
reg = 0x4ae1 0x200;
- interrupts = GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio1;
gpio-controller;
#gpio-cells = 2;
@@ -189,7 +189,7 @@
gpio2: gpio@48055000 {
compatible = ti,omap4-gpio;
reg = 0x48055000 0x200;
- interrupts = GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio2;
gpio-controller;
#gpio-cells = 2;
@@ -200,7 +200,7 @@
gpio3: gpio@48057000 {
compatible = ti,omap4-gpio;
reg = 0x48057000 0x200;
- interrupts = GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio3;
gpio-controller;
#gpio-cells = 2;
@@ -211,7 +211,7 @@
gpio4: gpio@48059000 {
compatible = ti,omap4-gpio;
reg = 0x48059000 0x200;
- interrupts = GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio4;
gpio-controller;
#gpio-cells = 2;
@@ -222,7 +222,7 @@
gpio5: gpio@4805b000 {
compatible = ti,omap4-gpio;
reg = 0x4805b000 0x200;
- interrupts = GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio5;
gpio-controller;
#gpio-cells = 2;
@@ -233,7 +233,7 @@
gpio6: gpio@4805d000 {
compatible = ti,omap4-gpio;
reg = 0x4805d000 0x200;
- interrupts = GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio6;
gpio-controller;
#gpio-cells = 2;
@@ -244,7 +244,7 @@
gpio7: gpio@48051000 {
compatible = ti,omap4-gpio;
reg = 0x48051000 0x200;
- interrupts = GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio7;
gpio-controller;
#gpio-cells = 2;
@@ -255,7 +255,7 @@
gpio8: gpio@48053000 {
compatible = ti,omap4-gpio;
reg = 0x48053000 0x200;
- interrupts = GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH
[RESEND Patch 5/9] ARM: dts: OMAP4: Add device nodes for ABB
From: Andrii.Tseglytskyi andrii.tseglyts...@ti.com
Add ABB device nodes for OMAP443x family of devices. abb_iva is
populated, but disabled as it is not used on current OMAP443x family,
but the node is used on OMAP446x family. Data is based on OMAP443x
Technical Reference Manual revision AN (April 2013).
ABB device nodes for OMAP4460 device Data is based on OMAP4460
Technical Reference Manual revision Z (April 2013)
[n...@ti.com: co-developer]
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Andrii.Tseglytskyi andrii.tseglyts...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/omap4.dtsi| 26 ++
arch/arm/boot/dts/omap443x.dtsi | 26 ++
arch/arm/boot/dts/omap4460.dtsi | 37 +
3 files changed, 89 insertions(+)
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index afa23bc..c18f0fd 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -776,6 +776,32 @@
dmas = sdma 117, sdma 116;
dma-names = tx, rx;
};
+
+ abb_mpu: regulator-abb-mpu {
+ compatible = ti,abb-v2;
+ regulator-name = abb_mpu;
+ #address-cells = 0;
+ #size-cells = 0;
+ ti,tranxdone-status-mask = 0x80;
+ clocks = sys_clkin_ck;
+ ti,settling-time = 50;
+ ti,clock-cycles = 16;
+
+ status = disabled;
+ };
+
+ abb_iva: regulator-abb-iva {
+ compatible = ti,abb-v2;
+ regulator-name = abb_iva;
+ #address-cells = 0;
+ #size-cells = 0;
+ ti,tranxdone-status-mask = 0x8000;
+ clocks = sys_clkin_ck;
+ ti,settling-time = 50;
+ ti,clock-cycles = 16;
+
+ status = disabled;
+ };
};
};
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index 8c1cfad..0adfa1d 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -43,6 +43,32 @@
#thermal-sensor-cells = 0;
};
};
+
+ ocp {
+ abb_mpu: regulator-abb-mpu {
+ status = okay;
+
+ reg = 0x4a307bd0 0x8, 0x4a306014 0x4;
+ reg-names = base-address, int-address;
+
+ ti,abb_info =
+ /*uVABB efuse rbb_m fbb_m vset_m*/
+ 1025000 0 0 0 0 0
+ 120 0 0 0 0 0
+ 1313000 0 0 0 0 0
+ 1375000 1 0 0 0 0
+ 1389000 1 0 0 0 0
+ ;
+ };
+
+ /* Default unused, just provide register info for record */
+ abb_iva: regulator-abb-iva {
+ reg = 0x4a307bd8 0x8, 0x4a306010 0x4;
+ reg-names = base-address, int-address;
+ };
+
+ };
+
};
/include/ omap443x-clocks.dtsi
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 6b32f52..194f9ef 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -50,7 +50,44 @@
#thermal-sensor-cells = 0;
};
+
+ abb_mpu: regulator-abb-mpu {
+ status = okay;
+
+ reg = 0x4a307bd0 0x8, 0x4a306014 0x4,
+ 0x4A002268 0x4;
+ reg-names = base-address, int-address,
+ efuse-address;
+
+ ti,abb_info =
+ /*uVABB efuse rbb_m fbb_m vset_m*/
+ 1025000 0 0 0 0 0
+ 120 0 0 0 0 0
+ 1313000 0 0 0x10 0x4 0
+ 1375000 1 0 0 0 0
+ 1389000 1 0 0 0 0
+ ;
+ };
+
+ abb_iva: regulator-abb-iva {
+ status = okay;
+
+ reg = 0x4a307bd8 0x8, 0x4a306010 0x4,
+ 0x4A002268 0x4;
+ reg-names = base-address, int-address,
+ efuse-address;
+
+ ti
[RESEND Patch 7/9] ARM: DTS: DRA7: Add crossbar device binding
From: Sricharan R r.sricha...@ti.com
This adds the irq crossbar device node.
There is a IRQ crossbar device in the soc, which
maps the irq requests from the peripherals to the
mpu interrupt controller's inputs. The Peripheral irq
requests are connected to only one crossbar
input and the output of the crossbar is connected to only one
controller's input line. The crossbar device is used to map
a peripheral input to a free mpu's interrupt controller line.
Cc: Benoit Cousson bcous...@baylibre.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Tony Lindgren t...@atomide.com
Signed-off-by: Sricharan R r.sricha...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 9e3caf3..88fc2eb 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -773,6 +773,14 @@
status = disabled;
};
};
+
+ crossbar_mpu: crossbar@4a02 {
+ compatible = ti,irq-crossbar;
+ reg = 0x4a002a48 0x130;
+ ti,max-irqs = 160;
+ ti,reg-size = 2;
+ ti,irqs-reserved = 0 1 2 3 5 6 131 132 139 140;
+ };
};
/include/ dra7xx-clocks.dtsi
--
1.9.0
--
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