Re: [PATCH 2/2] rtc: omap: Add external clock enabling support
On Friday 14 August 2015 02:03 PM, Alexandre Belloni wrote:
On 13/08/2015 at 12:37:48 +0530, Keerthy wrote :
Configure the clock source to either internal clock
or external clock based on the availability of the clocks.
External clock is preferred as it can be ticking during suspend.
Signed-off-by: Keerthy j-keer...@ti.com
---
drivers/rtc/rtc-omap.c | 44
1 file changed, 44 insertions(+)
diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c
index 8b6355f..479f730 100644
--- a/drivers/rtc/rtc-omap.c
+++ b/drivers/rtc/rtc-omap.c
@@ -25,6 +25,7 @@
#include linux/of_device.h
#include linux/pm_runtime.h
#include linux/io.h
+#include linux/clk.h
/*
* The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock
@@ -107,6 +108,7 @@
/* OMAP_RTC_OSC_REG bit fields: */
#define OMAP_RTC_OSC_32KCLK_ENBIT(6)
+#define OMAP_RTC_OSC_SEL_32KCLK_SRCBIT(3)
/* OMAP_RTC_IRQWAKEEN bit fields: */
#define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1)
@@ -136,6 +138,7 @@ struct omap_rtc {
int irq_timer;
u8 interrupts_reg;
bool is_pmic_controller;
+ bool has_ext_clk;
const struct omap_rtc_device_type *type;
};
@@ -525,6 +528,7 @@ static int omap_rtc_probe(struct platform_device *pdev)
{
struct omap_rtc *rtc;
struct resource *res;
+ struct clk *ext_clk, *int_clk;
u8 reg, mask, new_ctrl;
const struct platform_device_id *id_entry;
const struct of_device_id *of_id;
@@ -553,6 +557,17 @@ static int omap_rtc_probe(struct platform_device *pdev)
if (rtc-irq_alarm = 0)
return -ENOENT;
+ ext_clk = devm_clk_get(pdev-dev, ext-clk);
+ if (!IS_ERR(ext_clk)) {
+ rtc-has_ext_clk = true;
+ clk_prepare(ext_clk);
I'd say this has to be prepare_enable because you are not enabling those
clocks anywhere
+ } else {
+ int_clk = devm_clk_get(pdev-dev, int-clk);
+
+ if (!IS_ERR(int_clk))
+ clk_prepare(int_clk);
+ }
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
rtc-base = devm_ioremap_resource(pdev-dev, res);
if (IS_ERR(rtc-base))
@@ -627,6 +642,17 @@ static int omap_rtc_probe(struct platform_device *pdev)
if (reg != new_ctrl)
rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl);
+ /*
+* If we have the external clock then
+* Switch to external clock so we can keep ticking
+* acorss suspend
+*/
+ if (rtc-has_ext_clk) {
+ reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
+ rtc_write(rtc, OMAP_RTC_OSC_REG, reg |
+ OMAP_RTC_OSC_SEL_32KCLK_SRC);
+ }
+
rtc-type-lock(rtc);
device_init_wakeup(pdev-dev, true);
@@ -672,6 +698,8 @@ err:
static int __exit omap_rtc_remove(struct platform_device *pdev)
{
struct omap_rtc *rtc = platform_get_drvdata(pdev);
+ struct clk *ext_clk, *int_clk;
+ u8 reg;
if (pm_power_off == omap_rtc_power_off
omap_rtc_power_off_rtc == rtc) {
@@ -681,10 +709,26 @@ static int __exit omap_rtc_remove(struct platform_device
*pdev)
device_init_wakeup(pdev-dev, 0);
+ ext_clk = devm_clk_get(pdev-dev, ext-clk);
+ if (!IS_ERR(ext_clk)) {
+ clk_unprepare(ext_clk);
+ } else {
+ int_clk = devm_clk_get(pdev-dev, int-clk);
+
+ if (!IS_ERR(int_clk))
+ clk_unprepare(int_clk);
+ }
+
You can probably add ext_clk and int_clk to struct omap_rtc and avoid
those devm_clk_get.
Since both int_clk and ext_clk are mutual exclusive, you can have only
one variable.
Thanks,
Vaibhav
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[PATCH 0/2] ARM: AM33XX: clock: Add debugSS data to clk and hwmod database
This patch adds DebugSS data to clock-tree and hwmod data files. Changes from RFC/V1 (No code change): - Based on comments, we have to follow DT and loadable module approach for debugSS module as well, so separated out 2 patches of clock-tree and hwmod data addition from the RFC patch-series. - Added Paul's Ack on clock-tree patch. - Rebased on top of Benoit's for-3.11/dts branch. Link to original RFC - http://archive.arm.linux.org.uk/lurker/message/20130304.113554.53c9ec25.en.html Vaibhav Hiremath (2): ARM: AM33XX: clock: Add debugSS clock nodes ARM: AM33XX: hwmod: Add hwmod data for debugSS arch/arm/mach-omap2/cclock33xx_data.c | 47 +-- arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 69 +++- 2 files changed, 89 insertions(+), 27 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ARM: AM33XX: clock: Add debugSS clock nodes
Represent debugSS clock interface as provided in
CM_WKUP_DEBUGSS_CLKCTRL register, includes
- Clock gate for optional DEBUG_CLKA and DBGSYSCLK
- Clock Mux for TRC_PMD and STM_PMD
- Clock divider for STM and TPIU
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Acked-by: Paul Walmsley p...@pwsan.com
Cc: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/cclock33xx_data.c | 47 +---
1 files changed, 42 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c
b/arch/arm/mach-omap2/cclock33xx_data.c
index af3544c..6fd0ed1 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -431,15 +431,11 @@ DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents,
clk_ops_null);
* - Driver code is not yet migrated to use hwmod/runtime pm
* - Modules outside kernel access (to disable them by default)
*
- * - debugss
* - mmu (gfx domain)
* - cefuse
* - usbotg_fck (its additional clock and not really a modulemode)
* - ieee5000
*/
-DEFINE_CLK_GATE(debugss_ick, dpll_core_m4_ck, dpll_core_m4_ck, 0x0,
- AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
- 0x0, NULL);
DEFINE_CLK_GATE(mmu_fck, dpll_core_m4_ck, dpll_core_m4_ck, 0x0,
AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
@@ -863,6 +859,42 @@ static struct clk_hw_omap wdt1_fck_hw = {
DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
/*
+ * debugss optional clocks
+ */
+DEFINE_CLK_GATE(dbg_sysclk_ck, sys_clkin_ck, sys_clkin_ck,
+ 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+ AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(dbg_clka_ck, dpll_core_m4_ck, dpll_core_m4_ck,
+ 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+ AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL);
+
+static const char *stm_pmd_clock_mux_ck_parents[] = {
+ dbg_sysclk_ck, dbg_clka_ck,
+};
+
+DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
+ AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT,
+ AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
+ AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+ AM33XX_TRC_PMD_CLKSEL_SHIFT,
+ AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_DIVIDER(stm_clk_div_ck, stm_pmd_clock_mux_ck,
+ stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+ AM33XX_STM_PMD_CLKDIVSEL_SHIFT,
+ AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
+ NULL);
+
+DEFINE_CLK_DIVIDER(trace_clk_div_ck, trace_pmd_clk_mux_ck,
+ trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+ AM33XX_TRC_PMD_CLKDIVSEL_SHIFT,
+ AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
+ NULL);
+
+/*
* clkdev
*/
static struct omap_clk am33xx_clks[] = {
@@ -899,7 +931,6 @@ static struct omap_clk am33xx_clks[] = {
CLK(481cc000.d_can, NULL, dcan0_fck),
CLK(NULL, dcan1_fck,dcan1_fck),
CLK(481d.d_can, NULL, dcan1_fck),
- CLK(NULL, debugss_ick, debugss_ick),
CLK(NULL, pruss_ocp_gclk, pruss_ocp_gclk),
CLK(NULL, mcasp0_fck, mcasp0_fck),
CLK(NULL, mcasp1_fck, mcasp1_fck),
@@ -942,6 +973,12 @@ static struct omap_clk am33xx_clks[] = {
CLK(NULL, clkout2_div_ck, clkout2_div_ck),
CLK(NULL, timer_32k_ck, clkdiv32k_ick),
CLK(NULL, timer_sys_ck, sys_clkin_ck),
+ CLK(NULL, dbg_sysclk_ck,dbg_sysclk_ck),
+ CLK(NULL, dbg_clka_ck, dbg_clka_ck),
+ CLK(NULL, stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck),
+ CLK(NULL, trace_pmd_clk_mux_ck, trace_pmd_clk_mux_ck),
+ CLK(NULL, stm_clk_div_ck, stm_clk_div_ck),
+ CLK(NULL, trace_clk_div_ck, trace_clk_div_ck),
};
--
1.7.0.4
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[PATCH 2/2] ARM: AM33XX: hwmod: Add hwmod data for debugSS
In the original hwmod data file, DebugSS entry was disabled,
since we didn't (and do not) have SW to control it.
This patch enables it back with right data, so that it can be
controlled by different ways; and the suggested method it to
have modular driver for debugSS as well.
Refer to the link for more discussion on handling of debugSS -
https://patchwork.kernel.org/patch/2212111/
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 69 +++-
1 files changed, 47 insertions(+), 22 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 075f7cc..2a4bf69 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -416,7 +416,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
*
*- cEFUSE (doesn't fall under any ocp_if)
*- clkdiv32k
- *- debugss
*- ocp watch point
*/
#if 0
@@ -460,27 +459,6 @@ static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
},
};
-/*
- * 'debugss' class
- * debug sub system
- */
-static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
- .name = debugss,
-};
-
-static struct omap_hwmod am33xx_debugss_hwmod = {
- .name = debugss,
- .class = am33xx_debugss_hwmod_class,
- .clkdm_name = l3_aon_clkdm,
- .main_clk = debugss_ick,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
/* ocpwp */
static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
.name = ocpwp,
@@ -598,6 +576,34 @@ static struct omap_hwmod am33xx_ocmcram_hwmod = {
},
};
+/*
+ * 'debugss' class
+ * debug sub system
+ */
+static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
+ { .role = dbg_sysclk, .clk = dbg_sysclk_ck },
+ { .role = dbg_clka, .clk = dbg_clka_ck },
+};
+
+static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
+ .name = debugss,
+};
+
+static struct omap_hwmod am33xx_debugss_hwmod = {
+ .name = debugss,
+ .class = am33xx_debugss_hwmod_class,
+ .clkdm_name = l3_aon_clkdm,
+ .main_clk = trace_clk_div_ck,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = debugss_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks),
+};
+
/* 'smartreflex' class */
static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
.name = smartreflex,
@@ -2382,6 +2388,24 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l3_main - debugss */
+static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = {
+ {
+ .pa_start = 0x4b00,
+ .pa_end = 0x4b00 + SZ_16M - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
+ .master = am33xx_l3_main_hwmod,
+ .slave = am33xx_debugss_hwmod,
+ .clk= dpll_core_m4_ck,
+ .addr = am33xx_debugss_addrs,
+ .user = OCP_USER_MPU,
+};
+
/* l4 wkup - smartreflex0 */
static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
{
@@ -3533,6 +3557,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[]
__initdata = {
am33xx_pruss__l3_main,
am33xx_wkup_m3__l4_wkup,
am33xx_gfx__l3_main,
+ am33xx_l3_main__debugss,
am33xx_l4_wkup__wkup_m3,
am33xx_l4_wkup__control,
am33xx_l4_wkup__smartreflex0,
--
1.7.0.4
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[PATCH-V2 0/2] ARM: OMAP AM33XX: clock data: Enable clkout2 output on SoC pad
'clkout2' comes out on the device pad and is being used by various external on-board peripherals like, Audio codecs, Wilink and stuff. So enable the clkout2 by default during init sequence itself along with right pinmux configuration clkout2 output. Also, add the missing entry of clkout2_ck to the AM33xx clock table. As far as enabling of clkout2 during init is concerned, we can argue that it can be handled using DT property and enable the clock only when specified; but not until OMAP clock-tree migration to DT. Changes from V1: - Fixed spelling mistake in dts file - Added Acked-by from 'Paul Walmsley' Vaibhav Hiremath (2): ARM: OMAP AM33XX: clock data: Enable clkout2 as part of init ARM: dts: AM33XX: Set pinmux for clkout2 pad used for clock output arch/arm/boot/dts/am335x-bone.dts |8 +++- arch/arm/boot/dts/am335x-evm.dts |8 +++- arch/arm/boot/dts/am335x-evmsk.dts|8 +++- arch/arm/mach-omap2/cclock33xx_data.c |2 ++ 4 files changed, 23 insertions(+), 3 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH-V2 1/2] ARM: OMAP AM33XX: clock data: Enable clkout2 as part of init
clkout2 comes out on the pad and is being used by various
external on-board peripherals like, Audio codecs and stuff.
So enable the clkout2 by default during init sequence itself.
Also, add the missing entry of clkout2_ck to the clock table.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Acked-by: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/cclock33xx_data.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c
b/arch/arm/mach-omap2/cclock33xx_data.c
index 6fd0ed1..a8140b6 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -979,6 +979,7 @@ static struct omap_clk am33xx_clks[] = {
CLK(NULL, trace_pmd_clk_mux_ck, trace_pmd_clk_mux_ck),
CLK(NULL, stm_clk_div_ck, stm_clk_div_ck),
CLK(NULL, trace_clk_div_ck, trace_clk_div_ck),
+ CLK(NULL, clkout2_ck, clkout2_ck),
};
@@ -989,6 +990,7 @@ static const char *enable_init_clks[] = {
l4hs_gclk,
l4fw_gclk,
l4ls_gclk,
+ clkout2_ck, /* Required for external peripherals like, Audio codecs
*/
};
int __init am33xx_clk_init(void)
--
1.7.0.4
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[PATCH-V2 2/2] ARM: dts: AM33XX: Set pinmux for clkout2 pad used for clock output
xdma_event_intr1.clkout2 pad can be used to source clock
from either 32K OSC or any of the PLL (except MPU) outputs.
On the existing AM335x based boards (EVM, EVM-SK and Bone),
this pad is used to feed the clock to audio codes.
So, this patch configures the pinmux to get clkout2 on the pad.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
---
arch/arm/boot/dts/am335x-bone.dts |8 +++-
arch/arm/boot/dts/am335x-evm.dts |8 +++-
arch/arm/boot/dts/am335x-evmsk.dts |8 +++-
3 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index bfba6fc..74bfcc6 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -26,7 +26,7 @@
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = default;
- pinctrl-0 = ;
+ pinctrl-0 = clkout2_pin;
user_leds_s0: user_leds_s0 {
pinctrl-single,pins =
@@ -50,6 +50,12 @@
0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN
| MODE0 */
;
};
+
+ clkout2_pin: pinmux_clkout2_pin {
+ pinctrl-single,pins =
+ 0x1b4 0x03 /* xdma_event_intr1.clkout2
OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+ ;
+ };
};
ocp {
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 7647c9d..896d392 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -26,7 +26,7 @@
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = default;
- pinctrl-0 = matrix_keypad_s0 volume_keys_s0;
+ pinctrl-0 = matrix_keypad_s0 volume_keys_s0 clkout2_pin;
matrix_keypad_s0: matrix_keypad_s0 {
pinctrl-single,pins =
@@ -65,6 +65,12 @@
0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN
| MODE0 */
;
};
+
+ clkout2_pin: pinmux_clkout2_pin {
+ pinctrl-single,pins =
+ 0x1b4 0x03 /* xdma_event_intr1.clkout2
OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+ ;
+ };
};
ocp {
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index 0eec644..4d81dbc 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -32,7 +32,7 @@
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = default;
- pinctrl-0 = gpio_keys_s0;
+ pinctrl-0 = gpio_keys_s0 clkout2_pin;
user_leds_s0: user_leds_s0 {
pinctrl-single,pins =
@@ -65,6 +65,12 @@
0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN
| MODE0 */
;
};
+
+ clkout2_pin: pinmux_clkout2_pin {
+ pinctrl-single,pins =
+ 0x1b4 0x03 /* xdma_event_intr1.clkout2
OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+ ;
+ };
};
ocp {
--
1.7.0.4
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[PATCH-V2] ARM: OMAP2+: AM33xx: Fix missing reset status data to GFX hwmod
GFX has a reset status register (PRM_GFX.RM_GFX_RSTST),
so update the GFX hwmod data with .rstst_off and .st_shift
information.
Although it doesn't have impact on kernel boot, but this is
regression fix from original hwmod commit.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Tony Lindgren t...@atomide.com
---
Changes from V1 (No code change):
- Updated commit description to mention its regression
from original commit.
arch/arm/mach-omap2/omap_hwmod_33xx_data.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index d1cf3ab..38c7b04 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -329,7 +329,7 @@ static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
};
static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
- { .name = gfx, .rst_shift = 0 },
+ { .name = gfx, .rst_shift = 0, .st_shift = 0},
};
static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
@@ -347,6 +347,7 @@ static struct omap_hwmod am33xx_gfx_hwmod = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
.rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
+ .rstst_offs = AM33XX_RM_GFX_RSTST_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
--
1.7.0.4
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[PATCH-V2] ARM: OMAP3+: am33xx id: Add new am33xx specific function to check dev_feature
Layout of DEV_FEATURE register (offset = 0x604) is different
between TI81xx and AM33xx device, so create separate function
which will check for features available on specific AM33xx SoC
and set the flags accordingly.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Reviewed-by: Kevin Hilman khil...@linaro.org
---
Changes from V1:
- Removed SHIFT value, as it never gets used in code
- Used BIT() macro for MASK definition
arch/arm/mach-omap2/control.h |4
arch/arm/mach-omap2/id.c | 13 +
arch/arm/mach-omap2/io.c |2 +-
arch/arm/mach-omap2/soc.h |1 +
4 files changed, 19 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index e6c3281..174eb41 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -358,6 +358,10 @@
#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2
#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK(0x3 22)
+/* DEV Feature register to identify AM33XX features */
+#define AM33XX_DEV_FEATURE 0x604
+#define AM33XX_SGX_MASKBIT(29)
+
/* CONTROL OMAP STATUS register to identify OMAP3 features */
#define OMAP3_CONTROL_OMAP_STATUS 0x044c
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 1272c41..44be835 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -302,6 +302,19 @@ void __init ti81xx_check_features(void)
omap3_cpuinfo();
}
+void __init am33xx_check_features(void)
+{
+ u32 status;
+
+ omap_features = OMAP3_HAS_NEON;
+
+ status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
+ if (status AM33XX_SGX_MASK)
+ omap_features |= OMAP3_HAS_SGX;
+
+ omap3_cpuinfo();
+}
+
void __init omap3xxx_check_revision(void)
{
const char *cpu_rev;
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 09abf99..06a8946 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -576,7 +576,7 @@ void __init am33xx_init_early(void)
omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
omap3xxx_check_revision();
- ti81xx_check_features();
+ am33xx_check_features();
am33xx_voltagedomains_init();
am33xx_powerdomains_init();
am33xx_clockdomains_init();
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 197cc16..fd4507b 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -424,6 +424,7 @@ void omap4xxx_check_revision(void);
void omap5xxx_check_revision(void);
void omap3xxx_check_features(void);
void ti81xx_check_features(void);
+void am33xx_check_features(void);
void omap4xxx_check_features(void);
/*
--
1.7.0.4
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[PATCH] ARM: OMAP3+: am33xx id: Add new am33xx specific function to check dev_feature
Layout of DEV_FEATURE register (offset = 0x604) is different
between TI81xx and AM33xx device, so create separate function
which will check for features available on specific AM33xx SoC
and set the flags accordingly.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
---
arch/arm/mach-omap2/control.h |5 +
arch/arm/mach-omap2/id.c | 13 +
arch/arm/mach-omap2/io.c |2 +-
arch/arm/mach-omap2/soc.h |1 +
4 files changed, 20 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index e6c3281..4acdfc5 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -358,6 +358,11 @@
#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2
#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK(0x3 22)
+/* DEV Feature register to identify AM33XX features */
+#define AM33XX_DEV_FEATURE 0x604
+#define AM33XX_SGX_SHIFT 29
+#define AM33XX_SGX_MASK(1 AM33XX_SGX_SHIFT)
+
/* CONTROL OMAP STATUS register to identify OMAP3 features */
#define OMAP3_CONTROL_OMAP_STATUS 0x044c
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 9bc5a18..02feef7 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -302,6 +302,19 @@ void __init ti81xx_check_features(void)
omap3_cpuinfo();
}
+void __init am33xx_check_features(void)
+{
+ u32 status;
+
+ omap_features = OMAP3_HAS_NEON;
+
+ status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
+ if (status AM33XX_SGX_MASK)
+ omap_features |= OMAP3_HAS_SGX;
+
+ omap3_cpuinfo();
+}
+
void __init omap3xxx_check_revision(void)
{
const char *cpu_rev;
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 09abf99..06a8946 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -576,7 +576,7 @@ void __init am33xx_init_early(void)
omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
omap3xxx_check_revision();
- ti81xx_check_features();
+ am33xx_check_features();
am33xx_voltagedomains_init();
am33xx_powerdomains_init();
am33xx_clockdomains_init();
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index ccef2dd..7d8722c 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -424,6 +424,7 @@ void omap4xxx_check_revision(void);
void omap5xxx_check_revision(void);
void omap3xxx_check_features(void);
void ti81xx_check_features(void);
+void am33xx_check_features(void);
void omap4xxx_check_features(void);
/*
--
1.7.0.4
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[PATCH 0/2] ARM: OMAP AM33XX: clock data: Enable clkout2 output on SoC pad
'clkout2' comes out on the device pad and is being used by various external on-board peripherals like, Audio codecs, Wilink and stuff. So enable the clkout2 by default during init sequence itself along with right pinmux configuration clkout2 output. Also, add the missing entry of clkout2_ck to the AM33xx clock table. As far as enabling of clkout2 during init is concerned, we can argue that it can be handled using DT property and enable the clock only when specified; but not until OMAP clock-tree migration to DT. Vaibhav Hiremath (2): ARM: OMAP AM33XX: clock data: Enable clkout2 as part of init ARM: dts: AM33XX: Set pinmux for clkout2 pad used for clock output arch/arm/boot/dts/am335x-bone.dts |8 +++- arch/arm/boot/dts/am335x-evm.dts |8 +++- arch/arm/boot/dts/am335x-evmsk.dts|8 +++- arch/arm/mach-omap2/cclock33xx_data.c |2 ++ 4 files changed, 23 insertions(+), 3 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] ARM: dts: AM33XX: Set pinmux for clkout2 pad used for clock output
xdma_event_intr1.clkout2 pad can be used to source clock
from either 32K OSC or any of the PLL (except MPU) outputs.
On the existing AM335x based boards (EVM, EVM-SK and Bone),
this pad is used to feed the clock to audio codes.
So, this patch configures the pinmux to get clkout2 on the pad.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
---
arch/arm/boot/dts/am335x-bone.dts |8 +++-
arch/arm/boot/dts/am335x-evm.dts |8 +++-
arch/arm/boot/dts/am335x-evmsk.dts |8 +++-
3 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index bfba6fc..f4630a3 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -26,7 +26,7 @@
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = default;
- pinctrl-0 = ;
+ pinctrl-0 = clkout2_pin;
user_leds_s0: user_leds_s0 {
pinctrl-single,pins =
@@ -50,6 +50,12 @@
0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN
| MODE0 */
;
};
+
+ clkout2_pin: pinumx_clkout2_pin {
+ pinctrl-single,pins =
+ 0x1b4 0x03 /* xdma_event_intr1.clkout2
OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+ ;
+ };
};
ocp {
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index f598ed2..0673308 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -26,7 +26,7 @@
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = default;
- pinctrl-0 = matrix_keypad_s0 volume_keys_s0;
+ pinctrl-0 = matrix_keypad_s0 volume_keys_s0 clkout2_pin;
matrix_keypad_s0: matrix_keypad_s0 {
pinctrl-single,pins =
@@ -65,6 +65,12 @@
0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN
| MODE0 */
;
};
+
+ clkout2_pin: pinumx_clkout2_pin {
+ pinctrl-single,pins =
+ 0x1b4 0x03 /* xdma_event_intr1.clkout2
OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+ ;
+ };
};
ocp {
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index 0eec644..a559389 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -32,7 +32,7 @@
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = default;
- pinctrl-0 = gpio_keys_s0;
+ pinctrl-0 = gpio_keys_s0 clkout2_pin;
user_leds_s0: user_leds_s0 {
pinctrl-single,pins =
@@ -65,6 +65,12 @@
0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN
| MODE0 */
;
};
+
+ clkout2_pin: pinumx_clkout2_pin {
+ pinctrl-single,pins =
+ 0x1b4 0x03 /* xdma_event_intr1.clkout2
OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+ ;
+ };
};
ocp {
--
1.7.0.4
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[PATCH 1/2] ARM: OMAP AM33XX: clock data: Enable clkout2 as part of init
clkout2 comes out on the pad and is being used by various
external on-board peripherals like, Audio codecs and stuff.
So enable the clkout2 by default during init sequence itself.
Also, add the missing entry of clkout2_ck to the clock table.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
---
arch/arm/mach-omap2/cclock33xx_data.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c
b/arch/arm/mach-omap2/cclock33xx_data.c
index 6fd0ed1..a8140b6 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -979,6 +979,7 @@ static struct omap_clk am33xx_clks[] = {
CLK(NULL, trace_pmd_clk_mux_ck, trace_pmd_clk_mux_ck),
CLK(NULL, stm_clk_div_ck, stm_clk_div_ck),
CLK(NULL, trace_clk_div_ck, trace_clk_div_ck),
+ CLK(NULL, clkout2_ck, clkout2_ck),
};
@@ -989,6 +990,7 @@ static const char *enable_init_clks[] = {
l4hs_gclk,
l4fw_gclk,
l4ls_gclk,
+ clkout2_ck, /* Required for external peripherals like, Audio codecs
*/
};
int __init am33xx_clk_init(void)
--
1.7.0.4
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[PATCH] ARM: OMAP2: AM33XX: id: Add support for new AM335x PG2.1 Si
Add support for chip id detection of AM335x PG2.1 Silicon. Currently omap3xxx_check_revision() detects PG1.0 and PG2.0 only, this patch extends it by adding PG2.1 Si support. Signed-off-by: Vaibhav Hiremath hvaib...@ti.com --- arch/arm/mach-omap2/id.c |8 ++-- arch/arm/mach-omap2/soc.h |1 + 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 0f4c18e..9bc5a18 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -419,11 +419,15 @@ void __init omap3xxx_check_revision(void) cpu_rev = 1.0; break; case 1: - /* FALLTHROUGH */ - default: omap_revision = AM335X_REV_ES2_0; cpu_rev = 2.0; break; + case 2: + /* FALLTHROUGH */ + default: + omap_revision = AM335X_REV_ES2_1; + cpu_rev = 2.1; + break; } break; case 0xb8f2: diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index 18fdeeb..ccef2dd 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h @@ -396,6 +396,7 @@ IS_OMAP_TYPE(3430, 0x3430) #define AM335X_CLASS 0x33500033 #define AM335X_REV_ES1_0 AM335X_CLASS #define AM335X_REV_ES2_0 (AM335X_CLASS | (0x1 8)) +#define AM335X_REV_ES2_1 (AM335X_CLASS | (0x2 8)) #define OMAP443X_CLASS 0x44300044 #define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 8)) -- 1.7.0.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: OMAP2+: AM33xx: Add missing reset status info to GFX hwmod
GFX has a reset status register (PRM_GFX.RM_GFX_RSTST),
so update the GFX hwmod data with .rstst_off and .st_shift
information.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index d1cf3ab..38c7b04 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -329,7 +329,7 @@ static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
};
static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
- { .name = gfx, .rst_shift = 0 },
+ { .name = gfx, .rst_shift = 0, .st_shift = 0},
};
static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
@@ -347,6 +347,7 @@ static struct omap_hwmod am33xx_gfx_hwmod = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
.rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
+ .rstst_offs = AM33XX_RM_GFX_RSTST_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
--
1.7.0.4
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[PATCH 0/2] ARM: OMAP2+: AM33xx: Add sysconf info to wdt1 hwmod data
With the recent submitted patch from Santosh Shilimkar, ARM: OMAP2+: hwmod: Don't call _init_mpu_rt_base if no sysc (commit: 4a98c2d89), kernel is crashing while accessing wdt1 module without sysconf information, so add sysconf information to the wdt1 hwmod data. And also switch wdt1 parent clock to PRCM generated 32K clock-source during boot-time, as default On-Chip 32K RC Osc clock is not an accurate by design. Vaibhav Hiremath (2): ARM: OMAP2+: AM33xx: hwmod: Add missing sysc definition to wdt1 entry ARM: OMAP2+: am335x: Change the wdt1 func clk src to per_32k clk arch/arm/mach-omap2/cclock33xx_data.c |8 arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 15 +++ 2 files changed, 23 insertions(+), 0 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] ARM: OMAP2+: am335x: Change the wdt1 func clk src to per_32k clk
WDT1 module can take one of the below clocks as input functional clock - - On-Chip 32K RC Osc [default/reset] - 32K from PRCM The On-Chip 32K RC Osc clock is not an accurate clock-source as per the design/spec, so as a result, for example, timer which supposed to get expired @60Sec, but will expire somewhere ~@40Sec, which is not expected by any use-case. The solution here is to switch the input clock-source to PRCM generated 32K clock-source during boot-time itself. Signed-off-by: Vaibhav Hiremath hvaib...@ti.com Cc: Santosh Shilimkar santosh.shilim...@ti.com Cc: Benoit Cousson benoit.cous...@linaro.org Cc: Paul Walmsley p...@pwsan.com --- arch/arm/mach-omap2/cclock33xx_data.c |8 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c index 8327721..11e07b1 100644 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ b/arch/arm/mach-omap2/cclock33xx_data.c @@ -978,6 +978,14 @@ int __init am33xx_clk_init(void) clk_set_parent(timer3_fck, sys_clkin_ck); clk_set_parent(timer6_fck, sys_clkin_ck); + /* +* The On-Chip 32K RC Osc clock is not an accurate clock-source as per +* the design/spec, so as a result, for example, timer which supposed +* to get expired @60Sec, but will expire somewhere ~@40Sec, which is +* not expected by any use-case, so change WDT1 clock source to PRCM +* 32KHz clock. +*/ + clk_set_parent(wdt1_fck, clkdiv32k_ick); return 0; } -- 1.7.0.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ARM: OMAP2+: AM33xx: hwmod: Add missing sysc definition to wdt1 entry
This patch adds sysc definitions to the wdt1 hwmod entry, which in-turn
makes sure that sysc idle bit-fields are configured to valid state on
enable/disable callbacks.
With the recent submitted patch from Santosh Shilimkar,
ARM: OMAP2+: hwmod: Don't call _init_mpu_rt_base if no sysc
(commit: 4a98c2d89), it is required to add sysconf
information to each valid hwmod entry, else device will not be
come out from idle state properly and leads to below kernel
crash -
[2.190237] Unhandled fault: external abort on non-linefetch (0x1028) at
0xf9e35034
[2.198325] Internal error: : 1028 [#1] SMP ARM
[2.203101] Modules linked in:
[2.206334] CPU: 0Not tainted (3.9.0-rc3-00059-gd114294#1)
[2.212679] PC is at omap_wdt_disable.clone.5+0xc/0x60
[2.218090] LR is at omap_wdt_probe+0x184/0x1fc
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Benoit Cousson benoit.cous...@linaro.org
Cc: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 15 +++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 61c98f1..3ce2ff8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -28,6 +28,7 @@
#include prm-regbits-33xx.h
#include i2c.h
#include mmc.h
+#include wd_timer.h
/*
* IP blocks
@@ -2087,8 +2088,21 @@ static struct omap_hwmod am33xx_uart6_hwmod = {
};
/* 'wd_timer' class */
+static struct omap_hwmod_class_sysconfig wdt_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x10,
+ .syss_offs = 0x14,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields= omap_hwmod_sysc_type1,
+};
+
static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
.name = wd_timer,
+ .sysc = wdt_sysc,
+ .pre_shutdown = omap2_wd_timer_disable,
};
/*
@@ -2099,6 +2113,7 @@ static struct omap_hwmod am33xx_wd_timer1_hwmod = {
.name = wd_timer2,
.class = am33xx_wd_timer_hwmod_class,
.clkdm_name = l4_wkup_clkdm,
+ .flags = HWMOD_SWSUP_SIDLE,
.main_clk = wdt1_fck,
.prcm = {
.omap4 = {
--
1.7.0.4
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[PATCH-V2 4/6] ARM: dts: AM33XX: Add pinctrl binding to gpio-leds node
Now gpio-leds driver is using devm_pinctrl_get_select_default()
api to set default pinmux configuration required for the
functionality of the driver, so this patch moves respective
pinctrl binding inside leds node.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
---
arch/arm/boot/dts/am335x-bone.dts |5 -
arch/arm/boot/dts/am335x-evmsk.dts |5 -
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index 860630b..1d623e4 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -26,7 +26,7 @@
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = default;
- pinctrl-0 = user_leds_s0;
+ pinctrl-0 = ;
user_leds_s0: user_leds_s0 {
pinctrl-single,pins =
@@ -65,6 +65,9 @@
};
leds {
+ pinctrl-names = default;
+ pinctrl-0 = user_leds_s0;
+
compatible = gpio-leds;
led@2 {
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index 15a3052..21d5a08 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -32,7 +32,7 @@
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = default;
- pinctrl-0 = user_leds_s0 gpio_keys_s0;
+ pinctrl-0 = gpio_keys_s0;
user_leds_s0: user_leds_s0 {
pinctrl-single,pins =
@@ -121,6 +121,9 @@
};
leds {
+ pinctrl-names = default;
+ pinctrl-0 = user_leds_s0;
+
compatible = gpio-leds;
led@1 {
--
1.7.0.4
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[PATCH-V2 3/6] ARM: dts: AM33XX: Fix gpio numbering to match hardware/TRM
With DT support, where naming convention is based on base-addr
and not id, so we should follow TRM/Spec numbering label.
This patch changes GPIO numbering as per TRM, as gpio0-3.
Matt Porter had submitted base patch sometime back but it
didn't make it to the mainline -
https://patchwork.kernel.org/patch/1433001/
Later DT nodes for gpio based keypad and led driver got
merged, so this fix needs to propagate to board dts files
as well.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Signed-off-by: Matt Porter mpor...@ti.com
Acked-by: Peter Korsgaard jac...@sunsite.dk
Cc: Benoit Cousson b-cous...@ti.com
---
arch/arm/boot/dts/am335x-bone.dts |8
arch/arm/boot/dts/am335x-evm.dts | 14 +++---
arch/arm/boot/dts/am335x-evmsk.dts | 16
arch/arm/boot/dts/am33xx.dtsi |8
4 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index c917efa..860630b 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -69,27 +69,27 @@
led@2 {
label = beaglebone:green:heartbeat;
- gpios = gpio2 21 0;
+ gpios = gpio1 21 0;
linux,default-trigger = heartbeat;
default-state = off;
};
led@3 {
label = beaglebone:green:mmc0;
- gpios = gpio2 22 0;
+ gpios = gpio1 22 0;
linux,default-trigger = mmc0;
default-state = off;
};
led@4 {
label = beaglebone:green:usr2;
- gpios = gpio2 23 0;
+ gpios = gpio1 23 0;
default-state = off;
};
led@5 {
label = beaglebone:green:usr3;
- gpios = gpio2 24 0;
+ gpios = gpio1 24 0;
default-state = off;
};
};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index db52d3c..79b3cc8 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -143,12 +143,12 @@
debounce-delay-ms = 5;
col-scan-delay-us = 2;
- row-gpios = gpio2 25 0/* Bank1, pin25 */
-gpio2 26 0/* Bank1, pin26 */
-gpio2 27 0; /* Bank1, pin27 */
+ row-gpios = gpio1 25 0/* Bank1, pin25 */
+gpio1 26 0/* Bank1, pin26 */
+gpio1 27 0; /* Bank1, pin27 */
- col-gpios = gpio2 21 0/* Bank1, pin21 */
-gpio2 22 0; /* Bank1, pin22 */
+ col-gpios = gpio1 21 0/* Bank1, pin21 */
+gpio1 22 0; /* Bank1, pin22 */
linux,keymap = 0x008b /* MENU */
0x019e /* BACK */
@@ -167,14 +167,14 @@
switch@9 {
label = volume-up;
linux,code = 115;
- gpios = gpio1 2 1;
+ gpios = gpio0 2 1; /* Bank0, pin2 */
gpio-key,wakeup;
};
switch@10 {
label = volume-down;
linux,code = 114;
- gpios = gpio1 3 1;
+ gpios = gpio0 3 1; /* Bank0, pin3 */
gpio-key,wakeup;
};
};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index 24e915c..15a3052 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -125,26 +125,26 @@
led@1 {
label = evmsk:green:usr0;
- gpios = gpio2 4 0;
+ gpios = gpio1 4 0;
default-state = off;
};
led@2 {
label = evmsk:green:usr1;
- gpios = gpio2 5 0;
+ gpios = gpio1 5 0;
default-state = off;
};
led@3 {
label = evmsk:green:mmc0;
- gpios = gpio2 6 0;
+ gpios = gpio1 6 0;
linux,default-trigger = mmc0;
default-state = off;
};
led@4 {
label = evmsk:green:heartbeat;
- gpios = gpio2 7 0;
+ gpios = gpio1 7 0;
linux,default-trigger = heartbeat
[PATCH-V2 2/6] ARM: dts: AM33XX: Add default pinctrl binding for I2C device
Add pin control binding for I2C device nodes in all
board specific DT files (as per current usage),
EVM: Both i2c0 and i2c1
EVM-SK and Bone: Only i2c0
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Acked-by: Matt Porter mpor...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
---
arch/arm/boot/dts/am335x-bone.dts | 10 ++
arch/arm/boot/dts/am335x-evm.dts | 20
arch/arm/boot/dts/am335x-evmsk.dts | 10 ++
3 files changed, 40 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index cdc8307..c917efa 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -36,6 +36,13 @@
0x60 0x17 /* gpmc_a8.gpio1_24,
OUTPUT_PULLUP | MODE7 */
;
};
+
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins =
+ 0x188 0x30 /* i2c0_sda.i2c0_sda PULLUP |
INPUTENABLE | MODE0 */
+ 0x18c 0x30 /* i2c0_scl.i2c0_scl PULLUP |
INPUTENABLE | MODE0 */
+ ;
+ };
};
ocp {
@@ -44,6 +51,9 @@
};
i2c0: i2c@44e0b000 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c0_pins;
+
status = okay;
clock-frequency = 40;
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index a6539ad..db52d3c 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -44,6 +44,20 @@
0x154 0x27 /* spi0_d0.gpio0_3, INPUT |
MODE7 */
;
};
+
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins =
+ 0x188 0x30 /* i2c0_sda.i2c0_sda PULLUP |
INPUTENABLE | MODE0 */
+ 0x18c 0x30 /* i2c0_scl.i2c0_scl PULLUP |
INPUTENABLE | MODE0 */
+ ;
+ };
+
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins =
+ 0x158 0x32 /* spi0_d1.i2c1_sda PULLUP |
INPUTENABLE | MODE2 */
+ 0x15c 0x32 /* spi0_cs0.i2c1_scl PULLUP |
INPUTENABLE | MODE2 */
+ ;
+ };
};
ocp {
@@ -52,6 +66,9 @@
};
i2c0: i2c@44e0b000 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c0_pins;
+
status = okay;
clock-frequency = 40;
@@ -61,6 +78,9 @@
};
i2c1: i2c@4802a000 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c1_pins;
+
status = okay;
clock-frequency = 10;
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index 45cb39a..24e915c 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -51,6 +51,13 @@
0x9c 0x27 /* gpmc_ben0_cle.gpio2_5, INPUT
| MODE7 */
;
};
+
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins =
+ 0x188 0x30 /* i2c0_sda.i2c0_sda PULLUP |
INPUTENABLE | MODE0 */
+ 0x18c 0x30 /* i2c0_scl.i2c0_scl PULLUP |
INPUTENABLE | MODE0 */
+ ;
+ };
};
ocp {
@@ -59,6 +66,9 @@
};
i2c0: i2c@44e0b000 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c0_pins;
+
status = okay;
clock-frequency = 40;
--
1.7.0.4
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[PATCH-V2 6/6] ARM: dts: AM33XX: Add default pinctrl binding for UART0 device
Add pin control binding for UART0 device nodes in all
board specific DT files.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Acked-by: Matt Porter mpor...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
---
arch/arm/boot/dts/am335x-bone.dts | 10 ++
arch/arm/boot/dts/am335x-evm.dts | 10 ++
arch/arm/boot/dts/am335x-evmsk.dts | 10 ++
3 files changed, 30 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index be2c501..bfba6fc 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -43,10 +43,20 @@
0x18c 0x30 /* i2c0_scl.i2c0_scl PULLUP |
INPUTENABLE | MODE0 */
;
};
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins =
+ 0x170 0x30 /* uart0_rxd.uart0_rxd PULLUP |
INPUTENABLE | MODE0 */
+ 0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN
| MODE0 */
+ ;
+ };
};
ocp {
uart0: serial@44e09000 {
+ pinctrl-names = default;
+ pinctrl-0 = uart0_pins;
+
status = okay;
};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 2f3f5be..f598ed2 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -58,10 +58,20 @@
0x15c 0x32 /* spi0_cs0.i2c1_scl PULLUP |
INPUTENABLE | MODE2 */
;
};
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins =
+ 0x170 0x30 /* uart0_rxd.uart0_rxd PULLUP |
INPUTENABLE | MODE0 */
+ 0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN
| MODE0 */
+ ;
+ };
};
ocp {
uart0: serial@44e09000 {
+ pinctrl-names = default;
+ pinctrl-0 = uart0_pins;
+
status = okay;
};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index bcd7028..0eec644 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -58,10 +58,20 @@
0x18c 0x30 /* i2c0_scl.i2c0_scl PULLUP |
INPUTENABLE | MODE0 */
;
};
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins =
+ 0x170 0x30 /* uart0_rxd.uart0_rxd PULLUP |
INPUTENABLE | MODE0 */
+ 0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN
| MODE0 */
+ ;
+ };
};
ocp {
uart0: serial@44e09000 {
+ pinctrl-names = default;
+ pinctrl-0 = uart0_pins;
+
status = okay;
};
--
1.7.0.4
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[PATCH-V2 0/6] ARM: dts: AM33XX: Cleanup and pinctrl binding support
This patch series fixes the numbering schema for I2C and GPIO module and adds the pin-control binding for I2C, UART, GPIO-LED across supported platforms (EVM, EVM-SK and Bone). I have divided patches based on functionality and _not_ into EVM/Board perspective. Changes from V1: (no code change from last version, except uart) - Added Acked-by from Matt Porter and Peter Korsgaard on couple of patches. - Added new patch (PATCH 5/6) in the series for UART indexing fix Vaibhav Hiremath (6): ARM: dts: AM33XX: Fix the i2c numbering to match hardware/TRM ARM: dts: AM33XX: Add default pinctrl binding for I2C device ARM: dts: AM33XX: Fix gpio numbering to match hardware/TRM ARM: dts: AM33XX: Add pinctrl binding to gpio-leds node ARM: dts: AM33XX: Fix uart numbering to match hardware/TRM ARM: dts: AM33XX: Add default pinctrl binding for UART0 device arch/arm/boot/dts/am335x-bone.dts | 37 +- arch/arm/boot/dts/am335x-evm.dts | 50 --- arch/arm/boot/dts/am335x-evmsk.dts | 45 arch/arm/boot/dts/am33xx.dtsi | 38 +- 4 files changed, 123 insertions(+), 47 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH-V2 5/6] ARM: dts: AM33XX: Fix uart numbering to match hardware/TRM
With DT support, where naming convention is based on base-addr
and not id, so we should follow TRM/Spec numbering label.
This patch changes UART numbering as per TRM, as uart0-5.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Acked-by: Matt Porter mpor...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Peter Korsgaard jac...@sunsite.dk
---
arch/arm/boot/dts/am335x-bone.dts |2 +-
arch/arm/boot/dts/am335x-evm.dts |2 +-
arch/arm/boot/dts/am335x-evmsk.dts |2 +-
arch/arm/boot/dts/am33xx.dtsi | 24
4 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index 1d623e4..be2c501 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -46,7 +46,7 @@
};
ocp {
- uart1: serial@44e09000 {
+ uart0: serial@44e09000 {
status = okay;
};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 79b3cc8..2f3f5be 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -61,7 +61,7 @@
};
ocp {
- uart1: serial@44e09000 {
+ uart0: serial@44e09000 {
status = okay;
};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index 21d5a08..bcd7028 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -61,7 +61,7 @@
};
ocp {
- uart1: serial@44e09000 {
+ uart0: serial@44e09000 {
status = okay;
};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index dd237de..565e05e 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -15,12 +15,12 @@
interrupt-parent = intc;
aliases {
- serial0 = uart1;
- serial1 = uart2;
- serial2 = uart3;
- serial3 = uart4;
- serial4 = uart5;
- serial5 = uart6;
+ serial0 = uart0;
+ serial1 = uart1;
+ serial2 = uart2;
+ serial3 = uart3;
+ serial4 = uart4;
+ serial5 = uart5;
};
cpus {
@@ -131,7 +131,7 @@
interrupts = 62;
};
- uart1: serial@44e09000 {
+ uart0: serial@44e09000 {
compatible = ti,omap3-uart;
ti,hwmods = uart1;
clock-frequency = 4800;
@@ -140,7 +140,7 @@
status = disabled;
};
- uart2: serial@48022000 {
+ uart1: serial@48022000 {
compatible = ti,omap3-uart;
ti,hwmods = uart2;
clock-frequency = 4800;
@@ -149,7 +149,7 @@
status = disabled;
};
- uart3: serial@48024000 {
+ uart2: serial@48024000 {
compatible = ti,omap3-uart;
ti,hwmods = uart3;
clock-frequency = 4800;
@@ -158,7 +158,7 @@
status = disabled;
};
- uart4: serial@481a6000 {
+ uart3: serial@481a6000 {
compatible = ti,omap3-uart;
ti,hwmods = uart4;
clock-frequency = 4800;
@@ -167,7 +167,7 @@
status = disabled;
};
- uart5: serial@481a8000 {
+ uart4: serial@481a8000 {
compatible = ti,omap3-uart;
ti,hwmods = uart5;
clock-frequency = 4800;
@@ -176,7 +176,7 @@
status = disabled;
};
- uart6: serial@481aa000 {
+ uart5: serial@481aa000 {
compatible = ti,omap3-uart;
ti,hwmods = uart6;
clock-frequency = 4800;
--
1.7.0.4
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[PATCH-V2 1/6] ARM: dts: AM33XX: Fix the i2c numbering to match hardware/TRM
With DT support, where naming convention is based on base-addr
and not id, so we should follow TRM/Spec numbering label.
This patch changes I2C numbering as per TRM, as I2C0, I2C1 and I2C2.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Acked-by: Matt Porter mpor...@ti.com
Acked-by: Peter Korsgaard jac...@sunsite.dk
Cc: Benoit Cousson b-cous...@ti.com
---
arch/arm/boot/dts/am335x-bone.dts |2 +-
arch/arm/boot/dts/am335x-evm.dts |4 ++--
arch/arm/boot/dts/am335x-evmsk.dts |2 +-
arch/arm/boot/dts/am33xx.dtsi |6 +++---
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index 11b240c..cdc8307 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -43,7 +43,7 @@
status = okay;
};
- i2c1: i2c@44e0b000 {
+ i2c0: i2c@44e0b000 {
status = okay;
clock-frequency = 40;
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index d649644..a6539ad 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -51,7 +51,7 @@
status = okay;
};
- i2c1: i2c@44e0b000 {
+ i2c0: i2c@44e0b000 {
status = okay;
clock-frequency = 40;
@@ -60,7 +60,7 @@
};
};
- i2c2: i2c@4802a000 {
+ i2c1: i2c@4802a000 {
status = okay;
clock-frequency = 10;
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index f5a6162..45cb39a 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -58,7 +58,7 @@
status = okay;
};
- i2c1: i2c@44e0b000 {
+ i2c0: i2c@44e0b000 {
status = okay;
clock-frequency = 40;
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 0957645..c38b2fa 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -185,7 +185,7 @@
status = disabled;
};
- i2c1: i2c@44e0b000 {
+ i2c0: i2c@44e0b000 {
compatible = ti,omap4-i2c;
#address-cells = 1;
#size-cells = 0;
@@ -195,7 +195,7 @@
status = disabled;
};
- i2c2: i2c@4802a000 {
+ i2c1: i2c@4802a000 {
compatible = ti,omap4-i2c;
#address-cells = 1;
#size-cells = 0;
@@ -205,7 +205,7 @@
status = disabled;
};
- i2c3: i2c@4819c000 {
+ i2c2: i2c@4819c000 {
compatible = ti,omap4-i2c;
#address-cells = 1;
#size-cells = 0;
--
1.7.0.4
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[PATCH-V2] ARM: AM33XX: Add missing .clkdm_name to clkdiv32k_ick clock
It is required to enable respective clock-domain before
enabling any clock/module inside that clock-domain.
During common-clock migration, .clkdm_name field got missed
for clkdiv32k_ick clock, which leaves clk_24mhz_clkdm
unused; so it will be disabled even if childs of this clock-domain
is enabled, which keeps child modules in idle mode.
This fixes the kernel crash observed on AM335xEVM-SK platform,
where clkdiv32_ick clock is being used as a gpio debounce clock
and since clkdiv32k_ick is in idle mode it leads to below crash -
Crash Log:
==
[2.598347] Unhandled fault: external abort on non-linefetch (0x1028) at
0xfa1ac150
[2.606434] Internal error: : 1028 [#1] SMP ARM
[2.611207] Modules linked in:
[2.614449] CPU: 0Not tainted (3.8.4-01382-g1f449cd-dirty #4)
[2.620973] PC is at _set_gpio_debounce+0x60/0x104
[2.626025] LR is at clk_enable+0x30/0x3c
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Rajendra Nayak rna...@ti.com
---
Change from V1 (no code change):
- Commit description updated as per Rajendra and Paul's
comment.
arch/arm/mach-omap2/cclock33xx_data.c | 26 +++---
1 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c
b/arch/arm/mach-omap2/cclock33xx_data.c
index 476b820..8327721 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -446,9 +446,29 @@ DEFINE_CLK_GATE(cefuse_fck, sys_clkin_ck, sys_clkin_ck,
0x0,
*/
DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, clk_24mhz, clk_24mhz, 0x0, 1, 732);
-DEFINE_CLK_GATE(clkdiv32k_ick, clkdiv32k_ck, clkdiv32k_ck, 0x0,
- AM33XX_CM_PER_CLKDIV32K_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
- 0x0, NULL);
+static struct clk clkdiv32k_ick;
+
+static const char *clkdiv32k_ick_parent_names[] = {
+ clkdiv32k_ck,
+};
+
+static const struct clk_ops clkdiv32k_ick_ops = {
+ .enable = omap2_dflt_clk_enable,
+ .disable= omap2_dflt_clk_disable,
+ .is_enabled = omap2_dflt_clk_is_enabled,
+ .init = omap2_init_clk_clkdm,
+};
+
+static struct clk_hw_omap clkdiv32k_ick_hw = {
+ .hw = {
+ .clk= clkdiv32k_ick,
+ },
+ .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL_SHIFT,
+ .clkdm_name = clk_24mhz_clkdm,
+};
+
+DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names,
clkdiv32k_ick_ops);
/* usbotg_fck is an additional clock and not really a modulemode */
DEFINE_CLK_GATE(usbotg_fck, dpll_per_ck, dpll_per_ck, 0x0,
--
1.7.0.4
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[PATCH 4/5] ARM: dts: AM33XX: Add pinctrl binding to gpio-leds node
Now gpio-leds driver is using devm_pinctrl_get_select_default()
api to set default pinmux configuration required for the
functionality of the driver, so this patch moves respective
pinctrl binding inside leds node.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
---
arch/arm/boot/dts/am335x-bone.dts |5 -
arch/arm/boot/dts/am335x-evmsk.dts |5 -
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index 860630b..1d623e4 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -26,7 +26,7 @@
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = default;
- pinctrl-0 = user_leds_s0;
+ pinctrl-0 = ;
user_leds_s0: user_leds_s0 {
pinctrl-single,pins =
@@ -65,6 +65,9 @@
};
leds {
+ pinctrl-names = default;
+ pinctrl-0 = user_leds_s0;
+
compatible = gpio-leds;
led@2 {
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index 15a3052..21d5a08 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -32,7 +32,7 @@
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = default;
- pinctrl-0 = user_leds_s0 gpio_keys_s0;
+ pinctrl-0 = gpio_keys_s0;
user_leds_s0: user_leds_s0 {
pinctrl-single,pins =
@@ -121,6 +121,9 @@
};
leds {
+ pinctrl-names = default;
+ pinctrl-0 = user_leds_s0;
+
compatible = gpio-leds;
led@1 {
--
1.7.0.4
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[PATCH 0/5] ARM: dts: AM33XX: Cleanup and pinctrl binding support
This patch series fixes the numbering schema for I2C and GPIO module and adds the pin-control binding for I2C, UART, GPIO-LED across supported platforms (EVM, EVM-SK and Bone). I have divided patches based on functionality and _not_ into EVM/Board perspective. Vaibhav Hiremath (5): ARM: dts: AM33XX: Fix the i2c numbering to match hardware/TRM ARM: dts: AM33XX: Add default pinctrl binding for I2C device ARM: dts: AM33XX: Fix gpio numbering to match hardware/TRM ARM: dts: AM33XX: Add pinctrl binding to gpio-leds node ARM: dts: AM33XX: Add default pinctrl binding for UART0 device arch/arm/boot/dts/am335x-bone.dts | 35 + arch/arm/boot/dts/am335x-evm.dts | 48 +-- arch/arm/boot/dts/am335x-evmsk.dts | 43 --- arch/arm/boot/dts/am33xx.dtsi | 14 +- 4 files changed, 108 insertions(+), 32 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 5/5] ARM: dts: AM33XX: Add default pinctrl binding for UART0 device
Add pin control binding for UART0 device nodes in all
board specific DT files.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
---
arch/arm/boot/dts/am335x-bone.dts | 10 ++
arch/arm/boot/dts/am335x-evm.dts | 10 ++
arch/arm/boot/dts/am335x-evmsk.dts | 10 ++
3 files changed, 30 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index 1d623e4..3c4c66f 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -43,10 +43,20 @@
0x18c 0x30 /* i2c0_scl.i2c0_scl PULLUP |
INPUTENABLE | MODE0 */
;
};
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins =
+ 0x170 0x30 /* uart0_rxd.uart0_rxd PULLUP |
INPUTENABLE | MODE0 */
+ 0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN
| MODE0 */
+ ;
+ };
};
ocp {
uart1: serial@44e09000 {
+ pinctrl-names = default;
+ pinctrl-0 = uart0_pins;
+
status = okay;
};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 79b3cc8..89e1edd 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -58,10 +58,20 @@
0x15c 0x32 /* spi0_cs0.i2c1_scl PULLUP |
INPUTENABLE | MODE2 */
;
};
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins =
+ 0x170 0x30 /* uart0_rxd.uart0_rxd PULLUP |
INPUTENABLE | MODE0 */
+ 0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN
| MODE0 */
+ ;
+ };
};
ocp {
uart1: serial@44e09000 {
+ pinctrl-names = default;
+ pinctrl-0 = uart0_pins;
+
status = okay;
};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index 21d5a08..0e7f1b8 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -58,10 +58,20 @@
0x18c 0x30 /* i2c0_scl.i2c0_scl PULLUP |
INPUTENABLE | MODE0 */
;
};
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins =
+ 0x170 0x30 /* uart0_rxd.uart0_rxd PULLUP |
INPUTENABLE | MODE0 */
+ 0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN
| MODE0 */
+ ;
+ };
};
ocp {
uart1: serial@44e09000 {
+ pinctrl-names = default;
+ pinctrl-0 = uart0_pins;
+
status = okay;
};
--
1.7.0.4
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[PATCH 1/5] ARM: dts: AM33XX: Fix the i2c numbering to match hardware/TRM
With DT support, where naming convention is based on base-addr
and not id, so we should follow TRM/Spec numbering label.
This patch changes I2C numbering as per TRM, as I2C0, I2C1 and I2C2.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
---
arch/arm/boot/dts/am335x-bone.dts |2 +-
arch/arm/boot/dts/am335x-evm.dts |4 ++--
arch/arm/boot/dts/am335x-evmsk.dts |2 +-
arch/arm/boot/dts/am33xx.dtsi |6 +++---
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index 11b240c..cdc8307 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -43,7 +43,7 @@
status = okay;
};
- i2c1: i2c@44e0b000 {
+ i2c0: i2c@44e0b000 {
status = okay;
clock-frequency = 40;
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index d649644..a6539ad 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -51,7 +51,7 @@
status = okay;
};
- i2c1: i2c@44e0b000 {
+ i2c0: i2c@44e0b000 {
status = okay;
clock-frequency = 40;
@@ -60,7 +60,7 @@
};
};
- i2c2: i2c@4802a000 {
+ i2c1: i2c@4802a000 {
status = okay;
clock-frequency = 10;
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index f5a6162..45cb39a 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -58,7 +58,7 @@
status = okay;
};
- i2c1: i2c@44e0b000 {
+ i2c0: i2c@44e0b000 {
status = okay;
clock-frequency = 40;
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 0957645..c38b2fa 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -185,7 +185,7 @@
status = disabled;
};
- i2c1: i2c@44e0b000 {
+ i2c0: i2c@44e0b000 {
compatible = ti,omap4-i2c;
#address-cells = 1;
#size-cells = 0;
@@ -195,7 +195,7 @@
status = disabled;
};
- i2c2: i2c@4802a000 {
+ i2c1: i2c@4802a000 {
compatible = ti,omap4-i2c;
#address-cells = 1;
#size-cells = 0;
@@ -205,7 +205,7 @@
status = disabled;
};
- i2c3: i2c@4819c000 {
+ i2c2: i2c@4819c000 {
compatible = ti,omap4-i2c;
#address-cells = 1;
#size-cells = 0;
--
1.7.0.4
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[PATCH 3/5] ARM: dts: AM33XX: Fix gpio numbering to match hardware/TRM
With DT support, where naming convention is based on base-addr
and not id, so we should follow TRM/Spec numbering label.
This patch changes GPIO numbering as per TRM, as gpio0-3.
Matt Porter had submitted base patch sometime back but it
didn't make it to the mainline -
https://patchwork.kernel.org/patch/1433001/
Later DT nodes for gpio based keypad and led driver got
merged, so this fix needs to propagate to board dts files
as well.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Signed-off-by: Matt Porter mpor...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
---
arch/arm/boot/dts/am335x-bone.dts |8
arch/arm/boot/dts/am335x-evm.dts | 14 +++---
arch/arm/boot/dts/am335x-evmsk.dts | 16
arch/arm/boot/dts/am33xx.dtsi |8
4 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index c917efa..860630b 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -69,27 +69,27 @@
led@2 {
label = beaglebone:green:heartbeat;
- gpios = gpio2 21 0;
+ gpios = gpio1 21 0;
linux,default-trigger = heartbeat;
default-state = off;
};
led@3 {
label = beaglebone:green:mmc0;
- gpios = gpio2 22 0;
+ gpios = gpio1 22 0;
linux,default-trigger = mmc0;
default-state = off;
};
led@4 {
label = beaglebone:green:usr2;
- gpios = gpio2 23 0;
+ gpios = gpio1 23 0;
default-state = off;
};
led@5 {
label = beaglebone:green:usr3;
- gpios = gpio2 24 0;
+ gpios = gpio1 24 0;
default-state = off;
};
};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index db52d3c..79b3cc8 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -143,12 +143,12 @@
debounce-delay-ms = 5;
col-scan-delay-us = 2;
- row-gpios = gpio2 25 0/* Bank1, pin25 */
-gpio2 26 0/* Bank1, pin26 */
-gpio2 27 0; /* Bank1, pin27 */
+ row-gpios = gpio1 25 0/* Bank1, pin25 */
+gpio1 26 0/* Bank1, pin26 */
+gpio1 27 0; /* Bank1, pin27 */
- col-gpios = gpio2 21 0/* Bank1, pin21 */
-gpio2 22 0; /* Bank1, pin22 */
+ col-gpios = gpio1 21 0/* Bank1, pin21 */
+gpio1 22 0; /* Bank1, pin22 */
linux,keymap = 0x008b /* MENU */
0x019e /* BACK */
@@ -167,14 +167,14 @@
switch@9 {
label = volume-up;
linux,code = 115;
- gpios = gpio1 2 1;
+ gpios = gpio0 2 1; /* Bank0, pin2 */
gpio-key,wakeup;
};
switch@10 {
label = volume-down;
linux,code = 114;
- gpios = gpio1 3 1;
+ gpios = gpio0 3 1; /* Bank0, pin3 */
gpio-key,wakeup;
};
};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index 24e915c..15a3052 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -125,26 +125,26 @@
led@1 {
label = evmsk:green:usr0;
- gpios = gpio2 4 0;
+ gpios = gpio1 4 0;
default-state = off;
};
led@2 {
label = evmsk:green:usr1;
- gpios = gpio2 5 0;
+ gpios = gpio1 5 0;
default-state = off;
};
led@3 {
label = evmsk:green:mmc0;
- gpios = gpio2 6 0;
+ gpios = gpio1 6 0;
linux,default-trigger = mmc0;
default-state = off;
};
led@4 {
label = evmsk:green:heartbeat;
- gpios = gpio2 7 0;
+ gpios = gpio1 7 0;
linux,default-trigger = heartbeat;
default-state
[PATCH 2/5] ARM: dts: AM33XX: Add default pinctrl binding for I2C device
Add pin control binding for I2C device nodes in all
board specific DT files (as per current usage),
EVM: Both i2c0 and i2c1
EVM-SK and Bone: Only i2c0
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
---
arch/arm/boot/dts/am335x-bone.dts | 10 ++
arch/arm/boot/dts/am335x-evm.dts | 20
arch/arm/boot/dts/am335x-evmsk.dts | 10 ++
3 files changed, 40 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index cdc8307..c917efa 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -36,6 +36,13 @@
0x60 0x17 /* gpmc_a8.gpio1_24,
OUTPUT_PULLUP | MODE7 */
;
};
+
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins =
+ 0x188 0x30 /* i2c0_sda.i2c0_sda PULLUP |
INPUTENABLE | MODE0 */
+ 0x18c 0x30 /* i2c0_scl.i2c0_scl PULLUP |
INPUTENABLE | MODE0 */
+ ;
+ };
};
ocp {
@@ -44,6 +51,9 @@
};
i2c0: i2c@44e0b000 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c0_pins;
+
status = okay;
clock-frequency = 40;
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index a6539ad..db52d3c 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -44,6 +44,20 @@
0x154 0x27 /* spi0_d0.gpio0_3, INPUT |
MODE7 */
;
};
+
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins =
+ 0x188 0x30 /* i2c0_sda.i2c0_sda PULLUP |
INPUTENABLE | MODE0 */
+ 0x18c 0x30 /* i2c0_scl.i2c0_scl PULLUP |
INPUTENABLE | MODE0 */
+ ;
+ };
+
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins =
+ 0x158 0x32 /* spi0_d1.i2c1_sda PULLUP |
INPUTENABLE | MODE2 */
+ 0x15c 0x32 /* spi0_cs0.i2c1_scl PULLUP |
INPUTENABLE | MODE2 */
+ ;
+ };
};
ocp {
@@ -52,6 +66,9 @@
};
i2c0: i2c@44e0b000 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c0_pins;
+
status = okay;
clock-frequency = 40;
@@ -61,6 +78,9 @@
};
i2c1: i2c@4802a000 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c1_pins;
+
status = okay;
clock-frequency = 10;
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index 45cb39a..24e915c 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -51,6 +51,13 @@
0x9c 0x27 /* gpmc_ben0_cle.gpio2_5, INPUT
| MODE7 */
;
};
+
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins =
+ 0x188 0x30 /* i2c0_sda.i2c0_sda PULLUP |
INPUTENABLE | MODE0 */
+ 0x18c 0x30 /* i2c0_scl.i2c0_scl PULLUP |
INPUTENABLE | MODE0 */
+ ;
+ };
};
ocp {
@@ -59,6 +66,9 @@
};
i2c0: i2c@44e0b000 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c0_pins;
+
status = okay;
clock-frequency = 40;
--
1.7.0.4
--
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[PATCH] ARM: AM33XX: Add missing .clkdm_name to clkdiv32k_ick clock
During common-clock migration, .clkdm_name field got missed for clkdiv32k_ick clock, which leaves clk_24mhz_clkdm unused; so boot process will try to disable the clockdomain even childs of this clock is enabled, which keeps child modules in idle mode. This fixes the kernel crash observed on AM335xEVM-Sk platform, where clkdiv32_ick clock is being used as a gpio debounce clock and since clkdiv32k_ick is in idle mode it leads to below crash - Crash Log: = [2.598347] Unhandled fault: external abort on non-linefetch (0x1028) at 0xfa1ac150 [2.606434] Internal error: : 1028 [#1] SMP ARM [2.611207] Modules linked in: [2.614449] CPU: 0Not tainted (3.8.4-01382-g1f449cd-dirty #4) [2.620973] PC is at _set_gpio_debounce+0x60/0x104 [2.626025] LR is at clk_enable+0x30/0x3c [2.630249] pc : [c02e2850]lr : [c0449ad8]psr: 6193 [2.630249] sp : cf053df8 ip : 0001 fp : cf19e000 [2.642308] r10: cdc56800 r9 : cf19e010 r8 : cf0b8410 [2.647802] r7 : 0002 r6 : 0004 r5 : 00a0 r4 : cf0b8410 [2.654668] r3 : fa1ac150 r2 : fa1ac000 r1 : r0 : [2.661540] Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel [2.669324] Control: 10c5387d Table: 80004019 DAC: 0017 [2.675372] Process swapper/0 (pid: 1, stack limit = 0xcf052240) [2.681688] Stack: (0xcf053df8 to 0xcf054000) [2.686279] 3de0: cf0b846c 2113 [2.694892] 3e00: 1388 c02e2924 0002 cf0b848c 2113 1388 c02e0258 [2.703508] 3e20: cdc57ce8 cdca2784 c00028d8 cdc56800 c040ba10 cdc57c50 c08374e0 [2.712115] 3e40: 0001 0028 cdca2784 cdca2740 cdc57c00 cdc56800 c040bc58 [2.720727] 3e60: cf1a0bd0 cf19e010 c08374e0 c0d96ffc c08374e0 cf19e010 c08374e0 [2.729341] 3e80: c076c7b0 c07421c4 c0331c90 c0331c78 c033092c cf19e010 c08374e0 [2.737957] 3ea0: cf19e044 c0330bd8 cf19e010 c08374e0 c0330c84 [2.746573] 3ec0: c08374e0 c0330bf0 c032f2f8 cf0222a8 cf198a10 c08374e0 c08265c8 [2.755185] 3ee0: cdbca7c0 c033015c c067d1e0 c08374e0 c08374e0 c0844600 cf052000 [2.763793] 3f00: c03311b8 c0776fb0 c0844600 cf052000 [2.772393] 3f20: c07421c4 c0008818 0001dd4e 0007 c076c7b0 07753841 [2.780998] 3f40: 9a64d806 9a64d806 6113 c0776fb0 0007 c0776f90 [2.789603] 3f60: c0844600 00af c0793ee8 c07421c4 c07428f8 0007 0007 [2.798217] 3f80: c07421c4 c0513f0c [2.806827] 3fa0: c0513f14 c0013490 [2.815447] 3fc0: [2.824058] 3fe0: 0013 eebff7f9 3a5f1b7e [2.832668] [c02e2850] (_set_gpio_debounce+0x60/0x104) from [c02e2924] (gpio_debounce+0x30/0x44) [2.842272] [c02e2924] (gpio_debounce+0x30/0x44) from [c02e0258] (gpio_set_debounce+0xc4/0xdc) [2.851714] [c02e0258] (gpio_set_debounce+0xc4/0xdc) from [c040ba10] (gpio_keys_setup_key+0x190/0x268) [2.861871] [c040ba10] (gpio_keys_setup_key+0x190/0x268) from [c040bc58] (gpio_keys_probe+0x170/0x274) [2.872046] [c040bc58] (gpio_keys_probe+0x170/0x274) from [c0331c90] (platform_drv_probe+0x18/0x1c) [2.881940] [c0331c90] (platform_drv_probe+0x18/0x1c) from [c033092c] (really_probe+0x60/0x1f4) [2.891453] [c033092c] (really_probe+0x60/0x1f4) from [c0330bd8] (driver_probe_device+0x30/0x48) [2.901064] [c0330bd8] (driver_probe_device+0x30/0x48) from [c0330c84] (__driver_attach+0x94/0x98) [2.910858] [c0330c84] (__driver_attach+0x94/0x98) from [c032f2f8] (bus_for_each_dev+0x64/0x88) [2.920380] [c032f2f8] (bus_for_each_dev+0x64/0x88) from [c033015c] (bus_add_driver+0xa0/0x240) [2.929900] [c033015c] (bus_add_driver+0xa0/0x240) from [c03311b8] (driver_register+0x78/0x144) [2.939434] [c03311b8] (driver_register+0x78/0x144) from [c0008818] (do_one_initcall+0x118/0x180) [2.949160] [c0008818] (do_one_initcall+0x118/0x180) from [c07428f8] (kernel_init_freeable+0xfc/0x1cc) [2.959343] [c07428f8] (kernel_init_freeable+0xfc/0x1cc) from [c0513f14] (kernel_init+0x8/0xe4) [2.968867] [c0513f14] (kernel_init+0x8/0xe4) from [c0013490] (ret_from_fork+0x14/0x24) [2.977663] Code: e5943108 e5942008 e1d331be e0823003 (e5932000) [2.984092] ---[ end trace d1c5f252789a330b ]--- [2.989241] Kernel panic - not syncing: Attempted to kill init! exitcode=0x000b [2.989241] Signed-off-by: Vaibhav Hiremath hvaib...@ti.com Cc: Tony
Re: [PATCH 01/10] ARM: OMAP3/4: cpuidle: fix sparse and checkpatch warnings
On 12/9/2012 6:53 AM, Paul Walmsley wrote: Fix the following sparse warnings in the OMAP3/4 CPUIdle code: arch/arm/mach-omap2/cpuidle34xx.c:272:1: warning: symbol 'omap3_idle_dev' was not declared. Should it be static? arch/arm/mach-omap2/cpuidle34xx.c:274:23: warning: symbol 'omap3_idle_driver' was not declared. Should it be static? arch/arm/mach-omap2/cpuidle44xx.c:164:1: warning: symbol 'omap4_idle_dev' was not declared. Should it be static? arch/arm/mach-omap2/cpuidle44xx.c:166:23: warning: symbol 'omap4_idle_driver' was not declared. Should it be static? Also fix the following checkpatch warnings: WARNING: please, no space before tabs #44: FILE: arch/arm/mach-omap2/cpuidle34xx.c:105: +^I.name = ^Iomap3_idle,$ WARNING: please, no space before tabs #45: FILE: arch/arm/mach-omap2/cpuidle34xx.c:106: +^I.owner = ^ITHIS_MODULE,$ ERROR: code indent should use tabs where possible #211: FILE: arch/arm/mach-omap2/cpuidle44xx.c:74: +/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */$ Paul, I am using your paul-linux-pwrdm_post_fpwrst_devel_a_3.9 branch, where all the patches which you have posted are present (I believe so) and I am getting following sparse warning - CHECK arch/arm/mach-omap2/powerdomain.c arch/arm/mach-omap2/powerdomain.c:811:2: warning: context imbalance in 'pwrdm_lock': unexpected unlock arch/arm/mach-omap2/powerdomain.c:811:2:default context: wanted 1, got 0 include/linux/spinlock.h:340:2: warning: context problem in 'pwrdm_unlock': '_raw_spin_unlock_irqrestore' expected different context include/linux/spinlock.h:340:2:context 'lock': wanted = 1, got 0 arch/arm/mach-omap2/powerdomain.c:1130:14: warning: context problem in 'pwrdm_state_switch': 'pwrdm_unlock' expected different context arch/arm/mach-omap2/powerdomain.c:1130:14:default context: wanted = 1, got 0 arch/arm/mach-omap2/powerdomain.c:1295:14: warning: context problem in 'pwrdm_set_next_fpwrst': 'pwrdm_unlock' expected different context arch/arm/mach-omap2/powerdomain.c:1295:14:default context: wanted = 1, got 0 arch/arm/mach-omap2/powerdomain.c:1317:14: warning: context problem in 'pwrdm_read_next_fpwrst': 'pwrdm_unlock' expected different context arch/arm/mach-omap2/powerdomain.c:1317:14:default context: wanted = 1, got 0 arch/arm/mach-omap2/powerdomain.c:1382:14: warning: context problem in 'pwrdm_set_fpwrst': 'pwrdm_unlock' expected different context arch/arm/mach-omap2/powerdomain.c:1382:14:default context: wanted = 1, got 0 arch/arm/mach-omap2/powerdomain.c:1407:14: warning: context problem in 'pwrdm_read_fpwrst': 'pwrdm_unlock' expected different context arch/arm/mach-omap2/powerdomain.c:1407:14:default context: wanted = 1, got 0 arch/arm/mach-omap2/powerdomain.c:1432:14: warning: context problem in 'pwrdm_read_prev_fpwrst': 'pwrdm_unlock' expected different context arch/arm/mach-omap2/powerdomain.c:1432:14:default context: wanted = 1, got 0 arch/arm/mach-omap2/powerdomain.c:1505:14: warning: context problem in 'pwrdm_dbg_show_counter': 'pwrdm_unlock' expected different context arch/arm/mach-omap2/powerdomain.c:1505:14:default context: wanted = 1, got 0 arch/arm/mach-omap2/powerdomain.c:1542:14: warning: context problem in 'pwrdm_dbg_show_timer': 'pwrdm_unlock' expected different context arch/arm/mach-omap2/powerdomain.c:1542:14:default context: wanted = 1, got 0 CC arch/arm/mach-omap2/powerdomain.o On the other hand, I have boot tested it on BeagleBone platform. Thanks, Vaibhav -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 05/10] ARM: OMAP2+: PM/powerdomain: move omap_set_pwrdm_state() to powerdomain code
Minor comment below,
On 12/9/2012 6:53 AM, Paul Walmsley wrote:
Move omap_set_pwrdm_state() from the PM code to the powerdomain code,
and refactor it to split it up into several functions. A subsequent patch
will rename it to conform with the existing powerdomain function names.
Signed-off-by: Paul Walmsley p...@pwsan.com
Cc: Jean Pihet jean.pi...@newoldbits.com
Cc: Kevin Hilman khil...@deeprootsystems.com
---
arch/arm/mach-omap2/pm.c | 61
arch/arm/mach-omap2/pm.h |1
arch/arm/mach-omap2/powerdomain.c | 112
+++--
arch/arm/mach-omap2/powerdomain.h |3 +
4 files changed, 85 insertions(+), 92 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index cc8ed0f..2e2a897 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -76,10 +76,6 @@ static void __init omap2_init_processor_devices(void)
}
}
-/* Types of sleep_switch used in omap_set_pwrdm_state */
-#define FORCEWAKEUP_SWITCH 0
-#define LOWPOWERSTATE_SWITCH 1
-
int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
{
if ((clkdm-flags CLKDM_CAN_ENABLE_AUTO)
@@ -92,63 +88,6 @@ int __init omap_pm_clkdms_setup(struct clockdomain *clkdm,
void *unused)
}
/*
- * This sets pwrdm state (other than mpu core. Currently only ON
- * RET are supported.
- */
-int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 pwrst)
-{
- u8 curr_pwrst, next_pwrst;
- int sleep_switch = -1, ret = 0, hwsup = 0;
-
- if (!pwrdm || IS_ERR(pwrdm))
You can use IS_ERR_OR_NULL here.
Thanks,
Vaibhav
- return -EINVAL;
-
- while (!(pwrdm-pwrsts (1 pwrst))) {
- if (pwrst == PWRDM_POWER_OFF)
- return ret;
- pwrst--;
- }
-
- next_pwrst = pwrdm_read_next_pwrst(pwrdm);
- if (next_pwrst == pwrst)
- return ret;
-
- curr_pwrst = pwrdm_read_pwrst(pwrdm);
- if (curr_pwrst PWRDM_POWER_ON) {
- if ((curr_pwrst pwrst)
- (pwrdm-flags PWRDM_HAS_LOWPOWERSTATECHANGE)) {
- sleep_switch = LOWPOWERSTATE_SWITCH;
- } else {
- hwsup = clkdm_in_hwsup(pwrdm-pwrdm_clkdms[0]);
- clkdm_wakeup(pwrdm-pwrdm_clkdms[0]);
- sleep_switch = FORCEWAKEUP_SWITCH;
- }
- }
-
- ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
- if (ret)
- pr_err(%s: unable to set power state of powerdomain: %s\n,
-__func__, pwrdm-name);
-
- switch (sleep_switch) {
- case FORCEWAKEUP_SWITCH:
- if (hwsup)
- clkdm_allow_idle(pwrdm-pwrdm_clkdms[0]);
- else
- clkdm_sleep(pwrdm-pwrdm_clkdms[0]);
- break;
- case LOWPOWERSTATE_SWITCH:
- pwrdm_set_lowpwrstchange(pwrdm);
- pwrdm_state_switch(pwrdm);
- break;
- }
-
- return ret;
-}
-
-
-
-/*
* This API is to be called during init to set the various voltage
* domains to the voltage as per the opp table. Typically we boot up
* at the nominal voltage. So this function finds out the rate of
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 686137d..707e9cb 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -33,7 +33,6 @@ static inline int omap4_idle_init(void)
extern void *omap3_secure_ram_storage;
extern void omap3_pm_off_mode_enable(int);
extern void omap_sram_idle(void);
-extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
extern int (*omap_pm_suspend)(void);
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 97b3881..05f00660 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -921,35 +921,6 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm)
return (pwrdm pwrdm-flags PWRDM_HAS_HDWR_SAR) ? 1 : 0;
}
-/**
- * pwrdm_set_lowpwrstchange - Request a low power state change
- * @pwrdm: struct powerdomain *
- *
- * Allows a powerdomain to transtion to a lower power sleep state
- * from an existing sleep state without waking up the powerdomain.
- * Returns -EINVAL if the powerdomain pointer is null or if the
- * powerdomain does not support LOWPOWERSTATECHANGE, or returns 0
- * upon success.
- */
-int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
-{
- int ret = -EINVAL;
-
- if (!pwrdm)
- return -EINVAL;
-
- if (!(pwrdm-flags PWRDM_HAS_LOWPOWERSTATECHANGE))
- return -EINVAL;
-
- pr_debug(powerdomain: %s: setting LOWPOWERSTATECHANGE bit\n,
- pwrdm-name);
-
- if (arch_pwrdm
Re: [PATCH 02/12] ARM: OMAP2+: PM: introduce power domains functional states
On 12/9/2012 11:23 PM, Paul Walmsley wrote:
From: Jean Pihet jean.pi...@newoldbits.com
Introduce the functional states for power domains, which include
the power states and the logic states.
This patch provides the API functions to set and read the power
domains functional state and internal functions to convert between
the functional (i.e. logical) and the internal (or registers) values.
In the new API only the functions pwrdm_set_next_fpwrst() and
pwrdm_set_fpwrst() shall be used to change a power domain target
state, along with the associated PWRDM_FUNC_* macros as the state
parameters.
Note about the power domains allowed states:
Power domains have varied capabilities, as defined by the value of
the pwrsts and pwrsts_logic_ret fields of the powerdomain struct.
When reading or setting a low power state such as OFF/RET, a specific
requested state may not be supported on the given power domain.
In the states conversion functions a power or logic state is first
looked for in the lower power states in order to maximize the power
savings, then if not found in the higher power states. An iteration
function is used, as suggested by Rajendra Nayak rna...@ti.com
This function is temporary and will be removed later in the series.
This functionality brings consistency in the functional power states
core code and acts as a guard against hardware implementations
discrepancies, e.g. some power domains only support the RET logic
state although reading the logic state registers (previous, current
and next) always returns OFF. The DSS power domain on OMAP3 is an
example.
Signed-off-by: Jean Pihet j-pi...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Nishanth Menon n...@ti.com
[p...@pwsan.com: add offset for functional powerstates so it's not
possible to confuse them with the old API; use one fn to convert func
pwrsts to low-level hardware bits; skip hardware reads when hardware
logic retst and logic pwrst bits are missing; fix kerneldoc and
commit message; remove unnecessary PWRDM_LOGIC_MEM_PWRST_* macros;
combine spinlock patch into this patch; expand the number of operations
which take the spinlock]
Signed-off-by: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/powerdomain.c | 525
+
arch/arm/mach-omap2/powerdomain.h | 33 ++
2 files changed, 553 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 94b89a25..18f33de 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -1,7 +1,7 @@
/*
* OMAP powerdomain control
*
- * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008, 2011-2012 Texas Instruments, Inc.
* Copyright (C) 2007-2011 Nokia Corporation
*
* Written by Paul Walmsley
@@ -44,12 +44,19 @@ enum {
PWRDM_STATE_PREV,
};
-
/* pwrdm_list contains all registered struct powerdomains */
static LIST_HEAD(pwrdm_list);
static struct pwrdm_ops *arch_pwrdm;
+/*
+ * _fpwrst_names: human-readable functional powerstate names - should match
+ *the enum pwrdm_func_state order and names
+ */
+static const char * const _fpwrst_names[] = {
+ OFF, OSWR, CSWR, INACTIVE, ON
+};
+
/* Private functions */
static struct powerdomain *_pwrdm_lookup(const char *name)
@@ -145,7 +152,6 @@ static void _update_logic_membank_counters(struct
powerdomain *pwrdm)
static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
{
-
int prev, next, state, trace_state = 0;
if (pwrdm == NULL)
@@ -259,6 +265,309 @@ static bool _pwrdm_logic_retst_can_change(struct
powerdomain *pwrdm)
return _pwrdm_logic_retst_is_controllable(pwrdm);
}
+/**
+ * _match_pwrst: determine the closest supported power state
+ * @pwrsts: list of allowed states, defined as a bitmask
+ * @pwrst: initial state to be used as a starting point
+ * @min: minimum (i.e. lowest consumption) allowed state
+ * @max: maximum (i.e. highest consumption) allowed state
+ *
+ * Search down then up for a valid state from a list of allowed
+ * states. Used by states conversion functions (_pwrdm_fpwrst_to_*)
+ * to look for allowed power and logic states for a powerdomain.
+ * Returns the matching allowed state. XXX Deprecated. The software
+ * should not try to program unsupported powerstates.
+ */
+static int _match_pwrst(u32 pwrsts, int pwrst, int min, int max)
+{
+ int found = 1, new_pwrst = pwrst;
+
+ /*
+ * If the power domain does not allow any state programmation
+ * return the max state which is always allowed
+ */
+ if (!pwrsts)
+ return max;
+
+ /*
+ * Search lower: if the requested state is not supported
+ * try the lower states, stopping at the minimum allowed
+ * state
+ */
+ while (!(pwrsts (1
Re: [PATCH 09/10] ARM: OMAP2+: clockdomain: convert existing atomic usecounts into spinlock-protected shorts/ints
On 12/9/2012 6:53 AM, Paul Walmsley wrote:
The atomic usecounts seem to be confusing, and are no longer needed
since the operations that they are attached to really should take
place under lock. Replace the atomic counters with simple integers,
protected by the enclosing powerdomain spinlock.
Signed-off-by: Paul Walmsley p...@pwsan.com
Cc: Kevin Hilman khil...@deeprootsystems.com
---
arch/arm/mach-omap2/clockdomain.c | 88
+++-
arch/arm/mach-omap2/clockdomain.h |6 +-
arch/arm/mach-omap2/cm3xxx.c |6 +-
arch/arm/mach-omap2/cminst44xx.c |2 -
arch/arm/mach-omap2/pm-debug.c |6 +-
arch/arm/mach-omap2/pm.c |3 +
arch/arm/mach-omap2/prm2xxx_3xxx.c |3 +
7 files changed, 88 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-omap2/clockdomain.c
b/arch/arm/mach-omap2/clockdomain.c
index 9d5b69f..ed8ac2f 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -210,7 +210,8 @@ static int _clkdm_add_wkdep(struct clockdomain *clkdm1,
return ret;
}
- if (atomic_inc_return(cd-wkdep_usecount) == 1) {
+ cd-wkdep_usecount++;
+ if (cd-wkdep_usecount == 1) {
pr_debug(clockdomain: hardware will wake up %s when %s wakes
up\n,
clkdm1-name, clkdm2-name);
@@ -252,7 +253,8 @@ static int _clkdm_del_wkdep(struct clockdomain *clkdm1,
return ret;
}
- if (atomic_dec_return(cd-wkdep_usecount) == 0) {
+ cd-wkdep_usecount--;
+ if (cd-wkdep_usecount == 0) {
pr_debug(clockdomain: hardware will no longer wake up %s after
%s wakes up\n,
clkdm1-name, clkdm2-name);
@@ -296,7 +298,8 @@ static int _clkdm_add_sleepdep(struct clockdomain *clkdm1,
return ret;
}
- if (atomic_inc_return(cd-sleepdep_usecount) == 1) {
+ cd-sleepdep_usecount++;
+ if (cd-sleepdep_usecount == 1) {
pr_debug(clockdomain: will prevent %s from sleeping if %s is
active\n,
clkdm1-name, clkdm2-name);
@@ -340,7 +343,8 @@ static int _clkdm_del_sleepdep(struct clockdomain *clkdm1,
return ret;
}
- if (atomic_dec_return(cd-sleepdep_usecount) == 0) {
+ cd-sleepdep_usecount--;
+ if (cd-sleepdep_usecount == 0) {
pr_debug(clockdomain: will no longer prevent %s from sleeping
if %s is active\n,
clkdm1-name, clkdm2-name);
@@ -567,7 +571,21 @@ struct powerdomain *clkdm_get_pwrdm(struct clockdomain
*clkdm)
*/
int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
{
- return _clkdm_add_wkdep(clkdm1, clkdm2);
+ struct clkdm_dep *cd;
+ int ret;
+
+ if (!clkdm1 || !clkdm2)
+ return -EINVAL;
+
+ cd = _clkdm_deps_lookup(clkdm2, clkdm1-wkdep_srcs);
+ if (IS_ERR(cd))
+ return PTR_ERR(cd);
+
+ pwrdm_lock(cd-clkdm-pwrdm.ptr);
+ ret = _clkdm_add_wkdep(clkdm1, clkdm2);
+ pwrdm_unlock(cd-clkdm-pwrdm.ptr);
+
+ return ret;
}
/**
@@ -582,7 +600,21 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct
clockdomain *clkdm2)
*/
int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
{
- return _clkdm_del_wkdep(clkdm1, clkdm2);
+ struct clkdm_dep *cd;
+ int ret;
+
+ if (!clkdm1 || !clkdm2)
+ return -EINVAL;
+
+ cd = _clkdm_deps_lookup(clkdm2, clkdm1-wkdep_srcs);
+ if (IS_ERR(cd))
+ return PTR_ERR(cd);
+
+ pwrdm_lock(cd-clkdm-pwrdm.ptr);
+ ret = _clkdm_del_wkdep(clkdm1, clkdm2);
+ pwrdm_unlock(cd-clkdm-pwrdm.ptr);
+
+ return ret;
}
/**
@@ -620,7 +652,7 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct
clockdomain *clkdm2)
return ret;
}
- /* XXX It's faster to return the atomic wkdep_usecount */
+ /* XXX It's faster to return the wkdep_usecount */
return arch_clkdm-clkdm_read_wkdep(clkdm1, clkdm2);
}
@@ -659,7 +691,21 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
*/
int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain
*clkdm2)
{
- return _clkdm_add_sleepdep(clkdm1, clkdm2);
+ struct clkdm_dep *cd;
+ int ret;
+
+ if (!clkdm1 || !clkdm2)
+ return -EINVAL;
+
+ cd = _clkdm_deps_lookup(clkdm2, clkdm1-wkdep_srcs);
+ if (IS_ERR(cd))
+ return PTR_ERR(cd);
+
+ pwrdm_lock(cd-clkdm-pwrdm.ptr);
+ ret = _clkdm_add_sleepdep(clkdm1, clkdm2);
+ pwrdm_unlock(cd-clkdm-pwrdm.ptr);
+
+ return ret;
}
/**
@@ -676,7 +722,21 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1,
struct clockdomain *clkdm2)
*/
int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain
*clkdm2)
{
- return
Re: [PATCH 09/12] ARM: OMAP2+: powerdomain: skip register reads for powerdomains known to be on
On 12/10/2012 1:33 AM, Paul Walmsley wrote:
There's no need to determine the current power state for powerdomains
that must be on while the kernel is running. We mark these
powerdomains with a new flag, PWRDM_ACTIVE_WITH_KERNEL. Any
powerdomain marked with that flag is reported as being in the ON power
state while the kernel is running.
Signed-off-by: Paul Walmsley p...@pwsan.com
Cc: Benoît Cousson b-cous...@ti.com
---
arch/arm/mach-omap2/powerdomain.c |9 ++---
arch/arm/mach-omap2/powerdomain.h |4
arch/arm/mach-omap2/powerdomains2xxx_data.c |2 ++
arch/arm/mach-omap2/powerdomains33xx_data.c |3 ++-
arch/arm/mach-omap2/powerdomains3xxx_data.c |9 ++---
arch/arm/mach-omap2/powerdomains44xx_data.c |5 -
6 files changed, 24 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index f5e2727..a4bb0bb 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -462,7 +462,8 @@ static int _pwrdm_read_fpwrst(struct powerdomain *pwrdm)
int pwrst, logic_pwrst, ret;
u8 fpwrst;
- if (!_pwrdm_pwrst_can_change(pwrdm))
+ if (!_pwrdm_pwrst_can_change(pwrdm) ||
+ pwrdm-flags PWRDM_ACTIVE_WITH_KERNEL)
return PWRDM_FUNC_PWRST_ON;
pwrst = arch_pwrdm-pwrdm_read_pwrst(pwrdm);
@@ -1104,12 +1105,14 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm)
int pwrdm_state_switch_nolock(struct powerdomain *pwrdm)
{
- int ret;
+ int ret = 0;
if (!pwrdm || !arch_pwrdm)
return -EINVAL;
- ret = arch_pwrdm-pwrdm_wait_transition(pwrdm);
+ if (!(pwrdm-flags PWRDM_ACTIVE_WITH_KERNEL))
+ ret = arch_pwrdm-pwrdm_wait_transition(pwrdm);
+
if (!ret)
_pwrdm_state_switch(pwrdm);
diff --git a/arch/arm/mach-omap2/powerdomain.h
b/arch/arm/mach-omap2/powerdomain.h
index f4a189a..10941fd 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -78,10 +78,14 @@ enum pwrdm_func_state {
*
* PWRDM_HAS_LOWPOWERSTATECHANGE - can transition from a sleep state
* to a lower sleep state without waking up the powerdomain
+ *
+ * PWRDM_ACTIVE_WITH_KERNEL - this powerdomain's current power state is
+ * guaranteed to be ON whenever the kernel is running
*/
#define PWRDM_HAS_HDWR_SAR BIT(0)
#define PWRDM_HAS_MPU_QUIRK BIT(1)
#define PWRDM_HAS_LOWPOWERSTATECHANGEBIT(2)
+#define PWRDM_ACTIVE_WITH_KERNEL BIT(3)
/*
* Powerdomain internal flags (struct powerdomain._flags)
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c
b/arch/arm/mach-omap2/powerdomains2xxx_data.c
index 578eef8..112927f 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c
@@ -54,6 +54,7 @@ static struct powerdomain mpu_24xx_pwrdm = {
[0] = PWRSTS_ON,
},
.voltdm = { .name = core },
+ .flags= PWRDM_ACTIVE_WITH_KERNEL,
};
static struct powerdomain core_24xx_pwrdm = {
@@ -73,6 +74,7 @@ static struct powerdomain core_24xx_pwrdm = {
[2] = PWRSTS_OFF_RET_ON, /* MEM3ONSTATE */
},
.voltdm = { .name = core },
+ .flags= PWRDM_ACTIVE_WITH_KERNEL,
};
diff --git a/arch/arm/mach-omap2/powerdomains33xx_data.c
b/arch/arm/mach-omap2/powerdomains33xx_data.c
index 869adb8..acb148a 100644
--- a/arch/arm/mach-omap2/powerdomains33xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains33xx_data.c
@@ -123,7 +123,8 @@ static struct powerdomain mpu_33xx_pwrdm = {
.pwrstst_offs = AM33XX_PM_MPU_PWRSTST_OFFSET,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
- .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ .flags = (PWRDM_HAS_LOWPOWERSTATECHANGE |
+PWRDM_ACTIVE_WITH_KERNEL),
This needs to be applicable for wkup_pwrdm as well.
Thanks,
Vaibhav
.banks = 3,
.logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
.mem_on_mask= {
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c
b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index f0e14e9ef..ade93d3 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -58,7 +58,7 @@ static struct powerdomain mpu_3xxx_pwrdm = {
.prcm_offs= MPU_MOD,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
- .flags= PWRDM_HAS_MPU_QUIRK,
+ .flags= (PWRDM_HAS_MPU_QUIRK | PWRDM_ACTIVE_WITH_KERNEL),
.banks= 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET,
@@ -74,7 +74,7 @@ static struct powerdomain
Re: [PATCH] da8xx: Allow use by am33xx based devices
On 12/6/2012 1:38 PM, Manjunathappa, Prakash wrote: Hi Tomi, On Wed, Oct 31, 2012 at 10:52:59, Manjunathappa, Prakash wrote: Hi, On Wed, Oct 31, 2012 at 21:26:08, Pantelis Antoniou wrote: This driver can be used for AM33xx devices, like the popular beaglebone. Signed-off-by: Pantelis Antoniou pa...@antoniou-consulting.com --- drivers/video/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 9791d10..e7868d8 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -2202,7 +2202,7 @@ config FB_SH7760 config FB_DA8XX tristate DA8xx/OMAP-L1xx Framebuffer support - depends on FB ARCH_DAVINCI_DA8XX + depends on FB (ARCH_DAVINCI_DA8XX || SOC_AM33XX) Agreed this is present on da8xx and am33xx, but moving forward for supporting DT, we should be avoiding these dependencies. So instead change this to remove machine dependencies. I could be wrong here, having dependency on platform seems to be right. Otherwise may lead to build errors for other platforms. No, it should not result in to build error unless driver uses some platform specific api's. Thanks, Vaibhav Please ignore my comments and accept this patch. Thanks, Prakash ___ Davinci-linux-open-source mailing list davinci-linux-open-sou...@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/1] ARM: OMAP: fix build error in arch/arm/mach-omap2/timer.c
On 11/27/2012 10:22 PM, Jon Hunter wrote: On 11/27/2012 04:24 AM, Mugunthan V N wrote: CC arch/arm/mach-omap2/timer.o arch/arm/mach-omap2/timer.c: In function 'omap_get_timer_dt': arch/arm/mach-omap2/timer.c:195:3: error: implicit declaration of function 'prom_add_property' make[1]: *** [arch/arm/mach-omap2/timer.o] Error 1 make: *** [arch/arm/mach-omap2] Error 2 Thanks for sending. You may wish to mentioned that this is seen on today's linux-next (I am seeing the same problem). fix for build break as the functions prom_*_property is renamed to of_*_property by the below patch commit 79d1c712958f94372482ad74578b00f44e744c12 Author: Nathan Fontenot nf...@linux.vnet.ibm.com Date: Tue Oct 2 16:58:46 2012 + powerpc+of: Rename the drivers/of prom_* functions to of_* Rename the prom_*_property routines of the generic OF code to of_*_property. This brings them in line with the naming used by the rest of the OF code. Signed-off-by: Mugunthan V N mugunthan...@ti.com --- arch/arm/mach-omap2/timer.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 099e406..5fd5e23 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -192,7 +192,7 @@ static struct device_node * __init omap_get_timer_dt(struct of_device_id *match, continue; } -prom_add_property(np, device_disabled); +of_add_property(np, device_disabled); return np; } I tested this on the AM335x device and it is working fine. So ... Acked-by: Jon Hunter jon-hun...@ti.com Tested-by: Jon Hunter jon-hun...@ti.com This patch still not made its way to linux-next, so still build is broken for all OMAP platforms. Thanks, Vaibhav Cheers Jon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RESEND v5 0/4] OMAP GPMC DT bindings
On 11/29/2012 8:53 PM, Daniel Mack wrote: On 29.11.2012 16:08, Philip, Avinash wrote: On Thu, Nov 29, 2012 at 17:28:04, Daniel Mack wrote: Hi Avinash, On 29.11.2012 06:24, Philip, Avinash wrote: On Wed, Nov 28, 2012 at 22:28:55, Daniel Mack wrote: [Resending +devicetree-discuss, +Rob, +Grant] This is a series of patches to support GPMC peripherals on OMAP boards. Depends on Linus' master + omap-next (branch omap-for-v3.8/cleanup-headers-gpmc) Can you resend this series on top of linux_next? The only branch these patches depend on is the omap-for-v3.8/cleanup-headers-gpmc branch from omap_next. Are you actually seeing any merge conflicts with my series? If so, which branch are you referring to exactly? Some of the missing items I seen 1. Of_node not populated in omap_nand_platform_data structure. Hmm - gpmc_probe_nand_child() from 4/4 adds gpmc_nand_data-of_node = child; Do I miss anything? I didn't found definition for of_node member in omap_nand_platform_data structure. This also might be missing in liniux-next? Ah, right. I got that entry from your patch (mtd: nand: omap2: Support for hardware BCH error correction). But you're right, it should be part of my series. Will add that when resending, but note that your ELM series will then cause a (trivial) merge conflict. 2. Remove platform device creation from hwmod as GPMC DT is populating. Currently GPMC device creaing from DT HWMOD. This is already addressed in cd00b0530 (ARM: OMAP2+: gpmc: Fix kernel BUG for DT boot mode) by Vaibhav Hiremath, which I got via Afzal's USB branch: Purpose of VH's patch was to get beagle bone booting, but Jon sent another patch that made beagle bone boot and it has reached mainline by v3.7-rc2, hence the patch you are referring to is currently not going upstream. Still to have GPMC DT work, we need that patch as other wise there would be two GPMC devices. In earlier versions of your series, you had a similar patch, it is required, can you please add it to your series as otherwise with your series GPMC DT won't work. Ok, fine. Will do. Feel free to take that patch forward, merge into your series. Thanks, Vaibhav Daniel -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] ARM: AM335x: Fix warning in timer.c
On 11/28/2012 7:45 AM, Jon Hunter wrote:
When compiling the kernel with configuration options ...
# CONFIG_ARCH_OMAP2 is not set
# CONFIG_ARCH_OMAP3 is not set
# CONFIG_ARCH_OMAP4 is not set
# CONFIG_SOC_OMAP5 is not set
CONFIG_SOC_AM33XX=y
... the following build warning is seen.
CC arch/arm/mach-omap2/timer.o
arch/arm/mach-omap2/timer.c:395:19: warning:
‘omap2_sync32k_clocksource_init’
defined but not used [-Wunused-function]
This issue was introduced by commit 6f80b3b (ARM: OMAP2+: timer: remove
CONFIG_OMAP_32K_TIMER) where the omap2_sync32k_clocksource_init() is no
longer referenced by the timer initialisation function for the AM335x
device as it has no 32k-sync timer.
Fix this by only including the omap2_sync32k_clocksource_init() function
if either OMAP2, OMAP3, OMAP4 or OMAP5 devices are enabled.
Cc: Igor Grinberg grinb...@compulab.co.il
Signed-off-by: Jon Hunter jon-hun...@ti.com
---
arch/arm/mach-omap2/timer.c |3 +++
1 file changed, 3 insertions(+)
Jon,
I applied all these patches and it fixes build warning and also I have
tested it on Bone platform without any issues.
I also ran parse on this and saw further warning,
CHECK arch/arm/mach-omap2/timer.c
arch/arm/mach-omap2/timer.c:193:13: warning: symbol 'omap_dmtimer_init'
was not declared. Should it be static?
arch/arm/mach-omap2/timer.c:213:12: warning: symbol
'omap_dm_timer_get_errata' was not declared. Should it be static?
Below patch fixes that too, feel free to merge it into your's
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 085c7e7..1d1cfec 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -190,7 +190,7 @@ static struct device_node * __init
omap_get_timer_dt(struct of_device_id *match,
* kernel registering these devices remove them dynamically from the device
* tree on boot.
*/
-void __init omap_dmtimer_init(void)
+static void __init omap_dmtimer_init(void)
{
struct device_node *np;
@@ -210,7 +210,7 @@ void __init omap_dmtimer_init(void)
*
* Get the timer errata flags that are specific to the OMAP device
being used.
*/
-u32 __init omap_dm_timer_get_errata(void)
+static u32 __init omap_dm_timer_get_errata(void)
{
if (cpu_is_omap24xx())
return 0;
Thanks,
Vaibhav
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Re: AM335x: Beaglebone stops to boot with current git kernel
On 11/22/2012 1:30 AM, Igor Mazanov wrote:
On Wed, Nov 21, 2012 at 9:38 PM, Tony Lindgren t...@atomide.com wrote:
* Jean Pihet jean.pi...@newoldbits.com [121114 08:43]:
On Wed, Nov 14, 2012 at 4:28 PM, Igor Mazanov i.maza...@gmail.com wrote:
Beaglebone boot process is broken with the current git kernel. I use
omap2plus_defconfig for tests.
It looks like the boot process stops due to the last changes in the AM33xx
clock sysbsystem. A following patch resolves this issue:
...
The patch should change the name of the hwmod entry as well, can you
fold this change in the current patch?
Any news on updating this?
The current kernel boots, but after a switching to CCF doesn't work
the debugss - it's just disabled in the current hwmod code. So, it
looks like we can't use JTAG to connect to the running kernel.
just resumed from vacation...
JTAG clock will get disabled because, CONFIG_OMAP_RESET_CLOCKS will
disable unused clocks, so as debugss clock.
There is another thread started by Joel on the similar issue,
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg80863.html
Something below should be done for debugss on AM33xx,
diff --git a/arch/arm/mach-omap2/clock33xx_data.c
b/arch/arm/mach-omap2/clock33xx_data.c
index 17e3de5..60e0b53 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -584,6 +584,9 @@ static struct clk debugss_ick = {
.clkdm_name = l3_aon_clkdm,
.parent = dpll_core_m4_ck,
.ops= clkops_omap2_dflt,
+#ifdef CONFIG_DEBUG_KERNEL
+ .flags = ENABLE_ON_INIT,
+#endif
.enable_reg = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
.enable_bit = AM33XX_MODULEMODE_SWCTRL,
.recalc = followparent_recalc,
Thanks,
Vaibhav
Regards,
Igor.
Regards,
Tony
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Re: [PATCH] AM33XX: Clock: Fix JTAG disconnect during kernel boot
On 11/19/2012 9:45 PM, Jon Hunter wrote:
On 11/16/2012 08:44 PM, Joel A Fernandes wrote:
Hi Jon,
On Fri, Nov 16, 2012 at 6:12 PM, Jon Hunter jon-hun...@ti.com wrote:
diff --git a/arch/arm/mach-omap2/clock33xx_data.c
b/arch/arm/mach-omap2/clock33xx_data.c
index b7b7995..d0b4313 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -585,6 +585,7 @@ static struct clk debugss_ick = {
.clkdm_name = l3_aon_clkdm,
.parent = dpll_core_m4_ck,
.ops= clkops_omap2_dflt,
+ .flags = ENABLE_ON_INIT,
.enable_reg = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
.enable_bit = AM33XX_MODULEMODE_SWCTRL,
.recalc = followparent_recalc,
Does this mean this clock will always be enabled, even when not using
JTAG? If so, is that what you want?
Yes, the clock will always be on, because some times we connect JTAG
on a running Linux system without powering it down. I can't comment
without doing measurements if keeping the clock on has significant
impact on power, but I see what you mean. Definitely low power is a
parameter and folks who want lowest possible power might need to turn
off the clock and not have JTAG in production, but that depends on the
user's requirement. I personally don't care about power as much as I
care about not being able to JTAG, and I think there are other folks
who suffer from the same JTAG problem who wouldn't necessarily want
lowest power.
I can't say I am that familiar with the AM33xx architecture, but I know
that on OMAP this would keep on the debugss clock and power domain.
Do you need this change to connect JTAG after the kernel has booted or
just to maintain JTAG during kernel boot?
I am wondering if you should implement a new flag such as
DONT_DISABLE_ON_INIT so if the clock is on it is not disabled, but if
it is not enabled, you don't enabled it. Then that would be the best of
both worlds.
Joel,
The it should be handled is, on kernel_debug option we should keep it
enabled and default it should be disabled.
Something similar to,
diff --git a/arch/arm/mach-omap2/clock33xx_data.c
b/arch/arm/mach-omap2/clock33xx_data.c
index 17e3de5..60e0b53 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -584,6 +584,9 @@ static struct clk debugss_ick = {
.clkdm_name = l3_aon_clkdm,
.parent = dpll_core_m4_ck,
.ops= clkops_omap2_dflt,
+#ifdef CONFIG_DEBUG_KERNEL
+ .flags = ENABLE_ON_INIT,
+#endif
.enable_reg = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
.enable_bit = AM33XX_MODULEMODE_SWCTRL,
.recalc = followparent_recalc,
Can you please test above change??
Thanks,
Vaibhav
I was not sure if you are concerned about power at all. Or if having
that always enabled can inhibit low power states for suspend/idle etc.
Maybe, suspend/resume code can turn off clock on suspend and enable it
on resume.
Yes, but not ideal for a product assuming they are power sensitive.
Cheers
Jon
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Re: [PATCH v2 00/26] Move OMAP2+ over to common clk framework
On 11/8/2012 6:42 AM, Mike Turquette wrote: From: Mike Turquette mturque...@linaro.org Hi all, This series is based on top of Paul's PRM/CM clean-up work. It is a refresh of the patches Rajendra sent out a while back[1], with the addition of several fixes for PM regressions[2] across several platforms. I have tested on OMAP4430 Panda including PRCM diffing against pre-CCF patches (delta is zero) and also suspend/resume. I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming appears sane. However Panda-ES never comes back from suspend/resume. This problem exists on the PRM/CM branch I based on and was not introduced by this series. I am investigating that independently of this series. Anyone wanting to pull the work can find it at: git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8 [1] http://article.gmane.org/gmane.linux.ports.arm.omap/78771 [2] http://article.gmane.org/gmane.linux.ports.arm.omap/84015 Mike Turquette (3): ARM: OMAP4: clock: Convert to common clk ARM: OMAP2+: clock: remove unnecessary declarations ARM: OMAP2+: clock: Cleanup !CONFIG_COMMON_CLK parts Paul Walmsley (7): ARM: OMAP2xxx: clock: add APLL rate recalculation functions ARM: OMAP2+: clock: add OMAP CCF convenience macros to mach-omap2/clock.h ARM: AM33XX: clock: add clock data in common clock format ARM: OMAP44xx: clock: drop obsolete clock data ARM: OMAP3xxx: clk: drop obsolete clock data ARM: AM33xx: clock: drop obsolete clock data ARM: OMAP2xxx: clock: drop obsolete clock data Rajendra Nayak (15): ARM: OMAP: clock: Nuke plat/clock.c reuse struct clk as clk_hw_omap ARM: OMAP: hwmod: Fix up hwmod based clkdm accesses ARM: OMAP3: clock: Convert to common clk ARM: OMAP2: clock: Convert to common clk ARM: OMAP: clock: list all clk_hw_omap clks to enable/disable autoidle ARM: OMAP: clock: Define a function to enable clocks at init ARM: OMAP: clock: Get rid of some clkdm assocations within clks ARM: OMAP4: clock: Add 44xx data using common struct clk ARM: OMAP3: clock: Add 3xxx data using common struct clk ARM: omap2: clock: Add 24xx data using common struct clk ARM: OMAP: clock: Switch to COMMON clk ARM: OMAP: hwmod: Cleanup !CONFIG_COMMON_CLK parts ARM: OMAP4: clock: Cleanup !CONFIG_COMMON_CLK parts ARM: omap3: clock: Cleanup !CONFIG_COMMON_CLK parts ARM: omap2: clock: Cleanup !CONFIG_COMMON_CLK parts Vaibhav Hiremath (1): ARM: OMAP2+: hwmod: Invoke init_clkdm before other init functions arch/arm/mach-omap2/Kconfig |5 + arch/arm/mach-omap2/Makefile | 10 +- arch/arm/mach-omap2/cclock2420_data.c| 1959 ++ arch/arm/mach-omap2/cclock2430_data.c| 2073 +++ arch/arm/mach-omap2/cclock33xx_data.c| 961 +++ arch/arm/mach-omap2/cclock3xxx_data.c| 3595 + arch/arm/mach-omap2/cclock44xx_data.c| 1991 ++ arch/arm/mach-omap2/clkt2xxx_apll.c | 66 +- arch/arm/mach-omap2/clkt2xxx_dpll.c |8 +- arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 12 +- arch/arm/mach-omap2/clkt2xxx_osc.c | 13 +- arch/arm/mach-omap2/clkt2xxx_sys.c |7 +- arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 11 +- arch/arm/mach-omap2/clkt34xx_dpll3m2.c |8 +- arch/arm/mach-omap2/clkt_clksel.c| 194 +- arch/arm/mach-omap2/clkt_dpll.c | 28 +- arch/arm/mach-omap2/clkt_iclk.c | 31 +- arch/arm/mach-omap2/clock.c | 845 ++ arch/arm/mach-omap2/clock.h | 356 ++- arch/arm/mach-omap2/clock2420_data.c | 1986 -- arch/arm/mach-omap2/clock2430.c |8 +- arch/arm/mach-omap2/clock2430_data.c | 2085 --- arch/arm/mach-omap2/clock2xxx.c |1 + arch/arm/mach-omap2/clock2xxx.h | 47 +- arch/arm/mach-omap2/clock33xx_data.c | 1107 arch/arm/mach-omap2/clock34xx.c | 51 +- arch/arm/mach-omap2/clock3517.c | 24 +- arch/arm/mach-omap2/clock36xx.c | 22 +- arch/arm/mach-omap2/clock36xx.h |2 +- arch/arm/mach-omap2/clock3xxx.c |6 +- arch/arm/mach-omap2/clock3xxx.h |6 +- arch/arm/mach-omap2/clock3xxx_data.c | 3613 -- arch/arm/mach-omap2/clock44xx_data.c | 3398 arch/arm/mach-omap2/clock_common_data.c | 22 +- arch/arm/mach-omap2/cm-regbits-24xx.h|5 + arch/arm/mach-omap2/cm-regbits-34xx.h| 31 + arch/arm/mach-omap2/cm2xxx_3xxx.h|1 + arch/arm/mach-omap2/dpll3xxx.c | 226 +- arch/arm/mach-omap2/dpll44xx.c | 21 +- arch/arm/mach-omap2/io.c | 25 + arch/arm
Re: [PATCH 08/15] ARM: OMAP2+: hwmod: Fix the omap_hwmod_addr_space for CPGMAC0
On 11/5/2012 2:40 PM, Bedia, Vaibhav wrote: On Sun, Nov 04, 2012 at 20:54:17, Bedia, Vaibhav wrote: On Sat, Nov 03, 2012 at 21:48:48, Shilimkar, Santosh wrote: On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote: The first entry for CPGMAC0 should be ADDR_MAP_ON_INIT instead of ADDR_TYPE_RT to ensure the omap hwmod code maps the memory space at init and writes to the SYSCONFIG registers. Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com --- Sorry again similar question. Why CPGMAC0 should be mapped and sysconfig updated early ? Hmm I need to revisit this one. CPGMAC0 was not going to standby without this. Maybe something else is wrong in the hwmod data and needs fixing. Ok I checked this one. The change I made was indirectly fixing another issue with the AM33xx hwmod data. am33xx_cpgmac0_addr_space[] has two entries and the SYSC register is part of the second entry. The function _find_mpu_rt_addr_space in omap_hwmod.c looks for the first entry with the flag ADDR_TYPE_RT flag. The change I made indirectly made the second entry in am33xx_cpgmac0_addr_space[] become the first memory space with the ADDR_TYPE_RT flag. Due to this the hwmod code wrote to the correct SYSC address of CPGMAC0 and the IP went to standby during bootup. After changing the order of the entries in am33xx_cpgmac0_addr_space[] things work fine. Good catch. Just a side note on this, driver expects the addresses in this order only, first SS and then WR. Thanks, Vaibhav I'll make the changes in the next version. Regards, Vaibhav -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 04/15] ARM: OMAP2+: hwmod: Update the reset API for AM33XX
On 11/2/2012 6:02 PM, Vaibhav Bedia wrote:
WKUP-M3 has a reset status bit (RM_WKUP_STST.WKUP_M3_LRST)
Update the hardreset API to take care of the same to ensure
that the reset line properly deasserted.
Thanks for the patch, comments below -
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c |5 +
arch/arm/mach-omap2/prm33xx.c| 15 +++
arch/arm/mach-omap2/prm33xx.h|2 +-
3 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c
b/arch/arm/mach-omap2/omap_hwmod.c
index 37eeb45..a1d5835 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2944,11 +2944,8 @@ static int _am33xx_assert_hardreset(struct omap_hwmod
*oh,
static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
struct omap_hwmod_rst_info *ohri)
{
- if (ohri-st_shift)
- pr_err(omap_hwmod: %s: %s: hwmod data error: OMAP4 does not
support st_shift\n,
-oh-name, ohri-name);
-
return am33xx_prm_deassert_hardreset(ohri-rst_shift,
+ ohri-st_shift,
oh-clkdm-pwrdm.ptr-prcm_offs,
oh-prcm.omap4.rstctrl_offs,
oh-prcm.omap4.rstst_offs);
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 53ec9cb..0f29cb9 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -112,23 +112,22 @@ int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16
rstctrl_offs)
* -EINVAL upon an argument error, -EEXIST if the submodule was already out
* of reset, or -EBUSY if the submodule did not exit reset promptly.
*/
-int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
+int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
u16 rstctrl_offs, u16 rstst_offs)
{
int c;
- u32 mask = 1 shift;
-
- /* Check the current status to avoid de-asserting the line twice */
- if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0)
- return -EEXIST;
Any specific reason why you have removed this check?
Thanks,
Vaibhav
+ u32 mask = 1 st_shift;
/* Clear the reset status by writing 1 to the status bit */
am33xx_prm_rmw_reg_bits(0x, mask, inst, rstst_offs);
+
/* de-assert the reset control line */
+ mask = 1 shift;
+
am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
- /* wait the status to be set */
- omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst,
+ /* wait the status to be set */
+ omap_test_timeout(am33xx_prm_is_hardreset_asserted(st_shift, inst,
rstst_offs),
MAX_MODULE_HARDRESET_WAIT, c);
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
index 3f25c56..181fdab 100644
--- a/arch/arm/mach-omap2/prm33xx.h
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -124,6 +124,6 @@ extern void am33xx_prm_global_warm_sw_reset(void);
extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
u16 rstctrl_offs);
extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
-extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
+extern int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
u16 rstctrl_offs, u16 rstst_offs);
#endif
--
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Re: [PATCH 06/15] ARM: OMAP2+: hwmod: Enable OCMCRAM registration in AM33XX
On 11/2/2012 6:02 PM, Vaibhav Bedia wrote:
The hwmod data for OCMCRAM in AM33XX was commented out.
This data is needed by the power management code, hence
uncomment the same and register the OCP interface for it.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 11 ++-
1 files changed, 10 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 2e470ce..ec3fbb2 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -415,7 +415,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
*- cEFUSE (doesn't fall under any ocp_if)
*- clkdiv32k
*- debugss
- *- ocmc ram
*- ocp watch point
*- aes0
*- sha0
@@ -481,6 +480,7 @@ static struct omap_hwmod am33xx_debugss_hwmod = {
},
},
};
+#endif
/* ocmcram */
static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
@@ -501,6 +501,7 @@ static struct omap_hwmod am33xx_ocmcram_hwmod = {
},
};
+#if 0
Can you cut-n-paste the ocmcram hwmod entry outside of #if and resubmit
it again?
Thanks,
Vaibhav
/* ocpwp */
static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
.name = ocpwp,
@@ -3331,6 +3332,13 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
.flags = OCPIF_SWSUP_IDLE,
};
+/* l3 main - ocmc */
+static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
+ .master = am33xx_l3_main_hwmod,
+ .slave = am33xx_ocmcram_hwmod,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
am33xx_l4_fw__emif_fw,
am33xx_l3_main__emif,
@@ -3401,6 +3409,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[]
__initdata = {
am33xx_l3_main__tptc0,
am33xx_l3_main__tptc1,
am33xx_l3_main__tptc2,
+ am33xx_l3_main__ocmc,
am33xx_l3_s__usbss,
am33xx_l4_hs__cpgmac0,
am33xx_cpgmac0__mdio,
--
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Re: [PATCH 05/13] ARM: OMAP2+: PRCM: create SoC-specific chip restart functions
On 10/26/2012 4:51 AM, Paul Walmsley wrote:
Split omap_prcm_restart() from mach-omap2/prcm.c into SoC-specific
variants. These functions need to be able to save the reboot reason
into the scratchpad RAM. This implies a dependency on both the PRM
and SCM IP blocks, so they've been moved into their own file. This
will eventually call functions in the PRM and SCM drivers, once those
are created.
Signed-off-by: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/Makefile|5 +++
arch/arm/mach-omap2/common.h|4 ++
arch/arm/mach-omap2/omap2-restart.c | 65
+++
arch/arm/mach-omap2/omap3-restart.c | 36 +++
arch/arm/mach-omap2/omap4-common.c | 16 +
5 files changed, 126 insertions(+)
create mode 100644 arch/arm/mach-omap2/omap2-restart.c
create mode 100644 arch/arm/mach-omap2/omap3-restart.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 7a628e7..aa0f59c 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -49,6 +49,11 @@ AFLAGS_sram242x.o :=-Wa,-march=armv6
AFLAGS_sram243x.o:=-Wa,-march=armv6
AFLAGS_sram34xx.o:=-Wa,-march=armv7-a
+# Restart code (OMAP4/5 currently in omap4-common.c)
+obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o
+obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o
+obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o
+
# Pin multiplexing
obj-$(CONFIG_SOC_OMAP2420) += mux2420.o
obj-$(CONFIG_SOC_OMAP2430) += mux2430.o
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 320f0d7..06dff1a 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -115,6 +115,10 @@ void ti81xx_init_late(void);
void omap4430_init_late(void);
int omap2_common_pm_late_init(void);
void omap_prcm_restart(char, const char *);
+void omap2xxx_restart(char, const char *);
+void omap3xxx_restart(char, const char *);
+void omap44xx_restart(char, const char *);
+void omap5xxx_restart(char, const char *);
Paul,
omap5xxx_restart declaration needs to be removed from here.
There is no such function implemented in code.
Thanks,
Vaibhav
/* This gets called from mach-omap2/io.c, do not call this */
void __init omap2_set_globals_tap(u32 class, void __iomem *tap);
diff --git a/arch/arm/mach-omap2/omap2-restart.c
b/arch/arm/mach-omap2/omap2-restart.c
new file mode 100644
index 000..be6bc89
--- /dev/null
+++ b/arch/arm/mach-omap2/omap2-restart.c
@@ -0,0 +1,65 @@
+/*
+ * omap2-restart.c - code common to all OMAP2xxx machines.
+ *
+ * Copyright (C) 2012 Texas Instruments
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include linux/kernel.h
+#include linux/init.h
+#include linux/clk.h
+#include linux/io.h
+
+#include common.h
+#include prm2xxx.h
+
+/*
+ * reset_virt_prcm_set_ck, reset_sys_ck: pointers to the virt_prcm_set
+ * clock and the sys_ck. Used during the reset process
+ */
+static struct clk *reset_virt_prcm_set_ck, *reset_sys_ck;
+
+/* Reboot handling */
+
+/**
+ * omap2xxx_restart - Set DPLL to bypass mode for reboot to work
+ *
+ * Set the DPLL to bypass so that reboot completes successfully. No
+ * return value.
+ */
+void omap2xxx_restart(char mode, const char *cmd)
+{
+ u32 rate;
+
+ rate = clk_get_rate(reset_sys_ck);
+ clk_set_rate(reset_virt_prcm_set_ck, rate);
+
+ /* XXX Should save the cmd argument for use after the reboot */
+
+ omap2xxx_prm_dpll_reset(); /* never returns */
+ while (1);
+}
+
+/**
+ * omap2xxx_common_look_up_clks_for_reset - look up clocks needed for restart
+ *
+ * Some clocks need to be looked up in advance for the SoC restart
+ * operation to work - see omap2xxx_restart(). Returns -EINVAL upon
+ * error or 0 upon success.
+ */
+static int __init omap2xxx_common_look_up_clks_for_reset(void)
+{
+ reset_virt_prcm_set_ck = clk_get(NULL, virt_prcm_set);
+ if (IS_ERR(reset_virt_prcm_set_ck))
+ return -EINVAL;
+
+ reset_sys_ck = clk_get(NULL, sys_ck);
+ if (IS_ERR(reset_sys_ck))
+ return -EINVAL;
+
+ return 0;
+}
+core_initcall(omap2xxx_common_look_up_clks_for_reset);
diff --git a/arch/arm/mach-omap2/omap3-restart.c
b/arch/arm/mach-omap2/omap3-restart.c
new file mode 100644
index 000..923c582
--- /dev/null
+++ b/arch/arm/mach-omap2/omap3-restart.c
@@ -0,0 +1,36 @@
+/*
+ * omap3-restart.c - Code common to all OMAP3xxx machines.
+ *
+ * Copyright (C) 2009, 2012 Texas Instruments
+ * Copyright (C) 2010 Nokia Corporation
+ * Tony Lindgren t...@atomide.com
+ * Santosh Shilimkar santosh.shilim...@ti.com
+ *
+ * This program
Re: OMAP baseline test results for v3.7-rc3
On 10/30/2012 6:09 PM, Hiremath, Vaibhav wrote: On Tue, Oct 30, 2012 at 17:17:00, Paul Walmsley wrote: cc Vaibhav Hiremath On Tue, 30 Oct 2012, Mark Jackson wrote: At what point is booting from MMC on the BeagleBone going to start working ? I only ask, since, by default, a new BeagleBone is setup to boot from MMC, so anyone testing a new kernel will probably expect the same setup to work. BeagleBone boots initramfs from MMC now, which is what mine was shipped to do. Are you asking about rootfs on MMC? If so, Vaibhav would have a better sense of this than I. Mark, MMC is dependent on EDMA-DMA conversion patches from Matt, which he has already submitted to the list recently. So MMC support will come along with EDMA support. DMA-EDMA patches are targeted for v3.8, lets see how it goes. If you refer to the Matt's repo, you should get all the patches required to boot MMC support - https://github.com/ohporter/linux/tree/edma-dmaengine-am33xx-v3 I just tested this branch (+ one fix which Matt provided [1]) on BeagleBone, and MMC is working without any issues. I have tested with rootFS on MMC card. [1] - http://www.spinics.net/lists/linux-omap/msg79911.html Thanks, Vaibhav Thanks, Vaibhav ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH-V2 0/4] ARM: AM33XX: net: Add DT support to CPGMAC and MDIO driver
This patch-series adds support for, [1/4]: Typo mistake in CPSW driver while invoking runtime_pm api's [2/4]: Adds parent-child relation between CPSW MDIO module inside cpsw driver, as in case of AM33XX, the resources are shared and common register bit-field is provided to control module/clock enable/disable, makes it difficult to handle common resource. So the solution here is, to create parent-child relation between them. [3/4]: Add hwmod entry for MDIO module, required for MDIO driver. [4/4]: Add DT device nodes for both CPSW and MDIO modules in am33xx.dtsi, am335x-evm.dts and am335x-bone.dts file This patch series has been created on top of linux-omap/master and tested on both AM335x-EVM and BeagleBone platforms for NFS boot and basic ping test cases. All the patches are also available at, g...@github.com:hvaibhav/am335x-linux.git am335x-upstream-staging-cpsw Mugunthan V N (2): ARM: OMAP3+: hwmod: Add AM33XX HWMOD data for davinci_mdio module arm/dts: am33xx: Add CPSW and MDIO module nodes for AM33XX Vaibhav Hiremath (2): net: davinci_mdio: Fix typo mistake in calling runtime-pm api net: cpsw: Add parent-child relation support between cpsw and mdio arch/arm/boot/dts/am335x-bone.dts |8 arch/arm/boot/dts/am335x-evm.dts |8 arch/arm/boot/dts/am33xx.dtsi | 50 arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 32 ++ drivers/net/ethernet/ti/cpsw.c | 16 - drivers/net/ethernet/ti/davinci_mdio.c |2 +- 6 files changed, 113 insertions(+), 3 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/4] net: davinci_mdio: Fix typo mistake in calling runtime-pm api
By mistake (most likely a copy-paste), instead of pm_runtime_get_sync() api, driver is calling pm_runtime_put_sync() api in resume callback function. The bug was introduced by commit id (ae2c07aaf74: davinci_mdio: runtime PM support). Now, the reason why it didn't impact functionality is, the patch has been tested on AM335x-EVM and BeagleBone platform while submitting; and in case of AM335x the MDIO driver doesn't control the module enable/disable part, which is handled by CPSW driver. Signed-off-by: Vaibhav Hiremath hvaib...@ti.com Cc: Mugunthan V N mugunthan...@ti.com Cc: Richard Cochran richardcoch...@gmail.com --- drivers/net/ethernet/ti/davinci_mdio.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c index 51a96db..ae74280 100644 --- a/drivers/net/ethernet/ti/davinci_mdio.c +++ b/drivers/net/ethernet/ti/davinci_mdio.c @@ -465,7 +465,7 @@ static int davinci_mdio_resume(struct device *dev) u32 ctrl; spin_lock(data-lock); - pm_runtime_put_sync(data-dev); + pm_runtime_get_sync(data-dev); /* restart the scan state machine */ ctrl = __raw_readl(data-regs-control); -- 1.7.0.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/4] net: cpsw: Add parent-child relation support between cpsw and mdio
CPGMAC SubSystem consist of various sub-modules, like, mdio, cpdma,
cpsw, etc... These sub-modules are also used in some of Davinci family
of devices. Now based on requirement, use-case and available technology
nodes the integration of these sub-modules varies across devices.
So coming back to Linux net driver, currently separate and independent
platform devices drivers for CPSW and MDIO is implemented. In case of
Davinci they both has separate control, from resources perspective,
like clock.
In case of AM33XX, the resources are shared and only one register
bit-field is provided to control module/clock enable/disable, makes it
difficult to handle common resource.
So the solution here implemented in this patch is,
Create parent-child relationship between both the drivers, making
CPSW as a parent and MDIO as its child and enumerate all the child nodes
under CPSW module.
Both the drivers will function exactly the way it was operating before,
including runtime-pm functionality. No change is required in MDIO driver
(for that matter to any child driver).
As this is only supported during DT boot, the parent-child relationship
is created and populated in DT execution flow. The only required change
is inside DTS file, making MDIO as a child to CPSW node.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Mugunthan V N mugunthan...@ti.com
Cc: Richard Cochran richardcoch...@gmail.com
---
drivers/net/ethernet/ti/cpsw.c | 16 ++--
1 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index df55e24..fb1a692 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -827,7 +827,7 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data,
}
data-mac_control = prop;
- for_each_child_of_node(node, slave_node) {
+ for_each_node_by_name(slave_node, slave) {
struct cpsw_slave_data *slave_data = data-slave_data + i;
const char *phy_id = NULL;
const void *mac_addr = NULL;
@@ -862,6 +862,14 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data,
i++;
}
+ /*
+* Populate all the child nodes here...
+*/
+ ret = of_platform_populate(node, NULL, NULL, pdev-dev);
+ /* We do not want to force this, as in some cases may not have child */
+ if (ret)
+ pr_warn(Doesn't have any child node\n);
+
return 0;
error_ret:
@@ -895,6 +903,11 @@ static int __devinit cpsw_probe(struct platform_device
*pdev)
priv-msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
priv-rx_packet_max = max(rx_packet_max, 128);
+ /*
+* This may be required here for child devices.
+*/
+ pm_runtime_enable(pdev-dev);
+
if (cpsw_probe_dt(priv-data, pdev)) {
pr_err(cpsw: platform data missing\n);
ret = -ENODEV;
@@ -921,7 +934,6 @@ static int __devinit cpsw_probe(struct platform_device
*pdev)
for (i = 0; i data-slaves; i++)
priv-slaves[i].slave_num = i;
- pm_runtime_enable(pdev-dev);
priv-clk = clk_get(pdev-dev, fck);
if (IS_ERR(priv-clk)) {
dev_err(pdev-dev, fck is not found\n);
--
1.7.0.4
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[PATCH 3/4] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data for davinci_mdio module
From: Mugunthan V N mugunthan...@ti.com
This patch adds hwmod entry for davinci MDIO module,
creating parent-child relationship between CPSW and MDIO module.
This Parent-child relation is required in order to use common resources
like, clock, but still maintaining the logical separation between them.
CPGMAC SubSystem consist of various sub-modules, like, mdio, cpdma,
cpsw, etc... These sub-modules are also used in some of Davinci
family of devices, so separate and independent platform devices
drivers for CPSW and MDIO is implemented.
In case of AM33XX, the resources are shared and common register
bit-field is provided to control module/clock enable/disable,
makes it difficult to handle common resources from both drivers.
So the solution is, create parent-child relationship between
CPGMAC MDIO modules.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Richard Cochran richardcoch...@gmail.com
Cc: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 32
1 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index ad8d43b..3c235d8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -674,6 +674,7 @@ static struct omap_hwmod am33xx_cpgmac0_hwmod = {
.name = cpgmac0,
.class = am33xx_cpgmac0_hwmod_class,
.clkdm_name = cpsw_125mhz_clkdm,
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
.mpu_irqs = am33xx_cpgmac0_irqs,
.main_clk = cpsw_125mhz_gclk,
.prcm = {
@@ -685,6 +686,20 @@ static struct omap_hwmod am33xx_cpgmac0_hwmod = {
};
/*
+ * mdio class
+ */
+static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
+ .name = davinci_mdio,
+};
+
+static struct omap_hwmod am33xx_mdio_hwmod = {
+ .name = davinci_mdio,
+ .class = am33xx_mdio_hwmod_class,
+ .clkdm_name = cpsw_125mhz_clkdm,
+ .main_clk = cpsw_125mhz_gclk,
+};
+
+/*
* dcan class
*/
static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
@@ -2501,6 +2516,22 @@ static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
.user = OCP_USER_MPU,
};
+struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
+ {
+ .pa_start = 0x4A101000,
+ .pa_end = 0x4A101000 + SZ_256 - 1,
+ .flags = ADDR_MAP_ON_INIT,
+ },
+ { }
+};
+
+struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
+ .master = am33xx_cpgmac0_hwmod,
+ .slave = am33xx_mdio_hwmod,
+ .addr = am33xx_mdio_addr_space,
+ .user = OCP_USER_MPU,
+};
+
static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
{
.pa_start = 0x4808,
@@ -3371,6 +3402,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[]
__initdata = {
am33xx_l3_main__tptc2,
am33xx_l3_s__usbss,
am33xx_l4_hs__cpgmac0,
+ am33xx_cpgmac0__mdio,
NULL,
};
--
1.7.0.4
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[PATCH 4/4] arm/dts: am33xx: Add CPSW and MDIO module nodes for AM33XX
From: Mugunthan V N mugunthan...@ti.com
Add CPSW and MDIO related device tree data for AM33XX.
Also enable them into board/evm dts files by providing
respective phy-id.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Richard Cochran richardcoch...@gmail.com
Cc: Benoit Cousson b-cous...@ti.com
---
arch/arm/boot/dts/am335x-bone.dts |8 ++
arch/arm/boot/dts/am335x-evm.dts |8 ++
arch/arm/boot/dts/am33xx.dtsi | 50 +
3 files changed, 66 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index c634f87..e233cfa 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -78,3 +78,11 @@
};
};
};
+
+cpsw_emac0 {
+ phy_id = 4a101000.mdio:00;
+};
+
+cpsw_emac1 {
+ phy_id = 4a101000.mdio:01;
+};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 185d632..415c3b3 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -118,3 +118,11 @@
};
};
};
+
+cpsw_emac0 {
+ phy_id = 4a101000.mdio:00;
+};
+
+cpsw_emac1 {
+ phy_id = 4a101000.mdio:01;
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index bb31bff..f6bea04 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -210,5 +210,55 @@
interrupt-parent = intc;
interrupts = 91;
};
+
+ mac: ethernet@4A10 {
+ compatible = ti,cpsw;
+ ti,hwmods = cpgmac0;
+ cpdma_channels = 8;
+ host_port_no = 0;
+ cpdma_reg_ofs = 0x800;
+ cpdma_sram_ofs = 0xa00;
+ ale_reg_ofs = 0xd00;
+ ale_entries = 1024;
+ host_port_reg_ofs = 0x108;
+ hw_stats_reg_ofs = 0x900;
+ bd_ram_ofs = 0x2000;
+ bd_ram_size = 0x2000;
+ no_bd_ram = 0;
+ rx_descs = 64;
+ mac_control = 0x20;
+ slaves = 2;
+ reg = 0x4a10 0x800
+ 0x4a101200 0x100
+ 0x4a101000 0x100;
+ #address-cells = 1;
+ #size-cells = 1;
+ interrupt-parent = intc;
+ /* c0_rx_thresh_pend c0_rx_pend c0_tx_pend
c0_misc_pend*/
+ interrupts = 40 41 42 43;
+ ranges;
+ cpsw_emac0: slave@0 {
+ slave_reg_ofs = 0x208;
+ sliver_reg_ofs = 0xd80;
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+ cpsw_emac1: slave@1 {
+ slave_reg_ofs = 0x308;
+ sliver_reg_ofs = 0xdc0;
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ davinci_mdio: mdio@4a101000 {
+ compatible = ti,davinci_mdio;
+ #address-cells = 1;
+ #size-cells = 0;
+ ti,hwmods = davinci_mdio;
+ bus_freq = 100;
+ reg = 0x4a101000 0x100;
+ };
+
+ };
};
};
--
1.7.0.4
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Re: # (c) 2007, Joe Perches j...@perches.com
On 10/29/2012 1:51 PM, Vaibhav Hiremath wrote: Ignore this patch/mail, I screwed up with my command while sending patches. Sorry for noise. Thanks, Vaibhav -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: OMAP2+: am33xx: Add PRM warm reset/reboot support
This patch adds reboot capability to all AM33XX based boards/EVM's,
by asserting PRM warm reset bit on 'reboot' command.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Tested-by: Daniel Mack zon...@gmail.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Tony Lindgren t...@atomide.com
Cc: Afzal Mohammed af...@ti.com
---
Tested on AM335xEVM and BeagleBone platform.
arch/arm/mach-omap2/board-generic.c |1 +
arch/arm/mach-omap2/prcm.c |3 +++
arch/arm/mach-omap2/prm33xx.c | 15 +++
arch/arm/mach-omap2/prm33xx.h |1 +
4 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/board-generic.c
b/arch/arm/mach-omap2/board-generic.c
index 601ecdf..6a69ceb 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -114,6 +114,7 @@ DT_MACHINE_START(AM33XX_DT, Generic AM33XX (Flattened
Device Tree))
.init_machine = omap_generic_init,
.timer = omap3_am33xx_timer,
.dt_compat = am33xx_boards_compat,
+ .restart= omap_prcm_restart,
MACHINE_END
#endif
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index cff270a..07f163c 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -34,6 +34,7 @@
#include cm2xxx_3xxx.h
#include prm2xxx_3xxx.h
#include prm44xx.h
+#include prm33xx.h
#include prminst44xx.h
#include cminst44xx.h
#include prm-regbits-24xx.h
@@ -73,6 +74,8 @@ void omap_prcm_restart(char mode, const char *cmd)
omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
} else if (cpu_is_omap44xx()) {
omap4_prminst_global_warm_sw_reset(); /* never returns */
+ } else if (soc_is_am33xx()) {
+ am33xx_prm_global_warm_sw_reset(); /* never returns */
} else {
WARN_ON(1);
}
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 53ec9cb..657c3d0 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -135,6 +135,21 @@ int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
}
+void am33xx_prm_global_warm_sw_reset(void)
+{
+ u32 v;
+
+ v = am33xx_prm_read_reg(AM33XX_PRM_DEVICE_MOD,
+ AM33XX_PRM_RSTCTRL_OFFSET);
+ v |= AM33XX_GLOBAL_WARM_SW_RST_MASK;
+ am33xx_prm_write_reg(v, AM33XX_PRM_DEVICE_MOD,
+AM33XX_PRM_RSTCTRL_OFFSET);
+
+ /* OCP barrier */
+ v = am33xx_prm_read_reg(AM33XX_PRM_DEVICE_MOD,
+ AM33XX_PRM_RSTCTRL_OFFSET);
+}
+
static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
{
am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
index 3f25c56..cdfc694 100644
--- a/arch/arm/mach-omap2/prm33xx.h
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -126,4 +126,5 @@ extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16
inst,
extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
u16 rstctrl_offs, u16 rstst_offs);
+extern void am33xx_prm_global_warm_sw_reset(void);
#endif
--
1.7.0.4
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Re: [PATCH 00/13] ARM: OMAP: remove prcm.[ch]
On 10/26/2012 4:51 AM, Paul Walmsley wrote: Remove arch/arm/mach-omap2/prcm.c and arch/arm/plat-omap/include/plat/prcm.h. This is in preparation for moving the PRM/CM code to drivers/, although to be fair, these files should have been removed a long time ago. Intended for 3.8 cleanup. Applies on top of the existing PRM/CM split cleanup series, and the WDTIMER cleanup series. Paul, By any chance you have branch available with these patches, so that I can validate them here at my end? Thanks, Vaibhav - Paul --- omap2_prcm_cleanup_3.8 text data bss dec hex filename 7521423696876 5613996 13832295 d31067 vmlinux.omap2plus_defconfig.orig 7522239696612 5613996 13832847 d3128f vmlinux.omap2plus_defconfig Paul Walmsley (13): ARM: OMAP2+: common: remove mach-omap2/common.c and map_common_io code ARM: OMAP2/3: PRM: add SoC reset functions (using the CORE DPLL method) ARM: OMAP2xxx: clock: remove global 'dclk' variable ARM: OMAP2xxx: clock: move virt_prcm_set code into clkt2xxx_virt_prcm_set.c ARM: OMAP2+: PRCM: create SoC-specific chip restart functions ARM: OMAP2+: board files: use SoC-specific system restart functions ARM: OMAP2xxx: APLL/CM: convert to use omap2_cm_wait_module_ready() ARM: OMAP2+: CM/clock: convert _omap2_module_wait_ready() to use SoC-independent CM functions ARM: OMAP2+: PRCM: remove omap2_cm_wait_idlest() ARM: OMAP2+: PRCM: split and relocate the PRM/CM globals setup ARM: OMAP2+: PRCM: consolidate PRCM-related timeout macros ARM: OMAP2+: hwmod: call to _omap4_disable_module() should use the SoC-specific call ARM: OMAP2+: PRCM: remove obsolete prcm.[ch] arch/arm/mach-omap1/reset.c |2 arch/arm/mach-omap2/Makefile |9 + arch/arm/mach-omap2/am33xx.h |1 arch/arm/mach-omap2/board-2430sdp.c |2 arch/arm/mach-omap2/board-3430sdp.c |2 arch/arm/mach-omap2/board-3630sdp.c |2 arch/arm/mach-omap2/board-4430sdp.c |2 arch/arm/mach-omap2/board-am3517crane.c |2 arch/arm/mach-omap2/board-am3517evm.c|2 arch/arm/mach-omap2/board-apollon.c |2 arch/arm/mach-omap2/board-cm-t35.c | 18 +- arch/arm/mach-omap2/board-cm-t3517.c |2 arch/arm/mach-omap2/board-devkit8000.c |2 arch/arm/mach-omap2/board-generic.c | 10 + arch/arm/mach-omap2/board-h4.c |2 arch/arm/mach-omap2/board-igep0020.c |4 - arch/arm/mach-omap2/board-ldp.c |2 arch/arm/mach-omap2/board-n8x0.c |6 - arch/arm/mach-omap2/board-omap3beagle.c |2 arch/arm/mach-omap2/board-omap3evm.c |2 arch/arm/mach-omap2/board-omap3logic.c |4 - arch/arm/mach-omap2/board-omap3pandora.c |2 arch/arm/mach-omap2/board-omap3stalker.c |2 arch/arm/mach-omap2/board-omap3touchbook.c |2 arch/arm/mach-omap2/board-omap4panda.c |2 arch/arm/mach-omap2/board-overo.c|2 arch/arm/mach-omap2/board-rm680.c|4 - arch/arm/mach-omap2/board-rx51.c |2 arch/arm/mach-omap2/board-ti8168evm.c|4 - arch/arm/mach-omap2/board-zoom.c |4 - arch/arm/mach-omap2/clkt2xxx_apll.c | 57 ++- arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 36 - arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 70 - arch/arm/mach-omap2/clkt_iclk.c |1 arch/arm/mach-omap2/clock.c | 15 +- arch/arm/mach-omap2/clock.h | 28 arch/arm/mach-omap2/clock2420_data.c | 26 +-- arch/arm/mach-omap2/clock2430_data.c | 26 +-- arch/arm/mach-omap2/clock2xxx.c | 16 -- arch/arm/mach-omap2/clock2xxx.h |9 + arch/arm/mach-omap2/cm-regbits-24xx.h|2 arch/arm/mach-omap2/cm.h | 20 ++- arch/arm/mach-omap2/cm2xxx.c | 128 arch/arm/mach-omap2/cm2xxx.h |4 + arch/arm/mach-omap2/cm2xxx_3xxx.h|8 + arch/arm/mach-omap2/cm3xxx.c | 66 arch/arm/mach-omap2/cm3xxx.h |5 + arch/arm/mach-omap2/cm_common.c | 70 + arch/arm/mach-omap2/cminst44xx.h |2 arch/arm/mach-omap2/common.c | 202 -- arch/arm/mach-omap2/common.h | 111 ++ arch/arm/mach-omap2/control.c| 10 + arch/arm/mach-omap2/control.h|2 arch/arm/mach-omap2/cpuidle34xx.c|1 arch/arm/mach-omap2/display.c|2 arch/arm/mach-omap2/hdq1w.c |4 -
Re: OMAP baseline test results for v3.7-rc3
On 10/30/2012 8:06 AM, Paul Walmsley wrote: Here are some basic OMAP test results for Linux v3.7-rc3. Logs and other details at: http://www.pwsan.com/omap/testlogs/test_v3.7-rc3/20121028162003/ Passing tests - Boot to userspace: 2420n800, 3517evm, 3530es3beagle, 3730beaglexm, 37xxevm, 4430es2panda, 5912osk, am335xbone PM ret/off, suspend + dynamic idle: (none) Failing tests: fixed by posted patches -- Boot tests: * 2430sdp: vfp_reload_hw oops during MMC initialization - Kernel attempts to save FP registers that don't exist; fix posted: - http://www.spinics.net/lists/arm-kernel/msg200646.html - added to rmk's patch system as 7566/1 * AM335x Beaglebone: omap2plus_defconfig kernels don't boot - Due to GPMC missing support for DT - Temporary workaround at http://www.spinics.net/lists/arm-kernel/msg200787.html - May be fixed now, pending retest: - http://marc.info/?l=linux-omapm=135082257727502w=2 This is surprising, I have tested v3.7-rc3 branch on AM335xBone platform and its booting up for me without any issues. Jon had submitted another patch which fixes boot issue on Bone. https://patchwork.kernel.org/patch/1606471/ ==Boot Log U-Boot# U-Boot# U-Boot# U-Boot# U-Boot# U-Boot# mmc rescan 0 U-Boot# fatload mmc 0 8000 am335x-bone.dtb reading am335x-bone.dtb 4391 bytes read U-Boot# fatload mmc 0 8100 uImage reading uImage 3841320 bytes read U-Boot# fatload mmc 0 8200 ramdisk-pm.gz reading ramdisk-pm.gz 2022580 bytes read U-Boot# setenv bootargs console=ttyO0,115200n8 mem=256M root=/dev/ram rw initrd=0x8200,16MB ramdisk_size=65536 earlyprintk=serial U-Boot# bootm 8100 - 8000 ## Booting kernel from Legacy Image at 8100 ... Image Name: Linux-3.7.0-rc3 Image Type: ARM Linux Kernel Image (uncompressed) Data Size:3841256 Bytes = 3.7 MiB Load Address: 80008000 Entry Point: 80008000 Verifying Checksum ... OK ## Flattened Device Tree blob at 8000 Booting using the fdt blob at 0x8000 Loading Kernel Image ... OK OK Loading Device Tree to 8fe65000, end 8fe69126 ... OK Starting kernel ... [0.00] Booting Linux on physical CPU 0 [0.00] Linux version 3.7.0-rc3 (a0393758@psplinux064) (gcc version 4.5.3 20110311 (prerelease) (GCC) ) #1 SMP Tue Oct 30 09:46:04 IST 2012 [0.00] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c53c7d [0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [0.00] Machine: Generic AM33XX (Flattened Device Tree), model: TI AM335x BeagleBone [0.00] Memory policy: ECC disabled, Data cache writeback [0.00] AM335X ES1.0 (neon ) [0.00] PERCPU: Embedded 9 pages/cpu @c0f03000 s12928 r8192 d15744 u36864 [0.00] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64768 [0.00] Kernel command line: console=ttyO0,115200n8 mem=256M root=/dev/ram rw initrd=0x8200,16MB ramdisk_size=65536 earlyprintk=serial [0.00] PID hash table entries: 1024 (order: 0, 4096 bytes) [0.00] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) [0.00] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) [0.00] Memory: 255MB = 255MB total [0.00] Memory: 229112k/229112k available, 33032k reserved, 0K highmem [0.00] Virtual kernel memory layout: [0.00] vector : 0x - 0x1000 ( 4 kB) [0.00] fixmap : 0xfff0 - 0xfffe ( 896 kB) [0.00] vmalloc : 0xd080 - 0xff00 ( 744 MB) [0.00] lowmem : 0xc000 - 0xd000 ( 256 MB) [0.00] pkmap : 0xbfe0 - 0xc000 ( 2 MB) [0.00] modules : 0xbf00 - 0xbfe0 ( 14 MB) [0.00] .text : 0xc0008000 - 0xc06c4b68 (6899 kB) [0.00] .init : 0xc06c5000 - 0xc0715280 ( 321 kB) [0.00] .data : 0xc0716000 - 0xc07a13a0 ( 557 kB) [0.00].bss : 0xc07a13c4 - 0xc0cfbd6c (5483 kB) [0.00] Hierarchical RCU implementation. [0.00] RCU restricting CPUs from NR_CPUS=2 to nr_cpu_ids=1. [0.00] NR_IRQS:16 nr_irqs:16 16 [0.00] IRQ: Found an INTC at 0xfa20 (revision 5.0) with 128 interrupts [0.00] Total of 128 interrupts on 1 active controller [0.00] OMAP clockevent source: GPTIMER1 at 2400 Hz [0.00] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956ms [0.00] OMAP clocksource: GPTIMER2 at 2400 Hz [0.00] Console: colour dummy device 80x30 [0.00] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar [0.00] ... MAX_LOCKDEP_SUBCLASSES: 8 [0.00] ... MAX_LOCK_DEPTH: 48 [0.00] ... MAX_LOCKDEP_KEYS:8191 [0.00] ... CLASSHASH_SIZE:
Re: [PATCH 2/3] RTC: omap-rtc: enable pm_runtime
On 10/18/2012 9:23 PM, Daniel Mack wrote:
This is needed as preparation for platforms where using pm runtime usage
is mandatory.
Signed-off-by: Daniel Mack zon...@gmail.com
It looks like, you just duplicated effort here.
RTC patches have been already submitted quite some time back for AM33xx,
probably you missed to do google before spending time on this.
Patch Series -
http://www.mail-archive.com/davinci-linux-open-source@linux.davincidsp.com/msg23253.html
Denial,
It would be really helpful if you could test these patches and ack them.
Just FYI, we have bunch of parallel activities going inside team to
upstream all the patches/module/drivers/features, so to avoid such
duplication of effort, I suggest you to google for the patches or ping
on mailing list.
Thanks,
Vaibhav
---
drivers/rtc/rtc-omap.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c
index 0b614e3..baa876e 100644
--- a/drivers/rtc/rtc-omap.c
+++ b/drivers/rtc/rtc-omap.c
@@ -17,6 +17,7 @@
#include linux/module.h
#include linux/ioport.h
#include linux/delay.h
+#include linux/pm_runtime.h
#include linux/rtc.h
#include linux/bcd.h
#include linux/platform_device.h
@@ -322,6 +323,9 @@ static int __init omap_rtc_probe(struct platform_device
*pdev)
goto fail;
}
+ pm_runtime_enable(pdev-dev);
+ pm_runtime_get_sync(pdev-dev);
+
rtc = rtc_device_register(pdev-name, pdev-dev,
omap_rtc_ops, THIS_MODULE);
if (IS_ERR(rtc)) {
@@ -420,6 +424,8 @@ static int __exit omap_rtc_remove(struct platform_device
*pdev)
free_irq(omap_rtc_alarm, rtc);
rtc_device_unregister(rtc);
+ pm_runtime_put_sync(pdev-dev);
+ pm_runtime_disable(pdev-dev);
iounmap(rtc_base);
release_mem_region(mem-start, resource_size(mem));
return 0;
@@ -442,11 +448,15 @@ static int omap_rtc_suspend(struct platform_device
*pdev, pm_message_t state)
else
rtc_write(0, OMAP_RTC_INTERRUPTS_REG);
+ pm_runtime_put_sync(pdev-dev);
+
return 0;
}
static int omap_rtc_resume(struct platform_device *pdev)
{
+ pm_runtime_get_sync(pdev-dev);
+
if (device_may_wakeup(pdev-dev))
disable_irq_wake(omap_rtc_alarm);
else
--
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Re: Fwd: [PATCH 2/5] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data for davinci_mdio
On 10/17/2012 11:43 PM, Richard Cochran wrote:
Paul,
Would you please take this bugfix for 3.7-rc2? The suggestion to mail
you came from Toni Lindgren. The context where it came from is here:
http://lists.arm.linux.org.uk/lurker/message/20121015.191630.bdae3c50.en.html
Thanks,
Richard
- Forwarded message from Richard Cochran richardcoch...@gmail.com -
Date: Mon, 15 Oct 2012 21:16:32 +0200
From: Richard Cochran richardcoch...@gmail.com
To: net...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org, Arnd Bergmann a...@arndb.de,
David Miller da...@davemloft.net,
Russell King li...@arm.linux.org.uk,
Mugunthan V N mugunthan...@ti.com
Subject: [PATCH 2/5] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data for
davinci_mdio
X-Mailer: git-send-email 1.7.2.5
From: Mugunthan V N mugunthan...@ti.com
This patch adds minimal hwmod support for davinci mdio driver. This patch
requires rework on parent child relation between cpsw and davinci mdio
hwmod data to support runtime PM.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 34 ++-
1 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 59d5c1c..f96bbc0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -650,8 +650,7 @@ static struct omap_hwmod_class_sysconfig
am33xx_cpgmac_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x8,
.syss_offs = 0x4,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
-SYSS_HAS_RESET_STATUS),
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
MSTANDBY_NO),
.sysc_fields= omap_hwmod_sysc_type3,
@@ -682,6 +681,8 @@ static struct omap_hwmod am33xx_cpgmac0_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
+HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE),
Hey Richard,
I feel you have picked up this patch in premature state, I didn't like
this NO_RESET and NO_IDLE flag to be set for MDIO.
Couple of reasons,
1. These flags were added for validation, so I expect cpsw driver
should work without these flags set. I tested it mounting NFS as rootFS
and it works for me.
2. There is HW bug as far as idle (in turn ocp reset) is concerned, and
needs special handling for this. I already have patch for this, which I
will submit it to the list.
http://arago-project.org/git/projects/?p=linux-am33x.git;a=commitdiff;h=a28da2ac98f173f97dbbb46be1ce0a3879f21a11
Note: Sorry for long commit description, it was screwed up by someone
while git push.
I have pushed the tested branch to (linux-omap/master + CPSW patches) -
https://github.com/hvaibhav/am335x-linux/tree/am335x-upstream-staging
Thanks,
Vaibhav
};
/*
@@ -2510,6 +2511,34 @@ static struct omap_hwmod_addr_space
am33xx_elm_addr_space[] = {
{ }
};
+/* mdio class */
+static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
+ .name = davinci_mdio,
+};
+
+struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
+ {
+ .pa_start = 0x4A101000,
+ .pa_end = 0x4A101000 + SZ_256 - 1,
+ .flags = ADDR_MAP_ON_INIT,
+ },
+ { }
+};
+
+static struct omap_hwmod am33xx_mdio_hwmod = {
+ .name = davinci_mdio,
+ .class = am33xx_mdio_hwmod_class,
+ .clkdm_name = cpsw_125mhz_clkdm,
+ .main_clk = cpsw_125mhz_gclk,
+};
+
+struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
+ .master = am33xx_cpgmac0_hwmod,
+ .slave = am33xx_mdio_hwmod,
+ .addr = am33xx_mdio_addr_space,
+ .user = OCP_USER_MPU,
+};
+
static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
.master = am33xx_l4_ls_hwmod,
.slave = am33xx_elm_hwmod,
@@ -3371,6 +3400,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[]
__initdata = {
am33xx_l3_main__tptc2,
am33xx_l3_s__usbss,
am33xx_l4_hs__cpgmac0,
+ am33xx_cpgmac0__mdio,
NULL,
};
--
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Re: Fwd: [PATCH 2/5] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data for davinci_mdio
On 10/19/2012 12:14 AM, Richard Cochran wrote: On Thu, Oct 18, 2012 at 03:46:15AM +, Paul Walmsley wrote: Probably the driver was submitted before any SoC integration support was available. Grepping for 'cpsw' under arch/ turns up only AM33xx. AM335x didn't have device enumeration support in the mainline kernel until 3.7, via commit a2cfc509bc4eeef9f5c4607b1203f17f22ea2a36 (ARM: OMAP3+: hwmod: Add AM33XX HWMOD data). So I don't see how it could have worked with mainline. ... But it seems that the CPSW has never worked in the mainline kernel. So this particular patch is not fixing a regression. Therefore we shouldn't send it upstream during the -rc time period. Instead we'll schedule it to be sent a few weeks later, during the 3.8 merge window. Let's think about this some more: The driver's commit is from March and is included in v3.4-rc1. You say it will be working in 3.8, after 3.7 comes out, in about December. So how long does it take between merging code and actually getting it working? Sorry to harp on this so much, but I try out my patches with the tip of the appropriate tree before sending them, or when I cannot, at least I put into the log compile tested only or something like that. Another important point is, this driver is also required and used for Davinci family of devices (arch/mach/mach-davinci/). Thanks, Vaibhav Thanks, Richard ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: OMAP2+: gpmc: Fix kernel BUG for DT boot mode
With recent changes in omap gpmc driver code, in case of DT
boot mode, where bootloader does not configure gpmc cs space
will result into kernel BUG() inside gpmc_mem_init() function,
as gpmc cs0 gpmc_config7[0].csvalid bit is set to '1' and
gpmc_config7[0].baseaddress is set to '0' on reset.
This use-case is applicable for any board/EVM which doesn't have
any peripheral connected to gpmc cs0, for example BeagleXM and
BeagleBone, so DT boot mode fails.
This patch adds of_have_populated_dt() check before creating
device, so that for DT boot mode, gpmc probe will not be called
which is expected behavior, as gpmc is not supported yet from DT.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Afzal Mohammed af...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc Paul Walmsley p...@pwsan.com
---
This should go in for rc1, as this breaks AM33xx boot.
arch/arm/mach-omap2/gpmc.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 8ab1e1b..c68f9e1 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -981,6 +981,10 @@ static int __init omap_gpmc_init(void)
struct platform_device *pdev;
char *oh_name = gpmc;
+ /* If dtb is there, the devices will be created dynamically */
+ if (of_have_populated_dt())
+ return -ENODEV;
+
oh = omap_hwmod_lookup(oh_name);
if (!oh) {
pr_err(Could not look up %s\n, oh_name);
--
1.7.0.4
--
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Re: [PATCH V2 0/7] ARM: OMAP2+: Add device-tree support for timers
On 9/26/2012 10:23 PM, Jon Hunter wrote: On 09/20/2012 06:53 PM, Tony Lindgren wrote: * Benoit Cousson b-cous...@ti.com [120919 19:24]: Hi Tony, I was about to take the DTS patch, but was wondering if you will pull the driver changes for 3.7. I suggest that you do a separate branch on top of Paul's hwmod series when he posts those if that works for you? Benoit, I see that you have pulled in the DTS patch. Do you guys want me to rebase the remaining patches with Rob's change on Tony's master branch and re-submit? Jon, Sorry for delayed response, But I tried using your omap_test application to validate this patch series, but it is failing for me. How did you test it? Are you running same test application at your end? I am debugging this issue, i just thought I should tell you this before its too late. Below is the log - [root@arago /]# echo 3 /tmp/omap-test/timer/one [ 79.612223] omap_dm_timer_request_specific: Please use omap_dm_timer_request_by_cap() [ 79.620636] Timer 3 not available! [root@arago /]# [root@arago /]# echo 3 /tmp/omap-test/timer/all [ 135.111949] Testing 48042000.timer with 2400 Hz clock ... [root@arago /]# [ 137.457389] Timer read test PASSED! No errors, 100 loops [ 137.463267] Timer interrupt test PASSED! [ 137.467650] Testing 48042000.timer with 32768 Hz clock ... [ 139.816892] Timer read test PASSED! No errors, 100 loops [ 139.830776] Timer interrupt test PASSED! [ 139.835245] Testing 48044000.timer with 2400 Hz clock ... [ 142.183912] Timer read test PASSED! No errors, 100 loops [ 142.189734] Timer interrupt test PASSED! [ 142.194076] Testing 48044000.timer with 32768 Hz clock ... [ 144.543451] Timer read test PASSED! No errors, 100 loops [ 144.557334] Timer interrupt test PASSED! [ 144.561806] Testing 48046000.timer with 2400 Hz clock ... [ 146.910469] Timer read test PASSED! No errors, 100 loops [ 147.910493] Timer interrupt test FAILED! No interrupt occurred in 1 sec [ 147.917598] Testing 48046000.timer with 32768 Hz clock ... [ 150.262203] Timer read test PASSED! No errors, 100 loops [ 151.262049] Timer interrupt test FAILED! No interrupt occurred in 1 sec [ 151.269298] Testing 48048000.timer with 2400 Hz clock ... [ 153.613596] Timer read test PASSED! No errors, 100 loops [ 154.613618] Timer interrupt test FAILED! No interrupt occurred in 1 sec [ 154.620725] Testing 48048000.timer with 32768 Hz clock ... [ 156.965324] Timer read test PASSED! No errors, 100 loops [ 157.965176] Timer interrupt test FAILED! No interrupt occurred in 1 sec [ 157.972419] Testing 4804a000.timer with 2400 Hz clock ... [root@arago /]# [ 160.316753] Timer read test PASSED! No errors, 100 loops [root@arago /]# [ 161.316728] Timer interrupt test FAILED! No interrupt occurred in 1 sec [ 161.323912] Testing 4804a000.timer with 32768 Hz clock ... [root@arago /]# [ 163.668490] Timer read test PASSED! No errors, 100 loops [ 164.668328] Timer interrupt test FAILED! No interrupt occurred in 1 sec [ 164.675545] Tested 5 timers, skipped 6 timers and detected 6 errors [ 164.682202] Test iteration 0 complete in 29 secs [ 164.687104] Test summary: Iterations 1, Errors 6 Cheers Jon ___ devicetree-discuss mailing list devicetree-disc...@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: am33xx: clk: Update clkdev table to add mcasp alias
After Rajendra's common-clock preparation series,
commit (a1978ef4da1 - ARM: omap: hwmod: get rid of
all omap_clk_get_by_name usage) the clkdev table need to
update with an entry for clocks used by hwmod to have
clock name same as the alias.
Without this, the clk_get() in omap_hwmod would fail.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
---
arch/arm/mach-omap2/clock33xx_data.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock33xx_data.c
b/arch/arm/mach-omap2/clock33xx_data.c
index b87b88c..114ab4b 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -1035,6 +1035,8 @@ static struct omap_clk am33xx_clks[] = {
CLK(NULL, pruss_ocp_gclk, pruss_ocp_gclk,
CK_AM33XX),
CLK(davinci-mcasp.0, NULL, mcasp0_fck,CK_AM33XX),
CLK(davinci-mcasp.1, NULL, mcasp1_fck,CK_AM33XX),
+ CLK(NULL, mcasp0_fck, mcasp0_fck,CK_AM33XX),
+ CLK(NULL, mcasp1_fck, mcasp1_fck,CK_AM33XX),
CLK(NULL, mmc2_fck, mmc2_fck, CK_AM33XX),
CLK(NULL, mmu_fck, mmu_fck, CK_AM33XX),
CLK(NULL, smartreflex0_fck, smartreflex0_fck,
CK_AM33XX),
--
1.7.0.4
--
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[PATCH v2] ARM: OMAP2+: Add am335x evm and bone targets to common Makefile
This adds am335x-evm and am335x-bone dtb targets to 'make dtbs', just like other platforms. Signed-off-by: Vaibhav Hiremath hvaib...@ti.com --- Changes from V1: - Move target to common Makefile instead of the per-platform file. arch/arm/boot/dts/Makefile |4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d4ad2df..6f2dae8 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -75,7 +75,9 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ omap4-pandaES.dtb \ omap4-var_som.dtb \ omap4-sdp.dtb \ - omap5-evm.dtb + omap5-evm.dtb \ + am335x-evm.dtb \ + am335x-bone.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb dtb-$(CONFIG_ARCH_U8500) += snowball.dtb dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ -- 1.7.0.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL] ARM: AM33xx: hwmod/clock: add hwmod data and some clock/hwmod fixes for 3.7
On 9/12/2012 9:30 PM, Paul Walmsley wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi Tony, The following changes since commit 55d512e245bc7699a8800e23df1a24195dd08217: Linux 3.6-rc5 (2012-09-08 16:43:45 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending.git tags/omap-devel-a-for-3.7 Are you sure you have pushed this branch/repo? I am not able to fetch/see this. Thanks, Vaibhav for you to fetch changes up to e76f55a1e301c230f4a7bbef5db60ad7d90d6e94: ARM: AM33XX: clock: Add dcan clock aliases for device-tree (2012-09-12 09:19:54 -0600) - AM33xx hwmod data and miscellaneous clock and hwmod fixes. AM33xx should now boot on mainline after this is applied, according to Vaibhav. Basic build, boot, and PM test transcripts are here: http://www.pwsan.com/omap/testlogs/am33xx_hwmod_clock_devel_3.7/20120912092510/ - object size (delta in bytes from test_v3.6-rc5 (55d512e245bc7699a8800e23df1a24195dd08217)): text data bss total kernel +8972+16432 +64 +25468 2430_testconfig 0 0 0 0 5912osk_testconfig +8784+16440 0 +25224 am33xx_testconfig +8960+16464 0 +25424 n800_b_testconfig +8980+16408 0 +25388 n800_multi_omap2xxx +8960+16488 0 +25448 n800_testconfig 0 0 0 0 omap1510_defconfig 0 0 0 0 omap1_defconfig +8832+16488 0 +25320 omap2_4_testconfig +8864+16472 0 +25336 omap2plus_defconfig +8800+16440 0 +25240 omap2plus_defconfig_cpupm +8860+16488 0 +25348 omap2plus_no_pm +4712+16488 +64 +21264 omap3_4_testconfig +8956+16408 0 +25364 omap3_testconfig +8872+16472 0 +25344 omap4_testconfig +9040+16464 0 +25504 rmk_omap3430_ldp_oldconfig +4820+14632 0 +19452 rmk_omap4430_sdp_oldconfig Note that the object sizes for many .configs are larger than they should be, since CONFIG_SOC_AM33XX is selected by default during 'make oldnoconfig'. The next time these configs are updated, it will be deselected - probably during the next baseline test. Vaibhav Hiremath (4): ARM: OMAP2+: hwmod: Hook-up am33xx support in omap_hwmod framework ARM: OMAP3+: hwmod: Add AM33XX HWMOD data ARM: OMAP2+: dpll: Add missing soc_is_am33xx() check for common functions ARM: AM33XX: clock: Add dcan clock aliases for device-tree arch/arm/mach-omap2/Makefile |1 + arch/arm/mach-omap2/clkt_dpll.c |4 +- arch/arm/mach-omap2/clock33xx_data.c |2 + arch/arm/mach-omap2/dpll3xxx.c |4 +- arch/arm/mach-omap2/io.c |2 + arch/arm/mach-omap2/omap_hwmod.c | 178 ++ arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 3381 ++ arch/arm/plat-omap/include/plat/omap_hwmod.h |1 + 8 files changed, 3569 insertions(+), 4 deletions(-) create mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_data.c -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAEBAgAGBQJQULEwAAoJEMePsQ0LvSpL5tkP/AvKupNQDh4kOUko8p4ljgTB HxndMBqUMUFvF+M5oyhzdS8+dETLUbMZqHMFtrVA81YwC1nfQy3jbfi+PRch54k1 OhK8phTowsD2og8COkdZQ2sa4DJEnE2cSZtFvkswmuPw3AHjoD4zVXhQslXUJx12 ntzha96bNJbEvzzLUgREo4zCYkTGuLkIQVFJ7XdvySsKyma3ZnKep3VuZH2ymQUP DCKQxuPjAzic6JGGclf2hOQri0Q6bEx+LfFM3YEpdZ7eiZWVakT5XZS7tEv+gWxr HEuX8oeUGijTCNNEqCnGKQaRgkhrm6l/HKDyyXplFI8KZT4zr442IxVbgIK8vvRg 1Yvv1qos83Mm4KV/KDaTFftnd58ca/2bUxL37+1Sf8cGAL0R5TSyinCzMBJ9qYEo xkVoGdfs6Qeea5VY+ImnYC+pEMow9w0pykgUT5grsN/J8HjjFk7oWoSLOEbmzWf+ A+AWZwbLAcC56XkF7nKzBFZ8PeTDZu6y2maNqB5uJXV/QTe6MQ4VCAs0a6MogYVs DKBVnsT5LgCQBXUQPchXfNY61h2erXbTq33cmPLdXzQypbmFmmkbeO6NFvEO60O/ egHgeen+wckLJblPEJ4pq+hLY23Q04Ml8btFuiMz//2fBaPOGy62nyWoc6wxlaKm 31DSw8rqS9Z4uUsdgjiI =2rIh -END PGP SIGNATURE- ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ARM: AM33XX: hwmod: Remove platform specific header files
With recent mainline changes on gpio and mcspi drivers, the platform specific header files (plat/gpio.h and plat/mcspi.h) have been removed, which results into build failure on AM33XX hwmod data, which was still using these headers. This patch removes such both gpio and spi header file entry from omap_hwmod_33xx_data.c. Signed-off-by: Vaibhav Hiremath hvaib...@ti.com Cc: Paul Walmsley p...@pwsan.com --- arch/arm/mach-omap2/omap_hwmod_33xx_data.c |6 -- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index de7a3ab..7b7ed08 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -14,12 +14,14 @@ * GNU General Public License for more details. */ +#include linux/io.h +#include linux/platform_data/gpio-omap.h +#include linux/platform_data/spi-omap2-mcspi.h + #include plat/omap_hwmod.h #include plat/cpu.h -#include plat/gpio.h #include plat/dma.h #include plat/mmc.h -#include plat/mcspi.h #include plat/i2c.h #include omap_hwmod_common_data.h -- 1.7.0.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] ARM: AM33XX: hwmod: Add OMAP_INTC_START offset to all module int nos
With recent migration of omap architectures to SPARSE_IRQ framework,
it is important to add OMAP_INTC_START to all interrupt numbers
which will be eventually requested by drivers.
This is required in order to get AM33XX boot functionality.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 168 ++--
1 files changed, 84 insertions(+), 84 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 7b7ed08..3c320f4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -72,7 +72,7 @@ static struct omap_hwmod_class am33xx_emif_hwmod_class = {
};
static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
- { .name = ddrerr0, .irq = 101 },
+ { .name = ddrerr0, .irq = 101 + OMAP_INTC_START },
{ .irq = -1 }
};
@@ -102,8 +102,8 @@ static struct omap_hwmod_class am33xx_l3_hwmod_class = {
/* l3_main (l3_fast) */
static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
- { .name = l3debug, .irq = 9 },
- { .name = l3appint, .irq = 10 },
+ { .name = l3debug, .irq = 9 + OMAP_INTC_START },
+ { .name = l3appint, .irq = 10 + OMAP_INTC_START },
{ .irq = -1 }
};
@@ -220,10 +220,10 @@ static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
/* mpu */
static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
- { .name = emuint, .irq = 0 },
- { .name = commtx, .irq = 1 },
- { .name = commrx, .irq = 2 },
- { .name = bench, .irq = 3 },
+ { .name = emuint, .irq = 0 + OMAP_INTC_START },
+ { .name = commtx, .irq = 1 + OMAP_INTC_START },
+ { .name = commrx, .irq = 2 + OMAP_INTC_START },
+ { .name = bench, .irq = 3 + OMAP_INTC_START },
{ .irq = -1 }
};
@@ -255,7 +255,7 @@ static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] =
{
};
static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
- { .name = txev, .irq = 78 },
+ { .name = txev, .irq = 78 + OMAP_INTC_START },
{ .irq = -1 }
};
@@ -291,14 +291,14 @@ static struct omap_hwmod_rst_info am33xx_pruss_resets[] =
{
};
static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
- { .name = evtout0, .irq = 20 },
- { .name = evtout1, .irq = 21 },
- { .name = evtout2, .irq = 22 },
- { .name = evtout3, .irq = 23 },
- { .name = evtout4, .irq = 24 },
- { .name = evtout5, .irq = 25 },
- { .name = evtout6, .irq = 26 },
- { .name = evtout7, .irq = 27 },
+ { .name = evtout0, .irq = 20 + OMAP_INTC_START },
+ { .name = evtout1, .irq = 21 + OMAP_INTC_START },
+ { .name = evtout2, .irq = 22 + OMAP_INTC_START },
+ { .name = evtout3, .irq = 23 + OMAP_INTC_START },
+ { .name = evtout4, .irq = 24 + OMAP_INTC_START },
+ { .name = evtout5, .irq = 25 + OMAP_INTC_START },
+ { .name = evtout6, .irq = 26 + OMAP_INTC_START },
+ { .name = evtout7, .irq = 27 + OMAP_INTC_START },
{ .irq = -1 }
};
@@ -332,7 +332,7 @@ static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
};
static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
- { .name = gfxint, .irq = 37 },
+ { .name = gfxint, .irq = 37 + OMAP_INTC_START },
{ .irq = -1 }
};
@@ -387,7 +387,7 @@ static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class =
{
};
static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
- { .irq = 16 },
+ { .irq = 16 + OMAP_INTC_START },
{ .irq = -1 }
};
@@ -528,7 +528,7 @@ static struct omap_hwmod_class am33xx_aes_hwmod_class = {
};
static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
- { .irq = 102 },
+ { .irq = 102 + OMAP_INTC_START },
{ .irq = -1 }
};
@@ -552,7 +552,7 @@ static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
};
static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
- { .irq = 108 },
+ { .irq = 108 + OMAP_INTC_START },
{ .irq = -1 }
};
@@ -579,7 +579,7 @@ static struct omap_hwmod_class
am33xx_smartreflex_hwmod_class = {
/* smartreflex0 */
static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
- { .irq = 120 },
+ { .irq = 120 + OMAP_INTC_START },
{ .irq = -1 }
};
@@ -599,7 +599,7 @@ static struct omap_hwmod am33xx_smartreflex0_hwmod = {
/* smartreflex1 */
static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
- { .irq = 121 },
+ { .irq = 121 + OMAP_INTC_START },
{ .irq = -1 }
};
@@ -625,7 +625,7 @@ static struct omap_hwmod_class am33xx_control_hwmod_class =
{
};
static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
- { .irq = 8 },
+ { .irq = 8 + OMAP_INTC_START },
{ .irq = -1 }
};
@@ -665,10 +665,10 @@ static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class
= {
};
static struct
[PATCH 0/2] ARM: AM33XX: hwmod: Minor fixes for v3.7
Today Paul had given pull request for AM33XX hwmod data and related patches, and I wanted to make sure that things are working fine irrespective of merge window changes coming in. I without adding any further delay I tried the pull request on linux-next/master (-rc6) linux-omap/master (-rc4 + omap merges) and found that hwmod needs minor changes required for both, build and to boot. [1/2]: With recent mainline changes on gpio and mcspi drivers, platform specific header files (plat/gpio.h and plat/mcspi.h) have been removed, which results into build failure. Observed on linux-next/master checkout. [2/2]: With recent migration of omap architectures to SPARSE_IRQ framework, it is important to add OMAP_INTC_START to all interrupt numbers which will be eventually requested by drivers. Observed on linux-omap/master checkout. Both the patches have been varified for, - Build Test (omap2plus_defconfig) - Boot tested on Bone - Sparse check pass Paul, Request to review these patches and give another pull request for this. Vaibhav Hiremath (2): ARM: AM33XX: hwmod: Remove platform specific header files ARM: AM33XX: hwmod: Add OMAP_INTC_START offset to all module int nos arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 174 ++-- 1 files changed, 88 insertions(+), 86 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/29] Move OMAP2+ over to use COMMON clock
On 9/11/2012 12:05 PM, Paul Walmsley wrote:
Hi Rajendra,
A CCF testing branch has been built here. The base is v3.6-rc5, plus the
most recent version of the Common Clock Framework preparation patches that
you posted to the list, [PATCH v4 0/3] Prepare for OMAP2+ movement to
Common Clk, but updated to take RMK's feedback into account. Then the
'clk-next-omap-3.6-rc3' branch from your repo at
'git://github.com/rrnayak/linux.git' was added. Then some patches to drop
the old arch/arm/mach-omap2/clock*_data.c files were added.
This branch was then run through checkpatch.pl, and all of the parenthesis
alignment warnings have been fixed. I don't know what to do about these
crazy DECLARE_CLK_* macros; they have so many arguments that they are
basically impossible to read. Mike and I discussed converting them
into C99 structure initializers with named fields, but am not sure if it's
a readability advantage; it's probably going to be write-only data
either way. I've reflowed many of them to save diffstat but there are
quite a few more to go.
The branch was then built with a set of testing Kconfigs. Here's what was
found: (these are still being investigated)
- The OMAP4-only testconfig and rmk's OMAP4430-SDP Kconfigs failed:
undefined reference to `omap2_clkt_iclk_allow_idle':
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/build/omap4_testconfig/
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/build/rmk_omap4430_sdp_oldconfig/
- RMK's OMAP3430-LDP Kconfig failed with a whole set of warnings:
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/build/rmk_omap3430_ldp_oldconfig/
The kernel built with omap2plus_defconfig was then booted on several
OMAP2+ boards. Here's what was found:
- The kernel wouldn't boot on either the 3517EVM nor CM-T3517 boards.
This turned out to be due to some missing AM35XX clkdev aliases, the
lack of which cause the CCF code to panic. The patch that adds the
OMAP3 data has been updated to fix that bug and an HSOTGUSB clkdev
alias bug that was found by visual inspection.
- The 3730 Beagle XM issued a warning and stack trace upon boot.
Debugging with Mike, this turned out to be due to a bug in the
modified omap2_init_clksel_parent() function: it returned a register
bitfield rather than an array index. The patch that modifies this
function was then updated to fix the bug.
- The 2420 N800 seems to have some kind of MMC-related problem
that prevents it from booting. Still looking into this:
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/boot/2420n800/2420n800_log.txt
Then the branch was PM-tested to determine whether it can suspend and
serial-resume properly, and whether dynamic idle works. These tests
didn't go so well:
- 3530ES3 Beagleboard here was able to enter retention-idle
suspend, and leave it with serial wakeup, but the CORE powerdomain never
entered a low-power state. Dynamic retention-idle with serial wakeup
never resumed, and the test stopped there:
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/boot/3530es3beagle/3530es3beagle_log.txt
- 37xx EVM and 3730 Beagle XM fared better; they made it through the whole
test program, but the CORE powerdomain also never entered a low-power
state:
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/boot/37xxevm/37xxevm_log.txt
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/boot/3730beaglexm/3730beaglexm_log.txt
- 4430ES2 Panda never made past the first retention-idle suspend:
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/boot/4430es2panda/4430es2panda_log.txt
Could you please take a look and see if you can identify why the patches
aren't passing the tests? I can't send these upstream until they pass the
PM tests.
This testing branch can be found at the branch named
common_clk_testing_devel_3.7 of git://git.pwsan.com/linux-2.6
The testbed reports from this branch can be found here:
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/
And the baseline test reports from v3.6-rc5 can be found here:
http://www.pwsan.com/omap/testlogs/test_v3.6-rc5/20120908202511/
I tried this branch on BeagleBone platform and needs one small typo
correction in hwmod data patch (submitted earlier, which you are going
to queue it)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index de7a3ab..767a77d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -1441,7 +1441,7 @@ static struct omap_hwmod am33xx_mmc2_hwmod = {
.clkdm_name = l3s_clkdm,
Re: [PATCH v2 3/3] usb: musb: omap: Add device tree support for omap musb glue
On 9/11/2012 2:39 PM, Kishon Vijay Abraham I wrote:
Added device tree support for omap musb driver and updated the
Documentation with device tree binding information.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/usb/omap-usb.txt | 33
drivers/usb/musb/omap2430.c| 54
2 files changed, 87 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/omap-usb.txt
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt
b/Documentation/devicetree/bindings/usb/omap-usb.txt
new file mode 100644
index 000..29a043e
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -0,0 +1,33 @@
+OMAP GLUE
+
+OMAP MUSB GLUE
+ - compatible : Should be ti,omap4-musb or ti,omap3-musb
+ - ti,hwmods : must be usb_otg_hs
+ - multipoint : Should be 1 indicating the musb controller supports
+ multipoint. This is a MUSB configuration-specific setting.
+ - num_eps : Specifies the number of endpoints. This is also a
+ MUSB configuration-specific setting. Should be set to 16
+ - ram_bits : Specifies the ram address size. Should be set to 12
+ - interface_type : This is a board specific setting to describe the type of
+ interface between the controller and the phy. It should be 0 or 1
+ specifying ULPI and UTMI respectively.
+ - mode : Should be 3 to represent OTG. 1 signifies HOST and 2
+ represents PERIPHERAL.
+ - power : Should be 50. This signifies the controller can supply upto
+ 100mA when operating in host mode.
+
+SOC specific device node entry
+usb_otg_hs: usb_otg_hs@4a0ab000 {
+ compatible = ti,omap4-musb;
+ ti,hwmods = usb_otg_hs;
+ multipoint = 1;
+ num_eps = 16;
+ ram_bits = 12;
+};
reg and interrupt properties are missing here.
I would encourage to specify reg and interrupt properties in every
node getting newly added to the OMAP DTS files.
Thanks,
Vaibhav
+
+Board specific device node entry
+usb_otg_hs {
+ interface_type = 1;
+ mode = 3;
+ power = 50;
+};
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index f4d9503..d96873b 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -30,6 +30,7 @@
#include linux/init.h
#include linux/list.h
#include linux/io.h
+#include linux/of.h
#include linux/platform_device.h
#include linux/dma-mapping.h
#include linux/pm_runtime.h
@@ -470,8 +471,11 @@ static u64 omap2430_dmamask = DMA_BIT_MASK(32);
static int __devinit omap2430_probe(struct platform_device *pdev)
{
struct musb_hdrc_platform_data *pdata = pdev-dev.platform_data;
+ struct omap_musb_board_data *data;
struct platform_device *musb;
struct omap2430_glue*glue;
+ struct device_node *np = pdev-dev.of_node;
+ struct musb_hdrc_config *config;
struct resource *res;
int ret = -ENOMEM;
@@ -501,6 +505,42 @@ static int __devinit omap2430_probe(struct
platform_device *pdev)
if (glue-control_otghs == NULL)
dev_dbg(pdev-dev, Failed to obtain control memory\n);
+ if (np) {
+ pdata = devm_kzalloc(pdev-dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata) {
+ dev_err(pdev-dev,
+ failed to allocate musb platfrom data\n);
+ ret = -ENOMEM;
+ goto err1;
+ }
+
+ data = devm_kzalloc(pdev-dev, sizeof(*data), GFP_KERNEL);
+ if (!data) {
+ dev_err(pdev-dev,
+ failed to allocate musb board data\n);
+ ret = -ENOMEM;
+ goto err1;
+ }
+
+ config = devm_kzalloc(pdev-dev, sizeof(*config), GFP_KERNEL);
+ if (!data) {
+ dev_err(pdev-dev,
+ failed to allocate musb hdrc config\n);
+ goto err1;
+ }
+
+ of_property_read_u32(np, mode, (u32 *)pdata-mode);
+ of_property_read_u32(np, interface_type,
+ (u32 *)data-interface_type);
+ of_property_read_u32(np, num_eps, (u32 *)config-num_eps);
+ of_property_read_u32(np, ram_bits, (u32 *)config-ram_bits);
+ of_property_read_u32(np, power, (u32 *)pdata-power);
+ config-multipoint = of_property_read_bool(np, multipoint);
+
+ pdata-board_data = data;
+ pdata-config = config;
+ }
+
pdata-platform_ops = omap2430_ops;
platform_set_drvdata(pdev, glue);
@@ -597,12 +637,26 @@ static struct dev_pm_ops omap2430_pm_ops = {
#define DEV_PM_OPS NULL
#endif
+#ifdef
Re: [PATCH 13/16] ARM: omap: move platform_data definitions
On 9/11/2012 7:54 PM, Shilimkar, Santosh wrote: On Tue, Sep 11, 2012 at 7:47 PM, Arnd Bergmann a...@arndb.de wrote: On Tuesday 11 September 2012, Shilimkar, Santosh wrote: Just curious to know how you came with some of the above header names ? plat/mcbsp --- dsp-mcbsp.h There is no connection of DSP with McBSP. omap-mcbsp.h would been a better name. This one was a mistake on my side, as Tony and Peter already pointed out. How about asoc-mcbsp.h or asoc-omap-mcbsp.h? After re-reading the cover-letter and your below response, 'asoc-omap-mcbsp.h' seems to be fine. Note that mcbsp is also applicable to Davinci family of devices. Thanks, Vaibhav plat/nand.h -- /mtd-nand-omap2.h plat/onenand.h -- /mtd-onenand-omap2.h May be omap-nand.h and omap-onenand.h plat/mcspi.h--spi-omap2-mcspi.h May be omap-spi.h As I wrote in the introductory mail, I tried to always prefix the file names with the subsystem, followed by the name of the driver, in order to standardize on just one set of rules. Just read that now. The drivers implementing the three headers above are: drivers/mtd/nand/omap2.c drivers/mtd/onenand/omap2.c drivers/spi/spi-omap2-mcspi.c so these all seem appropriate. Sorry I missed the subsystem prefix point. These names seems to be fine then. Regards Santosh ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 02/10] ARM: OMAP: Fix timer posted mode support
On 9/6/2012 12:34 AM, Jon Hunter wrote:
Currently the dmtimer posted mode is being enabled when the function
__omap_dm_timer_reset() is called. This function is only being called for
OMAP1 timers and OMAP2+ timers that are being used as system timers. Hence,
for OMAP2+ timers that are NOT being used as a system timer, posted mode is
not enabled but the timer-posted variable is still set (incorrectly) in
the omap_dm_timer_prepare() function.
This is a regression introduced by commit 3392cdd3 (ARM: OMAP: dmtimer:
switch-over to platform device driver) which changed the code to only call
omap_dm_timer_reset() for OMAP1 devices. Although this is a regression from
the original code it only impacts performance and so is not needed for stable.
Signed-off-by: Jon Hunter jon-hun...@ti.com
---
arch/arm/mach-omap2/timer.c |3 +--
arch/arm/plat-omap/dmtimer.c | 14 +-
arch/arm/plat-omap/include/plat/dmtimer.h |9 -
3 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 5471706..e24ee0f 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -194,10 +194,9 @@ static int __init omap_dm_timer_init_one(struct
omap_dm_timer *timer,
}
__omap_dm_timer_init_regs(timer);
__omap_dm_timer_reset(timer, 1, 1);
- timer-posted = 1;
+ __omap_dm_timer_enable_posted(timer);
timer-rate = clk_get_rate(timer-fclk);
-
timer-reserved = 1;
return res;
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index c34f55b..22790ea 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -122,21 +122,15 @@ static void omap_dm_timer_wait_for_reset(struct
omap_dm_timer *timer)
static void omap_dm_timer_reset(struct omap_dm_timer *timer)
{
- omap_dm_timer_enable(timer);
if (timer-pdev-id != 1) {
omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
omap_dm_timer_wait_for_reset(timer);
}
-
__omap_dm_timer_reset(timer, 0, 0);
- omap_dm_timer_disable(timer);
- timer-posted = 1;
}
int omap_dm_timer_prepare(struct omap_dm_timer *timer)
{
- int ret;
-
/*
* FIXME: OMAP1 devices do not use the clock framework for dmtimers so
* do not call clk_get() for these devices.
@@ -150,13 +144,15 @@ int omap_dm_timer_prepare(struct omap_dm_timer *timer)
}
}
+ omap_dm_timer_enable(timer);
+
if (timer-capability OMAP_TIMER_NEEDS_RESET)
omap_dm_timer_reset(timer);
- ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
+ __omap_dm_timer_enable_posted(timer);
+ omap_dm_timer_disable(timer);
- timer-posted = 1;
- return ret;
+ return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
May be I am speculating here and I know this is tested and supposed to
work, but Isn't it safe to set parent keeping module enables.
I would still recommend you to move is before omap_dm_timer_disable().
There could be devices or hw bugs/issues, may be related to standby/idle
protocol happening underneath module enable/disable.
Thanks,
Vaibhav
}
static inline u32 omap_dm_timer_reserved_systimer(int id)
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h
b/arch/arm/plat-omap/include/plat/dmtimer.h
index 5ce2f00..fa9d04b 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -348,13 +348,20 @@ static inline void __omap_dm_timer_reset(struct
omap_dm_timer *timer,
l |= 1 2;
__raw_writel(l, timer-io_base + OMAP_TIMER_OCP_CFG_OFFSET);
+}
+
+static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
+{
+ if (timer-posted)
+ return;
if (timer-errata OMAP_TIMER_ERRATA_I103_I767)
return;
- /* Match hardware reset default of posted mode */
__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
OMAP_TIMER_CTRL_POSTED, 0);
+ timer-context.tsicr = OMAP_TIMER_CTRL_POSTED;
+ timer-posted = 1;
}
/**
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Re: [PATCH 09/10] ARM: OMAP: Add dmtimer interrupt disable function
On 9/6/2012 12:34 AM, Jon Hunter wrote:
The OMAP dmtimer driver does not currently have a function to disable the
timer interrupts. For some timer instances the timer interrupt enable
function can be used to disable the interrupts because the same interrupt
enable register is used to disable interrupts. However, some timer instances
have separate interrupt enable/disable registers and so this will not work.
Therefore, add a dedicated function to disable interrupts.
I think you should clearly specify which timer and which device you are
referring to.
Thanks,
Vaibhav
Signed-off-by: Jon Hunter jon-hun...@ti.com
---
arch/arm/plat-omap/dmtimer.c | 31
+
arch/arm/plat-omap/include/plat/dmtimer.h |3 ++-
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 541adbb..3b548dc 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -612,6 +612,37 @@ int omap_dm_timer_set_int_enable(struct omap_dm_timer
*timer,
}
EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
+/**
+ * omap_dm_timer_set_int_disable - disable timer interrupts
+ * @timer: pointer to timer handle
+ * @mask:bit mask of interrupts to be disabled
+ *
+ * Disables the specified timer interrupts for a timer.
+ */
+int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
+{
+ u32 l = mask;
+
+ if (unlikely(!timer))
+ return -EINVAL;
+
+ omap_dm_timer_enable(timer);
+
+ if (timer-revision == 1)
+ l = __raw_readl(timer-irq_ena) ~mask;
+
+ __raw_writel(l, timer-irq_dis);
+ l = __omap_dm_timer_read(timer, OMAP_TIMER_WAKEUP_EN_REG) ~mask;
+ __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
+
+ /* Save the context */
+ timer-context.tier = ~mask;
+ timer-context.twer = ~mask;
+ omap_dm_timer_disable(timer);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_disable);
+
unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
{
unsigned int l;
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h
b/arch/arm/plat-omap/include/plat/dmtimer.h
index b3150a3..820f0ce 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -130,6 +130,7 @@ int omap_dm_timer_set_pwm(struct omap_dm_timer *timer,
int def_on, int toggle, i
int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int
value);
+int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask);
unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int
value);
@@ -314,7 +315,7 @@ static inline void __omap_dm_timer_init_regs(struct
omap_dm_timer *timer)
OMAP_TIMER_V1_SYS_STAT_OFFSET;
timer-irq_stat = timer-io_base + OMAP_TIMER_V1_STAT_OFFSET;
timer-irq_ena = timer-io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
- timer-irq_dis = NULL;
+ timer-irq_dis = timer-io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
timer-pend = timer-io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
timer-func_base = timer-io_base;
} else {
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Re: [PATCH 00/10] ARM: OMAP: DMTIMER fixes and clean-up
On 9/6/2012 12:34 AM, Jon Hunter wrote:
This series includes several fixes for the OMAP DMTIMER driver and a few
clean-ups to simplify some of the code. This series is based upon 3.6-rc4.
Tested on OMAP5912 OSK, OMAP2420 H4, OMAP3430 Beagle and OMAP4430 Panda.
Testing includes ...
1. Booting kernel on above boards
2. Set date and ensuring time of day is correct after 24 hours
3. Checking the timer counter is incrementing when configuring and starting
a timer
4. Checking the timer overflow interrupt when timer expires.
5. Using different clock sources to operate the timer with.
6. Running a loop test overnight that continually runs test #3 and #4 for
each available timer
On the other hand I have validated this patch-series on both AM37xEVM
and BeagleBone platform. I used the test code which you shared with me
to validate it.
AM33XX Clock tree needs minor change here,
diff --git a/arch/arm/mach-omap2/clock33xx_data.c
b/arch/arm/mach-omap2/clock33xx_data.c
index a4006b2..daa36a5 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -1070,6 +1070,8 @@ static struct omap_clk am33xx_clks[] = {
CLK(NULL, gfx_fck_div_ck, gfx_fck_div_ck,
CK_AM33XX),
CLK(NULL, sysclkout_pre_ck, sysclkout_pre_ck,
CK_AM33XX),
CLK(NULL, clkout2_ck, clkout2_ck,CK_AM33XX),
+ CLK(NULL, timer_32k_ck, clkdiv32k_ick, CK_AM33XX),
+ CLK(NULL, timer_sys_ck, sys_clkin_ck, CK_AM33XX),
};
int __init am33xx_clk_init(void)
Thanks,
Vaibhav
Jon Hunter (10):
ARM: OMAP3+: Implement timer workaround for errata i103 and i767
ARM: OMAP: Fix timer posted mode support
ARM: OMAP3: Correct HWMOD DMTIMER SYSC register declarations
ARM: OMAP2/3: Define HWMOD software reset status for DMTIMERs
ARM: OMAP2+: Don't use __omap_dm_timer_reset()
ARM: OMAP: Fix dmtimer reset for timer1
ARM: OMAP: Clean-up dmtimer reset code
ARM: OMAP: Clean-up timer posted mode support
ARM: OMAP: Add dmtimer interrupt disable function
ARM: OMAP: Remove unnecessary call to clk_get()
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 15 ++-
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 41
arch/arm/mach-omap2/omap_hwmod_44xx_data.c |4 +
arch/arm/mach-omap2/timer.c| 27 +++--
arch/arm/plat-omap/dmtimer.c | 109
+---
arch/arm/plat-omap/include/plat/dmtimer.h | 95 ++---
6 files changed, 184 insertions(+), 107 deletions(-)
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Re: [GIT PULL] ARM: OMAP2+: PRCM/hwmod: some fixes for 3.6-rc
On 9/5/2012 9:45 PM, Paul Walmsley wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi Tony, The following changes since commit 4cbe5a555fa58a79b6ecbb6c531b8bab0650778d: Linux 3.6-rc4 (2012-09-01 10:39:58 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending.git tags/omap-fixes-a-for-3.6rc for you to fetch changes up to 8a94febc21743fe121bdaf1d1470d98b1135acc2: Merge branches 'clkdev_fixes_3.6rc', 'clkdm_fixes_3.6rc' and 'hwmod_data_fixes_a_3.6rc' into omap_fixes_a_3.6rc (2012-09-03 11:52:02 -0600) Paul, Isn't below patch good for -rc candidate (so as part of this 'fixes')? ARM: OMAP2+: dpll: Add missing soc_is_am33xx() check for common functions https://patchwork.kernel.org/patch/1371611/ Thanks, Vaibhav - Some hwmod, clockdomain, am335x fixes against v3.6-rc4. Test logs can be found here: http://www.pwsan.com/omap/testlogs/omap_fixes_a_3.6rc/20120904110254/ - Misael Lopez Cruz (1): ARM: OMAP: hwmod code: Disable module when hwmod enable fails Paul Walmsley (2): ARM: OMAP3xxx: clockdomain: fix software supervised wakeup/sleep Merge branches 'clkdev_fixes_3.6rc', 'clkdm_fixes_3.6rc' and 'hwmod_data_fixes_a_3.6rc' into omap_fixes_a_3.6rc Tero Kristo (2): ARM: OMAP3: hwmod data: fix iva2 reset info ARM: OMAP4: hwmod data: temporarily comment out data for the sl2if IP block Vaibhav Hiremath (1): ARM: OMAP2+: am33xx: Fix the timer fck clock naming convention arch/arm/mach-omap2/clock33xx_data.c | 14 arch/arm/mach-omap2/clockdomain2xxx_3xxx.c | 50 ++-- arch/arm/mach-omap2/cm-regbits-34xx.h |1 + arch/arm/mach-omap2/omap_hwmod.c |1 + arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 15 +++-- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 12 +++ 6 files changed, 75 insertions(+), 18 deletions(-) -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAEBAgAGBQJQR3ooAAoJEMePsQ0LvSpLQ94P/1DzifcEU/R0YFLZF+20XPd5 hOrUk2EWn7SlPAxZJMG1K+In7EZ3K4r7IYaROIbwUWJTO/hQdx6zwyAOec/qnutV WYRnQ+KN+x7gd8EYZPnS1voiqeH0SnP/wI2ri9UcMTV+tpAtO6ibD10iAUmBxSfX x9HaYb65cYA+ulMsQXX2g1oejV2+4eR+fWWI0+bGfOxIHPGQcEhSGSvNkDs9W/bE QfBKmTWeizx2jlRlXBG8pxV8MtEIDtwRZitcgTnyStw8LMqR/YnCOLIRoU2OHVcP UtQwIxtNqGaoqm3i6IXGM1BLI4ZT/EN0kr+1LZVl1WoFqL1tDrn39dSvSVfxfGje CjhkTk9XVzbV4GV+1yTt6JlfD3AimLwYqihKDs21a2OleAsQAu8a+gftsJtSp8Xu fscJcjr1c5JKyjE5CzbH7mbDgX+LTveZV3b6pT1m599UidP/NZ4yzUYrmkTmoSkk JdqQlTgahLxjBoBBDfNhavuCzA4cYNh6q0Pt6GhmWc1ZC7aR3+7xU4wUNXAvbKoe mUksJmjROwk4MlswLqpIkgt8iiEGa2LzHcyL7eVD2+oCun0FFlolqa1R3gTF9x8y Hr8iNv4b0OeX55oSZ53ijIDY4WwgmBVvnVjiWEiAkBuwqsghRLii5eemX572szGU lTSzo95e8x7kAaO6moNI =wc/t -END PGP SIGNATURE- ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 1/4] mfd: smsc: Add support for smsc gpio io/keypad driver
On 9/5/2012 5:06 PM, Sourav Poddar wrote: smsc ece1099 is a keyboard scan or gpio expansion device. The patch create keypad and gpio expander child for this multi function smsc driver. Cc: Samuel Ortiz sa...@linux.intel.com Cc: Benoit Cousson b-cous...@ti.com Cc: Felipe Balbi ba...@ti.com Cc: Santosh Shilimkar santosh.shilim...@ti.com Signed-off-by: Sourav Poddar sourav.pod...@ti.com --- Changes since v1: - Use Kconfig option correctly - Add regmap_config paramters - Modify formatting of logs for devid - Move read/write function to headed file as an inline function. Documentation/smsc_ece1099.txt | 56 drivers/mfd/Kconfig| 12 drivers/mfd/Makefile |1 + drivers/mfd/smsc-ece1099.c | 110 +++ include/linux/mfd/smsc.h | 111 5 files changed, 290 insertions(+), 0 deletions(-) create mode 100644 Documentation/smsc_ece1099.txt create mode 100644 drivers/mfd/smsc-ece1099.c create mode 100644 include/linux/mfd/smsc.h diff --git a/Documentation/smsc_ece1099.txt b/Documentation/smsc_ece1099.txt new file mode 100644 index 000..6b492e8 --- /dev/null +++ b/Documentation/smsc_ece1099.txt @@ -0,0 +1,56 @@ +What is smsc-ece1099? +-- + +The ECE1099 is a 40-Pin 3.3V Keyboard Scan Expansion +or GPIO Expansion device. The device supports a keyboard +scan matrix of 23x8. The device is connected to a Master +via the SMSC BC-Link interface or via the SMBus. +Keypad scan Input(KSI) and Keypad Scan Output(KSO) signals +are multiplexed with GPIOs. + +Interrupt generation + + +Interrupts can be generated by an edge detection on a GPIO +pin or an edge detection on one of the bus interface pins. +Interrupts can also be detected on the keyboard scan interface. +The bus interrupt pin (BC_INT# or SMBUS_INT#) is asserted if +any bit in one of the Interrupt Status registers is 1 and +the corresponding Interrupt Mask bit is also 1. + +In order for software to determine which device is the source +of an interrupt, it should first read the Group Interrupt Status Register +to determine which Status register group is a source for the interrupt. +Software should read both the Status register and the associated Mask register, +then AND the two values together. Bits that are 1 in the result of the AND +are active interrupts. Software clears an interrupt by writing a 1 to the +corresponding bit in the Status register. + +Communication Protocol +-- + +- SMbus slave Interface + The host processor communicates with the ECE1099 device + through a series of read/write registers via the SMBus + interface. SMBus is a serial communication protocol between + a computer host and its peripheral devices. The SMBus data + rate is 10KHz minimum to 400 KHz maximum + +- Slave Bus Interface + The ECE1099 device SMBus implementation is a subset of the + SMBus interface to the host. The device is a slave-only SMBus device. + The implementation in the device is a subset of SMBus since it + only supports four protocols. + + The Write Byte, Read Byte, Send Byte, and Receive Byte protocols are the + only valid SMBus protocols for the device. + +- BC-LinkTM Interface + The BC-Link is a proprietary bus that allows communication + between a Master device and a Companion device. The Master + device uses this serial bus to read and write registers + located on the Companion device. The bus comprises three signals, + BC_CLK, BC_DAT and BC_INT#. The Master device always provides the + clock, BC_CLK, and the Companion device is the source for an + independent asynchronous interrupt signal, BC_INT#. The ECE1099 + supports BC-Link speeds up to 24MHz. diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index d1facef..991ef15 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -385,6 +385,18 @@ config MFD_T7L66XB help Support for Toshiba Mobile IO Controller T7L66XB +config MFD_SMSC + bool Support for the SMSC ECE1099 series chips + depends on I2C=y + select MFD_CORE + select REGMAP_I2C + help +If you say yes here you get support for the +ece1099 chips from SMSC. + +To compile this driver as a module, choose M here: the +module will be called smsc. + config MFD_TC6387XB bool Support Toshiba TC6387XB depends on ARM HAVE_CLK diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 79dd22d..f587d91 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -77,6 +77,7 @@ obj-$(CONFIG_EZX_PCAP) += ezx-pcap.o obj-$(CONFIG_MCP)+= mcp-core.o obj-$(CONFIG_MCP_SA11X0) += mcp-sa11x0.o obj-$(CONFIG_MCP_UCB1200)+= ucb1x00-core.o
Re: [PATCHv2 2/4] Input: keypad: Add smsc ece1099 keypad driver
On 9/5/2012 5:06 PM, Sourav Poddar wrote:
From: G, Manjunath Kondaiah manj...@ti.com
SMSC ECE1099 is a keyboard scan or GPIO expansion device.The device
supports a keypad scan matrix of 23*8.This driver uses this
device as a keypad driver.
Cc: Dmitry Torokhov dmitry.torok...@gmail.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Felipe Balbi ba...@ti.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: G, Manjunath Kondaiah manj...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Acked-by: Felipe Balbi ba...@ti.com
---
Changes since v1:
- Prevent the use of kfree since devm_kzalloc was used.
- Use devexit around remove api
drivers/input/keyboard/Kconfig | 11 +
drivers/input/keyboard/Makefile |1 +
drivers/input/keyboard/smsc-ece1099-keypad.c | 306
++
3 files changed, 318 insertions(+), 0 deletions(-)
create mode 100644 drivers/input/keyboard/smsc-ece1099-keypad.c
diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index c50fa75..2a2d374 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -593,6 +593,17 @@ config KEYBOARD_TWL4030
To compile this driver as a module, choose M here: the
module will be called twl4030_keypad.
+config KEYBOARD_SMSC
+ tristate SMSC ECE1099 keypad support
+ depends on I2C=y
Any specific reason behind =y
+ help
+ Say Y here if your board use the smsc keypad controller
+ for omap5 defconfig. It's safe to say enable this
+ even on boards that don't use the keypad controller.
+
+ To compile this driver as a module, choose M here: the
+ module will be called smsc-ece1099-keypad.
+
config KEYBOARD_XTKBD
tristate XT keyboard
select SERIO
diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
index 44e7600..0f2aa26 100644
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -52,5 +52,6 @@ obj-$(CONFIG_KEYBOARD_TC3589X) +=
tc3589x-keypad.o
obj-$(CONFIG_KEYBOARD_TEGRA) += tegra-kbc.o
obj-$(CONFIG_KEYBOARD_TNETV107X) += tnetv107x-keypad.o
obj-$(CONFIG_KEYBOARD_TWL4030) += twl4030_keypad.o
+obj-$(CONFIG_KEYBOARD_SMSC)+= smsc-ece1099-keypad.o
obj-$(CONFIG_KEYBOARD_XTKBD) += xtkbd.o
obj-$(CONFIG_KEYBOARD_W90P910) += w90p910_keypad.o
diff --git a/drivers/input/keyboard/smsc-ece1099-keypad.c
b/drivers/input/keyboard/smsc-ece1099-keypad.c
new file mode 100644
index 000..71cd7d6
--- /dev/null
+++ b/drivers/input/keyboard/smsc-ece1099-keypad.c
@@ -0,0 +1,306 @@
+/*
+ * SMSC_ECE1099 Keypad driver
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/i2c.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/init.h
+#include linux/interrupt.h
+#include linux/input.h
+#include linux/gpio.h
+#include linux/slab.h
+#include linux/jiffies.h
+#include linux/input/matrix_keypad.h
+#include linux/delay.h
+#include linux/mfd/core.h
+#include linux/mfd/smsc.h
+#include linux/of_gpio.h
+#include linux/of.h
+
+#define KEYPRESS_TIME 200
+
+struct smsc_keypad {
+ struct smsc *smsc;
+ struct matrix_keymap_data *keymap_data;
+ unsigned int last_key_state[16];
+ unsigned int last_col;
+ unsigned int last_key_ms[16];
+ unsigned short *keymap;
+ struct i2c_client *client;
+ struct input_dev *input;
+ int rows, cols;
+ int row_shift;
+ bool no_autorepeat;
+ unsignedirq;
+ struct device *dev;
+};
+
+static void smsc_kp_scan(struct smsc_keypad *kp)
+{
+ struct input_dev *input = kp-input;
+ int i, j;
+ int row, col;
+ int temp, code;
+ unsigned int new_state[16];
+ unsigned int bits_changed;
+ int this_ms;
+
+ smsc_write(kp-dev, SMSC_KP_INT_MASK, 0x00);
+ smsc_write(kp-dev, SMSC_KP_INT_STAT, 0xFF);
+
+ /* Scan for row and column */
+ for (i = 0; i kp-cols; i++) {
+ smsc_write(kp-dev, SMSC_KP_OUT, SMSC_KSO_EVAL + i);
+ /* Read Row Status */
+ smsc_read(kp-dev, SMSC_KP_IN, temp);
+ if (temp == 0xFF)
+ continue;
+
+ col = i;
+ for (j = 0; j kp-rows; j++) {
+ if ((temp 0x01) != 0x00) {
+ temp = temp 1;
+ continue;
+ }
+
+ row = j;
+ new_state[col] = (1 row);
+ bits_changed = kp-last_key_state[col] ^ new_state[col];
+
Re: [PATCHv2 4/4] gpio: smscece: Add support for gpio IO expander feature
On 9/5/2012 5:07 PM, Sourav Poddar wrote:
smsc can be used as an gpio io expander device also. So adding
support for configuring smsc pins as a gpio.
Cc: Benoit Cousson b-cous...@ti.com
Cc: Felipe Balbi ba...@ti.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
Changes since v1:
- Use edge triggering instead of level
- Use devm_reuest_threaded_irq
- In remove part, use irq_free_desc and
irq_remove_domain api.
drivers/gpio/Kconfig|7 +
drivers/gpio/Makefile |1 +
drivers/gpio/gpio-smscece.c | 380
+++
3 files changed, 388 insertions(+), 0 deletions(-)
create mode 100644 drivers/gpio/gpio-smscece.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b16c8a7..e883929 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -444,6 +444,13 @@ config GPIO_ADP5588_IRQ
Say yes here to enable the adp5588 to be used as an interrupt
controller. It requires the driver to be built in the kernel.
+config GPIO_SMSCECE
+ tristate SMSCECE 1099 I2C GPIO expander
+ depends on I2C
+ help
+ This option enables support for 18 GPIOs found
+ on SMSC ECE 1099 GPIO Expanders.
+
comment PCI GPIO expanders:
config GPIO_CS5535
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 153cace..7c803c5 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_GPIO_74X164) += gpio-74x164.o
obj-$(CONFIG_GPIO_AB8500)+= gpio-ab8500.o
obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o
obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o
+obj-$(CONFIG_GPIO_SMSCECE) += gpio-smscece.o
obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o
diff --git a/drivers/gpio/gpio-smscece.c b/drivers/gpio/gpio-smscece.c
new file mode 100644
index 000..68a17fa
--- /dev/null
+++ b/drivers/gpio/gpio-smscece.c
@@ -0,0 +1,380 @@
+/*
+ * GPIO Chip driver for smsc
+ * SMSC I/O Expander and QWERTY Keypad Controller
+ *
+ * Copyright 2012 Texas Instruments Inc.
+ *
+ * Licensed under the GPL-2 or later.
Can you put proper license here?
+ */
+
+#include linux/module.h
+#include linux/kernel.h
+#include linux/slab.h
+#include linux/init.h
+#include linux/i2c.h
+#include linux/gpio.h
+#include linux/interrupt.h
+#include linux/irqdomain.h
+#include linux/irq.h
+#include linux/mfd/smsc.h
+#include linux/err.h
+
+struct smsc_gpio {
+ struct device *dev;
+ struct smsc *smsc;
+ struct gpio_chip gpio_chip;
+ struct mutex lock; /* protect cached dir, dat_out */
+ /* protect serialized access to the interrupt controller bus */
+ struct mutex irq_lock;
+ struct irq_domain *irq_domain;
+ unsigned gpio_start;
+ int type;
+ int flags;
+ int irq;
+ int irq_base;
+ unsigned int gpio_base;
+ unsigned int dat_out[5];
+ unsigned int dir[5];
+ unsigned int irq_trig_fall[5];
+ unsigned int irq_trig_raise[5];
+ unsigned int int_en[5];
+ unsigned int irq_mask[5];
+ unsigned int irq_stat[5];
+};
+
+static int smsc_gpio_get_value(struct gpio_chip *chip, unsigned off)
+{
+ struct smsc_gpio *sg =
+ container_of(chip, struct smsc_gpio, gpio_chip);
+ unsigned int get;
+ return !!(smsc_read(sg-dev,
+ (SMSC_GPIO_DATA_IN_START + SMSC_BANK(off)) SMSC_BIT(off),
+ get));
+}
+
+static void smsc_gpio_set_value(struct gpio_chip *chip,
+ unsigned off, int val)
+{
+ unsigned bank, bit;
+ struct smsc_gpio *sg =
+ container_of(chip, struct smsc_gpio, gpio_chip);
+
+ bank = SMSC_BANK(off);
+ bit = SMSC_BIT(off);
+
+ mutex_lock(sg-lock);
+ if (val)
+ sg-dat_out[bank] |= bit;
+ else
+ sg-dat_out[bank] = ~bit;
+
+ smsc_write(sg-dev, SMSC_GPIO_DATA_OUT_START + bank,
+sg-dat_out[bank]);
+ mutex_unlock(sg-lock);
+}
+
+static int smsc_gpio_direction_input(struct gpio_chip *chip, unsigned off)
+{
+ unsigned int reg;
+ struct smsc_gpio *sg =
+ container_of(chip, struct smsc_gpio, gpio_chip);
+ int reg_dir;
+
+ mutex_lock(sg-lock);
+ reg_dir = SMSC_CFG_START + off;
+ smsc_read(sg-dev, reg_dir, reg);
+ reg |= SMSC_GPIO_INPUT_LOW;
+ mutex_unlock(sg-lock);
+
+ return smsc_write(sg-dev, reg_dir, reg);
+}
+
+static int smsc_gpio_direction_output(struct gpio_chip *chip,
+ unsigned off, int val)
+{
+ unsigned int reg;
+ struct smsc_gpio *sg =
+ container_of(chip, struct smsc_gpio, gpio_chip);
+ int reg_dir;
+
+ mutex_lock(sg-lock);
+ reg_dir =
Re: [PATCH] ARM: omap_hwmod: Fix up resource names when booted with devicetree
On 9/5/2012 7:57 PM, Benoit Cousson wrote: Hi Paul, On 08/24/2012 06:20 PM, Peter Ujfalusi wrote: Hi Paul, On 08/24/2012 06:38 PM, Paul Walmsley wrote: Do we need both this one and your '[PATCH] driver core: Check if r-name is valid in platform_get_resource_byname()' ? Or would that second patch be enough? Is the crash happening in the platform_get_resource_byname() iterator? The crash happens in platform_get_resource_byname(). What I see as a problem that when we boot without DT the r-name is configured for the hwmods. If we boot with DT we discard the resources created by the OF (which also have the r-name configured). We replace the resources from hwmods but we do not fix up the resource names (which is done in other cases). I have sent the patch for the drivers core as well since I think it is a good practice anyway to check for NULL pointer before strcmp(). Either is good, but IMHO we should fix this in omap_hwmod (at least). Yes, clearly we do have a corner case today due to the mix of hwmod / DTS resource management. - Legacy boot + hwmod resources is OK - DTS boot with DTS resources will be OK - DTS boot with hwmod resources is not OK since the resource name will not be populated in the case resources are not named :-( If you are OK, I'll take that patch along with Vaibhav one to handle properly the resources from DTS long with the DTS patches I'm queuing for 3.7. Benoit, Note that this patch will add device name to all resources, since none of the resource will have name property and may break drivers; especially after my patch which respects DT resources. Also I just read the thread you started sometime back on _byname api, not sure that was the conclusion, but it seems like it is not recommended to use _byname. The driver should be fixed while converting to DT. http://lists.infradead.org/pipermail/linux-arm-kernel/2011-August/060861.html Thanks, Vaibhav Thanks, Benoit ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RESEND 3/4] ARM: AM33XX: board-generic: Add of_dev_auxdata to pass d_can raminit
On 9/6/2012 4:48 AM, Tony Lindgren wrote:
Hi,
* AnilKumar Ch anilku...@ti.com [120905 04:14]:
Add of_dev_auxdata to pass d_can raminit callback APIs to initialize
d_can RAM. D_CAN RAM initialization bits are present in CONTROL module
address space, which can be accessed by platform specific code. So
callback functions are added to serve this purpose, this can done by
using of_dev_auxdata.
Two callback APIs are added to of_dev_auxdata used by two instances of
D_CAN IP. These callback functions are used to enable/disable D_CAN RAM
from CAN driver.
I'd like to avoid the callbacks to the platform code where possible as
that's the biggest pain we already have moving things to work with device
tree for the existing drivers.
And I'm pretty convinced that whatever is done with callbacks should be
done with some Linux generic framework from the driver that has it's own
binding, such as clock framework, regulator framework, pinctrl framework,
runtime PM etc.
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -37,11 +40,46 @@ static struct of_device_id omap_dt_match_table[]
__initdata = {
{ }
};
+void d_can_hw_raminit(unsigned int instance, bool enable)
+{
+u32 val;
+
+val = readl(AM33XX_CTRL_REGADDR(AM33XX_CONTROL_DCAN_RAMINIT));
+if (enable) {
+val = ~AM33XX_DCAN_RAMINIT_START_MASK(instance);
+val |= AM33XX_DCAN_RAMINIT_START_MASK(instance);
+writel(val, AM33XX_CTRL_REGADDR(AM33XX_CONTROL_DCAN_RAMINIT));
+} else {
+val = ~AM33XX_DCAN_RAMINIT_START_MASK(instance);
+writel(val, AM33XX_CTRL_REGADDR(AM33XX_CONTROL_DCAN_RAMINIT));
+}
+}
This part does not look good to me, this is tweaking the omap control
module register bits directly. To me it seems that the above should
be implemented in the omap/am33xx hwmod code that gets initialized when
the dcan driver calls pm_runtime_enable()? Paul, got any other ideas?
Technically yes, this is required during module enable/disable sequence.
But there is no way currently supported in hwmod layer. Also I am not
quite sure how many other modules/devices may use this.
Couple of more examples I have here,
In case of AM3517 we have similar SoC integration, where VPFE, MAC and
USB required clock control (handled by clock-tree) and interrupt status
(handled by callbacks) from control module.
So not sure whether we can get rid of callbacks until we have control
module MFD driver (on which Konstantin is working on)
Thanks,
Vaibhav
Regards,
Tony
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Re: [PATCH 01/10] ARM: OMAP3+: Implement timer workaround for errata i103 and i767
On 9/6/2012 12:34 AM, Jon Hunter wrote:
Errata Titles:
i103: Delay needed to read some GP timer, WD timer and sync timer registers
after wakeup (OMAP3/4)
i767: Delay needed to read some GP timer registers after wakeup (OMAP5)
Description (i103/i767):
If a General Purpose Timer (GPTimer) is in posted mode (TSICR [2].POSTED=1),
due to internal resynchronizations, values read in TCRR, TCAR1 and TCAR2
registers right after the timer interface clock (L4) goes from stopped to
active may not return the expected values. The most common event leading to
this situation occurs upon wake up from idle.
GPTimer non-posted synchronization mode is not impacted by this limitation.
Workarounds:
1). Disable posted mode
2). Use static dependency between timer clock domain and MPUSS clock domain
3). Use no-idle mode when the timer is active
Workarounds #2 and #3 are not pratical from a power standpoint and so
workaround #1 has been implemented. Disabling posted mode adds some CPU
overhead
for configuring the timers as the CPU has to wait for the write to complete.
However, disabling posted mode guarantees correct operation.
Please note that it is safe to use posted mode for timers if the counter
(TCRR)
and capture (TCARx) registers will never be read. An example of this is the
clock-event system timer. This is used by the kernel to schedule events
however,
the timers counter is never read and capture registers are not used. Given
that
the kernel configures this timer often yet never reads the counter register it
is safe to enable posted mode in this case. Hence, for the timer used for
kernel
clock-events, posted mode is enabled by overriding the errata for devices that
are impacted by this defect.
Although both dmtimers and watchdogs are impacted by this defect this patch
only
implements the workaround for the dmtimer. Currently the watchdog driver does
not read the counter register and so no workaround is necessary.
Confirmed with Vaibhav Hiremath that this bug also impacts AM33xx devices.
Thanks for pinging me on this and getting it confirmed.
Signed-off-by: Jon Hunter jon-hun...@ti.com
---
arch/arm/mach-omap2/timer.c |9 +++
arch/arm/plat-omap/dmtimer.c |2 ++
arch/arm/plat-omap/include/plat/dmtimer.h | 39
+
3 files changed, 50 insertions(+)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 2ff6d41..5471706 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -208,6 +208,13 @@ static void __init omap2_gp_clockevent_init(int
gptimer_id,
{
int res;
+ /*
+ * For clock-event timers we never read the timer counter and
+ * so we are not impacted by errata i103 and i767. Therefore,
+ * we can safely ignore this errata for clock-event timers.
+ */
+ __omap_dm_timer_populate_errata(clkev, OMAP_TIMER_ERRATA_I103_I767);
+
Couple of points,
1. It is confusing to me, as you are passing the errata flag so i expect
api should set it. Why can't we do reverse way, you pass 0 here, since
you don't want to set and pass this flag every other places where you
want to enable this errata.
2. Why can't we enable for all timers? Even though clock-event is anyway
not reading it, but still is is applicable to it, right?
3. Why can't we just simply Add this flag to hwmod_data file and read it
back in omap_timer_init() and omap_dm_timer_init_one(). Wouldn't that be
a good approach to handle it?
Thanks,
Vaibhav
res = omap_dm_timer_init_one(clkev, gptimer_id, fck_source);
BUG_ON(res);
@@ -305,6 +312,8 @@ static void __init omap2_gptimer_clocksource_init(int
gptimer_id,
{
int res;
+ __omap_dm_timer_populate_errata(clksrc, 0);
+
res = omap_dm_timer_init_one(clksrc, gptimer_id, fck_source);
BUG_ON(res);
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 938b50a..c34f55b 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -730,6 +730,8 @@ static int __devinit omap_dm_timer_probe(struct
platform_device *pdev)
timer-pdev = pdev;
timer-capability = pdata-timer_capability;
+ __omap_dm_timer_populate_errata(timer, 0);
+
/* Skip pm_runtime_enable for OMAP1 */
if (!(timer-capability OMAP_TIMER_NEEDS_RESET)) {
pm_runtime_enable(dev);
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h
b/arch/arm/plat-omap/include/plat/dmtimer.h
index 19e7fa5..5ce2f00 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -36,6 +36,7 @@
#include linux/delay.h
#include linux/io.h
#include linux/platform_device.h
+#include plat/cpu.h
#ifndef __ASM_ARCH_DMTIMER_H
#define __ASM_ARCH_DMTIMER_H
@@ -61,6 +62,16 @@
#define OMAP_TIMER_HAS_PWM 0x2000
#define
Re: [PATCH 1/3] gpio-twl4030: get platform data from device tree
On 9/3/2012 7:24 PM, Florian Vaussard wrote:
Adds a number of missing properties to the device tree of
twl4030/gpio:
- ti,use-leds - .use_leds
- ti,debounce - .debounce
- ti,mmc-cd- .mmc_cd
- ti,pullups - .pullups
- ti,pulldowns - .pulldowns
Signed-off-by: Florian Vaussard florian.vauss...@epfl.ch
---
drivers/gpio/gpio-twl4030.c | 86 +-
1 files changed, 59 insertions(+), 27 deletions(-)
diff --git a/drivers/gpio/gpio-twl4030.c b/drivers/gpio/gpio-twl4030.c
index 94256fe..dabe76b 100644
--- a/drivers/gpio/gpio-twl4030.c
+++ b/drivers/gpio/gpio-twl4030.c
@@ -395,6 +395,33 @@ static int __devinit gpio_twl4030_debounce(u32 debounce,
u8 mmc_cd)
static int gpio_twl4030_remove(struct platform_device *pdev);
+static struct twl4030_gpio_platform_data *of_gpio_twl4030(struct device *dev)
+{
+ struct twl4030_gpio_platform_data *omap_twl_info;
+ const char *of_use_leds;
+
+ omap_twl_info = devm_kzalloc(dev, sizeof(*omap_twl_info), GFP_KERNEL);
+ if (!omap_twl_info)
+ return NULL;
+
+ omap_twl_info-gpio_base = -1;
+
+ of_property_read_string(dev-of_node, ti,use-leds, of_use_leds);
+ if (!strcmp(of_use_leds, true))
+ omap_twl_info-use_leds = true;
+
You can replace this with
omap_twl_info-use_leds = of_property_read_bool(dev-of_node,
ti,use-leds);
Otherwise looks OK to me, also I have tested it on OMAP3EVM.
Tested--Acked-By: Vaibhav Hiremath hvaib...@ti.com
Thanks,
Vaibhav
+ of_property_read_u32(dev-of_node, ti,debounce,
+ omap_twl_info-debounce);
+ of_property_read_u32(dev-of_node, ti,mmc-cd,
+ (u32 *)omap_twl_info-mmc_cd);
+ of_property_read_u32(dev-of_node, ti,pullups,
+ omap_twl_info-pullups);
+ of_property_read_u32(dev-of_node, ti,pulldowns,
+ omap_twl_info-pulldowns);
+
+ return omap_twl_info;
+}
+
static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
{
struct twl4030_gpio_platform_data *pdata = pdev-dev.platform_data;
@@ -423,39 +450,44 @@ static int __devinit gpio_twl4030_probe(struct
platform_device *pdev)
twl4030_gpio_irq_base = irq_base;
no_irqs:
- twl_gpiochip.base = -1;
twl_gpiochip.ngpio = TWL4030_GPIO_MAX;
twl_gpiochip.dev = pdev-dev;
- if (pdata) {
- twl_gpiochip.base = pdata-gpio_base;
+ if (node)
+ pdata = of_gpio_twl4030(pdev-dev);
- /*
- * NOTE: boards may waste power if they don't set pullups
- * and pulldowns correctly ... default for non-ULPI pins is
- * pulldown, and some other pins may have external pullups
- * or pulldowns. Careful!
- */
- ret = gpio_twl4030_pulls(pdata-pullups, pdata-pulldowns);
- if (ret)
- dev_dbg(pdev-dev, pullups %.05x %.05x -- %d\n,
- pdata-pullups, pdata-pulldowns,
- ret);
-
- ret = gpio_twl4030_debounce(pdata-debounce, pdata-mmc_cd);
- if (ret)
- dev_dbg(pdev-dev, debounce %.03x %.01x -- %d\n,
- pdata-debounce, pdata-mmc_cd,
- ret);
-
- /*
- * NOTE: we assume VIBRA_CTL.VIBRA_EN, in MODULE_AUDIO_VOICE,
- * is (still) clear if use_leds is set.
- */
- if (pdata-use_leds)
- twl_gpiochip.ngpio += 2;
+ if (pdata == NULL) {
+ dev_err(pdev-dev, Platform data is missing\n);
+ return -ENXIO;
}
+ twl_gpiochip.base = pdata-gpio_base;
+
+ /*
+ * NOTE: boards may waste power if they don't set pullups
+ * and pulldowns correctly ... default for non-ULPI pins is
+ * pulldown, and some other pins may have external pullups
+ * or pulldowns. Careful!
+ */
+ ret = gpio_twl4030_pulls(pdata-pullups, pdata-pulldowns);
+ if (ret)
+ dev_dbg(pdev-dev, pullups %.05x %.05x -- %d\n,
+ pdata-pullups, pdata-pulldowns,
+ ret);
+
+ ret = gpio_twl4030_debounce(pdata-debounce, pdata-mmc_cd);
+ if (ret)
+ dev_dbg(pdev-dev, debounce %.03x %.01x -- %d\n,
+ pdata-debounce, pdata-mmc_cd,
+ ret);
+
+ /*
+ * NOTE: we assume VIBRA_CTL.VIBRA_EN, in MODULE_AUDIO_VOICE,
+ * is (still) clear if use_leds is set.
+ */
+ if (pdata-use_leds)
+ twl_gpiochip.ngpio += 2;
+
ret = gpiochip_add(twl_gpiochip);
if (ret 0) {
dev_err(pdev-dev, could not register gpiochip, %d\n, ret);
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Re: [PATCH 2/3] gpio-twl4030: new dt properties for BeagleBoard and omap3-EVM
On 9/3/2012 7:24 PM, Florian Vaussard wrote:
Add device tree properties for twl4030/gpio, according to the
platform data of corresponding boards. This enables the led
connected to LEDB output for both boards, as well as
pullups/pulldowns on GPIO for the BeagleBoard.
Signed-off-by: Florian Vaussard florian.vauss...@epfl.ch
---
arch/arm/boot/dts/omap3-beagle.dts | 20
arch/arm/boot/dts/omap3-evm.dts| 13 +
2 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/omap3-beagle.dts
b/arch/arm/boot/dts/omap3-beagle.dts
index cdcb98c..16bff8b 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -17,6 +17,14 @@
device_type = memory;
reg = 0x8000 0x2000; /* 512 MB */
};
+
+ leds {
+ compatible = gpio-leds;
+ pmu_stat {
+ label = beagleboard::pmu_stat;
+ gpios = twl_gpio 19 0; /* LEDB */
+ };
+ };
};
i2c1 {
@@ -67,3 +75,15 @@
mmc3 {
status = disabled;
};
+
+twl_gpio {
+ ti,use-leds = true;
+ /* pullups: BIT(1) */
+ ti,pullups = 2;
+ /*
+ * pulldowns:
+ * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
+ * BIT(15), BIT(16), BIT(17)
+ */
+ ti,pulldowns = 238020;
Consider changing above value to hex presentation.
Otherwise looks ok to me, also I have tested it on OMAP3EVM.
Tested--Acked-By: Vaibhav Hiremath hvaib...@ti.com
Thanks,
Vaibhav
+};
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index f349ee9..f1e18fe 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -17,6 +17,15 @@
device_type = memory;
reg = 0x8000 0x1000; /* 256 MB */
};
+
+ leds {
+ compatible = gpio-leds;
+ ledb {
+ label = omap3evm::ledb;
+ gpios = twl_gpio 19 0; /* LEDB */
+ linux,default-trigger = default-on;
+ };
+ };
};
i2c1 {
@@ -46,3 +55,7 @@
reg = 0x5c;
};
};
+
+twl_gpio {
+ ti,use-leds = true;
+};
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Re: [PATCH 2/4] can: c_can: Add d_can raminit support
On 9/4/2012 11:44 AM, AnilKumar, Chimata wrote:
Hi Marc,
On Tue, Sep 04, 2012 at 02:09:15, Marc Kleine-Budde wrote:
On 09/03/2012 01:52 PM, AnilKumar Ch wrote:
Add D_CAN raminit support to C_CAN driver to enable D_CAN RAM.
DCAN RAM holds all the message objects during transmission or
receiving of data. This initialization/de-initialization should
be done in synchronous with D_CAN clock.
Signed-off-by: AnilKumar Ch anilku...@ti.com
---
drivers/net/can/c_can/c_can.c | 13
drivers/net/can/c_can/c_can.h |2 ++
drivers/net/can/c_can/c_can_platform.c | 10 +
include/linux/can/platform/c_can.h | 36
4 files changed, 61 insertions(+)
create mode 100644 include/linux/can/platform/c_can.h
diff --git a/drivers/net/can/c_can/c_can.c b/drivers/net/can/c_can/c_can.c
index aa6c5eb..c175410 100644
--- a/drivers/net/can/c_can/c_can.c
+++ b/drivers/net/can/c_can/c_can.c
@@ -214,6 +214,12 @@ static inline void c_can_pm_runtime_put_sync(const
struct c_can_priv *priv)
pm_runtime_put_sync(priv-device);
}
+static inline void c_can_reset_ram(const struct c_can_priv *priv, bool
enable)
+{
+ if (priv-ram_init)
+ priv-ram_init(priv-instance, enable);
+}
+
static inline int get_tx_next_msg_obj(const struct c_can_priv *priv)
{
return (priv-tx_next C_CAN_NEXT_MSG_OBJ_MASK) +
@@ -1071,6 +1077,8 @@ static int c_can_open(struct net_device *dev)
struct c_can_priv *priv = netdev_priv(dev);
c_can_pm_runtime_get_sync(priv);
+ /* Initialize DCAN RAM */
+ c_can_reset_ram(priv, true);
/* open the can device */
err = open_candev(dev);
@@ -1099,6 +1107,8 @@ static int c_can_open(struct net_device *dev)
exit_irq_fail:
close_candev(dev);
exit_open_fail:
+ /* De-Initialize DCAN RAM */
+ c_can_reset_ram(priv, false);
c_can_pm_runtime_put_sync(priv);
return err;
}
@@ -1112,6 +1122,9 @@ static int c_can_close(struct net_device *dev)
c_can_stop(dev);
free_irq(dev-irq, dev);
close_candev(dev);
+
+ /* De-Initialize DCAN RAM */
+ c_can_reset_ram(priv, false);
c_can_pm_runtime_put_sync(priv);
return 0;
diff --git a/drivers/net/can/c_can/c_can.h b/drivers/net/can/c_can/c_can.h
index 1437a6d..5f6339c 100644
--- a/drivers/net/can/c_can/c_can.h
+++ b/drivers/net/can/c_can/c_can.h
@@ -166,6 +166,8 @@ struct c_can_priv {
unsigned int tx_echo;
void *priv; /* for board-specific data */
u16 irqstatus;
+ unsigned int instance;
+ void (*ram_init) (unsigned int instance, bool enable);
};
struct net_device *alloc_c_can_dev(void);
diff --git a/drivers/net/can/c_can/c_can_platform.c
b/drivers/net/can/c_can/c_can_platform.c
index c351975..c6963b2 100644
--- a/drivers/net/can/c_can/c_can_platform.c
+++ b/drivers/net/can/c_can/c_can_platform.c
@@ -34,6 +34,7 @@
#include linux/of_device.h
#include linux/pm_runtime.h
#include linux/pinctrl/consumer.h
+#include linux/can/platform/c_can.h
#include linux/can/dev.h
@@ -98,6 +99,7 @@ static int __devinit c_can_plat_probe(struct
platform_device *pdev)
struct net_device *dev;
struct c_can_priv *priv;
const struct of_device_id *match;
+ struct c_can_platform_data *pdata = NULL;
const struct platform_device_id *id;
struct pinctrl *pinctrl;
struct resource *mem;
@@ -179,6 +181,14 @@ static int __devinit c_can_plat_probe(struct
platform_device *pdev)
priv-can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES;
priv-read_reg = c_can_plat_read_reg_aligned_to_16bit;
priv-write_reg = c_can_plat_write_reg_aligned_to_16bit;
+ pdata = pdev-dev.platform_data;
+ if (!pdata) {
+ dev_err(pdev-dev, d_can platform data missing\n);
+ ret = -EINVAL;
Is the ram_init mandatory on all d_can? There might be non omap d_can users.
As per AM335x specifications d_can module should have ram_init.
In that case it's better to print warning and break the switch.
As far as I know, ram_init is part of IP spec, how it is controlled
does varies based on SoC integration.
Thanks,
Vaibhav
Marc
+ goto exit_free_device;
+ }
+ priv-ram_init = pdata-ram_init;
+ priv-instance = pdata-instance;
break;
default:
ret = -EINVAL;
diff --git a/include/linux/can/platform/c_can.h
b/include/linux/can/platform/c_can.h
new file mode 100644
index 000..84b27d2
--- /dev/null
+++ b/include/linux/can/platform/c_can.h
@@ -0,0 +1,36 @@
+/*
+ * C_CAN controller driver platform header
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Bosch C_CAN/D_CAN controller is compliant to CAN protocol version 2.0
+ * part A and B.
+ *
+ * This program is free software; you can redistribute it and/or
+
Re: [PATCH v2 1/8] ARM/dts: OMAP2: Add McBSP entries for OMAP2420 and OMAP2430 SoC
On 9/3/2012 8:16 PM, Benoit Cousson wrote:
Hi Peter,
The overall series looks good to me, but I do have a couple of comments.
On 08/29/2012 03:31 PM, Peter Ujfalusi wrote:
The McBSP IP within OMAP2420 and 2430 is different we need to create separate
dtsi files for them.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/boot/dts/omap2420.dtsi | 39 ++
arch/arm/boot/dts/omap2430.dtsi | 83
+++
2 files changed, 122 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/omap2420.dtsi
create mode 100644 arch/arm/boot/dts/omap2430.dtsi
diff --git a/arch/arm/boot/dts/omap2420.dtsi
b/arch/arm/boot/dts/omap2420.dtsi
new file mode 100644
index 000..f375c68
--- /dev/null
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -0,0 +1,39 @@
+/*
+ * Device Tree Source for OMAP2420 SoC
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
Nit: 2012
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed as is without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ omap2.dtsi
+
+/ {
+compatible = ti,omap2420, ti,omap2;
+
+ocp {
+mcbsp1: mcbsp@48074000 {
+compatible = ti,omap2420-mcbsp;
+reg = 0x48074000 0xff;
+reg-names = mpu;
+interrupts = 0 59 0x4, /* TX interrupt */
+ 0 60 0x4; /* RX interrupt */
That one is not correct because it does comply with the interrupt
controller specifier that require only one cell:
intc: interrupt-controller@4820 {
compatible = ti,omap2-intc;
interrupt-controller;
#interrupt-cells = 1;
...
The one you are using is for GIC IRQ controller.
It works probably because we are using hwmod so far :-)
I think now we should kill the resource overwrite path, and should
respect and use resources passed from DT.
Benoit,
Did you get a chance to validate patch submitted towards this??
https://patchwork.kernel.org/patch/1384351/
Thanks,
Vaibhav
Didn't you get some warning?
In the case of OMAP2 3, it is much simpler:
+interrupts = 59, /* TX interrupt */
+ 60; /* RX interrupt */
That comment is applicable for OMAP2420, OMAP2430, and OMAP3 in general.
+interrupt-names = tx, rx;
+interrupt-parent = intc;
+ti,hwmods = mcbsp1;
+};
+
+mcbsp2: mcbsp@48076000 {
+compatible = ti,omap2420-mcbsp;
+reg = 0x48076000 0xff;
+reg-names = mpu;
+interrupts = 0 62 0x4, /* TX interrupt */
+ 0 63 0x4; /* RX interrupt */
+interrupt-names = tx, rx;
+interrupt-parent = intc;
+ti,hwmods = mcbsp2;
+};
+};
+};
diff --git a/arch/arm/boot/dts/omap2430.dtsi
b/arch/arm/boot/dts/omap2430.dtsi
new file mode 100644
index 000..531e346
--- /dev/null
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -0,0 +1,83 @@
+/*
+ * Device Tree Source for OMAP243x SoC
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
2012.
Regards,
Benoit
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Re: [PATCH RESEND v4 1/3] arm/dts: AM33XX: Add basic pinctrl device tree data
On 8/31/2012 2:02 AM, Tony Lindgren wrote:
* AnilKumar Ch anilku...@ti.com [120828 01:11]:
Adds basic pinctrl device tree data for AM33XX family of devices.
This patch is based on the pinctrl-single driver.
Signed-off-by: AnilKumar Ch anilku...@ti.com
---
arch/arm/boot/dts/am33xx.dtsi |9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index dde76f7..dfe9c559 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -40,6 +40,15 @@
};
};
+am3358_pinmux: pinmux@44E10800 {
+compatible = pinctrl-single;
+reg = 0x44E10800 0x0238;
+#address-cells = 1;
+#size-cells = 0;
+pinctrl-single,register-width = 32;
+pinctrl-single,function-mask = 0x7F;
+};
+
Nit: Please use lower case for the hex numbers as that's the
standard in Linux kernel.
Tony,
I could see that you have already merged the patch from Anil for
regulator support in bone evm dts file, which has uppper-case hex numbers.
Request you to merge the patch which I submitted to convert all hex
numbers to lower-case and then merge all dts changes only with
lower-case presentation.
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg74393.html
Thanks,
Vaibhav
Tony
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Without MACH_ option Early printk (DEBUG_LL)
Hi Russell Tony, AM335X EVM (based on AM33XX device) only supports DT boot mode and doesn't have CONFIG_MACH_AM335XEVM option defined. Some time back during baseport submission we had aligned that, we won't create separate EVM options, killing the board file all-together. Having said that, the early printk option (DEBUG_LL) is broken, the auto-generated file ./include/generated/mach-types.h still refers to CONFIG_MACH_AM335XEVM option, #ifdef CONFIG_MACH_AM335XEVM # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else # define machine_arch_type MACH_TYPE_AM335XEVM # endif # define machine_is_am335xevm() (machine_arch_type == MACH_TYPE_AM335XEVM) #else # define machine_is_am335xevm() (0) #endif So I am thinking of changing the config_xxx option to SOC_AM33XX or ARCH_OMAP2PLUS, something like below, am335xevmSOC_AM33XX AM335XEVM 3589 OR am335xevmARCH_OMAP2PLUS AM335XEVM 3589 Can you comment on this? Based on that I will submit the patch. Thanks, Vaibhav -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: OMAP2+: Makefile.boot: Add am335x evm and bone targets
This adds am335x-evm and am335x-bone dtb targets to 'make dtbs', just like other platforms. Signed-off-by: Vaibhav Hiremath hvaib...@ti.com Cc: Tony Lindgren t...@atomide.com --- arch/arm/mach-omap2/Makefile.boot |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/Makefile.boot b/arch/arm/mach-omap2/Makefile.boot index 6cf1c2d..1136072 100644 --- a/arch/arm/mach-omap2/Makefile.boot +++ b/arch/arm/mach-omap2/Makefile.boot @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_OMAP3)+= omap3-beagle.dtb omap3-evm.dtb dtb-$(CONFIG_ARCH_OMAP4) += omap4-panda.dtb omap4-pandaES.dtb dtb-$(CONFIG_ARCH_OMAP4) += omap4-var_som.dtb omap4-sdp.dtb dtb-$(CONFIG_SOC_OMAP5)+= omap5-evm.dtb +dtb-$(CONFIG_SOC_AM33XX) += am335x-evm.dtb am335x-bone.dtb -- 1.7.0.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 0/3] Prepare for OMAP2+ movement to Common Clk
On 8/31/2012 2:26 AM, Paul Walmsley wrote: Hi Rajendra On Wed, 29 Aug 2012, Rajendra Nayak wrote: Changes in v4: * Added *hack* comments around clk_prepare usage in hwmod rebased on 3.6-rc Assuming this is so (haven't looked closely at this series yet), and after the existing comments are taken into consideration and a new version reposted, will queue this series for 3.7. Care to respin your series that converts the data also, on top of your new version of this series? We should try to get that into 3.7 also. BTW are you still waiting for something from Vaibhav Hiremath for this? Or can the scripts convert the existing clock33xx_data.c also? I believe I have already shared all the patches with Rajendra, so please let me know if anything is pending on me. Thanks, Vaibhav - Paul ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH] ARM: OMAP2+: omap-device: Do not overwrite resources allocated by OF layer
With the new devices (like, AM33XX and OMAP5) we now only support
DT boot mode of operation and now it is the time to start killing
slowly the dependency on hwmod, so with this patch, we are starting
with device resources.
The idea here is implemented considering to both boot modes -
- DT boot mode
OF framework will construct the resource structure (currently
does for MEM IRQ resource) and we should respect/use these
resources, killing hwmod dependency.
If pdev-num_resources 0, we assume that MEM IRQ resources
have been allocated by OF layer already (through DTB).
Once DMA resource is available from OF layer, we should
kill filling any resources from hwmod.
- Non-DT boot mode
Here, pdev-num_resources = 0, and we should get all the
resources from hwmod (following existing steps)
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Kevin Hilman khil...@ti.com
---
This patch is tested on BeagleBone and AM37xEVM.
Why RFC?
Still we have function duplication omap_device_fill_resources() and
omap_device_fill_dma_resources(), we can actually split the function
into 3 resources and avoid duplication -
- omap_device_fill_dma_resources()
- omap_device_fill_mem_resources()
- omap_device_fill_irq_resources()
Actually I wanted to clean it further but thought of getting
feedback first and then proceed further.
arch/arm/mach-omap2/omap_hwmod.c | 27 ++
arch/arm/plat-omap/include/plat/omap_hwmod.h |1 +
arch/arm/plat-omap/omap_device.c | 72 +
3 files changed, 88 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 31ec283..edabfb3 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -3330,6 +3330,33 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh,
struct resource *res)
}
/**
+ * omap_hwmod_fill_dma_resources - fill struct resource array with dma data
+ * @oh: struct omap_hwmod *
+ * @res: pointer to the array of struct resource to fill
+ *
+ * Fill the struct resource array @res with dma resource data from the
+ * omap_hwmod @oh. Intended to be called by code that registers
+ * omap_devices. See also omap_hwmod_count_resources(). Returns the
+ * number of array elements filled.
+ */
+int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res)
+{
+ int i, sdma_reqs_cnt;
+ int r = 0;
+
+ sdma_reqs_cnt = _count_sdma_reqs(oh);
+ for (i = 0; i sdma_reqs_cnt; i++) {
+ (res + r)-name = (oh-sdma_reqs + i)-name;
+ (res + r)-start = (oh-sdma_reqs + i)-dma_req;
+ (res + r)-end = (oh-sdma_reqs + i)-dma_req;
+ (res + r)-flags = IORESOURCE_DMA;
+ r++;
+ }
+
+ return r;
+}
+
+/**
* omap_hwmod_get_resource_byname - fetch IP block integration data by name
* @oh: struct omap_hwmod * to operate on
* @type: one of the IORESOURCE_* constants from include/linux/ioport.h
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h
b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 9b9646c..0533073 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -615,6 +615,7 @@ int omap_hwmod_softreset(struct omap_hwmod *oh);
int omap_hwmod_count_resources(struct omap_hwmod *oh);
int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
+int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res);
int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
const char *name, struct resource *res);
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index c490240..fd15a3a 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -486,6 +486,33 @@ static int omap_device_fill_resources(struct omap_device
*od,
}
/**
+ * omap_device_fill_dma_resources - fill in array of struct resource with dma
resources
+ * @od: struct omap_device *
+ * @res: pointer to an array of struct resource to be filled in
+ *
+ * Populate one or more empty struct resource pointed to by @res with
+ * the dma resource data for this omap_device @od. Used by
+ * omap_device_alloc() after calling omap_device_count_resources().
+ *
+ * Ideally this function would not be needed at all. If we have
+ * mechanism to get dma resources from DT.
+ *
+ * Returns 0.
+ */
+static int omap_device_fill_dma_resources(struct omap_device *od,
+ struct resource *res)
+{
+ int i, r;
+
+ for (i = 0; i od-hwmods_cnt; i++) {
+ r = omap_hwmod_fill_dma_resources(od-hwmods[i], res);
+ res += r;
+ }
+
+ return 0;
+}
+
+/**
* omap_device_alloc
Re: [PATCH v3 3/4] arm/dts: AM33XX: Configure pinmuxs for D_CAN1 on AM335x-EVM
On 8/25/2012 1:44 AM, Tony Lindgren wrote:
* AnilKumar Ch anilku...@ti.com [120816 05:20]:
Add D_CAN1 pinctrl node to am3358_pinmux master node to export
D_CAN functionality on AM335x EVM according to pinctrl-single
driver.
Signed-off-by: AnilKumar Ch anilku...@ti.com
---
Changes from v2:
- Incorporated Vaibhav H's comments on v2
* Added dcan0 instances to am33xx.dtsi file
Changes from v1:
- These two patches separated from c_can DT support
patch series.
arch/arm/boot/dts/am335x-evm.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evm.dts
b/arch/arm/boot/dts/am335x-evm.dts
index 5dd8a6b..a64c30a 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -18,6 +18,18 @@
reg = 0x8000 0x1000; /* 256 MB */
};
+am3358_pinmux: pinmux@44E10800 {
This should be just am3358_pinmux as you already include it.
I think it won't work this way, it will result into syntax error.
The reason being is, unlike OMAP (and like other platforms, like, imx)
here we are again representing device hierarchy starting from root,
am335x-evm.dts:
/ {
ocp {
...
};
};
Although I am not too familiar with DTS compiler, but below code results
in syntax error:
am335x-evm.dts:
/ {
ocp {
...
am3358_pinmux {
...
};
};
};
Thanks,
Vaibhav
+pinctrl-names = default;
+pinctrl-0 = d_can1_pins;
+
+d_can1_pins: pinmux_d_can_pins {
+pinctrl-single,pins =
+0x168 0x2 /* uart0_ctsn.d_can1_tx, OUTPUT
| MODE2 */
+0x16C 0x32 /* uart0_rtsn.d_can1_rx,
INPUT_PULLUP | MODE2 */
+;
+};
+};
+
It would better to claim these pins in the dcan driver entry
rather than set them as pins enabled by the pinctrl driver.
The reason is that in case you want to enable runtime PM related
stuff, like some more advanced wake-up features, for the rx pin
you can do it in the driver.
Then one nit.. Please lowercase all hex number in this series as that's the
style
here.
Regards,
Tony
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Re: [PATCH] ARM: OMAP2+: am33xx: Fix the timer fck clock naming convention
On 7/17/2012 10:14 AM, Hiremath, Vaibhav wrote: On Tue, Jul 17, 2012 at 05:24:39, Paul Walmsley wrote: On Mon, 16 Jul 2012, Vaibhav Hiremath wrote: With commit ae6df418a21f3a361c5f9b878e32a8aba4e17692 Sub: ARM: OMAP2+: dmtimer: cleanup fclk usage) The Timer functional clock naming convention has changed from gptX_fck = timerXfck, and so as the timer init function in mach-omap2/timer.c. OMAP4 clocktree also has changed accordingly. AM33xx Clock Tree has been merged during rc3-4 timeframe, before above commit got merged, so similar change is required for AM33xx as well (Change the gptX_fck = timerX_fck). Signed-off-by: Vaibhav Hiremath hvaib...@ti.com Thanks, this looks like 3.6-rc material, right? Yes, that's correct. Tony/Paul, Ping !!! Thanks, Vaibhav Thanks, Vaibhav -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: AM33XX: clock: Add dcan clock aliases for device-tree
Currently, the device names for the dcan module follows the
format dcan.X, where 'X' is the dcan instance number.
On other side, driver may request for clock with/without con_id
and dev_id, and it is expected that platform should respect this
request and return the requested clock handle.
Now, when using device tree, the format of the device name created
by OF layer is different, reg-address.device-name,
assuming that the device-tree reg property is specified.
This causes the look-up failure for clock node in dcan driver
To fix this add new dcan clock alias for using device-tree.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Grant Likely grant.lik...@secretlab.ca
Cc: Rob Herring robherri...@gmail.com
---
arch/arm/mach-omap2/clock33xx_data.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock33xx_data.c
b/arch/arm/mach-omap2/clock33xx_data.c
index ae27de8..a4006b2 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -1027,7 +1027,9 @@ static struct omap_clk am33xx_clks[] = {
CLK(NULL, cefuse_fck, cefuse_fck,CK_AM33XX),
CLK(NULL, clkdiv32k_ick,clkdiv32k_ick, CK_AM33XX),
CLK(NULL, dcan0_fck,dcan0_fck, CK_AM33XX),
+ CLK(481cc000.d_can, NULL, dcan0_fck, CK_AM33XX),
CLK(NULL, dcan1_fck,dcan1_fck, CK_AM33XX),
+ CLK(481d.d_can, NULL, dcan1_fck, CK_AM33XX),
CLK(NULL, debugss_ick, debugss_ick, CK_AM33XX),
CLK(NULL, pruss_ocp_gclk, pruss_ocp_gclk,
CK_AM33XX),
CLK(davinci-mcasp.0, NULL, mcasp0_fck,CK_AM33XX),
--
1.7.0.4
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[PATCH 0/2] arm/dts: AM33XX: Add reg and interrupt property for all nodes
This series is trivial patch-series and should be considered as preparation for the future where we supposed to get rid of hwmod dependency. 1/2: Converts all hex numbers to lowercase, fixing inconsistency 2/2: Add reg and interrupt property to all device/module nodes inside DTS files. Although currently hwmod overwrites resources, I have validated this patch series by changing the omap_device layer to respect DT resources and boot Tested on BeagleBone platform. I will be submitting the changes for omap_device layer as well, still needs to fix on certain things. Vaibhav Hiremath (2): arm/dts: AM33XX: Convert all hex numbers to lower-case arm/dts: AM33XX: Specify reg and interrupt property for all nodes arch/arm/boot/dts/am335x-bone.dts |2 +- arch/arm/boot/dts/am335x-evm.dts |2 +- arch/arm/boot/dts/am33xx.dtsi | 62 +++-- 3 files changed, 54 insertions(+), 12 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] arm/dts: AM33XX: Convert all hex numbers to lower-case
To make it consistent, convert all hex number presentation
to lower-case from all am33xx specific nodes.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Tony Lindgren t...@atomide.com
---
arch/arm/boot/dts/am335x-bone.dts |2 +-
arch/arm/boot/dts/am335x-evm.dts |2 +-
arch/arm/boot/dts/am33xx.dtsi | 20 ++--
3 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index a7906cb..c64f7fa 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -19,7 +19,7 @@
};
ocp {
- uart1: serial@44E09000 {
+ uart1: serial@44e09000 {
status = okay;
};
};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 5dd8a6b..8963f20 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -19,7 +19,7 @@
};
ocp {
- uart1: serial@44E09000 {
+ uart1: serial@44e09000 {
status = okay;
};
};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index dde76f7..be43511 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -71,7 +71,7 @@
#interrupt-cells = 1;
};
- gpio2: gpio@4804C000 {
+ gpio2: gpio@4804c000 {
compatible = ti,omap4-gpio;
ti,hwmods = gpio2;
gpio-controller;
@@ -80,7 +80,7 @@
#interrupt-cells = 1;
};
- gpio3: gpio@481AC000 {
+ gpio3: gpio@481ac000 {
compatible = ti,omap4-gpio;
ti,hwmods = gpio3;
gpio-controller;
@@ -89,7 +89,7 @@
#interrupt-cells = 1;
};
- gpio4: gpio@481AE000 {
+ gpio4: gpio@481ae000 {
compatible = ti,omap4-gpio;
ti,hwmods = gpio4;
gpio-controller;
@@ -98,7 +98,7 @@
#interrupt-cells = 1;
};
- uart1: serial@44E09000 {
+ uart1: serial@44e09000 {
compatible = ti,omap3-uart;
ti,hwmods = uart1;
clock-frequency = 4800;
@@ -119,28 +119,28 @@
status = disabled;
};
- uart4: serial@481A6000 {
+ uart4: serial@481a6000 {
compatible = ti,omap3-uart;
ti,hwmods = uart4;
clock-frequency = 4800;
status = disabled;
};
- uart5: serial@481A8000 {
+ uart5: serial@481a8000 {
compatible = ti,omap3-uart;
ti,hwmods = uart5;
clock-frequency = 4800;
status = disabled;
};
- uart6: serial@481AA000 {
+ uart6: serial@481aa000 {
compatible = ti,omap3-uart;
ti,hwmods = uart6;
clock-frequency = 4800;
status = disabled;
};
- i2c1: i2c@44E0B000 {
+ i2c1: i2c@44e0b000 {
compatible = ti,omap4-i2c;
#address-cells = 1;
#size-cells = 0;
@@ -148,7 +148,7 @@
status = disabled;
};
- i2c2: i2c@4802A000 {
+ i2c2: i2c@4802a000 {
compatible = ti,omap4-i2c;
#address-cells = 1;
#size-cells = 0;
@@ -156,7 +156,7 @@
status = disabled;
};
- i2c3: i2c@4819C000 {
+ i2c3: i2c@4819c000 {
compatible = ti,omap4-i2c;
#address-cells = 1;
#size-cells = 0;
--
1.7.0.4
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[PATCH 2/2] arm/dts: AM33XX: Specify reg and interrupt property for all nodes
The device/node resources (like, IORESOURCE_MEM and IORESOURCE_IRQ)
are overwritten by hwmod resources, due to all known reasons but
that should not be the reason for not providing all the information
in the DTS blob. Ideally we should use DTS resource and use HWMOD
framework wherever required and for only specific things.
Newer platforms like, OMAP5 and AM33XX, we only support DT boot mode,
so this patch is preparation for the future where we supposed to get
rid of hwmod dependency anyway.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Benoit Cousson b-cous...@ti.com
---
arch/arm/boot/dts/am33xx.dtsi | 42 +
1 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index be43511..f0642e1 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -69,6 +69,9 @@
#gpio-cells = 2;
interrupt-controller;
#interrupt-cells = 1;
+ reg = 0x44e07000 0x1000;
+ interrupt-parent = intc;
+ interrupts = 96;
};
gpio2: gpio@4804c000 {
@@ -78,6 +81,9 @@
#gpio-cells = 2;
interrupt-controller;
#interrupt-cells = 1;
+ reg = 0x4804c000 0x1000;
+ interrupt-parent = intc;
+ interrupts = 98;
};
gpio3: gpio@481ac000 {
@@ -87,6 +93,9 @@
#gpio-cells = 2;
interrupt-controller;
#interrupt-cells = 1;
+ reg = 0x481ac000 0x1000;
+ interrupt-parent = intc;
+ interrupts = 32;
};
gpio4: gpio@481ae000 {
@@ -96,12 +105,18 @@
#gpio-cells = 2;
interrupt-controller;
#interrupt-cells = 1;
+ reg = 0x481ae000 0x1000;
+ interrupt-parent = intc;
+ interrupts = 62;
};
uart1: serial@44e09000 {
compatible = ti,omap3-uart;
ti,hwmods = uart1;
clock-frequency = 4800;
+ reg = 0x44e09000 0x2000;
+ interrupt-parent = intc;
+ interrupts = 72;
status = disabled;
};
@@ -109,6 +124,9 @@
compatible = ti,omap3-uart;
ti,hwmods = uart2;
clock-frequency = 4800;
+ reg = 0x48022000 0x2000;
+ interrupt-parent = intc;
+ interrupts = 73;
status = disabled;
};
@@ -116,6 +134,9 @@
compatible = ti,omap3-uart;
ti,hwmods = uart3;
clock-frequency = 4800;
+ reg = 0x48024000 0x2000;
+ interrupt-parent = intc;
+ interrupts = 74;
status = disabled;
};
@@ -123,6 +144,9 @@
compatible = ti,omap3-uart;
ti,hwmods = uart4;
clock-frequency = 4800;
+ reg = 0x481a6000 0x2000;
+ interrupt-parent = intc;
+ interrupts = 44;
status = disabled;
};
@@ -130,6 +154,9 @@
compatible = ti,omap3-uart;
ti,hwmods = uart5;
clock-frequency = 4800;
+ reg = 0x481a8000 0x2000;
+ interrupt-parent = intc;
+ interrupts = 45;
status = disabled;
};
@@ -137,6 +164,9 @@
compatible = ti,omap3-uart;
ti,hwmods = uart6;
clock-frequency = 4800;
+ reg = 0x481aa000 0x2000;
+ interrupt-parent = intc;
+ interrupts = 46;
status = disabled;
};
@@ -145,6 +175,9 @@
#address-cells = 1;
#size-cells = 0;
ti,hwmods = i2c1;
+ reg = 0x44e0b000 0x1000;
+ interrupt-parent = intc;
+ interrupts = 70;
status = disabled;
};
@@ -153,6 +186,9 @@
#address-cells = 1;
#size-cells = 0
[PATCH] ARM: OMAP2+: dpll: Add missing soc_is_am33xx() check for common functions
Add missing soc_is_am33xx() check for DPLL common control clock
related functions, without this dpll programmability would be broken
for am33xx family of devices.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Paul Walmsley p...@pwsan.com
---
Not sure whether this should go as a fix in -rc, as AM33XX device
doesn't still boot without hwmod data (which is not yet upstream).
arch/arm/mach-omap2/clkt_dpll.c |4 ++--
arch/arm/mach-omap2/dpll3xxx.c |4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index cd7fd0f..05ff99e 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -211,7 +211,7 @@ void omap2_init_dpll_parent(struct clk *clk)
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
clk_reparent(clk, dd-clk_bypass);
- } else if (cpu_is_omap44xx()) {
+ } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
@@ -257,7 +257,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
return dd-clk_bypass-rate;
- } else if (cpu_is_omap44xx()) {
+ } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index b9c8d2f..063e1f9 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -311,7 +311,7 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16
m, u8 n, u16 freqsel)
* Set jitter correction. No jitter correction for OMAP4 and 3630
* since freqsel field is no longer present
*/
- if (!cpu_is_omap44xx() !cpu_is_omap3630()) {
+ if (!soc_is_am33xx() !cpu_is_omap44xx() !cpu_is_omap3630()) {
v = __raw_readl(dd-control_reg);
v = ~dd-freqsel_mask;
v |= freqsel __ffs(dd-freqsel_mask);
@@ -471,7 +471,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned
long rate)
return -EINVAL;
/* No freqsel on OMAP4 and OMAP3630 */
- if (!cpu_is_omap44xx() !cpu_is_omap3630()) {
+ if (!soc_is_am33xx() !cpu_is_omap44xx()
!cpu_is_omap3630()) {
freqsel = _omap3_dpll_compute_freqsel(clk,
dd-last_rounded_n);
if (!freqsel)
--
1.7.0.4
--
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Re: OMAP HWMOD: Query regarding parent-child support
On 7/16/2012 7:41 PM, Vaibhav Hiremath wrote: Hi All, Paul, From last couple of days I am almost spending my whole time trying to get to somewhere on below issue and based on my understanding and learning so far I started feeling that, probably we might have made wrong decision to remove all leaf-nodes from the clock-tree. Instead we should have it removed from hwmod. :) Let's take a example of PWM Module (which is the context of my debugging) - As I mentioned before, PWM module present in AM33XX looks something like - -- | | | | PWMSS | | | | | --- - | | | eCAP | | ePWM | | eQEP | | | --- - | -- PWMSS: This actually controls all PM related signals like idle, standby, etc... eCAP/ePWM/eQEP: Technically it is independent module, reused from Davinci devices and is implemented as independent drivers in kernel. In case of AM33xx, the basic resources like, clock, idle signal and standby signal are abstracted at PWMSS level. This means the core IP (eCAP/ePWM/eQEP) have not changed from their original implementation. These core IP's (eCAP/ePWM/eQEP) are being used in Davinci family of devices, but without encapsulation of PWMSS, unlike AM33XX. This means, each module has its own clock enable/disable control mechanism and there is no dependency between them, unlike AM33XX. Options to support: 1. Use existing Clock Framework infrastructure to handle, which basically supports clock enable/disable function based on usecount and parent-child relation. Driver will simply work, without knowing anything about underneath platform, which is what expected. So create a dummy-clocks for submodules, making PWMSS clock as a parent will solve the issue here. And nothing wrong here, we are just treating, clock-enable = module-enable The only issue here is sysconf register access at hwmod level, if you leave sysconf idle and standby configuration at smart state, it works properly. I have validated it at my end. 2. MFD Driver: I think it will be miss-use of MFD driver and should be explored at all. I certainly vote for option-1. Paul, if you agree with me, I will submit the patch for option-1. NOTE: Same thing is applicable for CPSW driver, where two independent drivers (MDIO and CPSW) share common clock and needs similar fix. Thanks, Vaibhav During migration to run-time PM we came across unique (I believe) issue with respect to CPSW driver and eHRPWM. I am looking for pointers to handle these use-cases, as I am still going through the code and trying to understand myself on how can we handle this. CPSW: = CPSW Subsystem is built with 5 sub-modules, - CPSW SS (BaseAddr@0x4A10, rst@0x8) - MDIO (BaseAddr@0x4A101000) - CPSW WR (0x4A101200, rst@0x4) - CPSW SL1 (0x4A100D80, rst@0xc) - CPSW SL2 (0x4A100DC0, rst@0xc) - CPSW CPDMA (0x4A100800, rst@0x1c) Issue1: --- IP's are reused from legacy devices, for example, we have 2 separate platform driver for MDIO and cpsw, used between Davinci and AM335x. Everything is controlled through one MODULEMODE register in PRCM. So now we have 2 different modules accessing same resources (CLKCTRL.MODULEMODE), it is tricky to handle this usecase. Earlier with clock api's, it was easy, since clock framework used to handle ref_count for this and was sufficient here but with migration to runtime PM, we no longer use clk api's. Option1: It must be handled at driver level, and there will be handshaking between both the drivers. Which might impact legacy devices. Option2: It must be handled at SoC level, and parent and child creation is required here. parent-child creation is possible with platform device, but not sure about how it can be integrated with omap_device and hwmod. I am reading code and trying to understand how can this be handled? what is right place to create this parent-child relation? Issue2: --- Due to one of the HW bug, we have assert ocp-reset 4 sub-modules of CPSW before disabling clock/module (MODULEMODE=0) everytime. So for example, in every suspend-resume code before disabling the module, we have to assert ocp-reset and then disable the module. Also, please note that, the MDIO driver is separate and independent and requires clock to access sysconf register. We can have hwmod_class-reset function here, but the reset offset is different for every module, which makes it even difficult to handle. So if we have parent-child relation at some level, Where, we can register custom reset function to handle this scenario is required
