Re: [PATCHv5 27/35] ARM: dts: am33xx: add minimal l4 bus layout with control module support
On 03/21/2015 01:30 AM, Tony Lindgren wrote:
* Suman Anna s-a...@ti.com [150320 16:24]:
On 03/20/2015 05:35 PM, Tony Lindgren wrote:
* Suman Anna s-a...@ti.com [150320 14:44]:
On 03/20/2015 01:44 PM, Kristo, Tero wrote:
+ scm: scm@21 {
+ compatible = ti,am3-scm, simple-bus;
+ reg = 0x21 0x2000;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x21 0x2000;
+
+ am33xx_pinmux: pinmux@800 {
+ compatible = pinctrl-single;
+ reg = 0x800 0x238;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-single,register-width = 32;
+ pinctrl-single,function-mask = 0x7f;
+ };
+
+ scm_conf: scm_conf@0 {
+ compatible = syscon;
+ reg = 0x0 0x7fc;
Hmm, you are consolidating the am33xx_control_module and cm nodes, so is
this supposed to be 0x800 or 0x7fc? I would think it should be 0x800.
Seems correct to me, it's offset 0, size 0x7fc. So that's the scm_conf
syscon area before pinctrl-single at 0x44c0 + 0x21 + 0.
The io area for pinctrl-single starts at 0x800, so the scm_conf should
be before it in the dts file.
Well, I understand that it is how it was before, but we won't be mapping
or covering the last register efuse_sma before the pinctrl cfg
registers. Any reason for just leaving out that register?
Oh I see yeah that looks like a bug to me.
Tony
Updated this patch in my branch now to make scm_conf area be size 0x800.
-Tero
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Re: [PATCHv5 27/35] ARM: dts: am33xx: add minimal l4 bus layout with control module support
On 03/21/2015 01:30 AM, Tony Lindgren wrote:
* Suman Anna s-a...@ti.com [150320 16:24]:
On 03/20/2015 05:35 PM, Tony Lindgren wrote:
* Suman Anna s-a...@ti.com [150320 14:44]:
On 03/20/2015 01:44 PM, Kristo, Tero wrote:
+ scm: scm@21 {
+ compatible = ti,am3-scm, simple-bus;
+ reg = 0x21 0x2000;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x21 0x2000;
+
+ am33xx_pinmux: pinmux@800 {
+ compatible = pinctrl-single;
+ reg = 0x800 0x238;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-single,register-width = 32;
+ pinctrl-single,function-mask = 0x7f;
+ };
+
+ scm_conf: scm_conf@0 {
+ compatible = syscon;
+ reg = 0x0 0x7fc;
Hmm, you are consolidating the am33xx_control_module and cm nodes, so is
this supposed to be 0x800 or 0x7fc? I would think it should be 0x800.
Seems correct to me, it's offset 0, size 0x7fc. So that's the scm_conf
syscon area before pinctrl-single at 0x44c0 + 0x21 + 0.
The io area for pinctrl-single starts at 0x800, so the scm_conf should
be before it in the dts file.
Well, I understand that it is how it was before, but we won't be mapping
or covering the last register efuse_sma before the pinctrl cfg
registers. Any reason for just leaving out that register?
Oh I see yeah that looks like a bug to me.
Yea thats a bug, I wonder where I got this 7fc. Same issue exists for
am43xx also. I can fix this locally in my branch if that is fine.
-Tero
Tony
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Re: [PATCHv5 27/35] ARM: dts: am33xx: add minimal l4 bus layout with control module support
* Suman Anna s-a...@ti.com [150320 16:24]:
On 03/20/2015 05:35 PM, Tony Lindgren wrote:
* Suman Anna s-a...@ti.com [150320 14:44]:
On 03/20/2015 01:44 PM, Kristo, Tero wrote:
+ scm: scm@21 {
+ compatible = ti,am3-scm, simple-bus;
+ reg = 0x21 0x2000;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x21 0x2000;
+
+ am33xx_pinmux: pinmux@800 {
+ compatible = pinctrl-single;
+ reg = 0x800 0x238;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-single,register-width = 32;
+ pinctrl-single,function-mask = 0x7f;
+ };
+
+ scm_conf: scm_conf@0 {
+ compatible = syscon;
+ reg = 0x0 0x7fc;
Hmm, you are consolidating the am33xx_control_module and cm nodes, so is
this supposed to be 0x800 or 0x7fc? I would think it should be 0x800.
Seems correct to me, it's offset 0, size 0x7fc. So that's the scm_conf
syscon area before pinctrl-single at 0x44c0 + 0x21 + 0.
The io area for pinctrl-single starts at 0x800, so the scm_conf should
be before it in the dts file.
Well, I understand that it is how it was before, but we won't be mapping
or covering the last register efuse_sma before the pinctrl cfg
registers. Any reason for just leaving out that register?
Oh I see yeah that looks like a bug to me.
Tony
--
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the body of a message to majord...@vger.kernel.org
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Re: [PATCHv5 27/35] ARM: dts: am33xx: add minimal l4 bus layout with control module support
On 03/20/2015 05:35 PM, Tony Lindgren wrote:
* Suman Anna s-a...@ti.com [150320 14:44]:
On 03/20/2015 01:44 PM, Kristo, Tero wrote:
+ scm: scm@21 {
+ compatible = ti,am3-scm, simple-bus;
+ reg = 0x21 0x2000;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x21 0x2000;
+
+ am33xx_pinmux: pinmux@800 {
+ compatible = pinctrl-single;
+ reg = 0x800 0x238;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-single,register-width = 32;
+ pinctrl-single,function-mask = 0x7f;
+ };
+
+ scm_conf: scm_conf@0 {
+ compatible = syscon;
+ reg = 0x0 0x7fc;
Hmm, you are consolidating the am33xx_control_module and cm nodes, so is
this supposed to be 0x800 or 0x7fc? I would think it should be 0x800.
Seems correct to me, it's offset 0, size 0x7fc. So that's the scm_conf
syscon area before pinctrl-single at 0x44c0 + 0x21 + 0.
The io area for pinctrl-single starts at 0x800, so the scm_conf should
be before it in the dts file.
Well, I understand that it is how it was before, but we won't be mapping
or covering the last register efuse_sma before the pinctrl cfg
registers. Any reason for just leaving out that register?
regards
Suman
Also, are we ordering the child nodes of scm by node names or addresses.
I have to add the wkup_m3 node, and prefer ordering by addresses.
Yeah address ordering makes most sense here IMO.
Note that you should follow the TRM Table 2-2. L4_WKUP Peripheral Memory
Map and set up things as separate devices as shown there. Pretty much
each row in that table is a separate device on the interconnect. That's
especially true if the device has registers like revision, sysc, syss
and so on. In that case they can be clocked and idled separately.
So with these changes we follow the hardware mapping, although only
partially have it populated now for l4_wkup:
l3 (ocp) +- l4_per +- ...
| |- ...
|
+- l4_wkup +- prcm
| |- scm
| |- ...
|
+- ... +- ...
Regards,
Tony
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[PATCHv5 27/35] ARM: dts: am33xx: add minimal l4 bus layout with control module support
This patch creates an l4_wkup interconnect for AM33xx, and moves some of
the generic peripherals under it. System control module nodes are moved
under this new interconnect also, and the SCM clock layout is changed
to use the renamed SCM node as the clock provider.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
Documentation/devicetree/bindings/arm/omap/l4.txt |1 +
.../devicetree/bindings/arm/omap/prcm.txt |2 +-
arch/arm/boot/dts/am33xx-clocks.dtsi |2 +-
arch/arm/boot/dts/am33xx.dtsi | 87 +++-
arch/arm/mach-omap2/control.c |2 +-
5 files changed, 51 insertions(+), 43 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt
b/Documentation/devicetree/bindings/arm/omap/l4.txt
index 6402022..d333f0a 100644
--- a/Documentation/devicetree/bindings/arm/omap/l4.txt
+++ b/Documentation/devicetree/bindings/arm/omap/l4.txt
@@ -6,6 +6,7 @@ Required properties:
- compatible : Should be ti,omap2-l4 for OMAP2 family l4 core bus
Should be ti,omap2-l4-wkup for OMAP2 family l4 wkup bus
Should be ti,omap3-l4-core for OMAP3 family l4 core bus
+ Should be ti,am3-l4-wkup for AM33xx family l4 wkup bus
- ranges : contains the IO map range for the bus
Examples:
diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt
b/Documentation/devicetree/bindings/arm/omap/prcm.txt
index ef5a74b..c8e2027 100644
--- a/Documentation/devicetree/bindings/arm/omap/prcm.txt
+++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt
@@ -10,7 +10,7 @@ documentation about the individual clock/clockdomain nodes.
Required properties:
- compatible: Must be one of:
ti,am3-prcm
- ti,am3-scrm
+ ti,am3-scm
ti,am4-prcm
ti,am4-scrm
ti,omap2-prcm
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi
b/arch/arm/boot/dts/am33xx-clocks.dtsi
index 712edce..236c78a 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -7,7 +7,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-scrm_clocks {
+scm_clocks {
sys_clkin_ck: sys_clkin_ck {
#clock-cells = 0;
compatible = ti,mux-clock;
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index acd3705..8d26261 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -83,20 +83,6 @@
};
};
- am33xx_control_module: control_module@4a002000 {
- compatible = syscon;
- reg = 0x44e1 0x7fc;
- };
-
- am33xx_pinmux: pinmux@44e10800 {
- compatible = pinctrl-single;
- reg = 0x44e10800 0x0238;
- #address-cells = 1;
- #size-cells = 0;
- pinctrl-single,register-width = 32;
- pinctrl-single,function-mask = 0x7f;
- };
-
/*
* XXX: Use a flat representation of the AM33XX interconnect.
* The real AM33XX interconnect network is quite complex. Since
@@ -111,37 +97,58 @@
ranges;
ti,hwmods = l3_main;
- prcm: prcm@44e0 {
- compatible = ti,am3-prcm;
- reg = 0x44e0 0x4000;
-
- prcm_clocks: clocks {
- #address-cells = 1;
- #size-cells = 0;
- };
+ l4_wkup: l4_wkup@44c0 {
+ compatible = ti,am3-l4-wkup, simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x44c0 0x28;
- prcm_clockdomains: clockdomains {
- };
- };
+ prcm: prcm@20 {
+ compatible = ti,am3-prcm;
+ reg = 0x20 0x4000;
- scrm: scrm@44e1 {
- compatible = ti,am3-scrm;
- reg = 0x44e1 0x2000;
+ prcm_clocks: clocks {
+ #address-cells = 1;
+ #size-cells = 0;
+ };
- scrm_clocks: clocks {
- #address-cells = 1;
- #size-cells = 0;
+ prcm_clockdomains: clockdomains {
+ };
};
- scrm_clockdomains: clockdomains {
+ scm: scm@21 {
+ compatible = ti,am3-scm, simple-bus;
+ reg = 0x21 0x2000;
+
Re: [PATCHv5 27/35] ARM: dts: am33xx: add minimal l4 bus layout with control module support
Hi Tero,
On 03/20/2015 01:44 PM, Kristo, Tero wrote:
This patch creates an l4_wkup interconnect for AM33xx, and moves some of
the generic peripherals under it. System control module nodes are moved
under this new interconnect also, and the SCM clock layout is changed
to use the renamed SCM node as the clock provider.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
Documentation/devicetree/bindings/arm/omap/l4.txt |1 +
.../devicetree/bindings/arm/omap/prcm.txt |2 +-
arch/arm/boot/dts/am33xx-clocks.dtsi |2 +-
arch/arm/boot/dts/am33xx.dtsi | 87
+++-
arch/arm/mach-omap2/control.c |2 +-
5 files changed, 51 insertions(+), 43 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt
b/Documentation/devicetree/bindings/arm/omap/l4.txt
index 6402022..d333f0a 100644
--- a/Documentation/devicetree/bindings/arm/omap/l4.txt
+++ b/Documentation/devicetree/bindings/arm/omap/l4.txt
@@ -6,6 +6,7 @@ Required properties:
- compatible : Should be ti,omap2-l4 for OMAP2 family l4 core bus
Should be ti,omap2-l4-wkup for OMAP2 family l4 wkup bus
Should be ti,omap3-l4-core for OMAP3 family l4 core bus
+Should be ti,am3-l4-wkup for AM33xx family l4 wkup bus
- ranges : contains the IO map range for the bus
Examples:
diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt
b/Documentation/devicetree/bindings/arm/omap/prcm.txt
index ef5a74b..c8e2027 100644
--- a/Documentation/devicetree/bindings/arm/omap/prcm.txt
+++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt
@@ -10,7 +10,7 @@ documentation about the individual clock/clockdomain nodes.
Required properties:
- compatible:Must be one of:
ti,am3-prcm
- ti,am3-scrm
+ ti,am3-scm
ti,am4-prcm
ti,am4-scrm
ti,omap2-prcm
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi
b/arch/arm/boot/dts/am33xx-clocks.dtsi
index 712edce..236c78a 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -7,7 +7,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-scrm_clocks {
+scm_clocks {
sys_clkin_ck: sys_clkin_ck {
#clock-cells = 0;
compatible = ti,mux-clock;
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index acd3705..8d26261 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -83,20 +83,6 @@
};
};
- am33xx_control_module: control_module@4a002000 {
- compatible = syscon;
- reg = 0x44e1 0x7fc;
- };
-
- am33xx_pinmux: pinmux@44e10800 {
- compatible = pinctrl-single;
- reg = 0x44e10800 0x0238;
- #address-cells = 1;
- #size-cells = 0;
- pinctrl-single,register-width = 32;
- pinctrl-single,function-mask = 0x7f;
- };
-
/*
* XXX: Use a flat representation of the AM33XX interconnect.
* The real AM33XX interconnect network is quite complex. Since
@@ -111,37 +97,58 @@
ranges;
ti,hwmods = l3_main;
- prcm: prcm@44e0 {
- compatible = ti,am3-prcm;
- reg = 0x44e0 0x4000;
-
- prcm_clocks: clocks {
- #address-cells = 1;
- #size-cells = 0;
- };
+ l4_wkup: l4_wkup@44c0 {
+ compatible = ti,am3-l4-wkup, simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x44c0 0x28;
- prcm_clockdomains: clockdomains {
- };
- };
+ prcm: prcm@20 {
+ compatible = ti,am3-prcm;
+ reg = 0x20 0x4000;
- scrm: scrm@44e1 {
- compatible = ti,am3-scrm;
- reg = 0x44e1 0x2000;
+ prcm_clocks: clocks {
+ #address-cells = 1;
+ #size-cells = 0;
+ };
- scrm_clocks: clocks {
- #address-cells = 1;
- #size-cells = 0;
+ prcm_clockdomains: clockdomains {
+ };
};
- scrm_clockdomains: clockdomains {
+ scm: scm@21 {
+ compatible = ti,am3-scm, simple-bus;
+
Re: [PATCHv5 27/35] ARM: dts: am33xx: add minimal l4 bus layout with control module support
* Suman Anna s-a...@ti.com [150320 14:44]:
On 03/20/2015 01:44 PM, Kristo, Tero wrote:
+ scm: scm@21 {
+ compatible = ti,am3-scm, simple-bus;
+ reg = 0x21 0x2000;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x21 0x2000;
+
+ am33xx_pinmux: pinmux@800 {
+ compatible = pinctrl-single;
+ reg = 0x800 0x238;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-single,register-width = 32;
+ pinctrl-single,function-mask = 0x7f;
+ };
+
+ scm_conf: scm_conf@0 {
+ compatible = syscon;
+ reg = 0x0 0x7fc;
Hmm, you are consolidating the am33xx_control_module and cm nodes, so is
this supposed to be 0x800 or 0x7fc? I would think it should be 0x800.
Seems correct to me, it's offset 0, size 0x7fc. So that's the scm_conf
syscon area before pinctrl-single at 0x44c0 + 0x21 + 0.
The io area for pinctrl-single starts at 0x800, so the scm_conf should
be before it in the dts file.
Also, are we ordering the child nodes of scm by node names or addresses.
I have to add the wkup_m3 node, and prefer ordering by addresses.
Yeah address ordering makes most sense here IMO.
Note that you should follow the TRM Table 2-2. L4_WKUP Peripheral Memory
Map and set up things as separate devices as shown there. Pretty much
each row in that table is a separate device on the interconnect. That's
especially true if the device has registers like revision, sysc, syss
and so on. In that case they can be clocked and idled separately.
So with these changes we follow the hardware mapping, although only
partially have it populated now for l4_wkup:
l3 (ocp) +- l4_per +- ...
| |- ...
|
+- l4_wkup +- prcm
| |- scm
| |- ...
|
+- ... +- ...
Regards,
Tony
--
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the body of a message to majord...@vger.kernel.org
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