[linux-sunxi] Re: [PATCH v4 00/13] ata: ahci_platform: support allwinner R40 AHCI
Hi,
On Fri, Aug 31, 2018 at 4:31 AM Jens Axboe wrote:
>
> On 8/30/18 1:01 PM, Corentin Labbe wrote:
> > Hello
> >
> > This patchset add support for allwinner R40 AHCI controller.
> >
> > The whole patchset is tested on sun8i-r40-bananapi-m2-ultra and
> > on sun7i-a20-cubieboard2 which doesnt have any of the ressources added
> > by this serie, so no regression should come with it.
> >
> > The last patch(ata: ahci_sunxi: remove PHY code) should not be merged,
> > but will be resent for inclustion when all patchs will have hit linus
> > tree.
>
> Applied 1-12 with Hans's blessing, thanks Corentin.
Please don't merge device tree ("dts") patches, i.e. patches 9-12. We will
merge them through the sunxi / armsoc tree. Having them in separate trees
introduces conflicts when we have other stuff going through our tree.
Corentin, it's best to lay out the plan to get patches merges in the cover
letter, specifically which maintainer should take which patches, or if an
immutable tag/branch is preferred, when things can't be separated cleanly.
This helps other subsystem maintainers that don't routinely deal with armsoc.
Also, we probably can't merge the last patch that removes the PHY code,
since we have to support old device trees.
Thanks
ChenYu
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Re: [linux-sunxi] [PATCH v3 21/30] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor
On 30.08.2018 22:00, Philipp Rossak wrote:
On 30.08.2018 18:27, Ondřej Jirman wrote:
+static int sun8i_h3_calibrate(struct sun4i_gpadc_iio *info)
+{
+// regmap_write(info->regmap, SUNXI_THS_CDATA_0_1,
+// info->calibration_data[0]);
+// regmap_write(info->regmap, SUNXI_THS_CDATA_2_3,
+// info->calibration_data[1]);
This should probably be implemented, or left out completely.
regards,
o.
Thanks you are right!
This should be implemented! I will fix this in the next version!
Thanks,
Philipp
I just realized this function need to check if calibration datas are
available. Writing zeros to the calibration data regs "breaks" the
thermal sensor.
Philipp
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Re: [linux-sunxi] [PATCH v3 30/30] ARM: sun8i: a83t: full range OPP tables and CPUfreq
On 30.08.2018 18:38, Ondřej Jirman wrote: Hello, On Thu, Aug 30, 2018 at 05:45:18PM +0200, Philipp Rossak wrote: Since we have now thermal trotteling enabeled we can now add the full range of the OPP table. I'm not sure we can. I have a tablet with A83T SoC and it gets unstable at these frequencies even with thermal throttling on mainline kernel. (Though I have my own THS driver, but I doubt a different driver will change much.) There might be some other issue left in the cpufreq code. I'll let others test this on a better cooled boards though. Did you/someone test this? regards, o. I have a good cooled device, with big heatsinks and a fan blowing directly on it. But there is some big issue left! cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq [ 85.076270] Unable to handle kernel paging request at virtual address 2e83c684 [ 85.083519] pgd = (ptrval) [ 85.086220] [2e83c684] *pgd= [ 85.089813] Internal error: Oops: 5 [#3] SMP ARM [ 85.094429] Modules linked in: [ 85.097483] CPU: 4 PID: 127 Comm: sh Tainted: G D W 4.18.0-00031-g8f59917020b9-dirty #2 [ 85.106597] Hardware name: Allwinner A83t board [ 85.30] PC is at down_write+0x14/0x54 [ 85.115135] LR is at anon_vma_clone+0x9c/0x1e4 [ 85.119571] pc : []lr : []psr: 6013 [ 85.125826] sp : ede45e70 ip : 01a0 fp : eea3c690 [ 85.131041] r10: eea4193c r9 : 00400200 r8 : c0a942a4 [ 85.136255] r7 : 2e83c680 r6 : eea3aea0 r5 : eea3b220 r4 : 2e83c684 [ 85.142771] r3 : 0001 r2 : 2e83c680 r1 : ede45e58 r0 : 2e83c684 [ 85.149287] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none [ 85.156410] Control: 10c5387d Table: 6df1806a DAC: 0051 [ 85.162145] Process sh (pid: 127, stack limit = 0x(ptrval)) [ 85.167706] Stack: (0xede45e70 to 0xede46000) [ 85.172057] 5e60: eea3b900 c01e71b8 eea41900 ffebd684 [ 85.180221] 5e80: c0a637b0 c07ea07c c0a10754 eea3aea0 eea41900 c0a04c48 edd71880 [ 85.188385] 5ea0: eea3aea0 eea41900 c0a69030 c01e7324 0002 edd701c0 c0a04c48 edd71880 [ 85.196548] 5ec0: c011c2f4 0069 0002 [ 85.204711] 5ee0: edd701c0 edd82280 eea3af00 edd701f8 edd718b8 eea3af08 eea3af14 [ 85.212875] 5f00: eea3af10 ede44000 edd8255c 01200011 ede45f14 ede45f14 b61ea11a [ 85.221039] 5f20: edd805c0 01200011 c0a04c48 beef38b0 0078 [ 85.229202] 5f40: beef38dc c011ce0c ede44000 00ae c012d9e0 [ 85.237365] 5f60: eea43480 0400 b61ea11a b6fb5068 b6f8b670 beef38b0 [ 85.245529] 5f80: 0078 c0101204 ede44000 0078 beef38dc c011d1bc b6fb5068 [ 85.253692] 5fa0: 00ae c0101000 b6fb5068 b6f8b670 01200011 [ 85.261856] 5fc0: b6fb5068 b6f8b670 beef38b0 0078 b6f8ac4c b6fb5490 beef38dc [ 85.270020] 5fe0: 0002 beef38b0 b6f5bfd0 6010 01200011 [ 85.278191] [] (down_write) from [] (anon_vma_clone+0x9c/0x1e4) [ 85.285836] [] (anon_vma_clone) from [] (anon_vma_fork+0x24/0x160) [ 85.293741] [] (anon_vma_fork) from [] (copy_process.part.3+0xbc4/0x158c) [ 85.302253] [] (copy_process.part.3) from [] (_do_fork+0xb0/0x394) [ 85.310157] [] (_do_fork) from [] (sys_clone+0x20/0x28) [ 85.317107] [] (sys_clone) from [] (ret_fast_syscall+0x0/0x54) [ 85.324661] Exception stack(0xede45fa8 to 0xede45ff0) [ 85.329704] 5fa0: b6fb5068 b6f8b670 01200011 [ 85.337868] 5fc0: b6fb5068 b6f8b670 beef38b0 0078 b6f8ac4c b6fb5490 beef38dc [ 85.346021] 5fe0: 0002 beef38b0 b6f5bfd0 [ 85.351068] Code: e1a04000 f590f000 e3a03001 e34f3fff (e1902f9f) [ 85.357200] ---[ end trace aad10e0b4fcbf194 ]--- OR cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq [ 73.873939] [ cut here ] [ 73.878584] WARNING: CPU: 5 PID: 132 at mm/rmap.c:235 unlink_anon_vmas+0x1f4/0x1fc [ 73.886210] Modules linked in: [ 73.889276] CPU: 5 PID: 132 Comm: sh Tainted: G D 4.18.0-00031-g8f59917020b9-dirty #2 [ 73.898391] Hardware name: Allwinner A83t board [ 73.902934] [] (unwind_backtrace) from [] (show_stack+0x10/0x14) [ 73.910671] [] (show_stack) from [] (dump_stack+0x84/0x98) [ 73.917887] [] (dump_stack) from [] (__warn+0xfc/0x114) [ 73.924840] [] (__warn) from [] (warn_slowpath_null+0x40/0x48) [ 73.932398] [] (warn_slowpath_null) from [] (unlink_anon_vmas+0x1f4/0x1fc) [ 73.941006] [] (unlink_anon_vmas) from [] (free_pgtables+0x78/0xcc) [ 73.948999] [] (free_pgtables) from [] (exit_mmap+0xe4/0x188) [ 73.956471] [] (exit_mmap) from [] (mmput+0x40/0xf0) [ 73.963169] [] (mmput) from [] (flush_old_exec+0x550/0x6e0) [ 73.970473] [] (flush_old_exec) from [] (load_elf_binary+0x2f0/0x1324) [ 73.978726] [] (load_elf_binary) from
[linux-sunxi] Re: [PATCH v4 13/13 DONOTMERGE] ata: ahci_sunxi: remove PHY code
HI,
On 30-08-18 21:01, Corentin Labbe wrote:
Since PHY code is now handled by sun4i-a10-sata-phy, the code in
ahci_sunxi is useless, remove it.
Signed-off-by: Corentin Labbe
---
drivers/ata/ahci_sunxi.c | 93
1 file changed, 93 deletions(-)
diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
index b8cf3a1be80b..af17f8ce65b2 100644
--- a/drivers/ata/ahci_sunxi.c
+++ b/drivers/ata/ahci_sunxi.c
@@ -58,15 +58,6 @@ MODULE_PARM_DESC(enable_pmp,
#define AHCI_P0PHYCR 0x0178
#define AHCI_P0PHYSR 0x017c
-static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
-{
- u32 reg_val;
-
- reg_val = readl(reg);
- reg_val &= ~(clr_val);
- writel(reg_val, reg);
-}
-
static void sunxi_setbits(void __iomem *reg, u32 set_val)
{
u32 reg_val;
@@ -86,81 +77,6 @@ static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val,
u32 set_val)
writel(reg_val, reg);
}
-static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
-{
- return (readl(reg) >> shift) & mask;
-}
-
-static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
-{
- u32 reg_val;
- int timeout;
-
- /*
-* When using the new binding, the presence of a sata port node
-* means that PHY is handled by the PHY driver.
-* */
- if (of_get_child_count(dev->of_node)) {
- dev_info(dev, "Bypassing PHY init\n");
- return 0;
- }
-
- /* This magic is from the original code */
- writel(0, reg_base + AHCI_RWCR);
- msleep(5);
-
- sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
-(0x7 << 24),
-(0x5 << 24) | BIT(23) | BIT(18));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
-(0x3 << 16) | (0x1f << 8) | (0x3 << 6),
-(0x2 << 16) | (0x6 << 8) | (0x2 << 6));
- sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
- sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
-(0x7 << 20), (0x3 << 20));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
-(0x1f << 5), (0x19 << 5));
- msleep(5);
-
- sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
-
- timeout = 250; /* Power up takes aprox 50 us */
- do {
- reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28);
- if (reg_val == 0x02)
- break;
-
- if (--timeout == 0) {
- dev_err(dev, "PHY power up failed.\n");
- return -EIO;
- }
- udelay(1);
- } while (1);
-
- sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
-
- timeout = 100; /* Calibration takes aprox 10 us */
- do {
- reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24);
- if (reg_val == 0x00)
- break;
-
- if (--timeout == 0) {
- dev_err(dev, "PHY calibration failed.\n");
- return -EIO;
- }
- udelay(1);
- } while (1);
-
- msleep(15);
-
- writel(0x7, reg_base + AHCI_RWCR);
-
- return 0;
-}
-
static void ahci_sunxi_start_engine(struct ata_port *ap)
{
void __iomem *port_mmio = ahci_port_base(ap);
@@ -186,7 +102,6 @@ static struct scsi_host_template ahci_platform_sht = {
static int ahci_sunxi_probe(struct platform_device *pdev)
{
- struct device *dev = >dev;
struct ahci_host_priv *hpriv;
int rc;
@@ -200,10 +115,6 @@ static int ahci_sunxi_probe(struct platform_device *pdev)
if (rc)
return rc;
- rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
- if (rc)
- goto disable_resources;
-
hpriv->flags = AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
AHCI_HFLAG_YES_NCQ;
@@ -238,10 +149,6 @@ static int ahci_sunxi_resume(struct device *dev)
if (rc)
return rc;
- rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
- if (rc)
- goto disable_resources;
-
rc = ahci_platform_resume_host(dev);
if (rc)
goto disable_resources;
After this change ahci_sunxi_resume() is the same as ahci_platform_resume,
so you can drop the entire function and directly refer to
ahci_platform_resume in ahci_sunxi_pm_ops.
Regards,
Hans
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[linux-sunxi] Re: [PATCH v4 00/13] ata: ahci_platform: support allwinner R40 AHCI
Hi, On 30-08-18 21:01, Corentin Labbe wrote: Hello This patchset add support for allwinner R40 AHCI controller. The whole patchset is tested on sun8i-r40-bananapi-m2-ultra and on sun7i-a20-cubieboard2 which doesnt have any of the ressources added by this serie, so no regression should come with it. The last patch(ata: ahci_sunxi: remove PHY code) should not be merged, but will be resent for inclustion when all patchs will have hit linus tree. Thank you for your work on this, the entire series looks good to me: Reviewed-by: Hans de Goede Note I've one remark for the final do-not-merge patch I will reply to that patch separately. Regards, Hans Changes since v3: - Moved PHY code to a new sun4i-a10-phy-sata driver - Removed reset code since ahci_platform support now reset controller. Changes since V2 - Moved all ressources management to ahci_platform Corentin Labbe (13): dt-bindings: ata: ahci-platform: fix indentation of target-supply ata: ahci_platform: add support for AHCI controller regulator dt-bindings: ata: ahci-platform: document ahci-supply phy: Add sun4i-a10-phy-sata driver dt-bindings: phy: document sun4i-a10-sata-phy dt-bindings: ata: update ahci_sunxi bindings ata: ahci_sunxi: Bypass PHY init when using the new binding ata: ahci_sunxi: add support for r40 ARM: dts: sun8i: r40: add sata node ARM: dts: sun8i: sun8i-r40-bananapi-m2-ultra: enable AHCI ARM: dts: sun7i: a20: add sata-port/sata-phy nodes ARM: dts: sun4i: a10: add sata-port/sata-phy nodes ata: ahci_sunxi: remove PHY code .../devicetree/bindings/ata/ahci-platform.txt | 11 +- .../devicetree/bindings/phy/sun4i-sata-phy.txt | 20 ++ arch/arm/boot/dts/sun4i-a10.dtsi | 13 ++ arch/arm/boot/dts/sun7i-a20.dtsi | 13 ++ arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 21 +++ arch/arm/boot/dts/sun8i-r40.dtsi | 23 +++ drivers/ata/ahci.h | 1 + drivers/ata/ahci_sunxi.c | 87 + drivers/ata/libahci_platform.c | 26 ++- drivers/phy/allwinner/Kconfig | 7 + drivers/phy/allwinner/Makefile | 1 + drivers/phy/allwinner/phy-sun4i-sata.c | 208 + 12 files changed, 343 insertions(+), 88 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/sun4i-sata-phy.txt create mode 100644 drivers/phy/allwinner/phy-sun4i-sata.c -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] [PATCH v3 21/30] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor
On 30.08.2018 18:27, Ondřej Jirman wrote:
+static int sun8i_h3_calibrate(struct sun4i_gpadc_iio *info)
+{
+// regmap_write(info->regmap, SUNXI_THS_CDATA_0_1,
+// info->calibration_data[0]);
+// regmap_write(info->regmap, SUNXI_THS_CDATA_2_3,
+// info->calibration_data[1]);
This should probably be implemented, or left out completely.
regards,
o.
Thanks you are right!
This should be implemented! I will fix this in the next version!
Thanks,
Philipp
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[linux-sunxi] [PATCH v4 13/13 DONOTMERGE] ata: ahci_sunxi: remove PHY code
Since PHY code is now handled by sun4i-a10-sata-phy, the code in
ahci_sunxi is useless, remove it.
Signed-off-by: Corentin Labbe
---
drivers/ata/ahci_sunxi.c | 93
1 file changed, 93 deletions(-)
diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
index b8cf3a1be80b..af17f8ce65b2 100644
--- a/drivers/ata/ahci_sunxi.c
+++ b/drivers/ata/ahci_sunxi.c
@@ -58,15 +58,6 @@ MODULE_PARM_DESC(enable_pmp,
#define AHCI_P0PHYCR 0x0178
#define AHCI_P0PHYSR 0x017c
-static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
-{
- u32 reg_val;
-
- reg_val = readl(reg);
- reg_val &= ~(clr_val);
- writel(reg_val, reg);
-}
-
static void sunxi_setbits(void __iomem *reg, u32 set_val)
{
u32 reg_val;
@@ -86,81 +77,6 @@ static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val,
u32 set_val)
writel(reg_val, reg);
}
-static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
-{
- return (readl(reg) >> shift) & mask;
-}
-
-static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
-{
- u32 reg_val;
- int timeout;
-
- /*
-* When using the new binding, the presence of a sata port node
-* means that PHY is handled by the PHY driver.
-* */
- if (of_get_child_count(dev->of_node)) {
- dev_info(dev, "Bypassing PHY init\n");
- return 0;
- }
-
- /* This magic is from the original code */
- writel(0, reg_base + AHCI_RWCR);
- msleep(5);
-
- sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
-(0x7 << 24),
-(0x5 << 24) | BIT(23) | BIT(18));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
-(0x3 << 16) | (0x1f << 8) | (0x3 << 6),
-(0x2 << 16) | (0x6 << 8) | (0x2 << 6));
- sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
- sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
-(0x7 << 20), (0x3 << 20));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
-(0x1f << 5), (0x19 << 5));
- msleep(5);
-
- sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
-
- timeout = 250; /* Power up takes aprox 50 us */
- do {
- reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28);
- if (reg_val == 0x02)
- break;
-
- if (--timeout == 0) {
- dev_err(dev, "PHY power up failed.\n");
- return -EIO;
- }
- udelay(1);
- } while (1);
-
- sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
-
- timeout = 100; /* Calibration takes aprox 10 us */
- do {
- reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24);
- if (reg_val == 0x00)
- break;
-
- if (--timeout == 0) {
- dev_err(dev, "PHY calibration failed.\n");
- return -EIO;
- }
- udelay(1);
- } while (1);
-
- msleep(15);
-
- writel(0x7, reg_base + AHCI_RWCR);
-
- return 0;
-}
-
static void ahci_sunxi_start_engine(struct ata_port *ap)
{
void __iomem *port_mmio = ahci_port_base(ap);
@@ -186,7 +102,6 @@ static struct scsi_host_template ahci_platform_sht = {
static int ahci_sunxi_probe(struct platform_device *pdev)
{
- struct device *dev = >dev;
struct ahci_host_priv *hpriv;
int rc;
@@ -200,10 +115,6 @@ static int ahci_sunxi_probe(struct platform_device *pdev)
if (rc)
return rc;
- rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
- if (rc)
- goto disable_resources;
-
hpriv->flags = AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
AHCI_HFLAG_YES_NCQ;
@@ -238,10 +149,6 @@ static int ahci_sunxi_resume(struct device *dev)
if (rc)
return rc;
- rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
- if (rc)
- goto disable_resources;
-
rc = ahci_platform_resume_host(dev);
if (rc)
goto disable_resources;
--
2.16.4
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[linux-sunxi] [PATCH v4 12/13] ARM: dts: sun4i: a10: add sata-port/sata-phy nodes
This patch convert sun4i-a10 sata to the new binding which use a sata
phy node.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun4i-a10.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 3d62a8950720..52d5c2e79499 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -556,7 +556,20 @@
reg = <0x01c18000 0x1000>;
interrupts = <56>;
clocks = < CLK_AHB_SATA>, < CLK_SATA>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
+
+ sata_port: sata-port@0 {
+ reg = <0>;
+ phys = <_phy>;
+ };
+ };
+
+ sata_phy: sata_phy@1c180c0 {
+ compatible = "allwinner,sun4i-a10-sata-phy";
+ reg = <0x01c180c0 0x200>;
+ #phy-cells = <0>;
};
ehci1: usb@1c1c000 {
--
2.16.4
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[linux-sunxi] [PATCH v4 08/13] ata: ahci_sunxi: add support for r40
This patch add the r40 compatible to the ahci_sunxi's supported list of
compatible.
Since R40 need ahci_platform to handle the reset controller, we also add
the new AHCI_PLATFORM_GET_RESETS flag for ahci_platform_get_resources().
This has no consequence for older platform (a10, a20) since the reset is
optional.
Signed-off-by: Corentin Labbe
---
drivers/ata/ahci_sunxi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
index a09d189c6dda..b8cf3a1be80b 100644
--- a/drivers/ata/ahci_sunxi.c
+++ b/drivers/ata/ahci_sunxi.c
@@ -190,7 +190,7 @@ static int ahci_sunxi_probe(struct platform_device *pdev)
struct ahci_host_priv *hpriv;
int rc;
- hpriv = ahci_platform_get_resources(pdev, 0);
+ hpriv = ahci_platform_get_resources(pdev, AHCI_PLATFORM_GET_RESETS);
if (IS_ERR(hpriv))
return PTR_ERR(hpriv);
@@ -259,6 +259,7 @@ static SIMPLE_DEV_PM_OPS(ahci_sunxi_pm_ops,
ahci_platform_suspend,
static const struct of_device_id ahci_sunxi_of_match[] = {
{ .compatible = "allwinner,sun4i-a10-ahci", },
+ { .compatible = "allwinner,sun8i-r40-ahci", },
{ },
};
MODULE_DEVICE_TABLE(of, ahci_sunxi_of_match);
--
2.16.4
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[linux-sunxi] [PATCH v4 09/13] ARM: dts: sun8i: r40: add sata node
R40 have a sata controller which is the same as A20.
This patch adds a DT node for it.
Signed-off-by: Icenowy Zheng
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-r40.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 852c2ccc3268..d6b5820da850 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -550,6 +550,29 @@
#size-cells = <0>;
};
+ ahci: sata@1c18000 {
+ compatible = "allwinner,sun8i-r40-ahci";
+ reg = <0x01c18000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_SATA>, < CLK_SATA>;
+ resets = < RST_BUS_SATA>;
+ resets-name = "ahci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata_port: sata-port@0 {
+ reg = <0>;
+ phys = <_phy>;
+ };
+ };
+
+ sata_phy: sata-phy@1c180c0 {
+ compatible = "allwinner,sun8i-r40-sata-phy";
+ reg = <0x1c180c0 0x200>;
+ #phy-cells = <0>;
+ };
+
gmac: ethernet@1c5 {
compatible = "allwinner,sun8i-r40-gmac";
syscon = <>;
--
2.16.4
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[linux-sunxi] [PATCH v4 04/13] phy: Add sun4i-a10-phy-sata driver
This patch create a PHY SATA driver for allwinner SoC A10/A20/R40.
The code is taken from drivers/ata/ahci_sunxi.c but cannot be removed
from it yet, since we need to finish the transition to new binding with
the PHY usage.
Signed-off-by: Corentin Labbe
---
drivers/phy/allwinner/Kconfig | 7 ++
drivers/phy/allwinner/Makefile | 1 +
drivers/phy/allwinner/phy-sun4i-sata.c | 208 +
3 files changed, 216 insertions(+)
create mode 100644 drivers/phy/allwinner/phy-sun4i-sata.c
diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
index cdc1e745ba47..ef6fa389389a 100644
--- a/drivers/phy/allwinner/Kconfig
+++ b/drivers/phy/allwinner/Kconfig
@@ -1,6 +1,13 @@
#
# Phy drivers for Allwinner platforms
#
+config PHY_SUN4I_SATA
+ tristate "Allwinner sunxi SoC SATA PHY driver"
+ depends on ARCH_SUNXI && HAS_IOMEM && OF
+ select GENERIC_PHY
+ help
+ Enable this to support the SATA PHY present on A10/A20/R40.
+
config PHY_SUN4I_USB
tristate "Allwinner sunxi SoC USB PHY driver"
depends on ARCH_SUNXI && HAS_IOMEM && OF
diff --git a/drivers/phy/allwinner/Makefile b/drivers/phy/allwinner/Makefile
index 8605529c01a1..73ef882edb53 100644
--- a/drivers/phy/allwinner/Makefile
+++ b/drivers/phy/allwinner/Makefile
@@ -1,2 +1,3 @@
+obj-$(CONFIG_PHY_SUN4I_SATA) += phy-sun4i-sata.o
obj-$(CONFIG_PHY_SUN4I_USB)+= phy-sun4i-usb.o
obj-$(CONFIG_PHY_SUN9I_USB)+= phy-sun9i-usb.o
diff --git a/drivers/phy/allwinner/phy-sun4i-sata.c
b/drivers/phy/allwinner/phy-sun4i-sata.c
new file mode 100644
index ..93e29f99d26c
--- /dev/null
+++ b/drivers/phy/allwinner/phy-sun4i-sata.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Allwinner sun4i SATA phy driver
+ * Copyright (C) 2018 Corentin Labbe
+ *
+ * PHY init code taken from drivers/ahci/ahci_sunxi.c
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define AHCI_PHYCS0R 0x
+#define AHCI_PHYCS1R 0x0004
+#define AHCI_PHYCS2R 0x0008
+#define AHCI_TIMER1MS 0x0020
+#define AHCI_GPARAM1R 0x0028
+#define AHCI_GPARAM2R 0x002c
+#define AHCI_PPARAMR 0x0030
+#define AHCI_TESTR 0x0034
+#define AHCI_VERSIONR 0x0038
+#define AHCI_IDR 0x003c
+#define AHCI_RWCR 0x003c
+#define AHCI_P0DMACR 0x00b0
+#define AHCI_P0PHYCR 0x00b8
+#define AHCI_P0PHYSR 0x00bc
+
+struct sun4i_sata_phy_data {
+ struct phy *phy;
+ struct device *dev;
+ void __iomem*base;
+};
+
+static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
+{
+ u32 reg_val;
+
+ reg_val = readl(reg);
+ reg_val &= ~(clr_val);
+ writel(reg_val, reg);
+}
+
+static void sunxi_setbits(void __iomem *reg, u32 set_val)
+{
+ u32 reg_val;
+
+ reg_val = readl(reg);
+ reg_val |= set_val;
+ writel(reg_val, reg);
+}
+
+static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
+{
+ u32 reg_val;
+
+ reg_val = readl(reg);
+ reg_val &= ~(clr_val);
+ reg_val |= set_val;
+ writel(reg_val, reg);
+}
+
+static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
+{
+ return (readl(reg) >> shift) & mask;
+}
+
+static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
+{
+ u32 reg_val;
+ int timeout;
+
+ /* This magic is from the original code */
+ writel(0, reg_base + AHCI_RWCR);
+ msleep(5);
+
+ sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
+ sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, (0x7 << 24),
+(0x5 << 24) | BIT(23) | BIT(18));
+ sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
+(0x3 << 16) | (0x1f << 8) | (0x3 << 6),
+(0x2 << 16) | (0x6 << 8) | (0x2 << 6));
+ sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
+ sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
+ sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20));
+ sunxi_clrsetbits(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5));
+ msleep(5);
+
+ sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
+
+ timeout = 250; /* Power up takes aprox 50 us */
+ do {
+ reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28);
+ if (reg_val == 0x02)
+ break;
+
+ if (--timeout == 0) {
+ dev_err(dev, "PHY power up failed.\n");
+ return -EIO;
+ }
+ udelay(1);
+ } while (1);
+
+ sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
+
+ timeout = 100; /* Calibration takes aprox 10 us */
+ do {
+ reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24);
+ if (reg_val == 0x00)
+ break;
+
+
[linux-sunxi] [PATCH v4 03/13] dt-bindings: ata: ahci-platform: document ahci-supply
This patch document the new optional ahci-supply. Signed-off-by: Corentin Labbe Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/ata/ahci-platform.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt index b88820b4c01e..f495774c8af9 100644 --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt +++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt @@ -33,6 +33,7 @@ Optional properties: - target-supply : regulator for SATA target power - phys : reference to the SATA PHY node - phy-names : must be "sata-phy" +- ahci-supply : regulator for AHCI controller - ports-implemented : Mask that indicates which ports that the HBA supports are available for software to use. Useful if PORTS_IMPL is not programmed by the BIOS, which is true with -- 2.16.4 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v4 11/13] ARM: dts: sun7i: a20: add sata-port/sata-phy nodes
This patch convert sun7i-a20 sata to the new binding which use a sata
phy node.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun7i-a20.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 8f7e1e29841f..8ff28f7afa85 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -667,6 +667,19 @@
interrupts = ;
clocks = < CLK_AHB_SATA>, < CLK_SATA>;
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sata_port: sata-port@0 {
+ reg = <0>;
+ phys = <_phy>;
+ };
+ };
+
+ sata_phy: sata-phy@1c180c0 {
+ compatible = "allwinner,sun4i-a10-sata-phy";
+ reg = <0x1c180c0 0x200>;
+ #phy-cells = <0>;
};
ehci1: usb@1c1c000 {
--
2.16.4
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[linux-sunxi] [PATCH v4 06/13] dt-bindings: ata: update ahci_sunxi bindings
Since phy code is moved from ahci_sunxi to a dedicated driver, the
binding need to be updated with the new phy node requirement.
Signed-off-by: Corentin Labbe
---
Documentation/devicetree/bindings/ata/ahci-platform.txt | 8
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt
b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index f495774c8af9..aa6f4c745097 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -50,6 +50,14 @@ And at least one of the following properties:
- phys : reference to the SATA PHY node
- target-supply : regulator for SATA target power
+Required properties for:
+* allwinner,sun4i-a10-ahci
+* allwinner,sun8i-r40-ahci
+A port sub-node must be present and linked to a sata_phy.
+
+Required properties for allwinner,sun8i-r40-ahci
+The reset and ahci-supply properties must be present.
+
Examples:
sata@ffe08000 {
compatible = "snps,spear-ahci";
--
2.16.4
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[linux-sunxi] [PATCH v4 10/13] ARM: dts: sun8i: sun8i-r40-bananapi-m2-ultra: enable AHCI
This patch enable the AHCI controller.
Since this controller need two regulator, this patch add them.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index a891a387e8f1..b991b635c07d 100644
--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -105,6 +105,11 @@
};
};
+ {
+ ahci-supply = <_dldo4>;
+ status = "okay";
+};
+
{
status = "okay";
};
@@ -250,6 +255,22 @@
regulator-name = "vcc-wifi";
};
+_dldo4 {
+ regulator-min-microvolt = <250>;
+ regulator-max-microvolt = <250>;
+ regulator-name = "vdd2v5-sata";
+};
+
+_eldo3 {
+ regulator-min-microvolt = <120>;
+ regulator-max-microvolt = <120>;
+ regulator-name = "vdd1v2-sata";
+};
+
+_phy {
+ phy-supply = <_eldo3>;
+};
+
_tv0 {
status = "okay";
};
--
2.16.4
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[linux-sunxi] [PATCH v4 07/13] ata: ahci_sunxi: Bypass PHY init when using the new binding
The new binding split sata in two (ahci + PHY).
ahci_sunxi must not mess with PHY when the new binding is in use.
So when we detect sub-nodes, bypass the PHY init code.
This is a temporarly workaround for the period where DT and ata code
will be merged from separate tree.
When both new binding and PHY driver will be merged, a new patch which
remove all PHY code from ahci_sunxi.c will be sent.
Signed-off-by: Corentin Labbe
---
drivers/ata/ahci_sunxi.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
index 631610b72aa5..a09d189c6dda 100644
--- a/drivers/ata/ahci_sunxi.c
+++ b/drivers/ata/ahci_sunxi.c
@@ -96,6 +96,15 @@ static int ahci_sunxi_phy_init(struct device *dev, void
__iomem *reg_base)
u32 reg_val;
int timeout;
+ /*
+* When using the new binding, the presence of a sata port node
+* means that PHY is handled by the PHY driver.
+* */
+ if (of_get_child_count(dev->of_node)) {
+ dev_info(dev, "Bypassing PHY init\n");
+ return 0;
+ }
+
/* This magic is from the original code */
writel(0, reg_base + AHCI_RWCR);
msleep(5);
--
2.16.4
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[linux-sunxi] [PATCH v4 05/13] dt-bindings: phy: document sun4i-a10-sata-phy
This patch document the sun4i-a10-sata-phy bindings.
Signed-off-by: Corentin Labbe
---
.../devicetree/bindings/phy/sun4i-sata-phy.txt | 20
1 file changed, 20 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/sun4i-sata-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/sun4i-sata-phy.txt
b/Documentation/devicetree/bindings/phy/sun4i-sata-phy.txt
new file mode 100644
index ..f031542717c1
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/sun4i-sata-phy.txt
@@ -0,0 +1,20 @@
+Allwinner sun4i SATA PHY
+---
+
+Required properties:
+- compatible : should be one of
+ * allwinner,sun4i-a10-sata-phy
+ * allwinner,sun8i-r40-sata-phy
+- reg : a list of offset + length pairs
+- #phy-cells : from the generic phy bindings, must be 0
+
+Optional properties:
+- phy-supply : from the generic phy bindings, a phandle to a regulator that
+ provides power to the PHY.
+
+Example:
+ sata_phy0: sata-phy@a01800 {
+ compatible = "allwinner,sun8i-r40-sata-phy";
+ reg = <0x00a01800 0x4>;
+ #phy-cells = <0>;
+ };
--
2.16.4
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[linux-sunxi] [PATCH v4 02/13] ata: ahci_platform: add support for AHCI controller regulator
The SoC R40 AHCI controller need a regulator to work.
So this patch add a way to add an optional regulator on AHCI controller.
Signed-off-by: Corentin Labbe
---
drivers/ata/ahci.h | 1 +
drivers/ata/libahci_platform.c | 26 --
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 6a1515f0da40..1415f1012de5 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -352,6 +352,7 @@ struct ahci_host_priv {
struct clk *clks[AHCI_MAX_CLKS]; /* Optional */
struct reset_control*rsts; /* Optional */
struct regulator**target_pwrs; /* Optional */
+ struct regulator*ahci_regulator;/* Optional */
/*
* If platform uses PHYs. There is a 1:1 relation between the port
number and
* the PHY position in this array.
diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c
index c92c10d55374..a886b61476a3 100644
--- a/drivers/ata/libahci_platform.c
+++ b/drivers/ata/libahci_platform.c
@@ -139,7 +139,7 @@ EXPORT_SYMBOL_GPL(ahci_platform_disable_clks);
* ahci_platform_enable_regulators - Enable regulators
* @hpriv: host private area to store config values
*
- * This function enables all the regulators found in
+ * This function enables all the regulators found in controller and
* hpriv->target_pwrs, if any. If a regulator fails to be enabled, it
* disables all the regulators already enabled in reverse order and
* returns an error.
@@ -151,6 +151,12 @@ int ahci_platform_enable_regulators(struct ahci_host_priv
*hpriv)
{
int rc, i;
+ if (hpriv->ahci_regulator) {
+ rc = regulator_enable(hpriv->ahci_regulator);
+ if (rc)
+ return rc;
+ }
+
for (i = 0; i < hpriv->nports; i++) {
if (!hpriv->target_pwrs[i])
continue;
@@ -167,6 +173,8 @@ int ahci_platform_enable_regulators(struct ahci_host_priv
*hpriv)
if (hpriv->target_pwrs[i])
regulator_disable(hpriv->target_pwrs[i]);
+ if (hpriv->ahci_regulator)
+ regulator_disable(hpriv->ahci_regulator);
return rc;
}
EXPORT_SYMBOL_GPL(ahci_platform_enable_regulators);
@@ -175,7 +183,8 @@ EXPORT_SYMBOL_GPL(ahci_platform_enable_regulators);
* ahci_platform_disable_regulators - Disable regulators
* @hpriv: host private area to store config values
*
- * This function disables all regulators found in hpriv->target_pwrs.
+ * This function disables all regulators found in hpriv->target_pwrs and
+ * AHCI controller.
*/
void ahci_platform_disable_regulators(struct ahci_host_priv *hpriv)
{
@@ -186,6 +195,9 @@ void ahci_platform_disable_regulators(struct ahci_host_priv
*hpriv)
continue;
regulator_disable(hpriv->target_pwrs[i]);
}
+
+ if (hpriv->ahci_regulator)
+ regulator_disable(hpriv->ahci_regulator);
}
EXPORT_SYMBOL_GPL(ahci_platform_disable_regulators);
/**
@@ -351,6 +363,7 @@ static int ahci_platform_get_regulator(struct
ahci_host_priv *hpriv, u32 port,
*
* 1) mmio registers (IORESOURCE_MEM 0, mandatory)
* 2) regulator for controlling the targets power (optional)
+ *regulator for controlling the AHCI controller (optional)
* 3) 0 - AHCI_MAX_CLKS clocks, as specified in the devs devicetree node,
*or for non devicetree enabled platforms a single clock
* 4) resets, if flags has AHCI_PLATFORM_GET_RESETS (optional)
@@ -408,6 +421,15 @@ struct ahci_host_priv *ahci_platform_get_resources(struct
platform_device *pdev,
hpriv->clks[i] = clk;
}
+ hpriv->ahci_regulator = devm_regulator_get_optional(dev, "ahci");
+ if (IS_ERR(hpriv->ahci_regulator)) {
+ rc = PTR_ERR(hpriv->ahci_regulator);
+ if (rc == -EPROBE_DEFER)
+ goto err_out;
+ rc = 0;
+ hpriv->ahci_regulator = NULL;
+ }
+
if (flags & AHCI_PLATFORM_GET_RESETS) {
hpriv->rsts = devm_reset_control_array_get_optional_shared(dev);
if (IS_ERR(hpriv->rsts)) {
--
2.16.4
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[linux-sunxi] [PATCH v4 01/13] dt-bindings: ata: ahci-platform: fix indentation of target-supply
This patch fix the indentation of target-supply's ':'.
Signed-off-by: Corentin Labbe
---
Documentation/devicetree/bindings/ata/ahci-platform.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt
b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index 5d5bd456d9d9..b88820b4c01e 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -47,7 +47,7 @@ Sub-nodes required properties:
- reg : the port number
And at least one of the following properties:
- phys : reference to the SATA PHY node
-- target-supply: regulator for SATA target power
+- target-supply : regulator for SATA target power
Examples:
sata@ffe08000 {
--
2.16.4
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[linux-sunxi] [PATCH v4 00/13] ata: ahci_platform: support allwinner R40 AHCI
Hello This patchset add support for allwinner R40 AHCI controller. The whole patchset is tested on sun8i-r40-bananapi-m2-ultra and on sun7i-a20-cubieboard2 which doesnt have any of the ressources added by this serie, so no regression should come with it. The last patch(ata: ahci_sunxi: remove PHY code) should not be merged, but will be resent for inclustion when all patchs will have hit linus tree. Changes since v3: - Moved PHY code to a new sun4i-a10-phy-sata driver - Removed reset code since ahci_platform support now reset controller. Changes since V2 - Moved all ressources management to ahci_platform Corentin Labbe (13): dt-bindings: ata: ahci-platform: fix indentation of target-supply ata: ahci_platform: add support for AHCI controller regulator dt-bindings: ata: ahci-platform: document ahci-supply phy: Add sun4i-a10-phy-sata driver dt-bindings: phy: document sun4i-a10-sata-phy dt-bindings: ata: update ahci_sunxi bindings ata: ahci_sunxi: Bypass PHY init when using the new binding ata: ahci_sunxi: add support for r40 ARM: dts: sun8i: r40: add sata node ARM: dts: sun8i: sun8i-r40-bananapi-m2-ultra: enable AHCI ARM: dts: sun7i: a20: add sata-port/sata-phy nodes ARM: dts: sun4i: a10: add sata-port/sata-phy nodes ata: ahci_sunxi: remove PHY code .../devicetree/bindings/ata/ahci-platform.txt | 11 +- .../devicetree/bindings/phy/sun4i-sata-phy.txt | 20 ++ arch/arm/boot/dts/sun4i-a10.dtsi | 13 ++ arch/arm/boot/dts/sun7i-a20.dtsi | 13 ++ arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 21 +++ arch/arm/boot/dts/sun8i-r40.dtsi | 23 +++ drivers/ata/ahci.h | 1 + drivers/ata/ahci_sunxi.c | 87 + drivers/ata/libahci_platform.c | 26 ++- drivers/phy/allwinner/Kconfig | 7 + drivers/phy/allwinner/Makefile | 1 + drivers/phy/allwinner/phy-sun4i-sata.c | 208 + 12 files changed, 343 insertions(+), 88 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/sun4i-sata-phy.txt create mode 100644 drivers/phy/allwinner/phy-sun4i-sata.c -- 2.16.4 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] [PATCH v3 09/30] iio: adc: Threat A33 as thermal sensor and remove non thermal sun4i channel
On Thu, Aug 30, 2018 at 05:44:57PM +0200, Philipp Rossak wrote:
> We want to use this driver mostly as thermal sensor, that still supports
> the adc for the older chips, thus we threat the A33 as thermal sensor.
> We also remove the adc channel without thermal support.
Threat -> treat (in the title and in the message body too)
> Signed-off-by: Philipp Rossak
> ---
> drivers/iio/adc/sun4i-gpadc-iio.c | 19 ---
> 1 file changed, 19 deletions(-)
>
> diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
> b/drivers/iio/adc/sun4i-gpadc-iio.c
> index ab474ce86fb6..658a7e3e3370 100644
> --- a/drivers/iio/adc/sun4i-gpadc-iio.c
> +++ b/drivers/iio/adc/sun4i-gpadc-iio.c
> @@ -123,23 +123,6 @@ static const struct iio_chan_spec sun4i_gpadc_channels[]
> = {
> },
> };
>
> -static const struct iio_chan_spec sun4i_gpadc_channels_no_temp[] = {
> - SUN4I_GPADC_ADC_CHANNEL(0, "adc_chan0"),
> - SUN4I_GPADC_ADC_CHANNEL(1, "adc_chan1"),
> - SUN4I_GPADC_ADC_CHANNEL(2, "adc_chan2"),
> - SUN4I_GPADC_ADC_CHANNEL(3, "adc_chan3"),
> -};
> -
> -static const struct iio_chan_spec sun8i_a33_gpadc_channels[] = {
> - {
> - .type = IIO_TEMP,
> - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
> - BIT(IIO_CHAN_INFO_SCALE) |
> - BIT(IIO_CHAN_INFO_OFFSET),
> - .datasheet_name = "temp_adc",
> - },
> -};
> -
> static const struct regmap_config sun4i_gpadc_regmap_config = {
> .reg_bits = 32,
> .val_bits = 32,
> @@ -444,8 +427,6 @@ static int sun4i_gpadc_probe_dt(struct platform_device
> *pdev,
> return -ENODEV;
>
> info->no_irq = true;
> - indio_dev->num_channels = ARRAY_SIZE(sun8i_a33_gpadc_channels);
> - indio_dev->channels = sun8i_a33_gpadc_channels;
>
> mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> base = devm_ioremap_resource(>dev, mem);
> --
> 2.11.0
>
> --
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Re: [linux-sunxi] [PATCH v3 30/30] ARM: sun8i: a83t: full range OPP tables and CPUfreq
Hello,
On Thu, Aug 30, 2018 at 05:45:18PM +0200, Philipp Rossak wrote:
> Since we have now thermal trotteling enabeled we can now add the full
> range of the OPP table.
I'm not sure we can. I have a tablet with A83T SoC and it gets unstable
at these frequencies even with thermal throttling on mainline kernel. (Though
I have my own THS driver, but I doubt a different driver will change much.)
There might be some other issue left in the cpufreq code. I'll let others
test this on a better cooled boards though.
Did you/someone test this?
regards,
o.
> The operating points were found in Allwinner BSP and fex files.
>
> Signed-off-by: Philipp Rossak
> ---
> arch/arm/boot/dts/sun8i-a83t.dtsi | 32
> 1 file changed, 32 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
> b/arch/arm/boot/dts/sun8i-a83t.dtsi
> index 78aa448e869f..ddcf404f9c80 100644
> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
> @@ -250,6 +250,22 @@
> opp-microvolt = <84>;
> clock-latency-ns = <244144>; /* 8 32k periods */
> };
> +
> + opp-160800 {
> + opp-hz = /bits/ 64 <160800>;
> + opp-microvolt = <92>;
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + };
> + opp-18 { /* BOOT FREQ */
> + opp-hz = /bits/ 64 <18>;
> + opp-microvolt = <100>;
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + };
> + opp-201600 {
> + opp-hz = /bits/ 64 <201600>;
> + opp-microvolt = <108>;
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + };
> };
>
> cpu1_opp_table: opp_table1 {
> @@ -303,6 +319,22 @@
> opp-microvolt = <84>;
> clock-latency-ns = <244144>; /* 8 32k periods */
> };
> +
> + opp-160800 {
> + opp-hz = /bits/ 64 <160800>;
> + opp-microvolt = <92>;
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + };
> + opp-18 { /* BOOT FREQ */
> + opp-hz = /bits/ 64 <18>;
> + opp-microvolt = <100>;
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + };
> + opp-201600 {
> + opp-hz = /bits/ 64 <201600>;
> + opp-microvolt = <108>;
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + };
> };
>
> soc {
> --
> 2.11.0
>
> --
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Re: [linux-sunxi] [PATCH v3 21/30] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor
Hello,
On Thu, Aug 30, 2018 at 05:45:09PM +0200, Philipp Rossak wrote:
> This patch adds support for the H3 ths sensor.
>
> The H3 supports interrupts. The interrupt is configured to update the
> the sensor values every second. The calibration data is writen at the
> begin of the init process.
>
> Signed-off-by: Philipp Rossak
> ---
> drivers/iio/adc/sun4i-gpadc-iio.c | 91
> +
> include/linux/iio/adc/sun4i-gpadc.h | 18
> 2 files changed, 109 insertions(+)
>
> diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
> b/drivers/iio/adc/sun4i-gpadc-iio.c
> index c7b46c82e3e5..d5c7971b2558 100644
> --- a/drivers/iio/adc/sun4i-gpadc-iio.c
> +++ b/drivers/iio/adc/sun4i-gpadc-iio.c
> @@ -72,6 +72,7 @@ struct gpadc_data {
> u32 temp_data_base;
> int sensor_count;
> boolsupports_nvmem;
> + u32 ths_irq_clear;
> };
>
> static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, void *dev_id);
> @@ -79,6 +80,10 @@ static irqreturn_t sun4i_gpadc_data_irq_handler(int irq,
> void *dev_id);
> static int sun4i_ths_resume(struct sun4i_gpadc_iio *info);
> static int sun4i_ths_suspend(struct sun4i_gpadc_iio *info);
>
> +static int sun8i_h3_ths_resume(struct sun4i_gpadc_iio *info);
> +static int sun8i_h3_ths_suspend(struct sun4i_gpadc_iio *info);
> +static irqreturn_t sunx8i_h3_irq_thread(int irq, void *data);
> +
> static const struct gpadc_data sun4i_gpadc_data = {
> .temp_offset = -1932,
> .temp_scale = 133,
> @@ -137,6 +142,22 @@ static const struct gpadc_data sun8i_a33_gpadc_data = {
> .sensor_count = 1,
> };
>
> +static const struct gpadc_data sun8i_h3_ths_data = {
> + .temp_offset = -1791,
> + .temp_scale = -121,
> + .temp_data_base = SUN8I_H3_THS_TDATA0,
> + .ths_irq_thread = sunx8i_h3_irq_thread,
> + .support_irq = true,
> + .has_bus_clk = true,
> + .has_bus_rst = true,
> + .has_mod_clk = true,
> + .sensor_count = 1,
> + .supports_nvmem = true,
> + .ths_resume = sun8i_h3_ths_resume,
> + .ths_suspend = sun8i_h3_ths_suspend,
> + .ths_irq_clear = SUN8I_H3_THS_INTS_TDATA_IRQ_0,
> +};
> +
> struct sun4i_sensor_tzd {
> struct sun4i_gpadc_iio *info;
> struct thermal_zone_device *tzd;
> @@ -409,6 +430,31 @@ static irqreturn_t sun4i_gpadc_data_irq_handler(int irq,
> void *dev_id)
> return IRQ_HANDLED;
> }
>
> +static irqreturn_t sunx8i_h3_irq_thread(int irq, void *data)
> +{
> + struct sun4i_gpadc_iio *info = data;
> + int i;
> +
> + regmap_write(info->regmap, SUN8I_H3_THS_STAT,
> + info->data->ths_irq_clear);
> +
> + for (i = 0; i < info->data->sensor_count; i++)
> + thermal_zone_device_update(info->tzds[i].tzd,
> + THERMAL_EVENT_TEMP_SAMPLE);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int sun8i_h3_calibrate(struct sun4i_gpadc_iio *info)
> +{
> +// regmap_write(info->regmap, SUNXI_THS_CDATA_0_1,
> +// info->calibration_data[0]);
> +// regmap_write(info->regmap, SUNXI_THS_CDATA_2_3,
> +// info->calibration_data[1]);
This should probably be implemented, or left out completely.
regards,
o.
> + return 0;
> +}
> +
> static int sun4i_gpadc_runtime_suspend(struct device *dev)
> {
> struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
> @@ -428,6 +474,16 @@ static int sun4i_ths_suspend(struct sun4i_gpadc_iio
> *info)
> return 0;
> }
>
> +static int sun8i_h3_ths_suspend(struct sun4i_gpadc_iio *info)
> +{
> + /* Disable ths interrupt */
> + regmap_write(info->regmap, SUN8I_H3_THS_INTC, 0x0);
> + /* Disable temperature sensor */
> + regmap_write(info->regmap, SUN8I_H3_THS_CTRL2, 0x0);
> +
> + return 0;
> +}
> +
> static int sun4i_gpadc_runtime_resume(struct device *dev)
> {
> struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
> @@ -454,6 +510,37 @@ static int sun4i_ths_resume(struct sun4i_gpadc_iio *info)
> return 0;
> }
>
> +static int sun8i_h3_ths_resume(struct sun4i_gpadc_iio *info)
> +{
> + u32 value;
> +
> + sun8i_h3_calibrate(info);
> +
> + regmap_write(info->regmap, SUN8I_H3_THS_CTRL0,
> + SUN4I_GPADC_CTRL0_T_ACQ(0xff));
> +
> + regmap_write(info->regmap, SUN8I_H3_THS_CTRL2,
> + SUN8I_H3_THS_ACQ1(0x3f));
> +
> + regmap_write(info->regmap, SUN8I_H3_THS_STAT,
> + SUN8I_H3_THS_INTS_TDATA_IRQ_0);
> +
> + regmap_write(info->regmap, SUN8I_H3_THS_FILTER,
> + SUN4I_GPADC_CTRL3_FILTER_EN |
> + SUN4I_GPADC_CTRL3_FILTER_TYPE(0x2));
> +
> + regmap_write(info->regmap, SUN8I_H3_THS_INTC,
> + SUN8I_H3_THS_INTC_TDATA_IRQ_EN0 |
> + SUN8I_H3_THS_TEMP_PERIOD(0x55));
> +
> + regmap_read(info->regmap, SUN8I_H3_THS_CTRL2, );
> +
[linux-sunxi] [PATCH v3 19/30] iio: adc: sun4i-gpadc-iio: rework: support nvmem calibration data
This patch reworks the driver to support nvmem calibration cells.
The driver checks if the nvmem calibration is supported and reads out
the nvmem.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 18ab72e52d78..2fd73d143815 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -27,6 +27,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -70,6 +71,7 @@ struct gpadc_data {
boolhas_mod_clk;
u32 temp_data_base;
int sensor_count;
+ boolsupports_nvmem;
};
static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, void *dev_id);
@@ -146,6 +148,7 @@ struct sun4i_gpadc_iio {
struct clk *bus_clk;
struct clk *mod_clk;
struct reset_control*reset;
+ u32 calibration_data[2];
};
static const struct iio_chan_spec sun4i_gpadc_channels[] = {
@@ -484,6 +487,9 @@ static int sun4i_gpadc_probe_dt(struct platform_device
*pdev,
struct resource *mem;
void __iomem *base;
int ret;
+ struct nvmem_cell *cell;
+ ssize_t cell_size;
+ u32 *cell_data;
info->data = of_device_get_match_data(>dev);
if (!info->data)
@@ -494,6 +500,24 @@ static int sun4i_gpadc_probe_dt(struct platform_device
*pdev,
if (IS_ERR(base))
return PTR_ERR(base);
+ if (info->data->supports_nvmem) {
+
+ cell = nvmem_cell_get(>dev, "calibration");
+ if (IS_ERR(cell)) {
+ if (PTR_ERR(cell) == -EPROBE_DEFER)
+ return PTR_ERR(cell);
+ } else {
+ cell_data = (u32 *)nvmem_cell_read(cell, _size);
+ if (cell_size != 8)
+ dev_err(>dev,
+ "Calibration data has wrong size\n");
+ else {
+ info->calibration_data[0] = cell_data[0];
+ info->calibration_data[1] = cell_data[1];
+ }
+ }
+ }
+
if (info->data->has_bus_clk)
info->regmap = devm_regmap_init_mmio_clk(>dev, "bus",
base, _gpadc_regmap_config);
--
2.11.0
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[linux-sunxi] [PATCH v3 25/30] ARM: dts: sun8i: h3: add thermal zone to H3
This patch adds the thermal zones to the H3. We have only one sensor and
that is placed in the cpu.
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sun8i-h3.dtsi| 31 +++
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 1 +
2 files changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 5b7994cb1471..954848d5df50 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -78,6 +78,8 @@
clock-names = "cpu";
operating-points-v2 = <_opp_table>;
#cooling-cells = <2>;
+ cooling-min-level = <0>;
+ cooling-max-level = <15>;
};
cpu@1 {
@@ -102,6 +104,35 @@
};
};
+ thermal-zones {
+ cpu-thermal {
+ /* milliseconds */
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <>;
+
+ trips {
+ cpu_hot_trip: cpu-warm {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_very_hot_trip: cpu-very-hot {
+ temperature = <9>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ cpu-warm-limit {
+ trip = <_hot_trip>;
+ cooling-device = <
THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = ,
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 3520e4ad6042..2c83f4893757 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -47,6 +47,7 @@
#include
#include
#include
+#include
/ {
interrupt-parent = <>;
--
2.11.0
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[linux-sunxi] [PATCH v3 24/30] ARM: dts: sun8i: h3: add support for the thermal sensor in H3
This patch adds the missing compatible and the thermal sensor cells.
The H3 has one sensor.
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sun8i-h3.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 41d57c76f290..5b7994cb1471 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -185,3 +185,8 @@
{
compatible = "allwinner,sun8i-h3-pinctrl";
};
+
+ {
+ compatible = "allwinner,sun8i-h3-ths";
+ #thermal-sensor-cells = <0>;
+};
--
2.11.0
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[linux-sunxi] [PATCH v3 27/30] ARM: dts: sun8i: h3: use calibration for ths
The H3 SID is supported by the kernel so we can add a NVMEM Data cell,
that contains the calibration data.
On the H3 the eFuses are located at the offset 0x200. The thermal data
itself has an offset of 0x34 from the eFuse base. So we end on an offset
of 0x234.
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sun8i-h3.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 1866aec69ec1..0fc447f0c02a 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -106,8 +106,15 @@
soc {
sid: eeprom@1c14000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "allwinner,sun8i-h3-sid";
reg = <0x01c14000 0x400>;
+
+ /* Data cells */
+ thermal_calibration: calib@234 {
+ reg = <0x234 0x8>;
+ };
};
};
@@ -227,4 +234,6 @@
{
compatible = "allwinner,sun8i-h3-ths";
#thermal-sensor-cells = <0>;
+ nvmem-cells = <_calibration>;
+ nvmem-cell-names = "calibration";
};
--
2.11.0
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[linux-sunxi] [PATCH v3 30/30] ARM: sun8i: a83t: full range OPP tables and CPUfreq
Since we have now thermal trotteling enabeled we can now add the full
range of the OPP table.
The operating points were found in Allwinner BSP and fex files.
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 78aa448e869f..ddcf404f9c80 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -250,6 +250,22 @@
opp-microvolt = <84>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
+
+ opp-160800 {
+ opp-hz = /bits/ 64 <160800>;
+ opp-microvolt = <92>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+ opp-18 { /* BOOT FREQ */
+ opp-hz = /bits/ 64 <18>;
+ opp-microvolt = <100>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+ opp-201600 {
+ opp-hz = /bits/ 64 <201600>;
+ opp-microvolt = <108>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
};
cpu1_opp_table: opp_table1 {
@@ -303,6 +319,22 @@
opp-microvolt = <84>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
+
+ opp-160800 {
+ opp-hz = /bits/ 64 <160800>;
+ opp-microvolt = <92>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+ opp-18 { /* BOOT FREQ */
+ opp-hz = /bits/ 64 <18>;
+ opp-microvolt = <100>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+ opp-201600 {
+ opp-hz = /bits/ 64 <201600>;
+ opp-microvolt = <108>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
};
soc {
--
2.11.0
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[linux-sunxi] [PATCH v3 29/30] ARM: dts: sun8i: a83t: add thermal zone to A83T
This patch adds the thermal zones to the A83T. Sensor 0 is located
besides the cpu cluster 0. Sensor 1 is located besides cluster 1 and
sensor 2 is located besides in the gpu.
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 103 ++
1 file changed, 103 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index f2f745930b08..78aa448e869f 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -50,6 +50,7 @@
#include
#include
#include
+#include
/ {
interrupt-parent = <>;
@@ -69,6 +70,9 @@
cci-control-port = <_control0>;
enable-method = "allwinner,sun8i-a83t-smp";
reg = <0>;
+ #cooling-cells = <2>;
+ cooling-min-level = <0>;
+ cooling-max-level = <7>;
};
cpu@1 {
@@ -107,6 +111,9 @@
cci-control-port = <_control1>;
enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x100>;
+ #cooling-cells = <2>;
+ cooling-min-level = <0>;
+ cooling-max-level = <7>;
};
cpu@101 {
@@ -1035,4 +1042,100 @@
#size-cells = <0>;
};
};
+
+ thermal-zones {
+ cpu0_thermal: cpu0-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = < 0>;
+
+ trips {
+ cpu0_warm: cpu_warm {
+ temperature = <7>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu0_hot: cpu_hot {
+ temperature = <8>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu0_very_hot: cpu_very_hot {
+ temperature = <9>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu0_crit: cpu_crit {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ cpu_warm_limit_cpu {
+ trip = <_warm>;
+ cooling-device = <
THERMAL_NO_LIMIT 4>;
+ };
+ cpu_hot_limit_cpu {
+ trip = <_hot>;
+ cooling-device = < 5 5>;
+ };
+ cpu_very_hot_limit_cpu {
+ trip = <_very_hot>;
+ cooling-device = < 7
THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu1_thermal: cpu1-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = < 1>;
+
+ trips {
+ cpu1_warm: cpu_warm {
+ temperature = <7>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu1_hot: cpu_hot {
+ temperature = <8>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu1_very_hot: cpu_very_hot {
+ temperature = <9>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu1_crit: cpu_crit {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+
[linux-sunxi] [PATCH v3 28/30] ARM: dts: sun8i: a83t: add support for the thermal sensor in A83T
As we have gained the support for the thermal sensor in A83T,
we can now add its device nodes to the device tree.
The A83T seems to have a broken IRQ 31, thus we use here IRQ 41.
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 2be23d600957..f2f745930b08 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -757,6 +757,14 @@
clocks = <>;
};
+ ths: thermal-sensor@1f04000 {
+ compatible = "allwinner,sun8i-a83t-ths";
+ reg = <0x01f04000 0x100>;
+ interrupts = ;
+ #thermal-sensor-cells = <1>;
+ #io-channel-cells = <0>;
+ };
+
watchdog@1c20ca0 {
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
--
2.11.0
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[linux-sunxi] [PATCH v3 26/30] ARM: dts: sun8i: h3: enable H3 sid controller
This patch enables the the sid controller in the H3. It can be used
for thermal calibration data.
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 954848d5df50..1866aec69ec1 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -104,6 +104,13 @@
};
};
+ soc {
+ sid: eeprom@1c14000 {
+ compatible = "allwinner,sun8i-h3-sid";
+ reg = <0x01c14000 0x400>;
+ };
+ };
+
thermal-zones {
cpu-thermal {
/* milliseconds */
--
2.11.0
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[linux-sunxi] [PATCH v3 22/30] iio: adc: sun4i-gpadc-iio: add support for A83T thermal sensor
This patch adds support for the A83T ths sensor.
The A83T supports interrupts. The interrupt is configured to update the
the sensor values every second.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 59 +
include/linux/iio/adc/sun4i-gpadc.h | 6
2 files changed, 65 insertions(+)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index d5c7971b2558..a184a87c56d4 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -84,6 +84,8 @@ static int sun8i_h3_ths_resume(struct sun4i_gpadc_iio *info);
static int sun8i_h3_ths_suspend(struct sun4i_gpadc_iio *info);
static irqreturn_t sunx8i_h3_irq_thread(int irq, void *data);
+static int sun8i_a83t_ths_resume(struct sun4i_gpadc_iio *info);
+
static const struct gpadc_data sun4i_gpadc_data = {
.temp_offset = -1932,
.temp_scale = 133,
@@ -158,6 +160,21 @@ static const struct gpadc_data sun8i_h3_ths_data = {
.ths_irq_clear = SUN8I_H3_THS_INTS_TDATA_IRQ_0,
};
+static const struct gpadc_data sun8i_a83t_ths_data = {
+ .temp_offset = -2724,
+ .temp_scale = -70,
+ .temp_data_base = SUN8I_H3_THS_TDATA0,
+ .ths_irq_thread = sunx8i_h3_irq_thread,
+ .support_irq = true,
+ .sensor_count = 3,
+ .supports_nvmem = true,
+ .ths_resume = sun8i_a83t_ths_resume,
+ .ths_suspend = sun8i_h3_ths_suspend,
+ .ths_irq_clear = SUN8I_H3_THS_INTS_TDATA_IRQ_0 |
+ SUN8I_A83T_THS_INTS_TDATA_IRQ_1 |
+ SUN8I_A83T_THS_INTS_TDATA_IRQ_2,
+};
+
struct sun4i_sensor_tzd {
struct sun4i_gpadc_iio *info;
struct thermal_zone_device *tzd;
@@ -541,6 +558,44 @@ static int sun8i_h3_ths_resume(struct sun4i_gpadc_iio
*info)
return 0;
}
+static int sun8i_a83t_ths_resume(struct sun4i_gpadc_iio *info)
+{
+ u32 value;
+
+ sun8i_h3_calibrate(info);
+
+ regmap_write(info->regmap, SUN8I_H3_THS_CTRL0,
+ SUN4I_GPADC_CTRL0_T_ACQ(0x13f));
+
+ regmap_write(info->regmap, SUN8I_H3_THS_CTRL2,
+ SUN8I_H3_THS_ACQ1(0x13f));
+
+ regmap_write(info->regmap, SUN8I_H3_THS_STAT,
+ SUN8I_H3_THS_INTS_TDATA_IRQ_0 |
+ SUN8I_A83T_THS_INTS_TDATA_IRQ_1 |
+ SUN8I_A83T_THS_INTS_TDATA_IRQ_2);
+
+ regmap_write(info->regmap, SUN8I_H3_THS_FILTER,
+ SUN4I_GPADC_CTRL3_FILTER_EN |
+ SUN4I_GPADC_CTRL3_FILTER_TYPE(0x2));
+
+ regmap_write(info->regmap, SUN8I_H3_THS_INTC,
+ SUN8I_H3_THS_INTC_TDATA_IRQ_EN0 |
+ SUN8I_A83T_THS_INTC_TDATA_IRQ_EN1 |
+ SUN8I_A83T_THS_INTC_TDATA_IRQ_EN2 |
+ SUN8I_H3_THS_TEMP_PERIOD(0x257));
+
+ regmap_read(info->regmap, SUN8I_H3_THS_CTRL2, );
+
+ regmap_write(info->regmap, SUN8I_H3_THS_CTRL2,
+ SUN8I_H3_THS_TEMP_SENSE_EN0 |
+ SUN8I_A83T_THS_TEMP_SENSE_EN1 |
+ SUN8I_A83T_THS_TEMP_SENSE_EN2 |
+ value);
+
+ return 0;
+}
+
static int sun4i_gpadc_get_temp(void *data, int *temp)
{
struct sun4i_sensor_tzd *tzd = data;
@@ -588,6 +643,10 @@ static const struct of_device_id sun4i_gpadc_of_id[] = {
.compatible = "allwinner,sun8i-h3-ths",
.data = _h3_ths_data,
},
+ {
+ .compatible = "allwinner,sun8i-a83t-ths",
+ .data = _a83t_ths_data,
+ },
{ /* sentinel */ }
};
diff --git a/include/linux/iio/adc/sun4i-gpadc.h
b/include/linux/iio/adc/sun4i-gpadc.h
index 169b4de9a34d..673459bb3ec3 100644
--- a/include/linux/iio/adc/sun4i-gpadc.h
+++ b/include/linux/iio/adc/sun4i-gpadc.h
@@ -105,13 +105,19 @@
#define SUN8I_H3_THS_CTRL2 0x40
#define SUN8I_H3_THS_ACQ1(x) (GENMASK(31, 16) & ((x) << 16))
#define SUN8I_H3_THS_TEMP_SENSE_EN0BIT(0)
+#define SUN8I_A83T_THS_TEMP_SENSE_EN1 BIT(1)
+#define SUN8I_A83T_THS_TEMP_SENSE_EN2 BIT(2)
#define SUN8I_H3_THS_INTC 0x44
#define SUN8I_H3_THS_TEMP_PERIOD(x)(GENMASK(31, 12) & ((x) << 12))
#define SUN8I_H3_THS_INTC_TDATA_IRQ_EN0BIT(8)
+#define SUN8I_A83T_THS_INTC_TDATA_IRQ_EN1 BIT(9)
+#define SUN8I_A83T_THS_INTC_TDATA_IRQ_EN2 BIT(10)
#define SUN8I_H3_THS_STAT 0x48
#define SUN8I_H3_THS_INTS_TDATA_IRQ_0 BIT(8)
+#define SUN8I_A83T_THS_INTS_TDATA_IRQ_1BIT(9)
+#define SUN8I_A83T_THS_INTS_TDATA_IRQ_2BIT(10)
#define SUN8I_H3_THS_FILTER0x70
#define SUNXI_THS_CDATA_0_10x74
--
2.11.0
[linux-sunxi] [PATCH v3 20/30] iio: adc: sun4i-gpadc-iio: rework: device specific suspend & resume
Different sensors will have different suspend and resume functions. So
we are modularize the suspend and resume functions.
The resume function configures and initializes the thermal sensor and
the suspend function disables the sensors.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 2fd73d143815..c7b46c82e3e5 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -76,6 +76,9 @@ struct gpadc_data {
static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, void *dev_id);
+static int sun4i_ths_resume(struct sun4i_gpadc_iio *info);
+static int sun4i_ths_suspend(struct sun4i_gpadc_iio *info);
+
static const struct gpadc_data sun4i_gpadc_data = {
.temp_offset = -1932,
.temp_scale = 133,
@@ -87,6 +90,8 @@ static const struct gpadc_data sun4i_gpadc_data = {
.ths_irq_thread = sun4i_gpadc_data_irq_handler,
.support_irq = true,
.temp_data_base = SUN4I_GPADC_TEMP_DATA,
+ .ths_resume = sun4i_ths_resume,
+ .ths_suspend = sun4i_ths_suspend,
.sensor_count = 1,
};
@@ -101,6 +106,8 @@ static const struct gpadc_data sun5i_gpadc_data = {
.ths_irq_thread = sun4i_gpadc_data_irq_handler,
.support_irq = true,
.temp_data_base = SUN4I_GPADC_TEMP_DATA,
+ .ths_resume = sun4i_ths_resume,
+ .ths_suspend = sun4i_ths_suspend,
.sensor_count = 1,
};
@@ -115,6 +122,8 @@ static const struct gpadc_data sun6i_gpadc_data = {
.ths_irq_thread = sun4i_gpadc_data_irq_handler,
.support_irq = true,
.temp_data_base = SUN4I_GPADC_TEMP_DATA,
+ .ths_resume = sun4i_ths_resume,
+ .ths_suspend = sun4i_ths_suspend,
.sensor_count = 1,
};
@@ -123,6 +132,8 @@ static const struct gpadc_data sun8i_a33_gpadc_data = {
.temp_scale = 162,
.tp_mode_en = SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN,
.temp_data_base = SUN4I_GPADC_TEMP_DATA,
+ .ths_resume = sun4i_ths_resume,
+ .ths_suspend = sun4i_ths_suspend,
.sensor_count = 1,
};
@@ -401,6 +412,11 @@ static irqreturn_t sun4i_gpadc_data_irq_handler(int irq,
void *dev_id)
static int sun4i_gpadc_runtime_suspend(struct device *dev)
{
struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
+ return info->data->ths_suspend(info);
+}
+
+static int sun4i_ths_suspend(struct sun4i_gpadc_iio *info)
+{
/* Disable the ADC on IP */
regmap_write(info->regmap, SUN4I_GPADC_CTRL1, 0);
@@ -415,7 +431,11 @@ static int sun4i_gpadc_runtime_suspend(struct device *dev)
static int sun4i_gpadc_runtime_resume(struct device *dev)
{
struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
+ return info->data->ths_resume(info);
+}
+static int sun4i_ths_resume(struct sun4i_gpadc_iio *info)
+{
/* clkin = 6MHz */
regmap_write(info->regmap, SUN4I_GPADC_CTRL0,
SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(2) |
--
2.11.0
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[linux-sunxi] [PATCH v3 21/30] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor
This patch adds support for the H3 ths sensor.
The H3 supports interrupts. The interrupt is configured to update the
the sensor values every second. The calibration data is writen at the
begin of the init process.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 91 +
include/linux/iio/adc/sun4i-gpadc.h | 18
2 files changed, 109 insertions(+)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index c7b46c82e3e5..d5c7971b2558 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -72,6 +72,7 @@ struct gpadc_data {
u32 temp_data_base;
int sensor_count;
boolsupports_nvmem;
+ u32 ths_irq_clear;
};
static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, void *dev_id);
@@ -79,6 +80,10 @@ static irqreturn_t sun4i_gpadc_data_irq_handler(int irq,
void *dev_id);
static int sun4i_ths_resume(struct sun4i_gpadc_iio *info);
static int sun4i_ths_suspend(struct sun4i_gpadc_iio *info);
+static int sun8i_h3_ths_resume(struct sun4i_gpadc_iio *info);
+static int sun8i_h3_ths_suspend(struct sun4i_gpadc_iio *info);
+static irqreturn_t sunx8i_h3_irq_thread(int irq, void *data);
+
static const struct gpadc_data sun4i_gpadc_data = {
.temp_offset = -1932,
.temp_scale = 133,
@@ -137,6 +142,22 @@ static const struct gpadc_data sun8i_a33_gpadc_data = {
.sensor_count = 1,
};
+static const struct gpadc_data sun8i_h3_ths_data = {
+ .temp_offset = -1791,
+ .temp_scale = -121,
+ .temp_data_base = SUN8I_H3_THS_TDATA0,
+ .ths_irq_thread = sunx8i_h3_irq_thread,
+ .support_irq = true,
+ .has_bus_clk = true,
+ .has_bus_rst = true,
+ .has_mod_clk = true,
+ .sensor_count = 1,
+ .supports_nvmem = true,
+ .ths_resume = sun8i_h3_ths_resume,
+ .ths_suspend = sun8i_h3_ths_suspend,
+ .ths_irq_clear = SUN8I_H3_THS_INTS_TDATA_IRQ_0,
+};
+
struct sun4i_sensor_tzd {
struct sun4i_gpadc_iio *info;
struct thermal_zone_device *tzd;
@@ -409,6 +430,31 @@ static irqreturn_t sun4i_gpadc_data_irq_handler(int irq,
void *dev_id)
return IRQ_HANDLED;
}
+static irqreturn_t sunx8i_h3_irq_thread(int irq, void *data)
+{
+ struct sun4i_gpadc_iio *info = data;
+ int i;
+
+ regmap_write(info->regmap, SUN8I_H3_THS_STAT,
+ info->data->ths_irq_clear);
+
+ for (i = 0; i < info->data->sensor_count; i++)
+ thermal_zone_device_update(info->tzds[i].tzd,
+ THERMAL_EVENT_TEMP_SAMPLE);
+
+ return IRQ_HANDLED;
+}
+
+static int sun8i_h3_calibrate(struct sun4i_gpadc_iio *info)
+{
+// regmap_write(info->regmap, SUNXI_THS_CDATA_0_1,
+// info->calibration_data[0]);
+// regmap_write(info->regmap, SUNXI_THS_CDATA_2_3,
+// info->calibration_data[1]);
+
+ return 0;
+}
+
static int sun4i_gpadc_runtime_suspend(struct device *dev)
{
struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
@@ -428,6 +474,16 @@ static int sun4i_ths_suspend(struct sun4i_gpadc_iio *info)
return 0;
}
+static int sun8i_h3_ths_suspend(struct sun4i_gpadc_iio *info)
+{
+ /* Disable ths interrupt */
+ regmap_write(info->regmap, SUN8I_H3_THS_INTC, 0x0);
+ /* Disable temperature sensor */
+ regmap_write(info->regmap, SUN8I_H3_THS_CTRL2, 0x0);
+
+ return 0;
+}
+
static int sun4i_gpadc_runtime_resume(struct device *dev)
{
struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
@@ -454,6 +510,37 @@ static int sun4i_ths_resume(struct sun4i_gpadc_iio *info)
return 0;
}
+static int sun8i_h3_ths_resume(struct sun4i_gpadc_iio *info)
+{
+ u32 value;
+
+ sun8i_h3_calibrate(info);
+
+ regmap_write(info->regmap, SUN8I_H3_THS_CTRL0,
+ SUN4I_GPADC_CTRL0_T_ACQ(0xff));
+
+ regmap_write(info->regmap, SUN8I_H3_THS_CTRL2,
+ SUN8I_H3_THS_ACQ1(0x3f));
+
+ regmap_write(info->regmap, SUN8I_H3_THS_STAT,
+ SUN8I_H3_THS_INTS_TDATA_IRQ_0);
+
+ regmap_write(info->regmap, SUN8I_H3_THS_FILTER,
+ SUN4I_GPADC_CTRL3_FILTER_EN |
+ SUN4I_GPADC_CTRL3_FILTER_TYPE(0x2));
+
+ regmap_write(info->regmap, SUN8I_H3_THS_INTC,
+ SUN8I_H3_THS_INTC_TDATA_IRQ_EN0 |
+ SUN8I_H3_THS_TEMP_PERIOD(0x55));
+
+ regmap_read(info->regmap, SUN8I_H3_THS_CTRL2, );
+
+ regmap_write(info->regmap, SUN8I_H3_THS_CTRL2,
+ SUN8I_H3_THS_TEMP_SENSE_EN0 | value);
+
+ return 0;
+}
+
static int sun4i_gpadc_get_temp(void *data, int *temp)
{
struct sun4i_sensor_tzd *tzd = data;
@@ -497,6 +584,10 @@ static const struct of_device_id
[linux-sunxi] [PATCH v3 23/30] ARM: dts: sunxi-h3-h5: add support for the thermal sensor in H3 and H5
As we have gained the support for the thermal sensor in H3 and H5,
we can now add its device nodes to the device tree. The H3 and H5 share
most of its compatible. The compatible and the thermal sensor cells
will be added in an additional patch per device.
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index c3bff1105e5d..3520e4ad6042 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -488,6 +488,15 @@
};
};
+ ths: thermal-sensor@1c25000 {
+ reg = <0x01c25000 0x400>;
+ interrupts = ;
+ clocks = < CLK_BUS_THS>, < CLK_THS>;
+ clock-names = "bus", "mod";
+ resets = < RST_BUS_THS>;
+ #io-channel-cells = <0>;
+ };
+
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0xa0>;
--
2.11.0
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[linux-sunxi] [PATCH v3 18/30] iio: adc: sun4i-gpadc-iio: rework: support multiple sensors
For adding newer sensor some basic rework of the code is necessary.
This patch reworks the driver to be able to handle more than one
thermal sensor. Newer SoC like the A80 have 4 thermal sensors.
Because of this the maximal sensor count value was set to 4.
The sensor_id value is set during sensor registration and is for each
registered sensor indiviual. This makes it able to differntiate the
sensors when the value is read from the register.
In function sun4i_gpadc_read_raw(), the sensor number of the ths sensor
was directly set to 0 (sun4i_gpadc_temp_read(x,x,0)). This selects
in the temp_read function automatically sensor 0. A check for the
sensor_id is here not required since the old sensors only have one
thermal sensor. In addition to that is the sun4i_gpadc_read_raw()
function only used by the "older" sensors (before A33) where the
thermal sensor was a cobination of an adc and a thermal sensor.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 63 +
include/linux/iio/adc/sun4i-gpadc.h | 3 ++
2 files changed, 46 insertions(+), 20 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index c12de48c4e86..18ab72e52d78 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -69,6 +69,7 @@ struct gpadc_data {
boolhas_bus_rst;
boolhas_mod_clk;
u32 temp_data_base;
+ int sensor_count;
};
static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, void *dev_id);
@@ -84,6 +85,7 @@ static const struct gpadc_data sun4i_gpadc_data = {
.ths_irq_thread = sun4i_gpadc_data_irq_handler,
.support_irq = true,
.temp_data_base = SUN4I_GPADC_TEMP_DATA,
+ .sensor_count = 1,
};
static const struct gpadc_data sun5i_gpadc_data = {
@@ -97,6 +99,7 @@ static const struct gpadc_data sun5i_gpadc_data = {
.ths_irq_thread = sun4i_gpadc_data_irq_handler,
.support_irq = true,
.temp_data_base = SUN4I_GPADC_TEMP_DATA,
+ .sensor_count = 1,
};
static const struct gpadc_data sun6i_gpadc_data = {
@@ -110,6 +113,7 @@ static const struct gpadc_data sun6i_gpadc_data = {
.ths_irq_thread = sun4i_gpadc_data_irq_handler,
.support_irq = true,
.temp_data_base = SUN4I_GPADC_TEMP_DATA,
+ .sensor_count = 1,
};
static const struct gpadc_data sun8i_a33_gpadc_data = {
@@ -117,6 +121,13 @@ static const struct gpadc_data sun8i_a33_gpadc_data = {
.temp_scale = 162,
.tp_mode_en = SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN,
.temp_data_base = SUN4I_GPADC_TEMP_DATA,
+ .sensor_count = 1,
+};
+
+struct sun4i_sensor_tzd {
+ struct sun4i_gpadc_iio *info;
+ struct thermal_zone_device *tzd;
+ unsigned intsensor_id;
};
struct sun4i_gpadc_iio {
@@ -130,7 +141,7 @@ struct sun4i_gpadc_iio {
const struct gpadc_data *data;
/* prevents concurrent reads of temperature and ADC */
struct mutexmutex;
- struct thermal_zone_device *tzd;
+ struct sun4i_sensor_tzd tzds[MAX_SENSOR_COUNT];
struct device *sensor_device;
struct clk *bus_clk;
struct clk *mod_clk;
@@ -280,7 +291,8 @@ static int sun4i_gpadc_adc_read(struct iio_dev *indio_dev,
int channel,
SUN4I_GPADC_IRQ_FIFO_DATA);
}
-static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, int *val)
+static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, int *val,
+ int sensor)
{
struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
@@ -290,7 +302,8 @@ static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev,
int *val)
pm_runtime_get_sync(indio_dev->dev.parent);
- regmap_read(info->regmap, info->data->temp_data_base, val);
+ regmap_read(info->regmap, info->data->temp_data_base + 0x4 * sensor,
+ val);
pm_runtime_mark_last_busy(indio_dev->dev.parent);
pm_runtime_put_autosuspend(indio_dev->dev.parent);
@@ -334,7 +347,7 @@ static int sun4i_gpadc_read_raw(struct iio_dev *indio_dev,
ret = sun4i_gpadc_adc_read(indio_dev, chan->channel,
val);
else
- ret = sun4i_gpadc_temp_read(indio_dev, val);
+ ret = sun4i_gpadc_temp_read(indio_dev, val, 0);
if (ret)
return ret;
@@ -420,10 +433,11 @@ static int sun4i_gpadc_runtime_resume(struct device *dev)
static int sun4i_gpadc_get_temp(void *data, int *temp)
{
- struct sun4i_gpadc_iio *info = data;
+ struct sun4i_sensor_tzd *tzd = data;
+ struct sun4i_gpadc_iio *info = tzd->info;
int val, scale, offset;
- if
[linux-sunxi] [PATCH v3 17/30] iio: adc: sun4i-gpadc-iio: rework: support clocks and reset
For adding newer sensor some basic rework of the code is necessary.
The SoCs after H3 has newer thermal sensor ADCs, which have two clock
inputs (bus clock and sampling clock) and a reset. The registers are
also re-arranged.
This commit reworks the code, adds the process of the clocks and resets.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 72 +--
1 file changed, 70 insertions(+), 2 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index c278e165e161..c12de48c4e86 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -22,6 +22,7 @@
* shutdown for not being used.
*/
+#include
#include
#include
#include
@@ -31,6 +32,7 @@
#include
#include
#include
+#include
#include
#include
@@ -63,6 +65,9 @@ struct gpadc_data {
int (*ths_suspend)(struct sun4i_gpadc_iio *info);
int (*ths_resume)(struct sun4i_gpadc_iio *info);
boolsupport_irq;
+ boolhas_bus_clk;
+ boolhas_bus_rst;
+ boolhas_mod_clk;
u32 temp_data_base;
};
@@ -127,6 +132,9 @@ struct sun4i_gpadc_iio {
struct mutexmutex;
struct thermal_zone_device *tzd;
struct device *sensor_device;
+ struct clk *bus_clk;
+ struct clk *mod_clk;
+ struct reset_control*reset;
};
static const struct iio_chan_spec sun4i_gpadc_channels[] = {
@@ -472,8 +480,13 @@ static int sun4i_gpadc_probe_dt(struct platform_device
*pdev,
if (IS_ERR(base))
return PTR_ERR(base);
- info->regmap = devm_regmap_init_mmio(>dev, base,
-_gpadc_regmap_config);
+ if (info->data->has_bus_clk)
+ info->regmap = devm_regmap_init_mmio_clk(>dev, "bus",
+ base, _gpadc_regmap_config);
+ else
+ info->regmap = devm_regmap_init_mmio(>dev, base,
+ _gpadc_regmap_config);
+
if (IS_ERR(info->regmap)) {
ret = PTR_ERR(info->regmap);
dev_err(>dev, "failed to init regmap: %d\n", ret);
@@ -498,9 +511,58 @@ static int sun4i_gpadc_probe_dt(struct platform_device
*pdev,
}
}
+ if (info->data->has_bus_rst) {
+ info->reset = devm_reset_control_get(>dev, NULL);
+ if (IS_ERR(info->reset)) {
+ ret = PTR_ERR(info->reset);
+ return ret;
+ }
+
+ ret = reset_control_deassert(info->reset);
+ if (ret)
+ return ret;
+ }
+
+ if (info->data->has_bus_clk) {
+ info->bus_clk = devm_clk_get(>dev, "bus");
+ if (IS_ERR(info->bus_clk)) {
+ ret = PTR_ERR(info->bus_clk);
+ goto assert_reset;
+ }
+
+ ret = clk_prepare_enable(info->bus_clk);
+ if (ret)
+ goto assert_reset;
+ }
+
+ if (info->data->has_mod_clk) {
+ info->mod_clk = devm_clk_get(>dev, "mod");
+ if (IS_ERR(info->mod_clk)) {
+ ret = PTR_ERR(info->mod_clk);
+ goto disable_bus_clk;
+ }
+
+ /* Running at 4MHz */
+ ret = clk_set_rate(info->mod_clk, 400);
+ if (ret)
+ goto disable_bus_clk;
+
+ ret = clk_prepare_enable(info->mod_clk);
+ if (ret)
+ goto disable_bus_clk;
+ }
+
info->sensor_device = >dev;
return 0;
+
+disable_bus_clk:
+ clk_disable_unprepare(info->bus_clk);
+
+assert_reset:
+ reset_control_assert(info->reset);
+
+ return ret;
}
static int sun4i_gpadc_probe(struct platform_device *pdev)
@@ -586,6 +648,12 @@ static int sun4i_gpadc_remove(struct platform_device *pdev)
if (!info->data->support_irq)
iio_map_array_unregister(indio_dev);
+ clk_disable_unprepare(info->mod_clk);
+
+ clk_disable_unprepare(info->bus_clk);
+
+ reset_control_assert(info->reset);
+
return 0;
}
--
2.11.0
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[linux-sunxi] [PATCH v3 12/30] mfd: Remove old mfd driver & Move sun4i-gpadc.h to iio/adc/
Since we reworked the sun4i-gpadc iio driver we can now remove the mfd
driver and move it's header to include/linux/iio/adc.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c| 2 +-
drivers/mfd/sun4i-gpadc.c| 181 ---
include/linux/{mfd => iio/adc}/sun4i-gpadc.h | 0
3 files changed, 1 insertion(+), 182 deletions(-)
delete mode 100644 drivers/mfd/sun4i-gpadc.c
rename include/linux/{mfd => iio/adc}/sun4i-gpadc.h (100%)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 79b8efdab803..e1fe5e8e9dc0 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -37,7 +37,7 @@
#include
#include
#include
-#include
+#include
static unsigned int sun4i_gpadc_chan_select(unsigned int chan)
{
diff --git a/drivers/mfd/sun4i-gpadc.c b/drivers/mfd/sun4i-gpadc.c
deleted file mode 100644
index 9cfc88134d03..
--- a/drivers/mfd/sun4i-gpadc.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/* ADC MFD core driver for sunxi platforms
- *
- * Copyright (c) 2016 Quentin Schulz
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include
-
-#define ARCH_SUN4I_A10 0
-#define ARCH_SUN5I_A13 1
-#define ARCH_SUN6I_A31 2
-
-static struct resource adc_resources[] = {
- DEFINE_RES_IRQ_NAMED(SUN4I_GPADC_IRQ_FIFO_DATA, "FIFO_DATA_PENDING"),
- DEFINE_RES_IRQ_NAMED(SUN4I_GPADC_IRQ_TEMP_DATA, "TEMP_DATA_PENDING"),
-};
-
-static const struct regmap_irq sun4i_gpadc_regmap_irq[] = {
- REGMAP_IRQ_REG(SUN4I_GPADC_IRQ_FIFO_DATA, 0,
- SUN4I_GPADC_INT_FIFOC_TP_DATA_IRQ_EN),
- REGMAP_IRQ_REG(SUN4I_GPADC_IRQ_TEMP_DATA, 0,
- SUN4I_GPADC_INT_FIFOC_TEMP_IRQ_EN),
-};
-
-static const struct regmap_irq_chip sun4i_gpadc_regmap_irq_chip = {
- .name = "sun4i_gpadc_irq_chip",
- .status_base = SUN4I_GPADC_INT_FIFOS,
- .ack_base = SUN4I_GPADC_INT_FIFOS,
- .mask_base = SUN4I_GPADC_INT_FIFOC,
- .init_ack_masked = true,
- .mask_invert = true,
- .irqs = sun4i_gpadc_regmap_irq,
- .num_irqs = ARRAY_SIZE(sun4i_gpadc_regmap_irq),
- .num_regs = 1,
-};
-
-static struct mfd_cell sun4i_gpadc_cells[] = {
- {
- .name = "sun4i-a10-gpadc-iio",
- .resources = adc_resources,
- .num_resources = ARRAY_SIZE(adc_resources),
- },
- { .name = "iio_hwmon" }
-};
-
-static struct mfd_cell sun5i_gpadc_cells[] = {
- {
- .name = "sun5i-a13-gpadc-iio",
- .resources = adc_resources,
- .num_resources = ARRAY_SIZE(adc_resources),
- },
- { .name = "iio_hwmon" },
-};
-
-static struct mfd_cell sun6i_gpadc_cells[] = {
- {
- .name = "sun6i-a31-gpadc-iio",
- .resources = adc_resources,
- .num_resources = ARRAY_SIZE(adc_resources),
- },
- { .name = "iio_hwmon" },
-};
-
-static const struct regmap_config sun4i_gpadc_regmap_config = {
- .reg_bits = 32,
- .val_bits = 32,
- .reg_stride = 4,
- .fast_io = true,
-};
-
-static const struct of_device_id sun4i_gpadc_of_match[] = {
- {
- .compatible = "allwinner,sun4i-a10-ts",
- .data = (void *)ARCH_SUN4I_A10,
- }, {
- .compatible = "allwinner,sun5i-a13-ts",
- .data = (void *)ARCH_SUN5I_A13,
- }, {
- .compatible = "allwinner,sun6i-a31-ts",
- .data = (void *)ARCH_SUN6I_A31,
- }, { /* sentinel */ }
-};
-
-MODULE_DEVICE_TABLE(of, sun4i_gpadc_of_match);
-
-static int sun4i_gpadc_probe(struct platform_device *pdev)
-{
- struct sun4i_gpadc_dev *dev;
- struct resource *mem;
- const struct of_device_id *of_id;
- const struct mfd_cell *cells;
- unsigned int irq, size;
- int ret;
-
- of_id = of_match_node(sun4i_gpadc_of_match, pdev->dev.of_node);
- if (!of_id)
- return -EINVAL;
-
- switch ((long)of_id->data) {
- case ARCH_SUN4I_A10:
- cells = sun4i_gpadc_cells;
- size = ARRAY_SIZE(sun4i_gpadc_cells);
- break;
- case ARCH_SUN5I_A13:
- cells = sun5i_gpadc_cells;
- size = ARRAY_SIZE(sun5i_gpadc_cells);
- break;
- case ARCH_SUN6I_A31:
- cells = sun6i_gpadc_cells;
- size = ARRAY_SIZE(sun6i_gpadc_cells);
- break;
- default:
- return -EINVAL;
- }
-
- dev = devm_kzalloc(>dev, sizeof(*dev), GFP_KERNEL);
- if (!dev)
- return -ENOMEM;
-
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-
[linux-sunxi] [PATCH v3 03/30] iio: adc: Remove ID table
To disable the driver we are removing the compatibles.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 04d7147e0110..d95dd0fde2a6 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -698,21 +698,12 @@ static int sun4i_gpadc_remove(struct platform_device
*pdev)
return 0;
}
-static const struct platform_device_id sun4i_gpadc_id[] = {
- { "sun4i-a10-gpadc-iio", (kernel_ulong_t)_gpadc_data },
- { "sun5i-a13-gpadc-iio", (kernel_ulong_t)_gpadc_data },
- { "sun6i-a31-gpadc-iio", (kernel_ulong_t)_gpadc_data },
- { /* sentinel */ },
-};
-MODULE_DEVICE_TABLE(platform, sun4i_gpadc_id);
-
static struct platform_driver sun4i_gpadc_driver = {
.driver = {
.name = "sun4i-gpadc-iio",
.of_match_table = sun4i_gpadc_of_id,
.pm = _gpadc_pm_ops,
},
- .id_table = sun4i_gpadc_id,
.probe = sun4i_gpadc_probe,
.remove = sun4i_gpadc_remove,
};
--
2.11.0
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[linux-sunxi] [PATCH v3 15/30] iio: adc: sun4i-gpadc-iio: rename A33-specified registers to contain A33
From: Icenowy Zheng
As the H3 SoC, which is also in sun8i line, has totally different
register map for the thermal sensor (a cut down version of GPADC), we
should rename A23/A33-specified registers to contain A33, in order to
prevent obfuscation with H3 registers. Currently these registers are
only prefixed "SUN8I", not "SUN8I_A33".
Add "_A33" after "SUN8I" on the register names.
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
Acked-by: Lee Jones
Acked-by: Jonathan Cameron
---
drivers/iio/adc/sun4i-gpadc-iio.c | 2 +-
include/linux/iio/adc/sun4i-gpadc.h | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index e1fe5e8e9dc0..d48f338af563 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -106,7 +106,7 @@ static const struct gpadc_data sun6i_gpadc_data = {
static const struct gpadc_data sun8i_a33_gpadc_data = {
.temp_offset = -1662,
.temp_scale = 162,
- .tp_mode_en = SUN8I_GPADC_CTRL1_CHOP_TEMP_EN,
+ .tp_mode_en = SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN,
};
struct sun4i_gpadc_iio {
diff --git a/include/linux/iio/adc/sun4i-gpadc.h
b/include/linux/iio/adc/sun4i-gpadc.h
index ca59336f246b..d6850f39dcfb 100644
--- a/include/linux/iio/adc/sun4i-gpadc.h
+++ b/include/linux/iio/adc/sun4i-gpadc.h
@@ -38,9 +38,9 @@
#define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(3, 0) & BIT(x))
#define SUN6I_GPADC_CTRL1_ADC_CHAN_MASKGENMASK(3, 0)
-/* TP_CTRL1 bits for sun8i SoCs */
-#define SUN8I_GPADC_CTRL1_CHOP_TEMP_EN BIT(8)
-#define SUN8I_GPADC_CTRL1_GPADC_CALI_ENBIT(7)
+/* TP_CTRL1 bits for A33 */
+#define SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN BIT(8)
+#define SUN8I_A33_GPADC_CTRL1_GPADC_CALI_ENBIT(7)
#define SUN4I_GPADC_CTRL2 0x08
--
2.11.0
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[linux-sunxi] [PATCH v3 07/30] iio: adc: remove mfd_probe & sunwi_irq_init function
In the previous commit we removed the function call, now we remove the
unused functions.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 126 --
1 file changed, 126 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index d6f00d3b802d..f787442a9e5f 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -431,55 +431,6 @@ static const struct dev_pm_ops sun4i_gpadc_pm_ops = {
.runtime_resume = _gpadc_runtime_resume,
};
-static int sun4i_irq_init(struct platform_device *pdev, const char *name,
- irq_handler_t handler, const char *devname,
- unsigned int *irq, atomic_t *atomic)
-{
- int ret;
- struct sun4i_gpadc_dev *mfd_dev = dev_get_drvdata(pdev->dev.parent);
- struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(>dev));
-
- /*
-* Once the interrupt is activated, the IP continuously performs
-* conversions thus throws interrupts. The interrupt is activated right
-* after being requested but we want to control when these interrupts
-* occur thus we disable it right after being requested. However, an
-* interrupt might occur between these two instructions and we have to
-* make sure that does not happen, by using atomic flags. We set the
-* flag before requesting the interrupt and unset it right after
-* disabling the interrupt. When an interrupt occurs between these two
-* instructions, reading the atomic flag will tell us to ignore the
-* interrupt.
-*/
- atomic_set(atomic, 1);
-
- ret = platform_get_irq_byname(pdev, name);
- if (ret < 0) {
- dev_err(>dev, "no %s interrupt registered\n", name);
- return ret;
- }
-
- ret = regmap_irq_get_virq(mfd_dev->regmap_irqc, ret);
- if (ret < 0) {
- dev_err(>dev, "failed to get virq for irq %s\n", name);
- return ret;
- }
-
- *irq = ret;
- ret = devm_request_any_context_irq(>dev, *irq, handler, 0,
- devname, info);
- if (ret < 0) {
- dev_err(>dev, "could not request %s interrupt: %d\n",
- name, ret);
- return ret;
- }
-
- disable_irq(*irq);
- atomic_set(atomic, 0);
-
- return 0;
-}
-
static const struct of_device_id sun4i_gpadc_of_id[] = {
{
.compatible = "allwinner,sun8i-a33-ths",
@@ -523,83 +474,6 @@ static int sun4i_gpadc_probe_dt(struct platform_device
*pdev,
return 0;
}
-static int sun4i_gpadc_probe_mfd(struct platform_device *pdev,
-struct iio_dev *indio_dev)
-{
- struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
- struct sun4i_gpadc_dev *sun4i_gpadc_dev =
- dev_get_drvdata(pdev->dev.parent);
- int ret;
-
- info->no_irq = false;
- info->regmap = sun4i_gpadc_dev->regmap;
-
- indio_dev->num_channels = ARRAY_SIZE(sun4i_gpadc_channels);
- indio_dev->channels = sun4i_gpadc_channels;
-
- info->data = (struct gpadc_data
*)platform_get_device_id(pdev)->driver_data;
-
- /*
-* Since the controller needs to be in touchscreen mode for its thermal
-* sensor to operate properly, and that switching between the two modes
-* needs a delay, always registering in the thermal framework will
-* significantly slow down the conversion rate of the ADCs.
-*
-* Therefore, instead of depending on THERMAL_OF in Kconfig, we only
-* register the sensor if that option is enabled, eventually leaving
-* that choice to the user.
-*/
-
- if (IS_ENABLED(CONFIG_THERMAL_OF)) {
- /*
-* This driver is a child of an MFD which has a node in the DT
-* but not its children, because of DT backward compatibility
-* for A10, A13 and A31 SoCs. Therefore, the resulting devices
-* of this driver do not have an of_node variable.
-* However, its parent (the MFD driver) has an of_node variable
-* and since devm_thermal_zone_of_sensor_register uses its first
-* argument to match the phandle defined in the node of the
-* thermal driver with the of_node of the device passed as first
-* argument and the third argument to call ops from
-* thermal_zone_of_device_ops, the solution is to use the parent
-* device as first argument to match the phandle with its
-* of_node, and the device from this driver as third argument to
-* return the temperature.
-*/
- info->sensor_device = pdev->dev.parent;
- } else {
-
[linux-sunxi] [PATCH v3 09/30] iio: adc: Threat A33 as thermal sensor and remove non thermal sun4i channel
We want to use this driver mostly as thermal sensor, that still supports
the adc for the older chips, thus we threat the A33 as thermal sensor.
We also remove the adc channel without thermal support.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 19 ---
1 file changed, 19 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index ab474ce86fb6..658a7e3e3370 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -123,23 +123,6 @@ static const struct iio_chan_spec sun4i_gpadc_channels[] =
{
},
};
-static const struct iio_chan_spec sun4i_gpadc_channels_no_temp[] = {
- SUN4I_GPADC_ADC_CHANNEL(0, "adc_chan0"),
- SUN4I_GPADC_ADC_CHANNEL(1, "adc_chan1"),
- SUN4I_GPADC_ADC_CHANNEL(2, "adc_chan2"),
- SUN4I_GPADC_ADC_CHANNEL(3, "adc_chan3"),
-};
-
-static const struct iio_chan_spec sun8i_a33_gpadc_channels[] = {
- {
- .type = IIO_TEMP,
- .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
- BIT(IIO_CHAN_INFO_SCALE) |
- BIT(IIO_CHAN_INFO_OFFSET),
- .datasheet_name = "temp_adc",
- },
-};
-
static const struct regmap_config sun4i_gpadc_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
@@ -444,8 +427,6 @@ static int sun4i_gpadc_probe_dt(struct platform_device
*pdev,
return -ENODEV;
info->no_irq = true;
- indio_dev->num_channels = ARRAY_SIZE(sun8i_a33_gpadc_channels);
- indio_dev->channels = sun8i_a33_gpadc_channels;
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(>dev, mem);
--
2.11.0
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[linux-sunxi] [PATCH v3 13/30] arm: config: Enable SUN4I_GPADC in defconfig
Since we have now new compatibles we can enable the SUN4I_GPADC driver next to the sun4i-ts driver. Signed-off-by: Philipp Rossak --- arch/arm/configs/sunxi_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig index df433abfcb02..2189349820ac 100644 --- a/arch/arm/configs/sunxi_defconfig +++ b/arch/arm/configs/sunxi_defconfig @@ -132,6 +132,7 @@ CONFIG_DMA_SUN6I=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_EXTCON=y CONFIG_IIO=y +CONFIG_SUN4I_GPADC=y CONFIG_AXP20X_ADC=y CONFIG_PWM=y CONFIG_PWM_SUN4I=y -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v3 10/30] iio: adc: rework irq and adc_channel handling
We rework the irq handling and the adc_channel handling.
This is requiered since we merge the mfd driver into the adc driver.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 157 --
include/linux/mfd/sun4i-gpadc.h | 7 --
2 files changed, 98 insertions(+), 66 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 658a7e3e3370..a2027614ee0c 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -49,6 +49,8 @@ static unsigned int sun6i_gpadc_chan_select(unsigned int chan)
return SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(chan);
}
+struct sun4i_gpadc_iio;
+
struct gpadc_data {
int temp_offset;
int temp_scale;
@@ -56,8 +58,15 @@ struct gpadc_data {
unsigned inttp_adc_select;
unsigned int(*adc_chan_select)(unsigned int chan);
unsigned intadc_chan_mask;
+ booladc_channel;
+ irqreturn_t (*ths_irq_thread)(int irq, void *dev_id);
+ int (*ths_suspend)(struct sun4i_gpadc_iio *info);
+ int (*ths_resume)(struct sun4i_gpadc_iio *info);
+ boolsupport_irq;
};
+static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, void *dev_id);
+
static const struct gpadc_data sun4i_gpadc_data = {
.temp_offset = -1932,
.temp_scale = 133,
@@ -65,6 +74,9 @@ static const struct gpadc_data sun4i_gpadc_data = {
.tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
.adc_chan_select = _gpadc_chan_select,
.adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
+ .adc_channel = true,
+ .ths_irq_thread = sun4i_gpadc_data_irq_handler,
+ .support_irq = true,
};
static const struct gpadc_data sun5i_gpadc_data = {
@@ -74,6 +86,9 @@ static const struct gpadc_data sun5i_gpadc_data = {
.tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
.adc_chan_select = _gpadc_chan_select,
.adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
+ .adc_channel = true,
+ .ths_irq_thread = sun4i_gpadc_data_irq_handler,
+ .support_irq = true,
};
static const struct gpadc_data sun6i_gpadc_data = {
@@ -83,6 +98,9 @@ static const struct gpadc_data sun6i_gpadc_data = {
.tp_adc_select = SUN6I_GPADC_CTRL1_TP_ADC_SELECT,
.adc_chan_select = _gpadc_chan_select,
.adc_chan_mask = SUN6I_GPADC_CTRL1_ADC_CHAN_MASK,
+ .adc_channel = true,
+ .ths_irq_thread = sun4i_gpadc_data_irq_handler,
+ .support_irq = true,
};
static const struct gpadc_data sun8i_a33_gpadc_data = {
@@ -96,13 +114,10 @@ struct sun4i_gpadc_iio {
struct completion completion;
int temp_data;
u32 adc_data;
+ unsigned intirq_data_type;
struct regmap *regmap;
- unsigned intfifo_data_irq;
- atomic_tignore_fifo_data_irq;
- unsigned inttemp_data_irq;
- atomic_tignore_temp_data_irq;
+ unsigned intirq;
const struct gpadc_data *data;
- boolno_irq;
/* prevents concurrent reads of temperature and ADC */
struct mutexmutex;
struct thermal_zone_device *tzd;
@@ -130,6 +145,20 @@ static const struct regmap_config
sun4i_gpadc_regmap_config = {
.fast_io = true,
};
+static int sun4i_gpadc_irq_init(struct sun4i_gpadc_iio *info)
+{
+ u32 reg;
+
+ if (info->irq_data_type == SUN4I_GPADC_IRQ_FIFO_DATA)
+ reg = SUN4I_GPADC_INT_FIFOC_TEMP_IRQ_EN;
+ else
+ reg = SUN4I_GPADC_INT_FIFOC_TEMP_IRQ_EN;
+
+ regmap_write(info->regmap, SUN4I_GPADC_INT_FIFOC, reg);
+
+ return 0;
+}
+
static int sun4i_prepare_for_irq(struct iio_dev *indio_dev, int channel,
unsigned int irq)
{
@@ -151,7 +180,7 @@ static int sun4i_prepare_for_irq(struct iio_dev *indio_dev,
int channel,
if (ret)
return ret;
- if (irq == info->fifo_data_irq) {
+ if (irq == SUN4I_GPADC_IRQ_FIFO_DATA) {
ret = regmap_write(info->regmap, SUN4I_GPADC_CTRL1,
info->data->tp_mode_en |
info->data->tp_adc_select |
@@ -172,6 +201,8 @@ static int sun4i_prepare_for_irq(struct iio_dev *indio_dev,
int channel,
ret = regmap_write(info->regmap, SUN4I_GPADC_CTRL1,
info->data->tp_mode_en);
}
+ if (info->data->support_irq)
+ sun4i_gpadc_irq_init(info);
if (ret)
return ret;
@@ -194,11 +225,12 @@ static int sun4i_gpadc_read(struct iio_dev *indio_dev,
int channel, int
[linux-sunxi] [PATCH v3 01/30] mfd: Makefile: Remove build option for MFD:sun4i-gpadc
Since we are merging the mfd driver into the sun4i-gpadc driver we need to remove the build options for the sun4i-gpadc driver. Signed-off-by: Philipp Rossak --- drivers/mfd/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index e9fd20dba18d..c680994db988 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -220,7 +220,6 @@ obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI) += intel_soc_pmic_chtdc_ti.o obj-$(CONFIG_MFD_MT6397) += mt6397-core.o obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o -obj-$(CONFIG_MFD_SUN4I_GPADC) += sun4i-gpadc.o obj-$(CONFIG_MFD_STM32_LPTIMER)+= stm32-lptimer.o obj-$(CONFIG_MFD_STM32_TIMERS) += stm32-timers.o -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v3 02/30] mfd: Kconfig: Remove MFD_SUN4I_GPADC config option
We are merging the mfd:sun4i-gpadc driver into the iio/adc/sun4i-gpadc driver. So we need to remove the MFD_SUN4I_GPADC config option. Signed-off-by: Philipp Rossak --- drivers/mfd/Kconfig | 17 - 1 file changed, 17 deletions(-) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index b860eb5aa194..c7ab57d65610 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -40,23 +40,6 @@ config MFD_ACT8945A linear regulators, along with a complete ActivePath battery charger. -config MFD_SUN4I_GPADC - tristate "Allwinner sunxi platforms' GPADC MFD driver" - select MFD_CORE - select REGMAP_MMIO - select REGMAP_IRQ - depends on ARCH_SUNXI || COMPILE_TEST - depends on !TOUCHSCREEN_SUN4I - help - Select this to get support for Allwinner SoCs (A10, A13 and A31) ADC. - This driver will only map the hardware interrupt and registers, you - have to select individual drivers based on this MFD to be able to use - the ADC or the thermal sensor. This will try to probe the ADC driver - sun4i-gpadc-iio and the hwmon driver iio_hwmon. - - To compile this driver as a module, choose M here: the module will be - called sun4i-gpadc. - config MFD_AS3711 bool "AMS AS3711" select MFD_CORE -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v3 11/30] iio: adc: add new compatibles
We are now adding the new compatibles.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index a2027614ee0c..79b8efdab803 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -435,6 +435,18 @@ static const struct of_device_id sun4i_gpadc_of_id[] = {
.compatible = "allwinner,sun8i-a33-ths",
.data = _a33_gpadc_data,
},
+ {
+ .compatible = "allwinner,sun4i-a10-gpadc",
+ .data = _gpadc_data
+ },
+ {
+ .compatible = "allwinner,sun5i-a13-gpadc",
+ .data = _gpadc_data
+ },
+ {
+ .compatible = "allwinner,sun6i-a31-gpadc",
+ .data = _gpadc_data
+ },
{ /* sentinel */ }
};
--
2.11.0
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[linux-sunxi] [PATCH v3 05/30] iio: adc: move SUN4I_GPADC_CHANNEL define to header file
We are moving the SUN4I_GPADC_CHANNEL define to the header file.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 9 -
include/linux/mfd/sun4i-gpadc.h | 9 +
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index d95dd0fde2a6..666329940e1e 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -109,15 +109,6 @@ struct sun4i_gpadc_iio {
struct device *sensor_device;
};
-#define SUN4I_GPADC_ADC_CHANNEL(_channel, _name) { \
- .type = IIO_VOLTAGE,\
- .indexed = 1, \
- .channel = _channel,\
- .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
- .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
- .datasheet_name = _name,\
-}
-
static struct iio_map sun4i_gpadc_hwmon_maps[] = {
{
.adc_channel_label = "temp_adc",
diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h
index 139872c2e0fe..54c7c9375c1b 100644
--- a/include/linux/mfd/sun4i-gpadc.h
+++ b/include/linux/mfd/sun4i-gpadc.h
@@ -90,6 +90,15 @@
/* 10s delay before suspending the IP */
#define SUN4I_GPADC_AUTOSUSPEND_DELAY 1
+#define SUN4I_GPADC_ADC_CHANNEL(_channel, _name) { \
+ .type = IIO_VOLTAGE,\
+ .indexed = 1, \
+ .channel = _channel,\
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
+ .datasheet_name = _name,\
+}
+
struct sun4i_gpadc_dev {
struct device *dev;
struct regmap *regmap;
--
2.11.0
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[linux-sunxi] [PATCH v3 14/30] dt-bindings: update the Allwinner GPADC device tree binding for H3 & A83T
Allwinner H3 features a thermal sensor like the one in A33, but has its
register re-arranged, the clock divider moved to CCU (originally the
clock divider is in ADC) and added a pair of bus clock and reset.
Allwinner A83T features a thermal sensor similar to the H3, the ths clock,
the bus clock and the reset was removed from the CCU. The THS in A83T
has a clock that is directly connected and runs with 24 MHz.
Update the binding document to cover H3 and A83T.
Signed-off-by: Philipp Rossak
---
.../devicetree/bindings/iio/adc/sun4i-gpadc.txt| 41 --
1 file changed, 38 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/iio/adc/sun4i-gpadc.txt
b/Documentation/devicetree/bindings/iio/adc/sun4i-gpadc.txt
index a7ef9dd21f04..9116ad308cf1 100644
--- a/Documentation/devicetree/bindings/iio/adc/sun4i-gpadc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/sun4i-gpadc.txt
@@ -4,12 +4,35 @@ The Allwinner SoCs all have an ADC that can also act as a
thermal sensor
and sometimes as a touchscreen controller.
Required properties:
- - compatible: "allwinner,sun8i-a33-ths",
+ - compatible: must contain one of the following compatibles:
+ - "allwinner,sun8i-a33-ths"
+ - "allwinner,sun8i-h3-ths"
+ - "allwinner,sun8i-a83t-ths"
- reg: mmio address range of the chip,
- - #thermal-sensor-cells: shall be 0,
+ - #thermal-sensor-cells:
+ Please refer ,
- #io-channel-cells: shall be 0,
-Example:
+Required properties for the following compatibles:
+ - "allwinner,sun8i-h3-ths"
+ - "allwinner,sun8i-a83t-ths"
+ - interrupts: the sampling interrupt of the ADC,
+
+Required properties for the following compatibles:
+ - "allwinner,sun8i-h3-ths"
+ - clocks: the bus clock and the input clock of the ADC,
+ - clock-names: should be "bus" and "mod",
+ - resets: the bus reset of the ADC,
+
+Optional properties for the following compatibles:
+ - "allwinner,sun8i-h3-ths"
+ - "allwinner,sun8i-a83t-ths"
+ - nvmem-cells: A phandle to the calibration data provided by a nvmem device.
+ - nvmem-cell-names: Should be "calibration".
+
+Details see: bindings/nvmem/nvmem.txt
+
+Example for A33:
ths: ths@1c25000 {
compatible = "allwinner,sun8i-a33-ths";
reg = <0x01c25000 0x100>;
@@ -17,6 +40,18 @@ Example:
#io-channel-cells = <0>;
};
+Example for H3:
+ ths: thermal-sensor@1c25000 {
+ compatible = "allwinner,sun8i-h3-ths";
+ reg = <0x01c25000 0x400>;
+ clocks = < CLK_BUS_THS>, < CLK_THS>;
+ clock-names = "bus", "mod";
+ resets = < RST_BUS_THS>;
+ interrupts = ;
+ #thermal-sensor-cells = <0>;
+ #io-channel-cells = <0>;
+ };
+
sun4i, sun5i and sun6i SoCs are also supported via these bindings:
Required properties:
--
2.11.0
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[linux-sunxi] [PATCH v3 16/30] iio: adc: sun4i-gpadc-iio: rework: readout temp_data
For adding newer sensor some basic rework of the code is necessary.
This commit reworks the code and uses regmap field to read out
temp_data.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 21 +
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index d48f338af563..c278e165e161 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -63,6 +63,7 @@ struct gpadc_data {
int (*ths_suspend)(struct sun4i_gpadc_iio *info);
int (*ths_resume)(struct sun4i_gpadc_iio *info);
boolsupport_irq;
+ u32 temp_data_base;
};
static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, void *dev_id);
@@ -77,6 +78,7 @@ static const struct gpadc_data sun4i_gpadc_data = {
.adc_channel = true,
.ths_irq_thread = sun4i_gpadc_data_irq_handler,
.support_irq = true,
+ .temp_data_base = SUN4I_GPADC_TEMP_DATA,
};
static const struct gpadc_data sun5i_gpadc_data = {
@@ -89,6 +91,7 @@ static const struct gpadc_data sun5i_gpadc_data = {
.adc_channel = true,
.ths_irq_thread = sun4i_gpadc_data_irq_handler,
.support_irq = true,
+ .temp_data_base = SUN4I_GPADC_TEMP_DATA,
};
static const struct gpadc_data sun6i_gpadc_data = {
@@ -101,12 +104,14 @@ static const struct gpadc_data sun6i_gpadc_data = {
.adc_channel = true,
.ths_irq_thread = sun4i_gpadc_data_irq_handler,
.support_irq = true,
+ .temp_data_base = SUN4I_GPADC_TEMP_DATA,
};
static const struct gpadc_data sun8i_a33_gpadc_data = {
.temp_offset = -1662,
.temp_scale = 162,
.tp_mode_en = SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN,
+ .temp_data_base = SUN4I_GPADC_TEMP_DATA,
};
struct sun4i_gpadc_iio {
@@ -271,18 +276,18 @@ static int sun4i_gpadc_temp_read(struct iio_dev
*indio_dev, int *val)
{
struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
- if (!info->data->support_irq) {
- pm_runtime_get_sync(indio_dev->dev.parent);
+ if (info->data->adc_channel)
+ return sun4i_gpadc_read(indio_dev, 0, val,
+ SUN4I_GPADC_IRQ_TEMP_DATA);
- regmap_read(info->regmap, SUN4I_GPADC_TEMP_DATA, val);
+ pm_runtime_get_sync(indio_dev->dev.parent);
- pm_runtime_mark_last_busy(indio_dev->dev.parent);
- pm_runtime_put_autosuspend(indio_dev->dev.parent);
+ regmap_read(info->regmap, info->data->temp_data_base, val);
- return 0;
- }
+ pm_runtime_mark_last_busy(indio_dev->dev.parent);
+ pm_runtime_put_autosuspend(indio_dev->dev.parent);
- return sun4i_gpadc_read(indio_dev, 0, val, SUN4I_GPADC_IRQ_TEMP_DATA);
+ return 0;
}
static int sun4i_gpadc_temp_offset(struct iio_dev *indio_dev, int *val)
--
2.11.0
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[linux-sunxi] [PATCH v3 06/30] iio: adc: remove ofnode options
Since we are merging the mfd dirver into the adc driver we don't need two different probing functions. Thus we remove the ofnode options Signed-off-by: Philipp Rossak --- drivers/iio/adc/sun4i-gpadc-iio.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c index 666329940e1e..d6f00d3b802d 100644 --- a/drivers/iio/adc/sun4i-gpadc-iio.c +++ b/drivers/iio/adc/sun4i-gpadc-iio.c @@ -622,10 +622,7 @@ static int sun4i_gpadc_probe(struct platform_device *pdev) indio_dev->info = _gpadc_iio_info; indio_dev->modes = INDIO_DIRECT_MODE; - if (pdev->dev.of_node) - ret = sun4i_gpadc_probe_dt(pdev, indio_dev); - else - ret = sun4i_gpadc_probe_mfd(pdev, indio_dev); + ret = sun4i_gpadc_probe_dt(pdev, indio_dev); if (ret) return ret; -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v3 00/30] IIO-based thermal sensor driver for Allwinner H3 and A83T SoC
Allwiner H3 and A83T SoCs have a thermal sensor, which is a large refactored
version of the old Allwinner "GPADC" (although it have already only
thermal part left in A33).
This patch tried to add support for the sensor in H3 and A83T based on
This Patchtseries was in the beginning based on Icenowy Zengs v4 patchseries
[1]. Since we decided to merge the mfd driver into the GPADC this changed. So
only one patch could be reused.
Patches that adds support for H5, A64, A80 and H6 SoCs are allready prepared,
and will be upstreamed if this patchseries is applied and the testing is done.
Sorry for delaying this.
Regards,
Philipp
changes since v2:
* mfd driver is now merged into the gpadc driver
* complete rework
changes since v1:
* collecting all acks
* rewording commits/fix typos
* move code in place where it is used
* fix naming conventions of defines
* clarify commits
* update documentation to cover the new nvmem calibraion
* change nvmem calibration
Icenowy Zheng (1):
iio: adc: sun4i-gpadc-iio: rename A33-specified registers to contain
A33
Philipp Rossak (29):
mfd: Makefile: Remove build option for MFD:sun4i-gpadc
mfd: Kconfig: Remove MFD_SUN4I_GPADC config option
iio: adc: Remove ID table
iio: adc: Kconfig: Update Kconfig to new build options
iio: adc: move SUN4I_GPADC_CHANNEL define to header file
iio: adc: remove ofnode options
iio: adc: remove mfd_probe & sunwi_irq_init function
iio: adc: remove hwmon structure
iio: adc: Threat A33 as thermal sensor and remove non thermal sun4i
channel
iio: adc: rework irq and adc_channel handling
iio: adc: add new compatibles
mfd: Remove old mfd driver & Move sun4i-gpadc.h to iio/adc/
arm: config: Enable SUN4I_GPADC in defconfig
dt-bindings: update the Allwinner GPADC device tree binding for H3 &
A83T
iio: adc: sun4i-gpadc-iio: rework: readout temp_data
iio: adc: sun4i-gpadc-iio: rework: support clocks and reset
iio: adc: sun4i-gpadc-iio: rework: support multiple sensors
iio: adc: sun4i-gpadc-iio: rework: support nvmem calibration data
iio: adc: sun4i-gpadc-iio: rework: device specific suspend & resume
iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor
iio: adc: sun4i-gpadc-iio: add support for A83T thermal sensor
ARM: dts: sunxi-h3-h5: add support for the thermal sensor in H3 and H5
ARM: dts: sun8i: h3: add support for the thermal sensor in H3
ARM: dts: sun8i: h3: add thermal zone to H3
ARM: dts: sun8i: h3: enable H3 sid controller
ARM: dts: sun8i: h3: use calibration for ths
ARM: dts: sun8i: a83t: add support for the thermal sensor in A83T
ARM: dts: sun8i: a83t: add thermal zone to A83T
ARM: sun8i: a83t: full range OPP tables and CPUfreq
.../devicetree/bindings/iio/adc/sun4i-gpadc.txt| 41 +-
arch/arm/boot/dts/sun8i-a83t.dtsi | 143 +
arch/arm/boot/dts/sun8i-h3.dtsi| 52 ++
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 10 +
arch/arm/configs/sunxi_defconfig | 1 +
drivers/iio/adc/Kconfig| 11 +-
drivers/iio/adc/sun4i-gpadc-iio.c | 617 +
drivers/mfd/Kconfig| 17 -
drivers/mfd/Makefile | 1 -
drivers/mfd/sun4i-gpadc.c | 181 --
include/linux/{mfd => iio/adc}/sun4i-gpadc.h | 47 +-
11 files changed, 681 insertions(+), 440 deletions(-)
delete mode 100644 drivers/mfd/sun4i-gpadc.c
rename include/linux/{mfd => iio/adc}/sun4i-gpadc.h (72%)
--
2.11.0
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[linux-sunxi] [PATCH v3 04/30] iio: adc: Kconfig: Update Kconfig to new build options
Since we are merging the mfd driver into the iio adc driver we need to update the Kconfig build options. Signed-off-by: Philipp Rossak --- drivers/iio/adc/Kconfig | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 9da79070357c..5d0cffd6d2e4 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -713,13 +713,16 @@ config STX104 array module parameter. config SUN4I_GPADC - tristate "Support for the Allwinner SoCs GPADC" + tristate "Allwinner sunxi platforms' GPADC/Thermal driver" + select REGMAP_MMIO + select REGMAP_IRQ depends on IIO - depends on MFD_SUN4I_GPADC || MACH_SUN8I - depends on THERMAL || !THERMAL_OF + depends on ARCH_SUNXI || MACH_SUN8I + depends on THERMAL && THERMAL_OF help Say yes here to build support for Allwinner (A10, A13 and A31) SoCs - GPADC. This ADC provides 4 channels which can be used as an ADC or as + GPADC or newer SOCs (A33, H3, A83T, ...) Thermal sensor driver. + This ADC provides 4 channels which can be used as an ADC or as a touchscreen input and one channel for thermal sensor. The thermal sensor slows down ADC readings and can be disabled by -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH] drm/sun4i: Remove R40 display pipeline compatibles
On Mon, Aug 27, 2018 at 04:39:50PM +0800, Chen-Yu Tsai wrote: > Two patches from the R40 display pipeline support series weren't applied > with the rest of the series. When they did get applied, the -rc6 > deadline for drm-misc-next had past, so they didn't get into 4.19-rc1 > with the rest of the series. However, the two patches are crucial in > the parsing of the R40's display pipeline graph in the device tree. > Without them, the driver crashes because it can't follow the odd graph > structure. > > This patch removes the R40 compatibles from the sun4i-drm driver, > effectively disabling DRM support for the R40 for one release cycle. > This will prevent the driver from crashing upon probing. > > The compatibles should be reinstated for the next release. > > Signed-off-by: Chen-Yu Tsai > --- > > This is for 4.19-rc to fix the boot crash seen on the R40. > > This should go in drm-misc-fixes and into Linus' tree ASAP. > Once merged, the branch should also be merged into drm-misc-next, > and then we can revert it. Applied, thanks! Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] [PATCH 0/3] arm64: dts: allwinner: h5: Add device tree for Bananapi M2 Plus H5
Hi,
Allwinner's H5 SoC is pin compatible with the H3 SoC. As such, some
vendors produce H3 and H5 variants for the same device. Such is the
case with Libre Computer's ALL-H3-CC, and the Bananapi M2 Plus.
This series follows that of the ALL-H3-CC, splitting out a common
board dtsi, and then two SoC-specific dts files that include the
SoC level and common board dtsi's, as well as putting in the board
name. The first patch is a minor fix that I think should be done
before the migration.
Please have a look.
Also, on a related matter, Bananapi recently released revision v1.2
of the M2 Plus. The original commercially available version was v1.1.
v1.2 adds a GPIO control that can change the CPU cores' supply voltage
between 1.1V and 1.3V. Do we want two extra dts files for this? Put
them in the existing dts files regardless? Or let people handle this
via overlays?
Thanks
ChenYu
Chen-Yu Tsai (3):
ARM: dts: sun8i: h3: bpi-m2-plus: Fix address for external RGMII
Ethernet PHY
ARM: dts: sun8i: h3: Split out non-SoC-specific parts of Bananapi M2
Plus
arm64: dts: allwinner: h5: Add device tree for Bananapi M2 Plus H5
.../boot/dts/sun8i-h3-bananapi-m2-plus.dts| 190 +-
...2-plus.dts => sunxi-bananapi-m2-plus.dtsi} | 7 +-
arch/arm64/boot/dts/allwinner/Makefile| 1 +
.../allwinner/sun50i-h5-bananapi-m2-plus.dts | 11 +
4 files changed, 15 insertions(+), 194 deletions(-)
copy arch/arm/boot/dts/{sun8i-h3-bananapi-m2-plus.dts =>
sunxi-bananapi-m2-plus.dtsi} (97%)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts
--
2.18.0
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[linux-sunxi] [PATCH 1/3] ARM: dts: sun8i: h3: bpi-m2-plus: Fix address for external RGMII Ethernet PHY
The external RTL8211E RGMII Ethernet PHY is configured via external
resistors to use the address 0x1. The 0x0 address is a broadcast address
for this family of PHYs, and should not be used explicitly.
Fixes: 8c7ba536e709 ("ARM: sun8i: bananapi-m2-plus: Enable dwmac-sun8i")
Fixes: 4904337fe34f ("ARM: dts: sunxi: Restore EMAC changes (boards)")
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index 30540dc8e0c5..bdda0d99128e 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -140,7 +140,7 @@
_mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
+ reg = <1>;
};
};
--
2.18.0
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[linux-sunxi] [PATCH 2/3] ARM: dts: sun8i: h3: Split out non-SoC-specific parts of Bananapi M2 Plus
Three more variants of the Bananapi M2 Plus have been introduced. One
with the H5 instead of the H3, another with the H2+ instead, and the
last with the H3 but with WiFi and eMMC removed.
All these variants use the same board. This patch splits out the
non-SoC-specific parts of the device tree, so that they can be shared
among all the variants. The original Bananapi M2 Plus has been renamed
to Bananapi M2 Plus H3.
Signed-off-by: Chen-Yu Tsai
---
.../boot/dts/sun8i-h3-bananapi-m2-plus.dts| 190 +-
...2-plus.dts => sunxi-bananapi-m2-plus.dtsi} | 5 -
2 files changed, 2 insertions(+), 193 deletions(-)
copy arch/arm/boot/dts/{sun8i-h3-bananapi-m2-plus.dts =>
sunxi-bananapi-m2-plus.dtsi} (97%)
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index bdda0d99128e..195a75da13f1 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -42,195 +42,9 @@
/dts-v1/;
#include "sun8i-h3.dtsi"
-#include "sunxi-common-regulators.dtsi"
-
-#include
-#include
+#include "sunxi-bananapi-m2-plus.dtsi"
/ {
- model = "Banana Pi BPI-M2-Plus";
+ model = "Banana Pi BPI-M2-Plus H3";
compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
-
- aliases {
- ethernet0 =
- serial0 =
- serial1 =
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <_out_con>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
-
- pwr_led {
- label = "bananapi-m2-plus:red:pwr";
- gpios = <_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
- default-state = "on";
- };
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
-
- sw4 {
- label = "power";
- linux,code = ;
- gpios = <_pio 0 3 GPIO_ACTIVE_LOW>;
- };
- };
-
- reg_gmac_3v3: gmac-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "gmac-3v3";
- regulator-min-microvolt = <330>;
- regulator-max-microvolt = <330>;
- startup-delay-us = <10>;
- enable-active-high;
- gpio = < 3 6 GPIO_ACTIVE_HIGH>;
- };
-
- wifi_pwrseq: wifi_pwrseq {
- compatible = "mmc-pwrseq-simple";
- pinctrl-names = "default";
- reset-gpios = <_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
- };
-};
-
- {
- status = "okay";
-};
-
- {
- status = "okay";
-};
-
- {
- status = "okay";
-};
-
- {
- status = "okay";
-};
-
- {
- pinctrl-names = "default";
- pinctrl-0 = <_rgmii_pins>;
- phy-supply = <_gmac_3v3>;
- phy-handle = <_rgmii_phy>;
- phy-mode = "rgmii";
-
- status = "okay";
-};
-
-_mdio {
- ext_rgmii_phy: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- };
-};
-
- {
- status = "okay";
-};
-
-_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <_con_in>;
- };
-};
-
- {
- pinctrl-names = "default";
- pinctrl-0 = <_pins_a>;
- status = "okay";
-};
-
- {
- vmmc-supply = <_vcc3v3>;
- bus-width = <4>;
- cd-gpios = < 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- status = "okay";
-};
-
- {
- vmmc-supply = <_vcc3v3>;
- vqmmc-supply = <_vcc3v3>;
- mmc-pwrseq = <_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <>;
- interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
- interrupt-names = "host-wake";
- };
-};
-
- {
- pinctrl-names = "default";
- pinctrl-0 = <_8bit_pins>;
- vmmc-supply = <_vcc3v3>;
- vqmmc-supply = <_vcc3v3>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
- {
- status = "okay";
-};
-
- {
- status = "okay";
-};
-
- {
- status = "okay";
-};
-
-_usb0_vbus {
- gpio = < 3 11 GPIO_ACTIVE_HIGH>; /* PD11 */
- status = "okay";
-};
-
- {
- pinctrl-names = "default";
- pinctrl-0 = <_pins_a>;
- status = "okay";
-};
-
- {
- pinctrl-names = "default";
- pinctrl-0 = <_pins>,
[linux-sunxi] [PATCH 3/3] arm64: dts: allwinner: h5: Add device tree for Bananapi M2 Plus H5
The Bananapi M2 Plus H5 is a variant of the original Bananapi M2 Plus,
with the H3 SoC replaced with an H5. Everything else is the same.
Add a stub device tree incorporating the shared bananapi-m2-plus dtsi
file.
Signed-off-by: Chen-Yu Tsai
---
arch/arm64/boot/dts/allwinner/Makefile| 1 +
.../boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts | 11 +++
2 files changed, 12 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile
b/arch/arm64/boot/dts/allwinner/Makefile
index b7034327b28b..82335360499d 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb
sun50i-a64-pine64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-cc.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts
new file mode 100644
index ..77661006dfba
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2018 Chen-Yu Tsai
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include
+
+/ {
+ model = "Banana Pi BPI-M2-Plus H5";
+ compatible = "sinovoip,bpi-m2-plus", "allwinner,sun50i-h5";
+};
--
2.18.0
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