Setting ID cache enable in the same mtspr instruction
I think we need to hold off on this particular patch for a few days. I took a look at the manual section you're referencing here, and sure enough, it says that you shouldn't set both bits in the same mtspr instruction. The manual says this in more than one place, in fact. However, that seemed a little bit odd to me, so I talked with a few of the hardware designers for the 745x family. They assure me that the manual statement is false. The normal code that sets ICE/ICFI/ DCE/DCFI all on one mtspr should be fully functional on this processor family. I'm still working on confirming this and getting some history on *why* the manual says that, but for now I'd say it's a pretty good bet that the manual is in error. I will let you know if I find out this is not the case. You are correct, though, in that an isync is needed prior to the write of HID0[ICE]. It's probably missing because it's not listed in the synchronization table in chapter 2 of the manual. For what it's worth, as soon as I can confirm this, I will make sure the publications team here at Freescale is made aware of the error so it can be corrected in the next printing of the manual. I will also have the synchronization table updated as it also has incorrect information. Thanks, B
Setting ID cache enable in the same mtspr instruction
On Mon, May 29, 2006 at 02:15:14PM +0200, Roger Larsson wrote: Is the patch reversed? Sure looks like it. diff -Naur old new patch And what about comments, are they all still valid? enable and invalidate caches is now only Data cache... In cases when I am writing code like this I try to include the reason why it is not optimized together in one write... (or soon someone will do that optimization). Good point. /RogerL Also, please send the patches *inline*. Mark
Setting ID cache enable in the same mtspr instruction
Hi, Attached... -Original Message- From: Mark A. Greer [mailto:[EMAIL PROTECTED] Sent: Wednesday, May 24, 2006 1:35 AM To: Assaf Hoffman Cc: Mark A. Greer; linuxppc-embedded at ozlabs.org; Rita Shtern; Ronen Shitrit Subject: Re: Setting ID cache enable in the same mtspr instruction On Tue, May 23, 2006 at 12:55:46PM +0300, Assaf Hoffman wrote: Attached. Thanks. Er, how about a *patch* place inline (as in, not as an attachment). Thanks, Mark -- next part -- A non-text attachment was scrubbed... Name: cpu_setup_6xx.patch Type: application/octet-stream Size: 827 bytes Desc: cpu_setup_6xx.patch Url : http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20060529/2ee2c98c/attachment.obj
Setting ID cache enable in the same mtspr instruction
Is the patch reversed? diff -Naur old new patch And what about comments, are they all still valid? enable and invalidate caches is now only Data cache... In cases when I am writing code like this I try to include the reason why it is not optimized together in one write... (or soon someone will do that optimization). /RogerL
Setting ID cache enable in the same mtspr instruction
Hi, Attached... -Original Message- From: [EMAIL PROTECTED] [mailto:linuxppc-embedded-bounces+hoffman=marvell.com at ozlabs.org] On Behalf Of Roger Larsson Sent: Monday, May 29, 2006 3:15 PM To: linuxppc-embedded at ozlabs.org Subject: Re: Setting ID cache enable in the same mtspr instruction Importance: Low Is the patch reversed? diff -Naur old new patch And what about comments, are they all still valid? enable and invalidate caches is now only Data cache... In cases when I am writing code like this I try to include the reason why it is not optimized together in one write... (or soon someone will do that optimization). /RogerL ___ Linuxppc-embedded mailing list Linuxppc-embedded at ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded -- next part -- A non-text attachment was scrubbed... Name: cpu_setup_6xx.patch Type: application/octet-stream Size: 1114 bytes Desc: cpu_setup_6xx.patch Url : http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20060529/e6954d51/attachment.obj
Setting ID cache enable in the same mtspr instruction
Attached. Thanks. -Original Message- From: Mark A. Greer [mailto:[EMAIL PROTECTED] Sent: Monday, May 15, 2006 10:00 PM To: Assaf Hoffman Cc: linuxppc-embedded at ozlabs.org; Rita Shtern; Ronen Shitrit Subject: Re: Setting ID cache enable in the same mtspr instruction On Mon, May 08, 2006 at 01:39:13PM +0300, Assaf Hoffman wrote: Hi, I think the implementation of setup_common_caches() in file cpu_setup_6xx.S; not according to the spec as far as MPC74xx concerns. Looking in the spec (MPC7450 RISC Microprocessor Family Reference Manual, MPC7450UM Rev. 5 1/2005) section 3.4.1.5 L1 Instruction and Data Cache Flash Invalidation it says: Note that HID0[ICFI] and HID0[DCFI] must not both be set with the same mtspr instruction, due to the synchronization requirements described in Section 2.4.2.4.1, Context Synchronization. But in the code those two do set together. Also, the same section says: An isync must precede the setting of the HID0[ICFI] in order for the setting to take effect. But in the code, only 'sync' can be found. /* Enable caches for 603's, 604, 750 7400 */ setup_common_caches: mfspr r11,SPRN_HID0 andi. r0,r11,HID0_DCE ori r11,r11,HID0_ICE|HID0_DCE ori r8,r11,HID0_ICFI bne 1f /* don't invalidate the D-cache */ ori r8,r8,HID0_DCI /* unless it wasn't enabled */ 1:sync mtspr SPRN_HID0,r8/* enable and invalidate caches */ ^^^ Here we set both ICFI and DCFI in the same mtspr instruction. Also, no isync before setting ICFI. sync mtspr SPRN_HID0,r11 /* enable caches */ sync isync blr Please advice. Thanks. Yep, looks like a bug. How about a patch? :) Mark -- next part -- A non-text attachment was scrubbed... Name: cpu_setup_6xx.S Type: application/octet-stream Size: 10964 bytes Desc: cpu_setup_6xx.S Url : http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20060523/f995b3b6/attachment.obj
Setting ID cache enable in the same mtspr instruction
On Tue, May 23, 2006 at 12:55:46PM +0300, Assaf Hoffman wrote: Attached. Thanks. Er, how about a *patch* place inline (as in, not as an attachment). Thanks, Mark
Setting ID cache enable in the same mtspr instruction
On Mon, May 08, 2006 at 01:39:13PM +0300, Assaf Hoffman wrote: Hi, I think the implementation of setup_common_caches() in file cpu_setup_6xx.S; not according to the spec as far as MPC74xx concerns. Looking in the spec (MPC7450 RISC Microprocessor Family Reference Manual, MPC7450UM Rev. 5 1/2005) section 3.4.1.5 L1 Instruction and Data Cache Flash Invalidation it says: Note that HID0[ICFI] and HID0[DCFI] must not both be set with the same mtspr instruction, due to the synchronization requirements described in Section 2.4.2.4.1, Context Synchronization. But in the code those two do set together. Also, the same section says: An isync must precede the setting of the HID0[ICFI] in order for the setting to take effect. But in the code, only 'sync' can be found. /* Enable caches for 603's, 604, 750 7400 */ setup_common_caches: mfspr r11,SPRN_HID0 andi. r0,r11,HID0_DCE ori r11,r11,HID0_ICE|HID0_DCE ori r8,r11,HID0_ICFI bne 1f /* don't invalidate the D-cache */ ori r8,r8,HID0_DCI /* unless it wasn't enabled */ 1:sync mtspr SPRN_HID0,r8/* enable and invalidate caches */ ^^^ Here we set both ICFI and DCFI in the same mtspr instruction. Also, no isync before setting ICFI. sync mtspr SPRN_HID0,r11 /* enable caches */ sync isync blr Please advice. Thanks. Yep, looks like a bug. How about a patch? :) Mark
Setting ID cache enable in the same mtspr instruction
Hi, I think the implementation of setup_common_caches() in file cpu_setup_6xx.S; not according to the spec as far as MPC74xx concerns. Looking in the spec (MPC7450 RISC Microprocessor Family Reference Manual, MPC7450UM Rev. 5 1/2005) section 3.4.1.5 L1 Instruction and Data Cache Flash Invalidation it says: Note that HID0[ICFI] and HID0[DCFI] must not both be set with the same mtspr instruction, due to the synchronization requirements described in Section 2.4.2.4.1, Context Synchronization. But in the code those two do set together. Also, the same section says: An isync must precede the setting of the HID0[ICFI] in order for the setting to take effect. But in the code, only 'sync' can be found. /* Enable caches for 603's, 604, 750 7400 */ setup_common_caches: mfspr r11,SPRN_HID0 andi. r0,r11,HID0_DCE ori r11,r11,HID0_ICE|HID0_DCE ori r8,r11,HID0_ICFI bne 1f /* don't invalidate the D-cache */ ori r8,r8,HID0_DCI /* unless it wasn't enabled */ 1: sync mtspr SPRN_HID0,r8/* enable and invalidate caches */ ^^^ Here we set both ICFI and DCFI in the same mtspr instruction. Also, no isync before setting ICFI. sync mtspr SPRN_HID0,r11 /* enable caches */ sync isync blr Please advice. Thanks.
