[llvm-commits] [llvm] r47001 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Author: evancheng
Date: Tue Feb 12 01:59:45 2008
New Revision: 47001
URL: http://llvm.org/viewvc/llvm-project?rev=47001view=rev
Log:
Unbreak various insert_vector_elt and extract_vector_elt tests in presence of
SSE4.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=47001r1=47000r2=47001view=diff
==
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Feb 12 01:59:45 2008
@@ -698,11 +698,11 @@
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
if (Subtarget-is64Bit()) {
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Legal);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
}
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r46949 - in /llvm/trunk/lib/Target: TargetSelectionDAG.td X86/README-SSE.txt X86/X86ISelLowering.cpp X86/X86ISelLowering.h X86/X86InstrSSE.td
On Feb 10, 2008, at 8:19 PM, Nate Begeman wrote:
+
+ if (Subtarget-hasSSE41()) {
...
...
+if (Subtarget-is64Bit()) {
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Legal);
+
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
+}
+ }
I don't see the corresponding patterns? This breaks X86/illegal-
insert.ll on SSE4 capable machines. I am going to change them from
'legal' to 'custom' for now. Please fix if that's not right.
Thanks,
Evan
// We want to custom lower some of our intrinsics.
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
@@ -3655,10 +3682,34 @@
}
SDOperand
+X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op,
+SelectionDAG DAG) {
+ MVT::ValueType VT = Op.getValueType();
+ if (MVT::getSizeInBits(VT) == 8) {
+SDOperand Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32,
+Op.getOperand(0),
Op.getOperand(1));
+SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32,
Extract,
+DAG.getValueType(VT));
+return DAG.getNode(ISD::TRUNCATE, VT, Assert);
+ } else if (MVT::getSizeInBits(VT) == 16) {
+SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32,
+Op.getOperand(0),
Op.getOperand(1));
+SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32,
Extract,
+DAG.getValueType(VT));
+return DAG.getNode(ISD::TRUNCATE, VT, Assert);
+ }
+ return SDOperand();
+}
+
+
+SDOperand
X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op,
SelectionDAG DAG) {
if (!isaConstantSDNode(Op.getOperand(1)))
return SDOperand();
+ if (Subtarget-hasSSE41())
+return LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
+
MVT::ValueType VT = Op.getValueType();
// TODO: handle v16i8.
if (MVT::getSizeInBits(VT) == 16) {
@@ -3699,6 +3750,9 @@
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
DAG.getIntPtrConstant(0));
} else if (MVT::getSizeInBits(VT) == 64) {
+// FIXME: .td only matches this for 2 x f64, not 2 x i64 on
32b
+// FIXME: seems like this should be unnecessary if mov{h,l}pd
were taught
+//to match extract_elt for f64.
unsigned Idx = castConstantSDNode(Op.getOperand(1))-getValue();
if (Idx == 0)
return Op;
@@ -3724,9 +3778,47 @@
}
SDOperand
+X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDOperand Op,
SelectionDAG DAG){
+ MVT::ValueType VT = Op.getValueType();
+ MVT::ValueType EVT = MVT::getVectorElementType(VT);
+
+ SDOperand N0 = Op.getOperand(0);
+ SDOperand N1 = Op.getOperand(1);
+ SDOperand N2 = Op.getOperand(2);
+
+ if ((MVT::getSizeInBits(EVT) == 8) || (MVT::getSizeInBits(EVT) ==
16)) {
+unsigned Opc = (MVT::getSizeInBits(EVT) == 8) ? X86ISD::PINSRB
+ : X86ISD::PINSRW;
+// Transform it so it match pinsr{b,w} which expects a GR32 as
its second
+// argument.
+if (N1.getValueType() != MVT::i32)
+ N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
+if (N2.getValueType() != MVT::i32)
+ N2 = DAG.getIntPtrConstant(castConstantSDNode(N2)-
getValue());
+return DAG.getNode(Opc, VT, N0, N1, N2);
+ } else if (EVT == MVT::f32) {
+// Bits [7:6] of the constant are the source select. This will
always be
+// zero here. The DAG Combiner may combine an extract_elt
index into these
+// bits. For example (insert (extract, 3), 2) could be
matched by putting
+// the '3' into bits [7:6] of X86ISD::INSERTPS.
+// Bits [5:4] of the constant are the destination select. This
is the
+// value of the incoming immediate.
+// Bits [3:0] of the constant are the zero mask. The DAG
Combiner may
+// combine either bitwise AND or insert of float 0.0 to set
these bits.
+N2 = DAG.getIntPtrConstant(castConstantSDNode(N2)-getValue()
4);
+return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
+ }
+ return SDOperand();
+}
+
+SDOperand
X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG
DAG) {
MVT::ValueType VT = Op.getValueType();
MVT::ValueType EVT = MVT::getVectorElementType(VT);
+
+ if (Subtarget-hasSSE41())
+return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
+
if (EVT == MVT::i8)
return SDOperand();
@@ -5273,7 +5365,10 @@
case X86ISD::GlobalBaseReg: return X86ISD::GlobalBaseReg;
case X86ISD::Wrapper:return X86ISD::Wrapper;
case X86ISD::S2VEC: return X86ISD::S2VEC;
+ case X86ISD::PEXTRB: return X86ISD::PEXTRB;
case X86ISD::PEXTRW: return X86ISD::PEXTRW;
[llvm-commits] [llvm] r47012 - /llvm/trunk/utils/buildit/build_llvm
Author: dpatel Date: Tue Feb 12 12:20:50 2008 New Revision: 47012 URL: http://llvm.org/viewvc/llvm-project?rev=47012view=rev Log: Remove dead code. Modified: llvm/trunk/utils/buildit/build_llvm Modified: llvm/trunk/utils/buildit/build_llvm URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/buildit/build_llvm?rev=47012r1=47011r2=47012view=diff == --- llvm/trunk/utils/buildit/build_llvm (original) +++ llvm/trunk/utils/buildit/build_llvm Tue Feb 12 12:20:50 2008 @@ -157,8 +157,6 @@ fi cd $DEST_DIR$DEST_ROOT -lipo -extract ppc -extract i386 lib/LLVMlto.0.0.0.so -output lib/LLVMlto.0.0.0.so - # LTO is part of developer tools LTO_HOME=$DEST_DIR//Developer/usr if [ x$DEVELOPER_BIN != x ]; then ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r46827 - memoperands #1
Hi Chris, Thanks for the careful review! I've responded to parts of it already, and I'll be responding to more soon. On Feb 10, 2008, at 11:56 AM, Chris Lattner wrote: Instead of Size here, would it make sense to store an MVT? That would seem to capture strictly more information, thought I'm not sure if it's directly useful right now. This, and the question of whether to make LSBaseNode store a MemOperand instead of separate fields, are related. Also related is the question is what to do about the lowering of something like insert vector element where the element index isn't a constant and the target doesn't have an instruction to handle it. Legalize emits a store with a computed offset; what should the MemOperand for this look like? One way is to give it a larger size, to cover the known area over which the store might occur. This would mean it would use a different VT from the actual store, which could be confusing. Maybe it should have both a size and a VT. Dan ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47018 - in /llvm/trunk/test/CodeGen/X86: fold-mul-lohi.ll stride-nine-with-base-reg.ll stride-reuse.ll
Author: evancheng Date: Tue Feb 12 13:11:29 2008 New Revision: 47018 URL: http://llvm.org/viewvc/llvm-project?rev=47018view=rev Log: Don't mask the isel bug. Modified: llvm/trunk/test/CodeGen/X86/fold-mul-lohi.ll llvm/trunk/test/CodeGen/X86/stride-nine-with-base-reg.ll llvm/trunk/test/CodeGen/X86/stride-reuse.ll Modified: llvm/trunk/test/CodeGen/X86/fold-mul-lohi.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-mul-lohi.ll?rev=47018r1=47017r2=47018view=diff == --- llvm/trunk/test/CodeGen/X86/fold-mul-lohi.ll (original) +++ llvm/trunk/test/CodeGen/X86/fold-mul-lohi.ll Tue Feb 12 13:11:29 2008 @@ -1,5 +1,5 @@ ; RUN: llvm-as %s | llc -march=x86 | not grep lea -; RUN: llvm-as %s | llc -march=x86-64 -relocation-model=pic | not grep lea +; RUN: llvm-as %s | llc -march=x86-64 | not grep lea @B = external global [1000 x i8], align 32 @A = external global [1000 x i8], align 32 Modified: llvm/trunk/test/CodeGen/X86/stride-nine-with-base-reg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stride-nine-with-base-reg.ll?rev=47018r1=47017r2=47018view=diff == --- llvm/trunk/test/CodeGen/X86/stride-nine-with-base-reg.ll (original) +++ llvm/trunk/test/CodeGen/X86/stride-nine-with-base-reg.ll Tue Feb 12 13:11:29 2008 @@ -1,5 +1,5 @@ ; RUN: llvm-as %s | llc -march=x86 -relocation-model=static | grep lea | count 1 -; RUN: llvm-as %s | llc -march=x86-64 -relocation-model=pic | not grep lea +; RUN: llvm-as %s | llc -march=x86-64 | not grep lea ; For x86 there's an lea above the loop. In both cases, there shouldn't ; be any lea instructions inside the loop. Modified: llvm/trunk/test/CodeGen/X86/stride-reuse.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stride-reuse.ll?rev=47018r1=47017r2=47018view=diff == --- llvm/trunk/test/CodeGen/X86/stride-reuse.ll (original) +++ llvm/trunk/test/CodeGen/X86/stride-reuse.ll Tue Feb 12 13:11:29 2008 @@ -1,5 +1,5 @@ ; RUN: llvm-as %s | llc -march=x86 | not grep lea -; RUN: llvm-as %s | llc -march=x86-64 -relocation-model=pic | not grep lea +; RUN: llvm-as %s | llc -march=x86-64 | not grep lea @B = external global [1000 x float], align 32 @A = external global [1000 x float], align 32 ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47017 - /llvm/trunk/test/CodeGen/X86/peep-vector-extract-concat.ll
Author: evancheng
Date: Tue Feb 12 13:11:08 2008
New Revision: 47017
URL: http://llvm.org/viewvc/llvm-project?rev=47017view=rev
Log:
This test assumes no SSE4.1.
Modified:
llvm/trunk/test/CodeGen/X86/peep-vector-extract-concat.ll
Modified: llvm/trunk/test/CodeGen/X86/peep-vector-extract-concat.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/peep-vector-extract-concat.ll?rev=47017r1=47016r2=47017view=diff
==
--- llvm/trunk/test/CodeGen/X86/peep-vector-extract-concat.ll (original)
+++ llvm/trunk/test/CodeGen/X86/peep-vector-extract-concat.ll Tue Feb 12
13:11:08 2008
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s | llc -march=x86-64 | grep {shufps \$3, %xmm0, %xmm0}
+; RUN: llvm-as %s | llc -march=x86-64 -mattr=+sse2,-sse41 | grep {shufps
\$3, %xmm0, %xmm0}
define float @foo(8 x float %a) {
%c = extractelement 8 x float %a, i32 3
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47032 - /llvm/trunk/include/llvm/ADT/APInt.h
Author: djg
Date: Tue Feb 12 15:47:33 2008
New Revision: 47032
URL: http://llvm.org/viewvc/llvm-project?rev=47032view=rev
Log:
Change APInt::getBitsSet to accept a half-open range, where the
hiBit parameter marks the index one past the last desired set bit.
Modified:
llvm/trunk/include/llvm/ADT/APInt.h
Modified: llvm/trunk/include/llvm/ADT/APInt.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/APInt.h?rev=47032r1=47031r2=47032view=diff
==
--- llvm/trunk/include/llvm/ADT/APInt.h (original)
+++ llvm/trunk/include/llvm/ADT/APInt.h Tue Feb 12 15:47:33 2008
@@ -370,22 +370,22 @@
APInt getLoBits(uint32_t numBits) const;
/// Constructs an APInt value that has a contiguous range of bits set. The
- /// bits from loBit to hiBit will be set. All other bits will be zero. For
- /// example, with parameters(32, 0, 15) you would get 0x. If hiBit is
- /// less than loBit then the set bits wrap. For example, with
- /// parameters (32, 28, 3), you would get 0xF00F.
+ /// bits from loBit (inclusive) to hiBit (exclusive) will be set. All other
+ /// bits will be zero. For example, with parameters(32, 0, 16) you would get
+ /// 0x. If hiBit is less than loBit then the set bits wrap. For
+ /// example, with parameters (32, 28, 4), you would get 0xF00F.
/// @param numBits the intended bit width of the result
/// @param loBit the index of the lowest bit set.
/// @param hiBit the index of the highest bit set.
/// @returns An APInt value with the requested bits set.
/// @brief Get a value with a block of bits set.
static APInt getBitsSet(uint32_t numBits, uint32_t loBit, uint32_t hiBit) {
-assert(hiBit numBits hiBit out of range);
+assert(hiBit = numBits hiBit out of range);
assert(loBit numBits loBit out of range);
if (hiBit loBit)
- return getLowBitsSet(numBits, hiBit+1) |
+ return getLowBitsSet(numBits, hiBit) |
getHighBitsSet(numBits, numBits-loBit);
-return getLowBitsSet(numBits, hiBit-loBit+1).shl(loBit);
+return getLowBitsSet(numBits, hiBit-loBit).shl(loBit);
}
/// Constructs an APInt value that has the top hiBitsSet bits set.
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r46827 - memoperands #1
On Feb 12, 2008, at 11:27 AM, Dan Gohman wrote: Hi Chris, Thanks for the careful review! I've responded to parts of it already, and I'll be responding to more soon. Thanks Dan! On Feb 10, 2008, at 11:56 AM, Chris Lattner wrote: Instead of Size here, would it make sense to store an MVT? That would seem to capture strictly more information, thought I'm not sure if it's directly useful right now. This, and the question of whether to make LSBaseNode store a MemOperand instead of separate fields, are related. Ok, right. What is your opinion on this? Is there any reason not to give MemOperand a VT and then give LSBaseNode a MemOperand? Also related is the question is what to do about the lowering of something like insert vector element where the element index isn't a constant and the target doesn't have an instruction to handle it. Legalize emits a store with a computed offset; what should the MemOperand for this look like? One way is to give it a larger size, to cover the known area over which the store might occur. This would mean it would use a different VT from the actual store, which could be confusing. Maybe it should have both a size and a VT. Good question. This sort of thing is currently rare enough that it is probably fine to just use a null Value*, and have everything treat it conservatively. Would this be acceptable for now? -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r47027 - /llvm/trunk/docs/CFEBuildInstrs.html
On Feb 12, 2008, at 1:23 PM, Duncan Sands wrote: Author: baldrick Date: Tue Feb 12 15:22:58 2008 New Revision: 47027 URL: http://llvm.org/viewvc/llvm-project?rev=47027view=rev Log: Add instructions for building Ada and Fortran. Adjust mentions of gcc4 to be 4.0/4.2 agnostic. This file should probably be renamed tor GCCFEBuildInstrs.html... Thanks Duncan! Please go ahead and rename it (updating any references to it), but please put a stub page in place that links to the new one. -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47028 - /llvm/trunk/docs/CFEBuildInstrs.html
Author: baldrick Date: Tue Feb 12 15:28:39 2008 New Revision: 47028 URL: http://llvm.org/viewvc/llvm-project?rev=47028view=rev Log: Add more spacing. Modified: llvm/trunk/docs/CFEBuildInstrs.html Modified: llvm/trunk/docs/CFEBuildInstrs.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CFEBuildInstrs.html?rev=47028r1=47027r2=47028view=diff == --- llvm/trunk/docs/CFEBuildInstrs.html (original) +++ llvm/trunk/docs/CFEBuildInstrs.html Tue Feb 12 15:28:39 2008 @@ -87,10 +87,10 @@ pThere are some complications however:/p ol - liThe only platform for which the Ada front-end is known to build is + lipThe only platform for which the Ada front-end is known to build is 32 bit intel x86 running linux. It is unlikely to build for other - systems without some work./li - liThe build requires having a compiler that supports Ada, C and C++. + systems without some work./p/li + lipThe build requires having a compiler that supports Ada, C and C++. The Ada front-end is written in Ada so an Ada compiler is needed to build it. The LLVM parts of llvm-gcc are written in C++ so a C++ compiler is needed to build them. The rest of gcc is written in C. @@ -99,15 +99,15 @@ the rest of gcc). Otherwise it is possible to combine two versions of gcc, one that supports Ada and C (such as a href=http://libre.adacore.com/;GNAT GPL Edition/a) and another - which supports C++, see below./li + which supports C++, see below./p/li /ol pSupposing appropriate compilers are available, llvm-gcc with Ada support can be built using the following recipe:/p ol - liDownload the a href=http://llvm.org/releases/download.html;LLVM source/a - and unpack it: + lipDownload the a href=http://llvm.org/releases/download.html;LLVM source/a + and unpack it:/p div class=doc_code prewget http://llvm.org/releases/2.2/llvm-2.2.tar.gz @@ -115,17 +115,17 @@ mv llvm-2.2 llvm/pre /div - or a href=http://llvm.org/docs/GettingStarted.html#checkout;check out the - latest version from subversion/a: + por a href=http://llvm.org/docs/GettingStarted.html#checkout;check out the + latest version from subversion/a:/p div class=doc_code presvn co http://llvm.org/svn/llvm-project/llvm/trunk llvm/pre /div /li - liDownload the + lipDownload the a href=http://llvm.org/releases/download.html;llvm-gcc-4.2 source/a - and unpack it: + and unpack it:/p div class=doc_code prewget http://llvm.org/releases/2.2/llvm-gcc4.2-2.2.source.tar.gz @@ -133,16 +133,16 @@ mv llvm-gcc4.2-2.2.source llvm-gcc-4.2/pre /div - or a href=http://llvm.org/docs/GettingStarted.html#checkout;check out the - latest version from subversion/a: + por a href=http://llvm.org/docs/GettingStarted.html#checkout;check out the + latest version from subversion/a:/p div class=doc_code presvn co http://llvm.org/svn/llvm-project/llvm-gcc-4.2/trunk llvm-gcc-4.2/pre /div /li - liMake a build directory ttllvm-objects/tt for llvm and make it the - current directory: + lipMake a build directory ttllvm-objects/tt for llvm and make it the + current directory:/p div class=doc_code premkdir llvm-objects @@ -150,36 +150,36 @@ /div /li - liConfigure LLVM (here it is configured to install into tt/usr/local/tt): + lipConfigure LLVM (here it is configured to install into tt/usr/local/tt):/p div class=doc_code pre../llvm/configure --prefix=/usr/local/pre /div - If you have a multi-compiler setup and the C++ compiler is not the - default, then you can configure like this: + pIf you have a multi-compiler setup and the C++ compiler is not the + default, then you can configure like this:/p div class=doc_code preCXX=bPATH_TO_C++_COMPILER/b ../llvm/configure --prefix=/usr/local/pre /div /li - liBuild LLVM: + lipBuild LLVM:/p div class=doc_code premake/pre /div /li - liInstall LLVM (optional): + lipInstall LLVM (optional):/p div class=doc_code premake install/pre /div /li - liMake a build directory ttllvm-gcc-4.2-objects/tt for llvm-gcc and make it the - current directory: + lipMake a build directory ttllvm-gcc-4.2-objects/tt for llvm-gcc and make it the + current directory:/p div class=doc_code pre @@ -189,15 +189,15 @@ /div /li - liConfigure llvm-gcc (here it is configured to install into tt/usr/local/tt). + lipConfigure llvm-gcc (here it is configured to install into tt/usr/local/tt). Additional languages can be appended to the --enable-languages switch, - for example tt--enable-languages=ada,c,c++/tt. + for example tt--enable-languages=ada,c,c++/tt./p div class=doc_code pre../llvm-gcc-4.2/configure --prefix=/usr/local --enable-languages=ada,c --enable-checking
[llvm-commits] [llvm] r47027 - /llvm/trunk/docs/CFEBuildInstrs.html
Author: baldrick Date: Tue Feb 12 15:22:58 2008 New Revision: 47027 URL: http://llvm.org/viewvc/llvm-project?rev=47027view=rev Log: Add instructions for building Ada and Fortran. Adjust mentions of gcc4 to be 4.0/4.2 agnostic. This file should probably be renamed tor GCCFEBuildInstrs.html... Modified: llvm/trunk/docs/CFEBuildInstrs.html Modified: llvm/trunk/docs/CFEBuildInstrs.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CFEBuildInstrs.html?rev=47027r1=47026r2=47027view=diff == --- llvm/trunk/docs/CFEBuildInstrs.html (original) +++ llvm/trunk/docs/CFEBuildInstrs.html Tue Feb 12 15:22:58 2008 @@ -9,11 +9,11 @@ body div class=doc_title - Building the LLVM C/C++ Front-End + Building the LLVM GCC Front-End /div ol - lia href=#instructionsBuilding llvm-gcc 4 from Source/a/li + lia href=#instructionsBuilding llvm-gcc from Source/a/li lia href=#licenseLicense Information/a/li /ol @@ -23,25 +23,26 @@ !-- *** -- div class=doc_section - a name=instructionsBuilding llvm-gcc 4 from Source/a + a name=instructionsBuilding llvm-gcc from Source/a /div !-- *** -- div class=doc_text -pThis section describes how to aquire and build llvm-gcc4, which is based on -the GCC 4.0.1 front-end. This front-end supports C, C++, Objective-C, and -Objective-C++. Note that the instructions for building this front-end are -completely different (and much easier!) than those for building llvm-gcc3 in +pThis section describes how to acquire and build llvm-gcc 4.0 and 4.2, which are +based on the GCC 4.0.1/4.2.1 front-ends respectively. Both front-ends support C, +C++, Objective-C and Objective-C++. The 4.2 front-end also supports Ada and +Fortran to some extent. Note that the instructions for building these front-ends +are completely different (and much easier!) than those for building llvm-gcc3 in the past./p ol - lipRetrieve the appropriate llvm-gcc4-x.y.source.tar.gz archive from the + lipRetrieve the appropriate llvm-gcc4.x-y.z.source.tar.gz archive from the a href=http://llvm.org/releases/;llvm web site/a./p - pIt is also possible to download the sources of the llvm-gcc4 front end - from a read-only mirror using subversion. To check out the code the - first time use:/p + pIt is also possible to download the sources of the llvm-gcc front end + from a read-only mirror using subversion. To check out the 4.0 code + for first time use:/p div class=doc_code pre @@ -49,6 +50,14 @@ /pre /div +pTo check out the 4.2 code use:/p + +div class=doc_code +pre +svn co http://llvm.org/svn/llvm-project/llvm-gcc-4.2/trunk idst-directory/i +/pre +/div + pAfter that, the code can be be updated in the destination directory using:/p @@ -59,10 +68,174 @@ pThe mirror is brought up to date every evening./p/li liFollow the directions in the top-level ttREADME.LLVM/tt file for - up-to-date instructions on how to build llvm-gcc4./li + up-to-date instructions on how to build llvm-gcc. See below for building + with support for Ada or Fortran. +/ol + +/div + +!-- *** -- +div class=doc_section + a name=licenseBuilding the Ada front-end/a +/div + +div class=doc_text +pBuilding with support for Ada amounts to following the directions in the +top-level ttREADME.LLVM/tt file, adding ,ada to EXTRALANGS, for example: +ttEXTRALANGS=,ada/tt/p + +pThere are some complications however:/p + +ol + liThe only platform for which the Ada front-end is known to build is + 32 bit intel x86 running linux. It is unlikely to build for other + systems without some work./li + liThe build requires having a compiler that supports Ada, C and C++. + The Ada front-end is written in Ada so an Ada compiler is needed to + build it. The LLVM parts of llvm-gcc are written in C++ so a C++ + compiler is needed to build them. The rest of gcc is written in C. + Some linux distributions provide a version of gcc that supports all + three languages (the Ada part often comes as an add-on package to + the rest of gcc). Otherwise it is possible to combine two versions + of gcc, one that supports Ada and C (such as + a href=http://libre.adacore.com/;GNAT GPL Edition/a) and another + which supports C++, see below./li +/ol + +pSupposing appropriate compilers are available, llvm-gcc with Ada support can + be built using the following recipe:/p + +ol + liDownload the a href=http://llvm.org/releases/download.html;LLVM source/a + and unpack it: + +div class=doc_code +prewget http://llvm.org/releases/2.2/llvm-2.2.tar.gz +tar xzf llvm-2.2.tar.gz +mv llvm-2.2 llvm/pre +/div + + or a
Re: [llvm-commits] [llvm] r46949 - in /llvm/trunk/lib/Target: TargetSelectionDAG.td X86/README-SSE.txt X86/X86ISelLowering.cpp X86/X86ISelLowering.h X86/X86InstrSSE.td
On Feb 12, 2008, at 12:00 AM, Evan Cheng wrote:
On Feb 10, 2008, at 8:19 PM, Nate Begeman wrote:
+
+ if (Subtarget-hasSSE41()) {
...
...
+if (Subtarget-is64Bit()) {
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64,
Legal);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64,
Legal);
+
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64,
Legal);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64,
Legal);
+}
+ }
I don't see the corresponding patterns? This breaks X86/illegal-
insert.ll on SSE4 capable machines. I am going to change them from
'legal' to 'custom' for now. Please fix if that's not right.
Thanks,
Evan
Fix committed.
Nate
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47035 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86Instr64bit.td X86InstrFormats.td X86InstrSSE.td
Author: sampo
Date: Tue Feb 12 16:51:28 2008
New Revision: 47035
URL: http://llvm.org/viewvc/llvm-project?rev=47035view=rev
Log:
SSE4.1 64b integer insert/extract pattern support
Move formats into the formats file
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86Instr64bit.td
llvm/trunk/lib/Target/X86/X86InstrFormats.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=47035r1=47034r2=47035view=diff
==
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Feb 12 16:51:28 2008
@@ -636,7 +636,6 @@
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
-// Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones.
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
// Custom lower build_vector, vector_shuffle, and extract_vector_elt.
@@ -652,9 +651,12 @@
setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
+setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
-if (Subtarget-is64Bit())
+if (Subtarget-is64Bit()) {
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
+}
// Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++)
{
@@ -698,11 +700,8 @@
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
if (Subtarget-is64Bit()) {
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
-
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
}
}
Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=47035r1=47034r2=47035view=diff
==
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Tue Feb 12 16:51:28 2008
@@ -1271,8 +1271,41 @@
// X86-64 SSE4.1 Instructions
//===--===//
-// PEXTRB, unary, TA, 0x14, REX.W
-// PEXTRW, unary, TA, 0x15, REX.W
-// PEXTRQ, unary, TA, 0x16, REX.W
-// EXTRACTPS, unary, TA, 0x17, REX.W
-// PINSRQ, 2addr, binary, TA, 0x22, REX.W
+/// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
+multiclass SS41I_extract64bits8 opc, string OpcodeStr {
+ def rr : SS4AIopc, MRMSrcReg, (outs GR64:$dst),
+ (ins VR128:$src1, i32i8imm:$src2),
+ !strconcat(OpcodeStr,
+ \t{$src2, $src1, $dst|$dst, $src1, $src2}),
+ [(set GR64:$dst,
+ (extractelt (v2i64 VR128:$src1), imm:$src2))], OpSize,
REX_W;
+ def mr : SS4AIopc, MRMDestMem, (outs),
+ (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
+ !strconcat(OpcodeStr,
+ \t{$src2, $src1, $dst|$dst, $src1, $src2}),
+ [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
+ addr:$dst)], OpSize, REX_W;
+}
+
+defm PEXTRQ : SS41I_extract640x16, pextrq;
+
+let isTwoAddress = 1 in {
+ multiclass SS41I_insert64bits8 opc, string OpcodeStr {
+def rr : SS4AIopc, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
+ !strconcat(OpcodeStr,
+\t{$src3, $src2, $dst|$dst, $src2, $src3}),
+ [(set VR128:$dst,
+ (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))],
+ OpSize, REX_W;
+def rm : SS4AIopc, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
+ !strconcat(OpcodeStr,
+\t{$src3, $src2, $dst|$dst, $src2, $src3}),
+ [(set VR128:$dst,
+ (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
+
[llvm-commits] [llvm] r47047 - in /llvm/trunk/test/CodeGen/X86: coalescer-commute1.ll coalescer-commute2.ll coalescer-commute3.ll
Author: evancheng
Date: Tue Feb 12 21:23:53 2008
New Revision: 47047
URL: http://llvm.org/viewvc/llvm-project?rev=47047view=rev
Log:
New tests.
Added:
llvm/trunk/test/CodeGen/X86/coalescer-commute1.ll
llvm/trunk/test/CodeGen/X86/coalescer-commute2.ll
llvm/trunk/test/CodeGen/X86/coalescer-commute3.ll
Added: llvm/trunk/test/CodeGen/X86/coalescer-commute1.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/coalescer-commute1.ll?rev=47047view=auto
==
--- llvm/trunk/test/CodeGen/X86/coalescer-commute1.ll (added)
+++ llvm/trunk/test/CodeGen/X86/coalescer-commute1.ll Tue Feb 12 21:23:53 2008
@@ -0,0 +1,26 @@
+; RUN: llvm-as %s | llc -mtriple=i686-apple-darwin -mattr=+sse2
-coalescer-commute-instrs | not grep movaps
+; PR1877
+
[EMAIL PROTECTED] = weak global i32 0 ; i32* [#uses=1]
[EMAIL PROTECTED] = weak global float 0.00e+00 ; float*
[#uses=1]
+
+define void @runcont(i32* %source) nounwind {
+entry:
+ %tmp10 = load i32* @NNTOT, align 4 ; i32 [#uses=1]
+ br label %bb
+
+bb:; preds = %bb, %entry
+ %neuron.0 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ]
; i32 [#uses=2]
+ %thesum.0 = phi float [ 0.00e+00, %entry ], [ %tmp6, %bb ]
; float [#uses=1]
+ %tmp2 = getelementptr i32* %source, i32 %neuron.0 ;
i32* [#uses=1]
+ %tmp3 = load i32* %tmp2, align 4; i32 [#uses=1]
+ %tmp34 = sitofp i32 %tmp3 to float ; float [#uses=1]
+ %tmp6 = add float %tmp34, %thesum.0 ; float [#uses=2]
+ %indvar.next = add i32 %neuron.0, 1 ; i32 [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, %tmp10; i1 [#uses=1]
+ br i1 %exitcond, label %bb13, label %bb
+
+bb13: ; preds = %bb
+ volatile store float %tmp6, float* @G, align 4
+ ret void
+}
Added: llvm/trunk/test/CodeGen/X86/coalescer-commute2.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/coalescer-commute2.ll?rev=47047view=auto
==
--- llvm/trunk/test/CodeGen/X86/coalescer-commute2.ll (added)
+++ llvm/trunk/test/CodeGen/X86/coalescer-commute2.ll Tue Feb 12 21:23:53 2008
@@ -0,0 +1,21 @@
+; RUN: llvm-as %s | llc -mtriple=i686-apple-darwin -mattr=+sse2
-coalescer-commute-instrs | grep movsd | count 4
+
+define i32 @main(i32 %argc, i8** %argv) nounwind {
+entry:
+ br label %bb145.us.i.i
+
+bb145.us.i.i: ; preds = %bb145.us.i.i, %entry
+ %seed.3.reg2mem.0.us.i.i = phi double [ 0.00e+00, %entry ], [
%tmp9.i.us.i.i, %bb145.us.i.i ] ; double [#uses=1]
+ %tmp2.i13.us.i.i = mul double %seed.3.reg2mem.0.us.i.i, 1.680700e+04
; double [#uses=1]
+ %tmp3.i.us.i.i = add double %tmp2.i13.us.i.i, 1.00e+00
; double [#uses=1]
+ %tmp6.i15.us.i.i = call double @floor( double 0.00e+00 ) nounwind
readnone ; double [#uses=1]
+ %tmp7.i16.us.i.i = mul double %tmp6.i15.us.i.i, 0xC1DFFFC0
; double [#uses=1]
+ %tmp9.i.us.i.i = add double %tmp7.i16.us.i.i, %tmp3.i.us.i.i
; double [#uses=2]
+ %tmp5.i12.us.i.i = mul double %tmp9.i.us.i.i, 2.00e+00
; double [#uses=1]
+ %tmp6.i.us.i.i = fdiv double %tmp5.i12.us.i.i, 0x41DFFFC0
; double [#uses=1]
+ %tmp8.i.us.i.i = add double %tmp6.i.us.i.i, -1.00e+00
; double [#uses=1]
+ store double %tmp8.i.us.i.i, double* null, align 8
+ br label %bb145.us.i.i
+}
+
+declare double @floor(double) nounwind readnone
Added: llvm/trunk/test/CodeGen/X86/coalescer-commute3.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/coalescer-commute3.ll?rev=47047view=auto
==
--- llvm/trunk/test/CodeGen/X86/coalescer-commute3.ll (added)
+++ llvm/trunk/test/CodeGen/X86/coalescer-commute3.ll Tue Feb 12 21:23:53 2008
@@ -0,0 +1,24 @@
+; RUN: llvm-as %s | llc -mtriple=i686-apple-darwin -mattr=+sse2
-coalescer-commute-instrs | grep mov | count 6
+
+ %struct.quad_struct = type { i32, i32, %struct.quad_struct*,
%struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*,
%struct.quad_struct* }
+
+define fastcc i32 @perimeter(%struct.quad_struct* %tree, i32 %size) nounwind {
+entry:
+ switch i32 %size, label %UnifiedReturnBlock [
+i32 2, label %bb
+i32 0, label %bb50
+ ]
+
+bb:; preds = %entry
+ %tmp31 = tail call fastcc i32 @perimeter( %struct.quad_struct* null,
i32 0 ) nounwind ; i32 [#uses=1]
+ %tmp40 = tail call fastcc i32 @perimeter( %struct.quad_struct* null,
i32 0 ) nounwind ; i32 [#uses=1]
+ %tmp33 =
[llvm-commits] [llvm] r47046 - in /llvm/trunk: include/llvm/CodeGen/LiveIntervalAnalysis.h lib/CodeGen/SimpleRegisterCoalescing.cpp lib/CodeGen/SimpleRegisterCoalescing.h
Author: evancheng
Date: Tue Feb 12 21:01:43 2008
New Revision: 47046
URL: http://llvm.org/viewvc/llvm-project?rev=47046view=rev
Log:
Initial support for copy elimination by commuting its definition MI.
PR1877.
A3 = op A2 B0kill
..
B1 = A3 - this copy
..
= op A3 - more uses
==
B2 = op B0 A2kill
..
B1 = B2 - now an identify copy
..
= op B2 - more uses
This speeds up FreeBench/neural by 29%, Olden/bh by 12%, oopack_v1p8 by 53%.
Modified:
llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h
llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h
Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=47046r1=47045r2=47046view=diff
==
--- llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h Tue Feb 12 21:01:43
2008
@@ -213,6 +213,20 @@
}
}
+/// ReplaceMachineInstrInMaps - Replacing a machine instr with a new one in
+/// maps used by register allocator.
+void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
+ Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
+ if (mi2i != mi2iMap_.end()) {
+i2miMap_[mi2i-second/InstrSlots::NUM] = NewMI;
+Mi2IndexMap::const_iterator it = mi2iMap_.find(MI);
+assert(it != mi2iMap_.end() Invalid instruction!);
+unsigned Index = it-second;
+mi2iMap_.erase(MI);
+mi2iMap_[NewMI] = Index;
+ }
+}
+
BumpPtrAllocator getVNInfoAllocator() { return VNInfoAllocator; }
virtual void getAnalysisUsage(AnalysisUsage AU) const;
Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=47046r1=47045r2=47046view=diff
==
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Tue Feb 12 21:01:43 2008
@@ -36,6 +36,8 @@
using namespace llvm;
STATISTIC(numJoins, Number of interval joins performed);
+STATISTIC(numCommutes , Number of instruction commuting performed);
+STATISTIC(numExtends , Number of copies extended);
STATISTIC(numPeep , Number of identity moves eliminated after
coalescing);
STATISTIC(numAborts , Number of times interval joining aborted);
@@ -51,6 +53,10 @@
cl::desc(Use new coalescer heuristic),
cl::init(false));
+ static cl::optbool
+ CommuteDef(coalescer-commute-instrs,
+ cl::init(false),
Re: [llvm-commits] [llvm] r47042 - in /llvm/trunk: include/llvm/CodeGen/MachineRegisterInfo.h lib/CodeGen/MachineRegisterInfo.cpp
On Feb 12, 2008, at 6:45 PM, Evan Cheng wrote:
URL: http://llvm.org/viewvc/llvm-project?rev=47042view=rev
Log:
Added debugging routine dumpUses.
Nice.
+++ llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h Tue Feb 12
20:45:38 2008
+#ifndef NDEBUG
+ void dumpUses(unsigned RegNo) const;
+#endif
I wouldn't bother ifdefing this. This is a recipe for getting compile
errors later if someone forgets to #ifdef all uses.
+#ifndef NDEBUG
+void MachineRegisterInfo::dumpUses(unsigned Reg) const {
+ for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
+I.getOperand().getParent()-dump();
+}
+#endif
This can be simplified to: I-dump();
-Chris
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47045 - /llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
Author: sampo
Date: Tue Feb 12 20:58:33 2008
New Revision: 47045
URL: http://llvm.org/viewvc/llvm-project?rev=47045view=rev
Log:
Make register scavenging happy by not using a reg (CR0) that isn't defined
Modified:
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=47045r1=47044r2=47045view=diff
==
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Tue Feb 12 20:58:33 2008
@@ -293,7 +293,7 @@
// PowerPC Predicate operand. 20 = (05)|20 = always, CR0 is a dummy reg
// that doesn't matter.
def pred : PredicateOperandOtherVT, (ops imm, CRRC),
- (ops (i32 20), CR0) {
+ (ops (i32 20), (i32 zero_reg)) {
let PrintMethod = printPredicateOperand;
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47044 - in /llvm/trunk: include/llvm/CodeGen/LiveInterval.h lib/CodeGen/LiveInterval.cpp
Author: evancheng
Date: Tue Feb 12 20:48:26 2008
New Revision: 47044
URL: http://llvm.org/viewvc/llvm-project?rev=47044view=rev
Log:
- Added removeValNo() to remove all live ranges of a particular value#.
- removeRange() can now update value# information.
Modified:
llvm/trunk/include/llvm/CodeGen/LiveInterval.h
llvm/trunk/lib/CodeGen/LiveInterval.cpp
Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=47044r1=47043r2=47044view=diff
==
--- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Tue Feb 12 20:48:26 2008
@@ -299,12 +299,6 @@
/// contains the specified index, or end() if there is none.
iterator FindLiveRangeContaining(unsigned Idx);
-/// getOverlapingRanges - Given another live interval which is defined as a
-/// copy from this one, return a list of all of the live ranges where the
-/// two overlap and have different value numbers.
-void getOverlapingRanges(const LiveInterval Other, unsigned CopyIdx,
- std::vectorLiveRange* Ranges);
-
/// overlaps - Return true if the intersection of the two live intervals is
/// not empty.
bool overlaps(const LiveInterval other) const {
@@ -332,12 +326,16 @@
/// removeRange - Remove the specified range from this interval. Note that
/// the range must already be in this interval in its entirety.
-void removeRange(unsigned Start, unsigned End);
+void removeRange(unsigned Start, unsigned End, bool RemoveDeadValNo =
false);
-void removeRange(LiveRange LR) {
- removeRange(LR.start, LR.end);
+void removeRange(LiveRange LR, bool RemoveDeadValNo = false) {
+ removeRange(LR.start, LR.end, RemoveDeadValNo);
}
+/// removeValNo - Remove all the ranges defined by the specified value#.
+/// Also remove the value# from value# list.
+void removeValNo(VNInfo *ValNo);
+
/// getSize - Returns the sum of sizes of all the LiveRange's.
///
unsigned getSize() const;
Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=47044r1=47043r2=47044view=diff
==
--- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Tue Feb 12 20:48:26 2008
@@ -225,7 +225,8 @@
/// removeRange - Remove the specified range from this interval. Note that
/// the range must already be in this interval in its entirety.
-void LiveInterval::removeRange(unsigned Start, unsigned End) {
+void LiveInterval::removeRange(unsigned Start, unsigned End,
+ bool RemoveDeadValNo) {
// Find the LiveRange containing this span.
Ranges::iterator I = std::upper_bound(ranges.begin(), ranges.end(), Start);
assert(I != ranges.begin() Range is not in interval!);
@@ -234,9 +235,34 @@
Range is not entirely in interval!);
// If the span we are removing is at the start of the LiveRange, adjust it.
+ VNInfo *ValNo = I-valno;
if (I-start == Start) {
if (I-end == End) {
removeKills(I-valno, Start, End);
+ if (RemoveDeadValNo) {
+// Check if val# is dead.
+bool isDead = true;
+for (const_iterator II = begin(), EE = end(); II != EE; ++II)
+ if (II != I II-valno == ValNo) {
+isDead = false;
+break;
+ }
+if (isDead) {
+ // Now that ValNo is dead, remove it. If it is the largest value
+ // number, just nuke it (and any other deleted values neighboring
it),
+ // otherwise mark it as ~1U so it can be nuked later.
+ if (ValNo-id == getNumValNums()-1) {
+do {
+ VNInfo *VNI = valnos.back();
+ valnos.pop_back();
+ VNI-~VNInfo();
+} while (!valnos.empty() valnos.back()-def == ~1U);
+ } else {
+ValNo-def = ~1U;
+ }
+}
+ }
+
ranges.erase(I); // Removed the whole LiveRange.
} else
I-start = End;
@@ -246,7 +272,7 @@
// Otherwise if the span we are removing is at the end of the LiveRange,
// adjust the other way.
if (I-end == End) {
-removeKills(I-valno, Start, End);
+removeKills(ValNo, Start, End);
I-end = Start;
return;
}
@@ -256,9 +282,34 @@
I-end = Start; // Trim the old interval.
// Insert the new one.
- ranges.insert(next(I), LiveRange(End, OldEnd, I-valno));
+ ranges.insert(next(I), LiveRange(End, OldEnd, ValNo));
}
+/// removeValNo - Remove all the ranges defined by the specified value#.
+/// Also remove the value# from value# list.
+void LiveInterval::removeValNo(VNInfo *ValNo) {
+ if (empty())
[llvm-commits] [llvm] r47043 - in /llvm/trunk/lib: CodeGen/TargetInstrInfoImpl.cpp Target/PowerPC/PPCInstrInfo.cpp Target/X86/X86InstrInfo.cpp
Author: evancheng
Date: Tue Feb 12 20:46:49 2008
New Revision: 47043
URL: http://llvm.org/viewvc/llvm-project?rev=47043view=rev
Log:
commuteInstr() can now commute non-ssa machine instrs.
Modified:
llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=47043r1=47042r2=47043view=diff
==
--- llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Tue Feb 12 20:46:49 2008
@@ -23,8 +23,17 @@
This only knows how to commute register operands so far);
unsigned Reg1 = MI-getOperand(1).getReg();
unsigned Reg2 = MI-getOperand(2).getReg();
+ MachineOperand MO = MI-getOperand(0);
+ bool UpdateReg0 = MO.isReg() MO.getReg() == Reg1;
bool Reg1IsKill = MI-getOperand(1).isKill();
bool Reg2IsKill = MI-getOperand(2).isKill();
+ if (UpdateReg0) {
+// Must be two address instruction!
+assert(MI-getDesc().getOperandConstraint(0, TOI::TIED_TO)
+ Expecting a two-address instruction!);
+Reg2IsKill = false;
+MI-getOperand(0).setReg(Reg2);
+ }
MI-getOperand(2).setReg(Reg1);
MI-getOperand(1).setReg(Reg2);
MI-getOperand(2).setIsKill(Reg1IsKill);
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=47043r1=47042r2=47043view=diff
==
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Tue Feb 12 20:46:49 2008
@@ -147,10 +147,20 @@
// Op0 = (Op2 ~M) | (Op1 M)
// Swap op1/op2
+ unsigned Reg0 = MI-getOperand(0).getReg();
unsigned Reg1 = MI-getOperand(1).getReg();
unsigned Reg2 = MI-getOperand(2).getReg();
bool Reg1IsKill = MI-getOperand(1).isKill();
bool Reg2IsKill = MI-getOperand(2).isKill();
+ // If machine instrs are no longer in two-address forms, update
+ // destination register as well.
+ if (Reg0 == Reg1) {
+// Must be two address instruction!
+assert(MI-getDesc().getOperandConstraint(0, TOI::TIED_TO)
+ Expecting a two-address instruction!);
+MI-getOperand(0).setReg(Reg2);
+Reg2IsKill = false;
+ }
MI-getOperand(2).setReg(Reg1);
MI-getOperand(1).setReg(Reg2);
MI-getOperand(2).setIsKill(Reg1IsKill);
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=47043r1=47042r2=47043view=diff
==
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Feb 12 20:46:49 2008
@@ -1055,6 +1055,15 @@
unsigned C = MI-getOperand(2).getReg();
bool BisKill = MI-getOperand(1).isKill();
bool CisKill = MI-getOperand(2).isKill();
+// If machine instrs are no longer in two-address forms, update
+// destination register as well.
+if (A == B) {
+ // Must be two address instruction!
+ assert(MI-getDesc().getOperandConstraint(0, TOI::TIED_TO)
+ Expecting a two-address instruction!);
+ A = C;
+ CisKill = false;
+}
return BuildMI(get(Opc), A).addReg(C, false, false, CisKill)
.addReg(B, false, false, BisKill).addImm(Size-Amt);
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47042 - in /llvm/trunk: include/llvm/CodeGen/MachineRegisterInfo.h lib/CodeGen/MachineRegisterInfo.cpp
Author: evancheng
Date: Tue Feb 12 20:45:38 2008
New Revision: 47042
URL: http://llvm.org/viewvc/llvm-project?rev=47042view=rev
Log:
Added debugging routine dumpUses.
Modified:
llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h
llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp
Modified: llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h?rev=47042r1=47041r2=47042view=diff
==
--- llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h Tue Feb 12 20:45:38
2008
@@ -110,13 +110,22 @@
RegNo -= TargetRegisterInfo::FirstVirtualRegister;
return VRegInfo[RegNo].second;
}
+
+ /// getVRegDef - Return the machine instr that defines the specified virtual
+ /// register or null if none is found. This assumes that the code is in SSA
+ /// form, so there should only be one definition.
+ MachineInstr *getVRegDef(unsigned Reg) const;
+
+#ifndef NDEBUG
+ void dumpUses(unsigned RegNo) const;
+#endif
//======//
// Virtual Register Info
//======//
/// getRegClass - Return the register class of the specified virtual
register.
- const TargetRegisterClass *getRegClass(unsigned Reg) {
+ const TargetRegisterClass *getRegClass(unsigned Reg) const {
Reg -= TargetRegisterInfo::FirstVirtualRegister;
assert(Reg VRegInfo.size() Invalid vreg!);
return VRegInfo[Reg].first;
@@ -145,11 +154,6 @@
return VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1;
}
- /// getVRegDef - Return the machine instr that defines the specified virtual
- /// register or null if none is found. This assumes that the code is in SSA
- /// form, so there should only be one definition.
- MachineInstr *getVRegDef(unsigned Reg) const;
-
//======//
// Physical Register Use Info
Modified: llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp?rev=47042r1=47041r2=47042view=diff
==
--- llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp Tue Feb 12 20:45:38 2008
@@ -73,3 +73,11 @@
}
return 0;
}
+
+
+#ifndef NDEBUG
+void MachineRegisterInfo::dumpUses(unsigned Reg) const {
+ for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
+I.getOperand().getParent()-dump();
+}
+#endif
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47037 - in /llvm/trunk/lib/Target: ARM/ARMAsmPrinter.cpp X86/X86AsmPrinter.cpp
Author: johannes
Date: Tue Feb 12 17:35:09 2008
New Revision: 47037
URL: http://llvm.org/viewvc/llvm-project?rev=47037view=rev
Log:
__DATA not __DATA__ is the right segment name on darwin.
Spotted by Nick Kledzik.
Modified:
llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=47037r1=47036r2=47037view=diff
==
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Feb 12 17:35:09 2008
@@ -848,7 +848,7 @@
if (I-hasExternalLinkage()) {
if (const char *Directive = TAI-getZeroFillDirective()) {
O \t.globl\t name \n;
- O Directive __DATA__, __common, name ,
+ O Directive __DATA, __common, name ,
Size , Align \n;
continue;
}
Modified: llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp?rev=47037r1=47036r2=47037view=diff
==
--- llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp Tue Feb 12 17:35:09 2008
@@ -183,7 +183,7 @@
if (I-hasExternalLinkage()) {
if (const char *Directive = TAI-getZeroFillDirective()) {
O \t.globl name \n;
- O Directive __DATA__, __common, name ,
+ O Directive __DATA, __common, name ,
Size , Align \n;
continue;
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47036 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
Author: sampo
Date: Tue Feb 12 16:54:40 2008
New Revision: 47036
URL: http://llvm.org/viewvc/llvm-project?rev=47036view=rev
Log:
Remove some dead code
Modified:
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=47036r1=47035r2=47036view=diff
==
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Feb 12 16:54:40 2008
@@ -910,8 +910,8 @@
}
static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG DAG,
- unsigned *vRegs, unsigned ArgNo,
- unsigned NumGPRs, unsigned ArgOffset) {
+ unsigned ArgNo, unsigned NumGPRs,
+ unsigned ArgOffset) {
MachineFunction MF = DAG.getMachineFunction();
MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
SDOperand Root = Op.getOperand(0);
@@ -936,19 +936,16 @@
if (ObjGPRs == 1) {
unsigned VReg = RegInfo.createVirtualRegister(ARM::GPRRegClass);
RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
-vRegs[NumGPRs] = VReg;
ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
if (ObjectVT == MVT::f32)
ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue);
} else if (ObjGPRs == 2) {
unsigned VReg = RegInfo.createVirtualRegister(ARM::GPRRegClass);
RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
-vRegs[NumGPRs] = VReg;
ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
VReg = RegInfo.createVirtualRegister(ARM::GPRRegClass);
RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
-vRegs[NumGPRs+1] = VReg;
SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
assert(ObjectVT != MVT::i64 i64 should already be lowered);
@@ -987,11 +984,10 @@
SDOperand Root = Op.getOperand(0);
unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
unsigned NumGPRs = 0; // GPRs used for parameter passing.
- unsigned VRegs[4];
unsigned NumArgs = Op.Val-getNumValues()-1;
for (unsigned ArgNo = 0; ArgNo NumArgs; ++ArgNo)
-ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, VRegs, ArgNo,
+ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo,
NumGPRs, ArgOffset));
bool isVarArg = castConstantSDNode(Op.getOperand(2))-getValue() != 0;
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [poolalloc] r47023 - /poolalloc/trunk/include/poolalloc/PoolAllocate.h
Author: criswell
Date: Tue Feb 12 14:33:14 2008
New Revision: 47023
URL: http://llvm.org/viewvc/llvm-project?rev=47023view=rev
Log:
Added getPoolType() method which allows other passes to determine the type
of pool descriptors added by the Automatic Pool Allocation pass.
Modified:
poolalloc/trunk/include/poolalloc/PoolAllocate.h
Modified: poolalloc/trunk/include/poolalloc/PoolAllocate.h
URL:
http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/poolalloc/PoolAllocate.h?rev=47023r1=47022r2=47023view=diff
==
--- poolalloc/trunk/include/poolalloc/PoolAllocate.h (original)
+++ poolalloc/trunk/include/poolalloc/PoolAllocate.h Tue Feb 12 14:33:14 2008
@@ -205,6 +205,12 @@
GlobalVariable *CreateGlobalPool(unsigned RecSize, unsigned Alignment,
Instruction *IPHint = 0);
+ /// getPoolType - Return the type of a pool descriptor
+ const Type * getPoolType() {
+Type * VoidPtrType = PointerType::getUnqual(Type::Int8Ty);
+return ArrayType::get(VoidPtrType, 16);
+ }
+
private:
/// AddPoolPrototypes - Add prototypes for the pool functions to the
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [test-suite] r47025 - /test-suite/trunk/SingleSource/Benchmarks/Misc/oourafft.c
Author: laurov Date: Tue Feb 12 14:59:25 2008 New Revision: 47025 URL: http://llvm.org/viewvc/llvm-project?rev=47025view=rev Log: Reduce test size. Modified: test-suite/trunk/SingleSource/Benchmarks/Misc/oourafft.c Modified: test-suite/trunk/SingleSource/Benchmarks/Misc/oourafft.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Misc/oourafft.c?rev=47025r1=47024r2=47025view=diff == --- test-suite/trunk/SingleSource/Benchmarks/Misc/oourafft.c (original) +++ test-suite/trunk/SingleSource/Benchmarks/Misc/oourafft.c Tue Feb 12 14:59:25 2008 @@ -19,7 +19,7 @@ #define N 1024 #ifdef SMALL_PROBLEM_SIZE -#define TRIES 15000 +#define TRIES 5000 #else #define TRIES 15 #endif ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [test-suite] r47022 - in /test-suite/trunk/SingleSource/Benchmarks/Misc-C++: ray.cpp sphereflake.cpp
Author: laurov
Date: Tue Feb 12 14:16:49 2008
New Revision: 47022
URL: http://llvm.org/viewvc/llvm-project?rev=47022view=rev
Log:
Define SMALL_PROBLEM_SIZE.
Modified:
test-suite/trunk/SingleSource/Benchmarks/Misc-C++/ray.cpp
test-suite/trunk/SingleSource/Benchmarks/Misc-C++/sphereflake.cpp
Modified: test-suite/trunk/SingleSource/Benchmarks/Misc-C++/ray.cpp
URL:
http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Misc-C%2B%2B/ray.cpp?rev=47022r1=47021r2=47022view=diff
==
--- test-suite/trunk/SingleSource/Benchmarks/Misc-C++/ray.cpp (original)
+++ test-suite/trunk/SingleSource/Benchmarks/Misc-C++/ray.cpp Tue Feb 12
14:16:49 2008
@@ -101,8 +101,14 @@
return new Group(Sphere(c, 3*r), child);
}
+#ifdef SMALL_PROBLEM_SIZE
+#define TEST_SIZE 128
+#else
+#define TEST_SIZE 512
+#endif
+
int main(int argc, char *argv[]) {
- int level = 6, n = 512, ss = 4;
+ int level = 6, n = TEST_SIZE, ss = 4;
if (argc == 2) level = atoi(argv[1]);
Vec light = unitise(Vec(-1, -3, 2));
Scene *s(create(level, Vec(0, -1, 0), 1));
Modified: test-suite/trunk/SingleSource/Benchmarks/Misc-C++/sphereflake.cpp
URL:
http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Misc-C%2B%2B/sphereflake.cpp?rev=47022r1=47021r2=47022view=diff
==
--- test-suite/trunk/SingleSource/Benchmarks/Misc-C++/sphereflake.cpp (original)
+++ test-suite/trunk/SingleSource/Benchmarks/Misc-C++/sphereflake.cpp Tue Feb
12 14:16:49 2008
@@ -162,8 +162,14 @@
return n;
}
+#ifdef SMALL_PROBLEM_SIZE
+#define TEST_SIZE 256
+#else
+#define TEST_SIZE 1024
+#endif
+
int main(int argc,char*argv[]){
- enum{ w = 1024, h = w }; /* resolution */
+ enum{ w = TEST_SIZE, h = w }; /* resolution */
const int lvl=(argc==2?std::max(atoi(argv[1]),2):6);
int count=childs, dec=lvl;
while(--dec 1) count=(count*childs)+childs;
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47020 - /llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp
Author: evancheng Date: Tue Feb 12 13:25:12 2008 New Revision: 47020 URL: http://llvm.org/viewvc/llvm-project?rev=47020view=rev Log: Revert r46916 PPCTargetAsmInfo.cpp. Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp?rev=47020r1=47019r2=47020view=diff == --- llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp Tue Feb 12 13:25:12 2008 @@ -92,8 +92,8 @@ CommentString = #; GlobalPrefix = ; PrivateGlobalPrefix = ; - ConstantPoolSection = \t.section .rodata\t; - JumpTableDataSection = .section .rodata; + ConstantPoolSection = \t.section .rodata.cst4\t; + JumpTableDataSection = .section .rodata.cst4; CStringSection = \t.section\t.rodata; StaticCtorsSection = .section\t.ctors,\aw\,@progbits; StaticDtorsSection = .section\t.dtors,\aw\,@progbits; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47019 - /llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Author: evancheng
Date: Tue Feb 12 13:20:46 2008
New Revision: 47019
URL: http://llvm.org/viewvc/llvm-project?rev=47019view=rev
Log:
Only using x86-64 rip relative addressing in non-staic mode?
Modified:
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=47019r1=47018r2=47019view=diff
==
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Feb 12 13:20:46 2008
@@ -679,21 +679,25 @@
GlobalValue *GV = G-getGlobal();
AM.GV = GV;
AM.Disp += G-getOffset();
-AM.isRIPRel = is64Bit;
+AM.isRIPRel = TM.getRelocationModel() != Reloc::Static
+ Subtarget-isPICStyleRIPRel();
return false;
} else if (ConstantPoolSDNode *CP = dyn_castConstantPoolSDNode(N0)) {
AM.CP = CP-getConstVal();
AM.Align = CP-getAlignment();
AM.Disp += CP-getOffset();
-AM.isRIPRel = is64Bit;
+AM.isRIPRel = TM.getRelocationModel() != Reloc::Static
+ Subtarget-isPICStyleRIPRel();
return false;
} else if (ExternalSymbolSDNode *S =dyn_castExternalSymbolSDNode(N0)) {
AM.ES = S-getSymbol();
-AM.isRIPRel = is64Bit;
+AM.isRIPRel = TM.getRelocationModel() != Reloc::Static
+ Subtarget-isPICStyleRIPRel();
return false;
} else if (JumpTableSDNode *J = dyn_castJumpTableSDNode(N0)) {
AM.JT = J-getIndex();
-AM.isRIPRel = is64Bit;
+AM.isRIPRel = TM.getRelocationModel() != Reloc::Static
+ Subtarget-isPICStyleRIPRel();
return false;
}
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-www/pubs/index.html
Changes in directory llvm-www/pubs: index.html updated: 1.63 - 1.64 --- Log message: add to index page --- Diffs of the changes: (+3 -0) index.html |3 +++ 1 files changed, 3 insertions(+) Index: llvm-www/pubs/index.html diff -u llvm-www/pubs/index.html:1.63 llvm-www/pubs/index.html:1.64 --- llvm-www/pubs/index.html:1.63 Thu Jan 24 16:53:51 2008 +++ llvm-www/pubs/index.htmlTue Feb 12 13:36:35 2008 @@ -2,6 +2,9 @@ div class=www_sectiontitleLLVM Related Publications/div ol +lia href=2008-02-23-TRANSACT-TangerObjBased.htmlMaking Object-Based STM Practical in Unmanaged Environments/abr +Torvald Riegel and Diogo Becker de Brumbr +iACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2008)/i, Salt Lake City, Utah, 2008/li lia href=2008-CGO-DagISel.htmlNear-Optimal Instruction Selection on DAGs/abr David Ryan Koes and Seth Copen Goldsteinbr ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-www/pubs/2008-02-23-TRANSACT-TangerObjBased.html 2008-02-23-TRANSACT-TangerObjBased.pdf
Changes in directory llvm-www/pubs:
2008-02-23-TRANSACT-TangerObjBased.html added (r1.1)
2008-02-23-TRANSACT-TangerObjBased.pdf added (r1.1)
---
Log message:
new paper from Torvald Riegel
---
Diffs of the changes: (+49 -0)
2008-02-23-TRANSACT-TangerObjBased.html | 49
2008-02-23-TRANSACT-TangerObjBased.pdf |0
2 files changed, 49 insertions(+)
Index: llvm-www/pubs/2008-02-23-TRANSACT-TangerObjBased.html
diff -c /dev/null llvm-www/pubs/2008-02-23-TRANSACT-TangerObjBased.html:1.1
*** /dev/null Tue Feb 12 13:34:26 2008
--- llvm-www/pubs/2008-02-23-TRANSACT-TangerObjBased.html Tue Feb 12
13:34:15 2008
***
*** 0
--- 1,49
+ !DOCTYPE HTML PUBLIC -//W3C//DTD HTML 4.01 Transitional//EN
+ html
+ head
+ meta http-equiv=Content-Type content=text/html; charset=UTF-8 /
+ link rel=stylesheet href=../llvm.css type=text/css media=screen /
+ titleTransactifying Applications Using an Open Compiler Framework/title
+ /head
+ body
+
+ div class=pub_title
+ Making Object-Based STM Practical in Unmanaged Environments
+ /div
+ div class=pub_author
+ Torvald Riegel and Diogo Becker de Brum
+ /div
+
+ h2Abstract:/h2
+ blockquote
+ Current transactifying compilers for unmanaged environments (e.g., systems
software written
+ in C/C++) target only word-based software transactional memories (STMs)
because the
+ compiler cannot easily infer whether it is safe to transform a transactional
access to a
+ certain memory location in an object-based way. To use object-based STMs in
these
+ environments, programmers must use explicit calls to the STM or use a
restricted language
+ dialect, both of which are not practical. In this paper, we show how an
existing pointer
+ analysis can be used to let a transactifying compiler for C/C++ use
object-based accesses
+ whenever this is possible and safe, while falling back to word-based accesses
otherwise.
+ Programmers do not need to provide any annotations and do not have to use a
restricted
+ language. Our evaluation also shows that an object-based STM can be
significantly faster
+ than a word-based STM with an otherwise identical design and implementation,
even if the
+ parameters of the latter have been tuned.
+ /blockquote
+
+ h2Bibtex:/h2
+ pre
+ @inproceedings{Riegel2008objbased,
+ author = {{T}orvald {R}iegel and {B}ecker de {B}rum, {D}iogo},
+ title = {{M}aking {O}bject-{B}ased {STM} {P}ractical in {U}nmanaged
{E}nvironments},
+ booktitle = {{TRANSACT} 2008},
+ year = {2008},
+ }
+ /pre
+
+ h2Download:/h2
+ ul
+ lia href=2008-02-23-TRANSACT-TangerObjBased.pdfMaking Object-Based
STM Practical in Unmanaged Environments/a (PDF)/li
+ /ul
+
+ /body
+ /html
Index: llvm-www/pubs/2008-02-23-TRANSACT-TangerObjBased.pdf
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r47046 - in /llvm/trunk: include/llvm/CodeGen/LiveIntervalAnalysis.h lib/CodeGen/SimpleRegisterCoalescing.cpp lib/CodeGen/SimpleRegisterCoalescing.h
On Feb 12, 2008, at 7:01 PM, Evan Cheng wrote:
Author: evancheng
Date: Tue Feb 12 21:01:43 2008
New Revision: 47046
URL: http://llvm.org/viewvc/llvm-project?rev=47046view=rev
Log:
Initial support for copy elimination by commuting its definition MI.
Yay, thanks for tackling this Evan!
This speeds up FreeBench/neural by 29%, Olden/bh by 12%, oopack_v1p8
by 53%.
Very nice, does it also help shootout/fib?
+/// ReplaceMachineInstrInMaps - Replacing a machine instr with
a new one in
+/// maps used by register allocator.
+void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr
*NewMI) {
+ Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
+ if (mi2i != mi2iMap_.end()) {
Please change this to:
if (mi2i == mi2iMap_.end())
return;
...
Just to avoid indentation.
+i2miMap_[mi2i-second/InstrSlots::NUM] = NewMI;
+Mi2IndexMap::const_iterator it = mi2iMap_.find(MI);
+assert(it != mi2iMap_.end() Invalid instruction!);
+unsigned Index = it-second;
+mi2iMap_.erase(MI);
This would avoid another lookup if you used .erase(it);
+bool
SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval IntA,
+
LiveInterval IntB,
+
MachineInstr *CopyMI) {
...
+ // Get the location that B is defined at. Two options: either
this value has
+ // an unknown definition point or it is defined at CopyIdx. If
unknown, we
+ // can't process it.
+ if (!BValNo-reg) return false;
+ assert(BValNo-def == CopyIdx Copy doesn't define the value?);
+
+ // AValNo is the value number in A that defines the copy, A3 in
the example.
+ LiveInterval::iterator ALR =
IntA.FindLiveRangeContaining(CopyIdx-1);
+ VNInfo *AValNo = ALR-valno;
This idiom happens a lot in the preexisting code. Please use:
VNInfo *AValNo = IntA.FindLiveRangeContaining(CopyIdx-1)-valno;
Or better yet, add a new method that returns valno directly.
+ int Idx = -1;
Idx is too generic of a name for a variable with this long of
lifetime, please name it something more descriptive. What type of idx
is it?
+ for (unsigned i = 0, e = DefMI-getNumOperands(); i != e; ++i) {
This loop needs a comment. What are you trying to find with this
loop? Maybe it should be moved out to its own function which just
returns idx? This would force you to name it, which would describe
what it does :)
+MachineOperand MO = DefMI-getOperand(i);
+if (!MO.isRegister()) continue;
+unsigned Reg = MO.getReg();
+if (Reg TargetRegisterInfo::isVirtualRegister(Reg)) {
How about:
if (Reg == 0 || !isvreg) continue;
+ if (rep(Reg) == IntA.reg) {
+// If the dest register comes from an interval other than
IntA, we
+// can't handle this.
+if (Reg != IntA.reg)
+ return false;
I must be missing something here, how do you know this is a def operand?
Another random question unrelated to this code: now that we have
efficient RAUW, can we eliminate the 'rep' mapping stuff and just
RAUW vregs as they are coallesced?
+continue;
+ }
+ if (Idx != -1)
+// FIXME: Being overly careful here. We just need to figure
out the
+// which register operand will become the new def.
+return false;
+ Idx = i;
+}
+ }
+ if (Idx == -1)
+// Something like %reg1024 = add %reg1024, %reg1024
+return false;
+
+ MachineOperand MO = DefMI-getOperand(Idx);
+ unsigned NewReg = MO.getReg();
+ if (rep(NewReg) != IntB.reg || !MO.isKill())
+return false;
This logic would make more sense if I knew what Idx indicates and why
you're rejecting these cases :). Also, MO has a long lifetime, please
name it DefMO or something else more descriptive.
+ // Make sure there are no other definitions of IntB that would
reach the
+ // uses which the new definition can reach.
+ for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
+ AI != AE; ++AI) {
+if (AI-valno != AValNo) continue;
+LiveInterval::Ranges::iterator BI =
+ std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI-
start);
+if (BI != IntB.ranges.begin())
+ --BI;
+for (; BI != IntB.ranges.end() AI-end = BI-start; ++BI) {
+ if (BI-valno == BLR-valno)
+continue;
+ if (BI-start = AI-start BI-end AI-start)
+return false;
+ if (BI-start AI-start BI-start AI-end)
+return false;
+}
Please split this out into a static function or a method on
liveinterval.
+ }
+
+ // Commute def machine instr.
How about: at this point we have decided that it is legal to do this
transformation. Start by commuting the instruction.
+ MachineBasicBlock *MBB = DefMI-getParent();
+ MachineInstr *NewMI = tii_-commuteInstruction(DefMI);
+ if (NewMI
[llvm-commits] [llvm] r47015 - /llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
Author: djg
Date: Tue Feb 12 12:52:52 2008
New Revision: 47015
URL: http://llvm.org/viewvc/llvm-project?rev=47015view=rev
Log:
Add a doxygen comment for SrcValueSDNode, to make its purpose
clear and to clarify how it differs from MemOperandSDNode.
Modified:
llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=47015r1=47014r2=47015view=diff
==
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Tue Feb 12 12:52:52 2008
@@ -1396,6 +1396,14 @@
}
};
+/// SrcValueSDNode - An SDNode that holds an arbitrary LLVM IR Value. This is
+/// used when the SelectionDAG needs to make a simple reference to something
+/// in the LLVM IR representation.
+///
+/// Note that this is not used for carrying alias information; that is done
+/// with MemOperandSDNode, which includes a Value which is required to be a
+/// pointer, and several other fields specific to memory references.
+///
class SrcValueSDNode : public SDNode {
const Value *V;
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r46827 - MemOperands #2/2
On Feb 12, 2008, at 10:38 AM, Dan Gohman wrote:
On Feb 12, 2008, at 12:12 AM, Evan Cheng wrote:
+
+// Save loads/stores matched by a pattern.
+if (!N-isLeaf() N-getName().empty()) {
+ std::string EnumName = N-getOperator()-
getValueAsString(Opcode);
+ if (EnumName == ISD::LOAD ||
+ EnumName == ISD::STORE) {
+LSI.push_back(RootName);
+ }
+}
This doesn't seem safe. What if the pattern involves target
specific load / store nodes? Perhaps you can add a node property,
e.g. SDNPHasMemOp, to tell tblgen which operands would add memory
operands to the resulting target node?
The problem is that this code really needs an LSBaseSDNode. A target-
specific
load/store won't have that. I'm looking for better ways to solve
this. One way is
to require all target-specific load/store instructions to have
patterns, and that
they must use ld/st/ist to describe their memory references. I'm not
familiar enough
with all the targets yet to know if that's feasible.
Ok, then please just add a SDNPHasMemOp and mark ld, st, and ist with
it. tblgen should look for that property instead of EnumName. I don't
think there are target specific load / store nodes that might be
impacted at this tme.
Evan
Dan
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r46827 - MemOperands #2/2
On Feb 12, 2008, at 12:12 AM, Evan Cheng wrote:
+
+// Save loads/stores matched by a pattern.
+if (!N-isLeaf() N-getName().empty()) {
+ std::string EnumName = N-getOperator()-
getValueAsString(Opcode);
+ if (EnumName == ISD::LOAD ||
+ EnumName == ISD::STORE) {
+LSI.push_back(RootName);
+ }
+}
This doesn't seem safe. What if the pattern involves target specific
load / store nodes? Perhaps you can add a node property, e.g.
SDNPHasMemOp, to tell tblgen which operands would add memory
operands to the resulting target node?
The problem is that this code really needs an LSBaseSDNode. A target-
specific
load/store won't have that. I'm looking for better ways to solve this.
One way is
to require all target-specific load/store instructions to have
patterns, and that
they must use ld/st/ist to describe their memory references. I'm not
familiar enough
with all the targets yet to know if that's feasible.
Dan
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r47006 - /llvm/trunk/lib/Transforms/Scalar/GVN.cpp
Hi Eli,
Could you add a regression test from the testcase in the PR, to
verify that the load is optimized out?
Thanks,
Dan
On Feb 12, 2008, at 4:08 AM, Eli Friedman wrote:
Author: efriedma
Date: Tue Feb 12 06:08:14 2008
New Revision: 47006
URL: http://llvm.org/viewvc/llvm-project?rev=47006view=rev
Log:
Fix for bug 1996: optimize out loads of undef. This code basically
just
checks for a malloc/alloca immediately followed by a load.
Modified:
llvm/trunk/lib/Transforms/Scalar/GVN.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=47006r1=47005r2=47006view=diff
=
=
=
=
=
=
=
=
==
--- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Tue Feb 12 06:08:14 2008
@@ -1010,7 +1010,34 @@
dep = MD.getDependency(L, dep);
}
}
-
+
+ if (dep != MemoryDependenceAnalysis::None
+ dep != MemoryDependenceAnalysis::NonLocal
+ isaAllocationInst(dep)) {
+// Check that this load is actually from the
+// allocation we found
+Value* v = L-getOperand(0);
+while (true) {
+ if (BitCastInst *BC = dyn_castBitCastInst(v))
+v = BC-getOperand(0);
+ else if (GetElementPtrInst *GEP =
dyn_castGetElementPtrInst(v))
+v = GEP-getOperand(0);
+ else
+break;
+}
+if (v == dep) {
+ // If this load depends directly on an allocation, there isn't
+ // anything stored there; therefore, we can optimize this load
+ // to undef.
+ MD.removeInstruction(L);
+
+ L-replaceAllUsesWith(UndefValue::get(L-getType()));
+ toErase.push_back(L);
+ deletedLoad = true;
+ NumGVNLoad++;
+}
+ }
+
if (!deletedLoad)
last = L;
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [test-suite] r47011 - /test-suite/trunk/MultiSource/Benchmarks/Prolangs-C/plot2fig/plot.c
Author: laurov Date: Tue Feb 12 12:16:07 2008 New Revision: 47011 URL: http://llvm.org/viewvc/llvm-project?rev=47011view=rev Log: Fix test case. Modified: test-suite/trunk/MultiSource/Benchmarks/Prolangs-C/plot2fig/plot.c Modified: test-suite/trunk/MultiSource/Benchmarks/Prolangs-C/plot2fig/plot.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/Prolangs-C/plot2fig/plot.c?rev=47011r1=47010r2=47011view=diff == --- test-suite/trunk/MultiSource/Benchmarks/Prolangs-C/plot2fig/plot.c (original) +++ test-suite/trunk/MultiSource/Benchmarks/Prolangs-C/plot2fig/plot.c Tue Feb 12 12:16:07 2008 @@ -21,7 +21,7 @@ to draw the graphics. */ #include stdio.h -#include /usr/include/stdlib.h +#include stdlib.h #include ctype.h #ifdef sequent #include strings.h ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47031 - /llvm/trunk/docs/CFEBuildInstrs.html
Author: baldrick Date: Tue Feb 12 15:40:21 2008 New Revision: 47031 URL: http://llvm.org/viewvc/llvm-project?rev=47031view=rev Log: Note that these instructions are for x86-32 linux (the only platform on which the Ada compiler even builds). Modified: llvm/trunk/docs/CFEBuildInstrs.html Modified: llvm/trunk/docs/CFEBuildInstrs.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CFEBuildInstrs.html?rev=47031r1=47030r2=47031view=diff == --- llvm/trunk/docs/CFEBuildInstrs.html (original) +++ llvm/trunk/docs/CFEBuildInstrs.html Tue Feb 12 15:40:21 2008 @@ -103,7 +103,7 @@ /ol pSupposing appropriate compilers are available, llvm-gcc with Ada support can - be built using the following recipe:/p + be built on an x86-32 linux box using the following recipe:/p ol lipDownload the a href=http://llvm.org/releases/download.html;LLVM source/a ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r46916 - /llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp
Evan Cheng wrote: Any idea what the differences mean? .rodata.cst4 makes it possible to be merged? Was there a reason to change it or than to match gcc? You're right, this is a bad patch. I changed it because I was getting errors in the assembler with it, but then, that's not what changed to make the changes go away. You can revert the patch or I'll revert it later. The problem goes away when EH is set to disabled. I'll collect the errors and email them later today. Nick Thanks, Evan On Feb 9, 2008, at 4:03 PM, Nick Lewycky wrote: Author: nicholas Date: Sat Feb 9 18:03:54 2008 New Revision: 46916 URL: http://llvm.org/viewvc/llvm-project?rev=46916view=rev Log: Match GCC's behaviour for these sections. Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp?rev=46916r1=46915r2=46916view=diff = = = = = = = = == --- llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp Sat Feb 9 18:03:54 2008 @@ -92,8 +92,8 @@ CommentString = #; GlobalPrefix = ; PrivateGlobalPrefix = ; - ConstantPoolSection = \t.section .rodata.cst4\t; - JumpTableDataSection = .section .rodata.cst4; + ConstantPoolSection = \t.section .rodata\t; + JumpTableDataSection = .section .rodata; CStringSection = \t.section\t.rodata; StaticCtorsSection = .section\t.ctors,\aw\,@progbits; StaticDtorsSection = .section\t.dtors,\aw\,@progbits; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47026 - in /llvm/trunk: include/llvm/Analysis/MemoryDependenceAnalysis.h lib/Analysis/MemoryDependenceAnalysis.cpp lib/Transforms/Scalar/GVN.cpp test/Transforms/GVN/memcpy.ll
Author: resistor
Date: Tue Feb 12 15:15:18 2008
New Revision: 47026
URL: http://llvm.org/viewvc/llvm-project?rev=47026view=rev
Log:
Re-apply the patch to improve the optimizations of memcpy's, with several
bugs fixed. This now passes PPC bootstrap.
Modified:
llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h
llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp
llvm/trunk/lib/Transforms/Scalar/GVN.cpp
llvm/trunk/test/Transforms/GVN/memcpy.ll
Modified: llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h?rev=47026r1=47025r2=47026view=diff
==
--- llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h (original)
+++ llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h Tue Feb 12
15:15:18 2008
@@ -100,6 +100,11 @@
/// updating the dependence of instructions that previously depended on it.
void removeInstruction(Instruction* rem);
+/// dropInstruction - Remove an instruction from the analysis, making
+/// absolutely conservative assumptions when updating the cache. This is
+/// useful, for example when an instruction is changed rather than removed.
+void dropInstruction(Instruction* drop);
+
private:
Instruction* getCallSiteDependency(CallSite C, Instruction* start,
BasicBlock* block);
Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=47026r1=47025r2=47026view=diff
==
--- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Tue Feb 12 15:15:18
2008
@@ -457,6 +457,46 @@
return NonLocal;
}
+/// dropInstruction - Remove an instruction from the analysis, making
+/// absolutely conservative assumptions when updating the cache. This is
+/// useful, for example when an instruction is changed rather than removed.
+void MemoryDependenceAnalysis::dropInstruction(Instruction* drop) {
+ depMapType::iterator depGraphEntry = depGraphLocal.find(drop);
+ if (depGraphEntry != depGraphLocal.end())
+reverseDep[depGraphEntry-second.first].erase(drop);
+
+ // Drop dependency information for things that depended on this instr
+ SmallPtrSetInstruction*, 4 set = reverseDep[drop];
+ for (SmallPtrSetInstruction*, 4::iterator I = set.begin(), E = set.end();
+ I != E; ++I)
+depGraphLocal.erase(*I);
+
+ depGraphLocal.erase(drop);
+ reverseDep.erase(drop);
+
+ for (DenseMapBasicBlock*, Value*::iterator DI =
+ depGraphNonLocal[drop].begin(), DE = depGraphNonLocal[drop].end();
+ DI != DE; ++DI)
+if (DI-second != None)
+ reverseDepNonLocal[DI-second].erase(drop);
+
+ if (reverseDepNonLocal.count(drop)) {
+SmallPtrSetInstruction*, 4 set = reverseDepNonLocal[drop];
+for (SmallPtrSetInstruction*, 4::iterator I = set.begin(), E = set.end();
+ I != E; ++I)
+ for (DenseMapBasicBlock*, Value*::iterator DI =
+ depGraphNonLocal[*I].begin(), DE = depGraphNonLocal[*I].end();
+ DI != DE; ++DI)
+if (DI-second == drop)
+ DI-second = Dirty;
+ }
+
+ reverseDepNonLocal.erase(drop);
+ nonLocalDepMapType::iterator I = depGraphNonLocal.find(drop);
+ if (I != depGraphNonLocal.end())
+depGraphNonLocal.erase(I);
+}
+
/// removeInstruction - Remove an instruction from the dependence analysis,
/// updating the dependence of instructions that previously depended on it.
/// This method attempts to keep the cache coherent using the reverse map.
@@ -473,7 +513,7 @@
depMapType::iterator depGraphEntry = depGraphLocal.find(rem);
if (depGraphEntry != depGraphLocal.end()) {
-reverseDep[depGraphLocal[rem].first].erase(rem);
+reverseDep[depGraphEntry-second.first].erase(rem);
if (depGraphEntry-second.first != NonLocal
depGraphEntry-second.first != None
Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=47026r1=47025r2=47026view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Tue Feb 12 15:15:18 2008
@@ -19,6 +19,7 @@
#include llvm/Constants.h
#include llvm/DerivedTypes.h
#include llvm/Function.h
+#include llvm/IntrinsicInst.h
#include llvm/Instructions.h
#include llvm/Value.h
#include llvm/ADT/BitVector.h
@@ -736,6 +737,7 @@
SmallVectorInstruction*, 4 toErase);
bool processNonLocalLoad(LoadInst* L,
SmallVectorInstruction*, 4 toErase);
+bool
[llvm-commits] [llvm] r47006 - /llvm/trunk/lib/Transforms/Scalar/GVN.cpp
Author: efriedma
Date: Tue Feb 12 06:08:14 2008
New Revision: 47006
URL: http://llvm.org/viewvc/llvm-project?rev=47006view=rev
Log:
Fix for bug 1996: optimize out loads of undef. This code basically just
checks for a malloc/alloca immediately followed by a load.
Modified:
llvm/trunk/lib/Transforms/Scalar/GVN.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=47006r1=47005r2=47006view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Tue Feb 12 06:08:14 2008
@@ -1010,7 +1010,34 @@
dep = MD.getDependency(L, dep);
}
}
-
+
+ if (dep != MemoryDependenceAnalysis::None
+ dep != MemoryDependenceAnalysis::NonLocal
+ isaAllocationInst(dep)) {
+// Check that this load is actually from the
+// allocation we found
+Value* v = L-getOperand(0);
+while (true) {
+ if (BitCastInst *BC = dyn_castBitCastInst(v))
+v = BC-getOperand(0);
+ else if (GetElementPtrInst *GEP = dyn_castGetElementPtrInst(v))
+v = GEP-getOperand(0);
+ else
+break;
+}
+if (v == dep) {
+ // If this load depends directly on an allocation, there isn't
+ // anything stored there; therefore, we can optimize this load
+ // to undef.
+ MD.removeInstruction(L);
+
+ L-replaceAllUsesWith(UndefValue::get(L-getType()));
+ toErase.push_back(L);
+ deletedLoad = true;
+ NumGVNLoad++;
+}
+ }
+
if (!deletedLoad)
last = L;
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r47007 - in /llvm/trunk: lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/2008-02-12-SMAXTripCount.ll
On Feb 12, 2008, at 7:09 AM, Wojciech Matyjewicz wrote: Author: wmat Date: Tue Feb 12 09:09:36 2008 New Revision: 47007 URL: http://llvm.org/viewvc/llvm-project?rev=47007view=rev Log: Fix PR2002. Suppose n is the initial value for the induction variable (with step 1) and m is its final value. Then, the correct trip count is SMAX(m,n)-n. Previously, we used SMAX(0,m-n), but m-n may overflow and can't in general be interpreted as signed. Very nice, please add a comment above the code explaining what is going on though :) -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm-gcc-4.2] r46966 - in /llvm-gcc-4.2/trunk/gcc: config/i386/i386.h config/rs6000/rs6000.h llvm-abi.h
On Feb 12, 2008, at 5:17 AM, Duncan Sands wrote:
Hi Dale,
Treat struct { long long: 29; }; as int sized and
aligned, rather than long long. ABI issue.
if you look at the DECL_SIZE of the bitfield, rather than
the type size, I think it gives you 29. If so, DECL_SIZE
should simplify things for you. In fact as far as I can
see you should never use the type size for a record field.
For example the struct conversion stuff uses DECL_SIZE everywhere
(except at one point in the field indexing - I have a patch to fix
that which I'll apply at some point). Not using the type size
makes all these it's a big type shoved in a small place problems
magically go away.
I'm not sure what your suggestion is exactly; the issue isn't the
size, it is
that the code in HandleArgument for general RECORD_TYPEs is looking
at getDeclaredType, not the type in the field. (So what this patch
does is
use the INTEGER_REGS case instead.) The wide use of getDeclaredType
and the comments describing it make me think it would be unsafe in
general
to change that. It would certainly be more elegant if it works,
though.
I guess I'm confused, but in the example are you saying that you want
to pass this in registers as a long long? Or the opposite: you want
to pass it as an i32 because it fits in 32 bits? Or something else?
The latter. Before this patch the parameter passing code was
producing i64 for it, which is wrong.
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47048 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Author: sampo
Date: Wed Feb 13 00:43:04 2008
New Revision: 47048
URL: http://llvm.org/viewvc/llvm-project?rev=47048view=rev
Log:
Support legalizing insert_vector_elt on targets where the element
type is not legal.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=47048r1=47047r2=47048view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Feb 13 00:43:04 2008
@@ -1263,8 +1263,16 @@
break;
case ISD::INSERT_VECTOR_ELT:
Tmp1 = LegalizeOp(Node-getOperand(0)); // InVec
-Tmp2 = LegalizeOp(Node-getOperand(1)); // InVal
Tmp3 = LegalizeOp(Node-getOperand(2)); // InEltNo
+
+// The type of the value to insert may not be legal, even though the vector
+// type is legal. Legalize/Promote accordingly. We do not handle Expand
+// here.
+switch (getTypeAction(Node-getOperand(1).getValueType())) {
+default: assert(0 Cannot expand insert element operand);
+case Legal: Tmp2 = LegalizeOp(Node-getOperand(1)); break;
+case Promote: Tmp2 = PromoteOp(Node-getOperand(1)); break;
+}
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
@@ -1283,30 +1291,35 @@
// If the insert index is a constant, codegen this as a scalar_to_vector,
// then a shuffle that inserts it into the right position in the vector.
if (ConstantSDNode *InsertPos = dyn_castConstantSDNode(Tmp3)) {
-SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
- Tmp1.getValueType(), Tmp2);
-
-unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
-MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
-MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
-
-// We generate a shuffle of InVec and ScVec, so the shuffle mask should
-// be 0,1,2,3,4,5... with the appropriate element replaced with elt 0
of
-// the RHS.
-SmallVectorSDOperand, 8 ShufOps;
-for (unsigned i = 0; i != NumElts; ++i) {
- if (i != InsertPos-getValue())
-ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
- else
-ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
+// SCALAR_TO_VECTOR requires that the type of the value being inserted
+// match the element type of the vector being created.
+if (Tmp2.getValueType() ==
+MVT::getVectorElementType(Op.getValueType())) {
+ SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
+Tmp1.getValueType(), Tmp2);
+
+ unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
+ MVT::ValueType ShufMaskVT =
MVT::getIntVectorWithNumElements(NumElts);
+ MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
+
+ // We generate a shuffle of InVec and ScVec, so the shuffle mask
+ // should be 0,1,2,3,4,5... with the appropriate element replaced
with
+ // elt 0 of the RHS.
+ SmallVectorSDOperand, 8 ShufOps;
+ for (unsigned i = 0; i != NumElts; ++i) {
+if (i != InsertPos-getValue())
+ ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
+else
+ ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
+ }
+ SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
+ ShufOps[0], ShufOps.size());
+
+ Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
+ Tmp1, ScVec, ShufMask);
+ Result = LegalizeOp(Result);
+ break;
}
-SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
- ShufOps[0], ShufOps.size());
-
-Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
- Tmp1, ScVec, ShufMask);
-Result = LegalizeOp(Result);
-break;
}
// If the target doesn't support this, we have to spill the input vector
@@ -1316,7 +1329,7 @@
// permute it into place, if the idx is a constant and if the idx is
// supported by the target.
MVT::ValueType VT= Tmp1.getValueType();
- MVT::ValueType EltVT = Tmp2.getValueType();
+ MVT::ValueType EltVT = MVT::getVectorElementType(VT);
MVT::ValueType IdxVT = Tmp3.getValueType();
MVT::ValueType PtrVT = TLI.getPointerTy();
SDOperand StackPtr =
[llvm-commits] [llvm] r47049 - /llvm/trunk/test/CodeGen/PowerPC/vec_insert.ll
Author: sampo
Date: Wed Feb 13 00:48:40 2008
New Revision: 47049
URL: http://llvm.org/viewvc/llvm-project?rev=47049view=rev
Log:
Add testcase for recent legalizer change
Added:
llvm/trunk/test/CodeGen/PowerPC/vec_insert.ll
Added: llvm/trunk/test/CodeGen/PowerPC/vec_insert.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_insert.ll?rev=47049view=auto
==
--- llvm/trunk/test/CodeGen/PowerPC/vec_insert.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_insert.ll Wed Feb 13 00:48:40 2008
@@ -0,0 +1,8 @@
+; RUN: llvm-as %s | llc -march=ppc32 -mcpu=g5 | grep sth
+
+define 8 x i16 @insert(8 x i16 %foo, i16 %a) nounwind {
+entry:
+ %vecext = insertelement 8 x i16 %foo, i16 %a, i32 7 ; i8
[#uses=1]
+ ret 8 x i16 %vecext
+}
+
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47009 - in /llvm/trunk/test/Analysis/ScalarEvolution: 2007-07-15-NegativeStride.ll 2007-08-06-Unsigned.ll 2007-09-27-LargeStepping.ll 2007-11-18-OrInstruction.ll SolveQuadraticE
Author: wmat
Date: Tue Feb 12 09:12:40 2008
New Revision: 47009
URL: http://llvm.org/viewvc/llvm-project?rev=47009view=rev
Log:
Now that ScalarEvolution::print writes to the correct stream, there is
no need to redirect stderr into stdout.
Modified:
llvm/trunk/test/Analysis/ScalarEvolution/2007-07-15-NegativeStride.ll
llvm/trunk/test/Analysis/ScalarEvolution/2007-08-06-Unsigned.ll
llvm/trunk/test/Analysis/ScalarEvolution/2007-09-27-LargeStepping.ll
llvm/trunk/test/Analysis/ScalarEvolution/2007-11-18-OrInstruction.ll
llvm/trunk/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll
llvm/trunk/test/Analysis/ScalarEvolution/trip-count.ll
llvm/trunk/test/Analysis/ScalarEvolution/trip-count2.ll
Modified: llvm/trunk/test/Analysis/ScalarEvolution/2007-07-15-NegativeStride.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/2007-07-15-NegativeStride.ll?rev=47009r1=47008r2=47009view=diff
==
--- llvm/trunk/test/Analysis/ScalarEvolution/2007-07-15-NegativeStride.ll
(original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/2007-07-15-NegativeStride.ll Tue
Feb 12 09:12:40 2008
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s | opt -analyze -scalar-evolution | grep {Loop bb: 100
iterations}
+; RUN: llvm-as %s | opt -analyze -scalar-evolution | grep {Loop bb: 100
iterations}
; PR1533
@array = weak global [101 x i32] zeroinitializer, align 32 ; [100
x i32]* [#uses=1]
Modified: llvm/trunk/test/Analysis/ScalarEvolution/2007-08-06-Unsigned.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/2007-08-06-Unsigned.ll?rev=47009r1=47008r2=47009view=diff
==
--- llvm/trunk/test/Analysis/ScalarEvolution/2007-08-06-Unsigned.ll (original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/2007-08-06-Unsigned.ll Tue Feb 12
09:12:40 2008
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s | opt -scalar-evolution -analyze | grep {Loop bb: ( -1 +
( -1 \\* %x) + %y) iterations!}
+; RUN: llvm-as %s | opt -scalar-evolution -analyze | grep {Loop bb: ( -1 + (
-1 \\* %x) + %y) iterations!}
; PR1597
define i32 @f(i32 %x, i32 %y) {
Modified: llvm/trunk/test/Analysis/ScalarEvolution/2007-09-27-LargeStepping.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/2007-09-27-LargeStepping.ll?rev=47009r1=47008r2=47009view=diff
==
--- llvm/trunk/test/Analysis/ScalarEvolution/2007-09-27-LargeStepping.ll
(original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/2007-09-27-LargeStepping.ll Tue
Feb 12 09:12:40 2008
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s | opt -analyze -scalar-evolution | grep {13 iterations}
+; RUN: llvm-as %s | opt -analyze -scalar-evolution | grep {13 iterations}
; PR1706
define i32 @f() {
Modified: llvm/trunk/test/Analysis/ScalarEvolution/2007-11-18-OrInstruction.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/2007-11-18-OrInstruction.ll?rev=47009r1=47008r2=47009view=diff
==
--- llvm/trunk/test/Analysis/ScalarEvolution/2007-11-18-OrInstruction.ll
(original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/2007-11-18-OrInstruction.ll Tue
Feb 12 09:12:40 2008
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s | opt -analyze -scalar-evolution | grep -e {-- %b}
+; RUN: llvm-as %s | opt -analyze -scalar-evolution | grep -e {-- %b}
; PR1810
define void @fun() {
Modified: llvm/trunk/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll?rev=47009r1=47008r2=47009view=diff
==
--- llvm/trunk/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll
(original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll Tue Feb
12 09:12:40 2008
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s | opt -analyze -scalar-evolution | \
+; RUN: llvm-as %s | opt -analyze -scalar-evolution | \
; RUN: grep {100 iterations}
; PR1101
Modified: llvm/trunk/test/Analysis/ScalarEvolution/trip-count.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/trip-count.ll?rev=47009r1=47008r2=47009view=diff
==
--- llvm/trunk/test/Analysis/ScalarEvolution/trip-count.ll (original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/trip-count.ll Tue Feb 12 09:12:40
2008
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s | opt -analyze -scalar-evolution | \
+; RUN: llvm-as %s | opt -analyze -scalar-evolution | \
; RUN: grep {1 iterations}
; PR1101
Modified: llvm/trunk/test/Analysis/ScalarEvolution/trip-count2.ll
URL:
[llvm-commits] [llvm] r47008 - /llvm/trunk/test/Analysis/ScalarEvolution/2008-02-11-ReversedCondition.ll
Author: wmat
Date: Tue Feb 12 09:10:35 2008
New Revision: 47008
URL: http://llvm.org/viewvc/llvm-project?rev=47008view=rev
Log:
Change negative grep into positive one in my yesterday's testcase.
Modified:
llvm/trunk/test/Analysis/ScalarEvolution/2008-02-11-ReversedCondition.ll
Modified:
llvm/trunk/test/Analysis/ScalarEvolution/2008-02-11-ReversedCondition.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/2008-02-11-ReversedCondition.ll?rev=47008r1=47007r2=47008view=diff
==
--- llvm/trunk/test/Analysis/ScalarEvolution/2008-02-11-ReversedCondition.ll
(original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/2008-02-11-ReversedCondition.ll
Tue Feb 12 09:10:35 2008
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s | opt -scalar-evolution -analyze | not grep Unpredictable
+; RUN: llvm-as %s | opt -scalar-evolution -analyze | grep {Loop header: ( 0
smax %n) iterations!}
define void @foo(i32 %n) {
entry:
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r47039 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Ta
On Feb 12, 2008, at 4:35 PM, Dan Gohman wrote:
Convert SelectionDAG::ComputeMaskedBits to use APInt instead of
uint64_t.
Add an overload that supports the uint64_t interface for use by
clients
that haven't been updated yet.
Great! Thanks for tackling this Dan!
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Feb 12
18:35:47 2008
@@ -556,6 +556,12 @@
/// bitsets. This code only analyzes bits in Mask, in order to
short-circuit
/// processing. Targets can implement the
computeMaskedBitsForTargetNode
/// method in the TargetLowering class to allow target nodes to be
understood.
+ void ComputeMaskedBits(SDOperand Op, APInt Mask, APInt KnownZero,
Please pass Mask by const reference (likewise to the virtual method).
APInts are somewhat cheap to copy in the common case (no malloc) but
they aren't free, and it would be better to make the copies explicit
so they are only done when needed.
case ISD::SRL:
// (ushr X, C1) C2 == 0 iff (-1 C1) C2 == 0
..
+ APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
KnownZero |= HighBits; // High bits known zero.
How about: KnownZero |= APInt::getHighBitsSet(BitWidth, ShAmt);
case ISD::SRA:
if (ConstantSDNode *SA =
dyn_castConstantSDNode(Op.getOperand(1))) {
unsigned ShAmt = SA-getValue();
+ APInt InDemandedMask = (Mask ShAmt);
// If any of the demanded bits are produced by the sign
extension, we also
// demand the input sign bit.
+ APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
+ if (!!(HighBits Mask))
+InDemandedMask |= APInt::getSignBit(BitWidth);
Heh, this is clever, but non-obvious. How about:
if ((HighBits Mask) != 0)
or:
if ((HighBits Mask).getBoolValue())
which is less tricky but more obvious. There are a couple instances
of similar !! things.
In fact, this occurs often enough that it might be worthwhile to avoid
the construction of the temporary APInt. How about defining a new
method:
X.intersect(Y)
to be true if any bits in X are also set in Y? Aka (XY)!=0
ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero,
KnownOne,
Depth+1);
assert((KnownZero KnownOne) == 0 Bits known to be one
AND zero?);
+ KnownZero = KnownZero.lshr(ShAmt);
+ KnownOne = KnownOne.lshr(ShAmt);
// Handle the sign bits.
+ APInt SignBit = APInt::getSignBit(BitWidth);
+ SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now
in the mask.
It would be better to make an APInt with the bit in the right place
instead of starting with a sign bit and shifting it.
@@ -1283,14 +1274,18 @@
// Sign extension. Compute the demanded bits in the result that
are not
// present in the input.
-uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) Mask;
+APInt NewBits = ~APInt::getLowBitsSet(BitWidth,
+ MVT::getSizeInBits(EVT))
Mask;
instead of using ~lowbits, how about using getHighBitsSet?
// If the sign extended bits are demanded, we know that the sign
// bit is demanded.
+InSignBit.zext(BitWidth);
This is another create sign and extend. It would be better to just
make the apint with the bit set in the right place.
case ISD::LOAD: {
if (ISD::isZEXTLoad(Op.Val)) {
LoadSDNode *LD = castLoadSDNode(Op);
MVT::ValueType VT = LD-getMemoryVT();
- KnownZero |= ~MVT::getIntVTBitMask(VT) Mask;
+ KnownZero |= ~APInt::getLowBitsSet(BitWidth,
MVT::getSizeInBits(VT)) Mask;
Instead of ~lowbits, how about using highbits? likewise in a couple
other places.
case ISD::SIGN_EXTEND: {
MVT::ValueType InVT = Op.getOperand(0).getValueType();
+unsigned InBits = MVT::getSizeInBits(InVT);
+APInt InMask= APInt::getLowBitsSet(BitWidth, InBits);
+APInt InSignBit = APInt::getSignBit(InBits);
+APInt NewBits = (~InMask) Mask;
// If any of the sign extended bits are demanded, we know that
the sign
// bit is demanded.
+InSignBit.zext(BitWidth);
+if (!!(NewBits Mask))
+ Mask |= InSignBit;
I think this is a bug: NewBits is defined to be ... Mask. This is
either a bug or this can be replaced with NewBits != 0 which doesn't
seem right.
@@ -1402,11 +1415,11 @@
// Output known-0 bits are known if clear or set in both the low
clear bits
// common to both LHS RHS. For example, 8+(X3) is known to
have the
// low 3 bits clear.
-uint64_t KnownZeroOut =
std::min(CountTrailingZeros_64(~KnownZero),
-
CountTrailingZeros_64(~KnownZero2));
+unsigned KnownZeroOut =
std::min((~KnownZero).countTrailingZeros(),
+
(~KnownZero2).countTrailingZeros());
Huh, apint has a countLeadingOnes() but no countTrailingOnes(). If it
did, you could use it instead of ~'ing
[llvm-commits] [llvm] r47050 - /llvm/trunk/test/Transforms/GVN/2008-02-12UndefLoad.ll
Author: efriedma
Date: Wed Feb 13 00:55:57 2008
New Revision: 47050
URL: http://llvm.org/viewvc/llvm-project?rev=47050view=rev
Log:
Add test for PR1996. (This is my first time adding a test for a
transform, so please review.)
Added:
llvm/trunk/test/Transforms/GVN/2008-02-12UndefLoad.ll
Added: llvm/trunk/test/Transforms/GVN/2008-02-12UndefLoad.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/2008-02-12UndefLoad.ll?rev=47050view=auto
==
--- llvm/trunk/test/Transforms/GVN/2008-02-12UndefLoad.ll (added)
+++ llvm/trunk/test/Transforms/GVN/2008-02-12UndefLoad.ll Wed Feb 13 00:55:57
2008
@@ -0,0 +1,19 @@
+; RUN: llvm-as %s | opt -gvn | llvm-dis | not grep load
+
+%struct.anon = type { i32, i8, i8, i8, i8 }
+
+define i32 @a() {
+entry:
+%c = alloca %struct.anon; %struct.anon* [#uses=2]
+%tmp = getelementptr %struct.anon* %c, i32 0, i32 0 ;
i32* [#uses=1]
+%tmp1 = getelementptr i32* %tmp, i32 1 ; i32* [#uses=2]
+%tmp2 = load i32* %tmp1, align 4; i32 [#uses=1]
+%tmp3 = or i32 %tmp2, 11; i32 [#uses=1]
+%tmp4 = and i32 %tmp3, -21 ; i32 [#uses=1]
+store i32 %tmp4, i32* %tmp1, align 4
+%call = call i32 (...)* @x( %struct.anon* %c ) ; i32
[#uses=0]
+ret i32 undef
+}
+
+
+declare i32 @x(...)
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r47050 - /llvm/trunk/test/Transforms/GVN/2008-02-12UndefLoad.ll
Eli Friedman wrote:
Author: efriedma
Date: Wed Feb 13 00:55:57 2008
New Revision: 47050
URL: http://llvm.org/viewvc/llvm-project?rev=47050view=rev
Log:
Add test for PR1996. (This is my first time adding a test for a
transform, so please review.)
Added:
llvm/trunk/test/Transforms/GVN/2008-02-12UndefLoad.ll
Added: llvm/trunk/test/Transforms/GVN/2008-02-12UndefLoad.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/2008-02-12UndefLoad.ll?rev=47050view=auto
==
--- llvm/trunk/test/Transforms/GVN/2008-02-12UndefLoad.ll (added)
+++ llvm/trunk/test/Transforms/GVN/2008-02-12UndefLoad.ll Wed Feb 13 00:55:57
2008
@@ -0,0 +1,19 @@
+; RUN: llvm-as %s | opt -gvn | llvm-dis | not grep load
You should add:
; PR1996
here to provide a reference next time it fails.
Nick
+
+%struct.anon = type { i32, i8, i8, i8, i8 }
+
+define i32 @a() {
+entry:
+%c = alloca %struct.anon; %struct.anon* [#uses=2]
+%tmp = getelementptr %struct.anon* %c, i32 0, i32 0 ;
i32* [#uses=1]
+%tmp1 = getelementptr i32* %tmp, i32 1 ; i32* [#uses=2]
+%tmp2 = load i32* %tmp1, align 4; i32 [#uses=1]
+%tmp3 = or i32 %tmp2, 11; i32 [#uses=1]
+%tmp4 = and i32 %tmp3, -21 ; i32 [#uses=1]
+store i32 %tmp4, i32* %tmp1, align 4
+%call = call i32 (...)* @x( %struct.anon* %c ) ; i32
[#uses=0]
+ret i32 undef
+}
+
+
+declare i32 @x(...)
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47007 - in /llvm/trunk: lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/2008-02-12-SMAXTripCount.ll
Author: wmat
Date: Tue Feb 12 09:09:36 2008
New Revision: 47007
URL: http://llvm.org/viewvc/llvm-project?rev=47007view=rev
Log:
Fix PR2002. Suppose n is the initial value for the induction
variable (with step 1) and m is its final value. Then, the correct trip
count is SMAX(m,n)-n. Previously, we used SMAX(0,m-n), but m-n may
overflow and can't in general be interpreted as signed.
Patch by Nick Lewycky.
Added:
llvm/trunk/test/Analysis/ScalarEvolution/2008-02-12-SMAXTripCount.ll
Modified:
llvm/trunk/lib/Analysis/ScalarEvolution.cpp
Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=47007r1=47006r2=47007view=diff
==
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Feb 12 09:09:36 2008
@@ -2527,19 +2527,17 @@
if (AddRec-isAffine()) {
// The number of iterations for {n,+,1} m, is m-n. However, we don't
// know that m is = n on input to the loop. If it is, the condition
-// returns true zero times. To handle both cases, we return SMAX(0, m-n).
+// returns true zero times. To handle both cases, we return SMAX(m, n)-n.
// FORNOW: We only support unit strides.
SCEVHandle One = SE.getIntegerSCEV(1, RHS-getType());
if (AddRec-getOperand(1) != One)
return UnknownValue;
-SCEVHandle Iters = SE.getMinusSCEV(RHS, AddRec-getOperand(0));
+SCEVHandle Start = AddRec-getOperand(0);
+SCEVHandle End = isSigned ? SE.getSMaxExpr(RHS, Start) : (SCEVHandle)RHS;
-if (isSigned)
- return SE.getSMaxExpr(SE.getIntegerSCEV(0, RHS-getType()), Iters);
-else
- return Iters;
+return SE.getMinusSCEV(End, Start);
}
return UnknownValue;
Added: llvm/trunk/test/Analysis/ScalarEvolution/2008-02-12-SMAXTripCount.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/2008-02-12-SMAXTripCount.ll?rev=47007view=auto
==
--- llvm/trunk/test/Analysis/ScalarEvolution/2008-02-12-SMAXTripCount.ll (added)
+++ llvm/trunk/test/Analysis/ScalarEvolution/2008-02-12-SMAXTripCount.ll Tue
Feb 12 09:09:36 2008
@@ -0,0 +1,16 @@
+; RUN: llvm-as %s | opt -scalar-evolution -analyze | grep {Loop loop: ( 100
+ ( -100 smax %n)) iterations!}
+; PR2002
+
+define void @foo(i8 %n) {
+entry:
+ br label %loop
+loop:
+ %i = phi i8 [ -100, %entry ], [ %i.inc, %next ]
+ %cond = icmp slt i8 %i, %n
+ br i1 %cond, label %next, label %return
+next:
+%i.inc = add i8 %i, 1
+ br label %loop
+return:
+ ret void
+}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47051 - in /llvm/trunk/lib/Target: PowerPC/README_ALTIVEC.txt X86/README-SSE.txt
Author: sampo Date: Wed Feb 13 01:06:12 2008 New Revision: 47051 URL: http://llvm.org/viewvc/llvm-project?rev=47051view=rev Log: readme updates Modified: llvm/trunk/lib/Target/PowerPC/README_ALTIVEC.txt llvm/trunk/lib/Target/X86/README-SSE.txt Modified: llvm/trunk/lib/Target/PowerPC/README_ALTIVEC.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/README_ALTIVEC.txt?rev=47051r1=47050r2=47051view=diff == --- llvm/trunk/lib/Target/PowerPC/README_ALTIVEC.txt (original) +++ llvm/trunk/lib/Target/PowerPC/README_ALTIVEC.txt Wed Feb 13 01:06:12 2008 @@ -177,3 +177,12 @@ //===--===// + +An alternative to the store/store/load approach for illegal insert element +lowering would be: + +1. store element to any ol' slot +2. lvx the slot +3. lvsl 0; splat index; vcmpeq to generate a select mask +4. lvsl slot + x; vperm to rotate result into correct slot +5. vsel result together. Modified: llvm/trunk/lib/Target/X86/README-SSE.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README-SSE.txt?rev=47051r1=47050r2=47051view=diff == --- llvm/trunk/lib/Target/X86/README-SSE.txt (original) +++ llvm/trunk/lib/Target/X86/README-SSE.txt Wed Feb 13 01:06:12 2008 @@ -781,3 +781,14 @@ insertions. See comments in LowerINSERT_VECTOR_ELT_SSE4. + +//===-===// + +On a random note, SSE2 should declare insert/extract of 2 x f64 as legal, not +Custom. All combinations of insert/extract reg-reg, reg-mem, and mem-reg are +legal, it'll just take a few extra patterns written in the .td file. + +Note: this is not a code quality issue; the custom lowered code happens to be +right, but we shouldn't have to custom lower anything. This is probably related +to 2 x i64 ops being so bad. + ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm-gcc-4.2] r46966 - in /llvm-gcc-4.2/trunk/gcc: config/i386/i386.h config/rs6000/rs6000.h llvm-abi.h
Hi Dale,
Treat struct { long long: 29; }; as int sized and
aligned, rather than long long. ABI issue.
if you look at the DECL_SIZE of the bitfield, rather than
the type size, I think it gives you 29. If so, DECL_SIZE
should simplify things for you. In fact as far as I can
see you should never use the type size for a record field.
For example the struct conversion stuff uses DECL_SIZE everywhere
(except at one point in the field indexing - I have a patch to fix
that which I'll apply at some point). Not using the type size
makes all these it's a big type shoved in a small place problems
magically go away.
I'm not sure what your suggestion is exactly; the issue isn't the
size, it is
that the code in HandleArgument for general RECORD_TYPEs is looking
at getDeclaredType, not the type in the field. (So what this patch
does is
use the INTEGER_REGS case instead.) The wide use of getDeclaredType
and the comments describing it make me think it would be unsafe in
general
to change that. It would certainly be more elegant if it works, though.
I guess I'm confused, but in the example are you saying that you want
to pass this in registers as a long long? Or the opposite: you want
to pass it as an i32 because it fits in 32 bits? Or something else?
Thanks,
D.
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47052 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Author: lattner
Date: Wed Feb 13 01:25:05 2008
New Revision: 47052
URL: http://llvm.org/viewvc/llvm-project?rev=47052view=rev
Log:
teach dag combiner how to eliminate MERGE_VALUES nodes.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=47052r1=47051r2=47052view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Feb 13 01:25:05 2008
@@ -137,6 +137,7 @@
// otherwise- N should be replaced by the returned Operand.
//
SDOperand visitTokenFactor(SDNode *N);
+SDOperand visitMERGE_VALUES(SDNode *N);
SDOperand visitADD(SDNode *N);
SDOperand visitSUB(SDNode *N);
SDOperand visitADDC(SDNode *N);
@@ -662,6 +663,7 @@
switch(N-getOpcode()) {
default: break;
case ISD::TokenFactor:return visitTokenFactor(N);
+ case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
case ISD::ADD:return visitADD(N);
case ISD::SUB:return visitSUB(N);
case ISD::ADDC: return visitADDC(N);
@@ -837,6 +839,18 @@
return Result;
}
+/// MERGE_VALUES can always be eliminated.
+SDOperand DAGCombiner::visitMERGE_VALUES(SDNode *N) {
+ WorkListRemover DeadNodes(*this);
+ for (unsigned i = 0, e = N-getNumOperands(); i != e; ++i)
+DAG.ReplaceAllUsesOfValueWith(SDOperand(N, i), N-getOperand(i),
+ DeadNodes);
+ removeFromWorkList(N);
+ DAG.DeleteNode(N);
+ return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+}
+
+
static
SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG DAG)
{
MVT::ValueType VT = N0.getValueType();
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47053 - in /llvm/trunk/lib/Target: ARM/ARMISelLowering.cpp CellSPU/SPUISelLowering.cpp PowerPC/PPCISelLowering.cpp
Author: lattner
Date: Wed Feb 13 01:35:30 2008
New Revision: 47053
URL: http://llvm.org/viewvc/llvm-project?rev=47053view=rev
Log:
don't try to avoid inserting loads when lowering FORMAL_ARGUMENTS.
DAGCombine is now quite good at zapifying them.
Modified:
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=47053r1=47052r2=47053view=diff
==
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Feb 13 01:35:30 2008
@@ -954,22 +954,15 @@
NumGPRs += ObjGPRs;
if (ObjSize) {
-// If the argument is actually used, emit a load from the right stack
-// slot.
-if (!Op.Val-hasNUsesOfValue(0, ArgNo)) {
- MachineFrameInfo *MFI = MF.getFrameInfo();
- int FI = MFI-CreateFixedObject(ObjSize, ArgOffset);
- SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
- if (ObjGPRs == 0)
-ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
- else {
-SDOperand ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0);
-assert(ObjectVT != MVT::i64 i64 should already be lowered);
-ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
- }
-} else {
- // Don't emit a dead load.
- ArgValue = DAG.getNode(ISD::UNDEF, ObjectVT);
+MachineFrameInfo *MFI = MF.getFrameInfo();
+int FI = MFI-CreateFixedObject(ObjSize, ArgOffset);
+SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
+if (ObjGPRs == 0)
+ ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
+else {
+ SDOperand ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0);
+ assert(ObjectVT != MVT::i64 i64 should already be lowered);
+ ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
}
ArgOffset += ObjSize; // Move on to the next argument.
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=47053r1=47052r2=47053view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Wed Feb 13 01:35:30 2008
@@ -1008,17 +1008,9 @@
// We need to load the argument to a virtual register if we determined
above
// that we ran out of physical registers of the appropriate type
if (needsLoad) {
- // If the argument is actually used, emit a load from the right stack
- // slot.
- if (!Op.Val-hasNUsesOfValue(0, ArgNo)) {
-int FI = MFI-CreateFixedObject(ObjSize, ArgOffset);
-SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
-ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
- } else {
-// Don't emit a dead load.
-ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
- }
-
+ int FI = MFI-CreateFixedObject(ObjSize, ArgOffset);
+ SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
+ ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
ArgOffset += StackSlotSize;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=47053r1=47052r2=47053view=diff
==
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Feb 13 01:35:30 2008
@@ -1420,19 +1420,12 @@
}
// We need to load the argument to a virtual register if we determined
above
-// that we ran out of physical registers of the appropriate type
+// that we ran out of physical registers of the appropriate type.
if (needsLoad) {
- // If the argument is actually used, emit a load from the right stack
- // slot.
- if (!Op.Val-hasNUsesOfValue(0, ArgNo)) {
-int FI = MFI-CreateFixedObject(ObjSize,
-CurArgOffset + (ArgSize - ObjSize));
-SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
-ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
- } else {
-// Don't emit a dead load.
-ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
- }
+ int FI = MFI-CreateFixedObject(ObjSize,
+ CurArgOffset + (ArgSize - ObjSize));
+ SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
+ ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
}
ArgValues.push_back(ArgVal);
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
[llvm-commits] [llvm] r47054 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp test/CodeGen/X86/arg-cast.ll
Author: lattner
Date: Wed Feb 13 01:39:09 2008
New Revision: 47054
URL: http://llvm.org/viewvc/llvm-project?rev=47054view=rev
Log:
In SDISel, for targets that support FORMAL_ARGUMENTS nodes, lower this
node as soon as we create it in SDISel. Previously we would lower it in
legalize. The problem with this is that it only exposes the argument
loads implied by FORMAL_ARGUMENTs after legalize, so that only dag combine 2
can hack on them. This causes us to miss some optimizations because
datatype expansion also happens here.
Exposing the loads early allows us to do optimizations on them. For example
we now compile arg-cast.ll to:
_foo:
movl$2147483647, %eax
andl8(%esp), %eax
ret
where we previously produced:
_foo:
subl$12, %esp
movsd 16(%esp), %xmm0
movsd %xmm0, (%esp)
movl$2147483647, %eax
andl4(%esp), %eax
addl$12, %esp
ret
It might also make sense to do this for ISD::CALL nodes, which have implicit
stores on many targets.
Added:
llvm/trunk/test/CodeGen/X86/arg-cast.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=47054r1=47053r2=47054view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Feb 13
01:39:09 2008
@@ -4074,8 +4074,22 @@
// Create the node.
SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
- DAG.getNodeValueTypes(RetVals), RetVals.size(),
+ DAG.getVTList(RetVals[0], RetVals.size()),
Ops[0], Ops.size()).Val;
+
+ // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
+ // allows exposing the loads that may be part of the argument access to the
+ // first DAGCombiner pass.
+ SDOperand TmpRes = LowerOperation(SDOperand(Result, 0), DAG);
+
+ // The number of results should match up, except that the lowered one may
have
+ // an extra flag result.
+ assert((Result-getNumValues() == TmpRes.Val-getNumValues() ||
+ (Result-getNumValues()+1 == TmpRes.Val-getNumValues()
+ TmpRes.getValue(Result-getNumValues()).getValueType() ==
MVT::Flag))
+ Lowering produced unexpected number of results!);
+ Result = TmpRes.Val;
+
unsigned NumArgRegs = Result-getNumValues() - 1;
DAG.setRoot(SDOperand(Result, NumArgRegs));
Added: llvm/trunk/test/CodeGen/X86/arg-cast.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/arg-cast.ll?rev=47054view=auto
==
--- llvm/trunk/test/CodeGen/X86/arg-cast.ll (added)
+++ llvm/trunk/test/CodeGen/X86/arg-cast.ll Wed Feb 13 01:39:09 2008
@@ -0,0 +1,18 @@
+; This should compile to movl $2147483647, %eax + andl only.
+; RUN: llvm-as %s | llc | grep andl
+; RUN: llvm-as %s | llc | not grep movsd
+; RUN: llvm-as %s | llc | not grep esp
+; rdar://5736574
+
+target datalayout =
e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128
+target triple = i686-apple-darwin8
+
+define i32 @foo(double %x) nounwind {
+entry:
+ %x15 = bitcast double %x to i64 ; i64 [#uses=1]
+ %tmp713 = lshr i64 %x15, 32 ; i64 [#uses=1]
+ %tmp714 = trunc i64 %tmp713 to i32 ; i32 [#uses=1]
+ %tmp8 = and i32 %tmp714, 2147483647 ; i32 [#uses=1]
+ ret i32 %tmp8
+}
+
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r47055 - /llvm/trunk/test/Transforms/GVN/2008-02-12UndefLoad.ll
Author: efriedma
Date: Wed Feb 13 01:56:04 2008
New Revision: 47055
URL: http://llvm.org/viewvc/llvm-project?rev=47055view=rev
Log:
Add a note pointing to PR1996.
Modified:
llvm/trunk/test/Transforms/GVN/2008-02-12UndefLoad.ll
Modified: llvm/trunk/test/Transforms/GVN/2008-02-12UndefLoad.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/2008-02-12UndefLoad.ll?rev=47055r1=47054r2=47055view=diff
==
--- llvm/trunk/test/Transforms/GVN/2008-02-12UndefLoad.ll (original)
+++ llvm/trunk/test/Transforms/GVN/2008-02-12UndefLoad.ll Wed Feb 13 01:56:04
2008
@@ -1,4 +1,5 @@
; RUN: llvm-as %s | opt -gvn | llvm-dis | not grep load
+; PR1996
%struct.anon = type { i32, i8, i8, i8, i8 }
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
