Mesa (vulkan): spirv/alu: Add support for the NoContraction decoration

[Jason Ekstrand]

Module: Mesa
Branch: vulkan
Commit: fbb9e1f008f8059c373ae9f130be139e0d4e1ae9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fbb9e1f008f8059c373ae9f130be139e0d4e1ae9

Author: Jason Ekstrand 
Date:   Fri Mar 25 15:30:46 2016 -0700

spirv/alu: Add support for the NoContraction decoration

---

 src/compiler/nir/spirv/vtn_alu.c | 69 ++--
 1 file changed, 53 insertions(+), 16 deletions(-)

diff --git a/src/compiler/nir/spirv/vtn_alu.c b/src/compiler/nir/spirv/vtn_alu.c
index 450bc15..c9526f1 100644
--- a/src/compiler/nir/spirv/vtn_alu.c
+++ b/src/compiler/nir/spirv/vtn_alu.c
@@ -305,6 +305,17 @@ vtn_nir_alu_op_for_spirv_opcode(SpvOp opcode, bool *swap)
}
 }
 
+static void
+handle_no_contraction(struct vtn_builder *b, struct vtn_value *val, int member,
+  const struct vtn_decoration *dec, void *_void)
+{
+   assert(dec->scope == VTN_DEC_DECORATION);
+   if (dec->decoration != SpvDecorationNoContraction)
+  return;
+
+   b->nb.exact = true;
+}
+
 void
 vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
const uint32_t *w, unsigned count)
@@ -313,15 +324,39 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
const struct glsl_type *type =
   vtn_value(b, w[1], vtn_value_type_type)->type->type;
 
+   vtn_foreach_decoration(b, val, handle_no_contraction, NULL);
+
/* Collect the various SSA sources */
const unsigned num_inputs = count - 3;
struct vtn_ssa_value *vtn_src[4] = { NULL, };
-   for (unsigned i = 0; i < num_inputs; i++)
+   for (unsigned i = 0; i < num_inputs; i++) {
   vtn_src[i] = vtn_ssa_value(b, w[i + 3]);
 
+  /* The way SPIR-V defines the NoContraction decoration is rediculous.
+   * It expressly says in the SPIR-V spec:
+   *
+   *"For example, if applied to an OpFMul, that multiply can’t be
+   *combined with an addition to yield a fused multiply-add
+   *operation."
+   *
+   * Technically, this means we would have to either rewrite NIR with
+   * another silly "don't fuse me" flag or we would have to propagate
+   * the NoContraction decoration to all consumers of a value which
+   * would make it far more infectious than anyone intended.
+   *
+   * Instead, we take a short-cut by simply looking at the sources and
+   * see if any of them have it.  That should be good enough.
+   *
+   * See also issue #17 on the SPIR-V gitlab
+   */
+  vtn_foreach_decoration(b, vtn_untyped_value(b, w[i + 3]),
+ handle_no_contraction, NULL);
+   }
+
if (glsl_type_is_matrix(vtn_src[0]->type) ||
(num_inputs >= 2 && glsl_type_is_matrix(vtn_src[1]->type))) {
   vtn_handle_matrix_alu(b, opcode, val, vtn_src[0], vtn_src[1]);
+  b->nb.exact = false;
   return;
}
 
@@ -347,7 +382,7 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
nir_imm_int(>nb, NIR_FALSE),
NULL, NULL);
   }
-  return;
+  break;
 
case SpvOpAll:
   if (src[0]->num_components == 1) {
@@ -363,73 +398,73 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
nir_imm_int(>nb, NIR_TRUE),
NULL, NULL);
   }
-  return;
+  break;
 
case SpvOpOuterProduct: {
   for (unsigned i = 0; i < src[1]->num_components; i++) {
  val->ssa->elems[i]->def =
 nir_fmul(>nb, src[0], nir_channel(>nb, src[1], i));
   }
-  return;
+  break;
}
 
case SpvOpDot:
   val->ssa->def = nir_fdot(>nb, src[0], src[1]);
-  return;
+  break;
 
case SpvOpIAddCarry:
   assert(glsl_type_is_struct(val->ssa->type));
   val->ssa->elems[0]->def = nir_iadd(>nb, src[0], src[1]);
   val->ssa->elems[1]->def = nir_uadd_carry(>nb, src[0], src[1]);
-  return;
+  break;
 
case SpvOpISubBorrow:
   assert(glsl_type_is_struct(val->ssa->type));
   val->ssa->elems[0]->def = nir_isub(>nb, src[0], src[1]);
   val->ssa->elems[1]->def = nir_usub_borrow(>nb, src[0], src[1]);
-  return;
+  break;
 
case SpvOpUMulExtended:
   assert(glsl_type_is_struct(val->ssa->type));
   val->ssa->elems[0]->def = nir_imul(>nb, src[0], src[1]);
   val->ssa->elems[1]->def = nir_umul_high(>nb, src[0], src[1]);
-  return;
+  break;
 
case SpvOpSMulExtended:
   assert(glsl_type_is_struct(val->ssa->type));
   val->ssa->elems[0]->def = nir_imul(>nb, src[0], src[1]);
   val->ssa->elems[1]->def = nir_imul_high(>nb, src[0], src[1]);
-  return;
+  break;
 
case SpvOpFwidth:
   val->ssa->def = nir_fadd(>nb,
nir_fabs(>nb, nir_fddx(>nb, src[0])),
nir_fabs(>nb, nir_fddy(>nb, src[0])));
-  return;
+  break;
case SpvOpFwidthFine:
   

Mesa (vulkan): i965: Allow mul+add fusing again

[Jason Ekstrand]

Module: Mesa
Branch: vulkan
Commit: 6d658e9bd546581a0841e7acb8915dc05d44c628
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6d658e9bd546581a0841e7acb8915dc05d44c628

Author: Jason Ekstrand 
Date:   Fri Mar 25 15:53:40 2016 -0700

i965: Allow mul+add fusing again

---

 src/mesa/drivers/dri/i965/brw_nir.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_nir.c 
b/src/mesa/drivers/dri/i965/brw_nir.c
index ab6000b..8392189 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -495,7 +495,7 @@ brw_postprocess_nir(nir_shader *nir,
 
if (devinfo->gen >= 6) {
   /* Try and fuse multiply-adds */
-//  OPT(brw_nir_opt_peephole_ffma);
+  OPT(brw_nir_opt_peephole_ffma);
}
 
OPT(nir_opt_algebraic_late);

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Mesa (vulkan): nir/spirv: Get rid of the spirv2nir helper binary

[Jason Ekstrand]

Module: Mesa
Branch: vulkan
Commit: 98522c1853eac22b3501e8739020b362786d1811
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=98522c1853eac22b3501e8739020b362786d1811

Author: Jason Ekstrand 
Date:   Fri Mar 25 14:40:57 2016 -0700

nir/spirv: Get rid of the spirv2nir helper binary

This was useful once upon a time but now that we have a real Vulkan driver
to run our SPIR-V binaries through, there's really no point.

---

 src/compiler/Makefile.am | 16 +
 src/compiler/nir/spirv2nir.c | 55 
 2 files changed, 1 insertion(+), 70 deletions(-)

diff --git a/src/compiler/Makefile.am b/src/compiler/Makefile.am
index 8f37448..5032890 100644
--- a/src/compiler/Makefile.am
+++ b/src/compiler/Makefile.am
@@ -84,7 +84,7 @@ check_PROGRAMS += \
glsl/tests/sampler-types-test   \
glsl/tests/uniform-initializer-test
 
-noinst_PROGRAMS = glsl_compiler spirv2nir
+noinst_PROGRAMS = glsl_compiler
 
 glsl_tests_blob_test_SOURCES = \
glsl/tests/blob_test.c
@@ -176,20 +176,6 @@ glsl_glsl_test_LDADD = 
\
$(top_builddir)/src/libglsl_util.la \
$(PTHREAD_LIBS)
 
-spirv2nir_SOURCES = \
-   nir/spirv2nir.c
-
-spirv2nir_CPPFLAGS =   \
-   $(AM_CPPFLAGS)  \
-   -I$(top_builddir)/src/compiler/nir  \
-   -I$(top_srcdir)/src/compiler/nir
-
-spirv2nir_LDADD =  \
-   nir/libnir.la   \
-   $(top_builddir)/src/util/libmesautil.la \
-   -lm -lstdc++\
-   $(PTHREAD_LIBS)
-
 # We write our own rules for yacc and lex below. We'd rather use automake,
 # but automake makes it especially difficult for a number of reasons:
 #
diff --git a/src/compiler/nir/spirv2nir.c b/src/compiler/nir/spirv2nir.c
deleted file mode 100644
index c837186..000
--- a/src/compiler/nir/spirv2nir.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright © 2015 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *Jason Ekstrand (ja...@jlekstrand.net)
- *
- */
-
-/*
- * A simple executable that opens a SPIR-V shader, converts it to NIR, and
- * dumps out the result.  This should be useful for testing the
- * spirv_to_nir code.
- */
-
-#include "spirv/nir_spirv.h"
-
-#include 
-#include 
-#include 
-#include 
-
-int main(int argc, char **argv)
-{
-   int fd = open(argv[1], O_RDONLY);
-   off_t len = lseek(fd, 0, SEEK_END);
-
-   assert(len % 4 == 0);
-   size_t word_count = len / 4;
-
-   const void *map = mmap(NULL, len, PROT_READ, MAP_PRIVATE, fd, 0);
-   assert(map != NULL);
-
-   nir_function *func = spirv_to_nir(map, word_count, NULL, 0,
- MESA_SHADER_FRAGMENT, "main", NULL);
-   nir_print_shader(func->shader, stderr);
-}

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Mesa (vulkan): spirv/glsl: Add a helper for converting glsl opcodes into nir opcodes

[Jason Ekstrand]

Module: Mesa
Branch: vulkan
Commit: 00fa795cd3bfd89b925698367173167656d4ae6c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=00fa795cd3bfd89b925698367173167656d4ae6c

Author: Jason Ekstrand 
Date:   Fri Mar 25 15:15:45 2016 -0700

spirv/glsl: Add a helper for converting glsl opcodes into nir opcodes

This is similar to the way that regular ALU operations are handled.

---

 src/compiler/nir/spirv/vtn_glsl450.c | 117 +--
 1 file changed, 56 insertions(+), 61 deletions(-)

diff --git a/src/compiler/nir/spirv/vtn_glsl450.c 
b/src/compiler/nir/spirv/vtn_glsl450.c
index 3360fda..e05d28f 100644
--- a/src/compiler/nir/spirv/vtn_glsl450.c
+++ b/src/compiler/nir/spirv/vtn_glsl450.c
@@ -359,6 +359,57 @@ build_frexp(nir_builder *b, nir_ssa_def *x, nir_ssa_def 
**exponent)
  nir_bcsel(b, is_not_zero, exponent_value, zero));
 }
 
+static nir_op
+vtn_nir_alu_op_for_spirv_glsl_opcode(enum GLSLstd450 opcode)
+{
+   switch (opcode) {
+   case GLSLstd450Round: return nir_op_fround_even;
+   case GLSLstd450RoundEven: return nir_op_fround_even;
+   case GLSLstd450Trunc: return nir_op_ftrunc;
+   case GLSLstd450FAbs:  return nir_op_fabs;
+   case GLSLstd450SAbs:  return nir_op_iabs;
+   case GLSLstd450FSign: return nir_op_fsign;
+   case GLSLstd450SSign: return nir_op_isign;
+   case GLSLstd450Floor: return nir_op_ffloor;
+   case GLSLstd450Ceil:  return nir_op_fceil;
+   case GLSLstd450Fract: return nir_op_ffract;
+   case GLSLstd450Sin:   return nir_op_fsin;
+   case GLSLstd450Cos:   return nir_op_fcos;
+   case GLSLstd450Pow:   return nir_op_fpow;
+   case GLSLstd450Exp2:  return nir_op_fexp2;
+   case GLSLstd450Log2:  return nir_op_flog2;
+   case GLSLstd450Sqrt:  return nir_op_fsqrt;
+   case GLSLstd450InverseSqrt:   return nir_op_frsq;
+   case GLSLstd450FMin:  return nir_op_fmin;
+   case GLSLstd450UMin:  return nir_op_umin;
+   case GLSLstd450SMin:  return nir_op_imin;
+   case GLSLstd450FMax:  return nir_op_fmax;
+   case GLSLstd450UMax:  return nir_op_umax;
+   case GLSLstd450SMax:  return nir_op_imax;
+   case GLSLstd450FMix:  return nir_op_flrp;
+   case GLSLstd450Fma:   return nir_op_ffma;
+   case GLSLstd450Ldexp: return nir_op_ldexp;
+   case GLSLstd450FindILsb:  return nir_op_find_lsb;
+   case GLSLstd450FindSMsb:  return nir_op_ifind_msb;
+   case GLSLstd450FindUMsb:  return nir_op_ufind_msb;
+
+   /* Packing/Unpacking functions */
+   case GLSLstd450PackSnorm4x8: return nir_op_pack_snorm_4x8;
+   case GLSLstd450PackUnorm4x8: return nir_op_pack_unorm_4x8;
+   case GLSLstd450PackSnorm2x16:return nir_op_pack_snorm_2x16;
+   case GLSLstd450PackUnorm2x16:return nir_op_pack_unorm_2x16;
+   case GLSLstd450PackHalf2x16: return nir_op_pack_half_2x16;
+   case GLSLstd450UnpackSnorm4x8:   return nir_op_unpack_snorm_4x8;
+   case GLSLstd450UnpackUnorm4x8:   return nir_op_unpack_unorm_4x8;
+   case GLSLstd450UnpackSnorm2x16:  return nir_op_unpack_snorm_2x16;
+   case GLSLstd450UnpackUnorm2x16:  return nir_op_unpack_unorm_2x16;
+   case GLSLstd450UnpackHalf2x16:   return nir_op_unpack_half_2x16;
+
+   default:
+  unreachable("No NIR equivalent");
+   }
+}
+
 static void
 handle_glsl450_alu(struct vtn_builder *b, enum GLSLstd450 entrypoint,
const uint32_t *w, unsigned count)
@@ -372,39 +423,21 @@ handle_glsl450_alu(struct vtn_builder *b, enum GLSLstd450 
entrypoint,
 
/* Collect the various SSA sources */
unsigned num_inputs = count - 5;
-   nir_ssa_def *src[3];
+   nir_ssa_def *src[3] = { NULL, };
for (unsigned i = 0; i < num_inputs; i++)
   src[i] = vtn_ssa_value(b, w[i + 5])->def;
 
-   nir_op op;
switch (entrypoint) {
-   case GLSLstd450Round:   op = nir_op_fround_even;   break; /* TODO */
-   case GLSLstd450RoundEven:   op = nir_op_fround_even;   break;
-   case GLSLstd450Trunc:   op = nir_op_ftrunc;break;
-   case GLSLstd450FAbs:op = nir_op_fabs;  break;
-   case GLSLstd450SAbs:op = nir_op_iabs;  break;
-   case GLSLstd450FSign:   op = nir_op_fsign; break;
-   case GLSLstd450SSign:   op = nir_op_isign; break;
-   case GLSLstd450Floor:   op = nir_op_ffloor;break;
-   case GLSLstd450Ceil:op = nir_op_fceil; break;
-   case GLSLstd450Fract:   op = nir_op_ffract;break;
case GLSLstd450Radians:
   val->ssa->def = nir_fmul(nb, src[0], nir_imm_float(nb, 0.01745329251));
   return;
case GLSLstd450Degrees:
   val->ssa->def = nir_fmul(nb, src[0], nir_imm_float(nb, 57.2957795131));
   return;
-   case GLSLstd450Sin: op = nir_op_fsin;   break;
-   case GLSLstd450Cos: op = nir_op_fcos;   break;
case GLSLstd450Tan:

Mesa (vulkan): anv/image: Enable specifying a surface's minimum pitch

[Nanley Chery]

Module: Mesa
Branch: vulkan
Commit: 4eab37d6cda54a4ac600347f764ef223c3a7459f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4eab37d6cda54a4ac600347f764ef223c3a7459f

Author: Nanley Chery 
Date:   Mon Mar 21 10:41:06 2016 -0700

anv/image: Enable specifying a surface's minimum pitch

This is required to create multiple, horizontally adjacent, max-width
images from one blit2d surface. This is also required for more accurate
width specification of surfaces within a larger surface (which is seen
as the smaller surface's enclosing region).

Note that anv_image_create_info::stride has been unused since commit,
b36938964063a4072abfd779f5607743dbc3b6f1 .

Signed-off-by: Nanley Chery 
Reviewed-by: Jason Ekstrand 

---

 src/intel/vulkan/anv_image.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index b47425b..266fbe7 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -138,7 +138,7 @@ make_surface(const struct anv_device *dev,
   .array_len = vk_info->arrayLayers,
   .samples = vk_info->samples,
   .min_alignment = 0,
-  .min_pitch = 0,
+  .min_pitch = anv_info->stride,
   .usage = choose_isl_surf_usage(image->usage, aspect),
   .tiling_flags = tiling_flags);
 

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Mesa (vulkan): anv/blit2d: Add a function to create an ImageView

[Nanley Chery]

Module: Mesa
Branch: vulkan
Commit: 0e82896a116ea0212dfcb13fb1456c93732d8564
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0e82896a116ea0212dfcb13fb1456c93732d8564

Author: Nanley Chery 
Date:   Fri Mar 18 15:12:32 2016 -0700

anv/blit2d: Add a function to create an ImageView

This function differs from the open-coded implementation in that the
ImageView's width is determined by the caller and is not unconditionally
set to match the number of texels within the surface's pitch.

Signed-off-by: Nanley Chery 
Reviewed-by: Jason Ekstrand 

---

 src/intel/vulkan/anv_meta_blit2d.c | 196 -
 1 file changed, 83 insertions(+), 113 deletions(-)

diff --git a/src/intel/vulkan/anv_meta_blit2d.c 
b/src/intel/vulkan/anv_meta_blit2d.c
index 87c3358..734ba8e 100644
--- a/src/intel/vulkan/anv_meta_blit2d.c
+++ b/src/intel/vulkan/anv_meta_blit2d.c
@@ -55,6 +55,81 @@ vk_format_for_size(int bs)
 }
 
 static void
+create_iview(struct anv_cmd_buffer *cmd_buffer,
+ struct anv_meta_blit2d_surf *surf,
+ struct anv_meta_blit2d_rect *rect,
+ VkImageUsageFlags usage,
+ VkImage *img,
+ struct anv_image_view *iview)
+{
+   struct isl_tile_info tile_info;
+   isl_tiling_get_info(_buffer->device->isl_dev,
+   surf->tiling, surf->bs, _info);
+   const unsigned tile_width_px = tile_info.width > surf->bs ?
+  tile_info.width / surf->bs : 1;
+   uint32_t *rect_y = (usage == VK_IMAGE_USAGE_SAMPLED_BIT) ?
+  >src_y : >dst_y;
+   uint32_t *rect_x = (usage == VK_IMAGE_USAGE_SAMPLED_BIT) ?
+  >src_x : >dst_x;
+
+   /* Define the shared state among all created image views */
+   const VkImageCreateInfo image_info = {
+  .sType = VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO,
+  .imageType = VK_IMAGE_TYPE_2D,
+  .format = vk_format_for_size(surf->bs),
+  .extent = {
+ .width = rect->width + (*rect_x) % tile_width_px,
+ .height = rect->height + (*rect_y) % tile_info.height,
+ .depth = 1,
+  },
+  .mipLevels = 1,
+  .arrayLayers = 1,
+  .samples = 1,
+  .tiling = surf->tiling == ISL_TILING_LINEAR ?
+VK_IMAGE_TILING_LINEAR : VK_IMAGE_TILING_OPTIMAL,
+  .usage = usage,
+   };
+
+   /* Create the VkImage that is bound to the surface's memory. */
+   anv_image_create(anv_device_to_handle(cmd_buffer->device),
+&(struct anv_image_create_info) {
+   .vk_info = _info,
+   .isl_tiling_flags = 1 << surf->tiling,
+   .stride = surf->pitch,
+}, _buffer->pool->alloc, img);
+
+   /* We could use a vk call to bind memory, but that would require
+* creating a dummy memory object etc. so there's really no point.
+*/
+   anv_image_from_handle(*img)->bo = surf->bo;
+   anv_image_from_handle(*img)->offset = surf->base_offset;
+
+   /* Create a VkImageView that starts at the tile aligned offset closest
+* to the provided x/y offset into the surface.
+*/
+   uint32_t img_o = 0;
+   isl_surf_get_image_intratile_offset_el_xy(_buffer->device->isl_dev,
+ _image_from_handle(*img)->
+color_surface.isl,
+ *rect_x, *rect_y,
+ _o, rect_x, rect_y);
+   anv_image_view_init(iview, cmd_buffer->device,
+   &(VkImageViewCreateInfo) {
+  .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
+  .image = *img,
+  .viewType = VK_IMAGE_VIEW_TYPE_2D,
+  .format = image_info.format,
+  .subresourceRange = {
+ .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
+ .baseMipLevel = 0,
+ .levelCount = 1,
+ .baseArrayLayer = 0,
+ .layerCount = 1
+  },
+   }, cmd_buffer, img_o, usage);
+}
+
+static void
 meta_emit_blit2d(struct anv_cmd_buffer *cmd_buffer,
struct anv_image_view *src_iview,
VkOffset3D src_offset,
@@ -260,132 +335,27 @@ anv_meta_blit2d(struct anv_cmd_buffer *cmd_buffer,
 struct anv_meta_blit2d_rect *rects)
 {
VkDevice vk_device = anv_device_to_handle(cmd_buffer->device);
-   VkFormat src_format = vk_format_for_size(src->bs);
-   VkFormat dst_format = vk_format_for_size(dst->bs);
VkImageUsageFlags src_usage = VK_IMAGE_USAGE_SAMPLED_BIT;
VkImageUsageFlags dst_usage = VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
 
for (unsigned r = 0; r < num_rects; ++r) {
-
-  /* Create VkImages */
-  

Mesa (master): glsl: reduce buffer block duplication

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 8683d54d2be82519c31e087e17dd936d13fa9d07
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8683d54d2be82519c31e087e17dd936d13fa9d07

Author: Timothy Arceri 
Date:   Thu Mar 24 12:11:01 2016 +1100

glsl: reduce buffer block duplication

This reduces some of the craziness required for handling buffer
blocks. The problem is each shader stage holds its own information
about a block in memory, we were copying that information to a
program wide list but the per stage information remained meaning
when a binding was updated we needed to update all versions of it.

This changes the per stage blocks to instead point to a single
version of the block information in the program list.

Acked-by: Kenneth Graunke 

---

 src/compiler/glsl/link_uniform_initializers.cpp |  2 +-
 src/compiler/glsl/link_uniforms.cpp | 12 ++--
 src/compiler/glsl/linker.cpp| 78 +++--
 src/compiler/glsl/standalone_scaffolding.cpp|  5 --
 src/mesa/main/mtypes.h  |  9 +--
 src/mesa/main/uniforms.c| 33 +--
 6 files changed, 57 insertions(+), 82 deletions(-)

diff --git a/src/compiler/glsl/link_uniform_initializers.cpp 
b/src/compiler/glsl/link_uniform_initializers.cpp
index 3609f81..7d280cc 100644
--- a/src/compiler/glsl/link_uniform_initializers.cpp
+++ b/src/compiler/glsl/link_uniform_initializers.cpp
@@ -183,7 +183,7 @@ set_block_binding(gl_shader_program *prog, const char 
*block_name, int binding)
 
  if (stage_index != -1) {
 struct gl_shader *sh = prog->_LinkedShaders[i];
-sh->BufferInterfaceBlocks[stage_index].Binding = binding;
+sh->BufferInterfaceBlocks[stage_index]->Binding = binding;
  }
   }
 }
diff --git a/src/compiler/glsl/link_uniforms.cpp 
b/src/compiler/glsl/link_uniforms.cpp
index 940cc61..807b069 100644
--- a/src/compiler/glsl/link_uniforms.cpp
+++ b/src/compiler/glsl/link_uniforms.cpp
@@ -954,6 +954,8 @@ link_cross_validate_uniform_block(void *mem_ctx,
   new_block->Uniforms,
   sizeof(*linked_block->Uniforms) * linked_block->NumUniforms);
 
+   linked_block->Name = ralloc_strdup(*linked_blocks, linked_block->Name);
+
for (unsigned int i = 0; i < linked_block->NumUniforms; i++) {
   struct gl_uniform_buffer_variable *ubo_var =
  _block->Uniforms[i];
@@ -1005,9 +1007,9 @@ link_update_uniform_buffer_variables(struct gl_shader 
*shader)
 
   const unsigned l = strlen(var->name);
   for (unsigned i = 0; i < shader->NumBufferInterfaceBlocks; i++) {
- for (unsigned j = 0; j < 
shader->BufferInterfaceBlocks[i].NumUniforms; j++) {
+ for (unsigned j = 0; j < 
shader->BufferInterfaceBlocks[i]->NumUniforms; j++) {
 if (sentinel) {
-   const char *begin = 
shader->BufferInterfaceBlocks[i].Uniforms[j].Name;
+   const char *begin = 
shader->BufferInterfaceBlocks[i]->Uniforms[j].Name;
const char *end = strchr(begin, sentinel);
 
if (end == NULL)
@@ -1022,7 +1024,7 @@ link_update_uniform_buffer_variables(struct gl_shader 
*shader)
   break;
}
 } else if (!strcmp(var->name,
-   
shader->BufferInterfaceBlocks[i].Uniforms[j].Name)) {
+   
shader->BufferInterfaceBlocks[i]->Uniforms[j].Name)) {
found = true;
var->data.location = j;
break;
@@ -1148,9 +1150,9 @@ link_assign_uniform_locations(struct gl_shader_program 
*prog,
   sh->num_combined_uniform_components = sh->num_uniform_components;
 
   for (unsigned i = 0; i < sh->NumBufferInterfaceBlocks; i++) {
- if (!sh->BufferInterfaceBlocks[i].IsShaderStorage) {
+ if (!sh->BufferInterfaceBlocks[i]->IsShaderStorage) {
 sh->num_combined_uniform_components +=
-   sh->BufferInterfaceBlocks[i].UniformBufferSize / 4;
+   sh->BufferInterfaceBlocks[i]->UniformBufferSize / 4;
  }
   }
}
diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index 76b700d..cd35464 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -1192,11 +1192,11 @@ interstage_cross_validate_uniform_blocks(struct 
gl_shader_program *prog)
 int index = link_cross_validate_uniform_block(prog,
   
>BufferInterfaceBlocks,
   
>NumBufferInterfaceBlocks,
-  
>BufferInterfaceBlocks[j]);
+  
sh->BufferInterfaceBlocks[j]);
 
 if (index == -1) {
linker_error(prog, "uniform block `%s' has mismatching 
definitions\n",
-

Mesa (vulkan): nir/algebraic: Get rid of a redundant copy of fdiv lowering

[Jason Ekstrand]

Module: Mesa
Branch: vulkan
Commit: 13bad493b49fe24bd16cbec14592f22c94a826f8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=13bad493b49fe24bd16cbec14592f22c94a826f8

Author: Jason Ekstrand 
Date:   Fri Mar 25 12:12:12 2016 -0700

nir/algebraic: Get rid of a redundant copy of fdiv lowering

---

 src/compiler/nir/nir_opt_algebraic.py | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py
index 60cd731..2e9cd5f 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -82,7 +82,6 @@ optimizations = [
(('imul', a, 1), a),
(('fmul', a, -1.0), ('fneg', a)),
(('imul', a, -1), ('ineg', a)),
-   (('fdiv', a, b), ('fmul', a, ('frcp', b)), 'options->lower_fdiv'),
(('~ffma', 0.0, a, b), b),
(('~ffma', a, 0.0, b), b),
(('~ffma', a, b, 0.0), ('fmul', a, b)),

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Mesa (vulkan): nir/builder: Simplify nir_ssa_undef a bit

[Jason Ekstrand]

Module: Mesa
Branch: vulkan
Commit: b75d770963a6fde474ed84cad73ee754922bccbf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b75d770963a6fde474ed84cad73ee754922bccbf

Author: Jason Ekstrand 
Date:   Fri Mar 25 10:43:17 2016 -0700

nir/builder: Simplify nir_ssa_undef a bit

---

 src/compiler/nir/nir_builder.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h
index 22646f7..3dc7c25 100644
--- a/src/compiler/nir/nir_builder.h
+++ b/src/compiler/nir/nir_builder.h
@@ -83,8 +83,7 @@ nir_ssa_undef(nir_builder *build, unsigned num_components, 
unsigned bit_size)
if (!undef)
   return NULL;
 
-   nir_instr_insert(nir_before_block(nir_start_block(build->impl)),
->instr);
+   nir_instr_insert(nir_before_cf_list(>impl->body), >instr);
 
return >def;
 }

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Mesa (vulkan): nir/algebraic: Add better lowering of ldexp

[Jason Ekstrand]

Module: Mesa
Branch: vulkan
Commit: 08fe89864b94f970ce73368636a87eace3c81663
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=08fe89864b94f970ce73368636a87eace3c81663

Author: Jason Ekstrand 
Date:   Fri Mar 25 12:09:33 2016 -0700

nir/algebraic: Add better lowering of ldexp

---

 src/compiler/nir/nir_opt_algebraic.py | 29 +++--
 1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py
index ed21c5d..60cd731 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -276,8 +276,6 @@ optimizations = [
(('frem', a, b), ('fsub', a, ('fmul', b, ('ftrunc', ('fdiv', a, b, 
'options->lower_fmod'),
(('uadd_carry', a, b), ('b2i', ('ult', ('iadd', a, b), a)), 
'options->lower_uadd_carry'),
(('usub_borrow', a, b), ('b2i', ('ult', a, b)), 
'options->lower_usub_borrow'),
-   (('ldexp', 'x', 'exp'),
-('fmul', 'x', ('ishl', ('imin', ('imax', ('iadd', 'exp', 0x7f), 0), 0xff), 
23))),
 
(('bitfield_insert', 'base', 'insert', 'offset', 'bits'),
 ('bcsel', ('ilt', 31, 'bits'), 'insert',
@@ -359,6 +357,33 @@ optimizations = [
  'options->lower_unpack_snorm_4x8'),
 ]
 
+def fexp2i(exp):
+   # We assume that exp is already in range.
+   return ('ishl', ('iadd', exp, 127), 23)
+
+def ldexp32(f, exp):
+   # First, we clamp exp to a reasonable range.  The maximum range that we
+   # need is the largest range for an exponent, ([-127, 128] if you include
+   # inf and 0) plus the number of mantissa bits in either direction to
+   # account for denormals.  This means that we need at least a range of
+   # [-150, 151].  For our implementation, however, what we really care
+   # about is that neither exp/2 nor exp-exp/2 go out of the regular range
+   # for floating-point exponents.
+   exp = ('imin', ('imax', exp, -252), 254)
+
+   # Now we compute two powers of 2, one for exp/2 and one for exp-exp/2.
+   # While the spec technically defines ldexp as f * 2.0^exp, simply
+   # multiplying once doesn't work when denormals are involved because
+   # 2.0^exp may not be representable even though ldexp(f, exp) is (see
+   # comments above about range).  Instead, we create two powers of two and
+   # multiply by them each in turn.  That way the effective range of our
+   # exponent is doubled.
+   pow2_1 = fexp2i(('ishr', exp, 1))
+   pow2_2 = fexp2i(('isub', exp, ('ishr', exp, 1)))
+   return ('fmul', ('fmul', f, pow2_1), pow2_2)
+
+optimizations += [(('ldexp', 'x', 'exp'), ldexp32('x', 'exp'))]
+
 # Unreal Engine 4 demo applications open-codes bitfieldReverse()
 def bitfield_reverse(u):
 step1 = ('ior', ('ishl', u, 16), ('ushr', u, 16))

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Mesa (vulkan): i965/vec4: Get rid of a stray predicate inverse in opquantizef16

[Jason Ekstrand]

Module: Mesa
Branch: vulkan
Commit: 38250a9ca32ea79ada10918952c2917b535a4536
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=38250a9ca32ea79ada10918952c2917b535a4536

Author: Jason Ekstrand 
Date:   Fri Mar 25 13:55:37 2016 -0700

i965/vec4: Get rid of a stray predicate inverse in opquantizef16

This fixes 30 opquantize CTS tests on HSW

---

 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 7c06f92..a5db2f9 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -1248,7 +1248,6 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
   /* Select that or zero based on normal status */
   inst = emit(BRW_OPCODE_SEL, dst, zero, tmp32);
   inst->predicate = BRW_PREDICATE_NORMAL;
-  inst->predicate_inverse = true;
   inst->saturate = instr->dest.saturate;
   break;
}

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Mesa (vulkan): nir/builder: Add a bit size field to nir_ssa_undef

[Jason Ekstrand]

Module: Mesa
Branch: vulkan
Commit: d2eee52a6554217b21b93ab9d8ab39abee331dd8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2eee52a6554217b21b93ab9d8ab39abee331dd8

Author: Jason Ekstrand 
Date:   Fri Mar 25 10:40:24 2016 -0700

nir/builder: Add a bit size field to nir_ssa_undef

---

 src/compiler/nir/nir_builder.h| 3 ++-
 src/compiler/nir/spirv/spirv_to_nir.c | 4 ++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h
index 94f183c..22646f7 100644
--- a/src/compiler/nir/nir_builder.h
+++ b/src/compiler/nir/nir_builder.h
@@ -75,10 +75,11 @@ nir_builder_cf_insert(nir_builder *build, nir_cf_node *cf)
 }
 
 static inline nir_ssa_def *
-nir_ssa_undef(nir_builder *build, unsigned num_components)
+nir_ssa_undef(nir_builder *build, unsigned num_components, unsigned bit_size)
 {
nir_ssa_undef_instr *undef =
   nir_ssa_undef_instr_create(build->shader, num_components);
+   undef->def.bit_size = bit_size;
if (!undef)
   return NULL;
 
diff --git a/src/compiler/nir/spirv/spirv_to_nir.c 
b/src/compiler/nir/spirv/spirv_to_nir.c
index 42a1f95..cbc87d1 100644
--- a/src/compiler/nir/spirv/spirv_to_nir.c
+++ b/src/compiler/nir/spirv/spirv_to_nir.c
@@ -1496,7 +1496,7 @@ vtn_handle_image(struct vtn_builder *b, SpvOp opcode,
  assert(w[5] == SpvImageOperandsSampleMask);
  image.sample = vtn_ssa_value(b, w[6])->def;
   } else {
- image.sample = nir_ssa_undef(>nb, 1);
+ image.sample = nir_ssa_undef(>nb, 1, 32);
   }
   break;
 
@@ -1511,7 +1511,7 @@ vtn_handle_image(struct vtn_builder *b, SpvOp opcode,
  assert(w[4] == SpvImageOperandsSampleMask);
  image.sample = vtn_ssa_value(b, w[5])->def;
   } else {
- image.sample = nir_ssa_undef(>nb, 1);
+ image.sample = nir_ssa_undef(>nb, 1, 32);
   }
   break;
 

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Mesa (vulkan): nir: Add a better comment for INTRINSIC_RANGE

[Jason Ekstrand]

Module: Mesa
Branch: vulkan
Commit: b50f7f0011e6f497277c575bc36b5dab80d45bea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b50f7f0011e6f497277c575bc36b5dab80d45bea

Author: Jason Ekstrand 
Date:   Fri Mar 25 10:12:52 2016 -0700

nir: Add a better comment for INTRINSIC_RANGE

---

 src/compiler/nir/nir.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 2fd75ec..de6b93c 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -986,8 +986,8 @@ typedef enum {
NIR_INTRINSIC_UCP_ID = 4,
 
/**
-* The range of a load operation.  This specifies the maximum amount of
-* data starting at the base offset (if any) that can be accessed.
+* The ammount of data, starting from BASE, that this instruction may
+* access.  This is used to provide bounds if the offset is not constant.
 */
NIR_INTRINSIC_RANGE = 5,
 

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Mesa (vulkan): nir/spirv: Use the nir_ssa_undef helper from nir_builder

[Jason Ekstrand]

Module: Mesa
Branch: vulkan
Commit: ab31951bef17a46d4fb38c42be46dd5955463801
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ab31951bef17a46d4fb38c42be46dd5955463801

Author: Jason Ekstrand 
Date:   Fri Mar 25 10:40:45 2016 -0700

nir/spirv: Use the nir_ssa_undef helper from nir_builder

---

 src/compiler/nir/spirv/spirv_to_nir.c | 13 -
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/src/compiler/nir/spirv/spirv_to_nir.c 
b/src/compiler/nir/spirv/spirv_to_nir.c
index cbc87d1..663f41f 100644
--- a/src/compiler/nir/spirv/spirv_to_nir.c
+++ b/src/compiler/nir/spirv/spirv_to_nir.c
@@ -38,11 +38,8 @@ vtn_undef_ssa_value(struct vtn_builder *b, const struct 
glsl_type *type)
 
if (glsl_type_is_vector_or_scalar(type)) {
   unsigned num_components = glsl_get_vector_elements(val->type);
-  nir_ssa_undef_instr *undef =
- nir_ssa_undef_instr_create(b->shader, num_components);
-
-  nir_instr_insert_before_cf_list(>impl->body, >instr);
-  val->def = >def;
+  unsigned bit_size = glsl_get_bit_size(glsl_get_base_type(val->type));
+  val->def = nir_ssa_undef(>nb, num_components, bit_size);
} else {
   unsigned elems = glsl_get_length(val->type);
   val->elems = ralloc_array(b, struct vtn_ssa_value *, elems);
@@ -1863,13 +1860,11 @@ vtn_vector_shuffle(struct vtn_builder *b, unsigned 
num_components,
 {
nir_alu_instr *vec = create_vec(b->shader, num_components, src0->bit_size);
 
-   nir_ssa_undef_instr *undef = nir_ssa_undef_instr_create(b->shader, 1);
-   nir_builder_instr_insert(>nb, >instr);
-
for (unsigned i = 0; i < num_components; i++) {
   uint32_t index = indices[i];
   if (index == 0x) {
- vec->src[i].src = nir_src_for_ssa(>def);
+ vec->src[i].src =
+nir_src_for_ssa(nir_ssa_undef(>nb, 1, src0->bit_size));
   } else if (index < src0->num_components) {
  vec->src[i].src = nir_src_for_ssa(src0);
  vec->src[i].swizzle[0] = index;

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Mesa (vulkan): nir/glsl: Stop carying a pointer to the nir_shader in the visitor

[Jason Ekstrand]

Module: Mesa
Branch: vulkan
Commit: add8c837b5ec7e8ef6a0eefe4bd673f944210fdb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=add8c837b5ec7e8ef6a0eefe4bd673f944210fdb

Author: Jason Ekstrand 
Date:   Fri Mar 25 10:05:36 2016 -0700

nir/glsl: Stop carying a pointer to the nir_shader in the visitor

---

 src/compiler/nir/glsl_to_nir.cpp | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/src/compiler/nir/glsl_to_nir.cpp b/src/compiler/nir/glsl_to_nir.cpp
index 7b8b466..2a469ec 100644
--- a/src/compiler/nir/glsl_to_nir.cpp
+++ b/src/compiler/nir/glsl_to_nir.cpp
@@ -46,7 +46,7 @@ namespace {
 class nir_visitor : public ir_visitor
 {
 public:
-   nir_visitor(nir_shader *shader, gl_shader *sh);
+   nir_visitor(nir_shader *shader);
~nir_visitor();
 
virtual void visit(ir_variable *);
@@ -85,8 +85,6 @@ private:
 
bool supports_ints;
 
-   struct gl_shader *sh;
-
nir_shader *shader;
nir_function_impl *impl;
nir_builder b;
@@ -140,7 +138,7 @@ glsl_to_nir(const struct gl_shader_program *shader_prog,
 
nir_shader *shader = nir_shader_create(NULL, stage, options);
 
-   nir_visitor v1(shader, sh);
+   nir_visitor v1(shader);
nir_function_visitor v2();
v2.run(sh->ir);
visit_exec_list(sh->ir, );
@@ -215,11 +213,10 @@ glsl_to_nir(const struct gl_shader_program *shader_prog,
return shader;
 }
 
-nir_visitor::nir_visitor(nir_shader *shader, gl_shader *sh)
+nir_visitor::nir_visitor(nir_shader *shader)
 {
this->supports_ints = shader->options->native_integers;
this->shader = shader;
-   this->sh = sh;
this->is_global = true;
this->var_table = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
  _mesa_key_pointer_equal);

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Mesa (master): st/xa: emit sampler view declarations in shaders

[Brian Paul]

Module: Mesa
Branch: master
Commit: a8e5edaadfd5df6a473566ff55978aca27a37679
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8e5edaadfd5df6a473566ff55978aca27a37679

Author: Brian Paul 
Date:   Fri Mar 25 14:06:39 2016 -0600

st/xa: emit sampler view declarations in shaders

Fixes recent regressions with the VMware gallium driver.

Reviewed-by: Charmaine Lee 
Tested-by: Charmaine Lee 

---

 src/gallium/state_trackers/xa/xa_tgsi.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/src/gallium/state_trackers/xa/xa_tgsi.c 
b/src/gallium/state_trackers/xa/xa_tgsi.c
index 5d8b807..a50393d 100644
--- a/src/gallium/state_trackers/xa/xa_tgsi.c
+++ b/src/gallium/state_trackers/xa/xa_tgsi.c
@@ -339,6 +339,16 @@ create_yuv_shader(struct pipe_context *pipe, struct 
ureg_program *ureg)
 u_sampler = ureg_DECL_sampler(ureg, 1);
 v_sampler = ureg_DECL_sampler(ureg, 2);
 
+ureg_DECL_sampler_view(ureg, 0, TGSI_TEXTURE_2D,
+   TGSI_RETURN_TYPE_FLOAT, TGSI_RETURN_TYPE_FLOAT,
+   TGSI_RETURN_TYPE_FLOAT, TGSI_RETURN_TYPE_FLOAT);
+ureg_DECL_sampler_view(ureg, 1, TGSI_TEXTURE_2D,
+   TGSI_RETURN_TYPE_FLOAT, TGSI_RETURN_TYPE_FLOAT,
+   TGSI_RETURN_TYPE_FLOAT, TGSI_RETURN_TYPE_FLOAT);
+ureg_DECL_sampler_view(ureg, 2, TGSI_TEXTURE_2D,
+   TGSI_RETURN_TYPE_FLOAT, TGSI_RETURN_TYPE_FLOAT,
+   TGSI_RETURN_TYPE_FLOAT, TGSI_RETURN_TYPE_FLOAT);
+
 matrow0 = ureg_DECL_constant(ureg, 0);
 matrow1 = ureg_DECL_constant(ureg, 1);
 matrow2 = ureg_DECL_constant(ureg, 2);
@@ -475,6 +485,9 @@ create_fs(struct pipe_context *pipe, unsigned fs_traits)
 }
 if (is_composite) {
src_sampler = ureg_DECL_sampler(ureg, 0);
+ureg_DECL_sampler_view(ureg, 0, TGSI_TEXTURE_2D,
+   TGSI_RETURN_TYPE_FLOAT, TGSI_RETURN_TYPE_FLOAT,
+   TGSI_RETURN_TYPE_FLOAT, TGSI_RETURN_TYPE_FLOAT);
src_input = ureg_DECL_fs_input(ureg,
   TGSI_SEMANTIC_GENERIC, 0,
   TGSI_INTERPOLATE_PERSPECTIVE);
@@ -494,12 +507,18 @@ create_fs(struct pipe_context *pipe, unsigned fs_traits)
 
 if (has_mask) {
mask_sampler = ureg_DECL_sampler(ureg, 1);
+ureg_DECL_sampler_view(ureg, 1, TGSI_TEXTURE_2D,
+   TGSI_RETURN_TYPE_FLOAT, TGSI_RETURN_TYPE_FLOAT,
+   TGSI_RETURN_TYPE_FLOAT, TGSI_RETURN_TYPE_FLOAT);
mask_pos = ureg_DECL_fs_input(ureg,
  TGSI_SEMANTIC_GENERIC, 1,
  TGSI_INTERPOLATE_PERSPECTIVE);
 }
 #if 0  /* unused right now */
 dst_sampler = ureg_DECL_sampler(ureg, 2);
+ureg_DECL_sampler_view(ureg, 2, TGSI_TEXTURE_2D,
+   TGSI_RETURN_TYPE_FLOAT, TGSI_RETURN_TYPE_FLOAT,
+   TGSI_RETURN_TYPE_FLOAT, TGSI_RETURN_TYPE_FLOAT);
 dst_pos = ureg_DECL_fs_input(ureg,
 TGSI_SEMANTIC_POSITION, 2,
 TGSI_INTERPOLATE_PERSPECTIVE);

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Mesa (master): 48 new commits

[Tim Rowley]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=74a04840e5e7213e1b317cfee63ce1e236c622fa
Author: Tim Rowley 
Date:   Thu Mar 24 11:52:51 2016 -0600

swr: [rasterizer jitter] Fix MASKLOADD AVX prototype (float -> i32)

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=93c1a2dedfa8b786e969a9ae44765bf6841218ef
Author: Tim Rowley 
Date:   Thu Mar 24 00:01:23 2016 -0600

swr: [rasterizer core] NUMA optimizations...

- Affinitize hot-tile memory to specific NUMA nodes.
- Only do BE work for macrotiles assoicated with the numa node

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=090be2e434d6023428faa9842d38f9d5c3cef67a
Author: Tim Rowley 
Date:   Wed Mar 23 18:12:11 2016 -0600

swr: [rasterizer jitter] Fix logic bug for alpha-to-coverage.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0767e820fd96e8bac2943fa8942bea3ff81b8bd9
Author: Tim Rowley 
Date:   Tue Mar 22 17:28:06 2016 -0600

swr: [rasterizer core] Fix Compute workitem retirement

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=813e89c0cc0ea6a6ed4b69303073995b4c4c7666
Author: Tim Rowley 
Date:   Tue Mar 22 15:13:29 2016 -0600

swr: [rasterizer core] Cleanup state ring arena after last draw that 
references it completes

Rather than waiting for the API thread to re-use it.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=83822d7ed580e764b3e0a6cb773310af2473f062
Author: Tim Rowley 
Date:   Tue Mar 22 12:41:13 2016 -0600

swr: [rasterizer jitter] add missing include for llvm jitevents

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=51549912d1b1137572a0692972d1059ebb2e3384
Author: Tim Rowley 
Date:   Tue Mar 22 09:27:18 2016 -0600

swr: [rasterizer core] Reduce Arena blocksize to 128KB (from 1MB).

With global allocator this doesn't seem to affect performance at all.
Overall memory consumption drops by up to 85%.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed5b9539191ca700887566a82162c06d94f57497
Author: Tim Rowley 
Date:   Mon Mar 21 17:55:46 2016 -0600

swr: [rasterizer core] One last pass at Arena optimizations

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee6be9e92dbdc3dbeb26e0f873c1784d563bf641
Author: Tim Rowley 
Date:   Mon Mar 21 17:30:03 2016 -0600

swr: [rasterizer core] CachedArena optimizations

Reduce list traversal during Alloc and Free.

Add ability to have multiple lists based on alloc size (not used for now)

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=68314b676968e2cf0f8e94f573fa28e766e48349
Author: Tim Rowley 
Date:   Mon Mar 21 14:08:38 2016 -0600

swr: [rasterizer jitter] support llvm-svn

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec9d4c4b372df773e4453c228b938e7c6c526c4c
Author: Tim Rowley 
Date:   Mon Mar 21 11:15:32 2016 -0600

swr: [rasterizer core] Globally cache allocated arena blocks for fast 
re-allocation.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=12ce9d9aa1819c0d7fb969b459a070c3cc9a617f
Author: Tim Rowley 
Date:   Fri Mar 18 12:11:20 2016 -0600

swr: [rasterizer] more arena work

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4893224e2851683341d848926d267e5b5a4f39dc
Author: Tim Rowley 
Date:   Fri Mar 18 11:48:47 2016 -0600

swr: [rasterizer core] Add clipping against user clip distances in the 
NullPS backend.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=700a5b06e036d7515c6d5f2f9e2d40e5a65eb964
Author: Tim Rowley 
Date:   Thu Mar 17 18:10:25 2016 -0600

swr: [rasterizer core] Arena optimizations - preparing for global allocator.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5899076b6b24a7275fb6b4ad6a42686225ef0156
Author: Tim Rowley 
Date:   Thu Mar 17 16:50:46 2016 -0600

swr: [rasterizer core] Reset DrawContext arena at end of draw rather than 
upon reclaim of DC

Keeps overall memory consumption lower.
Also, remove unused knobs.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=73904184412fa5e9c2f1bab8580664c449f12aa2
Author: Tim Rowley 
Date:   Thu Mar 17 16:12:17 2016 -0600

swr: [rasterizer core] Add clipping of user clip planes in clipper.

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4b4547a7216ec6309da54f508211c0aba02ad5e3
Author: Tim Rowley 
Date:   Thu Mar 17 15:39:13 2016 -0600

swr: [rasterizer] Reduce max in-flight draws to 96 (by default)

URL:

Mesa (master): radeonsi: add support for Polaris (v2)

[Alex Deucher]

Module: Mesa
Branch: master
Commit: 42e442d888ce2d3dcb95350d17c298791f5d76cc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=42e442d888ce2d3dcb95350d17c298791f5d76cc

Author: Sonny Jiang 
Date:   Wed Nov  4 16:13:07 2015 -0500

radeonsi: add support for Polaris (v2)

v2: Polaris chips should be defined after Stoney

Signed-off-by: Sonny Jiang  (v1)
Reviewed-by: Michel Dänzer  (v1)
Signed-off-by: Leo Liu  (v2 diff)
Reviewed-by: Alex Deucher  (v2 diff)

---

 src/gallium/drivers/radeon/r600_pipe_common.c | 9 +
 src/gallium/drivers/radeon/radeon_winsys.h| 2 ++
 src/gallium/drivers/radeonsi/si_pipe.c| 2 ++
 src/gallium/drivers/radeonsi/si_state.c   | 8 
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 8 
 5 files changed, 29 insertions(+)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index eed9d83..720fc06 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -467,6 +467,8 @@ static const char* r600_get_chip_name(struct 
r600_common_screen *rscreen)
case CHIP_ICELAND: return "AMD ICELAND";
case CHIP_CARRIZO: return "AMD CARRIZO";
case CHIP_FIJI: return "AMD FIJI";
+   case CHIP_POLARIS10: return "AMD POLARIS10";
+   case CHIP_POLARIS11: return "AMD POLARIS11";
case CHIP_STONEY: return "AMD STONEY";
default: return "AMD unknown";
}
@@ -598,6 +600,13 @@ const char *r600_get_llvm_processor_name(enum 
radeon_family family)
case CHIP_FIJI: return "fiji";
case CHIP_STONEY: return "stoney";
 #endif
+#if HAVE_LLVM <= 0x0308
+   case CHIP_POLARIS10: return "tonga";
+   case CHIP_POLARIS11: return "tonga";
+#else
+   case CHIP_POLARIS10: return "polaris10";
+   case CHIP_POLARIS11: return "polaris11";
+#endif
default: return "";
}
 }
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index d35e963..baecca7 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -124,6 +124,8 @@ enum radeon_family {
 CHIP_CARRIZO,
 CHIP_FIJI,
 CHIP_STONEY,
+CHIP_POLARIS10,
+CHIP_POLARIS11,
 CHIP_LAST,
 };
 
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index dd1103e..ed84dc2 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -598,6 +598,8 @@ static bool si_init_gs_info(struct si_screen *sscreen)
case CHIP_HAWAII:
case CHIP_TONGA:
case CHIP_FIJI:
+   case CHIP_POLARIS10:
+   case CHIP_POLARIS11:
sscreen->gs_table_depth = 32;
return true;
default:
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 1245f56..a2b0da9 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3946,6 +3946,14 @@ static void si_init_config(struct si_context *sctx)
raster_config_1 = 0x002e;
}
break;
+   case CHIP_POLARIS10:
+   raster_config = 0x1612;
+   raster_config_1 = 0x002a;
+   break;
+   case CHIP_POLARIS11:
+   raster_config = 0x1612;
+   raster_config_1 = 0x;
+   break;
case CHIP_TONGA:
raster_config = 0x1612;
raster_config_1 = 0x002a;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index 938b9c2..87d9a6a 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -237,6 +237,14 @@ static boolean do_winsys_init(struct amdgpu_winsys *ws, 
int fd)
   ws->family = FAMILY_VI;
   ws->rev_id = VI_FIJI_P_A0;
   break;
+   case CHIP_POLARIS10:
+  ws->family = FAMILY_VI;
+  ws->rev_id = VI_POLARIS10_P_A0;
+  break;
+   case CHIP_POLARIS11:
+  ws->family = FAMILY_VI;
+  ws->rev_id = VI_POLARIS11_M_A0;
+  break;
default:
   fprintf(stderr, "amdgpu: Unknown family.\n");
   goto fail;

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Mesa (master): radeonsi: add Polaris PCI IDs

[Alex Deucher]

Module: Mesa
Branch: master
Commit: f00c840578a70e479ffb99f6b64c73dc420179fa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f00c840578a70e479ffb99f6b64c73dc420179fa

Author: Sonny Jiang 
Date:   Wed Nov  4 11:01:33 2015 -0500

radeonsi: add Polaris PCI IDs

Signed-off-by: Sonny Jiang 
Reviewed-by: Alex Deucher  (Polaris10)
Reviewed-by: Michel Dänzer  (Polaris11)

---

 include/pci_ids/radeonsi_pci_ids.h | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/include/pci_ids/radeonsi_pci_ids.h 
b/include/pci_ids/radeonsi_pci_ids.h
index bcf15a1..4df8e9d 100644
--- a/include/pci_ids/radeonsi_pci_ids.h
+++ b/include/pci_ids/radeonsi_pci_ids.h
@@ -182,4 +182,14 @@ CHIPSET(0x9877, CARRIZO_, CARRIZO)
 
 CHIPSET(0x7300, FIJI_, FIJI)
 
+CHIPSET(0x67E0, POLARIS11_, POLARIS11)
+CHIPSET(0x67E1, POLARIS11_, POLARIS11)
+CHIPSET(0x67E8, POLARIS11_, POLARIS11)
+CHIPSET(0x67E9, POLARIS11_, POLARIS11)
+CHIPSET(0x67EB, POLARIS11_, POLARIS11)
+CHIPSET(0x67FF, POLARIS11_, POLARIS11)
+
+CHIPSET(0x67C0, POLARIS10_, POLARIS10)
+CHIPSET(0x67DF, POLARIS10_, POLARIS10)
+
 CHIPSET(0x98E4, STONEY_, STONEY)

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Mesa (master): radeon/vce: add Polaris11 VCE firmware support

[Alex Deucher]

Module: Mesa
Branch: master
Commit: 0c5477465f08502fd81783ce17c449330537eb00
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c5477465f08502fd81783ce17c449330537eb00

Author: Sonny Jiang 
Date:   Tue Dec 15 15:16:29 2015 -0500

radeon/vce: add Polaris11 VCE firmware support

Signed-off-by: Sonny Jiang 

---

 src/gallium/drivers/radeon/radeon_vce.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/drivers/radeon/radeon_vce.c 
b/src/gallium/drivers/radeon/radeon_vce.c
index 2ab74e9..6584393 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -50,6 +50,7 @@
 #define FW_50_10_2 ((50 << 24) | (10 << 16) | (2 << 8))
 #define FW_50_17_3 ((50 << 24) | (17 << 16) | (3 << 8))
 #define FW_52_0_3 ((52 << 24) | (0 << 16) | (3 << 8))
+#define FW_52_4_3 ((52 << 24) | (4 << 16) | (3 << 8))
 
 /**
  * flush commands to the hardware
@@ -482,6 +483,7 @@ struct pipe_video_codec *rvce_create_encoder(struct 
pipe_context *context,
break;
 
case FW_52_0_3:
+   case FW_52_4_3:
radeon_vce_52_init(enc);
break;
 
@@ -514,6 +516,7 @@ bool rvce_is_fw_version_supported(struct r600_common_screen 
*rscreen)
case FW_50_10_2:
case FW_50_17_3:
case FW_52_0_3:
+   case FW_52_4_3:
return true;
default:
return false;

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Mesa (master): radeon/vce: disable two pipe mode for Polaris11

[Alex Deucher]

Module: Mesa
Branch: master
Commit: f87ed903fb6fd1bdb0cfa7a4dd5b9d00a9f38e31
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f87ed903fb6fd1bdb0cfa7a4dd5b9d00a9f38e31

Author: Sonny Jiang 
Date:   Tue Dec 15 15:33:40 2015 -0500

radeon/vce: disable two pipe mode for Polaris11

Signed-off-by: Sonny Jiang 
Reviewed-by: Leo Liu 

---

 src/gallium/drivers/radeon/radeon_vce.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_vce.c 
b/src/gallium/drivers/radeon/radeon_vce.c
index 6584393..99b82ca 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -409,7 +409,8 @@ struct pipe_video_codec *rvce_create_encoder(struct 
pipe_context *context,
 rscreen->info.drm_major == 3)
enc->use_vui = true;
if (rscreen->info.family >= CHIP_TONGA &&
- rscreen->info.family != CHIP_STONEY)
+   rscreen->info.family != CHIP_STONEY &&
+   rscreen->info.family != CHIP_POLARIS11)
enc->dual_pipe = true;
/* TODO enable B frame with dual instance */
if ((rscreen->info.family >= CHIP_TONGA) &&

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Mesa (master): winsys/amdgpu: addrlib - add Polaris support (v2)

[Alex Deucher]

Module: Mesa
Branch: master
Commit: f5e24b19e883281452952ecce3e811cda1f7946c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5e24b19e883281452952ecce3e811cda1f7946c

Author: Sonny Jiang 
Date:   Tue Nov  3 11:46:38 2015 -0500

winsys/amdgpu: addrlib - add Polaris support (v2)

v2: fix indentation as noted by Michel

Signed-off-by: Sonny Jiang 
Reviewed-by: Alex Deucher 
Reviewed-by: Michel Dänzer 

---

 src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp |  8 +++-
 src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h   |  2 ++
 src/gallium/winsys/amdgpu/drm/amdgpu_id.h| 10 +-
 3 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp 
b/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp
index 5702162..7c5d29a 100644
--- a/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp
+++ b/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp
@@ -351,6 +351,8 @@ AddrChipFamily CIAddrLib::HwlConvertChipFamily(
 m_settings.isIceland = ASICREV_IS_ICELAND_M(uChipRevision);
 m_settings.isTonga   = ASICREV_IS_TONGA_P(uChipRevision);
 m_settings.isFiji= ASICREV_IS_FIJI_P(uChipRevision);
+m_settings.isPolaris10   = 
ASICREV_IS_POLARIS10_P(uChipRevision);
+m_settings.isPolaris11   = 
ASICREV_IS_POLARIS11_M(uChipRevision);
 break;
 case FAMILY_CZ:
 m_settings.isCarrizo = 1;
@@ -403,7 +405,7 @@ BOOL_32 CIAddrLib::HwlInitGlobalParams(
 
 // @todo: VI
 // Move this to VI code path once created
-if (m_settings.isTonga)
+if (m_settings.isTonga || m_settings.isPolaris10)
 {
 m_pipes = 8;
 }
@@ -415,6 +417,10 @@ BOOL_32 CIAddrLib::HwlInitGlobalParams(
 {
 m_pipes = 16;
 }
+else if (m_settings.isPolaris11)
+{
+m_pipes = 4;
+}
 
 if (valid)
 {
diff --git a/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h 
b/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h
index 4cbe970..de995fa 100644
--- a/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h
+++ b/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h
@@ -60,6 +60,8 @@ struct CIChipSettings
 UINT_32 isIceland : 1;
 UINT_32 isTonga   : 1;
 UINT_32 isFiji: 1;
+UINT_32 isPolaris10   : 1;
+UINT_32 isPolaris11   : 1;
 // VI fusion (Carrizo)
 UINT_32 isCarrizo : 1;
 };
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_id.h 
b/src/gallium/winsys/amdgpu/drm/amdgpu_id.h
index 90fe0cd..40b835c 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_id.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_id.h
@@ -138,6 +138,10 @@ enum {
 
VI_FIJI_P_A0  = 60,
 
+   VI_POLARIS10_P_A0 = 80,
+
+   VI_POLARIS11_M_A0 = 90,
+
VI_UNKNOWN= 0xFF
 };
 
@@ -147,7 +151,11 @@ enum {
 #define ASICREV_IS_TONGA_P(eChipRev)   \
((eChipRev >= VI_TONGA_P_A0) && (eChipRev < VI_FIJI_P_A0))
 #define ASICREV_IS_FIJI_P(eChipRev)\
-   (eChipRev >= VI_FIJI_P_A0)
+   ((eChipRev >= VI_FIJI_P_A0)  && (eChipRev < VI_POLARIS10_P_A0))
+#define ASICREV_IS_POLARIS10_P(eChipRev)\
+   ((eChipRev >= VI_POLARIS10_P_A0) && (eChipRev < VI_POLARIS11_M_A0))
+#define ASICREV_IS_POLARIS11_M(eChipRev)   \
+   (eChipRev >= VI_POLARIS11_M_A0)
 
 /* CZ specific rev IDs */
 enum {

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Mesa (vulkan): anv: Add genxml register support

[Jordan Justen]

Module: Mesa
Branch: vulkan
Commit: d353ba8f5fee23e9d9c8165b6cbfaba33e19ace6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d353ba8f5fee23e9d9c8165b6cbfaba33e19ace6

Author: Jordan Justen 
Date:   Wed Mar 23 23:24:25 2016 -0700

anv: Add genxml register support

Signed-off-by: Jordan Justen 

---

 src/intel/vulkan/anv_private.h | 9 +
 1 file changed, 9 insertions(+)

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 94a13d7..77f453a 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -813,6 +813,15 @@ __gen_combine_address(struct anv_batch *batch, void 
*location,
 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
 #define __anv_cmd_header(cmd) cmd ## _header
 #define __anv_cmd_pack(cmd) cmd ## _pack
+#define __anv_reg_num(reg) reg ## _num
+
+#define anv_pack_struct(dst, struc, ...) do {  \
+  struct struc __template = {  \
+ __VA_ARGS__   \
+  };   \
+  __anv_cmd_pack(struc)(NULL, dst, &__template);   \
+  VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
+   } while (0)
 
 #define anv_batch_emit(batch, cmd, ...) do {   \
   void *__dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd));   \

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Mesa (vulkan): anv: Use genxml register support for L3 Cache config

[Jordan Justen]

Module: Mesa
Branch: vulkan
Commit: 8f3c23667433aacf5ad65a699c7ce082f3d6e416
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f3c23667433aacf5ad65a699c7ce082f3d6e416

Author: Jordan Justen 
Date:   Thu Mar 24 13:05:04 2016 -0700

anv: Use genxml register support for L3 Cache config

The programming of the L3 Cache registers should match the previous
manually packed LRI values.

Signed-off-by: Jordan Justen 

---

 src/intel/vulkan/gen7_cmd_buffer.c | 53 +++---
 src/intel/vulkan/gen8_cmd_buffer.c | 33 
 2 files changed, 48 insertions(+), 38 deletions(-)

diff --git a/src/intel/vulkan/gen7_cmd_buffer.c 
b/src/intel/vulkan/gen7_cmd_buffer.c
index dbf05d0..04c1d3b 100644
--- a/src/intel/vulkan/gen7_cmd_buffer.c
+++ b/src/intel/vulkan/gen7_cmd_buffer.c
@@ -294,17 +294,10 @@ flush_compute_descriptor_set(struct anv_cmd_buffer 
*cmd_buffer)
return VK_SUCCESS;
 }
 
-static void
-emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
-{
-   anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM),
-  .RegisterOffset = reg,
-  .DataDWord = imm);
-}
-
-#define GEN7_L3SQCREG1 0xb010
-#define GEN7_L3CNTLREG20xb020
-#define GEN7_L3CNTLREG30xb024
+#define emit_lri(batch, reg, imm)   \
+   anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM),\
+  .RegisterOffset = __anv_reg_num(reg), \
+  .DataDWord = imm)
 
 void
 genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, bool enable_slm)
@@ -315,12 +308,19 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer 
*cmd_buffer, bool enable_slm)
 * - src/mesa/drivers/dri/i965/gen7_l3_state.c
 */
 
-   uint32_t l3c2_val = enable_slm ?
-  /* All = 0 ways; URB = 16 ways; DC and RO = 16; SLM = 1 */
-  /*0x02040021*/0x01a1 :
-  /* All = 0 ways; URB = 32 ways; DC = 0; RO = 32; SLM = 0 */
-  /*0x04080040*/0x0230;
-   bool changed = cmd_buffer->state.current_l3_config != l3c2_val;
+   uint32_t l3cr2_slm, l3cr2_noslm;
+   anv_pack_struct(_noslm, GENX(L3CNTLREG2),
+   .URBAllocation = 24,
+   .ROAllocation = 0,
+   .DCAllocation = 16);
+   anv_pack_struct(_slm, GENX(L3CNTLREG2),
+   .SLMEnable = 1,
+   .URBAllocation = 16,
+   .URBLowBandwidth = 1,
+   .ROAllocation = 0,
+   .DCAllocation = 8);
+   const uint32_t l3cr2_val = enable_slm ? l3cr2_slm : l3cr2_noslm;
+   bool changed = cmd_buffer->state.current_l3_config != l3cr2_val;
 
if (changed) {
   /* According to the hardware docs, the L3 partitioning can only be 
changed
@@ -346,10 +346,21 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer 
*cmd_buffer, bool enable_slm)
  .CommandStreamerStallEnable = true);
 
   anv_finishme("write GEN7_L3SQCREG1");
-  emit_lri(_buffer->batch, GEN7_L3CNTLREG2, l3c2_val);
-  emit_lri(_buffer->batch, GEN7_L3CNTLREG3,
-   enable_slm ? 0x00040810 : 0x00040410);
-  cmd_buffer->state.current_l3_config = l3c2_val;
+  emit_lri(_buffer->batch, GENX(L3CNTLREG2), l3cr2_val);
+
+  uint32_t l3cr3_slm, l3cr3_noslm;
+  anv_pack_struct(_noslm, GENX(L3CNTLREG3),
+  .ISAllocation = 8,
+  .CAllocation = 4,
+  .TAllocation = 8);
+  anv_pack_struct(_slm, GENX(L3CNTLREG3),
+  .ISAllocation = 8,
+  .CAllocation = 8,
+  .TAllocation = 8);
+  const uint32_t l3cr3_val = enable_slm ? l3cr3_slm : l3cr3_noslm;
+  emit_lri(_buffer->batch, GENX(L3CNTLREG3), l3cr3_val);
+
+  cmd_buffer->state.current_l3_config = l3cr2_val;
}
 }
 
diff --git a/src/intel/vulkan/gen8_cmd_buffer.c 
b/src/intel/vulkan/gen8_cmd_buffer.c
index 87b5e34..3fb5c27 100644
--- a/src/intel/vulkan/gen8_cmd_buffer.c
+++ b/src/intel/vulkan/gen8_cmd_buffer.c
@@ -108,15 +108,10 @@ gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer 
*cmd_buffer)
 }
 #endif
 
-static void
-emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
-{
-   anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM),
-  .RegisterOffset = reg,
-  .DataDWord = imm);
-}
-
-#define GEN8_L3CNTLREG  0x7034
+#define emit_lri(batch, reg, imm)   \
+   anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM),\
+  .RegisterOffset = __anv_reg_num(reg), \
+  .DataDWord = imm)
 
 void
 genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, bool enable_slm)
@@ -127,12 +122,16 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer 
*cmd_buffer, bool enable_slm)
 * - src/mesa/drivers/dri/i965/gen7_l3_state.c
 */
 
-   uint32_t val = enable_slm ?
-  /* All = 48 ways; URB = 16 

Mesa (vulkan): genxml: Add register support

[Jordan Justen]

Module: Mesa
Branch: vulkan
Commit: b332013a56186d04d7b05b232a8ba021e95c44ba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b332013a56186d04d7b05b232a8ba021e95c44ba

Author: Jordan Justen 
Date:   Wed Mar 23 23:24:25 2016 -0700

genxml: Add register support

Signed-off-by: Jordan Justen 

---

 src/intel/genxml/gen_pack_header.py | 62 +
 1 file changed, 43 insertions(+), 19 deletions(-)

diff --git a/src/intel/genxml/gen_pack_header.py 
b/src/intel/genxml/gen_pack_header.py
index 5bc18c7..9ef7122 100755
--- a/src/intel/genxml/gen_pack_header.py
+++ b/src/intel/genxml/gen_pack_header.py
@@ -202,6 +202,13 @@ def safe_name(name):
 
 return name
 
+def num_from_str(num_str):
+if num_str.lower().startswith('0x'):
+return int(num_str, base=16)
+else:
+assert(not num_str.startswith('0') and 'octals numbers not allowed')
+return int(num_str)
+
 class Field:
 ufixed_pattern = re.compile("u(\d+)\.(\d+)")
 sfixed_pattern = re.compile("s(\d+)\.(\d+)")
@@ -472,25 +479,24 @@ class Parser:
 
 self.instruction = None
 self.structs = {}
+self.registers = {}
 
 def start_element(self, name, attrs):
 if name == "genxml":
 self.platform = attrs["name"]
 self.gen = attrs["gen"].replace('.', '')
 print(pack_header % {'license': license, 'platform': 
self.platform})
-elif name == "instruction":
-self.instruction = safe_name(attrs["name"])
-self.length_bias = int(attrs["bias"])
-if "length" in attrs:
-self.length = int(attrs["length"])
-size = self.length * 32
-else:
-self.length = None
-size = 0
-self.group = Group(self, None, 0, 1, size)
-elif name == "struct":
-self.struct = safe_name(attrs["name"])
-self.structs[attrs["name"]] = 1
+elif name in ("instruction", "struct", "register"):
+if name == "instruction":
+self.instruction = safe_name(attrs["name"])
+self.length_bias = int(attrs["bias"])
+elif name == "struct":
+self.struct = safe_name(attrs["name"])
+self.structs[attrs["name"]] = 1
+elif name == "register":
+self.register = safe_name(attrs["name"])
+self.reg_num = num_from_str(attrs["num"])
+self.registers[attrs["name"]] = 1
 if "length" in attrs:
 self.length = int(attrs["length"])
 size = self.length * 32
@@ -522,10 +528,15 @@ class Parser:
 self.emit_instruction()
 self.instruction = None
 self.group = None
-elif name  == "struct":
+elif name == "struct":
 self.emit_struct()
 self.struct = None
 self.group = None
+elif name == "register":
+self.emit_register()
+self.register = None
+self.reg_num = None
+self.group = None
 elif name == "group":
 self.group = self.group.parent
 elif name  == "field":
@@ -560,9 +571,9 @@ class Parser:
 def emit_instruction(self):
 name = self.instruction
 if not self.length == None:
-print('#define %-33s %4d' %
+print('#define %-33s %6d' %
   (self.gen_prefix(name + "_length"), self.length))
-print('#define %-33s %4d' %
+print('#define %-33s %6d' %
   (self.gen_prefix(name + "_length_bias"), self.length_bias))
 
 default_fields = []
@@ -571,7 +582,7 @@ class Parser:
 continue
 if field.default == None:
 continue
-default_fields.append("   .%-35s = %4d" % (field.name, 
field.default))
+default_fields.append("   .%-35s = %6d" % (field.name, 
field.default))
 
 if default_fields:
 print('#define %-40s\\' % (self.gen_prefix(name + '_header')))
@@ -582,10 +593,23 @@ class Parser:
 
 self.emit_pack_function(self.instruction, self.group)
 
+def emit_register(self):
+name = self.register
+if not self.reg_num == None:
+print('#define %-33s 0x%04x' %
+  (self.gen_prefix(name + "_num"), self.reg_num))
+
+if not self.length == None:
+print('#define %-33s %6d' %
+  (self.gen_prefix(name + "_length"), self.length))
+
+self.emit_template_struct(self.register, self.group)
+self.emit_pack_function(self.register, self.group)
+
 def emit_struct(self):
 name = self.struct
 if not self.length == None:
-print('#define %-33s %4d' %
+print('#define %-33s %6d' %
   (self.gen_prefix(name + "_length"), self.length))
 
 

Mesa (vulkan): genxml: Add L3 Cache Control register definitions

[Jordan Justen]

Module: Mesa
Branch: vulkan
Commit: 7a03fb9ccb3f8a94ec697bc6ebed8c5f859c8b8e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a03fb9ccb3f8a94ec697bc6ebed8c5f859c8b8e

Author: Jordan Justen 
Date:   Thu Mar 24 00:29:50 2016 -0700

genxml: Add L3 Cache Control register definitions

Based on intel_reg.h (5912da45a69923afa1b7f2eb5bb371d848813c41)

Signed-off-by: Jordan Justen 

---

 src/intel/genxml/gen7.xml  | 27 +++
 src/intel/genxml/gen75.xml | 26 ++
 src/intel/genxml/gen8.xml  |  8 
 src/intel/genxml/gen9.xml  |  8 
 4 files changed, 69 insertions(+)

diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 268ca3d..960df5e 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -2508,4 +2508,31 @@
 
   
 
+  
+
+
+
+
+  
+
+  
+
+
+
+
+
+
+
+
+  
+
+  
+
+
+
+
+
+
+  
+
 
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 94bb64e..26c1f9e 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2906,4 +2906,30 @@
 
   
 
+  
+
+
+
+
+  
+
+  
+
+
+
+
+
+
+
+  
+
+  
+
+
+
+
+
+
+  
+
 
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 96eda70..694e691 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -3163,4 +3163,12 @@
 
   
 
+  
+
+
+
+
+
+  
+
 
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 79d3006..bc2639a 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -3467,4 +3467,12 @@
 
   
 
+  
+
+
+
+
+
+  
+
 

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