Mesa (master): dri: add missing 16bits formats mapping
Module: Mesa
Branch: master
Commit: b28a2510cc49711803b9ebcdc315c5011e9a282e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b28a2510cc49711803b9ebcdc315c5011e9a282e
Author: Lionel Landwerlin
Date: Wed Jun 6 12:57:18 2018 +0100
dri: add missing 16bits formats mapping
i965 advertises the 16-bit R and RG formats through
eglQueryDmaBufFormatsEXT but falls over when a client tries to use or
asks more information about such a format because
driImageFormatToGLFormat returns MESA_FORMAT_NONE.
Found by Eero Tamminen.
v2: Add G16R16 formats (Lionel)
v3: Fix G16R16 mapping to mesa format (Jason)
Signed-off-by: Lionel Landwerlin
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106642
Reviewed-by: Plamena Manolova (v2)
Reviewed-by: Jason Ekstrand
---
src/mesa/drivers/dri/common/dri_util.c | 16
1 file changed, 16 insertions(+)
diff --git a/src/mesa/drivers/dri/common/dri_util.c
b/src/mesa/drivers/dri/common/dri_util.c
index a591dfcd7d..d257cb644c 100644
--- a/src/mesa/drivers/dri/common/dri_util.c
+++ b/src/mesa/drivers/dri/common/dri_util.c
@@ -936,6 +936,22 @@ static const struct {
.image_format = __DRI_IMAGE_FORMAT_SARGB8,
.mesa_format =MESA_FORMAT_B8G8R8A8_SRGB,
},
+ {
+ .image_format = __DRI_IMAGE_FORMAT_R16,
+ .mesa_format =MESA_FORMAT_R_UNORM16,
+ },
+ {
+ .image_format = __DRI_IMAGE_FORMAT_R16,
+ .mesa_format =MESA_FORMAT_L_UNORM16,
+ },
+ {
+ .image_format = __DRI_IMAGE_FORMAT_GR1616,
+ .mesa_format =MESA_FORMAT_R16G16_UNORM,
+ },
+ {
+ .image_format = __DRI_IMAGE_FORMAT_GR1616,
+ .mesa_format =MESA_FORMAT_L16A16_UNORM,
+ },
};
uint32_t
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv: intel: add softpin flag on imported BOs
Module: Mesa
Branch: master
Commit: 9aedee64acefd707aae62991f03ed43cb49da5d9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9aedee64acefd707aae62991f03ed43cb49da5d9
Author: Lionel Landwerlin
Date: Mon Jun 4 09:54:29 2018 +0100
anv: intel: add softpin flag on imported BOs
Looks like we forgot to update this bit of the driver for softpin.
Fixes: 4affeba1e9eb42 ("anv: Soft-pin everything else")
Signed-off-by: Lionel Landwerlin
Reviewed-by: Tapani Pälli
Reviewed-by: Jason Ekstrand
---
src/intel/vulkan/anv_intel.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/vulkan/anv_intel.c b/src/intel/vulkan/anv_intel.c
index 431cef5c6a..06db5787a9 100644
--- a/src/intel/vulkan/anv_intel.c
+++ b/src/intel/vulkan/anv_intel.c
@@ -76,6 +76,8 @@ VkResult anv_CreateDmaBufImageINTEL(
uint64_t bo_flags = 0;
if (device->instance->physicalDevice.supports_48bit_addresses)
bo_flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ if (device->instance->physicalDevice.use_softpin)
+ bo_flags |= EXEC_OBJECT_PINNED;
result = anv_bo_cache_import(device, >bo_cache,
pCreateInfo->fd, bo_flags, >bo);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: require pixel scoreboard stall prior to ISP disable
Module: Mesa
Branch: master
Commit: f536097f67521180dafd270b28ac9a852af9c141
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f536097f67521180dafd270b28ac9a852af9c141
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue May 1 12:32:45 2018 +0100
i965: require pixel scoreboard stall prior to ISP disable
Invalidating the indirect state pointers might affect a previously
scheduled & still running 3DPRIMITIVE (causing page fault). So stall
on pixel scoreboard before that.
v2: Fix compile issue :(
v3: Stall on pixel scoreboard
v4: Drop the post sync operation (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
Fixes: ca19ee33d7d39 ("i965/gen10: Ignore push constant packets during context
restore.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106243
---
src/mesa/drivers/dri/i965/brw_pipe_control.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 02278be6d6..879bfb660e 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -349,14 +349,21 @@ gen7_emit_vs_workaround_flush(struct brw_context *brw)
* context restore, so the mentioned hang doesn't happen. However,
* software must program push constant commands for all stages prior to
* rendering anything, so we flag them as dirty.
+ *
+ * Finally, we also make sure to stall at pixel scoreboard to make sure the
+ * constants have been loaded into the EUs prior to disable the push constants
+ * so that it doesn't hang a previous 3DPRIMITIVE.
*/
void
gen10_emit_isp_disable(struct brw_context *brw)
{
brw_emit_pipe_control(brw,
- PIPE_CONTROL_ISP_DIS |
+ PIPE_CONTROL_STALL_AT_SCOREBOARD |
PIPE_CONTROL_CS_STALL,
NULL, 0, 0);
+ brw_emit_pipe_control(brw,
+ PIPE_CONTROL_ISP_DIS,
+ NULL, 0, 0);
brw->vs.base.push_constants_dirty = true;
brw->tcs.base.push_constants_dirty = true;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv: emit pixel scoreboard stall before ISP disable
Module: Mesa
Branch: master
Commit: 766d801ca32118a722fb2e58a48ee9a96897d3b7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=766d801ca32118a722fb2e58a48ee9a96897d3b7
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue May 8 17:25:55 2018 +0100
anv: emit pixel scoreboard stall before ISP disable
We want to make sure that all indirect state data has been loaded into
the EUs before disable the pointers.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
Fixes: 78c125af3904c ("anv/gen10: Ignore push constant packets during context
restore.")
---
src/intel/vulkan/genX_cmd_buffer.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 2882cf3650..526e18af10 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1420,14 +1420,21 @@ genX(BeginCommandBuffer)(
* context restore, so the mentioned hang doesn't happen. However,
* software must program push constant commands for all stages prior to
* rendering anything. So we flag them dirty in BeginCommandBuffer.
+ *
+ * Finally, we also make sure to stall at pixel scoreboard to make sure the
+ * constants have been loaded into the EUs prior to disable the push constants
+ * so that it doesn't hang a previous 3DPRIMITIVE.
*/
static void
emit_isp_disable(struct anv_cmd_buffer *cmd_buffer)
{
anv_batch_emit(_buffer->batch, GENX(PIPE_CONTROL), pc) {
- pc.IndirectStatePointersDisable = true;
+ pc.StallAtPixelScoreboard = true;
pc.CommandStreamerStallEnable = true;
}
+ anv_batch_emit(_buffer->batch, GENX(PIPE_CONTROL), pc) {
+ pc.IndirectStatePointersDisable = true;
+ }
}
VkResult
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: silence unused variable
Module: Mesa
Branch: master
Commit: 3853f1c6f4b97edde22c767a80c137da6e39904a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3853f1c6f4b97edde22c767a80c137da6e39904a
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed May 9 16:40:37 2018 +0100
i965: silence unused variable
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Fixes: 2dc29e095f9da ("i965: Don't leak blorp on Gen4-5.")
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.olive...@intel.com>
---
src/mesa/drivers/dri/i965/brw_context.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index ec3fe3be40..bd1e20845f 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1098,7 +1098,6 @@ intelDestroyContext(__DRIcontext * driContextPriv)
struct brw_context *brw =
(struct brw_context *) driContextPriv->driverPrivate;
struct gl_context *ctx = >ctx;
- const struct gen_device_info *devinfo = >screen->devinfo;
_mesa_meta_free(>ctx);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: devinfo: silence coverity warning
Module: Mesa Branch: master Commit: 11d36c373adcb62016dce9a250120299cfb6e7d8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=11d36c373adcb62016dce9a250120299cfb6e7d8 Author: Lionel Landwerlin <lionel.g.landwer...@intel.com> Date: Wed May 9 15:08:03 2018 +0100 intel: devinfo: silence coverity warning It's just not possible to have a device with no subslices. CID: 1433511 Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/intel/dev/gen_device_info.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c index aa72d96e17..653cece6d7 100644 --- a/src/intel/dev/gen_device_info.c +++ b/src/intel/dev/gen_device_info.c @@ -1034,6 +1034,7 @@ gen_device_info_update_from_topology(struct gen_device_info *devinfo, } n_subslices += devinfo->num_subslices[s]; } + assert(n_subslices > 0); uint32_t eu_mask_len = topology->eu_stride * topology->max_subslices * topology->max_slices; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: devinfo: fix assertion on devices with odd number of EUs
Module: Mesa
Branch: master
Commit: 3cdf1bf97db19b94577b49079cbbc521157d4e03
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3cdf1bf97db19b94577b49079cbbc521157d4e03
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Mon Apr 23 17:52:37 2018 +0100
intel: devinfo: fix assertion on devices with odd number of EUs
I forgot to change the assert in the second helper function in a
previous change.
This hit the assert() on a Broadwell platform with 1 slice, 3
subslices but all EUs disabled in subslice 1 & 2.
Fixes: c1900f5b0fb ("intel: devinfo: add helper functions to fill fusing masks
values")
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/intel/dev/gen_device_info.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
index dfeab6e606..aa72d96e17 100644
--- a/src/intel/dev/gen_device_info.c
+++ b/src/intel/dev/gen_device_info.c
@@ -1044,11 +1044,7 @@ gen_device_info_update_from_topology(struct
gen_device_info *devinfo,
for (int b = 0; b < eu_mask_len; b++)
n_eus += __builtin_popcount(devinfo->eu_masks[b]);
- /* We expect the total number of EUs to be uniformly distributed throughout
-* the subslices.
-*/
- assert(n_subslices && (n_eus % n_subslices) == 0);
- devinfo->num_eu_per_subslice = n_eus / n_subslices;
+ devinfo->num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
}
bool
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel/genxml: recognize 0x, 0o and 0b when setting default value
Module: Mesa Branch: master Commit: 9d1ff2261ccec49994c8162c20969b693b29639a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d1ff2261ccec49994c8162c20969b693b29639a Author: Caio Marcelo de Oliveira Filho <caio.olive...@intel.com> Date: Wed May 2 14:48:57 2018 -0700 intel/genxml: recognize 0x, 0o and 0b when setting default value Remove the need of converting values that are documented in hexadecimal. This patch would allow writing instead of Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> --- src/intel/genxml/gen_pack_header.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/genxml/gen_pack_header.py b/src/intel/genxml/gen_pack_header.py index 8989f625d3..6a4c8033a7 100644 --- a/src/intel/genxml/gen_pack_header.py +++ b/src/intel/genxml/gen_pack_header.py @@ -241,7 +241,8 @@ class Field(object): self.prefix = None if "default" in attrs: -self.default = int(attrs["default"]) +# Base 0 recognizes 0x, 0o, 0b prefixes in addition to decimal ints. +self.default = int(attrs["default"], base=0) else: self.default = None ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: decoder: limit to the number decoded lines from VBO
Module: Mesa
Branch: master
Commit: 000452aebc0d8b53310b981517b6a6aa7c32ccd9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=000452aebc0d8b53310b981517b6a6aa7c32ccd9
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed May 2 18:39:20 2018 +0100
intel: decoder: limit to the number decoded lines from VBO
By default we set no limit, but the debug batch decoder in i965 sets
it to 100.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/intel/common/gen_batch_decoder.c | 22 ++
src/intel/common/gen_decoder.h| 2 ++
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 1 +
3 files changed, 17 insertions(+), 8 deletions(-)
diff --git a/src/intel/common/gen_batch_decoder.c
b/src/intel/common/gen_batch_decoder.c
index c059b19497..3852f32de3 100644
--- a/src/intel/common/gen_batch_decoder.c
+++ b/src/intel/common/gen_batch_decoder.c
@@ -43,6 +43,7 @@ gen_batch_decode_ctx_init(struct gen_batch_decode_ctx *ctx,
ctx->user_data = user_data;
ctx->fp = fp;
ctx->flags = flags;
+ ctx->max_vbo_decoded_lines = -1; /* No limit! */
if (xml_path == NULL)
ctx->spec = gen_spec_load(devinfo);
@@ -165,24 +166,29 @@ static void
ctx_print_buffer(struct gen_batch_decode_ctx *ctx,
struct gen_batch_decode_bo bo,
uint32_t read_length,
- uint32_t pitch)
+ uint32_t pitch,
+ int max_lines)
{
const uint32_t *dw_end = bo.map + MIN2(bo.size, read_length);
- unsigned line_count = 0;
+ int column_count = 0, line_count = -1;
for (const uint32_t *dw = bo.map; dw < dw_end; dw++) {
- if (line_count * 4 == pitch || line_count == 8) {
+ if (column_count * 4 == pitch || column_count == 8) {
fprintf(ctx->fp, "\n");
- line_count = 0;
+ column_count = 0;
+ line_count++;
+
+ if (max_lines >= 0 && line_count >= max_lines)
+break;
}
- fprintf(ctx->fp, line_count == 0 ? " " : " ");
+ fprintf(ctx->fp, column_count == 0 ? " " : " ");
if ((ctx->flags & GEN_BATCH_DECODE_FLOATS) && probably_float(*dw))
fprintf(ctx->fp, " %8.2f", *(float *) dw);
else
fprintf(ctx->fp, " 0x%08x", *dw);
- line_count++;
+ column_count++;
}
fprintf(ctx->fp, "\n");
}
@@ -387,7 +393,7 @@ handle_3dstate_vertex_buffers(struct gen_batch_decode_ctx
*ctx,
if (vb.map == 0 || vb_size == 0)
continue;
- ctx_print_buffer(ctx, vb, vb_size, pitch);
+ ctx_print_buffer(ctx, vb, vb_size, pitch, ctx->max_vbo_decoded_lines);
vb.map = NULL;
vb_size = 0;
@@ -576,7 +582,7 @@ decode_3dstate_constant(struct gen_batch_decode_ctx *ctx,
const uint32_t *p)
unsigned size = read_length[i] * 32;
fprintf(ctx->fp, "constant buffer %d, size %u\n", i, size);
- ctx_print_buffer(ctx, buffer[i], size, 0);
+ ctx_print_buffer(ctx, buffer[i], size, 0, -1);
}
}
}
diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
index 37f6c3ee98..f2207ddf88 100644
--- a/src/intel/common/gen_decoder.h
+++ b/src/intel/common/gen_decoder.h
@@ -220,6 +220,8 @@ struct gen_batch_decode_ctx {
struct gen_batch_decode_bo surface_base;
struct gen_batch_decode_bo dynamic_base;
struct gen_batch_decode_bo instruction_base;
+
+ int max_vbo_decoded_lines;
};
void gen_batch_decode_ctx_init(struct gen_batch_decode_ctx *ctx,
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index b3e4bdc981..bac6e6dae8 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -166,6 +166,7 @@ intel_batchbuffer_init(struct brw_context *brw)
gen_batch_decode_ctx_init(>decoder, devinfo, stderr,
decode_flags, NULL, decode_get_bo,
decode_get_state_size, brw);
+ batch->decoder.max_vbo_decoded_lines = 100;
}
batch->use_batch_first =
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: aubinator: add an option to limit the number of decoded VBO lines
Module: Mesa
Branch: master
Commit: 336decd67e03a4b47baffd2c699b73be8ddb1046
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=336decd67e03a4b47baffd2c699b73be8ddb1046
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed May 2 18:40:28 2018 +0100
intel: aubinator: add an option to limit the number of decoded VBO lines
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/intel/tools/aubinator.c | 39 +++
1 file changed, 23 insertions(+), 16 deletions(-)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index bc263dbf84..3120e82b22 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -58,6 +58,7 @@
static bool option_full_decode = true;
static bool option_print_offsets = true;
+static int max_vbo_lines = -1;
static enum { COLOR_AUTO, COLOR_ALWAYS, COLOR_NEVER } option_color;
/* state */
@@ -179,6 +180,7 @@ aubinator_init(uint16_t aub_pci_id, const char *app_name)
gen_batch_decode_ctx_init(_ctx, , outfile, batch_flags,
xml_path, get_gen_batch_bo, NULL, NULL);
+ batch_ctx.max_vbo_decoded_lines = max_vbo_lines;
char *color = GREEN_HEADER, *reset_color = NORMAL;
if (option_color == COLOR_NEVER)
@@ -547,14 +549,15 @@ print_help(const char *progname, FILE *file)
"Usage: %s [OPTION]... [FILE]\n"
"Decode aub file contents from either FILE or the standard
input.\n\n"
"A valid --gen option must be provided.\n\n"
- " --help display this help and exit\n"
- " --gen=platform decode for given platform (3 letter platform
name)\n"
- " --headers decode only command headers\n"
- " --color[=WHEN] colorize the output; WHEN can be 'auto'
(default\n"
- "if omitted), 'always', or 'never'\n"
- " --no-pager don't launch pager\n"
- " --no-offsetsdon't print instruction offsets\n"
- " --xml=DIR load hardware xml description from directory
DIR\n",
+ " --help display this help and exit\n"
+ " --gen=platform decode for given platform (3 letter
platform name)\n"
+ " --headers decode only command headers\n"
+ " --color[=WHEN] colorize the output; WHEN can be 'auto'
(default\n"
+ " if omitted), 'always', or 'never'\n"
+ " --max-vbo-lines=N limit the number of decoded VBO lines\n"
+ " --no-pager don't launch pager\n"
+ " --no-offsets don't print instruction offsets\n"
+ " --xml=DIR load hardware xml description from
directory DIR\n",
progname);
}
@@ -564,14 +567,15 @@ int main(int argc, char *argv[])
int c, i;
bool help = false, pager = true;
const struct option aubinator_opts[] = {
- { "help", no_argument, (int *) , true },
- { "no-pager", no_argument, (int *) ,false
},
- { "no-offsets", no_argument, (int *) _print_offsets, false
},
- { "gen",required_argument, NULL, 'g' },
- { "headers",no_argument, (int *) _full_decode, false
},
- { "color", required_argument, NULL, 'c' },
- { "xml",required_argument, NULL, 'x' },
- { NULL, 0, NULL, 0 }
+ { "help", no_argument, (int *) ,
true },
+ { "no-pager", no_argument, (int *) ,
false },
+ { "no-offsets",no_argument, (int *) _print_offsets,
false },
+ { "gen", required_argument, NULL, 'g'
},
+ { "headers", no_argument, (int *) _full_decode,
false },
+ { "color", required_argument, NULL, 'c'
},
+ { "xml", required_argument, NULL, 'x'
},
+ { "max-vbo-lines", required_argument, NULL, 'v'
},
+ { NULL,0, NULL, 0 }
};
outfile = stdout;
@@ -605,6 +609,9 @@ int main(int argc, char *argv[])
case 'x':
xml_path = strdup(optarg);
break;
+ case 'v':
+ max_vbo_lines = atoi(optarg);
+ break;
default:
break;
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: fix aubinator include
Module: Mesa
Branch: master
Commit: cf1d58787909757bb2d137fd8a53ef00e2cd6578
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cf1d58787909757bb2d137fd8a53ef00e2cd6578
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed May 2 17:51:03 2018 +0100
intel: fix aubinator include
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Fixes: 7c22c150c40b3 ("intel: Move batch decoder/disassembler from tools/ to
common/")
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/intel/tools/aubinator.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index ab053c66b3..bc263dbf84 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -40,8 +40,8 @@
#include "util/macros.h"
#include "common/gen_decoder.h"
+#include "common/gen_disasm.h"
#include "intel_aub.h"
-#include "gen_disasm.h"
/* Below is the only command missing from intel_aub.h in libdrm
* So, reuse intel_aub.h from libdrm and #define the
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: decoder: identify groups with fixed length
Module: Mesa
Branch: master
Commit: 4f128f7850e64829b8b1399ef0bdfd1eec7f4504
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f128f7850e64829b8b1399ef0bdfd1eec7f4504
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue May 1 22:14:12 2018 +0100
intel: decoder: identify groups with fixed length
& elements always have fixed length. The
get_length() method implies that we're dealing with an instruction in
which the length is encoded into the variable data but the field
iterator uses it without checking what kind of gen_group it is dealing
with.
Let's make get_length() report the correct length regardless of the
gen_group (register, struct or instruction).
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/intel/common/gen_decoder.c | 18 --
src/intel/common/gen_decoder.h | 1 +
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 7c462a0be4..93fa4864ee 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -151,7 +151,8 @@ static struct gen_group *
create_group(struct parser_context *ctx,
const char *name,
const char **atts,
- struct gen_group *parent)
+ struct gen_group *parent,
+ bool fixed_length)
{
struct gen_group *group;
@@ -161,6 +162,7 @@ create_group(struct parser_context *ctx,
group->spec = ctx->spec;
group->variable = false;
+ group->fixed_length = fixed_length;
for (int i = 0; atts[i]; i += 2) {
char *p;
@@ -370,18 +372,19 @@ start_element(void *data, const char *element_name, const
char **atts)
minor = 0;
ctx->spec->gen = gen_make_gen(major, minor);
- } else if (strcmp(element_name, "instruction") == 0 ||
- strcmp(element_name, "struct") == 0) {
- ctx->group = create_group(ctx, name, atts, NULL);
+ } else if (strcmp(element_name, "instruction") == 0) {
+ ctx->group = create_group(ctx, name, atts, NULL, false);
+ } else if (strcmp(element_name, "struct") == 0) {
+ ctx->group = create_group(ctx, name, atts, NULL, true);
} else if (strcmp(element_name, "register") == 0) {
- ctx->group = create_group(ctx, name, atts, NULL);
+ ctx->group = create_group(ctx, name, atts, NULL, true);
get_register_offset(atts, >group->register_offset);
} else if (strcmp(element_name, "group") == 0) {
struct gen_group *previous_group = ctx->group;
while (previous_group->next)
previous_group = previous_group->next;
- struct gen_group *group = create_group(ctx, "", atts, ctx->group);
+ struct gen_group *group = create_group(ctx, "", atts, ctx->group, false);
previous_group->next = group;
ctx->group = group;
} else if (strcmp(element_name, "field") == 0) {
@@ -713,6 +716,9 @@ gen_group_find_field(struct gen_group *group, const char
*name)
int
gen_group_get_length(struct gen_group *group, const uint32_t *p)
{
+ if (group && group->fixed_length)
+ return group->dw_length;
+
uint32_t h = p[0];
uint32_t type = field_value(h, 29, 31);
diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
index f28ac7d27a..7d3bedca5b 100644
--- a/src/intel/common/gen_decoder.h
+++ b/src/intel/common/gen_decoder.h
@@ -104,6 +104,7 @@ struct gen_group {
uint32_t group_offset, group_count;
uint32_t group_size;
bool variable;
+ bool fixed_length; /* True for & */
struct gen_group *parent;
struct gen_group *next;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: decoder: fix starting dword of struct fields
Module: Mesa
Branch: master
Commit: acbce2ac57d476e2af90a2892341581b76148c11
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=acbce2ac57d476e2af90a2892341581b76148c11
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed May 2 00:13:39 2018 +0100
intel: decoder: fix starting dword of struct fields
Struct fields might span several dwords, but iter_dword is incremented
up to the last dword of the current field before we print out the
struct's fields. We can't use iter_dword for computing the offset into
the pointer of data to decode.
v2: Fix displayed offset number (Ken)
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/intel/common/gen_decoder.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 93fa4864ee..bb87192d23 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -1062,9 +1062,10 @@ gen_print_group(FILE *outfile, struct gen_group *group,
uint64_t offset,
if (!gen_field_is_header(iter.field)) {
fprintf(outfile, "%s: %s\n", iter.name, iter.value);
if (iter.struct_desc) {
-uint64_t struct_offset = offset + 4 * iter_dword;
+int struct_dword = iter.start_bit / 32;
+uint64_t struct_offset = offset + 4 * struct_dword;
gen_print_group(outfile, iter.struct_desc, struct_offset,
-[iter_dword], iter.start_bit % 32, color);
+[struct_dword], iter.start_bit % 32, color);
}
}
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: decoder: document when fields should be used
Module: Mesa
Branch: master
Commit: 467430ddcc85be34bd79a3709b33e4510e3c9370
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=467430ddcc85be34bd79a3709b33e4510e3c9370
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue May 1 22:18:11 2018 +0100
intel: decoder: document when fields should be used
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/intel/common/gen_decoder.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
index 7d3bedca5b..8324ff9569 100644
--- a/src/intel/common/gen_decoder.h
+++ b/src/intel/common/gen_decoder.h
@@ -103,7 +103,7 @@ struct gen_group {
uint32_t dw_length;
uint32_t group_offset, group_count;
uint32_t group_size;
- bool variable;
+ bool variable; /* specific */
bool fixed_length; /* True for & */
struct gen_group *parent;
@@ -112,8 +112,7 @@ struct gen_group {
uint32_t opcode_mask;
uint32_t opcode;
- /* Register specific */
- uint32_t register_offset;
+ uint32_t register_offset; /* specific */
};
struct gen_value {
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: decoder: make the field iterator use more natural
Module: Mesa
Branch: master
Commit: 3c416a50d8d203115012363b13a4083f1c6de069
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3c416a50d8d203115012363b13a4083f1c6de069
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue May 1 22:12:56 2018 +0100
intel: decoder: make the field iterator use more natural
while (iter_next()) { ... }
instead of
do { ... } while (iter_next());
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/intel/common/gen_decoder.c | 26 ++--
src/intel/tools/gen_batch_decoder.c | 40 ++---
2 files changed, 36 insertions(+), 30 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 1b8123bf39..7c462a0be4 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -981,25 +981,31 @@ gen_field_iterator_init(struct gen_field_iterator *iter,
memset(iter, 0, sizeof(*iter));
iter->group = group;
- if (group->fields)
- iter->field = group->fields;
- else
- iter->field = group->next->fields;
iter->p = p;
iter->p_bit = p_bit;
int length = gen_group_get_length(iter->group, iter->p);
iter->p_end = length > 0 ? [length] : NULL;
iter->print_colors = print_colors;
-
- bool result = iter_decode_field(iter);
- if (length >= 0)
- assert(result);
}
bool
gen_field_iterator_next(struct gen_field_iterator *iter)
{
+ /* Initial condition */
+ if (!iter->field) {
+ if (iter->group->fields)
+ iter->field = iter->group->fields;
+ else
+ iter->field = iter->group->next->fields;
+
+ bool result = iter_decode_field(iter);
+ if (iter->p_end)
+ assert(result);
+
+ return true;
+ }
+
if (!iter_advance_field(iter))
return false;
@@ -1040,7 +1046,7 @@ gen_print_group(FILE *outfile, struct gen_group *group,
uint64_t offset,
int last_dword = -1;
gen_field_iterator_init(, group, p, p_bit, color);
- do {
+ while (gen_field_iterator_next()) {
int iter_dword = iter.end_bit / 32;
if (last_dword != iter_dword) {
for (int i = last_dword + 1; i <= iter_dword; i++)
@@ -1055,5 +1061,5 @@ gen_print_group(FILE *outfile, struct gen_group *group,
uint64_t offset,
[iter_dword], iter.start_bit % 32, color);
}
}
- } while (gen_field_iterator_next());
+ }
}
diff --git a/src/intel/tools/gen_batch_decoder.c
b/src/intel/tools/gen_batch_decoder.c
index c6b908758b..e8d0e11682 100644
--- a/src/intel/tools/gen_batch_decoder.c
+++ b/src/intel/tools/gen_batch_decoder.c
@@ -175,7 +175,7 @@ handle_state_base_address(struct gen_batch_decode_ctx *ctx,
const uint32_t *p)
struct gen_field_iterator iter;
gen_field_iterator_init(, inst, p, 0, false);
- do {
+ while (gen_field_iterator_next()) {
if (strcmp(iter.name, "Surface State Base Address") == 0) {
ctx->surface_base = ctx_get_bo(ctx, iter.raw_value);
} else if (strcmp(iter.name, "Dynamic State Base Address") == 0) {
@@ -183,7 +183,7 @@ handle_state_base_address(struct gen_batch_decode_ctx *ctx,
const uint32_t *p)
} else if (strcmp(iter.name, "Instruction Base Address") == 0) {
ctx->instruction_base = ctx_get_bo(ctx, iter.raw_value);
}
- } while (gen_field_iterator_next());
+ }
}
static void
@@ -272,14 +272,14 @@ handle_media_interface_descriptor_load(struct
gen_batch_decode_ctx *ctx,
gen_field_iterator_init(, inst, p, 0, false);
uint32_t descriptor_offset = 0;
int descriptor_count = 0;
- do {
+ while (gen_field_iterator_next()) {
if (strcmp(iter.name, "Interface Descriptor Data Start Address") == 0) {
descriptor_offset = strtol(iter.value, NULL, 16);
} else if (strcmp(iter.name, "Interface Descriptor Total Length") == 0) {
descriptor_count =
strtol(iter.value, NULL, 16) / (desc->dw_length * 4);
}
- } while (gen_field_iterator_next());
+ }
uint64_t desc_addr = ctx->dynamic_base.addr + descriptor_offset;
const uint32_t *desc_map = ctx->dynamic_base.map + descriptor_offset;
@@ -292,7 +292,7 @@ handle_media_interface_descriptor_load(struct
gen_batch_decode_ctx *ctx,
uint64_t ksp;
uint32_t sampler_offset, sampler_count;
uint32_t binding_table_offset, binding_entry_count;
- do {
+ while (gen_field_iterator_next()) {
if (strcmp(iter.name, "Kernel Start Pointer") == 0) {
ksp = strtoll(iter.value, NULL, 16);
} else if (strcmp(iter.name, "Sampler State Pointer") == 0) {
@@ -304,7 +304,7 @@ handle_media_interface_descriptor_load(struct
gen_batch_
Mesa (master): intel: batch-decoder: iterate VERTEX_BUFFER_STATE fields
Module: Mesa
Branch: master
Commit: ec5df73803f101276973eeb780d1591462e5e0a6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec5df73803f101276973eeb780d1591462e5e0a6
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed May 2 00:17:19 2018 +0100
intel: batch-decoder: iterate VERTEX_BUFFER_STATE fields
The gen_field_iterator only iterates the fields of a given gen_group.
If we want to iterate the fields of another gen_group contained as
field, we need to do it manually.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/intel/tools/gen_batch_decoder.c | 70 +
1 file changed, 39 insertions(+), 31 deletions(-)
diff --git a/src/intel/tools/gen_batch_decoder.c
b/src/intel/tools/gen_batch_decoder.c
index e8d0e11682..a0d6dbd3e5 100644
--- a/src/intel/tools/gen_batch_decoder.c
+++ b/src/intel/tools/gen_batch_decoder.c
@@ -322,6 +322,7 @@ handle_3dstate_vertex_buffers(struct gen_batch_decode_ctx
*ctx,
const uint32_t *p)
{
struct gen_group *inst = gen_spec_find_instruction(ctx->spec, p);
+ struct gen_group *vbs = gen_spec_find_struct(ctx->spec,
"VERTEX_BUFFER_STATE");
struct gen_batch_decode_bo vb = {};
uint32_t vb_size = 0;
@@ -332,43 +333,50 @@ handle_3dstate_vertex_buffers(struct gen_batch_decode_ctx
*ctx,
struct gen_field_iterator iter;
gen_field_iterator_init(, inst, p, 0, false);
while (gen_field_iterator_next()) {
- if (strcmp(iter.name, "Vertex Buffer Index") == 0) {
- index = iter.raw_value;
- } else if (strcmp(iter.name, "Buffer Pitch") == 0) {
- pitch = iter.raw_value;
- } else if (strcmp(iter.name, "Buffer Starting Address") == 0) {
- vb = ctx_get_bo(ctx, iter.raw_value);
- } else if (strcmp(iter.name, "Buffer Size") == 0) {
- vb_size = iter.raw_value;
- ready = true;
- } else if (strcmp(iter.name, "End Address") == 0) {
- if (vb.map && iter.raw_value >= vb.addr)
-vb_size = iter.raw_value - vb.addr;
- else
-vb_size = 0;
- ready = true;
- }
-
- if (!ready)
+ if (iter.struct_desc != vbs)
continue;
- fprintf(ctx->fp, "vertex buffer %d, size %d\n", index, vb_size);
+ struct gen_field_iterator vbs_iter;
+ gen_field_iterator_init(_iter, vbs, [iter.start_bit / 32], 0,
false);
+ while (gen_field_iterator_next(_iter)) {
+ if (strcmp(vbs_iter.name, "Vertex Buffer Index") == 0) {
+index = vbs_iter.raw_value;
+ } else if (strcmp(vbs_iter.name, "Buffer Pitch") == 0) {
+pitch = vbs_iter.raw_value;
+ } else if (strcmp(vbs_iter.name, "Buffer Starting Address") == 0) {
+vb = ctx_get_bo(ctx, vbs_iter.raw_value);
+ } else if (strcmp(vbs_iter.name, "Buffer Size") == 0) {
+vb_size = vbs_iter.raw_value;
+ready = true;
+ } else if (strcmp(vbs_iter.name, "End Address") == 0) {
+if (vb.map && vbs_iter.raw_value >= vb.addr)
+ vb_size = vbs_iter.raw_value - vb.addr;
+else
+ vb_size = 0;
+ready = true;
+ }
- if (vb.map == NULL) {
- fprintf(ctx->fp, " buffer contents unavailable\n");
- continue;
- }
+ if (!ready)
+continue;
- if (vb.map == 0 || vb_size == 0)
- continue;
+ fprintf(ctx->fp, "vertex buffer %d, size %d\n", index, vb_size);
+
+ if (vb.map == NULL) {
+fprintf(ctx->fp, " buffer contents unavailable\n");
+continue;
+ }
+
+ if (vb.map == 0 || vb_size == 0)
+continue;
- ctx_print_buffer(ctx, vb, vb_size, pitch);
+ ctx_print_buffer(ctx, vb, vb_size, pitch);
- vb.map = NULL;
- vb_size = 0;
- index = -1;
- pitch = -1;
- ready = false;
+ vb.map = NULL;
+ vb_size = 0;
+ index = -1;
+ pitch = -1;
+ ready = false;
+ }
}
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: perf: add support for raw queries
Module: Mesa
Branch: master
Commit: 2e3025c817a6694e3a6b093ea0e5e07922271a54
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e3025c817a6694e3a6b093ea0e5e07922271a54
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed Mar 7 14:28:41 2018 +
i965: perf: add support for raw queries
The INTEL_performance_query extension provides a list of queries that
a user can select to monitor a particular workload. Each query reports
different sets of counters (roughly looking at different parts of the
hardware, i.e. caches/fixed functions/etc...).
Each query has an associated configuration that we need to program
into the hardware before using the query. Up to now, we provided
predefined queries. This change allows the user to build its own query
(and associated configuration) externally, and have the i965 driver
use that configuration through a new query named :
Intel_Raw_Hardware_Counters_Set_0_Query
When this query is selected, the i965 driver will report raw counters
deltas (meaning their values need to be interpreted by the user, as
opposed to existing queries that provide human readable values).
This change is also useful for debug purposes for building new
pre-defined queries and verifying the underlying numbers make sense
before writing equations for user readable output.
This change's purpose is also to enable GPA. GPA uses a library called
MDAPI that processes raw counter data. MDAPI expects raw data to have
a certain layout (per generation which is a bit unfortunate...). This
change also embeds the expected data layouts.
v2: Enable raw queries on gen 7->11, v1 had 7->9 (Lionel)
v3: Don't assert on cherryview for gen7... (Ken)
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 +
src/mesa/drivers/dri/i965/brw_context.h| 3 +-
src/mesa/drivers/dri/i965/brw_performance_query.c | 111 --
src/mesa/drivers/dri/i965/brw_performance_query.h | 7 +
.../drivers/dri/i965/brw_performance_query_mdapi.c | 378 +
src/mesa/drivers/dri/i965/meson.build | 1 +
6 files changed, 474 insertions(+), 27 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources
b/src/mesa/drivers/dri/i965/Makefile.sources
index 31ecbe6d30..5e53d874d8 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -37,6 +37,7 @@ i965_FILES = \
brw_pipe_control.h \
brw_performance_query.h \
brw_performance_query.c \
+ brw_performance_query_mdapi.c \
brw_performance_query_metrics.h \
brw_program.c \
brw_program.h \
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index cd76364542..1e6a45eee1 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -681,7 +681,8 @@ struct gen_l3_config;
enum brw_query_kind {
OA_COUNTERS,
- PIPELINE_STATS
+ OA_COUNTERS_RAW,
+ PIPELINE_STATS,
};
struct brw_perf_query_register_prog {
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 9052f6cf19..ece2ff0ab6 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -266,6 +266,44 @@ static bool
brw_is_perf_query_ready(struct gl_context *ctx,
struct gl_perf_query_object *o);
+static uint64_t
+brw_perf_query_get_metric_id(struct brw_context *brw,
+ const struct brw_perf_query_info *query)
+{
+ /* These queries are know not to ever change, their config ID has been
+* loaded upon the first query creation. No need to look them up again.
+*/
+ if (query->kind == OA_COUNTERS)
+ return query->oa_metrics_set_id;
+
+ assert(query->kind == OA_COUNTERS_RAW);
+
+ /* Raw queries can be reprogrammed up by an external application/library.
+* When a raw query is used for the first time it's id is set to a value !=
+* 0. When it stops being used the id returns to 0. No need to reload the
+* ID when it's already loaded.
+*/
+ if (query->oa_metrics_set_id != 0) {
+ DBG("Raw query '%s' guid=%s using cached ID: %"PRIu64"\n",
+ query->name, query->guid, query->oa_metrics_set_id);
+ return query->oa_metrics_set_id;
+ }
+
+ char metric_id_file[280];
+ snprintf(metric_id_file, sizeof(metric_id_file),
+"%s/metrics/%s/id", brw->perfquery.sysfs_dev_dir, query->guid);
+
+ struct brw_perf_query_info *raw_query = (struct brw_perf_query_info *)query;
+ if (!read_file_uint64(metric_id_file, _query->oa_metrics_set_id)) {
+ DBG("Unable to read query guid=%s ID, falling back to test config\n",
quer
Mesa (master): i965: perf: read slice/unslice frequencies from OA reports
Module: Mesa
Branch: master
Commit: c61d445a5a44c7ea44f2bf1f8271270e45fae79c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c61d445a5a44c7ea44f2bf1f8271270e45fae79c
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed Mar 7 16:02:40 2018 +
i965: perf: read slice/unslice frequencies from OA reports
v2: Add comment breaking down where the frequency values come from (Ken)
v3: More documentation (Ken/Lionel)
Adjust clock ratio multiplier to reflect the divider's behavior (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 59 +++
src/mesa/drivers/dri/i965/brw_performance_query.h | 12 +
2 files changed, 71 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 32cf96a333..9052f6cf19 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1342,6 +1342,64 @@ brw_is_perf_query_ready(struct gl_context *ctx,
}
static void
+gen8_read_report_clock_ratios(const uint32_t *report,
+ uint64_t *slice_freq_hz,
+ uint64_t *unslice_freq_hz)
+{
+ /* The lower 16bits of the RPT_ID field of the OA reports contains a
+* snapshot of the bits coming from the RP_FREQ_NORMAL register and is
+* divided this way :
+*
+* RPT_ID[31:25]: RP_FREQ_NORMAL[20:14] (low squashed_slice_clock_frequency)
+* RPT_ID[10:9]: RP_FREQ_NORMAL[22:21] (high
squashed_slice_clock_frequency)
+* RPT_ID[8:0]: RP_FREQ_NORMAL[31:23] (squashed_unslice_clock_frequency)
+*
+* RP_FREQ_NORMAL[31:23]: Software Unslice Ratio Request
+*Multiple of 33.33MHz 2xclk (16 MHz 1xclk)
+*
+* RP_FREQ_NORMAL[22:14]: Software Slice Ratio Request
+*Multiple of 33.33MHz 2xclk (16 MHz 1xclk)
+*/
+
+ uint32_t unslice_freq = report[0] & 0x1ff;
+ uint32_t slice_freq_low = (report[0] >> 25) & 0x7f;
+ uint32_t slice_freq_high = (report[0] >> 9) & 0x3;
+ uint32_t slice_freq = slice_freq_low | (slice_freq_high << 7);
+
+ *slice_freq_hz = slice_freq * 1667ULL;
+ *unslice_freq_hz = unslice_freq * 1667ULL;
+}
+
+static void
+read_slice_unslice_frequencies(struct brw_context *brw,
+ struct brw_perf_query_object *obj)
+{
+ const struct gen_device_info *devinfo = >screen->devinfo;
+ uint32_t *begin_report, *end_report;
+
+ /* Slice/Unslice frequency is only available in the OA reports when the
+* "Disable OA reports due to clock ratio change" field in
+* OA_DEBUG_REGISTER is set to 1. This is how the kernel programs this
+* global register (see drivers/gpu/drm/i915/i915_perf.c)
+*
+* Documentation says this should be available on Gen9+ but experimentation
+* shows that Gen8 reports similar values, so we enable it there too.
+*/
+ if (devinfo->gen < 8)
+ return;
+
+ begin_report = obj->oa.map;
+ end_report = obj->oa.map + MI_RPC_BO_END_OFFSET_BYTES;
+
+ gen8_read_report_clock_ratios(begin_report,
+ >oa.slice_frequency[0],
+ >oa.unslice_frequency[0]);
+ gen8_read_report_clock_ratios(end_report,
+ >oa.slice_frequency[1],
+ >oa.unslice_frequency[1]);
+}
+
+static void
read_gt_frequency(struct brw_context *brw,
struct brw_perf_query_object *obj)
{
@@ -1382,6 +1440,7 @@ get_oa_counter_data(struct brw_context *brw,
if (!obj->oa.results_accumulated) {
read_gt_frequency(brw, obj);
+ read_slice_unslice_frequencies(brw, obj);
accumulate_oa_reports(brw, obj);
assert(obj->oa.results_accumulated);
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.h
b/src/mesa/drivers/dri/i965/brw_performance_query.h
index f8732738b4..a6604fb89f 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.h
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.h
@@ -118,6 +118,18 @@ struct brw_perf_query_object
* Frequency of the GT at begin and end of the query.
*/
uint64_t gt_frequency[2];
+
+ /**
+ * Frequency in the slices of the GT at the begin and end of the
+ * query.
+ */
+ uint64_t slice_frequency[2];
+
+ /**
+ * Frequency in the unslice of the GT at the begin and end of the
+ * query.
+ */
+ uint64_t unslice_frequency[2];
} oa;
struct {
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: perf: snapshot RPSTAT register
Module: Mesa
Branch: master
Commit: 43fcb72d2c288d10261ca51a909beabdee1ee761
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=43fcb72d2c288d10261ca51a909beabdee1ee761
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed Mar 7 10:46:58 2018 +
i965: perf: snapshot RPSTAT register
This register contains the current/previous frequency of the GT, it's
one of the value GPA would like to have as part of their queries.
v2: Don't use this register on baytrail/cherryview (Ken)
Use GET_FIELD() macro (Ken)
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_defines.h | 12 ++
src/mesa/drivers/dri/i965/brw_performance_query.c | 50 +++
src/mesa/drivers/dri/i965/brw_performance_query.h | 5 +++
3 files changed, 67 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 8bf6f68b67..855f1c7d74 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1656,6 +1656,18 @@ enum brw_pixel_shader_coverage_mask_mode {
#define CS_DEBUG_MODE2 0x20d8 /* Gen9+ */
# define CSDBG2_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE (1 << 4)
+#define GEN7_RPSTAT1 0xA01C
+#define GEN7_RPSTAT1_CURR_GT_FREQ_SHIFT 7
+#define GEN7_RPSTAT1_CURR_GT_FREQ_MASKINTEL_MASK(13, 7)
+#define GEN7_RPSTAT1_PREV_GT_FREQ_SHIFT 0
+#define GEN7_RPSTAT1_PREV_GT_FREQ_MASKINTEL_MASK(6, 0)
+
+#define GEN9_RPSTAT0 0xA01C
+#define GEN9_RPSTAT0_CURR_GT_FREQ_SHIFT 23
+#define GEN9_RPSTAT0_CURR_GT_FREQ_MASKINTEL_MASK(31, 23)
+#define GEN9_RPSTAT0_PREV_GT_FREQ_SHIFT 0
+#define GEN9_RPSTAT0_PREV_GT_FREQ_MASKINTEL_MASK(8, 0)
+
#define SLICE_COMMON_ECO_CHICKEN1 0x731c /* Gen9+ */
# define GLK_SCEC_BARRIER_MODE_GPGPU (0 << 7)
# define GLK_SCEC_BARRIER_MODE_3D_HULL (1 << 7)
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 44cac85c6e..32cf96a333 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -216,6 +216,8 @@ brw_perf_query(struct gl_perf_query_object *o)
#define MI_RPC_BO_SIZE 4096
#define MI_RPC_BO_END_OFFSET_BYTES (MI_RPC_BO_SIZE / 2)
+#define MI_FREQ_START_OFFSET_BYTES (3072)
+#define MI_FREQ_END_OFFSET_BYTES(3076)
/**/
@@ -946,6 +948,21 @@ close_perf(struct brw_context *brw)
}
}
+static void
+capture_frequency_stat_register(struct brw_context *brw,
+struct brw_bo *bo,
+uint32_t bo_offset)
+{
+ const struct gen_device_info *devinfo = >screen->devinfo;
+
+ if (devinfo->gen >= 7 && devinfo->gen <= 8 &&
+ !devinfo->is_baytrail && !devinfo->is_cherryview) {
+ brw_store_register_mem32(brw, bo, GEN7_RPSTAT1, bo_offset);
+ } else if (devinfo->gen >= 9) {
+ brw_store_register_mem32(brw, bo, GEN9_RPSTAT0, bo_offset);
+ }
+}
+
/**
* Driver hook for glBeginPerfQueryINTEL().
*/
@@ -1138,6 +1155,8 @@ brw_begin_perf_query(struct gl_context *ctx,
/* Take a starting OA counter snapshot. */
brw->vtbl.emit_mi_report_perf_count(brw, obj->oa.bo, 0,
obj->oa.begin_report_id);
+ capture_frequency_stat_register(brw, obj->oa.bo,
MI_FREQ_START_OFFSET_BYTES);
+
++brw->perfquery.n_active_oa_queries;
/* No already-buffered samples can possibly be associated with this query
@@ -1221,6 +1240,7 @@ brw_end_perf_query(struct gl_context *ctx,
*/
if (!obj->oa.results_accumulated) {
/* Take an ending OA counter snapshot. */
+ capture_frequency_stat_register(brw, obj->oa.bo,
MI_FREQ_END_OFFSET_BYTES);
brw->vtbl.emit_mi_report_perf_count(brw, obj->oa.bo,
MI_RPC_BO_END_OFFSET_BYTES,
obj->oa.begin_report_id + 1);
@@ -1321,6 +1341,35 @@ brw_is_perf_query_ready(struct gl_context *ctx,
return false;
}
+static void
+read_gt_frequency(struct brw_context *brw,
+ struct brw_perf_query_object *obj)
+{
+ const struct gen_device_info *devinfo = >screen->devinfo;
+ uint32_t start = *((uint32_t *)(obj->oa.map + MI_FREQ_START_OFFSET_BYTES)),
+ end = *((uint32_t *)(obj->oa.map + MI_FREQ_END_OFFSET_BYTES));
+
+ switch (devinfo->gen) {
+ case 7:
+ case 8:
+ obj->oa.gt_frequency[0] = GET_FIELD(start, GEN7_RPSTAT1_CURR_GT_FREQ) *
50ULL;
+ obj->oa.gt_frequency[1] = GET_FIELD(e
Mesa (master): i965: perf: extract utility functions
Module: Mesa
Branch: master
Commit: d71b442416be8ddbed93347d6a2f14a1294bec77
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d71b442416be8ddbed93347d6a2f14a1294bec77
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue Mar 6 17:09:21 2018 +
i965: perf: extract utility functions
We would like to reuse a number of the functions and structures in
another file in a future commit.
We also move the previous content of brw_performance_query.h into
brw_performance_query_metrics.h to be included by generated metrics
files.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 +
src/mesa/drivers/dri/i965/brw_oa.py| 2 +-
src/mesa/drivers/dri/i965/brw_performance_query.c | 299 +
src/mesa/drivers/dri/i965/brw_performance_query.h | 186 +++--
.../dri/i965/brw_performance_query_metrics.h | 57
src/mesa/drivers/dri/i965/meson.build | 1 +
6 files changed, 294 insertions(+), 252 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources
b/src/mesa/drivers/dri/i965/Makefile.sources
index 3479ceb9d1..31ecbe6d30 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -37,6 +37,7 @@ i965_FILES = \
brw_pipe_control.h \
brw_performance_query.h \
brw_performance_query.c \
+ brw_performance_query_metrics.h \
brw_program.c \
brw_program.h \
brw_program_binary.c \
diff --git a/src/mesa/drivers/dri/i965/brw_oa.py
b/src/mesa/drivers/dri/i965/brw_oa.py
index 7bf7987b4c..4c70f253d7 100644
--- a/src/mesa/drivers/dri/i965/brw_oa.py
+++ b/src/mesa/drivers/dri/i965/brw_oa.py
@@ -629,7 +629,7 @@ def main():
c(textwrap.dedent("""\
#include "brw_context.h"
-#include "brw_performance_query.h"
+#include "brw_performance_query_metrics.h"
#define MIN(a, b) ((a < b) ? (a) : (b))
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index ef5401a21b..44cac85c6e 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -76,15 +76,6 @@
#define FILE_DEBUG_FLAG DEBUG_PERFMON
-/*
- * The largest OA formats we can use include:
- * For Haswell:
- * 1 timestamp, 45 A counters, 8 B counters and 8 C counters.
- * For Gen8+
- * 1 timestamp, 1 clock, 36 A counters, 8 B counters and 8 C counters
- */
-#define MAX_OA_REPORT_COUNTERS 62
-
#define OAREPORT_REASON_MASK 0x3f
#define OAREPORT_REASON_SHIFT 19
#define OAREPORT_REASON_TIMER (1<<0)
@@ -216,85 +207,6 @@ struct brw_oa_sample_buf {
uint32_t last_timestamp;
};
-/**
- * i965 representation of a performance query object.
- *
- * NB: We want to keep this structure relatively lean considering that
- * applications may expect to allocate enough objects to be able to
- * query around all draw calls in a frame.
- */
-struct brw_perf_query_object
-{
- struct gl_perf_query_object base;
-
- const struct brw_perf_query_info *query;
-
- /* See query->kind to know which state below is in use... */
- union {
- struct {
-
- /**
- * BO containing OA counter snapshots at query Begin/End time.
- */
- struct brw_bo *bo;
-
- /**
- * Address of mapped of @bo
- */
- void *map;
-
- /**
- * The MI_REPORT_PERF_COUNT command lets us specify a unique
- * ID that will be reflected in the resulting OA report
- * that's written by the GPU. This is the ID we're expecting
- * in the begin report and the the end report should be
- * @begin_report_id + 1.
- */
- int begin_report_id;
-
- /**
- * Reference the head of the brw->perfquery.sample_buffers
- * list at the time that the query started (so we only need
- * to look at nodes after this point when looking for samples
- * related to this query)
- *
- * (See struct brw_oa_sample_buf description for more details)
- */
- struct exec_node *samples_head;
-
- /**
- * Storage for the final accumulated OA counters.
- */
- uint64_t accumulator[MAX_OA_REPORT_COUNTERS];
-
- /**
- * Hw ID used by the context on which the query was running.
- */
- uint32_t hw_id;
-
- /**
- * false while in the unaccumulated_elements list, and set to
- * true when the final, end MI_RPC snapshot has been
- * accumulated.
- */
- bool results_accumulated;
-
- /**
- * Number of reports accumulated to produce
Mesa (master): i965: perf: enable GPA query statistics
Module: Mesa
Branch: master
Commit: 2964e16e5158bfba1fa4da05f12d87ab584c2a1a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2964e16e5158bfba1fa4da05f12d87ab584c2a1a
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Fri Feb 9 10:56:42 2018 +
i965: perf: enable GPA query statistics
The combinaison of GPA/MDAPI components expects a particular name &
layout for their pipeline statistics query.
v2: Limit the query GPA/MDAPI statistics to gen7->9 (Lionel)
v3: Add curly braces (Ken)
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 1 +
src/mesa/drivers/dri/i965/brw_performance_query.h | 2 +-
.../drivers/dri/i965/brw_performance_query_mdapi.c | 66 ++
3 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index ece2ff0ab6..77d23133ad 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -2165,6 +2165,7 @@ brw_init_perf_query_info(struct gl_context *ctx)
return brw->perfquery.n_queries;
init_pipeline_statistic_query_registers(brw);
+ brw_perf_query_register_mdapi_statistic_query(brw);
oa_register = get_register_queries_function(devinfo);
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.h
b/src/mesa/drivers/dri/i965/brw_performance_query.h
index 20fdbc0473..66b32c0490 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.h
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.h
@@ -222,6 +222,6 @@ int brw_perf_query_get_mdapi_oa_data(struct brw_context
*brw,
size_t data_size,
uint8_t *data);
void brw_perf_query_register_mdapi_oa_query(struct brw_context *brw);
-
+void brw_perf_query_register_mdapi_statistic_query(struct brw_context *brw);
#endif /* BRW_PERFORMANCE_QUERY_H */
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query_mdapi.c
b/src/mesa/drivers/dri/i965/brw_performance_query_mdapi.c
index f98918ba76..70f69debe9 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query_mdapi.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query_mdapi.c
@@ -21,6 +21,7 @@
* IN THE SOFTWARE.
*/
+#include "brw_defines.h"
#include "brw_performance_query.h"
/**
@@ -99,6 +100,20 @@ struct mdapi_gen9_metrics {
uint32_t Reserved4;
};
+struct mdapi_pipeline_metrics {
+ uint64_t IAVertices;
+ uint64_t IAPrimitives;
+ uint64_t VSInvocations;
+ uint64_t GSInvocations;
+ uint64_t GSPrimitives;
+ uint64_t CInvocations;
+ uint64_t CPrimitives;
+ uint64_t PSInvocations;
+ uint64_t HSInvocations;
+ uint64_t DSInvocations;
+ uint64_t CSInvocations;
+};
+
int
brw_perf_query_get_mdapi_oa_data(struct brw_context *brw,
struct brw_perf_query_object *obj,
@@ -376,3 +391,54 @@ brw_perf_query_register_mdapi_oa_query(struct brw_context
*brw)
query->c_offset = copy_query->c_offset;
}
}
+
+void
+brw_perf_query_register_mdapi_statistic_query(struct brw_context *brw)
+{
+ const struct gen_device_info *devinfo = >screen->devinfo;
+
+ if (!(devinfo->gen >= 7 && devinfo->gen <= 9))
+ return;
+
+ struct brw_perf_query_info *query = brw_perf_query_append_query_info(brw);
+
+ query->kind = PIPELINE_STATS;
+ query->name = "Intel_Raw_Pipeline_Statistics_Query";
+ query->n_counters = 0;
+ query->counters =
+ rzalloc_array(brw, struct brw_perf_query_counter, MAX_STAT_COUNTERS);
+
+ /* The order has to match mdapi_pipeline_metrics. */
+ brw_perf_query_info_add_basic_stat_reg(query, IA_VERTICES_COUNT,
+ "N vertices submitted");
+ brw_perf_query_info_add_basic_stat_reg(query, IA_PRIMITIVES_COUNT,
+ "N primitives submitted");
+ brw_perf_query_info_add_basic_stat_reg(query, VS_INVOCATION_COUNT,
+ "N vertex shader invocations");
+ brw_perf_query_info_add_basic_stat_reg(query, GS_INVOCATION_COUNT,
+ "N geometry shader invocations");
+ brw_perf_query_info_add_basic_stat_reg(query, GS_PRIMITIVES_COUNT,
+ "N geometry shader primitives
emitted");
+ brw_perf_query_info_add_basic_stat_reg(query, CL_INVOCATION_COUNT,
+ "N primitives entering clipping");
+ brw_perf_query_info_add_basic_stat_reg(query, CL_PRIMITIVES_COUNT,
+ "N primitives leaving clipping");
+ if (devinfo->is_h
Mesa (master): anv: fix number of planes for depth & stencil
Module: Mesa
Branch: master
Commit: 0a6547014fbe5371f5b7253f2c2640ad0026b184
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0a6547014fbe5371f5b7253f2c2640ad0026b184
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Thu Apr 12 11:06:47 2018 -0700
anv: fix number of planes for depth & stencil
We're not counting correctly with depth & stencil images.
Additionally we need to move an assert that is meant just for color
attachments.
v2: Move an assert() (Reported by Craig)
Change aspect mask checks (Francesco)
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Fixes: a62a97933578a ("anv: enable multiple planes per image/imageView")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105994
Reviewed-by: Nanley Chery <nanley.g.ch...@intel.com>
---
src/intel/vulkan/anv_private.h | 4
src/intel/vulkan/genX_cmd_buffer.c | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 53115ae470..52d4ba58dc 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -2356,6 +2356,10 @@ anv_image_aspect_get_planes(VkImageAspectFlags
aspect_mask)
if (aspect_mask & VK_IMAGE_ASPECT_PLANE_2_BIT)
planes++;
+ if ((aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT) != 0 &&
+ (aspect_mask & VK_IMAGE_ASPECT_STENCIL_BIT) != 0)
+ planes++;
+
return planes;
}
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 3c703f6be4..cbe623802e 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1248,13 +1248,13 @@ genX(cmd_buffer_setup_attachments)(struct
anv_cmd_buffer *cmd_buffer,
struct anv_image_view *iview = framebuffer->attachments[i];
anv_assert(iview->vk_format == att->format);
- anv_assert(iview->n_planes == 1);
const uint32_t num_layers = iview->planes[0].isl.array_len;
state->attachments[i].pending_clear_views = (1 << num_layers) - 1;
union isl_color_value clear_color = { .u32 = { 0, } };
if (att_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
+anv_assert(iview->n_planes == 1);
assert(att_aspects == VK_IMAGE_ASPECT_COLOR_BIT);
color_attachment_compute_aux_usage(cmd_buffer->device,
state, i, begin->renderArea,
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: aubinator: print out addresses of invalid instructions
Module: Mesa
Branch: master
Commit: f3353e53dbd1afb1a399e8b2edac4ae403a2ecb2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f3353e53dbd1afb1a399e8b2edac4ae403a2ecb2
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Sat Apr 7 01:15:55 2018 +0100
intel: aubinator: print out addresses of invalid instructions
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/tools/gen_batch_decoder.c | 23 ++-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/src/intel/tools/gen_batch_decoder.c
b/src/intel/tools/gen_batch_decoder.c
index 1a8794c84e..c6b908758b 100644
--- a/src/intel/tools/gen_batch_decoder.c
+++ b/src/intel/tools/gen_batch_decoder.c
@@ -57,6 +57,7 @@ gen_batch_decode_ctx_finish(struct gen_batch_decode_ctx *ctx)
}
#define CSI "\e["
+#define RED_COLORCSI "31m"
#define BLUE_HEADER CSI "0;44m"
#define GREEN_HEADER CSI "1;42m"
#define NORMAL CSI "0m"
@@ -734,14 +735,23 @@ gen_print_batch(struct gen_batch_decode_ctx *ctx,
length = gen_group_get_length(inst, p);
assert(inst == NULL || length > 0);
length = MAX2(1, length);
+
+ const char *reset_color = ctx->flags & GEN_BATCH_DECODE_IN_COLOR ?
NORMAL : "";
+
+ uint64_t offset;
+ if (ctx->flags & GEN_BATCH_DECODE_OFFSETS)
+ offset = batch_addr + ((char *)p - (char *)batch);
+ else
+ offset = 0;
+
if (inst == NULL) {
- fprintf(ctx->fp, "unknown instruction %08x\n", p[0]);
+ fprintf(ctx->fp, "%s0x%08"PRIx64": unknown instruction %08x%s\n",
+ (ctx->flags & GEN_BATCH_DECODE_IN_COLOR) ? RED_COLOR : "",
+ offset, p[0], reset_color);
continue;
}
- const char *color, *reset_color;
- uint64_t offset;
-
+ const char *color;
const char *inst_name = gen_group_get_name(inst);
if (ctx->flags & GEN_BATCH_DECODE_IN_COLOR) {
reset_color = NORMAL;
@@ -759,11 +769,6 @@ gen_print_batch(struct gen_batch_decode_ctx *ctx,
reset_color = "";
}
- if (ctx->flags & GEN_BATCH_DECODE_OFFSETS)
- offset = batch_addr + ((char *)p - (char *)batch);
- else
- offset = 0;
-
fprintf(ctx->fp, "%s0x%08"PRIx64": 0x%08x: %-80s%s\n",
color, offset, p[0], inst_name, reset_color);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: compiler: silence compiler warning
Module: Mesa
Branch: master
Commit: 1beb80cb56170333c7fbe6bb144610d47e29f610
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1beb80cb56170333c7fbe6bb144610d47e29f610
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue Apr 3 14:41:18 2018 +0100
intel: compiler: silence compiler warning
../src/intel/compiler/brw_reg.h: In function ‘bool
brw_regs_negative_equal(const brw_reg*, const brw_reg*)’:
../src/intel/compiler/brw_reg.h:305:1: warning: control reaches end of non-void
function [-Wreturn-type]
Introduced by 8f83eea71e233 ("i965: Add negative_equals methods").
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Iago Toral Quiroga <ito...@igalia.com>
---
src/intel/compiler/brw_reg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h
index 68158cc0cc..afcd146de2 100644
--- a/src/intel/compiler/brw_reg.h
+++ b/src/intel/compiler/brw_reg.h
@@ -293,6 +293,7 @@ brw_regs_negative_equal(const struct brw_reg *a, const
struct brw_reg *b)
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
case BRW_REGISTER_TYPE_NF:
+ default:
unreachable("not reached");
}
} else {
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: genxml: decode variable length MI_LRI
Module: Mesa Branch: master Commit: 4d591272130c2d285b87e7925f620fcefdc2305e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4d591272130c2d285b87e7925f620fcefdc2305e Author: Lionel Landwerlin <lionel.g.landwer...@intel.com> Date: Tue Apr 3 11:21:31 2018 +0100 intel: genxml: decode variable length MI_LRI MI_LOAD_REGISTER_IMM can load multiple (register, value) tuples in one command. In our drivers we only use one tuple at a time, but the kernel might load more than one at a time. Instead of making all the tuple part of a group, we leave out the first tuple (the one we use in the generated packing structures). This is particularly useful for looking at error stats generated by the kernel. Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com> --- src/intel/genxml/gen10.xml | 4 src/intel/genxml/gen11.xml | 4 src/intel/genxml/gen4.xml | 4 src/intel/genxml/gen45.xml | 4 src/intel/genxml/gen5.xml | 4 src/intel/genxml/gen6.xml | 4 src/intel/genxml/gen7.xml | 4 src/intel/genxml/gen75.xml | 4 src/intel/genxml/gen8.xml | 4 src/intel/genxml/gen9.xml | 4 10 files changed, 40 insertions(+) diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml index bd914ad10e..8c35d70e9d 100644 --- a/src/intel/genxml/gen10.xml +++ b/src/intel/genxml/gen10.xml @@ -2969,6 +2969,10 @@ + + + + diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml index cb3212620f..517f0beb93 100644 --- a/src/intel/genxml/gen11.xml +++ b/src/intel/genxml/gen11.xml @@ -2956,6 +2956,10 @@ + + + + diff --git a/src/intel/genxml/gen4.xml b/src/intel/genxml/gen4.xml index e1ca810f23..6f513c5833 100644 --- a/src/intel/genxml/gen4.xml +++ b/src/intel/genxml/gen4.xml @@ -860,6 +860,10 @@ + + + + diff --git a/src/intel/genxml/gen45.xml b/src/intel/genxml/gen45.xml index 91dc363480..fbd57a00c5 100644 --- a/src/intel/genxml/gen45.xml +++ b/src/intel/genxml/gen45.xml @@ -890,6 +890,10 @@ + + + + diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml index 650692f6bd..5c93ecdda3 100644 --- a/src/intel/genxml/gen5.xml +++ b/src/intel/genxml/gen5.xml @@ -974,6 +974,10 @@ + + + + diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml index 08779733db..0493221bd7 100644 --- a/src/intel/genxml/gen6.xml +++ b/src/intel/genxml/gen6.xml @@ -1531,6 +1531,10 @@ + + + + diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml index 4865843fcb..baf42a7d32 100644 --- a/src/intel/genxml/gen7.xml +++ b/src/intel/genxml/gen7.xml @@ -2020,6 +2020,10 @@ + + + + diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml index da06e84ee9..7b635b22da 100644 --- a/src/intel/genxml/gen75.xml +++ b/src/intel/genxml/gen75.xml @@ -2380,6 +2380,10 @@ + + + + diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml index 28fbdfdf09..0f3757034f 100644 --- a/src/intel/genxml/gen8.xml +++ b/src/intel/genxml/gen8.xml @@ -2607,6 +2607,10 @@ + + + + diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml index 0912b6f7fe..7d3c74de74 100644 --- a/src/intel/genxml/gen9.xml +++ b/src/intel/genxml/gen9.xml @@ -2894,6 +2894,10 @@ + + + + ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: gen-decoder: print all dword a field belongs to
Module: Mesa
Branch: master
Commit: 78c18d99dc3c53e1026744835b202f89e7f7dfb6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=78c18d99dc3c53e1026744835b202f89e7f7dfb6
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue Apr 3 11:45:24 2018 +0100
intel: gen-decoder: print all dword a field belongs to
Prior to printing a decoded field, print out all dwords that field
belongs to. In particular with address fields spanning multiple
dwords, we want to have all the dwords presented before the field is
decoded to make it easier to read.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/common/gen_decoder.c | 13 +++--
src/intel/common/gen_decoder.h | 3 ++-
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 595fa29e43..1b8123bf39 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -841,7 +841,8 @@ iter_advance_field(struct gen_field_iterator *iter)
int group_member_offset = iter_group_offset_bits(iter, iter->group_iter);
- iter->bit = group_member_offset + iter->field->start;
+ iter->start_bit = group_member_offset + iter->field->start;
+ iter->end_bit = group_member_offset + iter->field->end;
iter->struct_desc = NULL;
return true;
@@ -852,10 +853,10 @@ iter_decode_field_raw(struct gen_field_iterator *iter,
uint64_t *qw)
{
*qw = 0;
- int field_start = iter->p_bit + iter->bit;
- int field_end = field_start + (iter->field->end - iter->field->start);
+ int field_start = iter->p_bit + iter->start_bit;
+ int field_end = iter->p_bit + iter->end_bit;
- const uint32_t *p = iter->p + (iter->bit / 32);
+ const uint32_t *p = iter->p + (iter->start_bit / 32);
if (iter->p_end && p >= iter->p_end)
return false;
@@ -1040,7 +1041,7 @@ gen_print_group(FILE *outfile, struct gen_group *group,
uint64_t offset,
gen_field_iterator_init(, group, p, p_bit, color);
do {
- int iter_dword = iter.bit / 32;
+ int iter_dword = iter.end_bit / 32;
if (last_dword != iter_dword) {
for (int i = last_dword + 1; i <= iter_dword; i++)
print_dword_header(outfile, , offset, i);
@@ -1051,7 +1052,7 @@ gen_print_group(FILE *outfile, struct gen_group *group,
uint64_t offset,
if (iter.struct_desc) {
uint64_t struct_offset = offset + 4 * iter_dword;
gen_print_group(outfile, iter.struct_desc, struct_offset,
-[iter_dword], iter.bit % 32, color);
+[iter_dword], iter.start_bit % 32, color);
}
}
} while (gen_field_iterator_next());
diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
index 7ae80cd23e..f28ac7d27a 100644
--- a/src/intel/common/gen_decoder.h
+++ b/src/intel/common/gen_decoder.h
@@ -73,7 +73,8 @@ struct gen_field_iterator {
const uint32_t *p;
int p_bit; /**< bit offset into p */
const uint32_t *p_end;
- int bit; /**< current field starts at this bit offset into p */
+ int start_bit; /**< current field starts at this bit offset into p */
+ int end_bit; /**< current field ends at this bit offset into p */
int group_iter;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: gen-decoder: don't decode fields beyond a dword length
Module: Mesa
Branch: master
Commit: 2841af6238b7648b388ba806f1ad181332b6eef0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2841af6238b7648b388ba806f1ad181332b6eef0
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue Apr 3 11:01:56 2018 +0100
intel: gen-decoder: don't decode fields beyond a dword length
For example, a PIPE_CONTROL with DWordLength = 2 should look like
this :
0xe374: 0x7a02: PIPE_CONTROL
0xe374: 0x7a02 : Dword 0
DWord Length: 2
0xe378: 0x0080 : Dword 1
Depth Cache Flush Enable: false
Stall At Pixel Scoreboard: false
State Cache Invalidation Enable: false
Constant Cache Invalidation Enable: false
VF Cache Invalidation Enable: false
DC Flush Enable: false
Pipe Control Flush Enable: false
Notify Enable: false
Indirect State Pointers Disable: false
Texture Cache Invalidation Enable: false
Instruction Cache Invalidate Enable: false
Render Target Cache Flush Enable: false
Depth Stall Enable: false
Post Sync Operation: 0 (No Write)
Generic Media State Clear: false
TLB Invalidate: false
Global Snapshot Count Reset: false
Command Streamer Stall Enable: false
Store Data Index: 0
LRI Post Sync Operation: 1 (MMIO Write Immediate Data)
Destination Address Type: 0 (PPGTT)
Flush LLC: false
0xe37c: 0x : Dword 2
Address: 0x
0xe384: 0x0500: MI_BATCH_BUFFER_END
Prior to this change, fields beyond the length of the command would be
decoded (notice the MI_BATCH_BUFFER_END decoded as part of the
previous PIPE_CONTROL) :
0xe374: 0x7a02: PIPE_CONTROL
0xe374: 0x7a02 : Dword 0
DWord Length: 2
0xe378: 0x0080 : Dword 1
Depth Cache Flush Enable: false
Stall At Pixel Scoreboard: false
State Cache Invalidation Enable: false
Constant Cache Invalidation Enable: false
VF Cache Invalidation Enable: false
DC Flush Enable: false
Pipe Control Flush Enable: false
Notify Enable: false
Indirect State Pointers Disable: false
Texture Cache Invalidation Enable: false
Instruction Cache Invalidate Enable: false
Render Target Cache Flush Enable: false
Depth Stall Enable: false
Post Sync Operation: 0 (No Write)
Generic Media State Clear: false
TLB Invalidate: false
Global Snapshot Count Reset: false
Command Streamer Stall Enable: false
Store Data Index: 0
LRI Post Sync Operation: 1 (MMIO Write Immediate Data)
Destination Address Type: 0 (PPGTT)
Flush LLC: false
0xe37c: 0x : Dword 2
Address: 0x
0xe380: 0x : Dword 3
0xe384: 0x0500 : Dword 4
Immediate Data: 83886080
0xe384: 0x0500: MI_BATCH_BUFFER_END
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/common/gen_decoder.c | 41 ++---
1 file changed, 26 insertions(+), 15 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 7ca71c0d9f..595fa29e43 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -847,35 +847,38 @@ iter_advance_field(struct gen_field_iterator *iter)
return true;
}
-static uint64_t
-iter_decode_field_raw(struct gen_field_iterator *iter)
+static bool
+iter_decode_field_raw(struct gen_field_iterator *iter, uint64_t *qw)
{
- uint64_t qw = 0;
+ *qw = 0;
int field_start = iter->p_bit + iter->bit;
int field_end = field_start + (iter->field->end - iter->field->start);
const uint32_t *p = iter->p + (iter->bit / 32);
+ if (iter->p_end && p >= iter->p_end)
+ return false;
+
if ((field_end - field_start) > 32) {
- if ((p + 1) < iter->p_end)
- qw = ((uint64_t) p[1]) << 32;
- qw |= p[0];
+ if (!iter->p_end || (p + 1) < iter->p_end)
+ *qw = ((uint64_t) p[1]) << 32;
+ *qw |= p[0];
} else
- qw = p[0];
+ *qw = p[0];
- qw = field_value(qw, field_start, field_end);
+ *qw = field_value(*qw, field_start, field_end);
/* Address & offset types have to be aligned to dwords, their start bit is
* a reminder of the alignment requirement.
*/
if (iter->field->type.kind == GEN_TYPE_ADDRESS ||
iter->field->type.kind == GEN_TYPE_OFFSET)
- qw <<= field_start % 32;
+ *qw <<= field_start % 32;
- return qw;
+ return true;
}
-static void
+static bool
iter_decode_field(struct gen_field_iterator *iter)
{
union {
@@ -890,7 +893,8 @@ iter_decode_field(struct gen_field_iterator *iter)
memset(, 0, sizeof(v));
- iter->raw_value = iter_decode_field_raw(iter);
+ if (!iter_decode_field_raw(iter, >raw_value))
+ return false;
const char *enum
Mesa (master): intel: genxml: add preemption control instructions
Module: Mesa Branch: master Commit: b3aa18dfd6fd343b45c1138e545d1130046bcb91 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3aa18dfd6fd343b45c1138e545d1130046bcb91 Author: Lionel Landwerlin <lionel.g.landwer...@intel.com> Date: Tue Mar 27 17:56:44 2018 +0100 intel: genxml: add preemption control instructions Helpful to debug kernel workaround batchbuffers. Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com> --- src/intel/genxml/gen10.xml | 7 +++ src/intel/genxml/gen11.xml | 7 +++ src/intel/genxml/gen8.xml | 6 ++ src/intel/genxml/gen9.xml | 6 ++ 4 files changed, 26 insertions(+) diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml index aeb9966759..bd914ad10e 100644 --- a/src/intel/genxml/gen10.xml +++ b/src/intel/genxml/gen10.xml @@ -2824,6 +2824,13 @@ + + + + + + + diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml index 6ca0e785ba..cb3212620f 100644 --- a/src/intel/genxml/gen11.xml +++ b/src/intel/genxml/gen11.xml @@ -2788,6 +2788,13 @@ + + + + + + + diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml index 71626c15cd..28fbdfdf09 100644 --- a/src/intel/genxml/gen8.xml +++ b/src/intel/genxml/gen8.xml @@ -2509,6 +2509,12 @@ + + + + + + diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml index c32f2c3162..0912b6f7fe 100644 --- a/src/intel/genxml/gen9.xml +++ b/src/intel/genxml/gen9.xml @@ -2752,6 +2752,12 @@ + + + + + + ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: error_decode: add an option to decode all buffers
Module: Mesa
Branch: master
Commit: 81375516b273094f29d4e1c4fcb90d832273690a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=81375516b273094f29d4e1c4fcb90d832273690a
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue Mar 27 18:10:45 2018 +0100
intel: error_decode: add an option to decode all buffers
The kernel reports workaround batch buffers, but we're not presenting
them currently. Also they might not be useful for debugging purely
userspace driver issues, when problems arise because of interactions
between kernel & userspace drivers, it's nice to be able to decode
them.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/tools/aubinator_error_decode.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/intel/tools/aubinator_error_decode.c
b/src/intel/tools/aubinator_error_decode.c
index 9abd05fd75..0234c59371 100644
--- a/src/intel/tools/aubinator_error_decode.c
+++ b/src/intel/tools/aubinator_error_decode.c
@@ -51,6 +51,7 @@
/* options */
static bool option_full_decode = true;
+static bool option_print_all_bb = false;
static bool option_print_offsets = true;
static enum { COLOR_AUTO, COLOR_ALWAYS, COLOR_NEVER } option_color;
static char *xml_path = NULL;
@@ -446,6 +447,7 @@ read_data_file(FILE *file)
{ "hw status", "HW status" },
{ "wa context", "WA context" },
{ "wa batchbuffer", "WA batch" },
+{ "NULL context", "Kernel context" },
{ "user", "user" },
{ "semaphores", "semaphores", },
{ "guc log buffer", "GuC log", },
@@ -602,7 +604,8 @@ read_data_file(FILE *file)
(unsigned) (sections[s].gtt_offset >> 32),
(unsigned) sections[s].gtt_offset);
- if (strcmp(sections[s].buffer_name, "batch buffer") == 0 ||
+ if (option_print_all_bb ||
+ strcmp(sections[s].buffer_name, "batch buffer") == 0 ||
strcmp(sections[s].buffer_name, "ring buffer") == 0 ||
strcmp(sections[s].buffer_name, "HW Context") == 0) {
gen_print_batch(_ctx, sections[s].data, sections[s].count,
@@ -660,7 +663,8 @@ print_help(const char *progname, FILE *file)
"if omitted), 'always', or 'never'\n"
" --no-pager don't launch pager\n"
" --no-offsetsdon't print instruction offsets\n"
- " --xml=DIR load hardware xml description from directory
DIR\n",
+ " --xml=DIR load hardware xml description from directory
DIR\n"
+ " --all-bbprint out all batchbuffers\n",
progname);
}
@@ -679,6 +683,7 @@ main(int argc, char *argv[])
{ "headers",no_argument, (int *) _full_decode, false
},
{ "color", required_argument, NULL, 'c' },
{ "xml",required_argument, NULL, 'x' },
+ { "all-bb", no_argument, (int *) _print_all_bb, true },
{ NULL, 0, NULL, 0 }
};
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): compiler: glsl: silence valgrind warning on write cache
Module: Mesa
Branch: master
Commit: 412fae46c0fdf9f56281aa9c81fd53961cc23594
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=412fae46c0fdf9f56281aa9c81fd53961cc23594
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Fri Mar 23 10:40:02 2018 +
compiler: glsl: silence valgrind warning on write cache
I don't think it actually fixes anything, but that's nice not to have valgrind
warnings.
It manifests itself when running the piglit test : glsl-fs-raytrace-bug27060
==2058== Uninitialised byte(s) found during client check request
==2058==at 0xC5BB040: blob_write_bytes (blob.c:152)
==2058==by 0xC595359: write_variable (nir_serialize.c:144)
==2058==by 0xC59560C: write_var_list (nir_serialize.c:192)
==2058==by 0xC5982E4: nir_serialize (nir_serialize.c:1124)
==2058==by 0xC0B729D: brw_program_serialize_nir (brw_program.c:835)
==2058==by 0xC0AB2D6: brw_link_shader (brw_link.cpp:358)
==2058==by 0xC32FE3F: _mesa_glsl_link_shader (ir_to_mesa.cpp:3169)
==2058==by 0xC36C7ED: create_new_program(gl_context*, state_key*)
(ff_fragment_shader.cpp:1127)
==2058==by 0xC36C8A6: _mesa_get_fixed_func_fragment_program
(ff_fragment_shader.cpp:1157)
==2058==by 0xC1B50AF: update_program (state.c:134)
==2058==by 0xC1B56DF: _mesa_update_state_locked (state.c:352)
==2058==by 0xC1B579A: _mesa_update_state (state.c:386)
==2058== Address 0xf1eab8a is 58 bytes inside a block of size 96 alloc'd
==2058==at 0x4C2CB8F: malloc (vg_replace_malloc.c:299)
==2058==by 0xC0FD306: ralloc_size (ralloc.c:121)
==2058==by 0xC0FD5B1: ralloc_array_size (ralloc.c:208)
==2058==by 0xC452B3B: (anonymous
namespace)::nir_visitor::visit(ir_variable*) (glsl_to_nir.cpp:448)
==2058==by 0xC45CE8B: ir_variable::accept(ir_visitor*) (ir.h:428)
==2058==by 0xC46D0B5: visit_exec_list(exec_list*, ir_visitor*) (ir.cpp:1898)
==2058==by 0xC451D2F: glsl_to_nir (glsl_to_nir.cpp:162)
==2058==by 0xC0B5223: brw_create_nir (brw_program.c:79)
==2058==by 0xC0AAB67: brw_link_shader (brw_link.cpp:257)
==2058==by 0xC32FE3F: _mesa_glsl_link_shader (ir_to_mesa.cpp:3169)
==2058==by 0xC36C7ED: create_new_program(gl_context*, state_key*)
(ff_fragment_shader.cpp:1127)
==2058==by 0xC36C8A6: _mesa_get_fixed_func_fragment_program
(ff_fragment_shader.cpp:1157)
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>
---
src/compiler/glsl/glsl_to_nir.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/compiler/glsl/glsl_to_nir.cpp
b/src/compiler/glsl/glsl_to_nir.cpp
index 65c5576d1a..9e938daf8d 100644
--- a/src/compiler/glsl/glsl_to_nir.cpp
+++ b/src/compiler/glsl/glsl_to_nir.cpp
@@ -445,8 +445,8 @@ nir_visitor::visit(ir_variable *ir)
var->num_state_slots = ir->get_num_state_slots();
if (var->num_state_slots > 0) {
- var->state_slots = ralloc_array(var, nir_state_slot,
- var->num_state_slots);
+ var->state_slots = rzalloc_array(var, nir_state_slot,
+ var->num_state_slots);
ir_state_slot *state_slots = ir->get_state_slots();
for (unsigned i = 0; i < var->num_state_slots; i++) {
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: add performance query support on CNL
Module: Mesa Branch: master Commit: 903e9952fbce28677945325fd3ac6f01b3e560ce URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=903e9952fbce28677945325fd3ac6f01b3e560ce Author: Lionel Landwerlin <lionel.g.landwer...@intel.com> Date: Thu Feb 22 17:12:42 2018 + i965: add performance query support on CNL v2: Add brw_oa_cnl.xml to EXTRA_DIST (Emil) Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Acked-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/Makefile.sources| 3 +- src/mesa/drivers/dri/i965/brw_oa_cnl.xml | 10410 src/mesa/drivers/dri/i965/brw_performance_query.c | 2 + src/mesa/drivers/dri/i965/meson.build | 1 + 4 files changed, 10415 insertions(+), 1 deletion(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=903e9952fbce28677945325fd3ac6f01b3e560ce ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: devinfo: store number of EUs per subslice
Module: Mesa
Branch: master
Commit: 7e2c6147da427df974b673178d7142836bfac6a1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e2c6147da427df974b673178d7142836bfac6a1
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed Mar 14 13:15:12 2018 +
intel: devinfo: store number of EUs per subslice
This will be reused to store values reported by the kernel. The main
use case will be for use as the input values of the metric sets
equations for the INTEL_performance_queries extension. By storing this
information in the gen_device_info we make this non GL specific so
this can be reused by Vulkan if we ever have an equivalent extension.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/intel/dev/gen_device_info.c | 35 +--
src/intel/dev/gen_device_info.h | 5 +
2 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
index 9e684b78a0..29d24aeda5 100644
--- a/src/intel/dev/gen_device_info.c
+++ b/src/intel/dev/gen_device_info.c
@@ -93,6 +93,7 @@ static const struct gen_device_info gen_device_info_i965 = {
.has_negative_rhw_bug = true,
.num_slices = 1,
.num_subslices = { 1, },
+ .num_eu_per_subslice = 8,
.num_thread_per_eu = 4,
.max_vs_threads = 16,
.max_gs_threads = 2,
@@ -111,6 +112,7 @@ static const struct gen_device_info gen_device_info_g4x = {
.is_g4x = true,
.num_slices = 1,
.num_subslices = { 1, },
+ .num_eu_per_subslice = 10,
.num_thread_per_eu = 5,
.max_vs_threads = 32,
.max_gs_threads = 2,
@@ -128,6 +130,7 @@ static const struct gen_device_info gen_device_info_ilk = {
.has_surface_tile_offset = true,
.num_slices = 1,
.num_subslices = { 1, },
+ .num_eu_per_subslice = 12,
.num_thread_per_eu = 6,
.max_vs_threads = 72,
.max_gs_threads = 32,
@@ -148,6 +151,7 @@ static const struct gen_device_info gen_device_info_snb_gt1
= {
.needs_unlit_centroid_workaround = true,
.num_slices = 1,
.num_subslices = { 1, },
+ .num_eu_per_subslice = 6,
.num_thread_per_eu = 6, /* Not confirmed */
.max_vs_threads = 24,
.max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
@@ -175,6 +179,7 @@ static const struct gen_device_info gen_device_info_snb_gt2
= {
.needs_unlit_centroid_workaround = true,
.num_slices = 1,
.num_subslices = { 1, },
+ .num_eu_per_subslice = 12,
.num_thread_per_eu = 6, /* Not confirmed */
.max_vs_threads = 60,
.max_gs_threads = 60,
@@ -206,6 +211,7 @@ static const struct gen_device_info gen_device_info_ivb_gt1
= {
GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
.num_slices = 1,
.num_subslices = { 1, },
+ .num_eu_per_subslice = 6,
.num_thread_per_eu = 6,
.l3_banks = 2,
.max_vs_threads = 36,
@@ -233,6 +239,7 @@ static const struct gen_device_info gen_device_info_ivb_gt2
= {
GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
.num_slices = 1,
.num_subslices = { 1, },
+ .num_eu_per_subslice = 12,
.num_thread_per_eu = 8, /* Not sure why this isn't a multiple of
* @max_wm_threads ... */
.l3_banks = 4,
@@ -261,6 +268,7 @@ static const struct gen_device_info gen_device_info_byt = {
GEN7_FEATURES, .is_baytrail = true, .gt = 1,
.num_slices = 1,
.num_subslices = { 1, },
+ .num_eu_per_subslice = 4,
.num_thread_per_eu = 8,
.l3_banks = 1,
.has_llc = false,
@@ -295,6 +303,7 @@ static const struct gen_device_info gen_device_info_hsw_gt1
= {
HSW_FEATURES, .gt = 1,
.num_slices = 1,
.num_subslices = { 1, },
+ .num_eu_per_subslice = 10,
.num_thread_per_eu = 7,
.l3_banks = 2,
.max_vs_threads = 70,
@@ -322,6 +331,7 @@ static const struct gen_device_info gen_device_info_hsw_gt2
= {
HSW_FEATURES, .gt = 2,
.num_slices = 1,
.num_subslices = { 2, },
+ .num_eu_per_subslice = 10,
.num_thread_per_eu = 7,
.l3_banks = 4,
.max_vs_threads = 280,
@@ -349,6 +359,7 @@ static const struct gen_device_info gen_device_info_hsw_gt3
= {
HSW_FEATURES, .gt = 3,
.num_slices = 2,
.num_subslices = { 2, },
+ .num_eu_per_subslice = 10,
.num_thread_per_eu = 7,
.l3_banks = 8,
.max_vs_threads = 280,
@@ -399,6 +410,7 @@ static const struct gen_device_info gen_device_info_bdw_gt1
= {
.is_broadwell = true,
.num_slices = 1,
.num_subslices = { 2, },
+ .num_eu_per_subslice = 8,
.num_thread_per_eu = 7,
.l3_banks = 2,
.max_cs_threads = 42,
@@ -422,6 +434,7 @@ static const struct gen_device_info gen_device_info_bdw_gt2
= {
.is_broadwell = true,
.num_slices = 1,
.num_subslices = { 3, },
+ .num_eu_per_subslice = 8,
.num_thread_per_eu = 7,
.l3_banks = 4,
.max_cs_threads = 56,
@@ -445,6 +458,7 @@ static const struct gen_device_info gen_device_info_bdw_gt3
= {
.i
Mesa (master): intel: devinfo: meson: include drm uapi
Module: Mesa Branch: master Commit: 2d26c9993389a8eb8f7125e2440a2e7c5729a405 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d26c9993389a8eb8f7125e2440a2e7c5729a405 Author: Lionel Landwerlin <lionel.g.landwer...@intel.com> Date: Wed Mar 14 15:43:57 2018 + intel: devinfo: meson: include drm uapi Already available with the autotools build. Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/intel/dev/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/dev/meson.build b/src/intel/dev/meson.build index 3346fe60c0..9369fd3c0d 100644 --- a/src/intel/dev/meson.build +++ b/src/intel/dev/meson.build @@ -28,6 +28,6 @@ files_libintel_dev = files( libintel_dev = static_library( ['intel_dev'], files_libintel_dev, - include_directories : [inc_common, inc_intel], + include_directories : [inc_common, inc_intel, inc_drm_uapi], c_args : [c_vis_args, no_override_init_args], ) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: perf: query topology
Module: Mesa
Branch: master
Commit: 57a11550bc6195c404496e4278920ea63a343f08
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=57a11550bc6195c404496e4278920ea63a343f08
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed Feb 21 19:15:46 2018 +
i965: perf: query topology
With the introduction of asymmetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam to tell userspace what subslices
are available.
We introduce a new uAPI in the kernel driver to report exactly what
part of the GPU are fused and require this to be available on Gen10+.
Prior generations can continue to rely on GETPARAM on older kernels.
This patch is quite a lot of code because we have to support lots of
different kernel versions, ranging from not providing any information
(for Haswell on 4.13 through 4.17), to being able to query through
GETPARAM (for gen8/9 on 4.13 through 4.17), to finally requiring 4.17
for Gen10+.
This change stores topology information in a unified way on
brw_context.topology from the various kernel APIs. And then generates
the appropriate values for the equations from that unified topology.
v2: Move slice/subslice masks fields to gen_device_info (Rafael)
v3: Add a gen_device_info_subslice_available() helper (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Acked-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/intel/dev/gen_device_info.h | 8 +
src/mesa/drivers/dri/i965/brw_performance_query.c | 181 +-
2 files changed, 118 insertions(+), 71 deletions(-)
diff --git a/src/intel/dev/gen_device_info.h b/src/intel/dev/gen_device_info.h
index 4d08f0dfed..40b7238342 100644
--- a/src/intel/dev/gen_device_info.h
+++ b/src/intel/dev/gen_device_info.h
@@ -247,6 +247,14 @@ struct gen_device_info
#define gen_device_info_is_9lp(devinfo) \
((devinfo)->is_broxton || (devinfo)->is_geminilake)
+static inline bool
+gen_device_info_subslice_available(const struct gen_device_info *devinfo,
+ int slice, int subslice)
+{
+ return (devinfo->subslice_masks[slice * devinfo->subslice_slice_stride +
+ subslice / 8] & (1U << (subslice % 8))) !=
0;
+}
+
int gen_get_pci_device_id_override(void);
int gen_device_name_to_pci_device_id(const char *name);
bool gen_get_device_info(int devid, struct gen_device_info *devinfo);
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 12f797c129..cca74001f1 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1911,6 +1911,100 @@ init_oa_configs(struct brw_context *brw)
}
static bool
+query_topology(struct brw_context *brw)
+{
+ __DRIscreen *screen = brw->screen->driScrnPriv;
+ struct drm_i915_query_item item = {
+ .query_id = DRM_I915_QUERY_TOPOLOGY_INFO,
+ };
+ struct drm_i915_query query = {
+ .num_items = 1,
+ .items_ptr = (uintptr_t) ,
+ };
+
+ if (drmIoctl(screen->fd, DRM_IOCTL_I915_QUERY, ))
+ return false;
+
+ struct drm_i915_query_topology_info *topo_info =
+ (struct drm_i915_query_topology_info *) calloc(1, item.length);
+ item.data_ptr = (uintptr_t) topo_info;
+
+ if (drmIoctl(screen->fd, DRM_IOCTL_I915_QUERY, ) ||
+ item.length <= 0)
+ return false;
+
+ gen_device_info_update_from_topology(>screen->devinfo,
+topo_info);
+
+ free(topo_info);
+
+ return true;
+}
+
+static bool
+getparam_topology(struct brw_context *brw)
+{
+ __DRIscreen *screen = brw->screen->driScrnPriv;
+ drm_i915_getparam_t gp;
+ int ret;
+
+ int slice_mask = 0;
+ gp.param = I915_PARAM_SLICE_MASK;
+ gp.value = _mask;
+ ret = drmIoctl(screen->fd, DRM_IOCTL_I915_GETPARAM, );
+ if (ret)
+ return false;
+
+ int subslice_mask = 0;
+ gp.param = I915_PARAM_SUBSLICE_MASK;
+ gp.value = _mask;
+ ret = drmIoctl(screen->fd, DRM_IOCTL_I915_GETPARAM, );
+ if (ret)
+ return false;
+
+ gen_device_info_update_from_masks(>screen->devinfo,
+ slice_mask,
+ subslice_mask,
+ brw->screen->eu_total);
+
+ return true;
+}
+
+static void
+compute_topology_builtins(struct brw_context *brw)
+{
+ const struct gen_device_info *devinfo = >screen->devinfo;
+
+ brw->perfquery.sys_vars.slice_mask = devinfo->slice_masks;
+ brw->perfquery.sys_vars.n_eu_slices = devinfo->num_slices;
+
+ for (int i = 0; i < sizeof(devinfo->subslice_masks[i]); i++) {
+ brw->perfquery.sys_vars.n_eu_sub_slices +=
+ _mesa_bitcount(devinfo->subslice_masks[i]);
+ }
+
+ for (int i = 0; i
Mesa (master): drm-uapi: bump headers
Module: Mesa
Branch: master
Commit: 5d3e74a5a539559612d41432e9cef8d1b2ce0638
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d3e74a5a539559612d41432e9cef8d1b2ce0638
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed Feb 21 14:21:08 2018 +
drm-uapi: bump headers
Required updates from drm-next for changes in i965.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Acked-by: Kenneth Graunke <kenn...@whitecape.org
---
include/drm-uapi/README | 8 +--
include/drm-uapi/drm_mode.h | 43 +---
include/drm-uapi/i915_drm.h | 152 +--
include/drm-uapi/tegra_drm.h | 22 +--
4 files changed, 189 insertions(+), 36 deletions(-)
diff --git a/include/drm-uapi/README b/include/drm-uapi/README
index 53dd711dad..7f63fb2038 100644
--- a/include/drm-uapi/README
+++ b/include/drm-uapi/README
@@ -13,9 +13,9 @@ $ make headers_install INSTALL_HDR_PATH=/path/to/install
The last update was done at the following kernel commit :
-commit ca797d29cd63e7b71b4eea29aff3b1cefd1ecb59
-Merge: 2c1c55cb75a9 010d118c2061
+commit 78230c46ec0a91dd4256c9e54934b3c7095a7ee3
+Merge: b65bd4031156 037f03155b7d
Author: Dave Airlie <airl...@redhat.com>
-Date: Mon Dec 4 09:40:35 2017 +1000
+Date: Wed Mar 21 14:07:03 2018 +1000
-Merge tag 'drm-intel-next-2017-11-17-1' of
git://anongit.freedesktop.org/drm/drm-intel into drm-next
+Merge tag 'omapdrm-4.17' of
git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux into drm-next
diff --git a/include/drm-uapi/drm_mode.h b/include/drm-uapi/drm_mode.h
index 5597a87154..50bcf4214f 100644
--- a/include/drm-uapi/drm_mode.h
+++ b/include/drm-uapi/drm_mode.h
@@ -38,14 +38,18 @@ extern "C" {
#define DRM_DISPLAY_MODE_LEN 32
#define DRM_PROP_NAME_LEN 32
-#define DRM_MODE_TYPE_BUILTIN (1<<0)
-#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN)
-#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN)
+#define DRM_MODE_TYPE_BUILTIN (1<<0) /* deprecated */
+#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) /* deprecated
*/
+#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) /* deprecated
*/
#define DRM_MODE_TYPE_PREFERRED(1<<3)
-#define DRM_MODE_TYPE_DEFAULT (1<<4)
+#define DRM_MODE_TYPE_DEFAULT (1<<4) /* deprecated */
#define DRM_MODE_TYPE_USERDEF (1<<5)
#define DRM_MODE_TYPE_DRIVER (1<<6)
+#define DRM_MODE_TYPE_ALL (DRM_MODE_TYPE_PREFERRED | \
+DRM_MODE_TYPE_USERDEF |\
+DRM_MODE_TYPE_DRIVER)
+
/* Video mode flags */
/* bit compatible with the xrandr RR_ definitions (bits 0-13)
*
@@ -66,8 +70,8 @@ extern "C" {
#define DRM_MODE_FLAG_PCSYNC (1<<7)
#define DRM_MODE_FLAG_NCSYNC (1<<8)
#define DRM_MODE_FLAG_HSKEW(1<<9) /* hskew provided */
-#define DRM_MODE_FLAG_BCAST(1<<10)
-#define DRM_MODE_FLAG_PIXMUX (1<<11)
+#define DRM_MODE_FLAG_BCAST(1<<10) /* deprecated */
+#define DRM_MODE_FLAG_PIXMUX (1<<11) /* deprecated */
#define DRM_MODE_FLAG_DBLCLK (1<<12)
#define DRM_MODE_FLAG_CLKDIV2 (1<<13)
/*
@@ -99,6 +103,20 @@ extern "C" {
#define DRM_MODE_FLAG_PIC_AR_16_9 \
(DRM_MODE_PICTURE_ASPECT_16_9<<19)
+#define DRM_MODE_FLAG_ALL (DRM_MODE_FLAG_PHSYNC | \
+DRM_MODE_FLAG_NHSYNC | \
+DRM_MODE_FLAG_PVSYNC | \
+DRM_MODE_FLAG_NVSYNC | \
+DRM_MODE_FLAG_INTERLACE | \
+DRM_MODE_FLAG_DBLSCAN |\
+DRM_MODE_FLAG_CSYNC | \
+DRM_MODE_FLAG_PCSYNC | \
+DRM_MODE_FLAG_NCSYNC | \
+DRM_MODE_FLAG_HSKEW | \
+DRM_MODE_FLAG_DBLCLK | \
+DRM_MODE_FLAG_CLKDIV2 |\
+DRM_MODE_FLAG_3D_MASK)
+
/* DPMS flags */
/* bit compatible with the xorg definitions. */
#define DRM_MODE_DPMS_ON 0
@@ -173,6 +191,10 @@ extern "C" {
DRM_MODE_REFLECT_X | \
DRM_MODE_REFLECT_Y)
+/* Content Protection Flags */
+#define DRM_MODE_CONTENT_PROTECTION_UNDESIRED 0
+#define DRM_MODE_CONTENT_PROTECTION_DESIRED 1
+#define DRM_MODE_CONTENT_PROTECTION_ENABLED 2
struct drm_mode_modeinfo {
__u32 clock;
@@ -341,7 +363,7 @@ struct drm_mode_get_connector {
__u32 pad;
};
-
Mesa (master): i965: perf: add support for new equation operators
Module: Mesa
Branch: master
Commit: e7f6d1e5f8a4486b1c04b70979131fe4c1852809
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e7f6d1e5f8a4486b1c04b70979131fe4c1852809
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Thu Feb 22 17:17:40 2018 +
i965: perf: add support for new equation operators
Some equations of the CNL metrics started to use operators we haven't
defined yet, just add those.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_oa.py | 15 +++
1 file changed, 15 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_oa.py
b/src/mesa/drivers/dri/i965/brw_oa.py
index b0b2be2af0..7bf7987b4c 100644
--- a/src/mesa/drivers/dri/i965/brw_oa.py
+++ b/src/mesa/drivers/dri/i965/brw_oa.py
@@ -120,6 +120,18 @@ def emit_umin(tmp_id, args):
c("uint64_t tmp{0} = MIN({1}, {2});".format(tmp_id, args[1], args[0]))
return tmp_id + 1
+def emit_lshft(tmp_id, args):
+c("uint64_t tmp{0} = {1} << {2};".format(tmp_id, args[1], args[0]))
+return tmp_id + 1
+
+def emit_rshft(tmp_id, args):
+c("uint64_t tmp{0} = {1} >> {2};".format(tmp_id, args[1], args[0]))
+return tmp_id + 1
+
+def emit_and(tmp_id, args):
+c("uint64_t tmp{0} = {1} & {2};".format(tmp_id, args[1], args[0]))
+return tmp_id + 1
+
ops = {}
# (n operands, emitter)
ops["FADD"] = (2, emit_fadd)
@@ -133,6 +145,9 @@ ops["UDIV"] = (2, emit_udiv)
ops["UMUL"] = (2, emit_umul)
ops["USUB"] = (2, emit_usub)
ops["UMIN"] = (2, emit_umin)
+ops["<<"] = (2, emit_lshft)
+ops[">>"] = (2, emit_rshft)
+ops["AND"] = (2, emit_and)
def brkt(subexp):
if " " in subexp:
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: devinfo: store slice/subslice/eu masks
Module: Mesa
Branch: master
Commit: c471716574c951cc332ca1cce1a221befc9f9392
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c471716574c951cc332ca1cce1a221befc9f9392
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed Mar 14 13:16:01 2018 +
intel: devinfo: store slice/subslice/eu masks
We want to store values coming from the kernel but as a first step, we
can generate mask values out the numbers already stored in the
gen_device_info masks.
v2: Add a helper to set EU masks (Lionel/Ken)
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/intel/dev/gen_device_info.c | 53 +
src/intel/dev/gen_device_info.h | 39 +-
2 files changed, 91 insertions(+), 1 deletion(-)
diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
index 29d24aeda5..acf921b60a 100644
--- a/src/intel/dev/gen_device_info.c
+++ b/src/intel/dev/gen_device_info.c
@@ -874,6 +874,57 @@ static const struct gen_device_info
gen_device_info_icl_1x8 = {
GEN11_FEATURES(1, 1, subslices(1), 6),
};
+static void
+gen_device_info_set_eu_mask(struct gen_device_info *devinfo,
+unsigned slice,
+unsigned subslice,
+unsigned eu_mask)
+{
+ unsigned subslice_offset = slice * devinfo->eu_slice_stride +
+ subslice * devinfo->eu_subslice_stride;
+
+ for (unsigned b_eu = 0; b_eu < devinfo->eu_subslice_stride; b_eu++) {
+ devinfo->eu_masks[subslice_offset + b_eu] =
+ (((1U << devinfo->num_eu_per_subslice) - 1) >> (b_eu * 8)) & 0xff;
+ }
+}
+
+/* Generate slice/subslice/eu masks from number of
+ * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
+ * structure.
+ *
+ * These can be overridden with values reported by the kernel either from
+ * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
+ * through the i915 query uapi.
+ */
+static void
+fill_masks(struct gen_device_info *devinfo)
+{
+ devinfo->slice_masks = (1U << devinfo->num_slices) - 1;
+
+ /* Subslice masks */
+ unsigned max_subslices = 0;
+ for (int s = 0; s < devinfo->num_slices; s++)
+ max_subslices = MAX2(devinfo->num_subslices[s], max_subslices);
+ devinfo->subslice_slice_stride = DIV_ROUND_UP(max_subslices, 8);
+
+ for (int s = 0; s < devinfo->num_slices; s++) {
+ devinfo->subslice_masks[s * devinfo->subslice_slice_stride] =
+ (1U << devinfo->num_subslices[s]) - 1;
+ }
+
+ /* EU masks */
+ devinfo->eu_subslice_stride = DIV_ROUND_UP(devinfo->num_eu_per_subslice, 8);
+ devinfo->eu_slice_stride = max_subslices * devinfo->eu_subslice_stride;
+
+ for (int s = 0; s < devinfo->num_slices; s++) {
+ for (int ss = 0; ss < devinfo->num_subslices[s]; ss++) {
+ gen_device_info_set_eu_mask(devinfo, s, ss,
+ (1U << devinfo->num_eu_per_subslice) - 1);
+ }
+ }
+}
+
bool
gen_get_device_info(int devid, struct gen_device_info *devinfo)
{
@@ -887,6 +938,8 @@ gen_get_device_info(int devid, struct gen_device_info
*devinfo)
return false;
}
+ fill_masks(devinfo);
+
/* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
*
* "Scratch Space per slice is computed based on 4 sub-slices. SW must
diff --git a/src/intel/dev/gen_device_info.h b/src/intel/dev/gen_device_info.h
index 17285ffed8..793ce09485 100644
--- a/src/intel/dev/gen_device_info.h
+++ b/src/intel/dev/gen_device_info.h
@@ -28,10 +28,16 @@
#include
#include
+#include "util/macros.h"
+
#ifdef __cplusplus
extern "C" {
#endif
+#define GEN_DEVICE_MAX_SLICES (6) /* Maximum on gen10 */
+#define GEN_DEVICE_MAX_SUBSLICES(8) /* Maximum on gen11 */
+#define GEN_DEVICE_MAX_EUS_PER_SUBSLICE (10) /* Maximum on Haswell */
+
/**
* Intel hardware information and quirks
*/
@@ -112,7 +118,7 @@ struct gen_device_info
/**
* Number of subslices for each slice (used to be uniform until CNL).
*/
- unsigned num_subslices[3];
+ unsigned num_subslices[GEN_DEVICE_MAX_SUBSLICES];
/**
* Number of EU per subslice.
@@ -124,6 +130,37 @@ struct gen_device_info
*/
unsigned num_thread_per_eu;
+ /**
+* A bit mask of the slices available.
+*/
+ uint8_t slice_masks;
+
+ /**
+* An array of bit mask of the subslices available, use
subslice_slice_stride
+* to access this array.
+*/
+ uint8_t subslice_masks[GEN_DEVICE_MAX_SLICES *
+ DIV_ROUND_UP(GEN_DEVICE_MAX_SUBSLICES, 8)];
+
+ /**
+* An array of bit mask of EUs available, use eu_slice_stride &
+* eu_subslice_stride to access this array.
+*/
+
Mesa (master): intel: devinfo: add helper functions to fill fusing masks values
Module: Mesa
Branch: master
Commit: c1900f5b0fb7a6f22a13f67e2645f3754b5df245
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c1900f5b0fb7a6f22a13f67e2645f3754b5df245
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed Mar 14 15:44:56 2018 +
intel: devinfo: add helper functions to fill fusing masks values
There are a couple of ways we can get the fusing information from the
kernel :
- Through DRM_I915_GETPARAM with the SLICE_MASK/SUBSLICE_MASK
parameters
- Through the new DRM_IOCTL_I915_QUERY by requesting the
DRM_I915_QUERY_TOPOLOGY_INFO
The second method is more accurate and also gives us the EUs fusing
masks. It's also a requirement for CNL as this platform has asymetric
subslices and the first method SUBSLICE_MASK value is assumed uniform
across slices.
v2: Change gen_device_info_update_from_masks() to generate topology
and call into gen_device_info_update_from_topology (Lionel/Ken)
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/intel/dev/gen_device_info.c | 126
src/intel/dev/gen_device_info.h | 15 -
2 files changed, 140 insertions(+), 1 deletion(-)
diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
index acf921b60a..f7cb94f179 100644
--- a/src/intel/dev/gen_device_info.c
+++ b/src/intel/dev/gen_device_info.c
@@ -28,8 +28,11 @@
#include
#include "gen_device_info.h"
#include "compiler/shader_enums.h"
+#include "util/bitscan.h"
#include "util/macros.h"
+#include
+
/**
* Get the PCI ID for the device name.
*
@@ -925,6 +928,129 @@ fill_masks(struct gen_device_info *devinfo)
}
}
+void
+gen_device_info_update_from_masks(struct gen_device_info *devinfo,
+ uint32_t slice_mask,
+ uint32_t subslice_mask,
+ uint32_t n_eus)
+{
+ struct {
+ struct drm_i915_query_topology_info base;
+ uint8_t data[100];
+ } topology;
+
+ assert((slice_mask & 0xff) == slice_mask);
+
+ memset(, 0, sizeof(topology));
+
+ topology.base.max_slices = util_last_bit(slice_mask);
+ topology.base.max_subslices = util_last_bit(subslice_mask);
+
+ topology.base.subslice_offset = DIV_ROUND_UP(topology.base.max_slices, 8);
+ topology.base.subslice_stride = DIV_ROUND_UP(topology.base.max_subslices,
8);
+
+ uint32_t n_subslices = __builtin_popcount(slice_mask) *
+ __builtin_popcount(subslice_mask);
+ uint32_t num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
+ uint32_t eu_mask = (1U << num_eu_per_subslice) - 1;
+
+ topology.base.eu_offset = topology.base.subslice_offset +
+ DIV_ROUND_UP(topology.base.max_subslices, 8);
+ topology.base.eu_stride = DIV_ROUND_UP(num_eu_per_subslice, 8);
+
+ /* Set slice mask in topology */
+ for (int b = 0; b < topology.base.subslice_offset; b++)
+ topology.base.data[b] = (slice_mask >> (b * 8)) & 0xff;
+
+ for (int s = 0; s < topology.base.max_slices; s++) {
+
+ /* Set subslice mask in topology */
+ for (int b = 0; b < topology.base.subslice_stride; b++) {
+ int subslice_offset = topology.base.subslice_offset +
+s * topology.base.subslice_stride + b;
+
+ topology.base.data[subslice_offset] = (subslice_mask >> (b * 8)) &
0xff;
+ }
+
+ /* Set eu mask in topology */
+ for (int ss = 0; ss < topology.base.max_subslices; ss++) {
+ for (int b = 0; b < topology.base.eu_stride; b++) {
+int eu_offset = topology.base.eu_offset +
+ (s * topology.base.max_subslices + ss) *
topology.base.eu_stride + b;
+
+topology.base.data[eu_offset] = (eu_mask >> (b * 8)) & 0xff;
+ }
+ }
+ }
+
+ gen_device_info_update_from_topology(devinfo, );
+}
+
+static void
+reset_masks(struct gen_device_info *devinfo)
+{
+ devinfo->subslice_slice_stride = 0;
+ devinfo->eu_subslice_stride = 0;
+ devinfo->eu_slice_stride = 0;
+
+ devinfo->num_slices = 0;
+ devinfo->num_eu_per_subslice = 0;
+ memset(devinfo->num_subslices, 0, sizeof(devinfo->num_subslices));
+
+ memset(>slice_masks, 0, sizeof(devinfo->slice_masks));
+ memset(devinfo->subslice_masks, 0, sizeof(devinfo->subslice_masks));
+ memset(devinfo->eu_masks, 0, sizeof(devinfo->eu_masks));
+}
+
+void
+gen_device_info_update_from_topology(struct gen_device_info *devinfo,
+ const struct drm_i915_query_topology_info
*topology)
+{
+ reset_masks(devinfo);
+
+ devinfo->subslice_slice_stride = topology->subslice_stride;
+
+ devinfo->eu_subslice_stride = DIV_ROUND_UP(topology->max_eus_per_subslice,
8);
+ devinfo->eu_slice_stride = topology->max_subslices *
devinfo->eu_subsl
Mesa (master): i965/perf: fix config registration when uploading to kernel
Module: Mesa
Branch: master
Commit: 1603ce1921a511f128025a49d055283440376231
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1603ce1921a511f128025a49d055283440376231
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Thu Mar 22 16:02:11 2018 +
i965/perf: fix config registration when uploading to kernel
When registring configurations to the kernel for the first time, we
run into an issue where the id number is not properly set (we're using
the wrong variable). As a result when trying to use that id later on,
we get an error.
This issue manifest itself the first time you use frameretrace after
reboot, subsequent runs are fine.
Fixes: 27ee83eaf7e9 ("i965: perf: add support for userspace configurations")
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 0d0fb94537..12f797c129 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1905,7 +1905,7 @@ init_oa_configs(struct brw_context *brw)
continue;
}
- register_oa_config(brw, query, config_id);
+ register_oa_config(brw, query, ret);
DBG("metric set: %s (added)\n", query->guid);
}
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: fix out of tree autotools build
Module: Mesa
Branch: master
Commit: 5770e1d89e0eb49eb3c9547e8657d636b6e7e5d7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5770e1d89e0eb49eb3c9547e8657d636b6e7e5d7
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue Mar 20 18:31:53 2018 +
i965: fix out of tree autotools build
Fixes: 2d2b15fbcab ("i965: fix autotools/android build")
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>
Reviewed-by: Mathias Fröhlich <mathias.froehl...@web.de>
---
src/mesa/drivers/dri/i965/Makefile.am | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/Makefile.am
b/src/mesa/drivers/dri/i965/Makefile.am
index fe106b4257..889d4c68a2 100644
--- a/src/mesa/drivers/dri/i965/Makefile.am
+++ b/src/mesa/drivers/dri/i965/Makefile.am
@@ -115,6 +115,9 @@ EXTRA_DIST = \
meson.build
brw_oa_metrics.c: brw_oa.py $(i965_oa_xml_FILES)
- $(PYTHON2) $(PYTHON_FLAGS) $(srcdir)/brw_oa.py
--code=$(builddir)/brw_oa_metrics.c --header=$(builddir)/brw_oa_metrics.h
$(i965_oa_xml_FILES)
+ $(PYTHON2) $(PYTHON_FLAGS) $(srcdir)/brw_oa.py \
+ --code=$(builddir)/brw_oa_metrics.c \
+ --header=$(builddir)/brw_oa_metrics.h \
+ $(i965_oa_xml_FILES:%=$(srcdir)/%)
brw_oa_metrics.h: brw_oa_metrics.c
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: pipecontrol: add LRI write immediate flag
Module: Mesa Branch: master Commit: d3e5d3955c1232aa405cf9ac3af65d4d377fd81a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d3e5d3955c1232aa405cf9ac3af65d4d377fd81a Author: Lionel Landwerlin <lionel.g.landwer...@intel.com> Date: Thu Mar 15 12:11:15 2018 + i965: pipecontrol: add LRI write immediate flag Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/brw_pipe_control.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.h b/src/mesa/drivers/dri/i965/brw_pipe_control.h index 651cd4d3e7..4c58e16660 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.h +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.h @@ -34,6 +34,7 @@ struct brw_bo; * additional flushing control. */ #define _3DSTATE_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24)) +#define PIPE_CONTROL_LRI_WRITE_IMMEDIATE (1 << 23) /* Gen7+ */ #define PIPE_CONTROL_CS_STALL (1 << 20) #define PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET (1 << 19) #define PIPE_CONTROL_TLB_INVALIDATE(1 << 18) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: genxml: add INSTPM/CS_DEBUG_MODE2 registers
Module: Mesa Branch: master Commit: 7f977d51b3cb27723dc0fd6395262568c89a87ab URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f977d51b3cb27723dc0fd6395262568c89a87ab Author: Lionel Landwerlin <lionel.g.landwer...@intel.com> Date: Fri Mar 2 16:44:14 2018 + intel: genxml: add INSTPM/CS_DEBUG_MODE2 registers Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/intel/genxml/gen10.xml | 6 ++ src/intel/genxml/gen11.xml | 6 ++ src/intel/genxml/gen6.xml | 7 +++ src/intel/genxml/gen7.xml | 7 +++ src/intel/genxml/gen75.xml | 7 +++ src/intel/genxml/gen8.xml | 7 +++ src/intel/genxml/gen9.xml | 6 ++ 7 files changed, 46 insertions(+) diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml index 2d36957c2a..cc696e800d 100644 --- a/src/intel/genxml/gen10.xml +++ b/src/intel/genxml/gen10.xml @@ -3541,4 +3541,10 @@ + + + + + + diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml index a93b62aa4c..417fac1365 100644 --- a/src/intel/genxml/gen11.xml +++ b/src/intel/genxml/gen11.xml @@ -3537,4 +3537,10 @@ + + + + + + diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml index 088f46f05f..08779733db 100644 --- a/src/intel/genxml/gen6.xml +++ b/src/intel/genxml/gen6.xml @@ -1963,4 +1963,11 @@ + + + + + + + diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml index 430c2ba73a..87e05c94ef 100644 --- a/src/intel/genxml/gen7.xml +++ b/src/intel/genxml/gen7.xml @@ -2551,4 +2551,11 @@ + + + + + + + diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml index e18a49ac4d..68aff857f3 100644 --- a/src/intel/genxml/gen75.xml +++ b/src/intel/genxml/gen75.xml @@ -3062,4 +3062,11 @@ + + + + + + + diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml index c0e837906c..8a4bf34cf7 100644 --- a/src/intel/genxml/gen8.xml +++ b/src/intel/genxml/gen8.xml @@ -3294,4 +3294,11 @@ + + + + + + + diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml index faee2acca1..cfae4a8b65 100644 --- a/src/intel/genxml/gen9.xml +++ b/src/intel/genxml/gen9.xml @@ -3622,4 +3622,10 @@ + + + + + + ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: fix autotools/android build
Module: Mesa
Branch: master
Commit: 2d2b15fbcab08d7844c15351919cd469cd9e11c4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d2b15fbcab08d7844c15351919cd469cd9e11c4
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue Mar 20 14:59:57 2018 +
i965: fix autotools/android build
Autotools/android builds generate the header & code files in 2 steps,
but the code generation requires the name of the header file to
include it.
This change generates both files in one command.
Fixes: 035cc7a12dc ("i965: perf: reduce i965 binary size")
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>
---
src/mesa/drivers/dri/i965/Android.mk | 9 +++--
src/mesa/drivers/dri/i965/Makefile.am | 10 +++---
2 files changed, 6 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/Android.mk
b/src/mesa/drivers/dri/i965/Android.mk
index a3d010a589..8c4a613bcf 100644
--- a/src/mesa/drivers/dri/i965/Android.mk
+++ b/src/mesa/drivers/dri/i965/Android.mk
@@ -312,15 +312,12 @@ LOCAL_GENERATED_SOURCES += $(addprefix $(intermediates)/,
\
i965_oa_xml_FILES := $(addprefix $(LOCAL_PATH)/, \
$(i965_oa_xml_FILES))
-$(intermediates)/brw_oa_metrics.h: $(LOCAL_PATH)/brw_oa.py $(i965_oa_xml_FILES)
- @echo "target Generated: $(PRIVATE_MODULE) <= $(notdir $(@))"
- @mkdir -p $(dir $@)
- $(hide) $(MESA_PYTHON2) $< --header=$@ $(i965_oa_xml_FILES)
-
$(intermediates)/brw_oa_metrics.c: $(LOCAL_PATH)/brw_oa.py $(i965_oa_xml_FILES)
@echo "target Generated: $(PRIVATE_MODULE) <= $(notdir $(@))"
@mkdir -p $(dir $@)
- $(hide) $(MESA_PYTHON2) $< --code=$@ $(i965_oa_xml_FILES)
+ $(hide) $(MESA_PYTHON2) $< --code=$@ $(i965_oa_xml_FILES) --header=$@
$(i965_oa_xml_FILES)
+
+$(intermediates)/brw_oa_metrics.h: $(intermediates)/brw_oa_metrics.c
include $(MESA_COMMON_MK)
include $(BUILD_SHARED_LIBRARY)
diff --git a/src/mesa/drivers/dri/i965/Makefile.am
b/src/mesa/drivers/dri/i965/Makefile.am
index 8c8ecc6d76..fe106b4257 100644
--- a/src/mesa/drivers/dri/i965/Makefile.am
+++ b/src/mesa/drivers/dri/i965/Makefile.am
@@ -114,11 +114,7 @@ EXTRA_DIST = \
$(i965_oa_xml_FILES) \
meson.build
-# Note: we avoid using a multi target rule here and outputting both the
-# .c and .h files in one go so we don't hit problems with parallel
-# make and multiple invocations of the same script trying to write
-# to the same files.
-brw_oa_metrics.h: brw_oa.py $(i965_oa_xml_FILES)
- $(PYTHON2) $(PYTHON_FLAGS) $(srcdir)/brw_oa.py
--header=$(builddir)/brw_oa_metrics.h $(i965_oa_xml_FILES)
brw_oa_metrics.c: brw_oa.py $(i965_oa_xml_FILES)
- $(PYTHON2) $(PYTHON_FLAGS) $(srcdir)/brw_oa.py
--code=$(builddir)/brw_oa_metrics.c $(i965_oa_xml_FILES)
+ $(PYTHON2) $(PYTHON_FLAGS) $(srcdir)/brw_oa.py
--code=$(builddir)/brw_oa_metrics.c --header=$(builddir)/brw_oa_metrics.h
$(i965_oa_xml_FILES)
+
+brw_oa_metrics.h: brw_oa_metrics.c
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: perf: reduce i965 binary size
Module: Mesa Branch: master Commit: 035cc7a12dc03ef8b8184f75b880ae41e452b215 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=035cc7a12dc03ef8b8184f75b880ae41e452b215 Author: Lionel Landwerlin <lionel.g.landwer...@intel.com> Date: Tue Mar 13 11:21:17 2018 + i965: perf: reduce i965 binary size Performance metric numbers are calculated the following way : - out of the 256 bytes long OA reports, we accumulate the deltas into an array of uint64_t - the equations' generated code reads the accumulated uint64_t deltas and normalizes them for a particular platform Our hardware is such that a number of counters in the OA reports always return the same values (i.e. they're not programmable), and they return the same values even across generations, and as a result a number of equations are identical in different metric sets across different generations. Up to now we've kept the generated code of the equations separated in different files (per generation/GT), and didn't apply any factorization of the common equations. We could have make some improvement by reusing equations within a given metrics file, but we can go even further and reuse across generations (i.e. all files). This change changes the code generation to emit a single file in which we reuse equations emitted code based on the hash of equations' strings. Here are the savings in a meson build : Before(.old)/after : $ du -h ./build/src/mesa/drivers/dri/libmesa_dri_drivers.so ./build/src/mesa/drivers/dri/libmesa_dri_drivers.so.old 43M ./build/src/mesa/drivers/dri/libmesa_dri_drivers.so 47M ./build/src/mesa/drivers/dri/libmesa_dri_drivers.so.old $ size build/src/mesa/drivers/dri/libmesa_dri_drivers.so build/src/mesa/drivers/dri/libmesa_dri_drivers.so.old text data bss dechex filename 13054002 409424 671856 14135282 d7aff2 build/src/mesa/drivers/dri/libmesa_dri_drivers.so 14550386 409552 671856 15631794 ee85b2 build/src/mesa/drivers/dri/libmesa_dri_drivers.so.old As a side comment here is the size of the drivers if we remove all of the metrics from the build : $ du -sh build/src/mesa/drivers/dri/libmesa_dri_drivers.so 40M build/src/mesa/drivers/dri/libmesa_dri_drivers.so v2: Fix an issue with hashing of counter equations (Lionel) Build system rework (Emil) Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Reviewed-by: Emil Velikov <emil.veli...@collabora.com> (build system part) Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/Android.mk | 11 +- src/mesa/drivers/dri/i965/Makefile.am | 21 +- src/mesa/drivers/dri/i965/Makefile.sources| 40 +- src/mesa/drivers/dri/i965/brw_oa.py | 433 ++ src/mesa/drivers/dri/i965/brw_performance_query.c | 13 +- src/mesa/drivers/dri/i965/meson.build | 37 +- 6 files changed, 334 insertions(+), 221 deletions(-) diff --git a/src/mesa/drivers/dri/i965/Android.mk b/src/mesa/drivers/dri/i965/Android.mk index 964313e6c5..a3d010a589 100644 --- a/src/mesa/drivers/dri/i965/Android.mk +++ b/src/mesa/drivers/dri/i965/Android.mk @@ -309,15 +309,18 @@ intermediates := $(call local-generated-sources-dir) LOCAL_GENERATED_SOURCES += $(addprefix $(intermediates)/, \ $(i965_oa_GENERATED_FILES)) -$(intermediates)/brw_oa_%.h: $(LOCAL_PATH)/brw_oa_%.xml $(LOCAL_PATH)/brw_oa.py +i965_oa_xml_FILES := $(addprefix $(LOCAL_PATH)/, \ + $(i965_oa_xml_FILES)) + +$(intermediates)/brw_oa_metrics.h: $(LOCAL_PATH)/brw_oa.py $(i965_oa_xml_FILES) @echo "target Generated: $(PRIVATE_MODULE) <= $(notdir $(@))" @mkdir -p $(dir $@) - $(hide) $(MESA_PYTHON2) $(word 2, $^) --header=$@ --chipset=$(basename $*) $< + $(hide) $(MESA_PYTHON2) $< --header=$@ $(i965_oa_xml_FILES) -$(intermediates)/brw_oa_%.c: $(LOCAL_PATH)/brw_oa_%.xml $(LOCAL_PATH)/brw_oa.py +$(intermediates)/brw_oa_metrics.c: $(LOCAL_PATH)/brw_oa.py $(i965_oa_xml_FILES) @echo "target Generated: $(PRIVATE_MODULE) <= $(notdir $(@))" @mkdir -p $(dir $@) - $(hide) $(MESA_PYTHON2) $(word 2, $^) --code=$@ --chipset=$(basename $*) $< + $(hide) $(MESA_PYTHON2) $< --code=$@ $(i965_oa_xml_FILES) include $(MESA_COMMON_MK) include $(BUILD_SHARED_LIBRARY) diff --git a/src/mesa/drivers/dri/i965/Makefile.am b/src/mesa/drivers/dri/i965/Makefile.am index 824882389e..8c8ecc6d76 100644 --- a/src/mesa/drivers/dri/i965/Makefile.am +++ b/src/mesa/drivers/dri/i965/Makefile.am @@ -110,26 +110,15 @@ BUILT_SOURCES = $(i965_oa_GENERATED_FILES) CLEANFILES = $(BUILT_SOURCES) EXTRA_DIST = \ - brw_oa_hsw.xml \ - brw_oa_bdw.xml \ - brw_oa_chv.xml \ - brw_oa_sklgt2.xml \ - brw_oa_sklgt3.xml \ - brw_oa_sklgt4.xml \ - brw_oa_bxt.xml \ - brw_oa_kblgt2.xml \ - brw_
Mesa (master): i965: perf: fix a counter return type on hsw
Module: Mesa Branch: master Commit: e9a9e859486104ff9326cbc424480e53dc4e81ba URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9a9e859486104ff9326cbc424480e53dc4e81ba Author: Lionel Landwerlin <lionel.g.landwer...@intel.com> Date: Tue Mar 13 11:45:12 2018 + i965: perf: fix a counter return type on hsw The equation code computes a float (percentage) yet the return type was an uint64_t. Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/brw_oa_hsw.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_oa_hsw.xml b/src/mesa/drivers/dri/i965/brw_oa_hsw.xml index ebc2bd7914..861cc1212a 100644 --- a/src/mesa/drivers/dri/i965/brw_oa_hsw.xml +++ b/src/mesa/drivers/dri/i965/brw_oa_hsw.xml @@ -1669,7 +1669,7 @@ /> https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv/pipeline: fail if TCS/TES compile fail
Module: Mesa
Branch: master
Commit: 318073ce660ca72b47ba83e37d1d0bc756f779b7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=318073ce660ca72b47ba83e37d1d0bc756f779b7
Author: Caio Marcelo de Oliveira Filho <caio.olive...@intel.com>
Date: Thu Mar 15 13:09:29 2018 -0700
anv/pipeline: fail if TCS/TES compile fail
v2: Add Fixes tag. (Lionel)
Fixes: e50d4807a35e679 ("anv: Compile TCS/TES shaders.")
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
src/intel/vulkan/anv_pipeline.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 9cfd16df2a..cb34f3be77 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -1349,13 +1349,15 @@ anv_pipeline_init(struct anv_pipeline *pipeline,
}
if (modules[MESA_SHADER_TESS_EVAL]) {
- anv_pipeline_compile_tcs_tes(pipeline, cache, pCreateInfo,
- modules[MESA_SHADER_TESS_CTRL],
- pStages[MESA_SHADER_TESS_CTRL]->pName,
-
pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
- modules[MESA_SHADER_TESS_EVAL],
- pStages[MESA_SHADER_TESS_EVAL]->pName,
-
pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo);
+ result = anv_pipeline_compile_tcs_tes(pipeline, cache, pCreateInfo,
+modules[MESA_SHADER_TESS_CTRL],
+
pStages[MESA_SHADER_TESS_CTRL]->pName,
+
pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
+modules[MESA_SHADER_TESS_EVAL],
+
pStages[MESA_SHADER_TESS_EVAL]->pName,
+
pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo);
+ if (result != VK_SUCCESS)
+ goto compile_fail;
}
if (modules[MESA_SHADER_GEOMETRY]) {
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv/pipeline: set active_stages early
Module: Mesa
Branch: master
Commit: f6338c3b856711d6a399b7f6dccbf3a7062b4586
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f6338c3b856711d6a399b7f6dccbf3a7062b4586
Author: Caio Marcelo de Oliveira Filho <caio.olive...@intel.com>
Date: Thu Mar 15 13:09:30 2018 -0700
anv/pipeline: set active_stages early
Since the intermediate states of active_stages are not used,
i.e. active_stages is read only after all stages were set into it,
just set its value before compiling the shaders.
This will allow to conditionally run certain passes based on what
other shaders are being used, e.g. a certain pass might only be
applicable to the vertex shader if there's no geometry or tessellation
shader being used.
v2: Use vk_to_mesa_shader_stage. (Lionel)
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
src/intel/vulkan/anv_pipeline.c | 12 +---
src/intel/vulkan/genX_pipeline.c | 1 +
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index cb34f3be77..4ca1e0be34 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -501,7 +501,6 @@ anv_pipeline_add_compiled_stage(struct anv_pipeline
*pipeline,
struct anv_shader_bin *shader)
{
pipeline->shaders[stage] = shader;
- pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
}
static VkResult
@@ -1334,11 +1333,18 @@ anv_pipeline_init(struct anv_pipeline *pipeline,
const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = {};
struct anv_shader_module *modules[MESA_SHADER_STAGES] = {};
for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
- gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
+ VkShaderStageFlagBits vk_stage = pCreateInfo->pStages[i].stage;
+ gl_shader_stage stage = vk_to_mesa_shader_stage(vk_stage);
pStages[stage] = >pStages[i];
modules[stage] = anv_shader_module_from_handle(pStages[stage]->module);
+ pipeline->active_stages |= vk_stage;
}
+ if (pipeline->active_stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT)
+ pipeline->active_stages |= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT;
+
+ assert(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT);
+
if (modules[MESA_SHADER_VERTEX]) {
result = anv_pipeline_compile_vs(pipeline, cache, pCreateInfo,
modules[MESA_SHADER_VERTEX],
@@ -1378,7 +1384,7 @@ anv_pipeline_init(struct anv_pipeline *pipeline,
goto compile_fail;
}
- assert(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT);
+ assert(pipeline->shaders[MESA_SHADER_VERTEX]);
anv_pipeline_setup_l3_config(pipeline, false);
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 9c08bc2033..eb2d414735 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1787,6 +1787,7 @@ compute_pipeline_create(
pipeline->needs_data_cache = false;
assert(pCreateInfo->stage.stage == VK_SHADER_STAGE_COMPUTE_BIT);
+ pipeline->active_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
ANV_FROM_HANDLE(anv_shader_module, module, pCreateInfo->stage.module);
result = anv_pipeline_compile_cs(pipeline, cache, pCreateInfo, module,
pCreateInfo->stage.pName,
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv: silence unused function warning on gen11
Module: Mesa
Branch: master
Commit: 0f544a3c51a9dd0e229cc953a2ddb87c14c6d51b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0f544a3c51a9dd0e229cc953a2ddb87c14c6d51b
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Thu Mar 15 16:14:34 2018 +
anv: silence unused function warning on gen11
[84/227] Compiling C object
'src/intel/vulkan/libanv_gen110@sta/genX_blorp_exec.c.o'.
../src/intel/vulkan/genX_blorp_exec.c:68:1: warning:
‘blorp_get_surface_base_address’ defined but not used [-Wunused-function]
blorp_get_surface_base_address(struct blorp_batch *batch)
^~
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
src/intel/blorp/blorp_genX_exec.h | 2 +-
src/intel/vulkan/genX_blorp_exec.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/intel/blorp/blorp_genX_exec.h
b/src/intel/blorp/blorp_genX_exec.h
index 1348659233..b612709035 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -78,7 +78,7 @@ static void
blorp_surface_reloc(struct blorp_batch *batch, uint32_t ss_offset,
struct blorp_address address, uint32_t delta);
-#if GEN_GEN >= 7
+#if GEN_GEN >= 7 && GEN_GEN <= 10
static struct blorp_address
blorp_get_surface_base_address(struct blorp_batch *batch);
#endif
diff --git a/src/intel/vulkan/genX_blorp_exec.c
b/src/intel/vulkan/genX_blorp_exec.c
index ac6e736664..1ecec19984 100644
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -64,6 +64,7 @@ blorp_surface_reloc(struct blorp_batch *batch, uint32_t
ss_offset,
anv_batch_set_error(_buffer->batch, result);
}
+#if GEN_GEN >= 7 && GEN_GEN <= 10
static struct blorp_address
blorp_get_surface_base_address(struct blorp_batch *batch)
{
@@ -73,6 +74,7 @@ blorp_get_surface_base_address(struct blorp_batch *batch)
.offset = 0,
};
}
+#endif
static void *
blorp_alloc_dynamic_state(struct blorp_batch *batch,
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv: silence unused variable warning
Module: Mesa
Branch: master
Commit: 51783f3e7d720d4348a664c2aa61c57d2324b0e2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=51783f3e7d720d4348a664c2aa61c57d2324b0e2
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Thu Mar 15 16:34:47 2018 +
anv: silence unused variable warning
Fixes: 59b0ea0c748 ("anv: Stop returning VK_ERROR_INCOMPATIBLE_DRIVER")
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
src/intel/vulkan/anv_device.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index d8c4e98631..82b237e76d 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -514,13 +514,6 @@ VkResult anv_CreateInstance(
assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
- /* Check if user passed a debug report callback to be used during
-* Create/Destroy of instance.
-*/
- const VkDebugReportCallbackCreateInfoEXT *ctor_cb =
- vk_find_struct_const(pCreateInfo->pNext,
- DEBUG_REPORT_CALLBACK_CREATE_INFO_EXT);
-
struct anv_instance_extension_table enabled_extensions = {};
for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
int idx;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: silence unused function warning
Module: Mesa
Branch: master
Commit: b5b56f91f533fd9df846f401f6626ba52a1adeda
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5b56f91f533fd9df846f401f6626ba52a1adeda
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Thu Mar 15 16:15:06 2018 +
i965: silence unused function warning
[123/227] Compiling C object
'src/mesa/drivers/dri/i965/libi965_gen110@sta/genX_blorp_exec.c.o'.
../src/mesa/drivers/dri/i965/genX_blorp_exec.c:99:1: warning:
‘blorp_get_surface_base_address’ defined but not used [-Wunused-function]
blorp_get_surface_base_address(struct blorp_batch *batch)
^~
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 53069e6fe2..3406a6fdec 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -94,7 +94,7 @@ blorp_surface_reloc(struct blorp_batch *batch, uint32_t
ss_offset,
#endif
}
-#if GEN_GEN >= 7
+#if GEN_GEN >= 7 && GEN_GEN <= 10
static struct blorp_address
blorp_get_surface_base_address(struct blorp_batch *batch)
{
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: perf: count number of accumlated reports
Module: Mesa
Branch: master
Commit: fb921a2870ae51cdad129438dfb1b20f1538b2fa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb921a2870ae51cdad129438dfb1b20f1538b2fa
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue Mar 6 17:11:56 2018 +
i965: perf: count number of accumlated reports
This will be reused later.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index d0faf4a2cb..71ea26753e 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -290,6 +290,10 @@ struct brw_perf_query_object
*/
bool results_accumulated;
+ /**
+ * Number of reports accumulated to produce the results.
+ */
+ uint32_t reports_accumulated;
} oa;
struct {
@@ -658,6 +662,8 @@ add_deltas(struct brw_context *brw,
int idx = 0;
int i;
+ obj->oa.reports_accumulated++;
+
switch (query->oa_format) {
case I915_OA_FORMAT_A32u40_A4u32_B8_C8:
accumulate_uint32(start + 1, end + 1, accumulator + idx++); /* timestamp
*/
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: perf: consolidate unmapping oa perf bo outside accumulation
Module: Mesa
Branch: master
Commit: d10a39ebe085dc28ab7352f76b57d628928e1e40
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d10a39ebe085dc28ab7352f76b57d628928e1e40
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed Mar 7 14:10:15 2018 +
i965: perf: consolidate unmapping oa perf bo outside accumulation
Do this in one place outside the only caller of the accumulation
function.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 71ea26753e..13eff31ee6 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1014,8 +1014,6 @@ end:
DBG("Marking %d accumulated - results gathered\n", o->Id);
- brw_bo_unmap(obj->oa.bo);
- obj->oa.map = NULL;
obj->oa.results_accumulated = true;
drop_from_unaccumulated_query_list(brw, obj);
dec_n_oa_users(brw);
@@ -1024,8 +1022,6 @@ end:
error:
- brw_bo_unmap(obj->oa.bo);
- obj->oa.map = NULL;
discard_all_queries(brw);
}
@@ -1470,6 +1466,9 @@ get_oa_counter_data(struct brw_context *brw,
if (!obj->oa.results_accumulated) {
accumulate_oa_reports(brw, obj);
assert(obj->oa.results_accumulated);
+
+ brw_bo_unmap(obj->oa.bo);
+ obj->oa.map = NULL;
}
for (int i = 0; i < n_counters; i++) {
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: perf: store sysfs device entry into context
Module: Mesa
Branch: master
Commit: b71da26496cad8179fce93e5b114bef2cddce987
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b71da26496cad8179fce93e5b114bef2cddce987
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed Feb 7 18:09:58 2018 +
i965: perf: store sysfs device entry into context
We want to reuse it later on.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_context.h | 3 +
src/mesa/drivers/dri/i965/brw_performance_query.c | 146 +++---
2 files changed, 73 insertions(+), 76 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index d6e3c7807f..d3e7c71207 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1189,6 +1189,9 @@ struct brw_context
*/
struct hash_table *oa_metrics_table;
+ /* Location of the device's sysfs entry. */
+ char sysfs_dev_dir[256];
+
struct brw_perf_query_info *queries;
int n_queries;
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 622c2d2d95..a084b30fe7 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -319,6 +319,47 @@ brw_perf_query(struct gl_perf_query_object *o)
/**/
static bool
+read_file_uint64(const char *file, uint64_t *val)
+{
+char buf[32];
+int fd, n;
+
+fd = open(file, 0);
+if (fd < 0)
+ return false;
+while ((n = read(fd, buf, sizeof (buf) - 1)) < 0 &&
+ errno == EINTR);
+close(fd);
+if (n < 0)
+ return false;
+
+buf[n] = '\0';
+*val = strtoull(buf, NULL, 0);
+
+return true;
+}
+
+static bool
+read_sysfs_drm_device_file_uint64(struct brw_context *brw,
+ const char *file,
+ uint64_t *value)
+{
+ char buf[512];
+ int len;
+
+ len = snprintf(buf, sizeof(buf), "%s/%s",
+ brw->perfquery.sysfs_dev_dir, file);
+ if (len < 0 || len >= sizeof(buf)) {
+ DBG("Failed to concatenate sys filename to read u64 from\n");
+ return false;
+ }
+
+ return read_file_uint64(buf, value);
+}
+
+/**/
+
+static bool
brw_is_perf_query_ready(struct gl_context *ctx,
struct gl_perf_query_object *o);
@@ -1746,27 +1787,6 @@ init_pipeline_statistic_query_registers(struct
brw_context *brw)
query->data_size = sizeof(uint64_t) * query->n_counters;
}
-static bool
-read_file_uint64(const char *file, uint64_t *val)
-{
-char buf[32];
-int fd, n;
-
-fd = open(file, 0);
-if (fd < 0)
- return false;
-while ((n = read(fd, buf, sizeof (buf) - 1)) < 0 &&
- errno == EINTR);
-close(fd);
-if (n < 0)
- return false;
-
-buf[n] = '\0';
-*val = strtoull(buf, NULL, 0);
-
-return true;
-}
-
static void
register_oa_config(struct brw_context *brw,
const struct brw_perf_query_info *query,
@@ -1780,14 +1800,14 @@ register_oa_config(struct brw_context *brw,
}
static void
-enumerate_sysfs_metrics(struct brw_context *brw, const char *sysfs_dev_dir)
+enumerate_sysfs_metrics(struct brw_context *brw)
{
char buf[256];
DIR *metricsdir = NULL;
struct dirent *metric_entry;
int len;
- len = snprintf(buf, sizeof(buf), "%s/metrics", sysfs_dev_dir);
+ len = snprintf(buf, sizeof(buf), "%s/metrics",
brw->perfquery.sysfs_dev_dir);
if (len < 0 || len >= sizeof(buf)) {
DBG("Failed to concatenate path to sysfs metrics/ directory\n");
return;
@@ -1814,7 +1834,7 @@ enumerate_sysfs_metrics(struct brw_context *brw, const
char *sysfs_dev_dir)
uint64_t id;
len = snprintf(buf, sizeof(buf), "%s/metrics/%s/id",
-sysfs_dev_dir, metric_entry->d_name);
+brw->perfquery.sysfs_dev_dir, metric_entry->d_name);
if (len < 0 || len >= sizeof(buf)) {
DBG("Failed to concatenate path to sysfs metric id file\n");
continue;
@@ -1834,37 +1854,18 @@ enumerate_sysfs_metrics(struct brw_context *brw, const
char *sysfs_dev_dir)
}
static bool
-read_sysfs_drm_device_file_uint64(struct brw_context *brw,
- const char *sysfs_dev_dir,
- const char *file,
- uint64_t *value)
-{
- char buf[512];
- int len;
-
- len
Mesa (master): i965: perf: default case for unknown query types
Module: Mesa
Branch: master
Commit: 80cd669a320fa0666d50f8427980401136f8f667
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=80cd669a320fa0666d50f8427980401136f8f667
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue Feb 6 17:29:32 2018 +
i965: perf: default case for unknown query types
Just some extra safety before further changes.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 32 ++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 613e61653f..8cb9d8277a 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -341,6 +341,9 @@ dump_perf_query_callback(GLuint id, void *query_void, void
*brw_void)
o->Active ? "Active," : (o->Ready ? "Ready," : "Pending,"),
obj->pipeline_stats.bo ? "yes" : "no");
break;
+ default:
+ unreachable("Unknown query type");
+ break;
}
}
@@ -437,6 +440,10 @@ brw_get_perf_query_info(struct gl_context *ctx,
case PIPELINE_STATS:
*n_active = brw->perfquery.n_active_pipeline_stats_queries;
break;
+
+ default:
+ unreachable("Unknown query type");
+ break;
}
}
@@ -1265,6 +1272,10 @@ brw_begin_perf_query(struct gl_context *ctx,
++brw->perfquery.n_active_pipeline_stats_queries;
break;
+
+ default:
+ unreachable("Unknown query type");
+ break;
}
if (INTEL_DEBUG & DEBUG_PERFMON)
@@ -1321,6 +1332,10 @@ brw_end_perf_query(struct gl_context *ctx,
STATS_BO_END_OFFSET_BYTES);
--brw->perfquery.n_active_pipeline_stats_queries;
break;
+
+ default:
+ unreachable("Unknown query type");
+ break;
}
}
@@ -1341,6 +1356,10 @@ brw_wait_perf_query(struct gl_context *ctx, struct
gl_perf_query_object *o)
case PIPELINE_STATS:
bo = obj->pipeline_stats.bo;
break;
+
+ default:
+ unreachable("Unknown query type");
+ break;
}
if (bo == NULL)
@@ -1386,9 +1405,12 @@ brw_is_perf_query_ready(struct gl_context *ctx,
return (obj->pipeline_stats.bo &&
!brw_batch_references(>batch, obj->pipeline_stats.bo) &&
!brw_bo_busy(obj->pipeline_stats.bo));
+
+ default:
+ unreachable("Unknown query type");
+ break;
}
- unreachable("missing ready check for unknown query kind");
return false;
}
@@ -1502,6 +1524,10 @@ brw_get_perf_query_data(struct gl_context *ctx,
case PIPELINE_STATS:
written = get_pipeline_stats_data(brw, obj, data_size, (uint8_t *)data);
break;
+
+ default:
+ unreachable("Unknown query type");
+ break;
}
if (bytes_written)
@@ -1567,6 +1593,10 @@ brw_delete_perf_query(struct gl_context *ctx,
obj->pipeline_stats.bo = NULL;
}
break;
+
+ default:
+ unreachable("Unknown query type");
+ break;
}
free(obj);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: perf: reuse timescale base function from query
Module: Mesa
Branch: master
Commit: e4387faafb1455b92d5e9620df9754cae1cd07e8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e4387faafb1455b92d5e9620df9754cae1cd07e8
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue Mar 6 15:47:00 2018 +
i965: perf: reuse timescale base function from query
We already have the same function in brw_queryobj.c
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index a084b30fe7..d0faf4a2cb 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -613,15 +613,6 @@ drop_from_unaccumulated_query_list(struct brw_context *brw,
reap_old_sample_buffers(brw);
}
-static uint64_t
-timebase_scale(struct brw_context *brw, uint32_t u32_time_delta)
-{
- const struct gen_device_info *devinfo = >screen->devinfo;
- uint64_t tmp = ((uint64_t)u32_time_delta) * 10ull;
-
- return tmp ? tmp / devinfo->timestamp_frequency : 0;
-}
-
static void
accumulate_uint32(const uint32_t *report0,
const uint32_t *report1,
@@ -943,13 +934,13 @@ accumulate_oa_reports(struct brw_context *brw,
/* Ignore reports that come before the start marker.
* (Note: takes care to allow overflow of 32bit timestamps)
*/
-if (timebase_scale(brw, report[1] - start[1]) > 50)
+if (brw_timebase_scale(brw, report[1] - start[1]) > 50)
continue;
/* Ignore reports that come after the end marker.
* (Note: takes care to allow overflow of 32bit timestamps)
*/
-if (timebase_scale(brw, report[1] - end[1]) <= 50)
+if (brw_timebase_scale(brw, report[1] - end[1]) <= 50)
goto end;
/* For Gen8+ since the counters continue while other
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: perf: store the hw_id of the context in the query
Module: Mesa
Branch: master
Commit: 5742b17da1f067aad592176e787abcb0bbfb0ebe
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5742b17da1f067aad592176e787abcb0bbfb0ebe
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed Feb 7 18:10:57 2018 +
i965: perf: store the hw_id of the context in the query
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 8cb9d8277a..622c2d2d95 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -279,6 +279,11 @@ struct brw_perf_query_object
uint64_t accumulator[MAX_OA_REPORT_COUNTERS];
/**
+ * Hw ID used by the context on which the query was running.
+ */
+ uint32_t hw_id;
+
+ /**
* false while in the unaccumulated_elements list, and set to
* true when the final, end MI_RPC snapshot has been
* accumulated.
@@ -844,7 +849,6 @@ accumulate_oa_reports(struct brw_context *brw,
uint32_t *end;
struct exec_node *first_samples_node;
bool in_ctx = true;
- uint32_t ctx_id;
int out_duration = 0;
assert(o->Ready);
@@ -862,7 +866,7 @@ accumulate_oa_reports(struct brw_context *brw,
goto error;
}
- ctx_id = start[2];
+ obj->oa.hw_id = start[2];
/* See if we have any periodic reports to accumulate too... */
@@ -917,11 +921,11 @@ accumulate_oa_reports(struct brw_context *brw,
* of OA counters while any other context is acctive.
*/
if (devinfo->gen >= 8) {
- if (in_ctx && report[2] != ctx_id) {
+ if (in_ctx && report[2] != obj->oa.hw_id) {
DBG("i915 perf: Switch AWAY (observed by ID change)\n");
in_ctx = false;
out_duration = 0;
- } else if (in_ctx == false && report[2] == ctx_id) {
+ } else if (in_ctx == false && report[2] == obj->oa.hw_id) {
DBG("i915 perf: Switch TO\n");
in_ctx = true;
@@ -938,10 +942,10 @@ accumulate_oa_reports(struct brw_context *brw,
if (out_duration >= 1)
add = false;
} else if (in_ctx) {
- assert(report[2] == ctx_id);
+ assert(report[2] == obj->oa.hw_id);
DBG("i915 perf: Continuation IN\n");
} else {
- assert(report[2] != ctx_id);
+ assert(report[2] != obj->oa.hw_id);
DBG("i915 perf: Continuation OUT\n");
add = false;
out_duration++;
@@ -1251,6 +1255,7 @@ brw_begin_perf_query(struct gl_context *ctx,
*/
buf->refcount++;
+ obj->oa.hw_id = 0x;
memset(obj->oa.accumulator, 0, sizeof(obj->oa.accumulator));
obj->oa.results_accumulated = false;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: aubinator_error_decode: fix segfault on missing register
Module: Mesa
Branch: master
Commit: fca9f5b5851d2eeba6d030e28dd783017fef55cf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fca9f5b5851d2eeba6d030e28dd783017fef55cf
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Thu Feb 22 13:41:10 2018 +
intel: aubinator_error_decode: fix segfault on missing register
Some register might be missing in our genxmls. Don't try to decode
them.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/intel/tools/aubinator_error_decode.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/intel/tools/aubinator_error_decode.c
b/src/intel/tools/aubinator_error_decode.c
index 2331114b44..017be5bbc2 100644
--- a/src/intel/tools/aubinator_error_decode.c
+++ b/src/intel/tools/aubinator_error_decode.c
@@ -65,7 +65,8 @@ print_head(unsigned int reg)
static void
print_register(struct gen_spec *spec, const char *name, uint32_t reg)
{
- struct gen_group *reg_spec = gen_spec_find_register_by_name(spec, name);
+ struct gen_group *reg_spec =
+ name ? gen_spec_find_register_by_name(spec, name) : NULL;
if (reg_spec) {
gen_print_group(stdout, reg_spec, 0, , 0,
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: perf: ensure reading config IDs from sysfs isn't interrupted
Module: Mesa Branch: master Commit: bd9672695b6b95085bb0af1d8eec9b550cdb01e6 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd9672695b6b95085bb0af1d8eec9b550cdb01e6 Author: Lionel Landwerlin <lionel.g.landwer...@intel.com> Date: Wed Feb 7 10:48:32 2018 + i965: perf: ensure reading config IDs from sysfs isn't interrupted Fixes: 458468c136e "i965: Expose OA counters via INTEL_performance_query" Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Cc: <mesa-sta...@lists.freedesktop.org> Reviewed-by: Eric Engestrom <eric.engest...@imgtec.com> --- src/mesa/drivers/dri/i965/brw_performance_query.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c b/src/mesa/drivers/dri/i965/brw_performance_query.c index c0bb4442be..613e61653f 100644 --- a/src/mesa/drivers/dri/i965/brw_performance_query.c +++ b/src/mesa/drivers/dri/i965/brw_performance_query.c @@ -1720,7 +1720,8 @@ read_file_uint64(const char *file, uint64_t *val) fd = open(file, 0); if (fd < 0) return false; -n = read(fd, buf, sizeof (buf) - 1); +while ((n = read(fd, buf, sizeof (buf) - 1)) < 0 && + errno == EINTR); close(fd); if (n < 0) return false; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: prevent potentially null pointer access
Module: Mesa
Branch: master
Commit: 712332ed54f14b5ee34c2990e351ca48992488b2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=712332ed54f14b5ee34c2990e351ca48992488b2
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Thu Feb 8 17:33:09 2018 +
i965: prevent potentially null pointer access
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Alejandro Piñeiro <apinhe...@igalia.com>
CID: 1418110
---
src/mesa/drivers/dri/i965/intel_screen.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index 1f866cf845..3f74ee78f3 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -315,7 +315,7 @@ modifier_is_supported(const struct gen_device_info *devinfo,
int i;
/* ISL had better know about the modifier */
- if (!modinfo)
+ if (!fmt || !modinfo)
return false;
if (modinfo->aux_usage == ISL_AUX_USAGE_CCS_E) {
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: perf: use drmIoctl() instead of ioctl()
Module: Mesa
Branch: master
Commit: bd6c0cab606fa0a3b821e50542ba06ff714292bf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd6c0cab606fa0a3b821e50542ba06ff714292bf
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue Feb 6 23:23:22 2018 +
i965: perf: use drmIoctl() instead of ioctl()
ioctl() might be interrupted, use drmIoctl() instead as it'll retry
automatically.
Fixes: 27ee83eaf7e "i965: perf: add support for userspace configurations"
Cc: "18.0" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>
Tested-by: Mark Janes <mark.a.ja...@intel.com>
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 5b8f30db2f..f4ff858bd5 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1842,7 +1842,7 @@ kernel_has_dynamic_config_support(struct brw_context *brw,
config.n_mux_regs = 1;
config.mux_regs_ptr = (uintptr_t) mux_regs;
- if (ioctl(screen->fd, DRM_IOCTL_I915_PERF_REMOVE_CONFIG, _id)
< 0 &&
+ if (drmIoctl(screen->fd, DRM_IOCTL_I915_PERF_REMOVE_CONFIG,
_id) < 0 &&
errno == ENOENT)
return true;
@@ -1889,7 +1889,7 @@ init_oa_configs(struct brw_context *brw, const char
*sysfs_dev_dir)
config.n_flex_regs = query->n_flex_regs;
config.flex_regs_ptr = (uintptr_t) query->flex_regs;
- ret = ioctl(screen->fd, DRM_IOCTL_I915_PERF_ADD_CONFIG, );
+ ret = drmIoctl(screen->fd, DRM_IOCTL_I915_PERF_ADD_CONFIG, );
if (ret < 0) {
DBG("Failed to load \"%s\" (%s) metrics set in kernel: %s\n",
query->name, query->guid, strerror(errno));
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: perf: cleanup detection of kernel support for loadable configs
Module: Mesa
Branch: master
Commit: e8436677339d65449bdabefd3ed8bb5a65f13d46
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e8436677339d65449bdabefd3ed8bb5a65f13d46
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue Feb 6 23:28:24 2018 +
i965: perf: cleanup detection of kernel support for loadable configs
The initial revision of the patch adding loadable configs was testing
the feature's availability by adding a new config successfully and
then removing it.
A second version tested the availability just by exercising the
removal. But some unused code remained.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 17 ++---
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index f4ff858bd5..c0bb4442be 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1832,21 +1832,8 @@ kernel_has_dynamic_config_support(struct brw_context
*brw,
/* Look for the test config, which we know we can't replace. */
if (read_file_uint64(config_path, _id) && config_id == 1) {
- uint32_t mux_regs[] = { 0x9888 /* NOA_WRITE */, 0x0 };
- struct drm_i915_perf_oa_config config;
-
- memset(, 0, sizeof(config));
-
- memcpy(config.uuid, query->guid, sizeof(config.uuid));
-
- config.n_mux_regs = 1;
- config.mux_regs_ptr = (uintptr_t) mux_regs;
-
- if (drmIoctl(screen->fd, DRM_IOCTL_I915_PERF_REMOVE_CONFIG,
_id) < 0 &&
- errno == ENOENT)
-return true;
-
- break;
+ return drmIoctl(screen->fd, DRM_IOCTL_I915_PERF_REMOVE_CONFIG,
+ _id) < 0 && errno == ENOENT;
}
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv: query CS timestamp frequency from the kernel
Module: Mesa
Branch: master
Commit: 2ead8f1690823bbb1acb8102bb6ceee26e8574b1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ead8f1690823bbb1acb8102bb6ceee26e8574b1
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Mon Dec 4 15:22:12 2017 +
anv: query CS timestamp frequency from the kernel
The reference value in gen_device_info isn't going to be acurate on
Gen10+. We should query it from the kernel, which reads a couple of
register to compute the actual value.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
src/intel/vulkan/anv_device.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 258668fa0b..97124154b6 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -371,6 +371,19 @@ anv_physical_device_init(struct anv_physical_device
*device,
bool swizzled = anv_gem_get_bit6_swizzle(fd, I915_TILING_X);
+ /* Starting with Gen10, the timestamp frequency of the command streamer may
+* vary from one part to another. We can query the value from the kernel.
+*/
+ if (device->info.gen >= 10) {
+ int timestamp_frequency =
+ anv_gem_get_param(fd, I915_PARAM_CS_TIMESTAMP_FREQUENCY);
+
+ if (timestamp_frequency < 0)
+ intel_logw("Kernel 4.16-rc1+ required to properly query CS timestamp
frequency");
+ else
+ device->info.timestamp_frequency = timestamp_frequency;
+ }
+
/* GENs prior to 8 do not support EU/Subslice info */
if (device->info.gen >= 8) {
device->subslice_total = anv_gem_get_param(fd,
I915_PARAM_SUBSLICE_TOTAL);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): drm-uapi: Update drm/i915 headers from drm-next
Module: Mesa
Branch: master
Commit: aa8a2a867056a93467623efbca950b51e592e67d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aa8a2a867056a93467623efbca950b51e592e67d
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Mon Dec 4 15:12:40 2017 +
drm-uapi: Update drm/i915 headers from drm-next
Taken from drm-next ca797d29cd63e7b71b4eea29aff3b1cefd1ecb59
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
include/drm-uapi/README | 8 +++---
include/drm-uapi/drm.h | 41 ++
include/drm-uapi/drm_mode.h | 70 +++--
include/drm-uapi/i915_drm.h | 38
4 files changed, 151 insertions(+), 6 deletions(-)
diff --git a/include/drm-uapi/README b/include/drm-uapi/README
index 27de91cad0..53dd711dad 100644
--- a/include/drm-uapi/README
+++ b/include/drm-uapi/README
@@ -13,9 +13,9 @@ $ make headers_install INSTALL_HDR_PATH=/path/to/install
The last update was done at the following kernel commit :
-commit 7846b12fe0b5feab5446d892f41b5140c1419109
-Merge: 7ebdb0d d78acfe
+commit ca797d29cd63e7b71b4eea29aff3b1cefd1ecb59
+Merge: 2c1c55cb75a9 010d118c2061
Author: Dave Airlie <airl...@redhat.com>
-Date: Tue Aug 29 10:38:14 2017 +1000
+Date: Mon Dec 4 09:40:35 2017 +1000
-Merge branch 'drm-vmwgfx-next' of
git://people.freedesktop.org/~syeh/repos_linux into drm-next
+Merge tag 'drm-intel-next-2017-11-17-1' of
git://anongit.freedesktop.org/drm/drm-intel into drm-next
diff --git a/include/drm-uapi/drm.h b/include/drm-uapi/drm.h
index 4737261ae3..f0bd91de0c 100644
--- a/include/drm-uapi/drm.h
+++ b/include/drm-uapi/drm.h
@@ -731,6 +731,28 @@ struct drm_syncobj_array {
__u32 pad;
};
+/* Query current scanout sequence number */
+struct drm_crtc_get_sequence {
+ __u32 crtc_id; /* requested crtc_id */
+ __u32 active; /* return: crtc output is active */
+ __u64 sequence; /* return: most recent vblank sequence */
+ __s64 sequence_ns; /* return: most recent time of first pixel out
*/
+};
+
+/* Queue event to be delivered at specified sequence. Time stamp marks
+ * when the first pixel of the refresh cycle leaves the display engine
+ * for the display
+ */
+#define DRM_CRTC_SEQUENCE_RELATIVE 0x0001 /* sequence is
relative to current */
+#define DRM_CRTC_SEQUENCE_NEXT_ON_MISS 0x0002 /* Use next
sequence if we've missed */
+
+struct drm_crtc_queue_sequence {
+ __u32 crtc_id;
+ __u32 flags;
+ __u64 sequence; /* on input, target sequence. on output, actual
sequence */
+ __u64 user_data;/* user data passed to event */
+};
+
#if defined(__cplusplus)
}
#endif
@@ -813,6 +835,9 @@ extern "C" {
#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
+#define DRM_IOCTL_CRTC_GET_SEQUENCEDRM_IOWR(0x3b, struct
drm_crtc_get_sequence)
+#define DRM_IOCTL_CRTC_QUEUE_SEQUENCE DRM_IOWR(0x3c, struct
drm_crtc_queue_sequence)
+
#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
#define DRM_IOCTL_MODE_GETRESOURCESDRM_IOWR(0xA0, struct drm_mode_card_res)
@@ -857,6 +882,11 @@ extern "C" {
#define DRM_IOCTL_SYNCOBJ_RESETDRM_IOWR(0xC4, struct
drm_syncobj_array)
#define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array)
+#define DRM_IOCTL_MODE_CREATE_LEASEDRM_IOWR(0xC6, struct
drm_mode_create_lease)
+#define DRM_IOCTL_MODE_LIST_LESSEESDRM_IOWR(0xC7, struct
drm_mode_list_lessees)
+#define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct
drm_mode_get_lease)
+#define DRM_IOCTL_MODE_REVOKE_LEASEDRM_IOWR(0xC9, struct
drm_mode_revoke_lease)
+
/**
* Device specific ioctls should only be in their respective headers
* The device specific ioctl range is from 0x40 to 0x9f.
@@ -887,6 +917,7 @@ struct drm_event {
#define DRM_EVENT_VBLANK 0x01
#define DRM_EVENT_FLIP_COMPLETE 0x02
+#define DRM_EVENT_CRTC_SEQUENCE0x03
struct drm_event_vblank {
struct drm_event base;
@@ -897,6 +928,16 @@ struct drm_event_vblank {
__u32 crtc_id; /* 0 on older kernels that do not support this */
};
+/* Event delivered at sequence. Time stamp marks when the first pixel
+ * of the refresh cycle leaves the display engine for the display
+ */
+struct drm_event_crtc_sequence {
+ struct drm_eventbase;
+ __u64 user_data;
+ __s64 time_ns;
+ __u64 sequence;
+};
+
/* typedef area */
typedef struct drm_clip_rect drm_clip_rect_t;
typedef struct drm_drawable_info drm_drawable_info_t;
diff --git a/include/drm-uapi/drm_mode.h b/include/drm-uapi/drm_mode.h
index 54fc38c3c3..5597a87154 100644
--- a/include/drm-uapi/drm_mode.h
+++ b/include/dr
Mesa (master): i965: read CS timestamp frequency from the kernel on Gen10+
Module: Mesa
Branch: master
Commit: b66e4b51bfc82621e590e6be8972a30958c0a08a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b66e4b51bfc82621e590e6be8972a30958c0a08a
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Mon Nov 6 11:11:42 2017 +
i965: read CS timestamp frequency from the kernel on Gen10+
We cannot figure this value out of the PCI-id anymore. Let's read it
from the kernel (which computes this from a few registers).
When running on a (upcoming) 4.16-rc1+ kernel, this will fixes piglit
tests on CNL :
spec@arb_timer_query@query gl_timestamp
spec@arb_timer_query@timestamp-get
spec@ext_timer_query@time-elapsed
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
src/mesa/drivers/dri/i965/intel_screen.c | 24
1 file changed, 24 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index db1552c188..0c17b4050c 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1686,6 +1686,27 @@ intelDestroyBuffer(__DRIdrawable * driDrawPriv)
}
static void
+intel_cs_timestamp_frequency(struct intel_screen *screen)
+{
+ /* We shouldn't need to update gen_device_info.timestamp_frequency prior to
+* gen10, PCI-id is enough to figure it out.
+*/
+ assert(screen->devinfo.gen >= 10);
+
+ int ret, freq;
+
+ ret = intel_get_param(screen, I915_PARAM_CS_TIMESTAMP_FREQUENCY,
+ );
+ if (ret < 0) {
+ _mesa_warning(NULL,
+"Kernel 4.15 required to read the CS timestamp
frequency.\n");
+ return;
+ }
+
+ screen->devinfo.timestamp_frequency = freq;
+}
+
+static void
intel_detect_sseu(struct intel_screen *screen)
{
assert(screen->devinfo.gen >= 8);
@@ -2405,6 +2426,9 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
isl_device_init(>isl_dev, >devinfo,
screen->hw_has_swizzling);
+ if (devinfo->gen >= 10)
+ intel_cs_timestamp_frequency(screen);
+
/* GENs prior to 8 do not support EU/Subslice info */
if (devinfo->gen >= 8) {
intel_detect_sseu(screen);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: perf: add support for userspace configurations
Module: Mesa
Branch: master
Commit: 27ee83eaf7e9976d3df77417eb20e2e1ff3750ff
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=27ee83eaf7e9976d3df77417eb20e2e1ff3750ff
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue Jul 25 17:22:58 2017 +0100
i965: perf: add support for userspace configurations
This allows us to deploy new configurations without touching the
kernel.
v2: Detect loadable configs without creating one (Chris)
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 109 --
1 file changed, 101 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 4b585c95b7..cdae18c627 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1730,6 +1730,18 @@ read_file_uint64(const char *file, uint64_t *val)
}
static void
+register_oa_config(struct brw_context *brw,
+ const struct brw_perf_query_info *query,
+ uint64_t config_id)
+{
+ struct brw_perf_query_info *registred_query = append_query_info(brw);
+ *registred_query = *query;
+ registred_query->oa_metrics_set_id = config_id;
+ DBG("metric set registred: id = %" PRIu64", guid = %s\n",
+ registred_query->oa_metrics_set_id, query->guid);
+}
+
+static void
enumerate_sysfs_metrics(struct brw_context *brw, const char *sysfs_dev_dir)
{
char buf[256];
@@ -1761,7 +1773,6 @@ enumerate_sysfs_metrics(struct brw_context *brw, const
char *sysfs_dev_dir)
entry = _mesa_hash_table_search(brw->perfquery.oa_metrics_table,
metric_entry->d_name);
if (entry) {
- struct brw_perf_query_info *query;
uint64_t id;
len = snprintf(buf, sizeof(buf), "%s/metrics/%s/id",
@@ -1776,12 +1787,7 @@ enumerate_sysfs_metrics(struct brw_context *brw, const
char *sysfs_dev_dir)
continue;
}
- query = append_query_info(brw);
- *query = *(struct brw_perf_query_info *)entry->data;
- query->oa_metrics_set_id = id;
-
- DBG("metric set known by mesa: id = %" PRIu64"\n",
- query->oa_metrics_set_id);
+ register_oa_config(brw, (const struct brw_perf_query_info
*)entry->data, id);
} else
DBG("metric set not known by mesa (skipping)\n");
}
@@ -1808,6 +1814,90 @@ read_sysfs_drm_device_file_uint64(struct brw_context
*brw,
}
static bool
+kernel_has_dynamic_config_support(struct brw_context *brw,
+ const char *sysfs_dev_dir)
+{
+ __DRIscreen *screen = brw->screen->driScrnPriv;
+ struct hash_entry *entry;
+
+ hash_table_foreach(brw->perfquery.oa_metrics_table, entry) {
+ struct brw_perf_query_info *query = entry->data;
+ char config_path[256];
+ uint64_t config_id;
+
+ snprintf(config_path, sizeof(config_path),
+ "%s/metrics/%s/id", sysfs_dev_dir, query->guid);
+
+ /* Look for the test config, which we know we can't replace. */
+ if (read_file_uint64(config_path, _id) && config_id == 1) {
+ uint32_t mux_regs[] = { 0x9888 /* NOA_WRITE */, 0x0 };
+ struct drm_i915_perf_oa_config config;
+
+ memset(, 0, sizeof(config));
+
+ memcpy(config.uuid, query->guid, sizeof(config.uuid));
+
+ config.n_mux_regs = 1;
+ config.mux_regs_ptr = (uintptr_t) mux_regs;
+
+ if (ioctl(screen->fd, DRM_IOCTL_I915_PERF_REMOVE_CONFIG, _id)
< 0 &&
+ errno == ENOENT)
+return true;
+
+ break;
+ }
+ }
+
+ return false;
+}
+
+static void
+init_oa_configs(struct brw_context *brw, const char *sysfs_dev_dir)
+{
+ __DRIscreen *screen = brw->screen->driScrnPriv;
+ struct hash_entry *entry;
+
+ hash_table_foreach(brw->perfquery.oa_metrics_table, entry) {
+ const struct brw_perf_query_info *query = entry->data;
+ struct drm_i915_perf_oa_config config;
+ char config_path[256];
+ uint64_t config_id;
+ int ret;
+
+ snprintf(config_path, sizeof(config_path),
+ "%s/metrics/%s/id", sysfs_dev_dir, query->guid);
+
+ /* Don't recreate already loaded configs. */
+ if (read_file_uint64(config_path, _id)) {
+ register_oa_config(brw, query, config_id);
+ continue;
+ }
+
+ memset(, 0, sizeof(config));
+
+ memcpy(config.uuid, query->guid, sizeof(config.uuid));
+
+ config.n_mux_regs = query->n_mux_regs;
+ config.mux_regs_ptr = (uintptr_t) query->mux_regs;
+
+ config.n_boolean_regs = query->n_b_counter_regs;
+
Mesa (master): i965: perf: update counter names on gen8/9 platforms
Module: Mesa Branch: master Commit: 064a4831e322351a0bf53b8e26842c6e819b59c9 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=064a4831e322351a0bf53b8e26842c6e819b59c9 Author: Lionel Landwerlin <lionel.g.landwer...@intel.com> Date: Thu Nov 9 16:46:47 2017 + i965: perf: update counter names on gen8/9 platforms Just fixing names. Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Acked-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/brw_oa_bdw.xml| 50 ++--- src/mesa/drivers/dri/i965/brw_oa_bxt.xml| 26 +++ src/mesa/drivers/dri/i965/brw_oa_glk.xml| 26 +++ src/mesa/drivers/dri/i965/brw_oa_kblgt2.xml | 26 +++ src/mesa/drivers/dri/i965/brw_oa_kblgt3.xml | 26 +++ src/mesa/drivers/dri/i965/brw_oa_sklgt2.xml | 26 +++ src/mesa/drivers/dri/i965/brw_oa_sklgt3.xml | 26 +++ src/mesa/drivers/dri/i965/brw_oa_sklgt4.xml | 26 +++ 8 files changed, 116 insertions(+), 116 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=064a4831e322351a0bf53b8e26842c6e819b59c9 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: perf: add support for CoffeeLake GT2
Module: Mesa Branch: master Commit: b5f6b9b0eb65a9e095618d00724b74f4f9f1dc62 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5f6b9b0eb65a9e095618d00724b74f4f9f1dc62 Author: Lionel Landwerlin <lionel.g.landwer...@intel.com> Date: Thu Aug 31 11:28:30 2017 +0100 i965: perf: add support for CoffeeLake GT2 Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Acked-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/Makefile.am | 1 + src/mesa/drivers/dri/i965/Makefile.sources| 4 +- src/mesa/drivers/dri/i965/brw_oa_cflgt2.xml | 10473 src/mesa/drivers/dri/i965/brw_performance_query.c | 6 + src/mesa/drivers/dri/i965/meson.build | 2 +- 5 files changed, 10484 insertions(+), 2 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=b5f6b9b0eb65a9e095618d00724b74f4f9f1dc62 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: perf: add support for CoffeeLake GT3
Module: Mesa Branch: master Commit: addfa4c5e8d8957cb8d3a0bf0f28ba178c87b97e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=addfa4c5e8d8957cb8d3a0bf0f28ba178c87b97e Author: Lionel Landwerlin <lionel.g.landwer...@intel.com> Date: Thu Nov 9 16:40:55 2017 + i965: perf: add support for CoffeeLake GT3 Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Acked-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/Makefile.am | 1 + src/mesa/drivers/dri/i965/Makefile.sources| 4 +- src/mesa/drivers/dri/i965/brw_oa_cflgt3.xml | 10704 src/mesa/drivers/dri/i965/brw_performance_query.c | 3 + src/mesa/drivers/dri/i965/meson.build | 2 +- 5 files changed, 10712 insertions(+), 2 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=addfa4c5e8d8957cb8d3a0bf0f28ba178c87b97e ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: add a debug option to disable oa config loading
Module: Mesa
Branch: master
Commit: 349712018bb05d7709bb90af194c544cb9e3474d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=349712018bb05d7709bb90af194c544cb9e3474d
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue Aug 29 10:41:27 2017 +0100
i965: add a debug option to disable oa config loading
This provides a good way to verify we haven't broken using the perf
driver on older kernels (which don't have the oa config loading
mechanism).
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/intel/common/gen_debug.c | 1 +
src/intel/common/gen_debug.h | 2 +-
src/mesa/drivers/dri/i965/brw_performance_query.c | 3 ++-
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_debug.c
index f58c593c44..a978f2f581 100644
--- a/src/intel/common/gen_debug.c
+++ b/src/intel/common/gen_debug.c
@@ -69,6 +69,7 @@ static const struct debug_control debug_control[] = {
{ "optimizer", DEBUG_OPTIMIZER },
{ "ann", DEBUG_ANNOTATION },
{ "no8", DEBUG_NO8 },
+ { "no-oaconfig", DEBUG_NO_OACONFIG },
{ "spill_fs",DEBUG_SPILL_FS },
{ "spill_vec4", DEBUG_SPILL_VEC4 },
{ "cs", DEBUG_CS },
diff --git a/src/intel/common/gen_debug.h b/src/intel/common/gen_debug.h
index e418e3fb16..ad62054ff2 100644
--- a/src/intel/common/gen_debug.h
+++ b/src/intel/common/gen_debug.h
@@ -69,7 +69,7 @@ extern uint64_t INTEL_DEBUG;
#define DEBUG_OPTIMIZER (1ull << 25)
#define DEBUG_ANNOTATION (1ull << 26)
#define DEBUG_NO8 (1ull << 27)
-/* Hole - feel free to reuse (1ull << 28) */
+#define DEBUG_NO_OACONFIG (1ull << 28)
#define DEBUG_SPILL_FS(1ull << 29)
#define DEBUG_SPILL_VEC4 (1ull << 30)
#define DEBUG_CS (1ull << 31)
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index cdae18c627..9a5117c46c 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -2144,7 +2144,8 @@ brw_init_perf_query_info(struct gl_context *ctx)
*/
oa_register(brw);
- if (kernel_has_dynamic_config_support(brw, sysfs_dev_dir))
+ if (likely((INTEL_DEBUG & DEBUG_NO_OACONFIG) == 0) &&
+ kernel_has_dynamic_config_support(brw, sysfs_dev_dir))
init_oa_configs(brw, sysfs_dev_dir);
else
enumerate_sysfs_metrics(brw, sysfs_dev_dir);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: perf: add busyness metric sets on gen8/9 platforms
Module: Mesa Branch: master Commit: 74f41fd781b9b93be1fc0bc05b6d25ce1f2887ce URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=74f41fd781b9b93be1fc0bc05b6d25ce1f2887ce Author: Lionel Landwerlin <lionel.g.landwer...@intel.com> Date: Thu Nov 9 16:51:26 2017 + i965: perf: add busyness metric sets on gen8/9 platforms Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Acked-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/brw_oa_bdw.xml| 183 +++ src/mesa/drivers/dri/i965/brw_oa_bxt.xml| 160 src/mesa/drivers/dri/i965/brw_oa_kblgt2.xml | 164 src/mesa/drivers/dri/i965/brw_oa_kblgt3.xml | 186 +++ src/mesa/drivers/dri/i965/brw_oa_sklgt2.xml | 164 src/mesa/drivers/dri/i965/brw_oa_sklgt3.xml | 187 src/mesa/drivers/dri/i965/brw_oa_sklgt4.xml | 187 7 files changed, 1231 insertions(+) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=74f41fd781b9b93be1fc0bc05b6d25ce1f2887ce ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: perf: update configs for loading from userspace
Module: Mesa Branch: master Commit: 3e7112e603f7b19038901b0592b9d8243b72c4ca URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e7112e603f7b19038901b0592b9d8243b72c4ca Author: Lionel Landwerlin <lionel.g.landwer...@intel.com> Date: Thu Aug 31 11:04:28 2017 +0100 i965: perf: update configs for loading from userspace When making configs loadable from userspace in the kernel, we left to userspace more responsability around programming some registers. In particular one register we use to set directly in the driver has now been moved into the configs. Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Acked-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/brw_oa_bdw.xml| 58 + src/mesa/drivers/dri/i965/brw_oa_bxt.xml| 16 src/mesa/drivers/dri/i965/brw_oa_chv.xml| 28 ++ src/mesa/drivers/dri/i965/brw_oa_glk.xml| 15 src/mesa/drivers/dri/i965/brw_oa_hsw.xml| 6 +++ src/mesa/drivers/dri/i965/brw_oa_kblgt2.xml | 18 + src/mesa/drivers/dri/i965/brw_oa_kblgt3.xml | 18 + src/mesa/drivers/dri/i965/brw_oa_sklgt2.xml | 48 src/mesa/drivers/dri/i965/brw_oa_sklgt3.xml | 18 + src/mesa/drivers/dri/i965/brw_oa_sklgt4.xml | 18 + 10 files changed, 243 insertions(+) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=3e7112e603f7b19038901b0592b9d8243b72c4ca ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: fix time elapsed counter equations in VME/ Media configs
Module: Mesa Branch: master Commit: a543ae4c2a75b5dfe956309b32f3ece1f0233f5b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a543ae4c2a75b5dfe956309b32f3ece1f0233f5b Author: Lionel Landwerlin <lionel.g.landwer...@intel.com> Date: Thu Nov 9 16:48:45 2017 + i965: fix time elapsed counter equations in VME/Media configs There was a mistake just in those metric sets. We probably didn't noticed because they're not really interesting for 3D workloads. Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Acked-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/brw_oa_bdw.xml| 4 ++-- src/mesa/drivers/dri/i965/brw_oa_kblgt2.xml | 4 ++-- src/mesa/drivers/dri/i965/brw_oa_kblgt3.xml | 4 ++-- src/mesa/drivers/dri/i965/brw_oa_sklgt2.xml | 4 ++-- src/mesa/drivers/dri/i965/brw_oa_sklgt3.xml | 4 ++-- src/mesa/drivers/dri/i965/brw_oa_sklgt4.xml | 4 ++-- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_oa_bdw.xml b/src/mesa/drivers/dri/i965/brw_oa_bdw.xml index c871a56347..fd3c28ffae 100644 --- a/src/mesa/drivers/dri/i965/brw_oa_bdw.xml +++ b/src/mesa/drivers/dri/i965/brw_oa_bdw.xml @@ -14693,7 +14693,7 @@ https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv: setup BO flags at state_pool/block_pool creation
Module: Mesa
Branch: master
Commit: 118a8c7587d919b3b85cec7855a16d9e778394e6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=118a8c7587d919b3b85cec7855a16d9e778394e6
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Fri Nov 17 17:26:59 2017 +
anv: setup BO flags at state_pool/block_pool creation
This will allow to set the flags on any anv_bo created/filled from a
state pool or block pool later.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/intel/vulkan/anv_allocator.c | 24 --
src/intel/vulkan/anv_device.c | 18
src/intel/vulkan/anv_private.h | 13 +---
src/intel/vulkan/tests/block_pool_no_free.c| 2 +-
src/intel/vulkan/tests/state_pool.c| 2 +-
src/intel/vulkan/tests/state_pool_free_list_only.c | 2 +-
src/intel/vulkan/tests/state_pool_no_free.c| 2 +-
7 files changed, 41 insertions(+), 22 deletions(-)
diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c
index ce37ccb488..8ed32b3c67 100644
--- a/src/intel/vulkan/anv_allocator.c
+++ b/src/intel/vulkan/anv_allocator.c
@@ -241,11 +241,13 @@ anv_block_pool_expand_range(struct anv_block_pool *pool,
VkResult
anv_block_pool_init(struct anv_block_pool *pool,
struct anv_device *device,
-uint32_t initial_size)
+uint32_t initial_size,
+uint64_t bo_flags)
{
VkResult result;
pool->device = device;
+ pool->bo_flags = bo_flags;
anv_bo_init(>bo, 0, 0);
pool->fd = memfd_create("block pool", MFD_CLOEXEC);
@@ -398,6 +400,7 @@ anv_block_pool_expand_range(struct anv_block_pool *pool,
* hard work for us.
*/
anv_bo_init(>bo, gem_handle, size);
+ pool->bo.flags = pool->bo_flags;
pool->bo.map = map;
return VK_SUCCESS;
@@ -515,8 +518,7 @@ anv_block_pool_grow(struct anv_block_pool *pool, struct
anv_block_state *state)
result = anv_block_pool_expand_range(pool, center_bo_offset, size);
- if (pool->device->instance->physicalDevice.has_exec_async)
- pool->bo.flags |= EXEC_OBJECT_ASYNC;
+ pool->bo.flags = pool->bo_flags;
done:
pthread_mutex_unlock(>device->mutex);
@@ -606,10 +608,12 @@ anv_block_pool_alloc_back(struct anv_block_pool *pool,
VkResult
anv_state_pool_init(struct anv_state_pool *pool,
struct anv_device *device,
-uint32_t block_size)
+uint32_t block_size,
+uint64_t bo_flags)
{
VkResult result = anv_block_pool_init(>block_pool, device,
- block_size * 16);
+ block_size * 16,
+ bo_flags);
if (result != VK_SUCCESS)
return result;
@@ -951,9 +955,11 @@ struct bo_pool_bo_link {
};
void
-anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device)
+anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device,
+ uint64_t bo_flags)
{
pool->device = device;
+ pool->bo_flags = bo_flags;
memset(pool->free_list, 0, sizeof(pool->free_list));
VG(VALGRIND_CREATE_MEMPOOL(pool, 0, false));
@@ -1005,11 +1011,7 @@ anv_bo_pool_alloc(struct anv_bo_pool *pool, struct
anv_bo *bo, uint32_t size)
if (result != VK_SUCCESS)
return result;
- if (pool->device->instance->physicalDevice.supports_48bit_addresses)
- new_bo.flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
-
- if (pool->device->instance->physicalDevice.has_exec_async)
- new_bo.flags |= EXEC_OBJECT_ASYNC;
+ new_bo.flags = pool->bo_flags;
assert(new_bo.size == pow2_size);
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 3aa213e205..fccf6a6377 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1211,21 +1211,31 @@ VkResult anv_CreateDevice(
}
pthread_condattr_destroy();
- anv_bo_pool_init(>batch_bo_pool, device);
+ uint64_t bo_flags =
+ (physical_device->supports_48bit_addresses ?
EXEC_OBJECT_SUPPORTS_48B_ADDRESS : 0) |
+ (physical_device->has_exec_async ? EXEC_OBJECT_ASYNC : 0);
+
+ anv_bo_pool_init(>batch_bo_pool, device, bo_flags);
result = anv_bo_cache_init(>bo_cache);
if (result != VK_SUCCESS)
goto fail_batch_bo_pool;
- result = anv_state_pool_init(>dynamic_state_pool, device, 16384);
+ /* For the state pools we explicitly disable 48bit. */
+ bo_flags = physical_device->has_exec_async ? EXEC_OBJECT_ASYNC : 0;
+
+ result = anv_state_pool_init(>dynamic_state_pool, device, 16384,
+bo_flags);
if (result != VK_SUCCESS)
Mesa (master): anv: flag batch & instruction BOs for capture
Module: Mesa
Branch: master
Commit: d4c52c540879d7e77aa83710f6b0acd3c5b30e99
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d4c52c540879d7e77aa83710f6b0acd3c5b30e99
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Fri Nov 17 17:29:26 2017 +
anv: flag batch & instruction BOs for capture
When the kernel support flagging our BO, let's mark batch &
instruction BOs for capture so then can be included in the error
state.
v2: Only add EXEC_CAPTURE if supported (Kristian)
v3: Fix operator precedence issue (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/intel/vulkan/anv_device.c | 7 +--
src/intel/vulkan/anv_private.h | 1 +
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index fccf6a6377..b5577ee61d 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -362,6 +362,7 @@ anv_physical_device_init(struct anv_physical_device *device,
goto fail;
device->has_exec_async = anv_gem_get_param(fd, I915_PARAM_HAS_EXEC_ASYNC);
+ device->has_exec_capture = anv_gem_get_param(fd,
I915_PARAM_HAS_EXEC_CAPTURE);
device->has_exec_fence = anv_gem_get_param(fd, I915_PARAM_HAS_EXEC_FENCE);
device->has_syncobj = anv_gem_get_param(fd,
I915_PARAM_HAS_EXEC_FENCE_ARRAY);
device->has_syncobj_wait = device->has_syncobj &&
@@ -1213,7 +1214,8 @@ VkResult anv_CreateDevice(
uint64_t bo_flags =
(physical_device->supports_48bit_addresses ?
EXEC_OBJECT_SUPPORTS_48B_ADDRESS : 0) |
- (physical_device->has_exec_async ? EXEC_OBJECT_ASYNC : 0);
+ (physical_device->has_exec_async ? EXEC_OBJECT_ASYNC : 0) |
+ (physical_device->has_exec_capture ? EXEC_OBJECT_CAPTURE : 0);
anv_bo_pool_init(>batch_bo_pool, device, bo_flags);
@@ -1230,7 +1232,8 @@ VkResult anv_CreateDevice(
goto fail_bo_cache;
result = anv_state_pool_init(>instruction_state_pool, device, 16384,
-bo_flags);
+bo_flags |
+(physical_device->has_exec_capture ?
EXEC_OBJECT_CAPTURE : 0));
if (result != VK_SUCCESS)
goto fail_dynamic_state_pool;
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index f9770788a6..6d4e43f2e6 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -773,6 +773,7 @@ struct anv_physical_device {
struct isl_device isl_dev;
int cmd_parser_version;
boolhas_exec_async;
+boolhas_exec_capture;
boolhas_exec_fence;
boolhas_syncobj;
boolhas_syncobj_wait;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: perf: factorize code for availability
Module: Mesa
Branch: master
Commit: 285a2192f93f09f5dc806dce0326281768539f55
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=285a2192f93f09f5dc806dce0326281768539f55
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue Jul 25 17:19:08 2017 +0100
i965: perf: factorize code for availability
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_oa.py | 28
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_oa.py
b/src/mesa/drivers/dri/i965/brw_oa.py
index 91f7ecb573..8c35923462 100644
--- a/src/mesa/drivers/dri/i965/brw_oa.py
+++ b/src/mesa/drivers/dri/i965/brw_oa.py
@@ -325,6 +325,21 @@ semantic_type_map = {
"ratio": "event"
}
+def output_availability(set, availability, counter_name):
+expression = splice_rpn_expression(set, counter_name, availability)
+lines = expression.split(' && ')
+n_lines = len(lines)
+if n_lines == 1:
+c("if (" + lines[0] + ") {")
+else:
+c("if (" + lines[0] + " &&")
+c_indent(4)
+for i in range(1, (n_lines - 1)):
+c(lines[i] + " &&")
+c(lines[(n_lines - 1)] + ") {")
+c_outdent(4)
+
+
def output_counter_report(set, counter, current_offset):
data_type = counter.get('data_type')
data_type_uc = data_type.upper()
@@ -343,18 +358,7 @@ def output_counter_report(set, counter, current_offset):
availability = counter.get('availability')
if availability:
-expression = splice_rpn_expression(set, counter, availability)
-lines = expression.split(' && ')
-n_lines = len(lines)
-if n_lines == 1:
-c("if (" + lines[0] + ") {")
-else:
-c("if (" + lines[0] + " &&")
-c_indent(4)
-for i in range(1, (n_lines - 1)):
-c(lines[i] + " &&")
-c(lines[(n_lines - 1)] + ") {")
-c_outdent(4)
+output_availability(set, availability, counter.get('name'))
c_indent(3)
c("counter = >counters[query->n_counters++];\n")
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: perf: list registers to program for queries
Module: Mesa
Branch: master
Commit: 24ec29b919f77116bb61f07bff09cbc14683d23d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=24ec29b919f77116bb61f07bff09cbc14683d23d
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue Jul 25 17:21:22 2017 +0100
i965: perf: list registers to program for queries
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_context.h | 15 ++
src/mesa/drivers/dri/i965/brw_oa.py | 51 +
2 files changed, 66 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 0960d635be..766b5bc073 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -615,6 +615,11 @@ enum brw_query_kind {
PIPELINE_STATS
};
+struct brw_perf_query_register_prog {
+ uint32_t reg;
+ uint32_t val;
+};
+
struct brw_perf_query_info
{
enum brw_query_kind kind;
@@ -634,6 +639,16 @@ struct brw_perf_query_info
int a_offset;
int b_offset;
int c_offset;
+
+ /* Register programming for a given query */
+ struct brw_perf_query_register_prog *flex_regs;
+ uint32_t n_flex_regs;
+
+ struct brw_perf_query_register_prog *mux_regs;
+ uint32_t n_mux_regs;
+
+ struct brw_perf_query_register_prog *b_counter_regs;
+ uint32_t n_b_counter_regs;
};
/**
diff --git a/src/mesa/drivers/dri/i965/brw_oa.py
b/src/mesa/drivers/dri/i965/brw_oa.py
index 8c35923462..576ea6687f 100644
--- a/src/mesa/drivers/dri/i965/brw_oa.py
+++ b/src/mesa/drivers/dri/i965/brw_oa.py
@@ -380,6 +380,45 @@ def output_counter_report(set, counter, current_offset):
return current_offset + sizeof(c_type)
+register_types = {
+'FLEX': 'flex_regs',
+'NOA': 'mux_regs',
+'OA': 'b_counter_regs',
+}
+
+def compute_register_lengths(set):
+register_lengths = {}
+register_configs = set.findall('register_config')
+for register_config in register_configs:
+t = register_types[register_config.get('type')]
+if t not in register_lengths:
+register_lengths[t] = len(register_config.findall('register'))
+else:
+register_lengths[t] += len(register_config.findall('register'))
+
+return register_lengths
+
+
+def generate_register_configs(set):
+register_configs = set.findall('register_config')
+for register_config in register_configs:
+t = register_types[register_config.get('type')]
+
+availability = register_config.get('availability')
+if availability:
+output_availability(set, availability, register_config.get('type')
+ ' register config')
+c_indent(3)
+
+for register in register_config.findall('register'):
+c("query->%s[query->n_%s++] = (struct
brw_perf_query_register_prog) { .reg = %s, .val = %s };" %
+ (t, t, register.get('address'), register.get('value')))
+
+if availability:
+c_outdent(3)
+c("}")
+c("\n")
+
+
def main():
global c_file
global header_file
@@ -475,6 +514,12 @@ def main():
max_values[counter.get('symbol_name')] = output_counter_max(set,
counter, empty_vars)
counter_vars["$" + counter.get('symbol_name')] = counter
+c("\n")
+register_lengths = compute_register_lengths(set);
+for reg_type, reg_length in register_lengths.iteritems():
+c("static struct brw_perf_query_register_prog
{0}_{1}_{2}[{3}];".format(chipset,
+
set.get('underscore_name'),
+
reg_type, reg_length))
c("\nstatic struct brw_perf_query_counter
{0}_{1}_query_counters[{2}];\n".format(chipset, set.get('underscore_name'),
len(counters)))
c("static struct brw_perf_query_info " + chipset + "_" +
set.get('underscore_name') + "_query = {\n")
@@ -510,6 +555,10 @@ def main():
.c_offset = 46,
"""))
+for reg_type, reg_length in register_lengths.iteritems():
+c(".{0} = {1}_{2}_{3},".format(reg_type, chipset,
set.get('underscore_name'), reg_type))
+c(".n_{0} = 0, /* Determined at runtime */".format(reg_type))
+
c_outdent(3)
c("};\n")
@@ -528,6 +577,8 @@ def main():
c("\nif (!query->data_size) {")
c_indent(3)
+generate_register_configs(set)
+
offset = 0
for counter in counters:
offset = output_counter_report(set, counter, offset)
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: perf: make revision variable available
Module: Mesa
Branch: master
Commit: 05231a4e740090f2e1eed720ac5d183125117267
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=05231a4e740090f2e1eed720ac5d183125117267
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue Jul 25 17:17:48 2017 +0100
i965: perf: make revision variable available
This will be used in the next commit to build up register programming.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src/mesa/drivers/dri/i965/brw_oa.py | 1 +
src/mesa/drivers/dri/i965/brw_performance_query.c | 4 +++-
src/mesa/drivers/dri/i965/intel_screen.c | 9 ++---
src/mesa/drivers/dri/i965/intel_screen.h | 3 +++
5 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 3bee3e99ed..0960d635be 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1087,6 +1087,7 @@ struct brw_context
uint64_t subslice_mask; /** $SubsliceMask */
uint64_t gt_min_freq; /** $GpuMinFrequency */
uint64_t gt_max_freq; /** $GpuMaxFrequency */
+ uint64_t revision;/** $SkuRevisionId */
} sys_vars;
/* OA metric sets, indexed by GUID, as know by Mesa at build time,
diff --git a/src/mesa/drivers/dri/i965/brw_oa.py
b/src/mesa/drivers/dri/i965/brw_oa.py
index 254c512a7d..91f7ecb573 100644
--- a/src/mesa/drivers/dri/i965/brw_oa.py
+++ b/src/mesa/drivers/dri/i965/brw_oa.py
@@ -175,6 +175,7 @@ hw_vars["$SubsliceMask"] =
"brw->perfquery.sys_vars.subslice_mask"
hw_vars["$GpuTimestampFrequency"] =
"brw->perfquery.sys_vars.timestamp_frequency"
hw_vars["$GpuMinFrequency"] = "brw->perfquery.sys_vars.gt_min_freq"
hw_vars["$GpuMaxFrequency"] = "brw->perfquery.sys_vars.gt_max_freq"
+hw_vars["$SkuRevisionId"] = "brw->perfquery.sys_vars.revision"
def output_rpn_equation_code(set, counter, equation, counter_vars):
c("/* RPN equation: " + equation + " */")
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index d8680b4879..4b585c95b7 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1812,6 +1812,7 @@ init_oa_sys_vars(struct brw_context *brw, const char
*sysfs_dev_dir)
{
const struct gen_device_info *devinfo = >screen->devinfo;
uint64_t min_freq_mhz = 0, max_freq_mhz = 0;
+ __DRIscreen *screen = brw->screen->driScrnPriv;
if (!read_sysfs_drm_device_file_uint64(brw, sysfs_dev_dir,
"gt_min_freq_mhz",
@@ -1826,6 +1827,8 @@ init_oa_sys_vars(struct brw_context *brw, const char
*sysfs_dev_dir)
brw->perfquery.sys_vars.gt_min_freq = min_freq_mhz * 100;
brw->perfquery.sys_vars.gt_max_freq = max_freq_mhz * 100;
brw->perfquery.sys_vars.timestamp_frequency = devinfo->timestamp_frequency;
+
+ brw->perfquery.sys_vars.revision = intel_device_get_revision(screen->fd);
brw->perfquery.sys_vars.n_eu_slices = devinfo->num_slices;
/* Assuming uniform distribution of subslices per slices. */
brw->perfquery.sys_vars.n_eu_sub_slices = devinfo->num_subslices[0];
@@ -1848,7 +1851,6 @@ init_oa_sys_vars(struct brw_context *brw, const char
*sysfs_dev_dir)
} else
unreachable("not reached");
} else {
- __DRIscreen *screen = brw->screen->driScrnPriv;
drm_i915_getparam_t gp;
int ret;
int slice_mask = 0;
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index 10064c3236..cdc36adc78 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -2129,14 +2129,9 @@ set_max_gl_versions(struct intel_screen *screen)
/**
* Return the revision (generally the revid field of the PCI header) of the
* graphics device.
- *
- * XXX: This function is useful to keep around even if it is not currently in
- * use. It is necessary for new platforms and revision specific workarounds or
- * features. Please don't remove it so that we know it at least continues to
- * build.
*/
-static __attribute__((__unused__)) int
-brw_get_revision(int fd)
+int
+intel_device_get_revision(int fd)
{
struct drm_i915_getparam gp;
int revision;
diff --git a/src/mesa/drivers/dri/i965/intel_screen.h
b/src/mesa/drivers/dri/i965/intel_screen.h
index 41e1dbdd4e..7948617b7f 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.h
+++ b/src/mesa/drivers/dri/i965/intel_screen.h
@@ -136,6 +136,9 @@ double get_
Mesa (master): intel: decoder: simplify field_is_header()
Module: Mesa
Branch: master
Commit: 20156931bf456932a4b53ad6685da42a7ad33ec2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=20156931bf456932a4b53ad6685da42a7ad33ec2
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Thu Sep 28 02:36:30 2017 +0100
intel: decoder: simplify field_is_header()
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/common/gen_decoder.c | 7 ---
src/intel/common/gen_decoder.h | 3 ++-
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index c0a46e5212..760a8769c5 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -288,6 +288,7 @@ create_field(struct parser_context *ctx, const char **atts)
struct gen_field *field;
field = rzalloc(ctx->group, struct gen_field);
+ field->parent = ctx->group;
for (int i = 0; atts[i]; i += 2) {
char *p;
@@ -960,7 +961,7 @@ print_dword_header(FILE *outfile,
}
bool
-gen_group_header_is_header(struct gen_group *group, struct gen_field *field)
+gen_field_is_header(struct gen_field *field)
{
uint32_t bits;
@@ -970,7 +971,7 @@ gen_group_header_is_header(struct gen_group *group, struct
gen_field *field)
bits = (1U << (field->end - field->start + 1)) - 1;
bits <<= field->start;
- return (group->opcode_mask & bits) != 0;
+ return (field->parent->opcode_mask & bits) != 0;
}
void
@@ -987,7 +988,7 @@ gen_print_group(FILE *outfile, struct gen_group *group,
print_dword_header(outfile, , offset, i);
last_dword = iter.dword;
}
- if (!gen_group_header_is_header(group, iter.field)) {
+ if (!gen_field_is_header(iter.field)) {
fprintf(outfile, "%s: %s\n", iter.name, iter.value);
if (iter.struct_desc) {
uint64_t struct_offset = offset + 4 * iter.dword;
diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
index f2291f43e9..9ee5fb51c2 100644
--- a/src/intel/common/gen_decoder.h
+++ b/src/intel/common/gen_decoder.h
@@ -56,7 +56,7 @@ int gen_group_get_length(struct gen_group *group, const
uint32_t *p);
const char *gen_group_get_name(struct gen_group *group);
uint32_t gen_group_get_opcode(struct gen_group *group);
struct gen_enum *gen_spec_find_enum(struct gen_spec *spec, const char *name);
-bool gen_group_header_is_header(struct gen_group *group, struct gen_field
*field);
+bool gen_field_is_header(struct gen_field *field);
struct gen_field_iterator {
struct gen_group *group;
@@ -145,6 +145,7 @@ struct gen_type {
};
struct gen_field {
+ struct gen_group *parent;
struct gen_field *next;
char *name;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: decoder: rename field() to field_value()
Module: Mesa
Branch: master
Commit: 81aee9fd4b461bf111da5392b5b29fd59092db4b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=81aee9fd4b461bf111da5392b5b29fd59092db4b
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Sat Sep 30 12:48:48 2017 +0100
intel: decoder: rename field() to field_value()
We would like to avoid collisions with variables named field.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/common/gen_decoder.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index c0d1d8670b..dbf87b9eff 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -235,7 +235,7 @@ mask(int start, int end)
}
static inline uint64_t
-field(uint64_t value, int start, int end)
+field_value(uint64_t value, int start, int end)
{
get_start_end_pos(, );
return (value & mask(start, end)) >> (start);
@@ -692,32 +692,32 @@ int
gen_group_get_length(struct gen_group *group, const uint32_t *p)
{
uint32_t h = p[0];
- uint32_t type = field(h, 29, 31);
+ uint32_t type = field_value(h, 29, 31);
switch (type) {
case 0: /* MI */ {
- uint32_t opcode = field(h, 23, 28);
+ uint32_t opcode = field_value(h, 23, 28);
if (opcode < 16)
return 1;
else
- return field(h, 0, 7) + 2;
+ return field_value(h, 0, 7) + 2;
break;
}
case 2: /* BLT */ {
- return field(h, 0, 7) + 2;
+ return field_value(h, 0, 7) + 2;
}
case 3: /* Render */ {
- uint32_t subtype = field(h, 27, 28);
- uint32_t opcode = field(h, 24, 26);
- uint16_t whole_opcode = field(h, 16, 31);
+ uint32_t subtype = field_value(h, 27, 28);
+ uint32_t opcode = field_value(h, 24, 26);
+ uint16_t whole_opcode = field_value(h, 16, 31);
switch (subtype) {
case 0:
if (whole_opcode == 0x6104 /* PIPELINE_SELECT_965 */)
return 1;
else if (opcode < 2)
-return field(h, 0, 7) + 2;
+return field_value(h, 0, 7) + 2;
else
return -1;
case 1:
@@ -727,9 +727,9 @@ gen_group_get_length(struct gen_group *group, const
uint32_t *p)
return -1;
case 2: {
if (opcode == 0)
-return field(h, 0, 7) + 2;
+return field_value(h, 0, 7) + 2;
else if (opcode < 3)
-return field(h, 0, 15) + 2;
+return field_value(h, 0, 15) + 2;
else
return -1;
}
@@ -737,7 +737,7 @@ gen_group_get_length(struct gen_group *group, const
uint32_t *p)
if (whole_opcode == 0x780b)
return 1;
else if (opcode < 4)
-return field(h, 0, 7) + 2;
+return field_value(h, 0, 7) + 2;
else
return -1;
}
@@ -853,13 +853,13 @@ iter_decode_field(struct gen_field_iterator *iter)
switch (iter->field->type.kind) {
case GEN_TYPE_UNKNOWN:
case GEN_TYPE_INT: {
- uint64_t value = field(v.qw, iter->start, iter->end);
+ uint64_t value = field_value(v.qw, iter->field->start, iter->field->end);
snprintf(iter->value, sizeof(iter->value), "%"PRId64, value);
enum_name = gen_get_enum_name(>field->inline_enum, value);
break;
}
case GEN_TYPE_UINT: {
- uint64_t value = field(v.qw, iter->start, iter->end);
+ uint64_t value = field_value(v.qw, iter->field->start, iter->field->end);
snprintf(iter->value, sizeof(iter->value), "%"PRIu64, value);
enum_name = gen_get_enum_name(>field->inline_enum, value);
break;
@@ -868,7 +868,7 @@ iter_decode_field(struct gen_field_iterator *iter)
const char *true_string =
iter->print_colors ? "\e[0;35mtrue\e[0m" : "true";
snprintf(iter->value, sizeof(iter->value), "%s",
- field(v.qw, iter->start, iter->end) ?
+ field_value(v.qw, iter->field->start, iter->field->end) ?
true_string : "false");
break;
}
@@ -889,8 +889,8 @@ iter_decode_field(struct gen_field_iterator *iter)
break;
case GEN_TYPE_UFIXED:
snprintf(iter->value, sizeof(iter->value), "%f",
- (float) field(v.qw, iter->start, iter->end) /
- (1 << iter->field->type.f));
+ (float) field_value(v.qw, iter->field->start,
+ iter->field->end) / (1 <<
iter->field->type.f));
break;
case GEN_TYPE_SFIXED:
/* FIXME: Sign extend extracted field. */
@@ -899,7 +899,7 @@ ite
Mesa (master): intel: common: make intel utils available from C++
Module: Mesa
Branch: master
Commit: cab93a901e14e97d4d243e4a451521dad957f0ac
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cab93a901e14e97d4d243e4a451521dad957f0ac
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed Sep 27 20:57:28 2017 +0100
intel: common: make intel utils available from C++
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/common/gen_decoder.h | 9 +
src/intel/common/gen_device_info.h | 8
src/intel/tools/gen_disasm.h | 8
3 files changed, 25 insertions(+)
diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
index 5d5ce7825f..f2291f43e9 100644
--- a/src/intel/common/gen_decoder.h
+++ b/src/intel/common/gen_decoder.h
@@ -30,6 +30,10 @@
#include "common/gen_device_info.h"
#include "util/hash_table.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
struct gen_spec;
struct gen_group;
struct gen_field;
@@ -164,4 +168,9 @@ void gen_print_group(FILE *out,
uint64_t offset, const uint32_t *p,
bool color);
+#ifdef __cplusplus
+}
+#endif
+
+
#endif /* GEN_DECODER_H */
diff --git a/src/intel/common/gen_device_info.h
b/src/intel/common/gen_device_info.h
index 59b345e949..30ddd905be 100644
--- a/src/intel/common/gen_device_info.h
+++ b/src/intel/common/gen_device_info.h
@@ -28,6 +28,10 @@
#include
#include
+#ifdef __cplusplus
+extern "C" {
+#endif
+
/**
* Intel hardware information and quirks
*/
@@ -198,4 +202,8 @@ struct gen_device_info
bool gen_get_device_info(int devid, struct gen_device_info *devinfo);
const char *gen_get_device_name(int devid);
+#ifdef __cplusplus
+}
+#endif
+
#endif /* GEN_DEVICE_INFO_H */
diff --git a/src/intel/tools/gen_disasm.h b/src/intel/tools/gen_disasm.h
index 24b56c9a8e..d2764bb90b 100644
--- a/src/intel/tools/gen_disasm.h
+++ b/src/intel/tools/gen_disasm.h
@@ -24,6 +24,10 @@
#ifndef GEN_DISASM_H
#define GEN_DISASM_H
+#ifdef __cplusplus
+extern "C" {
+#endif
+
struct gen_disasm;
struct gen_disasm *gen_disasm_create(int pciid);
@@ -32,4 +36,8 @@ void gen_disasm_disassemble(struct gen_disasm *disasm,
void gen_disasm_destroy(struct gen_disasm *disasm);
+#ifdef __cplusplus
+}
+#endif
+
#endif /* GEN_DISASM_H */
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: decoder: remove unused platform field
Module: Mesa
Branch: master
Commit: ea14ba01791c5f29eb235c77ff0fe34ad8cd29e7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea14ba01791c5f29eb235c77ff0fe34ad8cd29e7
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed Sep 27 18:57:58 2017 +0100
intel: decoder: remove unused platform field
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/common/gen_decoder.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 24c9fa79ad..c0a46e5212 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -49,7 +49,6 @@ struct parser_context {
XML_Parser parser;
int foo;
struct location loc;
- const char *platform;
struct gen_group *group;
struct gen_enum *enoom;
@@ -369,7 +368,6 @@ start_element(void *data, const char *element_name, const
char **atts)
if (gen == NULL)
fail(>loc, "no gen given");
- ctx->platform = strdup(name);
int major, minor;
int n = sscanf(gen, "%d.%d", , );
if (n == 0)
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: decoder: rename internal function to free name
Module: Mesa
Branch: master
Commit: 69d158573a174fb2a2ece6500d4572a3cff1c74f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=69d158573a174fb2a2ece6500d4572a3cff1c74f
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Thu Sep 28 02:37:20 2017 +0100
intel: decoder: rename internal function to free name
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/common/gen_decoder.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 760a8769c5..c0d1d8670b 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -827,7 +827,7 @@ iter_advance_field(struct gen_field_iterator *iter)
}
static void
-gen_field_decode(struct gen_field_iterator *iter)
+iter_decode_field(struct gen_field_iterator *iter)
{
union {
uint64_t qw;
@@ -937,7 +937,7 @@ gen_field_iterator_init(struct gen_field_iterator *iter,
iter->p_end = [gen_group_get_length(iter->group, iter->p)];
iter->print_colors = print_colors;
- gen_field_decode(iter);
+ iter_decode_field(iter);
}
bool
@@ -946,7 +946,7 @@ gen_field_iterator_next(struct gen_field_iterator *iter)
if (!iter_advance_field(iter))
return false;
- gen_field_decode(iter);
+ iter_decode_field(iter);
return true;
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: decoder: extract field value computation
Module: Mesa
Branch: master
Commit: ad876f721ebf952eaccf2d3f4979a1e53560f621
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad876f721ebf952eaccf2d3f4979a1e53560f621
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Sat Sep 30 13:48:36 2017 +0100
intel: decoder: extract field value computation
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/common/gen_decoder.c | 67 +++---
1 file changed, 37 insertions(+), 30 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index dbf87b9eff..2b6a86c012 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -241,14 +241,6 @@ field_value(uint64_t value, int start, int end)
return (value & mask(start, end)) >> (start);
}
-static inline uint64_t
-field_address(uint64_t value, int start, int end)
-{
- /* no need to right shift for address/offset */
- get_start_end_pos(, );
- return (value & mask(start, end));
-}
-
static struct gen_type
string_to_type(struct parser_context *ctx, const char *s)
{
@@ -826,6 +818,32 @@ iter_advance_field(struct gen_field_iterator *iter)
return true;
}
+static uint64_t
+iter_decode_field_raw(struct gen_field *field,
+ const uint32_t *p,
+ const uint32_t *end)
+{
+ uint64_t qw = 0;
+
+ if ((field->end - field->start) > 32) {
+ if ((p + 1) < end)
+ qw = ((uint64_t) p[1]) << 32;
+ qw |= p[0];
+ } else
+ qw = p[0];
+
+ qw = field_value(qw, field->start, field->end);
+
+ /* Address & offset types have to be aligned to dwords, their start bit is
+* a reminder of the alignment requirement.
+*/
+ if (field->type.kind == GEN_TYPE_ADDRESS ||
+ field->type.kind == GEN_TYPE_OFFSET)
+ qw <<= field->start % 32;
+
+ return qw;
+}
+
static void
iter_decode_field(struct gen_field_iterator *iter)
{
@@ -841,35 +859,28 @@ iter_decode_field(struct gen_field_iterator *iter)
memset(, 0, sizeof(v));
- if ((iter->field->end - iter->field->start) > 32) {
- if (>p[iter->dword + 1] < iter->p_end)
- v.qw = ((uint64_t) iter->p[iter->dword+1] << 32);
- v.qw |= iter->p[iter->dword];
- } else
- v.qw = iter->p[iter->dword];
+ v.qw = iter_decode_field_raw(iter->field,
+>p[iter->dword], iter->p_end);
const char *enum_name = NULL;
switch (iter->field->type.kind) {
case GEN_TYPE_UNKNOWN:
case GEN_TYPE_INT: {
- uint64_t value = field_value(v.qw, iter->field->start, iter->field->end);
- snprintf(iter->value, sizeof(iter->value), "%"PRId64, value);
- enum_name = gen_get_enum_name(>field->inline_enum, value);
+ snprintf(iter->value, sizeof(iter->value), "%"PRId64, v.qw);
+ enum_name = gen_get_enum_name(>field->inline_enum, v.qw);
break;
}
case GEN_TYPE_UINT: {
- uint64_t value = field_value(v.qw, iter->field->start, iter->field->end);
- snprintf(iter->value, sizeof(iter->value), "%"PRIu64, value);
- enum_name = gen_get_enum_name(>field->inline_enum, value);
+ snprintf(iter->value, sizeof(iter->value), "%"PRIu64, v.qw);
+ enum_name = gen_get_enum_name(>field->inline_enum, v.qw);
break;
}
case GEN_TYPE_BOOL: {
const char *true_string =
iter->print_colors ? "\e[0;35mtrue\e[0m" : "true";
snprintf(iter->value, sizeof(iter->value), "%s",
- field_value(v.qw, iter->field->start, iter->field->end) ?
- true_string : "false");
+ v.qw ? true_string : "false");
break;
}
case GEN_TYPE_FLOAT:
@@ -877,8 +888,7 @@ iter_decode_field(struct gen_field_iterator *iter)
break;
case GEN_TYPE_ADDRESS:
case GEN_TYPE_OFFSET:
- snprintf(iter->value, sizeof(iter->value), "0x%08"PRIx64,
- field_address(v.qw, iter->start, iter->end));
+ snprintf(iter->value, sizeof(iter->value), "0x%08"PRIx64, v.qw);
break;
case GEN_TYPE_STRUCT:
snprintf(iter->value, sizeof(iter->value), "",
@@ -889,8 +899,7 @@ iter_decode_field(struct gen_field_iterator *iter)
break;
case GEN_TYPE_UFIXED:
snprintf(iter->value, sizeof(iter->value), "%f",
- (float) field_value(v.qw, iter->field->start,
- iter->field->end) / (1 <<
iter->field->type.f));
+ (float) v.qw / (1 << iter->field->type.f));
Mesa (master): intel: decoder: enable decoding a single field
Module: Mesa
Branch: master
Commit: 8d8b9d11c97a679c0954a2f2e7ed8ddcd248ccfa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d8b9d11c97a679c0954a2f2e7ed8ddcd248ccfa
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Sat Sep 30 14:43:06 2017 +0100
intel: decoder: enable decoding a single field
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/common/gen_decoder.c | 37 +
src/intel/common/gen_decoder.h | 15 +++
2 files changed, 52 insertions(+)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 2b6a86c012..d09b6ea32b 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -568,6 +568,9 @@ gen_spec_load(const struct gen_device_info *devinfo)
ctx.spec->enums =
_mesa_hash_table_create(ctx.spec, _mesa_hash_string,
_mesa_key_string_equal);
+ ctx.spec->access_cache =
+ _mesa_hash_table_create(ctx.spec, _mesa_hash_string,
_mesa_key_string_equal);
+
total_length = zlib_inflate(compress_genxmls,
sizeof(compress_genxmls),
(void **) _data);
@@ -680,6 +683,32 @@ gen_spec_find_instruction(struct gen_spec *spec, const
uint32_t *p)
return NULL;
}
+struct gen_field *
+gen_group_find_field(struct gen_group *group, const char *name)
+{
+ char path[256];
+ snprintf(path, sizeof(path), "%s/%s", group->name, name);
+
+ struct gen_spec *spec = group->spec;
+ struct hash_entry *entry = _mesa_hash_table_search(spec->access_cache,
+ path);
+ if (entry)
+ return entry->data;
+
+ struct gen_field *field = group->fields;
+ while (field) {
+ if (strcmp(field->name, name) == 0) {
+ _mesa_hash_table_insert(spec->access_cache,
+ ralloc_strdup(spec, path),
+ field);
+ return field;
+ }
+ field = field->next;
+ }
+
+ return NULL;
+}
+
int
gen_group_get_length(struct gen_group *group, const uint32_t *p)
{
@@ -981,6 +1010,14 @@ gen_field_is_header(struct gen_field *field)
return (field->parent->opcode_mask & bits) != 0;
}
+void gen_field_decode(struct gen_field *field,
+ const uint32_t *p, const uint32_t *end,
+ union gen_field_value *value)
+{
+ uint32_t dword = field->start / 32;
+ value->u64 = iter_decode_field_raw(field, [dword], end);
+}
+
void
gen_print_group(FILE *outfile, struct gen_group *group,
uint64_t offset, const uint32_t *p, bool color)
diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
index 251582f712..8b00b6edc2 100644
--- a/src/intel/common/gen_decoder.h
+++ b/src/intel/common/gen_decoder.h
@@ -37,6 +37,7 @@ extern "C" {
struct gen_spec;
struct gen_group;
struct gen_field;
+union gen_field_value;
static inline uint32_t gen_make_gen(uint32_t major, uint32_t minor)
{
@@ -57,8 +58,13 @@ struct gen_enum *gen_spec_find_enum(struct gen_spec *spec,
const char *name);
int gen_group_get_length(struct gen_group *group, const uint32_t *p);
const char *gen_group_get_name(struct gen_group *group);
uint32_t gen_group_get_opcode(struct gen_group *group);
+struct gen_field *gen_group_find_field(struct gen_group *group, const char
*name);
struct gen_enum *gen_spec_find_enum(struct gen_spec *spec, const char *name);
+
bool gen_field_is_header(struct gen_field *field);
+void gen_field_decode(struct gen_field *field,
+ const uint32_t *p, const uint32_t *end,
+ union gen_field_value *value);
struct gen_field_iterator {
struct gen_group *group;
@@ -85,6 +91,8 @@ struct gen_spec {
struct hash_table *registers_by_name;
struct hash_table *registers_by_offset;
struct hash_table *enums;
+
+ struct hash_table *access_cache;
};
struct gen_group {
@@ -146,6 +154,13 @@ struct gen_type {
};
};
+union gen_field_value {
+ bool b32;
+ float f32;
+ uint64_t u64;
+ int64_t i64;
+};
+
struct gen_field {
struct gen_group *parent;
struct gen_field *next;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: decoder: expose missing find_enum()
Module: Mesa Branch: master Commit: bb16503542139bdd0acd1b77728f04fbc56d49e8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb16503542139bdd0acd1b77728f04fbc56d49e8 Author: Lionel Landwerlin <lionel.g.landwer...@intel.com> Date: Sat Sep 30 14:41:20 2017 +0100 intel: decoder: expose missing find_enum() Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com> --- src/intel/common/gen_decoder.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h index 9ee5fb51c2..251582f712 100644 --- a/src/intel/common/gen_decoder.h +++ b/src/intel/common/gen_decoder.h @@ -52,6 +52,8 @@ uint32_t gen_spec_get_gen(struct gen_spec *spec); struct gen_group *gen_spec_find_instruction(struct gen_spec *spec, const uint32_t *p); struct gen_group *gen_spec_find_register(struct gen_spec *spec, uint32_t offset); struct gen_group *gen_spec_find_register_by_name(struct gen_spec *spec, const char *name); +struct gen_enum *gen_spec_find_enum(struct gen_spec *spec, const char *name); + int gen_group_get_length(struct gen_group *group, const uint32_t *p); const char *gen_group_get_name(struct gen_group *group); uint32_t gen_group_get_opcode(struct gen_group *group); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: error-decode: implement a rolling window of programs
Module: Mesa
Branch: master
Commit: 938f62a1c7d72c7d512c9888b0a0bddef487
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=938f62a1c7d72c7d512c9888b0a0bddef487
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Thu Jun 1 15:23:38 2017 +0100
intel: error-decode: implement a rolling window of programs
If we have more programs than what we can store,
aubinator_error_decode will assert. Instead let's have a rolling
window of programs.
v2: Fix overflowing issues (Eric Engestrom)
v3: Go through programs starting at idx_program (Scott)
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Eric Engestrom <eric.engest...@imgtec.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/tools/aubinator_error_decode.c | 37
1 file changed, 23 insertions(+), 14 deletions(-)
diff --git a/src/intel/tools/aubinator_error_decode.c
b/src/intel/tools/aubinator_error_decode.c
index ed4d6f662c..4035723b87 100644
--- a/src/intel/tools/aubinator_error_decode.c
+++ b/src/intel/tools/aubinator_error_decode.c
@@ -47,6 +47,8 @@
#define GREEN_HEADER CSI "1;42m"
#define NORMAL CSI "0m"
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+
/* options */
static bool option_full_decode = true;
@@ -220,7 +222,15 @@ struct program {
#define MAX_NUM_PROGRAMS 4096
static struct program programs[MAX_NUM_PROGRAMS];
-static int num_programs = 0;
+static int idx_program = 0, num_programs = 0;
+
+static int next_program(void)
+{
+ int ret = idx_program;
+ idx_program = (idx_program + 1) % MAX_NUM_PROGRAMS;
+ num_programs = MIN(num_programs + 1, MAX_NUM_PROGRAMS);
+ return ret;
+}
static void decode(struct gen_spec *spec,
const char *buffer_name,
@@ -300,7 +310,7 @@ static void decode(struct gen_spec *spec,
enabled[1] ? "SIMD16 fragment shader" :
enabled[2] ? "SIMD32 fragment shader" : NULL;
-programs[num_programs++] = (struct program) {
+programs[next_program()] = (struct program) {
.type = type,
.command = inst->name,
.command_offset = offset,
@@ -309,7 +319,7 @@ static void decode(struct gen_spec *spec,
};
} else {
if (enabled[0]) /* SIMD8 */ {
- programs[num_programs++] = (struct program) {
+ programs[next_program()] = (struct program) {
.type = "SIMD8 fragment shader",
.command = inst->name,
.command_offset = offset,
@@ -318,7 +328,7 @@ static void decode(struct gen_spec *spec,
};
}
if (enabled[1]) /* SIMD16 */ {
- programs[num_programs++] = (struct program) {
+ programs[next_program()] = (struct program) {
.type = "SIMD16 fragment shader",
.command = inst->name,
.command_offset = offset,
@@ -327,7 +337,7 @@ static void decode(struct gen_spec *spec,
};
}
if (enabled[2]) /* SIMD32 */ {
- programs[num_programs++] = (struct program) {
+ programs[next_program()] = (struct program) {
.type = "SIMD32 fragment shader",
.command = inst->name,
.command_offset = offset,
@@ -374,7 +384,7 @@ static void decode(struct gen_spec *spec,
NULL;
if (is_enabled) {
-programs[num_programs++] = (struct program) {
+programs[next_program()] = (struct program) {
.type = type,
.command = inst->name,
.command_offset = offset,
@@ -383,8 +393,6 @@ static void decode(struct gen_spec *spec,
};
}
}
-
- assert(num_programs < MAX_NUM_PROGRAMS);
}
}
@@ -593,14 +601,15 @@ read_data_file(FILE *file)
printf("Disassembly of programs in instruction buffer at "
"0x%08"PRIx64":\n", gtt_offset);
for (int i = 0; i < num_programs; i++) {
- if (programs[i].instruction_base_address == gtt_offset) {
+ int idx = (idx_program + i) % MAX_NUM_PROGRAMS;
+ if (programs[idx].instruction_base_address == gtt_offset) {
printf("\n%s (specified by %s at batch offset "
"0x%08"PRIx64") at offset 0x%08"PRIx64"\n",
- programs[i].type,
- programs[i].command,
- programs[i].command_offset,
- programs[i].ksp);
-gen_disasm_disassemble(disasm, data, programs[i].ksp,
+
Mesa (master): intel: decoder: build sorted linked lists of fields
Module: Mesa
Branch: master
Commit: 3ae5c579169a62ee11be23d1587792a45747b77f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ae5c579169a62ee11be23d1587792a45747b77f
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed Aug 2 19:31:08 2017 +0100
intel: decoder: build sorted linked lists of fields
The xml files don't always have fields in order. This might confuse
our parsing of the commands. Let's have the fields in order. To do
this, the easiest way it to use a linked list. It also helps a bit
with the iterator.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/common/gen_decoder.c | 52 +-
src/intel/common/gen_decoder.h | 7 +++---
2 files changed, 34 insertions(+), 25 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 99a453bf5b..cdeb464c1b 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -56,6 +56,9 @@ struct parser_context {
int nvalues;
struct gen_value *values[256];
+ struct gen_field *fields[256];
+ int nfields;
+
struct gen_spec *spec;
};
@@ -359,19 +362,25 @@ create_value(struct parser_context *ctx, const char
**atts)
return value;
}
-static void
+static struct gen_field *
create_and_append_field(struct parser_context *ctx,
const char **atts)
{
- if (ctx->group->nfields == ctx->group->fields_size) {
- ctx->group->fields_size = MAX2(ctx->group->fields_size * 2, 2);
- ctx->group->fields =
- (struct gen_field **) realloc(ctx->group->fields,
- sizeof(ctx->group->fields[0]) *
- ctx->group->fields_size);
+ struct gen_field *field = create_field(ctx, atts);
+ struct gen_field *prev = NULL, *list = ctx->group->fields;
+
+ while (list && field->start > list->start) {
+ prev = list;
+ list = list->next;
}
- ctx->group->fields[ctx->group->nfields++] = create_field(ctx, atts);
+ field->next = list;
+ if (prev == NULL)
+ ctx->group->fields = field;
+ else
+ prev->next = field;
+
+ return field;
}
static void
@@ -421,7 +430,7 @@ start_element(void *data, const char *element_name, const
char **atts)
previous_group->next = group;
ctx->group = group;
} else if (strcmp(element_name, "field") == 0) {
- create_and_append_field(ctx, atts);
+ ctx->fields[ctx->nfields++] = create_and_append_field(ctx, atts);
} else if (strcmp(element_name, "enum") == 0) {
ctx->enoom = create_enum(ctx, name, atts);
} else if (strcmp(element_name, "value") == 0) {
@@ -441,18 +450,17 @@ end_element(void *data, const char *name)
strcmp(name, "struct") == 0 ||
strcmp(name, "register") == 0) {
struct gen_group *group = ctx->group;
+ struct gen_field *list = group->fields;
ctx->group = ctx->group->parent;
- for (int i = 0; i < group->nfields; i++) {
- if (group->fields[i]->start >= 16 &&
- group->fields[i]->end <= 31 &&
- group->fields[i]->has_default) {
+ while (list && list->end <= 31) {
+ if (list->start >= 16 && list->has_default) {
group->opcode_mask |=
- mask(group->fields[i]->start % 32, group->fields[i]->end % 32);
-group->opcode |=
- group->fields[i]->default_value << group->fields[i]->start;
+ mask(list->start % 32, list->end % 32);
+group->opcode |= list->default_value << list->start;
}
+ list = list->next;
}
if (strcmp(name, "instruction") == 0)
@@ -468,9 +476,10 @@ end_element(void *data, const char *name)
} else if (strcmp(name, "group") == 0) {
ctx->group = ctx->group->parent;
} else if (strcmp(name, "field") == 0) {
- assert(ctx->group->nfields > 0);
- struct gen_field *field = ctx->group->fields[ctx->group->nfields - 1];
+ struct gen_field *field = ctx->fields[ctx->nfields - 1];
size_t size = ctx->nvalues * sizeof(ctx->values[0]);
+ ctx->nfields--;
+ assert(ctx->nfields >= 0);
field->inline_enum.values = xzalloc(size);
field->inline_enum.nvalues = ctx->nvalues;
memcpy(field->inline_enum.values, ctx->values, size);
@@ -758,6 +767,7 @@ gen_field_iterator_init(struct gen_field_iterator *iter,
memset(iter, 0, sizeof(*iter));
iter->group = group;
+ it
Mesa (master): intel: decoder: reorder iterator init function
Module: Mesa
Branch: master
Commit: 0698318d1a8f53d7df0fb51dddf34bb01b4fb868
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0698318d1a8f53d7df0fb51dddf34bb01b4fb868
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed Aug 2 22:30:14 2017 +0100
intel: decoder: reorder iterator init function
Making the next change more readable.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/common/gen_decoder.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index acd0908acb..bd3e139404 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -758,20 +758,6 @@ gen_group_get_length(struct gen_group *group, const
uint32_t *p)
return -1;
}
-void
-gen_field_iterator_init(struct gen_field_iterator *iter,
-struct gen_group *group,
-const uint32_t *p,
-bool print_colors)
-{
- memset(iter, 0, sizeof(*iter));
-
- iter->group = group;
- iter->field = group->fields;
- iter->p = p;
- iter->print_colors = print_colors;
-}
-
static const char *
gen_get_enum_name(struct gen_enum *e, uint64_t value)
{
@@ -941,6 +927,20 @@ gen_field_iterator_next(struct gen_field_iterator *iter)
return true;
}
+void
+gen_field_iterator_init(struct gen_field_iterator *iter,
+struct gen_group *group,
+const uint32_t *p,
+bool print_colors)
+{
+ memset(iter, 0, sizeof(*iter));
+
+ iter->group = group;
+ iter->field = group->fields;
+ iter->p = p;
+ iter->print_colors = print_colors;
+}
+
static void
print_dword_header(FILE *outfile,
struct gen_field_iterator *iter,
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: common: expose gen_spec fields
Module: Mesa
Branch: master
Commit: 957a6eea7a674205c9990de1a682a19a94f9b7f2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=957a6eea7a674205c9990de1a682a19a94f9b7f2
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Fri Sep 22 18:00:25 2017 +0100
intel: common: expose gen_spec fields
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/common/gen_decoder.c | 13 -
src/intel/common/gen_decoder.h | 13 +
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 3aeaece2ae..99a453bf5b 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -39,19 +39,6 @@
#define XML_BUFFER_SIZE 4096
-struct gen_spec {
- uint32_t gen;
-
- int ncommands;
- struct gen_group *commands[256];
- int nstructs;
- struct gen_group *structs[256];
- int nregisters;
- struct gen_group *registers[256];
- int nenums;
- struct gen_enum *enums[256];
-};
-
struct location {
const char *filename;
int line_number;
diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
index 12d4551a12..ba9a19b55f 100644
--- a/src/intel/common/gen_decoder.h
+++ b/src/intel/common/gen_decoder.h
@@ -68,6 +68,19 @@ struct gen_field_iterator {
bool print_colors;
};
+struct gen_spec {
+ uint32_t gen;
+
+ uint32_t ncommands;
+ struct gen_group *commands[256];
+ uint32_t nstructs;
+ struct gen_group *structs[256];
+ uint32_t nregisters;
+ struct gen_group *registers[256];
+ uint32_t nenums;
+ struct gen_enum *enums[256];
+};
+
struct gen_group {
struct gen_spec *spec;
char *name;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: decoder: simplify creation of struct when 0-allocated
Module: Mesa
Branch: master
Commit: 1cf1591abd06a79f235d34fe44be2cab64629ca7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1cf1591abd06a79f235d34fe44be2cab64629ca7
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Sun Sep 24 00:43:09 2017 +0100
intel: decoder: simplify creation of struct when 0-allocated
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/common/gen_decoder.c | 4
1 file changed, 4 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index f3b2194da9..5b234d254a 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -161,8 +161,6 @@ create_group(struct parser_context *ctx,
group->name = ralloc_strdup(group, name);
group->spec = ctx->spec;
- group->group_offset = 0;
- group->group_count = 0;
group->variable = false;
if (parent) {
@@ -186,8 +184,6 @@ create_enum(struct parser_context *ctx, const char *name,
const char **atts)
if (name)
e->name = ralloc_strdup(e, name);
- e->nvalues = 0;
-
return e;
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: decoder: pack iterator variable declarations
Module: Mesa
Branch: master
Commit: 279531672e39cb5a4ffd00bdbb8805d88a366334
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=279531672e39cb5a4ffd00bdbb8805d88a366334
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Sun Sep 24 00:44:57 2017 +0100
intel: decoder: pack iterator variable declarations
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/common/gen_decoder.c | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 5b234d254a..97e54cd44a 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -131,10 +131,9 @@ static void
get_group_offset_count(const char **atts, uint32_t *offset, uint32_t *count,
uint32_t *size, bool *variable)
{
- char *p;
- int i;
+ for (int i = 0; atts[i]; i += 2) {
+ char *p;
- for (i = 0; atts[i]; i += 2) {
if (strcmp(atts[i], "count") == 0) {
*count = strtoul(atts[i + 1], , 0);
if (*count == 0)
@@ -190,10 +189,9 @@ create_enum(struct parser_context *ctx, const char *name,
const char **atts)
static void
get_register_offset(const char **atts, uint32_t *offset)
{
- char *p;
- int i;
+ for (int i = 0; atts[i]; i += 2) {
+ char *p;
- for (i = 0; atts[i]; i += 2) {
if (strcmp(atts[i], "num") == 0)
*offset = strtoul(atts[i + 1], , 0);
}
@@ -282,12 +280,12 @@ static struct gen_field *
create_field(struct parser_context *ctx, const char **atts)
{
struct gen_field *field;
- char *p;
- int i;
field = rzalloc(ctx->group, struct gen_field);
- for (i = 0; atts[i]; i += 2) {
+ for (int i = 0; atts[i]; i += 2) {
+ char *p;
+
if (strcmp(atts[i], "name") == 0)
field->name = ralloc_strdup(field, atts[i + 1]);
else if (strcmp(atts[i], "start") == 0)
@@ -346,13 +344,12 @@ static void
start_element(void *data, const char *element_name, const char **atts)
{
struct parser_context *ctx = data;
- int i;
const char *name = NULL;
const char *gen = NULL;
ctx->loc.line_number = XML_GetCurrentLineNumber(ctx->parser);
- for (i = 0; atts[i]; i += 2) {
+ for (int i = 0; atts[i]; i += 2) {
if (strcmp(atts[i], "name") == 0)
name = atts[i + 1];
else if (strcmp(atts[i], "gen") == 0)
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: decoder: split out getting the next field and decoding it
Module: Mesa
Branch: master
Commit: f5e5ca1e210c2e0f505ea154ca553275157dda73
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5e5ca1e210c2e0f505ea154ca553275157dda73
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed Aug 2 22:33:28 2017 +0100
intel: decoder: split out getting the next field and decoding it
Due to the new way we handle fields, we need *not* to forget the first
field when decoding instructions. The issue was that the advance
function was called first and skipped the first field.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/common/gen_decoder.c | 31 +--
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 4ef285667d..ac7c94f41e 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -837,17 +837,14 @@ iter_advance_field(struct gen_field_iterator *iter)
return true;
}
-bool
-gen_field_iterator_next(struct gen_field_iterator *iter)
+static void
+gen_field_decode(struct gen_field_iterator *iter)
{
union {
uint64_t qw;
float f;
} v;
- if (!iter_advance_field(iter))
- return false;
-
if (iter->field->name)
strncpy(iter->name, iter->field->name, sizeof(iter->name));
else
@@ -928,8 +925,6 @@ gen_field_iterator_next(struct gen_field_iterator *iter)
snprintf(iter->value + length, sizeof(iter->value) - length,
" (%s)", enum_name);
}
-
- return true;
}
void
@@ -941,9 +936,25 @@ gen_field_iterator_init(struct gen_field_iterator *iter,
memset(iter, 0, sizeof(*iter));
iter->group = group;
- iter->field = group->fields;
+ if (group->fields)
+ iter->field = group->fields;
+ else
+ iter->field = group->next->fields;
iter->p = p;
iter->print_colors = print_colors;
+
+ gen_field_decode(iter);
+}
+
+bool
+gen_field_iterator_next(struct gen_field_iterator *iter)
+{
+ if (!iter_advance_field(iter))
+ return false;
+
+ gen_field_decode(iter);
+
+ return true;
}
static void
@@ -977,7 +988,7 @@ gen_print_group(FILE *outfile, struct gen_group *group,
int last_dword = -1;
gen_field_iterator_init(, group, p, color);
- while (gen_field_iterator_next()) {
+ do {
if (last_dword != iter.dword) {
for (int i = last_dword + 1; i <= iter.dword; i++)
print_dword_header(outfile, , offset, i);
@@ -991,5 +1002,5 @@ gen_print_group(FILE *outfile, struct gen_group *group,
[iter.dword], color);
}
}
- }
+ } while (gen_field_iterator_next());
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: decoder: move field name copy
Module: Mesa Branch: master Commit: ffa011d1e3e6f57ce8a546c6a5210b15bde582d1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ffa011d1e3e6f57ce8a546c6a5210b15bde582d1 Author: Lionel Landwerlin <lionel.g.landwer...@intel.com> Date: Wed Aug 2 22:32:25 2017 +0100 intel: decoder: move field name copy This should be inside the function that actually decodes fields. Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com> --- src/intel/common/gen_decoder.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c index bd3e139404..4ef285667d 100644 --- a/src/intel/common/gen_decoder.c +++ b/src/intel/common/gen_decoder.c @@ -823,7 +823,7 @@ iter_advance_field(struct gen_field_iterator *iter) iter->field = iter->field->next; if (iter->field->name) - strncpy(iter->name, iter->field->name, sizeof(iter->name)); + strncpy(iter->name, iter->field->name, sizeof(iter->name)); else memset(iter->name, 0, sizeof(iter->name)); @@ -848,7 +848,12 @@ gen_field_iterator_next(struct gen_field_iterator *iter) if (!iter_advance_field(iter)) return false; - if ((iter->end - iter->start) > 32) + if (iter->field->name) + strncpy(iter->name, iter->field->name, sizeof(iter->name)); + else + memset(iter->name, 0, sizeof(iter->name)); + + if ((iter->field->end - iter->field->start) > 32) v.qw = ((uint64_t) iter->p[iter->dword+1] << 32) | iter->p[iter->dword]; else v.qw = iter->p[iter->dword]; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: common: print out all dword with field spanning multiple dwords
Module: Mesa
Branch: master
Commit: 1b369acdd83c853eede3e484251a42980f1f7b30
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b369acdd83c853eede3e484251a42980f1f7b30
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Wed Aug 2 19:33:09 2017 +0100
intel: common: print out all dword with field spanning multiple dwords
For example, we were skipping Dword 3 in this PIPE_CONTROL :
0x000ce130: 0x7a04: PIPE_CONTROL
DWord Length: 4
0x000ce134: 0x0010 : Dword 1
Flush LLC: false
Destination Address Type: 0 (PPGTT)
LRI Post Sync Operation: 0 (No LRI Operation)
Store Data Index: 0
Command Streamer Stall Enable: false
Global Snapshot Count Reset: false
TLB Invalidate: false
Generic Media State Clear: false
Post Sync Operation: 0 (No Write)
Depth Stall Enable: false
Render Target Cache Flush Enable: false
Instruction Cache Invalidate Enable: false
Texture Cache Invalidation Enable: false
Indirect State Pointers Disable: false
Notify Enable: false
Pipe Control Flush Enable: false
DC Flush Enable: false
VF Cache Invalidation Enable: true
Constant Cache Invalidation Enable: false
State Cache Invalidation Enable: false
Stall At Pixel Scoreboard: false
Depth Cache Flush Enable: false
0x000ce138: 0x : Dword 2
Address: 0x
0x000ce140: 0x : Dword 4
Immediate Data: 0
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/common/gen_decoder.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index cdeb464c1b..acd0908acb 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -943,10 +943,11 @@ gen_field_iterator_next(struct gen_field_iterator *iter)
static void
print_dword_header(FILE *outfile,
- struct gen_field_iterator *iter, uint64_t offset)
+ struct gen_field_iterator *iter,
+ uint64_t offset, uint32_t dword)
{
fprintf(outfile, "0x%08"PRIx64": 0x%08x : Dword %d\n",
- offset + 4 * iter->dword, iter->p[iter->dword], iter->dword);
+ offset + 4 * dword, iter->p[dword], dword);
}
static bool
@@ -968,12 +969,13 @@ gen_print_group(FILE *outfile, struct gen_group *group,
uint64_t offset, const uint32_t *p, bool color)
{
struct gen_field_iterator iter;
- int last_dword = 0;
+ int last_dword = -1;
gen_field_iterator_init(, group, p, color);
while (gen_field_iterator_next()) {
if (last_dword != iter.dword) {
- print_dword_header(outfile, , offset);
+ for (int i = last_dword + 1; i <= iter.dword; i++)
+print_dword_header(outfile, , offset, i);
last_dword = iter.dword;
}
if (!is_header_field(group, iter.field)) {
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: decoder: extract instruction/structs length
Module: Mesa
Branch: master
Commit: 38f338c19a7803a218a9b3249c4d6b2600edd75a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=38f338c19a7803a218a9b3249c4d6b2600edd75a
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue Sep 26 00:54:49 2017 +0100
intel: decoder: extract instruction/structs length
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/common/gen_decoder.c | 7 +++
src/intel/common/gen_decoder.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 97e54cd44a..24c9fa79ad 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -162,6 +162,13 @@ create_group(struct parser_context *ctx,
group->spec = ctx->spec;
group->variable = false;
+ for (int i = 0; atts[i]; i += 2) {
+ char *p;
+ if (strcmp(atts[i], "length") == 0) {
+ group->dw_length = strtoul(atts[i + 1], , 0);
+ }
+ }
+
if (parent) {
group->parent = parent;
get_group_offset_count(atts,
diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
index 12d0c063ee..5d5ce7825f 100644
--- a/src/intel/common/gen_decoder.h
+++ b/src/intel/common/gen_decoder.h
@@ -87,6 +87,7 @@ struct gen_group {
struct gen_field *fields; /* linked list of fields */
+ uint32_t dw_length;
uint32_t group_offset, group_count;
uint32_t group_size;
bool variable;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: decoder: expose helper to test header fields
Module: Mesa
Branch: master
Commit: de213b4af818e203680e2cf127bee0b0bf2482d6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=de213b4af818e203680e2cf127bee0b0bf2482d6
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Sat Sep 23 21:30:56 2017 +0100
intel: decoder: expose helper to test header fields
These fields are of little importance as they're used to recognize
instructions.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/common/gen_decoder.c | 6 +++---
src/intel/common/gen_decoder.h | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index d2190cb8b1..de4972a904 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -971,8 +971,8 @@ print_dword_header(FILE *outfile,
offset + 4 * dword, iter->p[dword], dword);
}
-static bool
-is_header_field(struct gen_group *group, struct gen_field *field)
+bool
+gen_group_header_is_header(struct gen_group *group, struct gen_field *field)
{
uint32_t bits;
@@ -999,7 +999,7 @@ gen_print_group(FILE *outfile, struct gen_group *group,
print_dword_header(outfile, , offset, i);
last_dword = iter.dword;
}
- if (!is_header_field(group, iter.field)) {
+ if (!gen_group_header_is_header(group, iter.field)) {
fprintf(outfile, "%s: %s\n", iter.name, iter.value);
if (iter.struct_desc) {
uint64_t struct_offset = offset + 4 * iter.dword;
diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
index 88375c8223..da12c01add 100644
--- a/src/intel/common/gen_decoder.h
+++ b/src/intel/common/gen_decoder.h
@@ -50,6 +50,7 @@ int gen_group_get_length(struct gen_group *group, const
uint32_t *p);
const char *gen_group_get_name(struct gen_group *group);
uint32_t gen_group_get_opcode(struct gen_group *group);
struct gen_enum *gen_spec_find_enum(struct gen_spec *spec, const char *name);
+bool gen_group_header_is_header(struct gen_group *group, struct gen_field
*field);
struct gen_field_iterator {
struct gen_group *group;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: decoder: don't read qword outside instruction/ struct limit
Module: Mesa
Branch: master
Commit: 68e1853ea3a6feabf14cbe42e8e003647fdc82f3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=68e1853ea3a6feabf14cbe42e8e003647fdc82f3
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Thu Aug 3 14:50:35 2017 +0100
intel: decoder: don't read qword outside instruction/struct limit
We used to print invalid data when the last field was being clamped to
32bits due to Dword Length of the whole instruction. Here is an
example where the decoder read part of the next instruction instead of
stopping at the 32bit limit:
0x000ce0b4: 0x1002: MI_STORE_DATA_IMM
0x000ce0b4: 0x1002 : Dword 0
DWord Length: 2
Store Qword: 0
Use Global GTT: false
0x000ce0b8: 0x00045010 : Dword 1
Core Mode Enable: 0
Address: 0x00045010
0x000ce0bc: 0x : Dword 2
0x000ce0c0: 0x : Dword 3
Immediate Data: 8791026489807077376
With this change we have the proper value :
0x000ce0b4: 0x1002: MI_STORE_DATA_IMM (4 Dwords)
0x000ce0b4: 0x1002 : Dword 0
DWord Length: 2
Store Qword: 0
Use Global GTT: false
0x000ce0b8: 0x00045010 : Dword 1
Core Mode Enable: 0
Address: 0x00045010
0x000ce0bc: 0x : Dword 2
0x000ce0c0: 0x : Dword 3
Immediate Data: 0
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/common/gen_decoder.c | 11 ---
src/intel/common/gen_decoder.h | 1 +
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index ac7c94f41e..d2190cb8b1 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -850,9 +850,13 @@ gen_field_decode(struct gen_field_iterator *iter)
else
memset(iter->name, 0, sizeof(iter->name));
- if ((iter->field->end - iter->field->start) > 32)
- v.qw = ((uint64_t) iter->p[iter->dword+1] << 32) | iter->p[iter->dword];
- else
+ memset(, 0, sizeof(v));
+
+ if ((iter->field->end - iter->field->start) > 32) {
+ if (>p[iter->dword + 1] < iter->p_end)
+ v.qw = ((uint64_t) iter->p[iter->dword+1] << 32);
+ v.qw |= iter->p[iter->dword];
+ } else
v.qw = iter->p[iter->dword];
const char *enum_name = NULL;
@@ -941,6 +945,7 @@ gen_field_iterator_init(struct gen_field_iterator *iter,
else
iter->field = group->next->fields;
iter->p = p;
+ iter->p_end = [gen_group_get_length(iter->group, iter->p)];
iter->print_colors = print_colors;
gen_field_decode(iter);
diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
index b8666ca304..88375c8223 100644
--- a/src/intel/common/gen_decoder.h
+++ b/src/intel/common/gen_decoder.h
@@ -57,6 +57,7 @@ struct gen_field_iterator {
char value[128];
struct gen_group *struct_desc;
const uint32_t *p;
+ const uint32_t *p_end;
int dword; /**< current field starts at [dword] */
int start; /**< current field starts at this bit number */
int end; /**< current field ends at this bit number */
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: common: silence compiler warning
Module: Mesa
Branch: master
Commit: a1faf48636f438992b17be50dec656a0c74c5585
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a1faf48636f438992b17be50dec656a0c74c5585
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Fri Oct 27 17:44:14 2017 +0100
intel: common: silence compiler warning
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com>
---
src/intel/common/gen_decoder.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 85880143f0..cd1894b85f 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -569,7 +569,7 @@ gen_spec_load(const struct gen_device_info *devinfo)
{
struct parser_context ctx;
void *buf;
- uint8_t *text_data;
+ uint8_t *text_data = NULL;
uint32_t text_offset = 0, text_length = 0, total_length;
uint32_t gen_10 = devinfo_to_gen(devinfo);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): util: hashtable: make hashing prototypes match
Module: Mesa
Branch: master
Commit: a8b1715b8ab974518f9713b82955f049a2c1c7ec
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8b1715b8ab974518f9713b82955f049a2c1c7ec
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Fri Oct 27 17:43:45 2017 +0100
util: hashtable: make hashing prototypes match
It seems nobody's using the string hashing function. If you try to
pass it directly to the hashtable creation function, you'll get
compiler warning for non matching prototypes. Let's make them match.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/util/hash_table.c | 3 ++-
src/util/hash_table.h | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/util/hash_table.c b/src/util/hash_table.c
index 1bda2149b9..b7421a0144 100644
--- a/src/util/hash_table.c
+++ b/src/util/hash_table.c
@@ -476,9 +476,10 @@ _mesa_hash_data(const void *data, size_t size)
/** FNV-1a string hash implementation */
uint32_t
-_mesa_hash_string(const char *key)
+_mesa_hash_string(const void *_key)
{
uint32_t hash = _mesa_fnv32_1a_offset_bias;
+ const char *key = _key;
while (*key != 0) {
hash = _mesa_fnv32_1a_accumulate(hash, *key);
diff --git a/src/util/hash_table.h b/src/util/hash_table.h
index cf939130fc..d3e0758b26 100644
--- a/src/util/hash_table.h
+++ b/src/util/hash_table.h
@@ -94,7 +94,7 @@ _mesa_hash_table_random_entry(struct hash_table *ht,
bool (*predicate)(struct hash_entry *entry));
uint32_t _mesa_hash_data(const void *data, size_t size);
-uint32_t _mesa_hash_string(const char *key);
+uint32_t _mesa_hash_string(const void *key);
bool _mesa_key_string_equal(const void *a, const void *b);
bool _mesa_key_pointer_equal(const void *a, const void *b);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv: disable stencil pma fix on Gen > 9
Module: Mesa
Branch: master
Commit: 0c95adaf9eb9763016c3319fef6d581b4d6d7359
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c95adaf9eb9763016c3319fef6d581b4d6d7359
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Fri Oct 20 18:28:48 2017 +0100
anv: disable stencil pma fix on Gen > 9
This workaround isn't listed on Gen10.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/intel/vulkan/gen8_cmd_buffer.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/vulkan/gen8_cmd_buffer.c
b/src/intel/vulkan/gen8_cmd_buffer.c
index f19867ca32..751212b8f4 100644
--- a/src/intel/vulkan/gen8_cmd_buffer.c
+++ b/src/intel/vulkan/gen8_cmd_buffer.c
@@ -259,6 +259,8 @@ want_depth_pma_fix(struct anv_cmd_buffer *cmd_buffer)
UNUSED static bool
want_stencil_pma_fix(struct anv_cmd_buffer *cmd_buffer)
{
+ if (GEN_GEN > 9)
+ return false;
assert(GEN_GEN == 9);
/* From the Skylake PRM Vol. 2c CACHE_MODE_1::STC PMA Optimization Enable:
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
