[Mesa-dev] [PATCH] mesa: add OES_EGL_image_external_essl3 support

[Tapani Pälli]

From: Ilia Mirkin 

Signed-off-by: Ilia Mirkin 
Reviewed-by: Tapani Pälli 
---

This one was originally sent as:
https://patchwork.freedesktop.org/patch/45339/

I've done trivial rebase for the patch, went through the changes 
once more and gave it r-b. If no objections, I'll push it in.

 src/compiler/glsl/builtin_functions.cpp  | 17 +
 src/compiler/glsl/builtin_types.cpp  |  3 ++-
 src/compiler/glsl/glsl_lexer.ll  |  2 +-
 src/compiler/glsl/glsl_parser_extras.cpp |  1 +
 src/compiler/glsl/glsl_parser_extras.h   |  2 ++
 src/mesa/main/extensions_table.h |  1 +
 6 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/src/compiler/glsl/builtin_functions.cpp 
b/src/compiler/glsl/builtin_functions.cpp
index 530cdc0264..293e8bd638 100644
--- a/src/compiler/glsl/builtin_functions.cpp
+++ b/src/compiler/glsl/builtin_functions.cpp
@@ -188,6 +188,14 @@ texture_external(const _mesa_glsl_parse_state *state)
return state->OES_EGL_image_external_enable;
 }
 
+static bool
+texture_external_es3(const _mesa_glsl_parse_state *state)
+{
+   return state->OES_EGL_image_external_essl3_enable &&
+  state->es_shader &&
+  state->is_version(0, 300);
+}
+
 /** True if texturing functions with explicit LOD are allowed. */
 static bool
 lod_exists_in_stage(const _mesa_glsl_parse_state *state)
@@ -1919,6 +1927,8 @@ builtin_builder::create_builtins()
 
 _texture(ir_tex, v130, glsl_type::float_type, 
glsl_type::sampler2DRectShadow_type, glsl_type::vec3_type),
 
+_texture(ir_tex, texture_external_es3, glsl_type::vec4_type,  
glsl_type::samplerExternalOES_type, glsl_type::vec2_type),
+
 _texture(ir_txb, v130_fs_only, glsl_type::vec4_type,  
glsl_type::sampler1D_type,  glsl_type::float_type),
 _texture(ir_txb, v130_fs_only, glsl_type::ivec4_type, 
glsl_type::isampler1D_type, glsl_type::float_type),
 _texture(ir_txb, v130_fs_only, glsl_type::uvec4_type, 
glsl_type::usampler1D_type, glsl_type::float_type),
@@ -2078,6 +2088,9 @@ builtin_builder::create_builtins()
 
 _texture(ir_tex, v130, glsl_type::vec4_type,  
glsl_type::sampler2DRect_type,  glsl_type::vec3_type, TEX_PROJECT),
 _texture(ir_tex, v130, glsl_type::ivec4_type, 
glsl_type::isampler2DRect_type, glsl_type::vec3_type, TEX_PROJECT),
+_texture(ir_tex, texture_external_es3, glsl_type::vec4_type,  
glsl_type::samplerExternalOES_type, glsl_type::vec3_type, TEX_PROJECT),
+_texture(ir_tex, texture_external_es3, glsl_type::vec4_type,  
glsl_type::samplerExternalOES_type, glsl_type::vec4_type, TEX_PROJECT),
+
 _texture(ir_tex, v130, glsl_type::uvec4_type, 
glsl_type::usampler2DRect_type, glsl_type::vec3_type, TEX_PROJECT),
 _texture(ir_tex, v130, glsl_type::vec4_type,  
glsl_type::sampler2DRect_type,  glsl_type::vec4_type, TEX_PROJECT),
 _texture(ir_tex, v130, glsl_type::ivec4_type, 
glsl_type::isampler2DRect_type, glsl_type::vec4_type, TEX_PROJECT),
@@ -2143,8 +2156,12 @@ builtin_builder::create_builtins()
 _texelFetch(texture_multisample_array, glsl_type::vec4_type,  
glsl_type::sampler2DMSArray_type,  glsl_type::ivec3_type),
 _texelFetch(texture_multisample_array, glsl_type::ivec4_type, 
glsl_type::isampler2DMSArray_type, glsl_type::ivec3_type),
 _texelFetch(texture_multisample_array, glsl_type::uvec4_type, 
glsl_type::usampler2DMSArray_type, glsl_type::ivec3_type),
+
+_texelFetch(texture_external_es3, glsl_type::vec4_type,  
glsl_type::samplerExternalOES_type, glsl_type::ivec2_type),
+
 NULL);
 
+
add_function("texelFetchOffset",
 _texelFetch(v130, glsl_type::vec4_type,  
glsl_type::sampler1D_type,  glsl_type::int_type, glsl_type::int_type),
 _texelFetch(v130, glsl_type::ivec4_type, 
glsl_type::isampler1D_type, glsl_type::int_type, glsl_type::int_type),
diff --git a/src/compiler/glsl/builtin_types.cpp 
b/src/compiler/glsl/builtin_types.cpp
index cae972b5b3..b64f75779b 100644
--- a/src/compiler/glsl/builtin_types.cpp
+++ b/src/compiler/glsl/builtin_types.cpp
@@ -331,7 +331,8 @@ _mesa_glsl_initialize_types(struct _mesa_glsl_parse_state 
*state)
   add_type(symbols, glsl_type::sampler2DArrayShadow_type);
}
 
-   if (state->OES_EGL_image_external_enable) {
+   if (state->OES_EGL_image_external_enable ||
+   state->OES_EGL_image_external_essl3_enable) {
   add_type(symbols, glsl_type::samplerExternalOES_type);
}
 
diff --git a/src/compiler/glsl/glsl_lexer.ll b/src/compiler/glsl/glsl_lexer.ll
index d2278ba01d..4b36574b73 100644
--- a/src/compiler/glsl/glsl_lexer.ll
+++ b/src/compiler/glsl/glsl_lexer.ll
@@ -427,7 +427,7 @@ usamplerCubeArray TYPE_WITH_ALT(400, 310, 400, 320, 
yyextra->ARB_texture_cube_ma
 samplerCubeArrayShadow   

[Mesa-dev] [PATCH] r600: fix resq for buffer images.

[Dave Airlie]

From: Dave Airlie 

If this is an image buffer, we need to calculate the correct resource
id.

Fixes:
KHR-GL45.shader_image_size.*

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/r600_shader.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 9a0d6b5dd1..8c4460a5d5 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -8821,7 +8821,10 @@ static int tgsi_resq(struct r600_shader_ctx *ctx)
(inst->Src[0].Register.File == TGSI_FILE_IMAGE && 
inst->Memory.Texture == TGSI_TEXTURE_BUFFER)) {
if (ctx->bc->chip_class < EVERGREEN)
ctx->shader->uses_tex_buffers = true;
-   return r600_do_buffer_txq(ctx, 0, 
ctx->shader->image_size_const_offset);
+   unsigned offset = 0;
+   if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
+   offset += R600_IMAGE_REAL_RESOURCE_OFFSET - 
R600_MAX_CONST_BUFFERS + ctx->shader->image_size_const_offset;
+   return r600_do_buffer_txq(ctx, 0, offset);
}
 
if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY &&
-- 
2.14.3

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Re: [Mesa-dev] [PATCH 11/11] r600/radeonsi/clover: always assume PIPE_SHADER_IR_NATIVE for clover

[Timothy Arceri]

On 02/02/18 17:21, Timothy Arceri wrote:

On 02/02/18 16:38, Jan Vesely wrote:

On Fri, 2018-02-02 at 15:03 +1100, Timothy Arceri wrote:

When PIPE_SHADER_IR_LLVM existed this query made sense but now it
always returns PIPE_SHADER_IR_NATIVE. Also it is now conlicting
with PIPE_SHADER_IR_NIR for compute shaders, so just assume this
is always PIPE_SHADER_IR_NATIVE for clover.

This change indirectly enables NIR support for compute shaders
on radeonsi.
---
  src/gallium/drivers/r600/r600_pipe.c  | 6 +-
  src/gallium/drivers/radeonsi/si_get.c | 3 ---
  src/gallium/state_trackers/clover/core/device.cpp | 3 +--
  3 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_pipe.c 
b/src/gallium/drivers/r600/r600_pipe.c

index 6c021e568d..287fe497ca 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -595,11 +595,7 @@ static int r600_get_shader_param(struct 
pipe_screen* pscreen,

  case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
  return 16;
  case PIPE_SHADER_CAP_PREFERRED_IR:
-    if (shader == PIPE_SHADER_COMPUTE) {
-    return PIPE_SHADER_IR_NATIVE;
-    } else {
-    return PIPE_SHADER_IR_TGSI;
-    }
+    return PIPE_SHADER_IR_TGSI;
  case PIPE_SHADER_CAP_SUPPORTED_IRS:
  if (rscreen->b.family >= CHIP_CEDAR)
  return (1 << PIPE_SHADER_IR_TGSI);
diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c

index 40f4cc267e..46cc190db1 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -391,9 +391,6 @@ static int si_get_shader_param(struct 
pipe_screen* pscreen,

  break;
  case PIPE_SHADER_COMPUTE:
  switch (param) {
-    case PIPE_SHADER_CAP_PREFERRED_IR:
-    return PIPE_SHADER_IR_NATIVE;
-
  case PIPE_SHADER_CAP_SUPPORTED_IRS: {
  int ir = 1 << PIPE_SHADER_IR_NATIVE;
diff --git a/src/gallium/state_trackers/clover/core/device.cpp 
b/src/gallium/state_trackers/clover/core/device.cpp

index 9dd7eed3f1..116f0c7604 100644
--- a/src/gallium/state_trackers/clover/core/device.cpp
+++ b/src/gallium/state_trackers/clover/core/device.cpp
@@ -243,8 +243,7 @@ device::vendor_name() const {
  enum pipe_shader_ir
  device::ir_format() const {
-   return (enum pipe_shader_ir) pipe->get_shader_param(
-  pipe, PIPE_SHADER_COMPUTE, PIPE_SHADER_CAP_PREFERRED_IR);
+   return PIPE_SHADER_IR_NATIVE;


This looks like it forces IR_NATIVE for absolutely everybody. Why
should other devices use IR_NATIVE just because radeonsi wants
experimental NIR for GL?


It's not just about experimental NIR. If say freedreno or any other nir 
driver was to use clover they would have the same problem.


Well it would be return PIPE_SHADER_IR_NIR here at least.

Also I'm 99% 
certain that no drivers other than radeonsi and r600 even care what this 
value is. All other drivers have this set to  PIPE_SHADER_IR_TGSI does 
that make anymore sense?


I see no there is indeed a tgsi path for clover. I guess maybe this 
change has more impact than I first thought.


Happy to here suggestions for solving the current conflict in uses of 
PIPE_SHADER_CAP_PREFERRED_IR.






Jan


  }
  std::string



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[Mesa-dev] [PATCH] r600/eg: fix cube map array buffer images.

[Dave Airlie]

From: Dave Airlie 

This fixes a crash in:
KHR-GL45.texture_cube_map_array.texture_size_compute_sh.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/r600_state_common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/r600/r600_state_common.c 
b/src/gallium/drivers/r600/r600_state_common.c
index d9c74b5f47..477372c3c1 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -1421,7 +1421,7 @@ void eg_setup_buffer_constants(struct r600_context *rctx, 
int shader_type)
int idx = i - sview_bits;
if (images->enabled_mask & (1 << idx)) {
uint32_t offset = (base_offset / 4) + i;
-   constants[offset] = 
images->views[i].base.resource->array_size / 6;
+   constants[offset] = 
images->views[idx].base.resource->array_size / 6;
}
}
}
-- 
2.14.3

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Re: [Mesa-dev] [PATCH (resend)] r600/sb: Don't require array declarations for TGSI_FILE_SYSTEM_VALUE

[Gert Wollny]

Am Freitag, den 02.02.2018, 02:13 +0100 schrieb Roland Scheidegger:
> Am 30.01.2018 um 09:21 schrieb Gert Wollny:
> > Although gl_SampleMaskIn is declared as an array in GLSL, it is
> > effectively a 32 bit mask on all hardware supported by mesa, so the
> > array indexing is ignored (Thanks Glenn Kennard for the
> > explanation).
> > 
> > Add a comment that the assert is not made superfluos by the else
> > branch.
> > 
> > Corrects: piglit spec@arb_gpu_shader5@execution@samplemaskin-
> > indirect for
> > debug builds (it already passed in release).
> > 
> > Signed-off-by: Gert Wollny 
> > ---
> > 
> >  src/gallium/drivers/r600/sb/sb_bc_parser.cpp | 8 +++-
> >  1 file changed, 7 insertions(+), 1 deletion(-)
> > 
> > diff --git a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
> > b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
> > index 970e4141d5..b92e058daf 100644
> > --- a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
> > +++ b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
> > @@ -125,7 +125,9 @@ int bc_parser::parse_decls() {
> > return 0;
> > }
> >  
> > -   if (pshader->indirect_files & ~((1 << TGSI_FILE_CONSTANT)
> > | (1 << TGSI_FILE_SAMPLER))) {
> > +   if (pshader->indirect_files &
> > +   ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER)
> > |
> > +  (1 << TGSI_FILE_SYSTEM_VALUE))) {
> 
> So I suppose this is ok because none of the other system values
> could be arrays.
> That said, isn't that actually a bug in glsl to tgsi translation? the
> sample mask is never an array in gallium/tgsi (and not declared as
> such), so I think it should not turn up as indirect when properly
> translated, reading the value should not end up as indexed.

Well, the spec says the sample mask is an array [1], but Glenn told me
that in the end on all supported hardware it ends up as a bit mask [2].

Best, 
Gert 

[1] 
https://www.khronos.org/registry/OpenGL-Refpages/gl4/html/gl_SampleMask
.xhtml

[2]https://lists.freedesktop.org/archives/mesa-dev/2017-September/16937
4.html
> 
> Roland
> 
> 
> > assert(pshader->num_arrays);
> >  
> > @@ -135,6 +137,10 @@ int bc_parser::parse_decls() {
> > sh->add_gpr_array(a.gpr_start,
> > a.gpr_count, a.comp_mask);
> > }
> > } else {
> > +   /* When the above assert is disabled and
> > proper array info
> > +* is missing for some reason then, as a
> > fallback, make sure
> > +* that all GPRs can be accessed
> > indirectly.
> > +*/
> > sh->add_gpr_array(0, pshader->bc.ngpr,
> > 0x0F);
> > }
> > }
> > 
> 
> 
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[Mesa-dev] [PATCH] r600: fix VERTEX_ATTRIB_STRIDE to be 2048

[Dave Airlie]

From: Dave Airlie 

This fixes:
KHR-GL45.limits.max_vertex_attrib_stride
looks like a typo from the first commit.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/r600_pipe.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/r600/r600_pipe.c 
b/src/gallium/drivers/r600/r600_pipe.c
index 6c021e568d..29fadf6200 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -451,7 +451,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum 
pipe_cap param)
return family >= CHIP_CEDAR ? 4 : 1;
 
case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
-   return 2047;
+   return 2048;
 
/* Texturing. */
case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
-- 
2.14.3

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Re: [Mesa-dev] [PATCH 11/11] r600/radeonsi/clover: always assume PIPE_SHADER_IR_NATIVE for clover

[Timothy Arceri]

On 02/02/18 16:38, Jan Vesely wrote:

On Fri, 2018-02-02 at 15:03 +1100, Timothy Arceri wrote:

When PIPE_SHADER_IR_LLVM existed this query made sense but now it
always returns PIPE_SHADER_IR_NATIVE. Also it is now conlicting
with PIPE_SHADER_IR_NIR for compute shaders, so just assume this
is always PIPE_SHADER_IR_NATIVE for clover.

This change indirectly enables NIR support for compute shaders
on radeonsi.
---
  src/gallium/drivers/r600/r600_pipe.c  | 6 +-
  src/gallium/drivers/radeonsi/si_get.c | 3 ---
  src/gallium/state_trackers/clover/core/device.cpp | 3 +--
  3 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_pipe.c 
b/src/gallium/drivers/r600/r600_pipe.c
index 6c021e568d..287fe497ca 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -595,11 +595,7 @@ static int r600_get_shader_param(struct pipe_screen* 
pscreen,
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return 16;
  case PIPE_SHADER_CAP_PREFERRED_IR:
-   if (shader == PIPE_SHADER_COMPUTE) {
-   return PIPE_SHADER_IR_NATIVE;
-   } else {
-   return PIPE_SHADER_IR_TGSI;
-   }
+   return PIPE_SHADER_IR_TGSI;
case PIPE_SHADER_CAP_SUPPORTED_IRS:
if (rscreen->b.family >= CHIP_CEDAR)
return (1 << PIPE_SHADER_IR_TGSI);
diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c
index 40f4cc267e..46cc190db1 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -391,9 +391,6 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
break;
case PIPE_SHADER_COMPUTE:
switch (param) {
-   case PIPE_SHADER_CAP_PREFERRED_IR:
-   return PIPE_SHADER_IR_NATIVE;
-
case PIPE_SHADER_CAP_SUPPORTED_IRS: {
int ir = 1 << PIPE_SHADER_IR_NATIVE;
  
diff --git a/src/gallium/state_trackers/clover/core/device.cpp b/src/gallium/state_trackers/clover/core/device.cpp

index 9dd7eed3f1..116f0c7604 100644
--- a/src/gallium/state_trackers/clover/core/device.cpp
+++ b/src/gallium/state_trackers/clover/core/device.cpp
@@ -243,8 +243,7 @@ device::vendor_name() const {
  
  enum pipe_shader_ir

  device::ir_format() const {
-   return (enum pipe_shader_ir) pipe->get_shader_param(
-  pipe, PIPE_SHADER_COMPUTE, PIPE_SHADER_CAP_PREFERRED_IR);
+   return PIPE_SHADER_IR_NATIVE;


This looks like it forces IR_NATIVE for absolutely everybody. Why
should other devices use IR_NATIVE just because radeonsi wants
experimental NIR for GL?


It's not just about experimental NIR. If say freedreno or any other nir 
driver was to use clover they would have the same problem. Also I'm 99% 
certain that no drivers other than radeonsi and r600 even care what this 
value is. All other drivers have this set to  PIPE_SHADER_IR_TGSI does 
that make anymore sense?




Jan


  }
  
  std::string



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[Mesa-dev] [PATCH v2 3/3] st/radeonsi: enable disk cache for nir

[Timothy Arceri]

Reviewed-by: Marek Olšák 
---
 src/gallium/drivers/radeonsi/si_pipe.c |  4 
 src/mesa/state_tracker/st_program.c| 15 +++
 2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index b44c2fc825..ab45901072 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -620,10 +620,6 @@ static void si_disk_cache_create(struct si_screen *sscreen)
if (sscreen->debug_flags & DBG_ALL_SHADERS)
return;
 
-   /* TODO: remove this once gallium supports a nir cache */
-   if (sscreen->debug_flags & DBG(NIR))
-   return;
-
uint32_t mesa_timestamp;
if (disk_cache_get_function_timestamp(si_disk_cache_create,
  _timestamp)) {
diff --git a/src/mesa/state_tracker/st_program.c 
b/src/mesa/state_tracker/st_program.c
index 191567ceec..d9b7155a91 100644
--- a/src/mesa/state_tracker/st_program.c
+++ b/src/mesa/state_tracker/st_program.c
@@ -465,6 +465,7 @@ st_translate_vertex_program(struct st_context *st,
   >tgsi.stream_output);
   }
 
+  st_store_ir_in_disk_cache(st, >Base, true);
   return true;
}
 
@@ -899,9 +900,11 @@ st_translate_fragment_program(struct st_context *st,
   }
}
 
-   /* We have already compiler to NIR so just return */
-   if (stfp->shader_program)
+   /* We have already compiled to NIR so just return */
+   if (stfp->shader_program) {
+  st_store_ir_in_disk_cache(st, >Base, true);
   return true;
+   }
 
ureg = ureg_create_with_screen(PIPE_SHADER_FRAGMENT, st->pipe->screen);
if (ureg == NULL)
@@ -1471,6 +1474,7 @@ st_translate_geometry_program(struct st_context *st,
/* We have already compiled to NIR so just return */
if (stgp->shader_program) {
   st_translate_program_stream_output(>Base, 
>tgsi.stream_output);
+  st_store_ir_in_disk_cache(st, >Base, true);
   return true;
}
 
@@ -1570,8 +1574,10 @@ st_translate_tessctrl_program(struct st_context *st,
struct ureg_program *ureg;
 
/* We have already compiled to NIR so just return */
-   if (sttcp->shader_program)
+   if (sttcp->shader_program) {
+  st_store_ir_in_disk_cache(st, >Base, true);
   return true;
+   }
 
ureg = ureg_create_with_screen(PIPE_SHADER_TESS_CTRL, st->pipe->screen);
if (ureg == NULL)
@@ -1601,6 +1607,7 @@ st_translate_tesseval_program(struct st_context *st,
/* We have already compiled to NIR so just return */
if (sttep->shader_program) {
   st_translate_program_stream_output(>Base, 
>tgsi.stream_output);
+  st_store_ir_in_disk_cache(st, >Base, true);
   return true;
}
 
@@ -1651,7 +1658,7 @@ st_translate_compute_program(struct st_context *st,
   /* no compute variants: */
   st_finalize_nir(st, >Base, stcp->shader_program,
   (struct nir_shader *) stcp->tgsi.prog);
-
+  st_store_ir_in_disk_cache(st, >Base, true);
   return true;
}
 
-- 
2.14.3

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[Mesa-dev] [PATCH v2 2/3] st: add nir shader disk cache support

[Timothy Arceri]

v2: include compute shader support
---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp |   2 +-
 src/mesa/state_tracker/st_program.c|   6 +-
 src/mesa/state_tracker/st_shader_cache.c   | 163 ++---
 src/mesa/state_tracker/st_shader_cache.h   |   8 +-
 4 files changed, 135 insertions(+), 44 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 355ba28218..4f5f3ccc56 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -6924,7 +6924,7 @@ st_link_shader(struct gl_context *ctx, struct 
gl_shader_program *prog)
bool use_nir = preferred_ir == PIPE_SHADER_IR_NIR;
 
/* Return early if we are loading the shader from on-disk cache */
-   if (st_load_tgsi_from_disk_cache(ctx, prog)) {
+   if (st_load_ir_from_disk_cache(ctx, prog, use_nir)) {
   return GL_TRUE;
}
 
diff --git a/src/mesa/state_tracker/st_program.c 
b/src/mesa/state_tracker/st_program.c
index 2c367efa6c..191567ceec 100644
--- a/src/mesa/state_tracker/st_program.c
+++ b/src/mesa/state_tracker/st_program.c
@@ -538,7 +538,7 @@ st_translate_vertex_program(struct st_context *st,
 
if (stvp->glsl_to_tgsi) {
   stvp->glsl_to_tgsi = NULL;
-  st_store_tgsi_in_disk_cache(st, >Base);
+  st_store_ir_in_disk_cache(st, >Base, false);
}
 
return stvp->tgsi.tokens != NULL;
@@ -995,7 +995,7 @@ st_translate_fragment_program(struct st_context *st,
 
if (stfp->glsl_to_tgsi) {
   stfp->glsl_to_tgsi = NULL;
-  st_store_tgsi_in_disk_cache(st, >Base);
+  st_store_ir_in_disk_cache(st, >Base, false);
}
 
return stfp->tgsi.tokens != NULL;
@@ -1411,7 +1411,7 @@ st_translate_program_common(struct st_context *st,
outputMapping,
_state->stream_output);
 
-   st_store_tgsi_in_disk_cache(st, prog);
+   st_store_ir_in_disk_cache(st, prog, false);
 
if ((ST_DEBUG & DEBUG_TGSI) && (ST_DEBUG & DEBUG_MESA)) {
   _mesa_print_program(prog);
diff --git a/src/mesa/state_tracker/st_shader_cache.c 
b/src/mesa/state_tracker/st_shader_cache.c
index 12d73965bf..8eccf7c921 100644
--- a/src/mesa/state_tracker/st_shader_cache.c
+++ b/src/mesa/state_tracker/st_shader_cache.c
@@ -26,6 +26,8 @@
 #include "st_program.h"
 #include "st_shader_cache.h"
 #include "compiler/glsl/program.h"
+#include "compiler/nir/nir.h"
+#include "compiler/nir/nir_serialize.h"
 #include "pipe/p_shader_tokens.h"
 #include "program/ir_to_mesa.h"
 #include "util/u_memory.h"
@@ -44,20 +46,33 @@ write_stream_out_to_cache(struct blob *blob,
 sizeof(tgsi->stream_output));
 }
 
+static void
+copy_blob_to_driver_cache_blob(struct blob *blob, struct gl_program *prog)
+{
+   prog->driver_cache_blob = ralloc_size(NULL, blob->size);
+   memcpy(prog->driver_cache_blob, blob->data, blob->size);
+   prog->driver_cache_blob_size = blob->size;
+}
+
 static void
 write_tgsi_to_cache(struct blob *blob, const struct tgsi_token *tokens,
 struct gl_program *prog, unsigned num_tokens)
 {
blob_write_uint32(blob, num_tokens);
blob_write_bytes(blob, tokens, num_tokens * sizeof(struct tgsi_token));
+   copy_blob_to_driver_cache_blob(blob, prog);
+}
 
-   prog->driver_cache_blob = ralloc_size(NULL, blob->size);
-   memcpy(prog->driver_cache_blob, blob->data, blob->size);
-   prog->driver_cache_blob_size = blob->size;
+static void
+write_nir_to_cache(struct blob *blob, struct gl_program *prog)
+{
+   nir_serialize(blob, prog->nir);
+   copy_blob_to_driver_cache_blob(blob, prog);
 }
 
-void
-st_serialise_tgsi_program(struct gl_context *ctx, struct gl_program *prog)
+static void
+st_serialise_ir_program(struct gl_context *ctx, struct gl_program *prog,
+bool nir)
 {
struct blob blob;
blob_init();
@@ -73,8 +88,12 @@ st_serialise_tgsi_program(struct gl_context *ctx, struct 
gl_program *prog)
sizeof(stvp->result_to_output));
 
   write_stream_out_to_cache(, >tgsi);
-  write_tgsi_to_cache(, stvp->tgsi.tokens, prog,
-  stvp->num_tgsi_tokens);
+
+  if (nir)
+ write_nir_to_cache(, prog);
+  else
+ write_tgsi_to_cache(, stvp->tgsi.tokens, prog,
+ stvp->num_tgsi_tokens);
   break;
}
case MESA_SHADER_TESS_CTRL:
@@ -83,22 +102,32 @@ st_serialise_tgsi_program(struct gl_context *ctx, struct 
gl_program *prog)
   struct st_common_program *stcp = (struct st_common_program *) prog;
 
   write_stream_out_to_cache(, >tgsi);
-  write_tgsi_to_cache(, stcp->tgsi.tokens, prog,
-  stcp->num_tgsi_tokens);
+
+  if (nir)
+ write_nir_to_cache(, prog);
+  else
+ write_tgsi_to_cache(, stcp->tgsi.tokens, prog,
+ stcp->num_tgsi_tokens);
   break;
}
case MESA_SHADER_FRAGMENT: {
   struct 

[Mesa-dev] [PATCH v2 1/3] st/glsl_to_tgsi: move nir detection earlier

[Timothy Arceri]

We move the nir check before the shader cache call so that we can
call a nir based caching function in a following patch.

Also with this change we simply check if vertex shaders support
NIR rather than looping over the stages as mixing of shader types
is not supported anyway.
---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 15 +++
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 84ed614927..355ba28218 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -6916,15 +6916,20 @@ extern "C" {
 GLboolean
 st_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
 {
+   struct pipe_screen *pscreen = ctx->st->pipe->screen;
+
+   enum pipe_shader_ir preferred_ir = (enum pipe_shader_ir)
+  pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX,
+PIPE_SHADER_CAP_PREFERRED_IR);
+   bool use_nir = preferred_ir == PIPE_SHADER_IR_NIR;
+
/* Return early if we are loading the shader from on-disk cache */
if (st_load_tgsi_from_disk_cache(ctx, prog)) {
   return GL_TRUE;
}
 
-   struct pipe_screen *pscreen = ctx->st->pipe->screen;
assert(prog->data->LinkStatus);
 
-   bool use_nir = false;
for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
   if (prog->_LinkedShaders[i] == NULL)
  continue;
@@ -6944,12 +6949,6 @@ st_link_shader(struct gl_context *ctx, struct 
gl_shader_program *prog)
   unsigned if_threshold = pscreen->get_shader_param(pscreen, ptarget,
 
PIPE_SHADER_CAP_LOWER_IF_THRESHOLD);
 
-  enum pipe_shader_ir preferred_ir = (enum pipe_shader_ir)
- pscreen->get_shader_param(pscreen, ptarget,
-   PIPE_SHADER_CAP_PREFERRED_IR);
-  if (preferred_ir == PIPE_SHADER_IR_NIR)
- use_nir = true;
-
   /* If there are forms of indirect addressing that the driver
* cannot handle, perform the lowering pass.
*/
-- 
2.14.3

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Re: [Mesa-dev] [PATCH 11/11] r600/radeonsi/clover: always assume PIPE_SHADER_IR_NATIVE for clover

[Jan Vesely]

On Fri, 2018-02-02 at 15:03 +1100, Timothy Arceri wrote:
> When PIPE_SHADER_IR_LLVM existed this query made sense but now it
> always returns PIPE_SHADER_IR_NATIVE. Also it is now conlicting
> with PIPE_SHADER_IR_NIR for compute shaders, so just assume this
> is always PIPE_SHADER_IR_NATIVE for clover.
> 
> This change indirectly enables NIR support for compute shaders
> on radeonsi.
> ---
>  src/gallium/drivers/r600/r600_pipe.c  | 6 +-
>  src/gallium/drivers/radeonsi/si_get.c | 3 ---
>  src/gallium/state_trackers/clover/core/device.cpp | 3 +--
>  3 files changed, 2 insertions(+), 10 deletions(-)
> 
> diff --git a/src/gallium/drivers/r600/r600_pipe.c 
> b/src/gallium/drivers/r600/r600_pipe.c
> index 6c021e568d..287fe497ca 100644
> --- a/src/gallium/drivers/r600/r600_pipe.c
> +++ b/src/gallium/drivers/r600/r600_pipe.c
> @@ -595,11 +595,7 @@ static int r600_get_shader_param(struct pipe_screen* 
> pscreen,
>   case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
>   return 16;
>  case PIPE_SHADER_CAP_PREFERRED_IR:
> - if (shader == PIPE_SHADER_COMPUTE) {
> - return PIPE_SHADER_IR_NATIVE;
> - } else {
> - return PIPE_SHADER_IR_TGSI;
> - }
> + return PIPE_SHADER_IR_TGSI;
>   case PIPE_SHADER_CAP_SUPPORTED_IRS:
>   if (rscreen->b.family >= CHIP_CEDAR)
>   return (1 << PIPE_SHADER_IR_TGSI);
> diff --git a/src/gallium/drivers/radeonsi/si_get.c 
> b/src/gallium/drivers/radeonsi/si_get.c
> index 40f4cc267e..46cc190db1 100644
> --- a/src/gallium/drivers/radeonsi/si_get.c
> +++ b/src/gallium/drivers/radeonsi/si_get.c
> @@ -391,9 +391,6 @@ static int si_get_shader_param(struct pipe_screen* 
> pscreen,
>   break;
>   case PIPE_SHADER_COMPUTE:
>   switch (param) {
> - case PIPE_SHADER_CAP_PREFERRED_IR:
> - return PIPE_SHADER_IR_NATIVE;
> -
>   case PIPE_SHADER_CAP_SUPPORTED_IRS: {
>   int ir = 1 << PIPE_SHADER_IR_NATIVE;
>  
> diff --git a/src/gallium/state_trackers/clover/core/device.cpp 
> b/src/gallium/state_trackers/clover/core/device.cpp
> index 9dd7eed3f1..116f0c7604 100644
> --- a/src/gallium/state_trackers/clover/core/device.cpp
> +++ b/src/gallium/state_trackers/clover/core/device.cpp
> @@ -243,8 +243,7 @@ device::vendor_name() const {
>  
>  enum pipe_shader_ir
>  device::ir_format() const {
> -   return (enum pipe_shader_ir) pipe->get_shader_param(
> -  pipe, PIPE_SHADER_COMPUTE, PIPE_SHADER_CAP_PREFERRED_IR);
> +   return PIPE_SHADER_IR_NATIVE;

This looks like it forces IR_NATIVE for absolutely everybody. Why
should other devices use IR_NATIVE just because radeonsi wants
experimental NIR for GL?

Jan

>  }
>  
>  std::string

-- 
Jan Vesely 

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[Mesa-dev] [PATCH] r600/eg: use texture target to pick array size not view target (v2)

[Dave Airlie]

From: Dave Airlie 

This fixes a few CTS cases in :
KHR-GL45.texture_view.view_sampling

some multisample cases are still broken, but not sure this is
the same problem.

v2: fix more cases

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/evergreen_state.c | 17 ++---
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 63a39a23f8..90f05c06d3 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -811,18 +811,21 @@ static int evergreen_fill_tex_resource_words(struct 
r600_context *rctx,
}
nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
 
-   if (params->target == PIPE_TEXTURE_1D_ARRAY) {
-   height = 1;
-   depth = texture->array_size;
-   } else if (params->target == PIPE_TEXTURE_2D_ARRAY) {
-   depth = texture->array_size;
-   } else if (params->target == PIPE_TEXTURE_CUBE_ARRAY)
-   depth = texture->array_size / 6;
 
va = tmp->resource.gpu_address;
 
/* array type views and views into array types need to use layer offset 
*/
dim = r600_tex_dim(tmp, params->target, texture->nr_samples);
+
+   if (dim == V_03_SQ_TEX_DIM_1D_ARRAY) {
+   height = 1;
+   depth = texture->array_size;
+   } else if (dim == V_03_SQ_TEX_DIM_2D_ARRAY ||
+  dim == V_03_SQ_TEX_DIM_2D_ARRAY_MSAA) {
+   depth = texture->array_size;
+   } else if (dim == V_03_SQ_TEX_DIM_CUBEMAP)
+   depth = texture->array_size / 6;
+
tex_resource_words[0] = (S_03_DIM(dim) |
 S_03_PITCH((pitch / 8) - 1) |
 S_03_TEX_WIDTH(width - 1));
-- 
2.14.3

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Re: [Mesa-dev] [PATCH 2/9] glsl: add u64->fp64 and i64->fp64 builtins.

[Dave Airlie]

On 2 February 2018 at 03:40, Roland Scheidegger  wrote:
> I suppose this is a bit inefficient if the hw actually supports some
> double ops?
> I mean for uint->double you could just convert the low 8 bits and high
> 24 bits (or different split) separately to float, convert both to double
> and add them. (I think should work for int->double exactly the same
> despite the sign bit.)
> But in any case, for hw not supporting double ops at all this looks like
> the right approach.

I've sent a patch that did this instead, definitely smaller instructions count.

Consider this series dropped for now, Elie don't worry we'll get soft
fp64 in there yet :-)

Dave.
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Re: [Mesa-dev] [PATCH 11/11] r600/radeonsi/clover: always assume PIPE_SHADER_IR_NATIVE for clover

[Timothy Arceri]

On 02/02/18 15:12, Ilia Mirkin wrote:

Seems like the proper solution to this problem is to use something
like ST_DEBUG=nir (which would in turn check the SUPPORTED_IRS bitmap)
rather than trying to hack drivers...


That sounds like more of a hack to me. What happend when nir becomes the 
default? As it stands PIPE_SHADER_CAP_PREFERRED_IR is being used for 2
different uses cases. 1. for getting the preferred IR to be used with 
clover and 2. for getting the IR to be used with OpenGL.


The use case for clover is used to include PIPE_SHADER_IR_LLVM but that 
has been gone for a while now, so it's not really needed anymore. IMO 
this patch improves on the current situation.




On Thu, Feb 1, 2018 at 11:03 PM, Timothy Arceri  wrote:

When PIPE_SHADER_IR_LLVM existed this query made sense but now it
always returns PIPE_SHADER_IR_NATIVE. Also it is now conlicting
with PIPE_SHADER_IR_NIR for compute shaders, so just assume this
is always PIPE_SHADER_IR_NATIVE for clover.

This change indirectly enables NIR support for compute shaders
on radeonsi.
---
  src/gallium/drivers/r600/r600_pipe.c  | 6 +-
  src/gallium/drivers/radeonsi/si_get.c | 3 ---
  src/gallium/state_trackers/clover/core/device.cpp | 3 +--
  3 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_pipe.c 
b/src/gallium/drivers/r600/r600_pipe.c
index 6c021e568d..287fe497ca 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -595,11 +595,7 @@ static int r600_get_shader_param(struct pipe_screen* 
pscreen,
 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 return 16;
  case PIPE_SHADER_CAP_PREFERRED_IR:
-   if (shader == PIPE_SHADER_COMPUTE) {
-   return PIPE_SHADER_IR_NATIVE;
-   } else {
-   return PIPE_SHADER_IR_TGSI;
-   }
+   return PIPE_SHADER_IR_TGSI;
 case PIPE_SHADER_CAP_SUPPORTED_IRS:
 if (rscreen->b.family >= CHIP_CEDAR)
 return (1 << PIPE_SHADER_IR_TGSI);
diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c
index 40f4cc267e..46cc190db1 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -391,9 +391,6 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
 break;
 case PIPE_SHADER_COMPUTE:
 switch (param) {
-   case PIPE_SHADER_CAP_PREFERRED_IR:
-   return PIPE_SHADER_IR_NATIVE;
-
 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 int ir = 1 << PIPE_SHADER_IR_NATIVE;

diff --git a/src/gallium/state_trackers/clover/core/device.cpp 
b/src/gallium/state_trackers/clover/core/device.cpp
index 9dd7eed3f1..116f0c7604 100644
--- a/src/gallium/state_trackers/clover/core/device.cpp
+++ b/src/gallium/state_trackers/clover/core/device.cpp
@@ -243,8 +243,7 @@ device::vendor_name() const {

  enum pipe_shader_ir
  device::ir_format() const {
-   return (enum pipe_shader_ir) pipe->get_shader_param(
-  pipe, PIPE_SHADER_COMPUTE, PIPE_SHADER_CAP_PREFERRED_IR);
+   return PIPE_SHADER_IR_NATIVE;
  }

  std::string
--
2.14.3

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[Mesa-dev] [PATCH] r600/fp64: fix integer->double conversion

[Dave Airlie]

From: Dave Airlie 

Doing a straight uint/int->fp32->fp64 conversion causes
some precision issues, Roland suggested splitting the
integer into two portions and doing two separate
int->fp32->fp64 conversions then adding the results.

This passes the tests in CTS and piglit.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/r600_shader.c | 118 +
 1 file changed, 90 insertions(+), 28 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 13aa681049..22f2736b03 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -4490,44 +4490,106 @@ static int egcm_int_to_double(struct r600_shader_ctx 
*ctx)
 {
struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
struct r600_bytecode_alu alu;
-   int i, r;
-   int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
+   int i, c, r;
+   int write_mask = inst->Dst[0].Register.WriteMask;
+   int temp_reg = r600_get_temp(ctx);
 
assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
inst->Instruction.Opcode == TGSI_OPCODE_U2D);
 
-   for (i = 0; i <= (lasti+1)/2; i++) {
-   memset(, 0, sizeof(struct r600_bytecode_alu));
-   alu.op = ctx->inst_info->op;
-
-   r600_bytecode_src([0], >src[0], i);
-   alu.dst.sel = ctx->temp_reg;
-   alu.dst.chan = i;
-   alu.dst.write = 1;
-   alu.last = 1;
+   for (c = 0; c < 2; c++) {
+   int dchan = c * 2;
+   if (write_mask & (0x3 << dchan)) {
+   /* split into 24-bit int and 8-bit int */
+   memset(, 0, sizeof(struct r600_bytecode_alu));
+   alu.op = ALU_OP2_AND_INT;
+   alu.dst.sel = temp_reg;
+   alu.dst.chan = dchan;
+   r600_bytecode_src([0], >src[0], c);
+   alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
+   alu.src[1].value = 0xff00;
+   alu.dst.write = 1;
+   r = r600_bytecode_add_alu(ctx->bc, );
+   if (r)
+   return r;
 
-   r = r600_bytecode_add_alu(ctx->bc, );
-   if (r)
-   return r;
+   memset(, 0, sizeof(struct r600_bytecode_alu));
+   alu.op = ALU_OP2_AND_INT;
+   alu.dst.sel = temp_reg;
+   alu.dst.chan = dchan + 1;
+   r600_bytecode_src([0], >src[0], c);
+   alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
+   alu.src[1].value = 0xff;
+   alu.dst.write = 1;
+   alu.last = 1;
+   r = r600_bytecode_add_alu(ctx->bc, );
+   if (r)
+   return r;
+   }
}
 
-   for (i = 0; i <= lasti; i++) {
-   memset(, 0, sizeof(struct r600_bytecode_alu));
-   alu.op = ALU_OP1_FLT32_TO_FLT64;
+   for (c = 0; c < 2; c++) {
+   int dchan = c * 2;
+   if (write_mask & (0x3 << dchan)) {
+   for (i = dchan; i <= dchan + 1; i++) {
+   memset(, 0, sizeof(struct 
r600_bytecode_alu));
+   alu.op = i == dchan ? ctx->inst_info->op : 
ALU_OP1_UINT_TO_FLT;
 
-   alu.src[0].chan = i/2;
-   if (i%2 == 0)
-   alu.src[0].sel = ctx->temp_reg;
-   else {
-   alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
-   alu.src[0].value = 0x0;
+   alu.src[0].sel = temp_reg;
+   alu.src[0].chan = i;
+   alu.dst.sel = temp_reg;
+   alu.dst.chan = i;
+   alu.dst.write = 1;
+   alu.last = i == dchan + 1;
+
+   r = r600_bytecode_add_alu(ctx->bc, );
+   if (r)
+   return r;
+   }
}
-   tgsi_dst(ctx, >Dst[0], i, );
-   alu.last = i == lasti;
+   }
 
-   r = r600_bytecode_add_alu(ctx->bc, );
-   if (r)
-   return r;
+   for (c = 0; c < 2; c++) {
+   int dchan = c * 2;
+   if (write_mask & (0x3 << dchan)) {
+   for (i = 0; i < 4; i++) {
+   memset(, 0, sizeof(struct 
r600_bytecode_alu));
+   alu.op = ALU_OP1_FLT32_TO_FLT64;
+
+   alu.src[0].chan = dchan + (i / 2);
+   

Re: [Mesa-dev] [PATCH 11/11] r600/radeonsi/clover: always assume PIPE_SHADER_IR_NATIVE for clover

[Ilia Mirkin]

Seems like the proper solution to this problem is to use something
like ST_DEBUG=nir (which would in turn check the SUPPORTED_IRS bitmap)
rather than trying to hack drivers...

On Thu, Feb 1, 2018 at 11:03 PM, Timothy Arceri  wrote:
> When PIPE_SHADER_IR_LLVM existed this query made sense but now it
> always returns PIPE_SHADER_IR_NATIVE. Also it is now conlicting
> with PIPE_SHADER_IR_NIR for compute shaders, so just assume this
> is always PIPE_SHADER_IR_NATIVE for clover.
>
> This change indirectly enables NIR support for compute shaders
> on radeonsi.
> ---
>  src/gallium/drivers/r600/r600_pipe.c  | 6 +-
>  src/gallium/drivers/radeonsi/si_get.c | 3 ---
>  src/gallium/state_trackers/clover/core/device.cpp | 3 +--
>  3 files changed, 2 insertions(+), 10 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/r600_pipe.c 
> b/src/gallium/drivers/r600/r600_pipe.c
> index 6c021e568d..287fe497ca 100644
> --- a/src/gallium/drivers/r600/r600_pipe.c
> +++ b/src/gallium/drivers/r600/r600_pipe.c
> @@ -595,11 +595,7 @@ static int r600_get_shader_param(struct pipe_screen* 
> pscreen,
> case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
> return 16;
>  case PIPE_SHADER_CAP_PREFERRED_IR:
> -   if (shader == PIPE_SHADER_COMPUTE) {
> -   return PIPE_SHADER_IR_NATIVE;
> -   } else {
> -   return PIPE_SHADER_IR_TGSI;
> -   }
> +   return PIPE_SHADER_IR_TGSI;
> case PIPE_SHADER_CAP_SUPPORTED_IRS:
> if (rscreen->b.family >= CHIP_CEDAR)
> return (1 << PIPE_SHADER_IR_TGSI);
> diff --git a/src/gallium/drivers/radeonsi/si_get.c 
> b/src/gallium/drivers/radeonsi/si_get.c
> index 40f4cc267e..46cc190db1 100644
> --- a/src/gallium/drivers/radeonsi/si_get.c
> +++ b/src/gallium/drivers/radeonsi/si_get.c
> @@ -391,9 +391,6 @@ static int si_get_shader_param(struct pipe_screen* 
> pscreen,
> break;
> case PIPE_SHADER_COMPUTE:
> switch (param) {
> -   case PIPE_SHADER_CAP_PREFERRED_IR:
> -   return PIPE_SHADER_IR_NATIVE;
> -
> case PIPE_SHADER_CAP_SUPPORTED_IRS: {
> int ir = 1 << PIPE_SHADER_IR_NATIVE;
>
> diff --git a/src/gallium/state_trackers/clover/core/device.cpp 
> b/src/gallium/state_trackers/clover/core/device.cpp
> index 9dd7eed3f1..116f0c7604 100644
> --- a/src/gallium/state_trackers/clover/core/device.cpp
> +++ b/src/gallium/state_trackers/clover/core/device.cpp
> @@ -243,8 +243,7 @@ device::vendor_name() const {
>
>  enum pipe_shader_ir
>  device::ir_format() const {
> -   return (enum pipe_shader_ir) pipe->get_shader_param(
> -  pipe, PIPE_SHADER_COMPUTE, PIPE_SHADER_CAP_PREFERRED_IR);
> +   return PIPE_SHADER_IR_NATIVE;
>  }
>
>  std::string
> --
> 2.14.3
>
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[Mesa-dev] [PATCH 07/11] ac/radeonsi: create ac_build_shader_clock() helper

[Timothy Arceri]

---
 src/amd/common/ac_llvm_build.c   | 8 
 src/amd/common/ac_llvm_build.h   | 2 ++
 src/gallium/drivers/radeonsi/si_shader.c | 6 +-
 3 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 6afe7f9723..026550184f 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -343,6 +343,14 @@ ac_build_optimization_barrier(struct ac_llvm_context *ctx,
}
 }
 
+LLVMValueRef
+ac_build_shader_clock(struct ac_llvm_context *ctx)
+{
+   LLVMValueRef tmp = ac_build_intrinsic(ctx, "llvm.readcyclecounter",
+ ctx->i64, NULL, 0, 0);
+   return LLVMBuildBitCast(ctx->builder, tmp, ctx->v2i32, "");
+}
+
 LLVMValueRef
 ac_build_ballot(struct ac_llvm_context *ctx,
LLVMValueRef value)
diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
index 78437d603e..57e5c7b5c1 100644
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -118,6 +118,8 @@ ac_build_phi(struct ac_llvm_context *ctx, LLVMTypeRef type,
 void ac_build_optimization_barrier(struct ac_llvm_context *ctx,
   LLVMValueRef *pvgpr);
 
+LLVMValueRef ac_build_shader_clock(struct ac_llvm_context *ctx);
+
 LLVMValueRef ac_build_ballot(struct ac_llvm_context *ctx, LLVMValueRef value);
 
 LLVMValueRef ac_build_vote_all(struct ac_llvm_context *ctx, LLVMValueRef 
value);
diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index e262dc9192..08088450d7 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -3940,11 +3940,7 @@ static void clock_emit(
struct lp_build_emit_data *emit_data)
 {
struct si_shader_context *ctx = si_shader_context(bld_base);
-   LLVMValueRef tmp;
-
-   tmp = lp_build_intrinsic(ctx->ac.builder, "llvm.readcyclecounter",
-ctx->i64, NULL, 0, 0);
-   tmp = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->v2i32, "");
+   LLVMValueRef tmp = ac_build_shader_clock(>ac);
 
emit_data->output[0] =
LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
-- 
2.14.3

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[Mesa-dev] [PATCH 03/11] ac/radeonsi: add local_invocation_ids to the abi

[Timothy Arceri]

---
 src/amd/common/ac_nir_to_llvm.c   | 5 ++---
 src/amd/common/ac_shader_abi.h| 2 ++
 src/gallium/drivers/radeonsi/si_shader.c  | 4 ++--
 src/gallium/drivers/radeonsi/si_shader_internal.h | 1 -
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 60702d47d3..570c798d4e 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -91,7 +91,6 @@ struct nir_to_llvm_context {
LLVMValueRef push_constants;
LLVMValueRef view_index;
LLVMValueRef num_work_groups;
-   LLVMValueRef local_invocation_ids;
LLVMValueRef tg_size;
 
LLVMValueRef vertex_buffers;
@@ -795,7 +794,7 @@ static void create_function(struct nir_to_llvm_context *ctx,
if (ctx->shader_info->info.cs.uses_local_invocation_idx)
add_arg(, ARG_SGPR, ctx->ac.i32, >tg_size);
add_arg(, ARG_VGPR, ctx->ac.v3i32,
-   >local_invocation_ids);
+   >abi.local_invocation_ids);
break;
case MESA_SHADER_VERTEX:
declare_global_input_sgprs(ctx, stage, has_previous_stage,
@@ -4323,7 +4322,7 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
break;
}
case nir_intrinsic_load_local_invocation_id: {
-   result = ctx->nctx->local_invocation_ids;
+   result = ctx->abi->local_invocation_ids;
break;
}
case nir_intrinsic_load_base_instance:
diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index 3d3dcc2e8e..9a35ff925b 100644
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -54,6 +54,8 @@ struct ac_shader_abi {
LLVMValueRef ancillary;
LLVMValueRef sample_coverage;
LLVMValueRef prim_mask;
+   /* CS */
+   LLVMValueRef local_invocation_ids;
LLVMValueRef workgroup_ids[3];
 
/* For VS and PS: pre-loaded shader inputs.
diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 5b420edf5c..74a221c809 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2154,7 +2154,7 @@ void si_load_system_value(struct si_shader_context *ctx,
}
 
case TGSI_SEMANTIC_THREAD_ID:
-   value = LLVMGetParam(ctx->main_fn, ctx->param_thread_id);
+   value = ctx->abi.local_invocation_ids;
break;
 
case TGSI_SEMANTIC_HELPER_INVOCATION:
@@ -4953,7 +4953,7 @@ static void create_function(struct si_shader_context *ctx)
add_arg_assign(, ARG_SGPR, ctx->i32, 
>abi.workgroup_ids[i]);
}
 
-   ctx->param_thread_id = add_arg(, ARG_VGPR, v3i32);
+   add_arg_assign(, ARG_VGPR, v3i32, 
>abi.local_invocation_ids);
break;
default:
assert(0 && "unimplemented shader");
diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h 
b/src/gallium/drivers/radeonsi/si_shader_internal.h
index 202778e04d..c0d83fb93e 100644
--- a/src/gallium/drivers/radeonsi/si_shader_internal.h
+++ b/src/gallium/drivers/radeonsi/si_shader_internal.h
@@ -186,7 +186,6 @@ struct si_shader_context {
/* CS */
int param_grid_size;
int param_block_size;
-   int param_thread_id;
 
LLVMTargetMachineRef tm;
 
-- 
2.14.3

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[Mesa-dev] [PATCH 05/11] radeonsi: add get_block_size() helper

[Timothy Arceri]

This will be reused by the nir backend in a later patch.
---
 src/gallium/drivers/radeonsi/si_shader.c | 47 ++--
 1 file changed, 27 insertions(+), 20 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 74a221c809..2c538d55a0 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1867,6 +1867,32 @@ static LLVMValueRef get_sample_id(struct 
si_shader_context *ctx)
return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
 }
 
+static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
+{
+   struct si_shader_context *ctx = si_shader_context_from_abi(abi);
+
+   LLVMValueRef values[3];
+   LLVMValueRef result;
+   unsigned i;
+   unsigned *properties = ctx->shader->selector->info.properties;
+
+   if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
+   unsigned sizes[3] = {
+   properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
+   properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
+   properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
+   };
+
+   for (i = 0; i < 3; ++i)
+   values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
+
+   result = lp_build_gather_values(>gallivm, values, 3);
+   } else {
+   result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
+   }
+
+   return result;
+}
 
 /**
  * Load a dword from a constant buffer.
@@ -2117,27 +2143,8 @@ void si_load_system_value(struct si_shader_context *ctx,
break;
 
case TGSI_SEMANTIC_BLOCK_SIZE:
-   {
-   LLVMValueRef values[3];
-   unsigned i;
-   unsigned *properties = ctx->shader->selector->info.properties;
-
-   if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
-   unsigned sizes[3] = {
-   properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
-   properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
-   properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
-   };
-
-   for (i = 0; i < 3; ++i)
-   values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
-
-   value = lp_build_gather_values(>gallivm, values, 
3);
-   } else {
-   value = LLVMGetParam(ctx->main_fn, 
ctx->param_block_size);
-   }
+   value = get_block_size(>abi);
break;
-   }
 
case TGSI_SEMANTIC_BLOCK_ID:
{
-- 
2.14.3

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[Mesa-dev] [PATCH 10/11] radeonsi/nir: add nir support for compiling compute shaders

[Timothy Arceri]

---
 src/gallium/drivers/radeonsi/si_compute.c | 44 ++-
 src/gallium/drivers/radeonsi/si_compute.h |  5 +++-
 src/gallium/drivers/radeonsi/si_get.c |  8 +++---
 3 files changed, 39 insertions(+), 18 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_compute.c 
b/src/gallium/drivers/radeonsi/si_compute.c
index ac4fab3ea0..93d720272c 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -98,8 +98,19 @@ static void si_create_compute_state_async(void *job, int 
thread_index)
memset(, 0, sizeof(sel));
 
sel.screen = program->screen;
-   tgsi_scan_shader(program->tokens, );
-   sel.tokens = program->tokens;
+
+   if (program->ir_type == PIPE_SHADER_IR_TGSI) {
+   tgsi_scan_shader(program->ir.tgsi, );
+   sel.tokens = program->ir.tgsi;
+   } else {
+   assert(program->ir_type == PIPE_SHADER_IR_NIR);
+   sel.nir = program->ir.nir;
+
+   si_nir_scan_shader(sel.nir, );
+   si_lower_nir();
+   }
+
+
sel.type = PIPE_SHADER_COMPUTE;
sel.local_size = program->local_size;
si_get_active_slot_masks(,
@@ -141,7 +152,9 @@ static void si_create_compute_state_async(void *job, int 
thread_index)
sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] 
== 0;
}
 
-   FREE(program->tokens);
+   if (program->ir_type == PIPE_SHADER_IR_TGSI)
+   FREE(program->ir.tgsi);
+
program->shader.selector = NULL;
 }
 
@@ -162,11 +175,16 @@ static void *si_create_compute_state(
program->use_code_object_v2 = HAVE_LLVM >= 0x0400 &&
cso->ir_type == PIPE_SHADER_IR_NATIVE;
 
-   if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
-   program->tokens = tgsi_dup_tokens(cso->prog);
-   if (!program->tokens) {
-   FREE(program);
-   return NULL;
+   if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
+   if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
+   program->ir.tgsi = tgsi_dup_tokens(cso->prog);
+   if (!program->ir.tgsi) {
+   FREE(program);
+   return NULL;
+   }
+   } else {
+   assert(cso->ir_type == PIPE_SHADER_IR_NIR);
+   program->ir.nir = (struct nir_shader *) cso->prog;
}
 
program->compiler_ctx_state.debug = sctx->debug;
@@ -231,7 +249,7 @@ static void si_bind_compute_state(struct pipe_context *ctx, 
void *state)
return;
 
/* Wait because we need active slot usage masks. */
-   if (program->ir_type == PIPE_SHADER_IR_TGSI)
+   if (program->ir_type != PIPE_SHADER_IR_NATIVE)
util_queue_fence_wait(>ready);
 
si_set_active_descriptors(sctx,
@@ -380,7 +398,7 @@ static bool si_switch_compute_shader(struct si_context 
*sctx,
sctx->cs_shader_state.offset == offset)
return true;
 
-   if (program->ir_type == PIPE_SHADER_IR_TGSI) {
+   if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
config = >config;
} else {
unsigned lds_blocks;
@@ -806,7 +824,7 @@ static void si_launch_grid(
sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 SI_CONTEXT_CS_PARTIAL_FLUSH;
 
-   if (program->ir_type == PIPE_SHADER_IR_TGSI &&
+   if (program->ir_type != PIPE_SHADER_IR_NATIVE &&
program->shader.compilation_failed)
return;
 
@@ -871,7 +889,7 @@ static void si_launch_grid(
  RADEON_PRIO_COMPUTE_GLOBAL);
}
 
-   if (program->ir_type == PIPE_SHADER_IR_TGSI)
+   if (program->ir_type != PIPE_SHADER_IR_NATIVE)
si_setup_tgsi_grid(sctx, info);
 
si_emit_dispatch_packets(sctx, info);
@@ -892,7 +910,7 @@ static void si_launch_grid(
 
 void si_destroy_compute(struct si_compute *program)
 {
-   if (program->ir_type == PIPE_SHADER_IR_TGSI) {
+   if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
util_queue_drop_job(>screen->shader_compiler_queue,
>ready);
util_queue_fence_destroy(>ready);
diff --git a/src/gallium/drivers/radeonsi/si_compute.h 
b/src/gallium/drivers/radeonsi/si_compute.h
index c19b701fc7..ec411588f6 100644
--- a/src/gallium/drivers/radeonsi/si_compute.h
+++ b/src/gallium/drivers/radeonsi/si_compute.h
@@ -33,7 +33,10 @@
 struct si_compute {
struct pipe_reference reference;
struct si_screen *screen;
-   struct tgsi_token *tokens;
+   union {
+   struct tgsi_token *tgsi;
+   struct nir_shader *nir;
+   } ir;
struct util_queue_fence ready;
struct 

[Mesa-dev] [PATCH 09/11] ac/radeonsi: add num_work_groups to the abi

[Timothy Arceri]

---
 src/amd/common/ac_nir_to_llvm.c   | 5 ++---
 src/amd/common/ac_shader_abi.h| 1 +
 src/gallium/drivers/radeonsi/si_shader.c  | 4 ++--
 src/gallium/drivers/radeonsi/si_shader_internal.h | 1 -
 4 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index bf36c7ef84..28f73a30b3 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -90,7 +90,6 @@ struct nir_to_llvm_context {
LLVMValueRef ring_offsets;
LLVMValueRef push_constants;
LLVMValueRef view_index;
-   LLVMValueRef num_work_groups;
LLVMValueRef tg_size;
 
LLVMValueRef vertex_buffers;
@@ -780,7 +779,7 @@ static void create_function(struct nir_to_llvm_context *ctx,
 
if (ctx->shader_info->info.cs.uses_grid_size) {
add_arg(, ARG_SGPR, ctx->ac.v3i32,
-   >num_work_groups);
+   >abi.num_work_groups);
}
 
for (int i = 0; i < 3; i++) {
@@ -4385,7 +4384,7 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
result = ctx->abi->instance_id;
break;
case nir_intrinsic_load_num_work_groups:
-   result = ctx->nctx->num_work_groups;
+   result = ctx->abi->num_work_groups;
break;
case nir_intrinsic_load_local_invocation_index:
result = visit_load_local_invocation_index(ctx->nctx);
diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index 55842ea342..9499c1a15f 100644
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -56,6 +56,7 @@ struct ac_shader_abi {
LLVMValueRef prim_mask;
/* CS */
LLVMValueRef local_invocation_ids;
+   LLVMValueRef num_work_groups;
LLVMValueRef workgroup_ids[3];
 
/* For VS and PS: pre-loaded shader inputs.
diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 08088450d7..797450845b 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2139,7 +2139,7 @@ void si_load_system_value(struct si_shader_context *ctx,
break;
 
case TGSI_SEMANTIC_GRID_SIZE:
-   value = LLVMGetParam(ctx->main_fn, ctx->param_grid_size);
+   value = ctx->abi.num_work_groups;
break;
 
case TGSI_SEMANTIC_BLOCK_SIZE:
@@ -4946,7 +4946,7 @@ static void create_function(struct si_shader_context *ctx)
declare_global_desc_pointers(ctx, );
declare_per_stage_desc_pointers(ctx, , true);
if (shader->selector->info.uses_grid_size)
-   ctx->param_grid_size = add_arg(, ARG_SGPR, 
v3i32);
+   add_arg_assign(, ARG_SGPR, v3i32, 
>abi.num_work_groups);
if (shader->selector->info.uses_block_size)
ctx->param_block_size = add_arg(, ARG_SGPR, 
v3i32);
 
diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h 
b/src/gallium/drivers/radeonsi/si_shader_internal.h
index c0d83fb93e..aec0fe3102 100644
--- a/src/gallium/drivers/radeonsi/si_shader_internal.h
+++ b/src/gallium/drivers/radeonsi/si_shader_internal.h
@@ -184,7 +184,6 @@ struct si_shader_context {
int param_gs_vtx23_offset; /* in dwords (GFX9) */
int param_gs_vtx45_offset; /* in dwords (GFX9) */
/* CS */
-   int param_grid_size;
int param_block_size;
 
LLVMTargetMachineRef tm;
-- 
2.14.3

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[Mesa-dev] [PATCH 11/11] r600/radeonsi/clover: always assume PIPE_SHADER_IR_NATIVE for clover

[Timothy Arceri]

When PIPE_SHADER_IR_LLVM existed this query made sense but now it
always returns PIPE_SHADER_IR_NATIVE. Also it is now conlicting
with PIPE_SHADER_IR_NIR for compute shaders, so just assume this
is always PIPE_SHADER_IR_NATIVE for clover.

This change indirectly enables NIR support for compute shaders
on radeonsi.
---
 src/gallium/drivers/r600/r600_pipe.c  | 6 +-
 src/gallium/drivers/radeonsi/si_get.c | 3 ---
 src/gallium/state_trackers/clover/core/device.cpp | 3 +--
 3 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_pipe.c 
b/src/gallium/drivers/r600/r600_pipe.c
index 6c021e568d..287fe497ca 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -595,11 +595,7 @@ static int r600_get_shader_param(struct pipe_screen* 
pscreen,
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return 16;
 case PIPE_SHADER_CAP_PREFERRED_IR:
-   if (shader == PIPE_SHADER_COMPUTE) {
-   return PIPE_SHADER_IR_NATIVE;
-   } else {
-   return PIPE_SHADER_IR_TGSI;
-   }
+   return PIPE_SHADER_IR_TGSI;
case PIPE_SHADER_CAP_SUPPORTED_IRS:
if (rscreen->b.family >= CHIP_CEDAR)
return (1 << PIPE_SHADER_IR_TGSI);
diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c
index 40f4cc267e..46cc190db1 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -391,9 +391,6 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
break;
case PIPE_SHADER_COMPUTE:
switch (param) {
-   case PIPE_SHADER_CAP_PREFERRED_IR:
-   return PIPE_SHADER_IR_NATIVE;
-
case PIPE_SHADER_CAP_SUPPORTED_IRS: {
int ir = 1 << PIPE_SHADER_IR_NATIVE;
 
diff --git a/src/gallium/state_trackers/clover/core/device.cpp 
b/src/gallium/state_trackers/clover/core/device.cpp
index 9dd7eed3f1..116f0c7604 100644
--- a/src/gallium/state_trackers/clover/core/device.cpp
+++ b/src/gallium/state_trackers/clover/core/device.cpp
@@ -243,8 +243,7 @@ device::vendor_name() const {
 
 enum pipe_shader_ir
 device::ir_format() const {
-   return (enum pipe_shader_ir) pipe->get_shader_param(
-  pipe, PIPE_SHADER_COMPUTE, PIPE_SHADER_CAP_PREFERRED_IR);
+   return PIPE_SHADER_IR_NATIVE;
 }
 
 std::string
-- 
2.14.3

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[Mesa-dev] [PATCH 06/11] ac/radeonsi: add load_local_group_size() to the abi

[Timothy Arceri]

---
 src/amd/common/ac_nir_to_llvm.c  | 3 +++
 src/amd/common/ac_shader_abi.h   | 2 ++
 src/gallium/drivers/radeonsi/si_shader.c | 1 +
 3 files changed, 6 insertions(+)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index b2e72e109e..4c346119c3 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4317,6 +4317,9 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
result = ctx->abi->base_vertex;
break;
}
+   case nir_intrinsic_load_local_group_size:
+   result = ctx->abi->load_local_group_size(ctx->abi);
+   break;
case nir_intrinsic_load_vertex_id_zero_base: {
result = ctx->abi->vertex_id;
break;
diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index 9a35ff925b..55842ea342 100644
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -157,6 +157,8 @@ struct ac_shader_abi {
LLVMValueRef (*load_sample_position)(struct ac_shader_abi *abi,
 LLVMValueRef sample_id);
 
+   LLVMValueRef (*load_local_group_size)(struct ac_shader_abi *abi);
+
/* Whether to clamp the shadow reference value to [0,1]on VI. Radeonsi 
currently
 * uses it due to promoting D16 to D32, but radv needs it off. */
bool clamp_shadow_reference;
diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 2c538d55a0..e262dc9192 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -6038,6 +6038,7 @@ static bool si_compile_tgsi_main(struct si_shader_context 
*ctx,
ctx->abi.load_sample_position = load_sample_position;
break;
case PIPE_SHADER_COMPUTE:
+   ctx->abi.load_local_group_size = get_block_size;
break;
default:
assert(!"Unsupported shader type");
-- 
2.14.3

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[Mesa-dev] [PATCH 08/11] ac: implement nir_intrinsic_shader_clock

[Timothy Arceri]

---
 src/amd/common/ac_nir_to_llvm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 4c346119c3..bf36c7ef84 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4448,6 +4448,9 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
case nir_intrinsic_image_size:
result = visit_image_size(ctx, instr);
break;
+   case nir_intrinsic_shader_clock:
+   result = ac_build_shader_clock(>ac);
+   break;
case nir_intrinsic_discard:
case nir_intrinsic_discard_if:
emit_discard(ctx, instr);
-- 
2.14.3

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[Mesa-dev] radeonsi nir support for compute shaders

[Timothy Arceri]

Confiliting values returned by PIPE_SHADER_CAP_PREFERRED_IR meant
that compute for NIR was always disable before this series (see 
patch 11).

This series should contain everything except shared 
variable/atomic support, I intend to tackle those in a follow up
series.

Please review.

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[Mesa-dev] [PATCH 02/11] ac/radeonsi: add workgroup_ids to the abi

[Timothy Arceri]

---
 src/amd/common/ac_nir_to_llvm.c   | 9 -
 src/amd/common/ac_shader_abi.h| 1 +
 src/gallium/drivers/radeonsi/si_shader.c  | 9 -
 src/gallium/drivers/radeonsi/si_shader_internal.h | 1 -
 4 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index fd5989389b..60702d47d3 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -91,7 +91,6 @@ struct nir_to_llvm_context {
LLVMValueRef push_constants;
LLVMValueRef view_index;
LLVMValueRef num_work_groups;
-   LLVMValueRef workgroup_ids[3];
LLVMValueRef local_invocation_ids;
LLVMValueRef tg_size;
 
@@ -786,10 +785,10 @@ static void create_function(struct nir_to_llvm_context 
*ctx,
}
 
for (int i = 0; i < 3; i++) {
-   ctx->workgroup_ids[i] = NULL;
+   ctx->abi.workgroup_ids[i] = NULL;
if (ctx->shader_info->info.cs.uses_block_id[i]) {
add_arg(, ARG_SGPR, ctx->ac.i32,
-   >workgroup_ids[i]);
+   >abi.workgroup_ids[i]);
}
}
 
@@ -4308,8 +4307,8 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
LLVMValueRef values[3];
 
for (int i = 0; i < 3; i++) {
-   values[i] = ctx->nctx->workgroup_ids[i] ?
-   ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
+   values[i] = ctx->abi->workgroup_ids[i] ?
+   ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
}
 
result = ac_build_gather_values(>ac, values, 3);
diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index d9bb5a1e32..3d3dcc2e8e 100644
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -54,6 +54,7 @@ struct ac_shader_abi {
LLVMValueRef ancillary;
LLVMValueRef sample_coverage;
LLVMValueRef prim_mask;
+   LLVMValueRef workgroup_ids[3];
 
/* For VS and PS: pre-loaded shader inputs.
 *
diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 76215b318a..5b420edf5c 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2145,9 +2145,8 @@ void si_load_system_value(struct si_shader_context *ctx,
 
for (int i = 0; i < 3; i++) {
values[i] = ctx->i32_0;
-   if (ctx->param_block_id[i] >= 0) {
-   values[i] = LLVMGetParam(ctx->main_fn,
-
ctx->param_block_id[i]);
+   if (ctx->abi.workgroup_ids[i]) {
+   values[i] = ctx->abi.workgroup_ids[i];
}
}
value = lp_build_gather_values(>gallivm, values, 3);
@@ -4949,9 +4948,9 @@ static void create_function(struct si_shader_context *ctx)
ctx->param_block_size = add_arg(, ARG_SGPR, 
v3i32);
 
for (i = 0; i < 3; i++) {
-   ctx->param_block_id[i] = -1;
+   ctx->abi.workgroup_ids[i] = NULL;
if (shader->selector->info.uses_block_id[i])
-   ctx->param_block_id[i] = add_arg(, 
ARG_SGPR, ctx->i32);
+   add_arg_assign(, ARG_SGPR, ctx->i32, 
>abi.workgroup_ids[i]);
}
 
ctx->param_thread_id = add_arg(, ARG_VGPR, v3i32);
diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h 
b/src/gallium/drivers/radeonsi/si_shader_internal.h
index 489c468f03..202778e04d 100644
--- a/src/gallium/drivers/radeonsi/si_shader_internal.h
+++ b/src/gallium/drivers/radeonsi/si_shader_internal.h
@@ -186,7 +186,6 @@ struct si_shader_context {
/* CS */
int param_grid_size;
int param_block_size;
-   int param_block_id[3];
int param_thread_id;
 
LLVMTargetMachineRef tm;
-- 
2.14.3

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[Mesa-dev] [PATCH 04/11] ac: don't call emit_outputs() for compute

[Timothy Arceri]

---
 src/amd/common/ac_nir_to_llvm.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 570c798d4e..b2e72e109e 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -6758,8 +6758,9 @@ void ac_nir_translate(struct ac_llvm_context *ac, struct 
ac_shader_abi *abi,
visit_cf_list(, >impl->body);
phi_post_pass();
 
-   ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
- ctx.outputs);
+   if (nir->info.stage != MESA_SHADER_COMPUTE)
+   ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
+ ctx.outputs);
 
free(ctx.locals);
ralloc_free(ctx.defs);
-- 
2.14.3

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[Mesa-dev] [PATCH 01/11] radeonsi/nir: gather some compute info in si_nir_scan_shader()

[Timothy Arceri]

---
 src/gallium/drivers/radeonsi/si_shader_nir.c | 30 +++-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 128be585cd..28b031d935 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -86,6 +86,27 @@ static void scan_instruction(struct tgsi_shader_info *info,
case nir_intrinsic_load_invocation_id:
info->uses_invocationid = true;
break;
+   case nir_intrinsic_load_num_work_groups:
+   info->uses_grid_size = true;
+   break;
+   case nir_intrinsic_load_local_group_size:
+   /* The block size is translated to IMM with a fixed 
block size. */
+   if 
(info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
+   info->uses_block_size = true;
+   break;
+   case nir_intrinsic_load_local_invocation_id:
+   case nir_intrinsic_load_work_group_id: {
+   unsigned mask = 
nir_ssa_def_components_read(>dest.ssa);
+   while (mask) {
+   unsigned i = u_bit_scan();
+
+   if (intr->intrinsic == 
nir_intrinsic_load_work_group_id)
+   info->uses_block_id[i] = true;
+   else
+   info->uses_thread_id[i] = true;
+   }
+   break;
+   }
case nir_intrinsic_load_vertex_id:
info->uses_vertexid = 1;
break;
@@ -226,7 +247,8 @@ void si_nir_scan_shader(const struct nir_shader *nir,
   nir->info.stage == MESA_SHADER_GEOMETRY ||
   nir->info.stage == MESA_SHADER_TESS_CTRL ||
   nir->info.stage == MESA_SHADER_TESS_EVAL ||
-  nir->info.stage == MESA_SHADER_FRAGMENT);
+  nir->info.stage == MESA_SHADER_FRAGMENT ||
+  nir->info.stage == MESA_SHADER_COMPUTE);
 
info->processor = pipe_shader_type_from_mesa(nir->info.stage);
info->num_tokens = 2; /* indicate that the shader is non-empty */
@@ -261,6 +283,12 @@ void si_nir_scan_shader(const struct nir_shader *nir,
info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = 
nir->info.gs.invocations;
}
 
+   if (nir->info.stage == MESA_SHADER_COMPUTE) {
+   info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = 
nir->info.cs.local_size[0];
+   info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = 
nir->info.cs.local_size[1];
+   info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = 
nir->info.cs.local_size[2];
+   }
+
i = 0;
uint64_t processed_inputs = 0;
unsigned num_inputs = 0;
-- 
2.14.3

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Re: [Mesa-dev] [PATCH] mesa: don't flag _NEW_COLOR for KHR adv.blend if prog constant doesn't change

[Ian Romanick]

Reviewed-by: Ian Romanick 

I also ran it through our CI.

On 01/31/2018 11:54 AM, Marek Olšák wrote:
> From: Marek Olšák 
> 
> This only affects drivers that set DriverFlags.NewBlend.
> 
> v2: - fix typo advanded -> advanced
> - return "enum gl_advanced_blend_mode" from
>   _mesa_get_advanced_blend_sh_constant
> - don't call FLUSH_VERTICES twice
> ---
>  src/mesa/main/blend.c |  6 --
>  src/mesa/main/blend.h | 43 
> +++
>  src/mesa/main/enable.c| 14 +
>  src/mesa/program/prog_statevars.c |  3 ++-
>  4 files changed, 51 insertions(+), 15 deletions(-)
> 
> diff --git a/src/mesa/main/blend.c b/src/mesa/main/blend.c
> index 6b379f2..ec8e27e 100644
> --- a/src/mesa/main/blend.c
> +++ b/src/mesa/main/blend.c
> @@ -528,21 +528,22 @@ _mesa_BlendEquation( GLenum mode )
>  
> if (!changed)
>return;
>  
>  
> if (!legal_simple_blend_equation(ctx, mode) && !advanced_mode) {
>_mesa_error(ctx, GL_INVALID_ENUM, "glBlendEquation");
>return;
> }
>  
> -   _mesa_flush_vertices_for_blend_state(ctx);
> +   _mesa_flush_vertices_for_blend_adv(ctx, ctx->Color.BlendEnabled,
> +  advanced_mode);
>  
> for (buf = 0; buf < numBuffers; buf++) {
>ctx->Color.Blend[buf].EquationRGB = mode;
>ctx->Color.Blend[buf].EquationA = mode;
> }
> ctx->Color._BlendEquationPerBuffer = GL_FALSE;
> ctx->Color._AdvancedBlendMode = advanced_mode;
>  
> if (ctx->Driver.BlendEquationSeparate)
>ctx->Driver.BlendEquationSeparate(ctx, mode, mode);
> @@ -553,21 +554,22 @@ _mesa_BlendEquation( GLenum mode )
>   * Set blend equation for one color buffer/target.
>   */
>  static void
>  blend_equationi(struct gl_context *ctx, GLuint buf, GLenum mode,
>  enum gl_advanced_blend_mode advanced_mode)
>  {
> if (ctx->Color.Blend[buf].EquationRGB == mode &&
> ctx->Color.Blend[buf].EquationA == mode)
>return;  /* no change */
>  
> -   _mesa_flush_vertices_for_blend_state(ctx);
> +   _mesa_flush_vertices_for_blend_adv(ctx, ctx->Color.BlendEnabled,
> +  advanced_mode);
> ctx->Color.Blend[buf].EquationRGB = mode;
> ctx->Color.Blend[buf].EquationA = mode;
> ctx->Color._BlendEquationPerBuffer = GL_TRUE;
>  
> if (buf == 0)
>ctx->Color._AdvancedBlendMode = advanced_mode;
>  }
>  
>  
>  void GLAPIENTRY
> diff --git a/src/mesa/main/blend.h b/src/mesa/main/blend.h
> index 2454e0c..c95bc57 100644
> --- a/src/mesa/main/blend.h
> +++ b/src/mesa/main/blend.h
> @@ -147,28 +147,55 @@ extern void
>  _mesa_update_clamp_vertex_color(struct gl_context *ctx,
>  const struct gl_framebuffer *drawFb);
>  
>  extern mesa_format
>  _mesa_get_render_format(const struct gl_context *ctx, mesa_format format);
>  
>  extern void  
>  _mesa_init_color( struct gl_context * ctx );
>  
>  
> +static inline enum gl_advanced_blend_mode
> +_mesa_get_advanced_blend_sh_constant(GLbitfield blend_enabled,
> + enum gl_advanced_blend_mode mode)
> +{
> +   return blend_enabled ? mode : BLEND_NONE;
> +}
> +
> +static inline bool
> +_mesa_advanded_blend_sh_constant_changed(struct gl_context *ctx,
> + GLbitfield new_blend_enabled,
> + enum gl_advanced_blend_mode 
> new_mode)
> +{
> +   return _mesa_get_advanced_blend_sh_constant(new_blend_enabled, new_mode) 
> !=
> +  _mesa_get_advanced_blend_sh_constant(ctx->Color.BlendEnabled,
> +   
> ctx->Color._AdvancedBlendMode);
> +}
> +
>  static inline void
>  _mesa_flush_vertices_for_blend_state(struct gl_context *ctx)
>  {
> -   /* The advanced blend mode needs _NEW_COLOR to update the state constant,
> -* so we have to set it. This is inefficient.
> -* This should only be done for states that affect the state constant.
> -* It shouldn't be done for other blend states.
> -*/
> -   if (_mesa_has_KHR_blend_equation_advanced(ctx) ||
> -   !ctx->DriverFlags.NewBlend) {
> +   if (!ctx->DriverFlags.NewBlend) {
>FLUSH_VERTICES(ctx, _NEW_COLOR);
> } else {
>FLUSH_VERTICES(ctx, 0);
> +  ctx->NewDriverState |= ctx->DriverFlags.NewBlend;
> +   }
> +}
> +
> +static inline void
> +_mesa_flush_vertices_for_blend_adv(struct gl_context *ctx,
> +   GLbitfield new_blend_enabled,
> +   enum gl_advanced_blend_mode new_mode)
> +{
> +   /* The advanced blend mode needs _NEW_COLOR to update the state constant. 
> */
> +   if (_mesa_has_KHR_blend_equation_advanced(ctx) &&
> +   _mesa_advanded_blend_sh_constant_changed(ctx, new_blend_enabled,
> +new_mode)) {
> +  FLUSH_VERTICES(ctx, 

[Mesa-dev] [PATCH] anv: Do color resolve tracking one slice at a time for 3D images

[Jason Ekstrand]

---
 src/intel/vulkan/anv_image.c   | 14 +-
 src/intel/vulkan/anv_private.h |  9 -
 src/intel/vulkan/genX_cmd_buffer.c | 34 --
 3 files changed, 33 insertions(+), 24 deletions(-)

diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 6008e3c..a3e857c 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -262,11 +262,15 @@ add_aux_state_tracking_buffer(struct anv_image *image,
/* Clear color and fast clear type */
unsigned state_size = device->isl_dev.ss.clear_value_size + 4;
 
-   /* We only need to track compression on CCS_E surfaces.  We don't consider
-* 3D images as actually having multiple array layers.
-*/
-   if (image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E)
-  state_size += image->levels * image->array_size * 4;
+   /* We only need to track compression on CCS_E surfaces. */
+   if (image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E) {
+  if (image->type == VK_IMAGE_TYPE_3D) {
+ for (uint32_t l = 0; l < image->levels; l++)
+state_size += anv_minify(image->extent.depth, l) * 4;
+  } else {
+ state_size += image->levels * image->array_size * 4;
+  }
+   }
 
image->planes[plane].fast_clear_state_offset =
   image->planes[plane].offset + image->planes[plane].size;
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 0cd94bf..f208618 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -2573,8 +2573,15 @@ anv_image_get_compression_state_addr(const struct 
anv_device *device,
struct anv_address addr =
   anv_image_get_fast_clear_type_addr(device, image, aspect);
addr.offset += 4; /* Go past the fast clear type */
-   addr.offset += level * image->array_size * 4;
+
+   if (image->type == VK_IMAGE_TYPE_3D) {
+  for (uint32_t l = 0; l < image->levels; l++)
+ addr.offset += anv_minify(image->extent.depth, l) * 4;
+   } else {
+  addr.offset += level * image->array_size * 4;
+   }
addr.offset += array_layer * 4;
+
return addr;
 }
 
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index e29228d..b4b6b7d 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -632,14 +632,8 @@ anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer 
*cmd_buffer,
   mip.CompareOperation = COMPARE_SRCS_EQUAL;
}
 
-   if (image->type == VK_IMAGE_TYPE_3D) {
-  anv_image_ccs_op(cmd_buffer, image, aspect, level,
-   0, anv_minify(image->extent.depth, level),
-   resolve_op, true);
-   } else {
-  anv_image_ccs_op(cmd_buffer, image, aspect, level,
-   array_layer, 1, resolve_op, true);
-   }
+   anv_image_ccs_op(cmd_buffer, image, aspect, level,
+array_layer, 1, resolve_op, true);
 }
 
 void
@@ -836,9 +830,6 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
base_layer, layer_count);
}
 
-   if (image->type == VK_IMAGE_TYPE_3D)
-  base_layer = 0;
-
if (base_layer >= anv_image_aux_layers(image, aspect, base_level))
   return;
 
@@ -897,10 +888,6 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
 uint32_t level_layer_count =
MIN2(layer_count, anv_image_aux_layers(image, aspect, level));
 
-/* A transition of a 3D subresource works on all slices. */
-if (image->type == VK_IMAGE_TYPE_3D)
-   level_layer_count = anv_minify(image->extent.depth, level);
-
 anv_image_ccs_op(cmd_buffer, image, aspect, level,
  base_layer, level_layer_count,
  ISL_AUX_OP_AMBIGUATE, false);
@@ -994,7 +981,10 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
 
for (uint32_t l = 0; l < level_count; l++) {
   uint32_t level = base_level + l;
-  for (uint32_t a = 0; a < layer_count; a++) {
+  uint32_t level_layer_count =
+ MIN2(layer_count, anv_image_aux_layers(image, aspect, level));
+
+  for (uint32_t a = 0; a < level_layer_count; a++) {
  uint32_t array_layer = base_layer + a;
  anv_cmd_predicated_ccs_resolve(cmd_buffer, image, aspect,
 level, array_layer, resolve_op,
@@ -1663,12 +1653,20 @@ void genX(CmdPipelineBarrier)(
 anv_image_expand_aspects(image, range->aspectMask);
  uint32_t aspect_bit;
 
+ uint32_t base_layer, layer_count;
+ if (image->type == VK_IMAGE_TYPE_3D) {
+base_layer = 0;
+layer_count = anv_minify(image->extent.depth, range->baseMipLevel);
+ } else {
+base_layer = range->baseArrayLayer;
+layer_count = anv_get_layerCount(image, range);
+ }
+
  anv_foreach_image_aspect_bit(aspect_bit, image, 

Re: [Mesa-dev] [PATCH] r600/eg: add crap indirect compute support.

[Roland Scheidegger]

That's not much "indirect" the way it's done, but looks alright to me ;-).

Reviewed-by: Roland Scheidegger 


Am 30.01.2018 um 03:22 schrieb Dave Airlie:
> From: Dave Airlie 
> 
> I think the cp packets can be made work, but I think it might
> need a kernel change, so for now just do the worst thing.
> ---
>  src/gallium/drivers/r600/evergreen_compute.c | 26 +++---
>  1 file changed, 19 insertions(+), 7 deletions(-)
> 
> diff --git a/src/gallium/drivers/r600/evergreen_compute.c 
> b/src/gallium/drivers/r600/evergreen_compute.c
> index 7880d0f..b2c724f 100644
> --- a/src/gallium/drivers/r600/evergreen_compute.c
> +++ b/src/gallium/drivers/r600/evergreen_compute.c
> @@ -630,13 +630,25 @@ static void evergreen_emit_dispatch(struct r600_context 
> *rctx,
>   radeon_compute_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC,
>   lds_size | (num_waves << 14));
>  
> - /* Dispatch packet */
> - radeon_emit(cs, PKT3C(PKT3_DISPATCH_DIRECT, 3, 0));
> - radeon_emit(cs, info->grid[0]);
> - radeon_emit(cs, info->grid[1]);
> - radeon_emit(cs, info->grid[2]);
> - /* VGT_DISPATCH_INITIATOR = COMPUTE_SHADER_EN */
> - radeon_emit(cs, 1);
> + if (info->indirect) {
> + struct r600_resource *indirect_resource = (struct r600_resource 
> *)info->indirect;
> + unsigned *data = r600_buffer_map_sync_with_rings(>b, 
> indirect_resource, PIPE_TRANSFER_READ);
> + if (data) {
> + radeon_emit(cs, PKT3C(PKT3_DISPATCH_DIRECT, 3, 0));
> + radeon_emit(cs, data[0]);
> + radeon_emit(cs, data[1]);
> + radeon_emit(cs, data[2]);
> + radeon_emit(cs, 1);
> + }
> + } else {
> + /* Dispatch packet */
> + radeon_emit(cs, PKT3C(PKT3_DISPATCH_DIRECT, 3, 0));
> + radeon_emit(cs, info->grid[0]);
> + radeon_emit(cs, info->grid[1]);
> + radeon_emit(cs, info->grid[2]);
> + /* VGT_DISPATCH_INITIATOR = COMPUTE_SHADER_EN */
> + radeon_emit(cs, 1);
> + }
>  
>   if (rctx->is_debug)
>   eg_trace_emit(rctx);
> 

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Re: [Mesa-dev] [PATCH (resend)] r600/sb: Don't require array declarations for TGSI_FILE_SYSTEM_VALUE

[Roland Scheidegger]

Am 30.01.2018 um 09:21 schrieb Gert Wollny:
> Although gl_SampleMaskIn is declared as an array in GLSL, it is
> effectively a 32 bit mask on all hardware supported by mesa, so the
> array indexing is ignored (Thanks Glenn Kennard for the explanation).
> 
> Add a comment that the assert is not made superfluos by the else branch.
> 
> Corrects: piglit spec@arb_gpu_shader5@execution@samplemaskin-indirect for
> debug builds (it already passed in release).
> 
> Signed-off-by: Gert Wollny 
> ---
> 
>  src/gallium/drivers/r600/sb/sb_bc_parser.cpp | 8 +++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp 
> b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
> index 970e4141d5..b92e058daf 100644
> --- a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
> +++ b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
> @@ -125,7 +125,9 @@ int bc_parser::parse_decls() {
>   return 0;
>   }
>  
> - if (pshader->indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << 
> TGSI_FILE_SAMPLER))) {
> + if (pshader->indirect_files &
> + ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER) |
> +  (1 << TGSI_FILE_SYSTEM_VALUE))) {
So I suppose this is ok because none of the other system values
could be arrays.
That said, isn't that actually a bug in glsl to tgsi translation? the
sample mask is never an array in gallium/tgsi (and not declared as
such), so I think it should not turn up as indirect when properly
translated, reading the value should not end up as indexed.

Roland


>   assert(pshader->num_arrays);
>  
> @@ -135,6 +137,10 @@ int bc_parser::parse_decls() {
>   sh->add_gpr_array(a.gpr_start, a.gpr_count, 
> a.comp_mask);
>   }
>   } else {
> + /* When the above assert is disabled and proper array 
> info
> +  * is missing for some reason then, as a fallback, make 
> sure
> +  * that all GPRs can be accessed indirectly.
> +  */
>   sh->add_gpr_array(0, pshader->bc.ngpr, 0x0F);
>   }
>   }
> 

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Re: [Mesa-dev] [PATCH] r600: initial attempt at gl_HelperInvocation (v3)

[Dave Airlie]

>>
>> It might be for this test, but I don't think it is in general. We want 
>> boolean
>> which I think is 0 or 0x, not 0.0 or 1.0.
>
> The initial alu reg write was 0x, and the resinfo gives you back
> a fixed 0, so...

Doh I just noticed it now, my brain had a copy of the older patch in it, once I
read the patch I actually sent it made more sense!

Thanks,
Dave.
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Re: [Mesa-dev] [PATCH] r600: initial attempt at gl_HelperInvocation (v3)

[Roland Scheidegger]

Am 02.02.2018 um 00:23 schrieb Dave Airlie:
> On 2 February 2018 at 09:23, Dave Airlie  wrote:
>> On 2 February 2018 at 02:05, Roland Scheidegger  wrote:
>>> Am 01.02.2018 um 09:21 schrieb Dave Airlie:
 From: Dave Airlie 

 This passes the CTS and piglit tests.

 This also disable sb for helper invocations until it doesn't
 mess up the VPM flags.

 Thanks to Ilia and Glenn for advice, and Roland for working
 out the working evergreen path.
 ---
  src/gallium/drivers/r600/r600_asm.c|   7 +-
  src/gallium/drivers/r600/r600_isa.c|   1 +
  src/gallium/drivers/r600/r600_isa.h|   5 +-
  src/gallium/drivers/r600/r600_shader.c | 113 
 +
  src/gallium/drivers/r600/r600_shader.h |   1 +
  src/gallium/drivers/r600/r600_sq.h |   2 +
  6 files changed, 126 insertions(+), 3 deletions(-)

 diff --git a/src/gallium/drivers/r600/r600_asm.c 
 b/src/gallium/drivers/r600/r600_asm.c
 index 21d069d..ec2d34e 100644
 --- a/src/gallium/drivers/r600/r600_asm.c
 +++ b/src/gallium/drivers/r600/r600_asm.c
 @@ -2099,9 +2099,12 @@ void r600_bytecode_disasm(struct r600_bytecode *bc)
   fprintf(stderr, "%04d %08X %08X  %s ", id, 
 bc->bytecode[id],
   bc->bytecode[id + 1], 
 cfop->name);
   fprintf(stderr, "%d @%d ", cf->ndw / 4, 
 cf->addr);
 - fprintf(stderr, "\n");
 + if (cf->vpm)
 + fprintf(stderr, "VPM ");
   if (cf->end_of_program)
   fprintf(stderr, "EOP ");
 + fprintf(stderr, "\n");
 +
   } else if (cfop->flags & CF_EXP) {
   int o = 0;
   const char *exp_type[] = {"PIXEL", "POS  ", 
 "PARAM"};
 @@ -2198,6 +2201,8 @@ void r600_bytecode_disasm(struct r600_bytecode *bc)
   fprintf(stderr, "POP:%X ", 
 cf->pop_count);
   if (cf->count && (cfop->flags & CF_EMIT))
   fprintf(stderr, "STREAM%d ", 
 cf->count);
 + if (cf->vpm)
 + fprintf(stderr, "VPM ");
   if (cf->end_of_program)
   fprintf(stderr, "EOP ");
   fprintf(stderr, "\n");
 diff --git a/src/gallium/drivers/r600/r600_isa.c 
 b/src/gallium/drivers/r600/r600_isa.c
 index 2633cdc..611b370 100644
 --- a/src/gallium/drivers/r600/r600_isa.c
 +++ b/src/gallium/drivers/r600/r600_isa.c
 @@ -506,6 +506,7 @@ static const struct cf_op_info cf_op_table[] = {
   {"ALU_EXT",   {   -1,   -1, 0x0C, 0x0C 
 },  CF_CLAUSE | CF_ALU | CF_ALU_EXT  },
   {"ALU_CONTINUE",  { 0x0D, 0x0D, 0x0D,   -1 
 },  CF_CLAUSE | CF_ALU  },
   {"ALU_BREAK", { 0x0E, 0x0E, 0x0E,   -1 
 },  CF_CLAUSE | CF_ALU  },
 + {"ALU_VALID_PIXEL_MODE",  {   -1,   -1,   -1, 0x0E 
 },  CF_CLAUSE | CF_ALU  },
   {"ALU_ELSE_AFTER",{ 0x0F, 0x0F, 0x0F, 0x0F 
 },  CF_CLAUSE | CF_ALU  },
   {"CF_NATIVE", { 0x00, 0x00, 0x00, 0x00 
 },  0  }
  };
 diff --git a/src/gallium/drivers/r600/r600_isa.h 
 b/src/gallium/drivers/r600/r600_isa.h
 index f6e2697..fcaf1f7 100644
 --- a/src/gallium/drivers/r600/r600_isa.h
 +++ b/src/gallium/drivers/r600/r600_isa.h
 @@ -646,10 +646,11 @@ struct cf_op_info
  #define CF_OP_ALU_EXT  84
  #define CF_OP_ALU_CONTINUE 85
  #define CF_OP_ALU_BREAK86
 -#define CF_OP_ALU_ELSE_AFTER   87
 +#define CF_OP_ALU_VALID_PIXEL_MODE 87
 +#define CF_OP_ALU_ELSE_AFTER   88

  /* CF_NATIVE means that r600_bytecode_cf contains pre-encoded native data 
 */
 -#define CF_NATIVE  88
 +#define CF_NATIVE  89

  enum r600_chip_class {
   ISA_CC_R600,
 diff --git a/src/gallium/drivers/r600/r600_shader.c 
 b/src/gallium/drivers/r600/r600_shader.c
 index a462691..9388db9 100644
 --- a/src/gallium/drivers/r600/r600_shader.c
 +++ b/src/gallium/drivers/r600/r600_shader.c
 @@ -197,6 +197,7 @@ int r600_pipe_shader_create(struct pipe_context *ctx,

   use_sb &= !shader->shader.uses_atomics;
   use_sb &= 

Re: [Mesa-dev] [PATCH] r600: initial attempt at gl_HelperInvocation (v3)

[Dave Airlie]

On 2 February 2018 at 09:23, Dave Airlie  wrote:
> On 2 February 2018 at 02:05, Roland Scheidegger  wrote:
>> Am 01.02.2018 um 09:21 schrieb Dave Airlie:
>>> From: Dave Airlie 
>>>
>>> This passes the CTS and piglit tests.
>>>
>>> This also disable sb for helper invocations until it doesn't
>>> mess up the VPM flags.
>>>
>>> Thanks to Ilia and Glenn for advice, and Roland for working
>>> out the working evergreen path.
>>> ---
>>>  src/gallium/drivers/r600/r600_asm.c|   7 +-
>>>  src/gallium/drivers/r600/r600_isa.c|   1 +
>>>  src/gallium/drivers/r600/r600_isa.h|   5 +-
>>>  src/gallium/drivers/r600/r600_shader.c | 113 
>>> +
>>>  src/gallium/drivers/r600/r600_shader.h |   1 +
>>>  src/gallium/drivers/r600/r600_sq.h |   2 +
>>>  6 files changed, 126 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/src/gallium/drivers/r600/r600_asm.c 
>>> b/src/gallium/drivers/r600/r600_asm.c
>>> index 21d069d..ec2d34e 100644
>>> --- a/src/gallium/drivers/r600/r600_asm.c
>>> +++ b/src/gallium/drivers/r600/r600_asm.c
>>> @@ -2099,9 +2099,12 @@ void r600_bytecode_disasm(struct r600_bytecode *bc)
>>>   fprintf(stderr, "%04d %08X %08X  %s ", id, 
>>> bc->bytecode[id],
>>>   bc->bytecode[id + 1], 
>>> cfop->name);
>>>   fprintf(stderr, "%d @%d ", cf->ndw / 4, 
>>> cf->addr);
>>> - fprintf(stderr, "\n");
>>> + if (cf->vpm)
>>> + fprintf(stderr, "VPM ");
>>>   if (cf->end_of_program)
>>>   fprintf(stderr, "EOP ");
>>> + fprintf(stderr, "\n");
>>> +
>>>   } else if (cfop->flags & CF_EXP) {
>>>   int o = 0;
>>>   const char *exp_type[] = {"PIXEL", "POS  ", 
>>> "PARAM"};
>>> @@ -2198,6 +2201,8 @@ void r600_bytecode_disasm(struct r600_bytecode *bc)
>>>   fprintf(stderr, "POP:%X ", 
>>> cf->pop_count);
>>>   if (cf->count && (cfop->flags & CF_EMIT))
>>>   fprintf(stderr, "STREAM%d ", 
>>> cf->count);
>>> + if (cf->vpm)
>>> + fprintf(stderr, "VPM ");
>>>   if (cf->end_of_program)
>>>   fprintf(stderr, "EOP ");
>>>   fprintf(stderr, "\n");
>>> diff --git a/src/gallium/drivers/r600/r600_isa.c 
>>> b/src/gallium/drivers/r600/r600_isa.c
>>> index 2633cdc..611b370 100644
>>> --- a/src/gallium/drivers/r600/r600_isa.c
>>> +++ b/src/gallium/drivers/r600/r600_isa.c
>>> @@ -506,6 +506,7 @@ static const struct cf_op_info cf_op_table[] = {
>>>   {"ALU_EXT",   {   -1,   -1, 0x0C, 0x0C }, 
>>>  CF_CLAUSE | CF_ALU | CF_ALU_EXT  },
>>>   {"ALU_CONTINUE",  { 0x0D, 0x0D, 0x0D,   -1 }, 
>>>  CF_CLAUSE | CF_ALU  },
>>>   {"ALU_BREAK", { 0x0E, 0x0E, 0x0E,   -1 }, 
>>>  CF_CLAUSE | CF_ALU  },
>>> + {"ALU_VALID_PIXEL_MODE",  {   -1,   -1,   -1, 0x0E }, 
>>>  CF_CLAUSE | CF_ALU  },
>>>   {"ALU_ELSE_AFTER",{ 0x0F, 0x0F, 0x0F, 0x0F }, 
>>>  CF_CLAUSE | CF_ALU  },
>>>   {"CF_NATIVE", { 0x00, 0x00, 0x00, 0x00 }, 
>>>  0  }
>>>  };
>>> diff --git a/src/gallium/drivers/r600/r600_isa.h 
>>> b/src/gallium/drivers/r600/r600_isa.h
>>> index f6e2697..fcaf1f7 100644
>>> --- a/src/gallium/drivers/r600/r600_isa.h
>>> +++ b/src/gallium/drivers/r600/r600_isa.h
>>> @@ -646,10 +646,11 @@ struct cf_op_info
>>>  #define CF_OP_ALU_EXT  84
>>>  #define CF_OP_ALU_CONTINUE 85
>>>  #define CF_OP_ALU_BREAK86
>>> -#define CF_OP_ALU_ELSE_AFTER   87
>>> +#define CF_OP_ALU_VALID_PIXEL_MODE 87
>>> +#define CF_OP_ALU_ELSE_AFTER   88
>>>
>>>  /* CF_NATIVE means that r600_bytecode_cf contains pre-encoded native data 
>>> */
>>> -#define CF_NATIVE  88
>>> +#define CF_NATIVE  89
>>>
>>>  enum r600_chip_class {
>>>   ISA_CC_R600,
>>> diff --git a/src/gallium/drivers/r600/r600_shader.c 
>>> b/src/gallium/drivers/r600/r600_shader.c
>>> index a462691..9388db9 100644
>>> --- a/src/gallium/drivers/r600/r600_shader.c
>>> +++ b/src/gallium/drivers/r600/r600_shader.c
>>> @@ -197,6 +197,7 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
>>>
>>>   use_sb &= !shader->shader.uses_atomics;
>>>   use_sb &= !shader->shader.uses_images;
>>> + use_sb &= !shader->shader.uses_helper_invocation;
>>>
>>>   /* Check if the bytecode has already been built. */
>>>   if 

Re: [Mesa-dev] [PATCH] r600: initial attempt at gl_HelperInvocation (v3)

[Dave Airlie]

On 2 February 2018 at 02:05, Roland Scheidegger  wrote:
> Am 01.02.2018 um 09:21 schrieb Dave Airlie:
>> From: Dave Airlie 
>>
>> This passes the CTS and piglit tests.
>>
>> This also disable sb for helper invocations until it doesn't
>> mess up the VPM flags.
>>
>> Thanks to Ilia and Glenn for advice, and Roland for working
>> out the working evergreen path.
>> ---
>>  src/gallium/drivers/r600/r600_asm.c|   7 +-
>>  src/gallium/drivers/r600/r600_isa.c|   1 +
>>  src/gallium/drivers/r600/r600_isa.h|   5 +-
>>  src/gallium/drivers/r600/r600_shader.c | 113 
>> +
>>  src/gallium/drivers/r600/r600_shader.h |   1 +
>>  src/gallium/drivers/r600/r600_sq.h |   2 +
>>  6 files changed, 126 insertions(+), 3 deletions(-)
>>
>> diff --git a/src/gallium/drivers/r600/r600_asm.c 
>> b/src/gallium/drivers/r600/r600_asm.c
>> index 21d069d..ec2d34e 100644
>> --- a/src/gallium/drivers/r600/r600_asm.c
>> +++ b/src/gallium/drivers/r600/r600_asm.c
>> @@ -2099,9 +2099,12 @@ void r600_bytecode_disasm(struct r600_bytecode *bc)
>>   fprintf(stderr, "%04d %08X %08X  %s ", id, 
>> bc->bytecode[id],
>>   bc->bytecode[id + 1], 
>> cfop->name);
>>   fprintf(stderr, "%d @%d ", cf->ndw / 4, 
>> cf->addr);
>> - fprintf(stderr, "\n");
>> + if (cf->vpm)
>> + fprintf(stderr, "VPM ");
>>   if (cf->end_of_program)
>>   fprintf(stderr, "EOP ");
>> + fprintf(stderr, "\n");
>> +
>>   } else if (cfop->flags & CF_EXP) {
>>   int o = 0;
>>   const char *exp_type[] = {"PIXEL", "POS  ", 
>> "PARAM"};
>> @@ -2198,6 +2201,8 @@ void r600_bytecode_disasm(struct r600_bytecode *bc)
>>   fprintf(stderr, "POP:%X ", 
>> cf->pop_count);
>>   if (cf->count && (cfop->flags & CF_EMIT))
>>   fprintf(stderr, "STREAM%d ", 
>> cf->count);
>> + if (cf->vpm)
>> + fprintf(stderr, "VPM ");
>>   if (cf->end_of_program)
>>   fprintf(stderr, "EOP ");
>>   fprintf(stderr, "\n");
>> diff --git a/src/gallium/drivers/r600/r600_isa.c 
>> b/src/gallium/drivers/r600/r600_isa.c
>> index 2633cdc..611b370 100644
>> --- a/src/gallium/drivers/r600/r600_isa.c
>> +++ b/src/gallium/drivers/r600/r600_isa.c
>> @@ -506,6 +506,7 @@ static const struct cf_op_info cf_op_table[] = {
>>   {"ALU_EXT",   {   -1,   -1, 0x0C, 0x0C },  
>> CF_CLAUSE | CF_ALU | CF_ALU_EXT  },
>>   {"ALU_CONTINUE",  { 0x0D, 0x0D, 0x0D,   -1 },  
>> CF_CLAUSE | CF_ALU  },
>>   {"ALU_BREAK", { 0x0E, 0x0E, 0x0E,   -1 },  
>> CF_CLAUSE | CF_ALU  },
>> + {"ALU_VALID_PIXEL_MODE",  {   -1,   -1,   -1, 0x0E },  
>> CF_CLAUSE | CF_ALU  },
>>   {"ALU_ELSE_AFTER",{ 0x0F, 0x0F, 0x0F, 0x0F },  
>> CF_CLAUSE | CF_ALU  },
>>   {"CF_NATIVE", { 0x00, 0x00, 0x00, 0x00 },  
>> 0  }
>>  };
>> diff --git a/src/gallium/drivers/r600/r600_isa.h 
>> b/src/gallium/drivers/r600/r600_isa.h
>> index f6e2697..fcaf1f7 100644
>> --- a/src/gallium/drivers/r600/r600_isa.h
>> +++ b/src/gallium/drivers/r600/r600_isa.h
>> @@ -646,10 +646,11 @@ struct cf_op_info
>>  #define CF_OP_ALU_EXT  84
>>  #define CF_OP_ALU_CONTINUE 85
>>  #define CF_OP_ALU_BREAK86
>> -#define CF_OP_ALU_ELSE_AFTER   87
>> +#define CF_OP_ALU_VALID_PIXEL_MODE 87
>> +#define CF_OP_ALU_ELSE_AFTER   88
>>
>>  /* CF_NATIVE means that r600_bytecode_cf contains pre-encoded native data */
>> -#define CF_NATIVE  88
>> +#define CF_NATIVE  89
>>
>>  enum r600_chip_class {
>>   ISA_CC_R600,
>> diff --git a/src/gallium/drivers/r600/r600_shader.c 
>> b/src/gallium/drivers/r600/r600_shader.c
>> index a462691..9388db9 100644
>> --- a/src/gallium/drivers/r600/r600_shader.c
>> +++ b/src/gallium/drivers/r600/r600_shader.c
>> @@ -197,6 +197,7 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
>>
>>   use_sb &= !shader->shader.uses_atomics;
>>   use_sb &= !shader->shader.uses_images;
>> + use_sb &= !shader->shader.uses_helper_invocation;
>>
>>   /* Check if the bytecode has already been built. */
>>   if (!shader->shader.bc.bytecode) {
>> @@ -346,6 +347,7 @@ struct r600_shader_ctx {
>>   boolean clip_vertex_write;
>>   unsignedcv_output;
>>   

Re: [Mesa-dev] [PATCH 2/3] gallium: Add a new A4B4G4R4 pipe format for Broadcom.

[Marek Olšák]

Patch 1 & 2:

Reviewed-by: Marek Olšák 

Marek

On Thu, Feb 1, 2018 at 8:20 PM, Eric Anholt  wrote:
> The VC5 HW puts A in the low bits and R in the high bits.  We can't just
> swizzle in the shaders because the blending HW can't pick what channel A
> is in, so make a new format to match it.
> ---
>  src/gallium/auxiliary/util/u_format.csv | 1 +
>  src/gallium/drivers/svga/svga_format.c  | 1 +
>  src/gallium/include/pipe/p_format.h | 1 +
>  src/mesa/state_tracker/st_format.c  | 8 +++-
>  4 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/auxiliary/util/u_format.csv 
> b/src/gallium/auxiliary/util/u_format.csv
> index 689895f400c9..f9e4925f27cc 100644
> --- a/src/gallium/auxiliary/util/u_format.csv
> +++ b/src/gallium/auxiliary/util/u_format.csv
> @@ -78,6 +78,7 @@ PIPE_FORMAT_X1B5G5R5_UNORM, plain, 1, 1, x1  , un5 
> , un5 , un5 , wzy1, r
>  PIPE_FORMAT_A1B5G5R5_UNORM, plain, 1, 1, un1 , un5 , un5 , un5 , 
> wzyx, rgb, un5 , un5 , un5 , un1 , xyzw
>  PIPE_FORMAT_B4G4R4A4_UNORM, plain, 1, 1, un4 , un4 , un4 , un4 , 
> zyxw, rgb, un4 , un4 , un4 , un4 , yzwx
>  PIPE_FORMAT_B4G4R4X4_UNORM, plain, 1, 1, un4 , un4 , un4 , x4  , 
> zyx1, rgb, x4  , un4 , un4 , un4 , yzw1
> +PIPE_FORMAT_A4B4G4R4_UNORM, plain, 1, 1, un4 , un4 , un4 , un4 , 
> wzyx, rgb, un4 , un4 , un4 , un4 , xyzw
>  PIPE_FORMAT_B5G6R5_UNORM  , plain, 1, 1, un5 , un6 , un5 , , 
> zyx1, rgb, un5 , un6 , un5 , , xyz1
>  PIPE_FORMAT_R10G10B10A2_UNORM , plain, 1, 1, un10, un10, un10, un2 , 
> xyzw, rgb, un2 , un10, un10, un10, wzyx
>  PIPE_FORMAT_R10G10B10X2_UNORM , plain, 1, 1, un10, un10, un10, x2,   
> xyz1, rgb, x2  , un10, un10, un10, wzy1
> diff --git a/src/gallium/drivers/svga/svga_format.c 
> b/src/gallium/drivers/svga/svga_format.c
> index 964923f084ea..20a6e6b159f3 100644
> --- a/src/gallium/drivers/svga/svga_format.c
> +++ b/src/gallium/drivers/svga/svga_format.c
> @@ -368,6 +368,7 @@ static const struct vgpu10_format_entry 
> format_conversion_table[] =
> { PIPE_FORMAT_R10G10B10X2_UNORM, SVGA3D_FORMAT_INVALID,  
> SVGA3D_FORMAT_INVALID,   0 },
> { PIPE_FORMAT_A1B5G5R5_UNORM,SVGA3D_FORMAT_INVALID,  
> SVGA3D_FORMAT_INVALID,   0 },
> { PIPE_FORMAT_X1B5G5R5_UNORM,SVGA3D_FORMAT_INVALID,  
> SVGA3D_FORMAT_INVALID,   0 },
> +   { PIPE_FORMAT_A4B4G4R4_UNORM,SVGA3D_FORMAT_INVALID,  
> SVGA3D_FORMAT_INVALID,   0 },
>  };
>
>
> diff --git a/src/gallium/include/pipe/p_format.h 
> b/src/gallium/include/pipe/p_format.h
> index fedac8a06d7e..57399800fa47 100644
> --- a/src/gallium/include/pipe/p_format.h
> +++ b/src/gallium/include/pipe/p_format.h
> @@ -394,6 +394,7 @@ enum pipe_format {
> PIPE_FORMAT_R10G10B10X2_UNORM   = 308,
> PIPE_FORMAT_A1B5G5R5_UNORM  = 309,
> PIPE_FORMAT_X1B5G5R5_UNORM  = 310,
> +   PIPE_FORMAT_A4B4G4R4_UNORM  = 311,
>
> PIPE_FORMAT_COUNT
>  };
> diff --git a/src/mesa/state_tracker/st_format.c 
> b/src/mesa/state_tracker/st_format.c
> index cc72ba406e6e..c50ce1e14bb1 100644
> --- a/src/mesa/state_tracker/st_format.c
> +++ b/src/mesa/state_tracker/st_format.c
> @@ -84,6 +84,8 @@ st_mesa_format_to_pipe_format(const struct st_context *st,
>return PIPE_FORMAT_A1B5G5R5_UNORM;
> case MESA_FORMAT_B4G4R4A4_UNORM:
>return PIPE_FORMAT_B4G4R4A4_UNORM;
> +   case MESA_FORMAT_A4B4G4R4_UNORM:
> +  return PIPE_FORMAT_A4B4G4R4_UNORM;
> case MESA_FORMAT_B5G6R5_UNORM:
>return PIPE_FORMAT_B5G6R5_UNORM;
> case MESA_FORMAT_B2G3R3_UNORM:
> @@ -567,6 +569,8 @@ st_pipe_format_to_mesa_format(enum pipe_format format)
>return MESA_FORMAT_A1B5G5R5_UNORM;
> case PIPE_FORMAT_B4G4R4A4_UNORM:
>return MESA_FORMAT_B4G4R4A4_UNORM;
> +   case PIPE_FORMAT_A4B4G4R4_UNORM:
> +  return MESA_FORMAT_A4B4G4R4_UNORM;
> case PIPE_FORMAT_B5G6R5_UNORM:
>return MESA_FORMAT_B5G6R5_UNORM;
> case PIPE_FORMAT_B2G3R3_UNORM:
> @@ -1155,7 +1159,8 @@ static const struct format_mapping format_map[] = {
> },
> {
>{ GL_RGBA4, GL_RGBA2, 0 },
> -  { PIPE_FORMAT_B4G4R4A4_UNORM, DEFAULT_RGBA_FORMATS }
> +  { PIPE_FORMAT_B4G4R4A4_UNORM, PIPE_FORMAT_A4B4G4R4_UNORM,
> +DEFAULT_RGBA_FORMATS }
> },
> {
>{ GL_RGB5_A1, 0 },
> @@ -1170,6 +1175,7 @@ static const struct format_mapping format_map[] = {
> {
>{ GL_RGB4 },
>{ PIPE_FORMAT_B4G4R4X4_UNORM, PIPE_FORMAT_B4G4R4A4_UNORM,
> +PIPE_FORMAT_A4B4G4R4_UNORM,
>  DEFAULT_RGB_FORMATS }
> },
> {
> --
> 2.15.0
>
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[Mesa-dev] [PATCH] gallium: remove llvm from ir struct

[Timothy Arceri]

This was added in 425dc4c4b366 but never used. Also since
100796c15c3a native has superseded llvm.
---
 src/gallium/include/pipe/p_state.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/gallium/include/pipe/p_state.h 
b/src/gallium/include/pipe/p_state.h
index 2b56d60b5e..640e6ed26d 100644
--- a/src/gallium/include/pipe/p_state.h
+++ b/src/gallium/include/pipe/p_state.h
@@ -267,7 +267,6 @@ struct pipe_shader_state
/* TODO move tokens into union. */
const struct tgsi_token *tokens;
union {
-  void *llvm;
   void *native;
   void *nir;
} ir;
-- 
2.14.3

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Re: [Mesa-dev] [PATCH 2/9] glsl: add u64->fp64 and i64->fp64 builtins.

[Dylan Baker]

Quoting Elie Tournier (2018-02-01 12:13:53)
> On Thu, Feb 01, 2018 at 10:00:12AM -0800, Dylan Baker wrote:
> > There are changes from Makefile.sources that need be ported to corresponding
> > meson.build files as well.
> Oh yes, nice spot. I will do it on my local fp64 branch too.
> > 
> > It looks like builtin_float64.h is generated from float64.glsl, is that 
> > right?
> Like builtin_int64h and int64.glsl, builtin_float64.h is generated from 
> float64.glsl.
> 
> > I'm not very happy about checking in a generated file for all of the reasons
> > that we don't check generated files in. I recognize that trying to generate 
> > code
> > from an in tree binary at compile time makes the cross compiling situation 
> > less
> > than ideal since we would need to bootstrap the glsl compiler, but it's 
> > still
> > annoying. This is why we stopped using glsl compilation for mesa, and added
> > tools like nir_builder and ir_builder. I guess that's a pretty big 
> > complaint and
> > I don't expect you to fix it, but it's frustrating that we're going to have 
> > to
> > check generated code in and deal with all the problems that come along with
> > that.
> This project is quite big. Using ir_builder would make this project even 
> bigger.
> At least for me. ;)

Yeah, I understand that. :)


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Re: [Mesa-dev] [PATCH] r600: don't do stack workarounds for hemlock

[Alex Deucher]

On Tue, Jan 30, 2018 at 12:07 AM,   wrote:
> From: Roland Scheidegger 
>
> By the looks of it it seems hemlock is treated separately to cypress, but
> certainly it won't need the stack workarounds cedar/redwood (and
> seemingly every other eg chip except cypress/juniper) need.
> (Discovered by accident.)

Acked-by: Alex Deucher 

> ---
>  src/gallium/drivers/r600/sb/sb_bc.h | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/src/gallium/drivers/r600/sb/sb_bc.h 
> b/src/gallium/drivers/r600/sb/sb_bc.h
> index b35671bf0f..a249395474 100644
> --- a/src/gallium/drivers/r600/sb/sb_bc.h
> +++ b/src/gallium/drivers/r600/sb/sb_bc.h
> @@ -665,6 +665,7 @@ public:
> return false;
>
> switch (hw_chip) {
> +   case HW_CHIP_HEMLOCK:
> case HW_CHIP_CYPRESS:
> case HW_CHIP_JUNIPER:
> return false;
> --
> 2.12.3
>
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[Mesa-dev] [PATCH 2/3] gallium: Add a new A4B4G4R4 pipe format for Broadcom.

[Eric Anholt]

The VC5 HW puts A in the low bits and R in the high bits.  We can't just
swizzle in the shaders because the blending HW can't pick what channel A
is in, so make a new format to match it.
---
 src/gallium/auxiliary/util/u_format.csv | 1 +
 src/gallium/drivers/svga/svga_format.c  | 1 +
 src/gallium/include/pipe/p_format.h | 1 +
 src/mesa/state_tracker/st_format.c  | 8 +++-
 4 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/util/u_format.csv 
b/src/gallium/auxiliary/util/u_format.csv
index 689895f400c9..f9e4925f27cc 100644
--- a/src/gallium/auxiliary/util/u_format.csv
+++ b/src/gallium/auxiliary/util/u_format.csv
@@ -78,6 +78,7 @@ PIPE_FORMAT_X1B5G5R5_UNORM, plain, 1, 1, x1  , un5 , 
un5 , un5 , wzy1, r
 PIPE_FORMAT_A1B5G5R5_UNORM, plain, 1, 1, un1 , un5 , un5 , un5 , wzyx, 
rgb, un5 , un5 , un5 , un1 , xyzw
 PIPE_FORMAT_B4G4R4A4_UNORM, plain, 1, 1, un4 , un4 , un4 , un4 , zyxw, 
rgb, un4 , un4 , un4 , un4 , yzwx
 PIPE_FORMAT_B4G4R4X4_UNORM, plain, 1, 1, un4 , un4 , un4 , x4  , zyx1, 
rgb, x4  , un4 , un4 , un4 , yzw1
+PIPE_FORMAT_A4B4G4R4_UNORM, plain, 1, 1, un4 , un4 , un4 , un4 , wzyx, 
rgb, un4 , un4 , un4 , un4 , xyzw
 PIPE_FORMAT_B5G6R5_UNORM  , plain, 1, 1, un5 , un6 , un5 , , zyx1, 
rgb, un5 , un6 , un5 , , xyz1
 PIPE_FORMAT_R10G10B10A2_UNORM , plain, 1, 1, un10, un10, un10, un2 , xyzw, 
rgb, un2 , un10, un10, un10, wzyx
 PIPE_FORMAT_R10G10B10X2_UNORM , plain, 1, 1, un10, un10, un10, x2,   xyz1, 
rgb, x2  , un10, un10, un10, wzy1
diff --git a/src/gallium/drivers/svga/svga_format.c 
b/src/gallium/drivers/svga/svga_format.c
index 964923f084ea..20a6e6b159f3 100644
--- a/src/gallium/drivers/svga/svga_format.c
+++ b/src/gallium/drivers/svga/svga_format.c
@@ -368,6 +368,7 @@ static const struct vgpu10_format_entry 
format_conversion_table[] =
{ PIPE_FORMAT_R10G10B10X2_UNORM, SVGA3D_FORMAT_INVALID,  
SVGA3D_FORMAT_INVALID,   0 },
{ PIPE_FORMAT_A1B5G5R5_UNORM,SVGA3D_FORMAT_INVALID,  
SVGA3D_FORMAT_INVALID,   0 },
{ PIPE_FORMAT_X1B5G5R5_UNORM,SVGA3D_FORMAT_INVALID,  
SVGA3D_FORMAT_INVALID,   0 },
+   { PIPE_FORMAT_A4B4G4R4_UNORM,SVGA3D_FORMAT_INVALID,  
SVGA3D_FORMAT_INVALID,   0 },
 };
 
 
diff --git a/src/gallium/include/pipe/p_format.h 
b/src/gallium/include/pipe/p_format.h
index fedac8a06d7e..57399800fa47 100644
--- a/src/gallium/include/pipe/p_format.h
+++ b/src/gallium/include/pipe/p_format.h
@@ -394,6 +394,7 @@ enum pipe_format {
PIPE_FORMAT_R10G10B10X2_UNORM   = 308,
PIPE_FORMAT_A1B5G5R5_UNORM  = 309,
PIPE_FORMAT_X1B5G5R5_UNORM  = 310,
+   PIPE_FORMAT_A4B4G4R4_UNORM  = 311,
 
PIPE_FORMAT_COUNT
 };
diff --git a/src/mesa/state_tracker/st_format.c 
b/src/mesa/state_tracker/st_format.c
index cc72ba406e6e..c50ce1e14bb1 100644
--- a/src/mesa/state_tracker/st_format.c
+++ b/src/mesa/state_tracker/st_format.c
@@ -84,6 +84,8 @@ st_mesa_format_to_pipe_format(const struct st_context *st,
   return PIPE_FORMAT_A1B5G5R5_UNORM;
case MESA_FORMAT_B4G4R4A4_UNORM:
   return PIPE_FORMAT_B4G4R4A4_UNORM;
+   case MESA_FORMAT_A4B4G4R4_UNORM:
+  return PIPE_FORMAT_A4B4G4R4_UNORM;
case MESA_FORMAT_B5G6R5_UNORM:
   return PIPE_FORMAT_B5G6R5_UNORM;
case MESA_FORMAT_B2G3R3_UNORM:
@@ -567,6 +569,8 @@ st_pipe_format_to_mesa_format(enum pipe_format format)
   return MESA_FORMAT_A1B5G5R5_UNORM;
case PIPE_FORMAT_B4G4R4A4_UNORM:
   return MESA_FORMAT_B4G4R4A4_UNORM;
+   case PIPE_FORMAT_A4B4G4R4_UNORM:
+  return MESA_FORMAT_A4B4G4R4_UNORM;
case PIPE_FORMAT_B5G6R5_UNORM:
   return MESA_FORMAT_B5G6R5_UNORM;
case PIPE_FORMAT_B2G3R3_UNORM:
@@ -1155,7 +1159,8 @@ static const struct format_mapping format_map[] = {
},
{
   { GL_RGBA4, GL_RGBA2, 0 },
-  { PIPE_FORMAT_B4G4R4A4_UNORM, DEFAULT_RGBA_FORMATS }
+  { PIPE_FORMAT_B4G4R4A4_UNORM, PIPE_FORMAT_A4B4G4R4_UNORM,
+DEFAULT_RGBA_FORMATS }
},
{
   { GL_RGB5_A1, 0 },
@@ -1170,6 +1175,7 @@ static const struct format_mapping format_map[] = {
{
   { GL_RGB4 },
   { PIPE_FORMAT_B4G4R4X4_UNORM, PIPE_FORMAT_B4G4R4A4_UNORM,
+PIPE_FORMAT_A4B4G4R4_UNORM,
 DEFAULT_RGB_FORMATS }
},
{
-- 
2.15.0

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[Mesa-dev] [PATCH 1/3] mesa: Drop incorrect A4B4G4R4 _mesa_format_matches_format_and_type() cases.

[Eric Anholt]

swapBytes operates on bytes, not 4-bit channels, so you can't just take
non-swapBytes cases and flip the REV flag.

Avoids piglit texture-packed-formats regressions when enabling the
ABGR format.

Fixes: c5a5c9a7db89 ("mesa/formats: add new mesa formats and their pack/unpack 
functions.")
---
 src/mesa/main/formats.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index c1d8641116ec..8d32757a8795 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -1568,15 +1568,9 @@ _mesa_format_matches_format_and_type(mesa_format 
mesa_format,
   if (format == GL_RGBA && type == GL_UNSIGNED_SHORT_4_4_4_4 && !swapBytes)
  return GL_TRUE;
 
-  if (format == GL_RGBA && type == GL_UNSIGNED_SHORT_4_4_4_4_REV && 
swapBytes)
- return GL_TRUE;
-
   if (format == GL_ABGR_EXT && type == GL_UNSIGNED_SHORT_4_4_4_4_REV && 
!swapBytes)
  return GL_TRUE;
 
-  if (format == GL_ABGR_EXT && type == GL_UNSIGNED_SHORT_4_4_4_4 && 
swapBytes)
- return GL_TRUE;
-
   return GL_FALSE;
 
case MESA_FORMAT_R4G4B4A4_UNORM:
-- 
2.15.0

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[Mesa-dev] [PATCH 3/3] broadcom/vc5: Switch our RGBA4 support to the new gallium format.

[Eric Anholt]

Fixes fbo-generatemipmap-formats, fbo-alphatest-formats, etc. tests for
GL_RGBA4, GL_RGB4, GL_RGBA2, etc.
---
 src/gallium/drivers/vc5/v3dx_format_table.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/gallium/drivers/vc5/v3dx_format_table.c 
b/src/gallium/drivers/vc5/v3dx_format_table.c
index 6d198a225f07..884f7373a173 100644
--- a/src/gallium/drivers/vc5/v3dx_format_table.c
+++ b/src/gallium/drivers/vc5/v3dx_format_table.c
@@ -70,8 +70,7 @@ static const struct vc5_format format_table[] = {
 FORMAT(R10G10B10A2_UNORM, RGB10_A2, RGB10_A2,SWIZ_XYZW, 16, 0),
 FORMAT(B10G10R10A2_UINT,  RGB10_A2UI,   RGB10_A2UI,  SWIZ_ZYXW, 16, 0),
 
-FORMAT(B4G4R4A4_UNORM,ABGR, RGBA4,   SWIZ_YZWX, 16, 0),
-FORMAT(B4G4R4X4_UNORM,ABGR, RGBA4,   SWIZ_YZW1, 16, 0),
+FORMAT(A4B4G4R4_UNORM,ABGR, RGBA4,   SWIZ_XYZW, 16, 0),
 
 FORMAT(A1B5G5R5_UNORM,ABGR1555, RGB5_A1, SWIZ_XYZW, 16, 0),
 FORMAT(X1B5G5R5_UNORM,ABGR1555, RGB5_A1, SWIZ_XYZ1, 16, 0),
-- 
2.15.0

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[Mesa-dev] [Bug 104374] Cemu 1.11.1 via Wine using Mesa Mild exposes LLVM AMDGPU bugs on RX Vega..

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104374

--- Comment #2 from João Henrique  ---
This is the same issue as https://bugs.freedesktop.org/show_bug.cgi?id=104902
and it is reproducible on non mesa_mild branches (such as Padoka PPA)

Included in that bug report is a piece of code to reproduce the issue without
needing any additional data, only requiring SDL2 and GLEW.

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Re: [Mesa-dev] [PATCH] gallivm/llvmpipe: add const qualifiers on sampler variables

[Roland Scheidegger]

Makes sense.
Reviewed-by: Roland Scheidegger 

Am 01.02.2018 um 21:18 schrieb Brian Paul:
> Once a lp_build_sampler_soa or lp_build_sampler_aos object is created,
> it should never be modified.  Found by inspection.
> ---
>  src/gallium/auxiliary/draw/draw_llvm.c  | 2 +-
>  src/gallium/auxiliary/gallivm/lp_bld_tgsi.h | 8 
>  src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c | 2 +-
>  src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c | 2 +-
>  src/gallium/drivers/llvmpipe/lp_state_fs.c  | 2 +-
>  5 files changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/src/gallium/auxiliary/draw/draw_llvm.c 
> b/src/gallium/auxiliary/draw/draw_llvm.c
> index 8de29ea..69c1080 100644
> --- a/src/gallium/auxiliary/draw/draw_llvm.c
> +++ b/src/gallium/auxiliary/draw/draw_llvm.c
> @@ -606,7 +606,7 @@ generate_vs(struct draw_llvm_variant *variant,
>  const LLVMValueRef (*inputs)[TGSI_NUM_CHANNELS],
>  const struct lp_bld_tgsi_system_values *system_values,
>  LLVMValueRef context_ptr,
> -struct lp_build_sampler_soa *draw_sampler,
> +const struct lp_build_sampler_soa *draw_sampler,
>  boolean clamp_vertex_color)
>  {
> struct draw_llvm *llvm = variant->llvm;
> diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.h 
> b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.h
> index a50..309ece8 100644
> --- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.h
> +++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.h
> @@ -201,7 +201,7 @@ struct lp_build_sampler_soa
>  struct lp_build_sampler_aos
>  {
> LLVMValueRef
> -   (*emit_fetch_texel)( struct lp_build_sampler_aos *sampler,
> +   (*emit_fetch_texel)( const struct lp_build_sampler_aos *sampler,
>  struct lp_build_context *bld,
>  unsigned target, /* TGSI_TEXTURE_* */
>  unsigned unit,
> @@ -228,7 +228,7 @@ lp_build_tgsi_soa(struct gallivm_state *gallivm,
>LLVMValueRef (*outputs)[4],
>LLVMValueRef context_ptr,
>LLVMValueRef thread_data_ptr,
> -  struct lp_build_sampler_soa *sampler,
> +  const struct lp_build_sampler_soa *sampler,
>const struct tgsi_shader_info *info,
>const struct lp_build_tgsi_gs_iface *gs_iface);
>  
> @@ -241,7 +241,7 @@ lp_build_tgsi_aos(struct gallivm_state *gallivm,
>LLVMValueRef consts_ptr,
>const LLVMValueRef *inputs,
>LLVMValueRef *outputs,
> -  struct lp_build_sampler_aos *sampler,
> +  const struct lp_build_sampler_aos *sampler,
>const struct tgsi_shader_info *info);
>  
>  
> @@ -545,7 +545,7 @@ struct lp_build_tgsi_aos_context
> const LLVMValueRef *inputs;
> LLVMValueRef *outputs;
>  
> -   struct lp_build_sampler_aos *sampler;
> +   const struct lp_build_sampler_aos *sampler;
>  
> struct tgsi_declaration_sampler_view sv[PIPE_MAX_SHADER_SAMPLER_VIEWS];
>  
> diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c 
> b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
> index 2529c6a..85b2e8a 100644
> --- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
> +++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
> @@ -862,7 +862,7 @@ lp_build_tgsi_aos(struct gallivm_state *gallivm,
>LLVMValueRef consts_ptr,
>const LLVMValueRef *inputs,
>LLVMValueRef *outputs,
> -  struct lp_build_sampler_aos *sampler,
> +  const struct lp_build_sampler_aos *sampler,
>const struct tgsi_shader_info *info)
>  {
> struct lp_build_tgsi_aos_context bld;
> diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c 
> b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
> index 97efc3a..fad74c6 100644
> --- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
> +++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
> @@ -3780,7 +3780,7 @@ lp_build_tgsi_soa(struct gallivm_state *gallivm,
>LLVMValueRef (*outputs)[TGSI_NUM_CHANNELS],
>LLVMValueRef context_ptr,
>LLVMValueRef thread_data_ptr,
> -  struct lp_build_sampler_soa *sampler,
> +  const struct lp_build_sampler_soa *sampler,
>const struct tgsi_shader_info *info,
>const struct lp_build_tgsi_gs_iface *gs_iface)
>  {
> diff --git a/src/gallium/drivers/llvmpipe/lp_state_fs.c 
> b/src/gallium/drivers/llvmpipe/lp_state_fs.c
> index 0daf7ae..603fd84 100644
> --- a/src/gallium/drivers/llvmpipe/lp_state_fs.c
> +++ b/src/gallium/drivers/llvmpipe/lp_state_fs.c
> @@ -299,7 +299,7 @@ generate_fs_loop(struct gallivm_state *gallivm,
>   LLVMValueRef context_ptr,
>   LLVMValueRef num_loop,
>   struct 

[Mesa-dev] [PATCH] gallivm/llvmpipe: add const qualifiers on sampler variables

[Brian Paul]

Once a lp_build_sampler_soa or lp_build_sampler_aos object is created,
it should never be modified.  Found by inspection.
---
 src/gallium/auxiliary/draw/draw_llvm.c  | 2 +-
 src/gallium/auxiliary/gallivm/lp_bld_tgsi.h | 8 
 src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c | 2 +-
 src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c | 2 +-
 src/gallium/drivers/llvmpipe/lp_state_fs.c  | 2 +-
 5 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/gallium/auxiliary/draw/draw_llvm.c 
b/src/gallium/auxiliary/draw/draw_llvm.c
index 8de29ea..69c1080 100644
--- a/src/gallium/auxiliary/draw/draw_llvm.c
+++ b/src/gallium/auxiliary/draw/draw_llvm.c
@@ -606,7 +606,7 @@ generate_vs(struct draw_llvm_variant *variant,
 const LLVMValueRef (*inputs)[TGSI_NUM_CHANNELS],
 const struct lp_bld_tgsi_system_values *system_values,
 LLVMValueRef context_ptr,
-struct lp_build_sampler_soa *draw_sampler,
+const struct lp_build_sampler_soa *draw_sampler,
 boolean clamp_vertex_color)
 {
struct draw_llvm *llvm = variant->llvm;
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.h 
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.h
index a50..309ece8 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.h
@@ -201,7 +201,7 @@ struct lp_build_sampler_soa
 struct lp_build_sampler_aos
 {
LLVMValueRef
-   (*emit_fetch_texel)( struct lp_build_sampler_aos *sampler,
+   (*emit_fetch_texel)( const struct lp_build_sampler_aos *sampler,
 struct lp_build_context *bld,
 unsigned target, /* TGSI_TEXTURE_* */
 unsigned unit,
@@ -228,7 +228,7 @@ lp_build_tgsi_soa(struct gallivm_state *gallivm,
   LLVMValueRef (*outputs)[4],
   LLVMValueRef context_ptr,
   LLVMValueRef thread_data_ptr,
-  struct lp_build_sampler_soa *sampler,
+  const struct lp_build_sampler_soa *sampler,
   const struct tgsi_shader_info *info,
   const struct lp_build_tgsi_gs_iface *gs_iface);
 
@@ -241,7 +241,7 @@ lp_build_tgsi_aos(struct gallivm_state *gallivm,
   LLVMValueRef consts_ptr,
   const LLVMValueRef *inputs,
   LLVMValueRef *outputs,
-  struct lp_build_sampler_aos *sampler,
+  const struct lp_build_sampler_aos *sampler,
   const struct tgsi_shader_info *info);
 
 
@@ -545,7 +545,7 @@ struct lp_build_tgsi_aos_context
const LLVMValueRef *inputs;
LLVMValueRef *outputs;
 
-   struct lp_build_sampler_aos *sampler;
+   const struct lp_build_sampler_aos *sampler;
 
struct tgsi_declaration_sampler_view sv[PIPE_MAX_SHADER_SAMPLER_VIEWS];
 
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c 
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
index 2529c6a..85b2e8a 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
@@ -862,7 +862,7 @@ lp_build_tgsi_aos(struct gallivm_state *gallivm,
   LLVMValueRef consts_ptr,
   const LLVMValueRef *inputs,
   LLVMValueRef *outputs,
-  struct lp_build_sampler_aos *sampler,
+  const struct lp_build_sampler_aos *sampler,
   const struct tgsi_shader_info *info)
 {
struct lp_build_tgsi_aos_context bld;
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c 
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
index 97efc3a..fad74c6 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
@@ -3780,7 +3780,7 @@ lp_build_tgsi_soa(struct gallivm_state *gallivm,
   LLVMValueRef (*outputs)[TGSI_NUM_CHANNELS],
   LLVMValueRef context_ptr,
   LLVMValueRef thread_data_ptr,
-  struct lp_build_sampler_soa *sampler,
+  const struct lp_build_sampler_soa *sampler,
   const struct tgsi_shader_info *info,
   const struct lp_build_tgsi_gs_iface *gs_iface)
 {
diff --git a/src/gallium/drivers/llvmpipe/lp_state_fs.c 
b/src/gallium/drivers/llvmpipe/lp_state_fs.c
index 0daf7ae..603fd84 100644
--- a/src/gallium/drivers/llvmpipe/lp_state_fs.c
+++ b/src/gallium/drivers/llvmpipe/lp_state_fs.c
@@ -299,7 +299,7 @@ generate_fs_loop(struct gallivm_state *gallivm,
  LLVMValueRef context_ptr,
  LLVMValueRef num_loop,
  struct lp_build_interp_soa_context *interp,
- struct lp_build_sampler_soa *sampler,
+ const struct lp_build_sampler_soa *sampler,
  LLVMValueRef mask_store,
  LLVMValueRef (*out_color)[4],
  LLVMValueRef depth_ptr,
-- 
2.7.4

Re: [Mesa-dev] [PATCH 2/9] glsl: add u64->fp64 and i64->fp64 builtins.

[Elie Tournier]

On Thu, Feb 01, 2018 at 10:00:12AM -0800, Dylan Baker wrote:
> There are changes from Makefile.sources that need be ported to corresponding
> meson.build files as well.
Oh yes, nice spot. I will do it on my local fp64 branch too.
> 
> It looks like builtin_float64.h is generated from float64.glsl, is that right?
Like builtin_int64h and int64.glsl, builtin_float64.h is generated from 
float64.glsl.

> I'm not very happy about checking in a generated file for all of the reasons
> that we don't check generated files in. I recognize that trying to generate 
> code
> from an in tree binary at compile time makes the cross compiling situation 
> less
> than ideal since we would need to bootstrap the glsl compiler, but it's still
> annoying. This is why we stopped using glsl compilation for mesa, and added
> tools like nir_builder and ir_builder. I guess that's a pretty big complaint 
> and
> I don't expect you to fix it, but it's frustrating that we're going to have to
> check generated code in and deal with all the problems that come along with
> that.
This project is quite big. Using ir_builder would make this project even bigger.
At least for me. ;)
> 
> Dylan
> 
> Quoting Dave Airlie (2018-01-31 19:33:51)
> > From: Elie Tournier 
> > 
> > This adds the first two fp64 builtins.
> > They are for int/uint to fp64 conversions.
> > 
> > cayman hw can't do it, and this avoids me having to lower it in
> > the backend, and also starts to provide some of the soft fp64
> > infrastructure.
> > 
> > [airlied: extracted from Elie's tree]
> > Signed-off-by: Dave Airlie 
> > ---
> >  src/compiler/Makefile.sources   |   1 +
> >  src/compiler/glsl/builtin_float64.h | 872 
> > 
> >  src/compiler/glsl/builtin_functions.cpp |   8 +
> >  src/compiler/glsl/builtin_functions.h   |   6 +
> >  src/compiler/glsl/float64.glsl  | 126 +
> >  src/compiler/glsl/generate_ir.cpp   |   2 +-
> >  6 files changed, 1014 insertions(+), 1 deletion(-)
> >  create mode 100644 src/compiler/glsl/builtin_float64.h
> >  create mode 100644 src/compiler/glsl/float64.glsl
> > 
> > diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
> > index bb93ba68a2..9623b3ea62 100644
> > --- a/src/compiler/Makefile.sources
> > +++ b/src/compiler/Makefile.sources
> > @@ -22,6 +22,7 @@ LIBGLSL_FILES = \
> > glsl/builtin_functions.cpp \
> > glsl/builtin_functions.h \
> > glsl/builtin_int64.h \
> > +   glsl/builtin_float64.h \
> > glsl/builtin_types.cpp \
> > glsl/builtin_variables.cpp \
> > glsl/generate_ir.cpp \
> > diff --git a/src/compiler/glsl/builtin_float64.h 
> > b/src/compiler/glsl/builtin_float64.h
> > new file mode 100644
> > index 00..5747d22418
> > --- /dev/null
> > +++ b/src/compiler/glsl/builtin_float64.h
> > @@ -0,0 +1,872 @@
> > +ir_function_signature *
> > +countLeadingZeros32(void *mem_ctx, builtin_available_predicate avail)
> > +{
> > +   ir_function_signature *const sig =
> > +  new(mem_ctx) ir_function_signature(glsl_type::int_type, avail);
> > +   ir_factory body(>body, mem_ctx);
> > +   sig->is_defined = true;
> > +
> > +   exec_list sig_parameters;
> > +
> > +   ir_variable *const r000B = new(mem_ctx) 
> > ir_variable(glsl_type::uint_type, "a", ir_var_function_in);
> > +   sig_parameters.push_tail(r000B);
> > +   ir_variable *const r000C = body.make_temp(glsl_type::int_type, 
> > "return_value");
> > +   ir_variable *const r000D = new(mem_ctx) 
> > ir_variable(glsl_type::int_type, "shiftCount", ir_var_auto);
> > +   body.emit(r000D);
> > +   /* IF CONDITION */
> > +   ir_expression *const r000F = equal(r000B, body.constant(0u));
> > +   ir_if *f000E = new(mem_ctx) ir_if(operand(r000F).val);
> > +   exec_list *const f000E_parent_instructions = body.instructions;
> > +
> > +  /* THEN INSTRUCTIONS */
> > +  body.instructions = >then_instructions;
> > +
> > +  body.emit(assign(r000C, body.constant(int(32)), 0x01));
> > +
> > +
> > +  /* ELSE INSTRUCTIONS */
> > +  body.instructions = >else_instructions;
> > +
> > +  body.emit(assign(r000D, body.constant(int(0)), 0x01));
> > +
> > +  /* IF CONDITION */
> > +  ir_expression *const r0011 = bit_and(r000B, 
> > body.constant(4294901760u));
> > +  ir_expression *const r0012 = equal(r0011, body.constant(0u));
> > +  ir_if *f0010 = new(mem_ctx) ir_if(operand(r0012).val);
> > +  exec_list *const f0010_parent_instructions = body.instructions;
> > +
> > + /* THEN INSTRUCTIONS */
> > + body.instructions = >then_instructions;
> > +
> > + body.emit(assign(r000D, body.constant(int(16)), 0x01));
> > +
> > + body.emit(assign(r000B, lshift(r000B, body.constant(int(16))), 
> > 0x01));
> > +
> > +
> > +  body.instructions = f0010_parent_instructions;
> > +  body.emit(f0010);
> > +
> > +  /* END IF */
> > +
> > +  /* IF CONDITION */
> > +  

Re: [Mesa-dev] [PATCH 2/9] glsl: add u64->fp64 and i64->fp64 builtins.

[Dylan Baker]

There are changes from Makefile.sources that need be ported to corresponding
meson.build files as well.

It looks like builtin_float64.h is generated from float64.glsl, is that right?
I'm not very happy about checking in a generated file for all of the reasons
that we don't check generated files in. I recognize that trying to generate code
from an in tree binary at compile time makes the cross compiling situation less
than ideal since we would need to bootstrap the glsl compiler, but it's still
annoying. This is why we stopped using glsl compilation for mesa, and added
tools like nir_builder and ir_builder. I guess that's a pretty big complaint and
I don't expect you to fix it, but it's frustrating that we're going to have to
check generated code in and deal with all the problems that come along with
that.

Dylan

Quoting Dave Airlie (2018-01-31 19:33:51)
> From: Elie Tournier 
> 
> This adds the first two fp64 builtins.
> They are for int/uint to fp64 conversions.
> 
> cayman hw can't do it, and this avoids me having to lower it in
> the backend, and also starts to provide some of the soft fp64
> infrastructure.
> 
> [airlied: extracted from Elie's tree]
> Signed-off-by: Dave Airlie 
> ---
>  src/compiler/Makefile.sources   |   1 +
>  src/compiler/glsl/builtin_float64.h | 872 
> 
>  src/compiler/glsl/builtin_functions.cpp |   8 +
>  src/compiler/glsl/builtin_functions.h   |   6 +
>  src/compiler/glsl/float64.glsl  | 126 +
>  src/compiler/glsl/generate_ir.cpp   |   2 +-
>  6 files changed, 1014 insertions(+), 1 deletion(-)
>  create mode 100644 src/compiler/glsl/builtin_float64.h
>  create mode 100644 src/compiler/glsl/float64.glsl
> 
> diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
> index bb93ba68a2..9623b3ea62 100644
> --- a/src/compiler/Makefile.sources
> +++ b/src/compiler/Makefile.sources
> @@ -22,6 +22,7 @@ LIBGLSL_FILES = \
> glsl/builtin_functions.cpp \
> glsl/builtin_functions.h \
> glsl/builtin_int64.h \
> +   glsl/builtin_float64.h \
> glsl/builtin_types.cpp \
> glsl/builtin_variables.cpp \
> glsl/generate_ir.cpp \
> diff --git a/src/compiler/glsl/builtin_float64.h 
> b/src/compiler/glsl/builtin_float64.h
> new file mode 100644
> index 00..5747d22418
> --- /dev/null
> +++ b/src/compiler/glsl/builtin_float64.h
> @@ -0,0 +1,872 @@
> +ir_function_signature *
> +countLeadingZeros32(void *mem_ctx, builtin_available_predicate avail)
> +{
> +   ir_function_signature *const sig =
> +  new(mem_ctx) ir_function_signature(glsl_type::int_type, avail);
> +   ir_factory body(>body, mem_ctx);
> +   sig->is_defined = true;
> +
> +   exec_list sig_parameters;
> +
> +   ir_variable *const r000B = new(mem_ctx) ir_variable(glsl_type::uint_type, 
> "a", ir_var_function_in);
> +   sig_parameters.push_tail(r000B);
> +   ir_variable *const r000C = body.make_temp(glsl_type::int_type, 
> "return_value");
> +   ir_variable *const r000D = new(mem_ctx) ir_variable(glsl_type::int_type, 
> "shiftCount", ir_var_auto);
> +   body.emit(r000D);
> +   /* IF CONDITION */
> +   ir_expression *const r000F = equal(r000B, body.constant(0u));
> +   ir_if *f000E = new(mem_ctx) ir_if(operand(r000F).val);
> +   exec_list *const f000E_parent_instructions = body.instructions;
> +
> +  /* THEN INSTRUCTIONS */
> +  body.instructions = >then_instructions;
> +
> +  body.emit(assign(r000C, body.constant(int(32)), 0x01));
> +
> +
> +  /* ELSE INSTRUCTIONS */
> +  body.instructions = >else_instructions;
> +
> +  body.emit(assign(r000D, body.constant(int(0)), 0x01));
> +
> +  /* IF CONDITION */
> +  ir_expression *const r0011 = bit_and(r000B, 
> body.constant(4294901760u));
> +  ir_expression *const r0012 = equal(r0011, body.constant(0u));
> +  ir_if *f0010 = new(mem_ctx) ir_if(operand(r0012).val);
> +  exec_list *const f0010_parent_instructions = body.instructions;
> +
> + /* THEN INSTRUCTIONS */
> + body.instructions = >then_instructions;
> +
> + body.emit(assign(r000D, body.constant(int(16)), 0x01));
> +
> + body.emit(assign(r000B, lshift(r000B, body.constant(int(16))), 
> 0x01));
> +
> +
> +  body.instructions = f0010_parent_instructions;
> +  body.emit(f0010);
> +
> +  /* END IF */
> +
> +  /* IF CONDITION */
> +  ir_expression *const r0014 = bit_and(r000B, 
> body.constant(4278190080u));
> +  ir_expression *const r0015 = equal(r0014, body.constant(0u));
> +  ir_if *f0013 = new(mem_ctx) ir_if(operand(r0015).val);
> +  exec_list *const f0013_parent_instructions = body.instructions;
> +
> + /* THEN INSTRUCTIONS */
> + body.instructions = >then_instructions;
> +
> + body.emit(assign(r000D, add(r000D, body.constant(int(8))), 0x01));
> +
> + body.emit(assign(r000B, lshift(r000B, body.constant(int(8))), 
> 0x01));
> +

Re: [Mesa-dev] [PATCH 1/6] meson: find python2 on macOS

[Dylan Baker]

Quoting Emil Velikov (2018-02-01 03:49:12)
> On 28 January 2018 at 14:24, Jon Turney  wrote:
> > From: Dylan Baker 
> >
> > ---
> >  meson.build | 8 +++-
> >  1 file changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/meson.build b/meson.build
> > index 824e3c46bc5..178743eddb1 100644
> > --- a/meson.build
> > +++ b/meson.build
> > @@ -642,7 +642,13 @@ if with_platform_android
> >pre_args += '-DHAVE_ANDROID_PLATFORM'
> >  endif
> >
> > -prog_python2 = find_program('python2')
> > +# Basically we can't trust Linux because one distro had decided that python
> > +# should be python3. macOS doesn't have a python2 binary, however.
> > +if build_machine.system() != 'darwin'
> > +  prog_python2 = find_program('python2')
> > +else
> > +  prog_python2 = find_program('python')
> > +endif
> 
> I think this is better suited in meson, thus everyone doesn't need to
> reinvent the wheel.
> Even if we're moving towards python2-free world ;-)
> 
> Until then, the patch looks reasonable.
> Reviewed-by: Emil Velikov 
> 
> -Emil

Meson does have a utility for finding python 3, and they'd take one for python 
2,
but since meson itself is written in python 3 only it seems kinda silly. After
the meson stuff settles I'd like to get on with converting our python generators
to be at least hybrid if not python 3 only.

Dylan


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Re: [Mesa-dev] [Test Patch] Meson: ensure vdpau has proper symbolsexposed

[Dylan Baker]

Emil had requested some changes, and it's on my list to get these respun
today and back on the list. I'll CC you on them.

Thanks for reminding me :)

Dylan

Quoting Marc Dietrich (2018-02-01 02:44:25)
> Am Mittwoch, 17. Januar 2018, 18:41:00 CET schrieb Dylan Baker:
> > I dug into what autotools is doing. It's using -Wl,--whole-archive to link
> > everything, in this target, not just the state tracker. I think I'm okay
> > with this patch given that, so I'm going to apply the same change to the
> > other media state trackers and send it out as a series.
> 
> ping?
> 
> > 
> > Quoting Dylan Baker (2018-01-11 09:24:42)
> > 
> > > Signed-off-by: Dylan Baker 
> > > ---
> > > 
> > >  src/gallium/targets/vdpau/meson.build | 16 +---
> > >  1 file changed, 13 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/src/gallium/targets/vdpau/meson.build
> > > b/src/gallium/targets/vdpau/meson.build index 67f1469fb0f..432a32a7340
> > > 100644
> > > --- a/src/gallium/targets/vdpau/meson.build
> > > +++ b/src/gallium/targets/vdpau/meson.build
> > > @@ -23,6 +23,7 @@
> > > 
> > >  # configure.ac)
> > >  
> > >  vdpau_link_args = []
> > > 
> > > +vdpau_link_with = []
> > > 
> > >  vdpau_link_depends = []
> > >  vdpau_drivers = []
> > > 
> > > @@ -35,6 +36,13 @@ if with_ld_dynamic_list
> > > 
> > >vdpau_link_depends += files('../dri-vdpau.dyn')
> > >  
> > >  endif
> > > 
> > > +if with_dri
> > > +  vdpau_link_with += libswdri
> > > +endif
> > > +if with_gallium_drisw_kms
> > > +  vdpau_link_with += libswkmsdri
> > > +endif
> > > +
> > > 
> > >  libvdpau_gallium = shared_library(
> > >  
> > >'vdpau_gallium',
> > >'target.c',
> > > 
> > > @@ -44,12 +52,14 @@ libvdpau_gallium = shared_library(
> > > 
> > >include_directories : [
> > >
> > >  inc_common, inc_util, inc_gallium_winsys, inc_gallium_drivers,
> > >
> > >],
> > > 
> > > +  link_whole : [libvdpau_st],
> > > 
> > >link_with : [
> > > 
> > > -libvdpau_st, libgalliumvlwinsys, libgalliumvl, libgallium,
> > > libmesa_util, -libpipe_loader_static, libws_null, libwsw,
> > > +libgalliumvlwinsys, libgalliumvl, libgallium, libmesa_util,
> > > +libpipe_loader_static, libws_null, libwsw, vdpau_link_with,
> > > 
> > >],
> > >dependencies : [
> > > 
> > > -dep_thread, dep_xcb, dep_x11_xcb, dep_xcb_dri2, dep_libdrm,
> > > +dep_thread, dep_xcb, dep_x11_xcb, dep_xcb_dri2, dep_xcb_dri3,
> > > +dep_xcb_present, dep_xshmfence, dep_xcb_xfixes, dep_xcb_sync,
> > > dep_libdrm,> 
> > >  driver_r300, driver_r600, driver_radeonsi, driver_nouveau,
> > >
> > >],
> > >link_depends : vdpau_link_depends,
> 


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Re: [Mesa-dev] [Mesa-stable] [PATCH 1/2] meson/swr: re-shuffle generated files

[Dylan Baker]

With the below nits fixed, for the series:
Reviewed-by: Dylan Baker 

Quoting George Kyriazis (2018-02-01 08:54:14)
> Move generated files from codegen/meson.build to other directories, in order
> to satisfy generated include file dependencies
> 
> Add correct file lists for architecture-specific libraries.
> 
> cc: mesa-sta...@lists.freedesktop.org
> cc: dy...@pnwbakers.com
> ---
>  src/gallium/drivers/swr/meson.build| 10 +--
>  .../drivers/swr/rasterizer/codegen/meson.build | 76 
> --
>  .../swr/rasterizer/core/backends/meson.build   | 63 ++
>  .../drivers/swr/rasterizer/jitter/meson.build  | 56 
>  4 files changed, 125 insertions(+), 80 deletions(-)
>  create mode 100644 
> src/gallium/drivers/swr/rasterizer/core/backends/meson.build
>  create mode 100644 src/gallium/drivers/swr/rasterizer/jitter/meson.build
> 
> diff --git a/src/gallium/drivers/swr/meson.build 
> b/src/gallium/drivers/swr/meson.build
> index ae86c8e..c61fd73 100644
> --- a/src/gallium/drivers/swr/meson.build
> +++ b/src/gallium/drivers/swr/meson.build
> @@ -151,7 +151,9 @@ files_swr_arch = files(
>  swr_context_files = files('swr_context.h')
>  swr_state_files = files('rasterizer/core/state.h')
>  swr_event_proto_files = files('rasterizer/archrast/events.proto')
> +subdir('rasterizer/jitter')
>  subdir('rasterizer/codegen')
> +subdir('rasterizer/core/backends')
>  
>  swr_incs = include_directories(
>'rasterizer/codegen', 'rasterizer/core', 'rasterizer/jitter',
> @@ -180,7 +182,7 @@ if with_swr_arches.contains('avx')
>swr_arch_defines += '-DHAVE_SWR_AVX'
>swr_arch_libs += shared_library(
>  'swrAVX',
> -files_swr_common,
> +[files_swr_common, files_swr_arch],
>  cpp_args : [swr_cpp_args, swr_avx_args, '-DKNOB_ARCH=KNOB_ARCH_AVX'],
>  link_args : [ld_args_gc_sections],
>  include_directories : [swr_incs],
> @@ -212,7 +214,7 @@ if with_swr_arches.contains('avx2')
>swr_arch_defines += '-DHAVE_SWR_AVX2'
>swr_arch_libs += shared_library(
>  'swrAVX2',
> -files_swr_common,
> +[files_swr_common, files_swr_arch],
>  cpp_args : [swr_cpp_args, swr_avx2_args, '-DKNOB_ARCH=KNOB_ARCH_AVX2'],
>  link_args : [ld_args_gc_sections],
>  include_directories : [swr_incs],
> @@ -236,7 +238,7 @@ if with_swr_arches.contains('knl')
>swr_arch_defines += '-DHAVE_SWR_KNL'
>swr_arch_libs += shared_library(
>  'swrKNL',
> -files_swr_common,
> +[files_swr_common, files_swr_arch],
>  cpp_args : [
>swr_cpp_args, swr_knl_args, '-DKNOB_ARCH=KNOB_ARCH_AVX512',
>'-DKNOB_ARCH_KNIGHTS',
> @@ -263,7 +265,7 @@ if with_swr_arches.contains('skx')
>swr_arch_defines += '-DHAVE_SWR_SKX'
>swr_arch_libs += shared_library(
>  'swrSKX',
> -files_swr_common,
> +[files_swr_common, files_swr_arch],
>  cpp_args : [swr_cpp_args, swr_skx_args, '-DKNOB_ARCH=KNOB_ARCH_AVX512'],
>  link_args : [ld_args_gc_sections],
>  include_directories : [swr_incs],
> diff --git a/src/gallium/drivers/swr/rasterizer/codegen/meson.build 
> b/src/gallium/drivers/swr/rasterizer/codegen/meson.build
> index a21f405..2cef0d3 100644
> --- a/src/gallium/drivers/swr/rasterizer/codegen/meson.build
> +++ b/src/gallium/drivers/swr/rasterizer/codegen/meson.build
> @@ -40,40 +40,6 @@ gen_knobs_h = custom_target(
>),
>  )
>  
> -gen_builder_hpp = custom_target(
> -  'gen_builder.hpp',
> -  input : [
> -'gen_llvm_ir_macros.py',
> -join_paths(
> -  dep_llvm.get_configtool_variable('includedir'), 'llvm', 'IR',
> -  'IRBuilder.h'
> -)
> -  ],
> -  output : 'gen_builder.hpp',
> -  command : [
> -prog_python2, '@INPUT0@', '--input', '@INPUT1@', '--output', '@OUTPUT@',
> -'--gen_h', '--output-dir', meson.current_build_dir()
> -  ],
> -  depend_files : files(
> -'templates/gen_builder.hpp',
> -'gen_common.py',
> -  ),
> -  build_by_default : true,
> -)
> -
> -gen_builder_x86_hpp = custom_target(
> -  'gen_builder_x86.hpp',
> -  input : 'gen_llvm_ir_macros.py',
> -  output : 'gen_builder_x86.hpp',
> -  command : [
> -prog_python2, '@INPUT0@', '--gen_x86_h', '--output', '@OUTPUT@',
> -'--output-dir', meson.current_build_dir()
> -  ],
> -  depend_files : files(
> -'templates/gen_builder.hpp',
> -'gen_common.py',
> -  ),
> -)
>  
>  # The generators above this are needed individually, while the below 
> generators
>  # are all inputs to the same lib, so they don't need unique names.
> @@ -114,45 +80,3 @@ foreach x : [['gen_ar_event.hpp', '--gen_event_hpp'],
>)
>  endforeach
>  
> -files_swr_common += custom_target(
> -  'gen_backend_pixel',
> -  input : 'gen_backends.py',
> -  output : [
> -'gen_BackendPixelRate0.cpp', 'gen_BackendPixelRate1.cpp',
> -'gen_BackendPixelRate2.cpp', 'gen_BackendPixelRate3.cpp',
> -'gen_BackendPixelRate.hpp',
> -  ],
> -  command : [
> -prog_python2, '@INPUT@',
> -'--outdir', 

[Mesa-dev] [Bug 104908] Texture Compression Hint not converted to enum16

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104908

Brian Paul  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #2 from Brian Paul  ---
Fixed with commit 030821a8737cd8a7be001e40dafc1879f3df7866

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Re: [Mesa-dev] [PATCH] renderonly: fix dumb BO allocation for non 32bpp formats

[Lucas Stach]

Am Mittwoch, den 31.01.2018, 11:37 + schrieb Daniel Stone:
> On 30 January 2018 at 14:22, Lucas Stach 
> wrote:
> > Take into account the resource format, instead of applying a
> > hardcoded
> > 32bpp. This not only over-allocates 16bpp formats, but also results
> > in
> > a wrong stride being filled into the handle.
> 
> Bikeshed: just use util_format_getblocksizebits()? getblocksize()
> internally just divides getblocksizebits by 8, so this is redundant.
> WIth that:
> Reviewed-by: Daniel Stone 

Thanks. Changed and pushed out with stable tag.

Regards,
Lucas
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Re: [Mesa-dev] [PATCH 0/8] Partly untangle pos/generic0 aliasing dependencies v2.

[Mathias Fröhlich]

Hi Brian,

On Thursday, 1 February 2018 17:17:57 CET Brian Paul wrote:
> Looks good.
> 
> Reviewed-by: Brian Paul 

Thanks!!

> I don't remember, do you need me to push these for you?

I used to have an account for mesa. I have not used that for some time, but I 
assume that it is still functional.
I think I will try at first!
Thanks for asking!

best

Mathias


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Re: [Mesa-dev] [PATCH 1/4] vbo: use vbo local var for draw call in vbo_save_playback_vertex_list()

[Mathias Fröhlich]

Hi Brian,

with the updated comment that Ilia found, also

Reviewed-by: Mathias Fröhlich 

best

Mathias

> ---
>  src/mesa/vbo/vbo_save_draw.c | 14 +++---
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/src/mesa/vbo/vbo_save_draw.c b/src/mesa/vbo/vbo_save_draw.c
> index 906ed22..859c605 100644
> --- a/src/mesa/vbo/vbo_save_draw.c
> +++ b/src/mesa/vbo/vbo_save_draw.c
> @@ -282,13 +282,13 @@ vbo_save_playback_vertex_list(struct gl_context *ctx, 
void *data)
>if (node->vertex_count > 0) {
>   GLuint min_index = node->start_vertex;
>   GLuint max_index = min_index + node->vertex_count - 1;
> - vbo_context(ctx)->draw_prims(ctx,
> -  node->prims,
> -  node->prim_count,
> -  NULL,
> -  GL_TRUE,
> -  min_index, max_index,
> -  NULL, 0, NULL);
> + vbo->draw_prims(ctx,
> + node->prims,
> + node->prim_count,
> + NULL,
> + GL_TRUE,
> + min_index, max_index,
> + NULL, 0, NULL);
>}
> }
>  
> 




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[Mesa-dev] [Bug 104908] Texture Compression Hint not converted to enum16

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104908

--- Comment #1 from Brian Paul  ---
The patch looks good to me.  I'll push it in a bit.

I don't see any other issues related to Hint.TextureCompression.
Unfortunately, there's no Piglit test that hits this.

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Re: [Mesa-dev] [PATCH 1/6] meson: find python2 on macOS

[Jon Turney]

On 01/02/2018 11:49, Emil Velikov wrote:

On 28 January 2018 at 14:24, Jon Turney  wrote:

From: Dylan Baker 

---
  meson.build | 8 +++-
  1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/meson.build b/meson.build
index 824e3c46bc5..178743eddb1 100644
--- a/meson.build
+++ b/meson.build
@@ -642,7 +642,13 @@ if with_platform_android
pre_args += '-DHAVE_ANDROID_PLATFORM'
  endif

-prog_python2 = find_program('python2')
+# Basically we can't trust Linux because one distro had decided that python
+# should be python3. macOS doesn't have a python2 binary, however.
+if build_machine.system() != 'darwin'
+  prog_python2 = find_program('python2')
+else
+  prog_python2 = find_program('python')
+endif


I think this is better suited in meson, thus everyone doesn't need to
reinvent the wheel.
Even if we're moving towards python2-free world ;-)


I wonder why this can't just be find_program('python2', 'python'), 
similar to what autotools does?

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[Mesa-dev] [PATCH 2/4] travis: conditionalize building of prerequisites on if OS=linux

[Jon Turney]

Use a '|' YAML literal block to avoid the convoluted syntax needed to put
the entire conditional on a single line.

Signed-off-by: Jon Turney 
---
 .travis.yml | 91 +++--
 1 file changed, 47 insertions(+), 44 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index 211df3ec1e..1d6cf98519 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -419,62 +419,64 @@ install:
   # Install dependencies where we require specific versions (or where
   # disallowed by Travis CI's package whitelisting).
 
-  - wget $XORG_RELEASES/util/$XORGMACROS_VERSION.tar.bz2
-  - tar -jxvf $XORGMACROS_VERSION.tar.bz2
-  - (cd $XORGMACROS_VERSION && ./configure --prefix=$HOME/prefix && make 
install)
+  - |
+if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then
+  wget $XORG_RELEASES/util/$XORGMACROS_VERSION.tar.bz2 ;
+  tar -jxvf $XORGMACROS_VERSION.tar.bz2 ;
+  (cd $XORGMACROS_VERSION && ./configure --prefix=$HOME/prefix && make 
install) ;
 
-  - wget $XORG_RELEASES/proto/$GLPROTO_VERSION.tar.bz2
-  - tar -jxvf $GLPROTO_VERSION.tar.bz2
-  - (cd $GLPROTO_VERSION && ./configure --prefix=$HOME/prefix && make install)
+  wget $XORG_RELEASES/proto/$GLPROTO_VERSION.tar.bz2 ;
+  tar -jxvf $GLPROTO_VERSION.tar.bz2 ;
+  (cd $GLPROTO_VERSION && ./configure --prefix=$HOME/prefix && make 
install) ;
 
-  - wget $XORG_RELEASES/proto/$DRI2PROTO_VERSION.tar.bz2
-  - tar -jxvf $DRI2PROTO_VERSION.tar.bz2
-  - (cd $DRI2PROTO_VERSION && ./configure --prefix=$HOME/prefix && make 
install)
+  wget $XORG_RELEASES/proto/$DRI2PROTO_VERSION.tar.bz2 ;
+  tar -jxvf $DRI2PROTO_VERSION.tar.bz2 ;
+  (cd $DRI2PROTO_VERSION && ./configure --prefix=$HOME/prefix && make 
install) ;
 
-  - wget $XCB_RELEASES/$XCBPROTO_VERSION.tar.bz2
-  - tar -jxvf $XCBPROTO_VERSION.tar.bz2
-  - (cd $XCBPROTO_VERSION && ./configure --prefix=$HOME/prefix && make install)
+  wget $XCB_RELEASES/$XCBPROTO_VERSION.tar.bz2 ;
+  tar -jxvf $XCBPROTO_VERSION.tar.bz2 ;
+  (cd $XCBPROTO_VERSION && ./configure --prefix=$HOME/prefix && make 
install) ;
 
-  - wget $XCB_RELEASES/$LIBXCB_VERSION.tar.bz2
-  - tar -jxvf $LIBXCB_VERSION.tar.bz2
-  - (cd $LIBXCB_VERSION && ./configure --prefix=$HOME/prefix && make install)
+  wget $XCB_RELEASES/$LIBXCB_VERSION.tar.bz2 ;
+  tar -jxvf $LIBXCB_VERSION.tar.bz2 ;
+  (cd $LIBXCB_VERSION && ./configure --prefix=$HOME/prefix && make 
install) ;
 
-  - wget $XORG_RELEASES/lib/$LIBPCIACCESS_VERSION.tar.bz2
-  - tar -jxvf $LIBPCIACCESS_VERSION.tar.bz2
-  - (cd $LIBPCIACCESS_VERSION && ./configure --prefix=$HOME/prefix && make 
install)
+  wget $XORG_RELEASES/lib/$LIBPCIACCESS_VERSION.tar.bz2 ;
+  tar -jxvf $LIBPCIACCESS_VERSION.tar.bz2 ;
+  (cd $LIBPCIACCESS_VERSION && ./configure --prefix=$HOME/prefix && make 
install) ;
 
-  - wget http://dri.freedesktop.org/libdrm/$LIBDRM_VERSION.tar.bz2
-  - tar -jxvf $LIBDRM_VERSION.tar.bz2
-  - (cd $LIBDRM_VERSION && ./configure --prefix=$HOME/prefix --enable-vc4 
--enable-freedreno --enable-etnaviv-experimental-api && make install)
+  wget http://dri.freedesktop.org/libdrm/$LIBDRM_VERSION.tar.bz2 ;
+  tar -jxvf $LIBDRM_VERSION.tar.bz2 ;
+  (cd $LIBDRM_VERSION && ./configure --prefix=$HOME/prefix --enable-vc4 
--enable-freedreno --enable-etnaviv-experimental-api && make install) ;
 
-  - wget $XORG_RELEASES/lib/$LIBXSHMFENCE_VERSION.tar.bz2
-  - tar -jxvf $LIBXSHMFENCE_VERSION.tar.bz2
-  - (cd $LIBXSHMFENCE_VERSION && ./configure --prefix=$HOME/prefix && make 
install)
+  wget $XORG_RELEASES/lib/$LIBXSHMFENCE_VERSION.tar.bz2 ;
+  tar -jxvf $LIBXSHMFENCE_VERSION.tar.bz2 ;
+  (cd $LIBXSHMFENCE_VERSION && ./configure --prefix=$HOME/prefix && make 
install) ;
 
-  - wget 
http://people.freedesktop.org/~aplattner/vdpau/$LIBVDPAU_VERSION.tar.bz2
-  - tar -jxvf $LIBVDPAU_VERSION.tar.bz2
-  - (cd $LIBVDPAU_VERSION && ./configure --prefix=$HOME/prefix && make install)
+  wget 
http://people.freedesktop.org/~aplattner/vdpau/$LIBVDPAU_VERSION.tar.bz2 ;
+  tar -jxvf $LIBVDPAU_VERSION.tar.bz2 ;
+  (cd $LIBVDPAU_VERSION && ./configure --prefix=$HOME/prefix && make 
install) ;
 
-  - wget 
http://www.freedesktop.org/software/vaapi/releases/libva/$LIBVA_VERSION.tar.bz2
-  - tar -jxvf $LIBVA_VERSION.tar.bz2
-  - (cd $LIBVA_VERSION && ./configure --prefix=$HOME/prefix --disable-wayland 
--disable-dummy-driver && make install)
+  wget 
http://www.freedesktop.org/software/vaapi/releases/libva/$LIBVA_VERSION.tar.bz2 
;
+  tar -jxvf $LIBVA_VERSION.tar.bz2 ;
+  (cd $LIBVA_VERSION && ./configure --prefix=$HOME/prefix 
--disable-wayland --disable-dummy-driver && make install) ;
 
-  - wget $WAYLAND_RELEASES/$LIBWAYLAND_VERSION.tar.xz
-  - tar -axvf $LIBWAYLAND_VERSION.tar.xz
-  - (cd $LIBWAYLAND_VERSION && ./configure --prefix=$HOME/prefix 
--enable-libraries --without-host-scanner --disable-documentation 
--disable-dtd-validation && make install)
+  

[Mesa-dev] [PATCH 4/4] travis: add osx autotools build

[Jon Turney]

Signed-off-by: Jon Turney 
---
 .travis.yml | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/.travis.yml b/.travis.yml
index e18327bec9..fc137c9667 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -396,6 +396,36 @@ matrix:
 - libexpat1-dev
 - libx11-xcb-dev
 - libelf-dev
+- env:
+- LABEL="macOS make"
+- BUILD=make
+- MAKEFLAGS="-j4"
+- MAKE_CHECK_COMMAND="make check"
+- DRI_LOADERS="--with-platforms=x11 --disable-egl"
+  os: osx
+
+before_install:
+  - |
+if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then
+  HOMEBREW_NO_AUTO_UPDATE=1 brew install python3 ninja expat gettext ;
+  # Set PATH for homebrew pip3 installs
+  PATH="$HOME/Library/Python/3.6/bin:${PATH}" ;
+  # Set PKG_CONFIG_PATH for keg-only expat
+  PKG_CONFIG_PATH="/usr/local/opt/expat/lib/pkgconfig:${PKG_CONFIG_PATH}" ;
+  # Set PATH for keg-only gettext
+  PATH="/usr/local/opt/gettext/bin:${PATH}" ;
+
+  # Install xquartz for prereqs ...
+  XQUARTZ_VERSION="2.7.11" ;
+  wget -nv 
https://dl.bintray.com/xquartz/downloads/XQuartz-${XQUARTZ_VERSION}.dmg ;
+  hdiutil attach XQuartz-${XQUARTZ_VERSION}.dmg ;
+  sudo installer -pkg /Volumes/XQuartz-${XQUARTZ_VERSION}/XQuartz.pkg 
-target / ;
+  hdiutil detach /Volumes/XQuartz-${XQUARTZ_VERSION} ;
+  # ... and set paths
+  PATH="/opt/X11/bin:${PATH}" ;
+  
PKG_CONFIG_PATH="/opt/X11/share/pkgconfig:/opt/X11/lib/pkgconfig:${PKG_CONFIG_PATH}"
 ;
+  ACLOCAL="aclocal -I /opt/X11/share/aclocal -I /usr/local/share/aclocal" ;
+fi
 
 install:
   - pip2 install --user mako
-- 
2.16.1

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[Mesa-dev] [PATCH 0/4] Fix osx build and add to CI (reprise)

[Jon Turney]

Jon Turney (4):
  glx/test: fix building for osx
  travis: conditionalize building of prerequisites on if OS=linux
  travis: pip -> pip2
  travis: add osx autotools build

 .travis.yml   | 123 --
 src/glx/tests/fake_glx_screen.cpp |  11 
 src/glx/tests/indirect_api.cpp|   4 ++
 3 files changed, 93 insertions(+), 45 deletions(-)

-- 
2.16.1

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[Mesa-dev] [PATCH 3/4] travis: pip -> pip2

[Jon Turney]

On travis, for OSX, python2 from homebrew is pre-installed. per [1]:

 python points to the macOS system Python (with no manual PATH modification)
 python2 points to Homebrew’s Python 2.7.x (if installed)
 python3 points to Homebrew’s Python 3.x (if installed)
 pip doesn't exist
 pip2 points to Homebrew’s Python 2.7.x’s pip (if installed)
 pip3 points to Homebrew’s Python 3.x’s pip (if installed)

We will end up using 'python2' for building mesa.

Just use 'pip2' instead of 'pip', as that seems to work for all platforms on
travis.

[1] https://docs.brew.sh/Homebrew-and-Python.html

Signed-off-by: Jon Turney 
---
 .travis.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.travis.yml b/.travis.yml
index 1d6cf98519..e18327bec9 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -398,7 +398,7 @@ matrix:
 - libelf-dev
 
 install:
-  - pip install --user mako
+  - pip2 install --user mako
 
   # Install the latest meson from pip, since the version in the ubuntu repos is
   # often quite old.
-- 
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[Mesa-dev] [PATCH 1/4] glx/test: fix building for osx

[Jon Turney]

An additional stub for applegl_create_context() is needed
Cannot test indirect API as it's not built on osx, currently

Signed-off-by: Jon Turney 
---
 src/glx/tests/fake_glx_screen.cpp | 11 +++
 src/glx/tests/indirect_api.cpp|  4 
 2 files changed, 15 insertions(+)

diff --git a/src/glx/tests/fake_glx_screen.cpp 
b/src/glx/tests/fake_glx_screen.cpp
index 801f54a6fa..71e4e8ce48 100644
--- a/src/glx/tests/fake_glx_screen.cpp
+++ b/src/glx/tests/fake_glx_screen.cpp
@@ -75,6 +75,17 @@ indirect_create_context_attribs(struct glx_screen *base,
return indirect_create_context(base, config_base, shareList, 0);
 }
 
+#ifdef GLX_USE_APPLEGL
+extern "C" struct glx_context *
+applegl_create_context(struct glx_screen *base,
+  struct glx_config *config_base,
+  struct glx_context *shareList,
+  int renderType)
+{
+   return indirect_create_context(base, config_base, shareList, renderType);
+}
+#endif
+
 /* This is necessary so that we don't have to link with glxcurrent.c
  * which would require us to link with X libraries and what not.
  */
diff --git a/src/glx/tests/indirect_api.cpp b/src/glx/tests/indirect_api.cpp
index 34304a185e..b9a4ca0655 100644
--- a/src/glx/tests/indirect_api.cpp
+++ b/src/glx/tests/indirect_api.cpp
@@ -705,6 +705,8 @@ void __indirect_glFramebufferTextureLayer(void) { }
 }
 /*@}*/
 
+#ifndef GLX_USE_APPLEGL
+
 class IndirectAPI : public ::testing::Test {
 public:
virtual void SetUp();
@@ -1518,3 +1520,5 @@ TEST_F(IndirectAPI, EXT_texture_array)
 {
EXPECT_EQ((_glapi_proc) __indirect_glFramebufferTextureLayer, 
table[_glapi_get_proc_offset("glFramebufferTextureLayerEXT")]);
 }
+
+#endif
-- 
2.16.1

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Re: [Mesa-dev] [PATCH v2] mesa: enable ASTC/ETC1 compressed 3D textures

[Juan A. Suarez Romero]

On Thu, 2018-02-01 at 12:45 +0100, Juan A. Suarez Romero wrote:
> On Mon, 2018-01-29 at 16:25 -0800, Eric Anholt wrote:
> > "Juan A. Suarez Romero"  writes:
> > 
> > > Enable these kind of 3D texture when proper extensions are available.
> > > 
> > > Fixes KHR-GLES2.texture_3d.* with these textures.
> > > 
> > > v2: add better clarification (Eric)
> > > ---
> > >  src/mesa/main/teximage.c | 31 ---
> > >  1 file changed, 24 insertions(+), 7 deletions(-)
> > > 
> > > diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
> > > index e5f8bb0718f..56235898c66 100644
> > > --- a/src/mesa/main/teximage.c
> > > +++ b/src/mesa/main/teximage.c
> > > @@ -1487,6 +1487,9 @@ _mesa_target_can_be_compressed(const struct 
> > > gl_context *ctx, GLenum target,
> > >break;
> > > case GL_TEXTURE_3D:
> > >switch (layout) {
> > > +  case MESA_FORMAT_LAYOUT_ETC1:
> > > + target_can_be_compresed = 
> > > ctx->Extensions.OES_compressed_ETC1_RGB8_texture;
> > > + break;
> > >case MESA_FORMAT_LAYOUT_ETC2:
> > >   /* See ETC2/EAC comment in case GL_TEXTURE_CUBE_MAP_ARRAY. */
> > 
> > OK, I took a look at the ETC2/EAC comment above, this time, and it looks
> > like 3D textures are supposed to be not supported with ETC2 or ASTC
> > according to table 8.17 in GLES 3.2.
> > 
> > This is looking more like a testcase bug to me.
> 
> 
> Yes, you're right. This is similar to another patch I sent for review
> and that turned out it was wrong for the same reason (both patches are
> related with the same test).
> 
> So I withdraw this patch, and I'll send a fix for the testcase instead.
> 
> Thanks.
> 

After re-reading again more carefully, I think the patch is partially
correct, though it needs changes.

According to spec KHR_texture_compression_astc_{hdr,ldr} if hdr is
supported then the 3D textures column must be checked for all ASTC
textures.

If only LDR is supported, then it is kept unchecked, unless
KHR_texture_compression_astc_sliced_3d is also supported, which again mark as 
checked all ASTC textures for 3D Textures.

This is already correctly implemented in Mesa for CompressedTexImage3D.

But the last part of the patch was doing the check for
CompressedTexSubImage3D (incorrectly, which needs to be fixed). 

According to KHR_texture_compression_astc_{hdr,ldr}:


  An INVALID_OPERATION error is generated by CompressedTexSubImage3D if
   is TEXTURE_CUBE_MAP_ARRAY and the "Cube Map Array" column of
  table 8.19 is *not* checked, or if  is TEXTURE_3D and the "3D
  Tex." column of table 8.19 is *not* checked"


My understanding is that if HDR is implemented, or LDR and
astc_sliced_3d are implemented, then the 3D Tex. column is checked and
thus it is correct to call either CompressedTexImage3D a
CompressedTexSubImage3D.

I'll send a new patch.

> KHR_texture_compression_astc_sliced_3d
>   J.A.
> 
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Re: [Mesa-dev] [PATCH mesa 1/2] meson: centralise the libdrm versions information

[Emil Velikov]

On 31 January 2018 at 17:11, Dylan Baker  wrote:
> Quoting Emil Velikov (2018-01-31 03:42:00)
>> On 30 January 2018 at 21:31, Dylan Baker  wrote:
>> > Quoting Emil Velikov (2018-01-30 10:43:06)
>> >> On 29 January 2018 at 18:57, Dylan Baker  wrote:
>> >> > Quoting Eric Engestrom (2018-01-29 10:15:50)
>> >> >> The big comment is taken from the equivalent block in configure.ac
>> >> >>
>> >> >> Signed-off-by: Eric Engestrom 
>> >> >> ---
>> >> >>  meson.build | 30 
>> >> >> +
>> >> >>  src/gallium/targets/d3dadapter9/meson.build |  2 +-
>> >> >>  src/mesa/drivers/dri/meson.build|  2 +-
>> >> >>  3 files changed, 24 insertions(+), 10 deletions(-)
>> >> >>
>> >> >> diff --git a/meson.build b/meson.build
>> >> >> index 0a00798c2a5093ec803b..6d7a8e976ff6ad002d9a 100644
>> >> >> --- a/meson.build
>> >> >> +++ b/meson.build
>> >> >> @@ -41,6 +41,20 @@ pre_args = [
>> >> >>
>> >> >> '-DPACKAGE_BUGREPORT="https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa;',
>> >> >>  ]
>> >> >>
>> >> >> +# The idea is that libdrm is distributed as one cohesive package, even
>> >> >> +# though it is composed of multiple libraries. However some drivers
>> >> >> +# may have different version requirements than others. This list
>> >> >> +# codifies which drivers need which version of libdrm. Any libdrm
>> >> >> +# version dependencies in non-driver-specific code should be reflected
>> >> >> +# in the first entry.
>> >> >> +libdrm_version   = '2.4.75'
>> >> >> +libdrm_amdgpu_version= '2.4.89'
>> >> >> +libdrm_etnaviv_version   = '2.4.82'
>> >> >> +libdrm_freedreno_version = '2.4.82'
>> >> >> +libdrm_intel_version = '2.4.75'
>> >> >> +libdrm_nouveau_version   = '2.4.66'
>> >> >> +libdrm_radeon_version= '2.4.71'
>> >> >
>> >> > Is there any reason we can't just make these (for example):
>> >> > libdrm_radeon_version= '>= 2.4.71'
>> >> >
>> >> > Since that avoids all of the format calls?
>> >> >
>> >> Is there particular reason why meson doesn't allow plain
>> >> concatenation, and one must go through the format dance?
>> >> Off the top of my head, I think that most higher level programming
>> >> languages (including python) have it, making for clearer and more
>> >> obvious code.
>> >>
>> >> That aside:
>> >> A huge +1 from me on the idea, although the libdrm_foo checks should
>> >> become libdrm && libdrm_foo.
>> >> See commit 2b4eaabff01a3a8ea0c4742ac481492092c1ab4f.
>> >>
>> >> Thanks
>> >> Emil
>> >
>> > I'm confused by that commit. pkg-config is supposed to handle this, 
>> > libdrm_intel
>> > (for example) has `Requires : libdrm` in it, so when you generate libs you 
>> > get
>> > `-ldrm_intel -ldrm`. Why do we need to check libdrm as well? If it's just 
>> > that
>> > we need to make sure that the version matches we should fix the pkg-config 
>> > files
>> > in libdrm to set `Requires : libdrm >= version`. Or am I missing something?
>> >
>> Only libdrm_intel has Requires: libdrm. Everyone else has the
>> 'correct' Requires.Private
>> Thus adding a version check won't be enough.
>>
>> Personally the commit feels like a workaround but Dave and Ilia wanted
>> it, so we went ahead.
>>
>> -Emil
>
> If we need to ensure that the versions of libdrm == libdrm_* then
> Requires.private is the wrong field to use. What do you think the correct 
> thing
> to do here is?
>
The perfect solution is to go back in time ;-) That aside, I'd stick
with what Dave/Ilia is suggesting.

-Emil
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Re: [Mesa-dev] [PATCH 2/9] glsl: add u64->fp64 and i64->fp64 builtins.

[Roland Scheidegger]

I suppose this is a bit inefficient if the hw actually supports some
double ops?
I mean for uint->double you could just convert the low 8 bits and high
24 bits (or different split) separately to float, convert both to double
and add them. (I think should work for int->double exactly the same
despite the sign bit.)
But in any case, for hw not supporting double ops at all this looks like
the right approach.

Roland

Am 01.02.2018 um 04:33 schrieb Dave Airlie:
> From: Elie Tournier 
> 
> This adds the first two fp64 builtins.
> They are for int/uint to fp64 conversions.
> 
> cayman hw can't do it, and this avoids me having to lower it in
> the backend, and also starts to provide some of the soft fp64
> infrastructure.
> 
> [airlied: extracted from Elie's tree]
> Signed-off-by: Dave Airlie 
> ---
>  src/compiler/Makefile.sources   |   1 +
>  src/compiler/glsl/builtin_float64.h | 872 
> 
>  src/compiler/glsl/builtin_functions.cpp |   8 +
>  src/compiler/glsl/builtin_functions.h   |   6 +
>  src/compiler/glsl/float64.glsl  | 126 +
>  src/compiler/glsl/generate_ir.cpp   |   2 +-
>  6 files changed, 1014 insertions(+), 1 deletion(-)
>  create mode 100644 src/compiler/glsl/builtin_float64.h
>  create mode 100644 src/compiler/glsl/float64.glsl
> 
> diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
> index bb93ba68a2..9623b3ea62 100644
> --- a/src/compiler/Makefile.sources
> +++ b/src/compiler/Makefile.sources
> @@ -22,6 +22,7 @@ LIBGLSL_FILES = \
>   glsl/builtin_functions.cpp \
>   glsl/builtin_functions.h \
>   glsl/builtin_int64.h \
> + glsl/builtin_float64.h \
>   glsl/builtin_types.cpp \
>   glsl/builtin_variables.cpp \
>   glsl/generate_ir.cpp \
> diff --git a/src/compiler/glsl/builtin_float64.h 
> b/src/compiler/glsl/builtin_float64.h
> new file mode 100644
> index 00..5747d22418
> --- /dev/null
> +++ b/src/compiler/glsl/builtin_float64.h
> @@ -0,0 +1,872 @@
> +ir_function_signature *
> +countLeadingZeros32(void *mem_ctx, builtin_available_predicate avail)
> +{
> +   ir_function_signature *const sig =
> +  new(mem_ctx) ir_function_signature(glsl_type::int_type, avail);
> +   ir_factory body(>body, mem_ctx);
> +   sig->is_defined = true;
> +
> +   exec_list sig_parameters;
> +
> +   ir_variable *const r000B = new(mem_ctx) ir_variable(glsl_type::uint_type, 
> "a", ir_var_function_in);
> +   sig_parameters.push_tail(r000B);
> +   ir_variable *const r000C = body.make_temp(glsl_type::int_type, 
> "return_value");
> +   ir_variable *const r000D = new(mem_ctx) ir_variable(glsl_type::int_type, 
> "shiftCount", ir_var_auto);
> +   body.emit(r000D);
> +   /* IF CONDITION */
> +   ir_expression *const r000F = equal(r000B, body.constant(0u));
> +   ir_if *f000E = new(mem_ctx) ir_if(operand(r000F).val);
> +   exec_list *const f000E_parent_instructions = body.instructions;
> +
> +  /* THEN INSTRUCTIONS */
> +  body.instructions = >then_instructions;
> +
> +  body.emit(assign(r000C, body.constant(int(32)), 0x01));
> +
> +
> +  /* ELSE INSTRUCTIONS */
> +  body.instructions = >else_instructions;
> +
> +  body.emit(assign(r000D, body.constant(int(0)), 0x01));
> +
> +  /* IF CONDITION */
> +  ir_expression *const r0011 = bit_and(r000B, 
> body.constant(4294901760u));
> +  ir_expression *const r0012 = equal(r0011, body.constant(0u));
> +  ir_if *f0010 = new(mem_ctx) ir_if(operand(r0012).val);
> +  exec_list *const f0010_parent_instructions = body.instructions;
> +
> + /* THEN INSTRUCTIONS */
> + body.instructions = >then_instructions;
> +
> + body.emit(assign(r000D, body.constant(int(16)), 0x01));
> +
> + body.emit(assign(r000B, lshift(r000B, body.constant(int(16))), 
> 0x01));
> +
> +
> +  body.instructions = f0010_parent_instructions;
> +  body.emit(f0010);
> +
> +  /* END IF */
> +
> +  /* IF CONDITION */
> +  ir_expression *const r0014 = bit_and(r000B, 
> body.constant(4278190080u));
> +  ir_expression *const r0015 = equal(r0014, body.constant(0u));
> +  ir_if *f0013 = new(mem_ctx) ir_if(operand(r0015).val);
> +  exec_list *const f0013_parent_instructions = body.instructions;
> +
> + /* THEN INSTRUCTIONS */
> + body.instructions = >then_instructions;
> +
> + body.emit(assign(r000D, add(r000D, body.constant(int(8))), 0x01));
> +
> + body.emit(assign(r000B, lshift(r000B, body.constant(int(8))), 
> 0x01));
> +
> +
> +  body.instructions = f0013_parent_instructions;
> +  body.emit(f0013);
> +
> +  /* END IF */
> +
> +  /* IF CONDITION */
> +  ir_expression *const r0017 = bit_and(r000B, 
> body.constant(4026531840u));
> +  ir_expression *const r0018 = equal(r0017, body.constant(0u));
> +  ir_if *f0016 = new(mem_ctx) ir_if(operand(r0018).val);
> +  exec_list *const f0016_parent_instructions = 

Re: [Mesa-dev] [PATCH mesa 1/2] meson: centralise the libdrm versions information

[Dylan Baker]

Quoting Emil Velikov (2018-01-31 03:42:00)
> On 30 January 2018 at 21:31, Dylan Baker  wrote:
> > Quoting Emil Velikov (2018-01-30 10:43:06)
> >> On 29 January 2018 at 18:57, Dylan Baker  wrote:
> >> > Quoting Eric Engestrom (2018-01-29 10:15:50)
> >> >> The big comment is taken from the equivalent block in configure.ac
> >> >>
> >> >> Signed-off-by: Eric Engestrom 
> >> >> ---
> >> >>  meson.build | 30 
> >> >> +
> >> >>  src/gallium/targets/d3dadapter9/meson.build |  2 +-
> >> >>  src/mesa/drivers/dri/meson.build|  2 +-
> >> >>  3 files changed, 24 insertions(+), 10 deletions(-)
> >> >>
> >> >> diff --git a/meson.build b/meson.build
> >> >> index 0a00798c2a5093ec803b..6d7a8e976ff6ad002d9a 100644
> >> >> --- a/meson.build
> >> >> +++ b/meson.build
> >> >> @@ -41,6 +41,20 @@ pre_args = [
> >> >>
> >> >> '-DPACKAGE_BUGREPORT="https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa;',
> >> >>  ]
> >> >>
> >> >> +# The idea is that libdrm is distributed as one cohesive package, even
> >> >> +# though it is composed of multiple libraries. However some drivers
> >> >> +# may have different version requirements than others. This list
> >> >> +# codifies which drivers need which version of libdrm. Any libdrm
> >> >> +# version dependencies in non-driver-specific code should be reflected
> >> >> +# in the first entry.
> >> >> +libdrm_version   = '2.4.75'
> >> >> +libdrm_amdgpu_version= '2.4.89'
> >> >> +libdrm_etnaviv_version   = '2.4.82'
> >> >> +libdrm_freedreno_version = '2.4.82'
> >> >> +libdrm_intel_version = '2.4.75'
> >> >> +libdrm_nouveau_version   = '2.4.66'
> >> >> +libdrm_radeon_version= '2.4.71'
> >> >
> >> > Is there any reason we can't just make these (for example):
> >> > libdrm_radeon_version= '>= 2.4.71'
> >> >
> >> > Since that avoids all of the format calls?
> >> >
> >> Is there particular reason why meson doesn't allow plain
> >> concatenation, and one must go through the format dance?
> >> Off the top of my head, I think that most higher level programming
> >> languages (including python) have it, making for clearer and more
> >> obvious code.
> >>
> >> That aside:
> >> A huge +1 from me on the idea, although the libdrm_foo checks should
> >> become libdrm && libdrm_foo.
> >> See commit 2b4eaabff01a3a8ea0c4742ac481492092c1ab4f.
> >>
> >> Thanks
> >> Emil
> >
> > I'm confused by that commit. pkg-config is supposed to handle this, 
> > libdrm_intel
> > (for example) has `Requires : libdrm` in it, so when you generate libs you 
> > get
> > `-ldrm_intel -ldrm`. Why do we need to check libdrm as well? If it's just 
> > that
> > we need to make sure that the version matches we should fix the pkg-config 
> > files
> > in libdrm to set `Requires : libdrm >= version`. Or am I missing something?
> >
> Only libdrm_intel has Requires: libdrm. Everyone else has the
> 'correct' Requires.Private
> Thus adding a version check won't be enough.
> 
> Personally the commit feels like a workaround but Dave and Ilia wanted
> it, so we went ahead.
> 
> -Emil

If we need to ensure that the versions of libdrm == libdrm_* then
Requires.private is the wrong field to use. What do you think the correct thing
to do here is?

Dylan


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Re: [Mesa-dev] [PATCH libdrm] meson: fix libdrm_nouveau pkgconfig include directories

[Dylan Baker]

Thanks!

Quoting Eric Engestrom (2018-01-31 03:14:50)
> On Thursday, 2018-01-25 16:14:45 -0800, Dylan Baker wrote:
> > Signed-off-by: Dylan Baker 
> 
> Reviewed-by: Eric Engestrom 
> 
> > ---
> > 
> > I have tested building every mesa driver against this (with and without 
> > udev!)
> > so I'm pretty sure that this is the last pkgbuild problem.
> > 
> > I'm sure I'll be sad in a day or two...
> > 
> >  nouveau/meson.build | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/nouveau/meson.build b/nouveau/meson.build
> > index bfecf84b..f031cd63 100644
> > --- a/nouveau/meson.build
> > +++ b/nouveau/meson.build
> > @@ -45,7 +45,7 @@ install_headers(
> >  pkg.generate(
> >name : 'libdrm_nouveau',
> >libraries : libdrm_nouveau,
> > -  subdirs : ['.', 'nouveau'],
> > +  subdirs : ['.', 'libdrm', 'libdrm/nouveau'],
> >version : meson.project_version(),
> >requires_private : 'libdrm',
> >description : 'Userspace interface to nouveau kernel DRM services',
> > -- 
> > 2.16.0
> > 


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Re: [Mesa-dev] [PATCH mesa v2 1/2] meson: centralise the libdrm versions information

[Dylan Baker]

Quoting Eric Engestrom (2018-01-31 03:47:25)
> The big comment is taken from the equivalent block in configure.ac
> 
> Signed-off-by: Eric Engestrom 
> ---
>  meson.build | 30 
> +
>  src/gallium/targets/d3dadapter9/meson.build |  2 +-
>  src/mesa/drivers/dri/meson.build|  2 +-
>  3 files changed, 24 insertions(+), 10 deletions(-)
> 
> diff --git a/meson.build b/meson.build
> index 80ea60ffa7d915654a89..30c2198d77dde383d7ac 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -41,6 +41,20 @@ pre_args = [
>
> '-DPACKAGE_BUGREPORT="https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa;',
>  ]
>  
> +# The idea is that libdrm is distributed as one cohesive package, even
> +# though it is composed of multiple libraries. However some drivers
> +# may have different version requirements than others. This list
> +# codifies which drivers need which version of libdrm. Any libdrm
> +# version dependencies in non-driver-specific code should be reflected
> +# in the first entry.
> +libdrm_version   = '2.4.75'
> +libdrm_amdgpu_version= '2.4.89'
> +libdrm_etnaviv_version   = '2.4.82'
> +libdrm_freedreno_version = '2.4.82'
> +libdrm_intel_version = '2.4.75'
> +libdrm_nouveau_version   = '2.4.66'
> +libdrm_radeon_version= '2.4.71'
> +
>  with_vulkan_icd_dir = get_option('vulkan-icd-dir')
>  with_tests = get_option('build-tests')
>  with_valgrind = get_option('valgrind')
> @@ -199,7 +213,7 @@ endif
>  
>  dep_libdrm_intel = []
>  if with_dri_i915 or with_gallium_i915
> -  dep_libdrm_intel = dependency('libdrm_intel', version : '>= 2.4.75')
> +  dep_libdrm_intel = dependency('libdrm_intel', version : '>= ' + 
> libdrm_intel_version)
>  endif
>  
>  system_has_kms_drm = ['openbsd', 'netbsd', 'freebsd', 'dragonfly', 
> 'linux'].contains(host_machine.system())
> @@ -922,7 +936,7 @@ else
>  endif
>  
>  with_gallium_drisw_kms = false
> -dep_libdrm = dependency('libdrm', version : '>= 2.4.75',
> +dep_libdrm = dependency('libdrm', version : '>= ' + libdrm_version,
>  required : with_dri2 or with_dri3)
>  if dep_libdrm.found()
>pre_args += '-DHAVE_LIBDRM'
> @@ -957,20 +971,20 @@ dep_libdrm_nouveau = []
>  dep_libdrm_etnaviv = []
>  dep_libdrm_freedreno = []
>  if with_amd_vk or with_gallium_radeonsi
> -  dep_libdrm_amdgpu = dependency('libdrm_amdgpu', version : '>= 2.4.89')
> +  dep_libdrm_amdgpu = dependency('libdrm_amdgpu', version : '>= ' + 
> libdrm_amdgpu_version)
>  endif
>  if (with_gallium_radeonsi or with_dri_r100 or with_dri_r200 or
>  with_gallium_r300 or with_gallium_r600)
> -  dep_libdrm_radeon = dependency('libdrm_radeon', version : '>= 2.4.71')
> +  dep_libdrm_radeon = dependency('libdrm_radeon', version : '>= ' + 
> libdrm_radeon_version)
>  endif
>  if with_gallium_nouveau or with_dri_nouveau
> -  dep_libdrm_nouveau = dependency('libdrm_nouveau', version : '>= 2.4.66')
> +  dep_libdrm_nouveau = dependency('libdrm_nouveau', version : '>= ' + 
> libdrm_nouveau_version)
>  endif
>  if with_gallium_etnaviv
> -  dep_libdrm_etnaviv = dependency('libdrm_etnaviv', version : '>= 2.4.82')
> +  dep_libdrm_etnaviv = dependency('libdrm_etnaviv', version : '>= ' + 
> libdrm_etnaviv_version)
>  endif
>  if with_gallium_freedreno
> -  dep_libdrm_freedreno = dependency('libdrm_freedreno', version : '>= 
> 2.4.89')
> +  dep_libdrm_freedreno = dependency('libdrm_freedreno', version : '>= ' + 
> libdrm_freedreno_version)
>  endif
>  
>  llvm_modules = ['bitwriter', 'engine', 'mcdisassembler', 'mcjit']
> @@ -1203,7 +1217,7 @@ gl_priv_reqs = [
>'x11', 'xext', 'xdamage >= 1.1', 'xfixes', 'x11-xcb', 'xcb',
>'xcb-glx >= 1.8.1']
>  if dep_libdrm.found()
> -  gl_priv_reqs += 'libdrm >= 2.4.75'
> +  gl_priv_reqs += 'libdrm >= ' + libdrm_version
>  endif
>  if dep_xxf86vm != [] and dep_xxf86vm.found()
>gl_priv_reqs += 'xxf86vm'
> diff --git a/src/gallium/targets/d3dadapter9/meson.build 
> b/src/gallium/targets/d3dadapter9/meson.build
> index 5476e80e70cf9e2dba5a..498737d1edbf39b3bea2 100644
> --- a/src/gallium/targets/d3dadapter9/meson.build
> +++ b/src/gallium/targets/d3dadapter9/meson.build
> @@ -78,5 +78,5 @@ pkg.generate(
>name : 'd3d',
>description : 'Native D3D driver modules',
>version : '.'.join(nine_version),
> -  requires_private : 'libdrm >= 2.4.75',
> +  requires_private : 'libdrm >= ' + libdrm_version,
>  )
> diff --git a/src/mesa/drivers/dri/meson.build 
> b/src/mesa/drivers/dri/meson.build
> index 87021fba885ab148988d..2a2757577828598489c9 100644
> --- a/src/mesa/drivers/dri/meson.build
> +++ b/src/mesa/drivers/dri/meson.build
> @@ -69,7 +69,7 @@ endif
>  if with_dri
>dri_req_private = []
>if dep_libdrm.found()
> -dri_req_private = ['libdrm >= 2.4.75']  # FIXME: don't hardcode this
> +dri_req_private += 'libdrm >= ' + libdrm_version
>endif
>  
>pkg.generate(
> -- 
> Cheers,
>   Eric
> 

I'm not going to say no because Emil 

Re: [Mesa-dev] [PATCH 4/4] vbo: change an argument in vbo_draw_indirect_prims()

[Marek Olšák]

With the comments on patch 3 addressed, the series is:

Reviewed-by: Marek Olšák 

Marek

On Thu, Feb 1, 2018 at 4:39 AM, Brian Paul  wrote:
> In vbo_draw_indirect_prims() pass the 'indirect_data' argument to
> vbo->draw_prims().  All the callers are passing ctx->DrawIndirectBuffer
> so this should be no functional change.  Add a (temporary) assertion to
> be sure.
> ---
>  src/mesa/vbo/vbo_context.c | 17 -
>  1 file changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/src/mesa/vbo/vbo_context.c b/src/mesa/vbo/vbo_context.c
> index fe1d0f5..5bc6bf0 100644
> --- a/src/mesa/vbo/vbo_context.c
> +++ b/src/mesa/vbo/vbo_context.c
> @@ -140,15 +140,19 @@ init_mat_currval(struct gl_context *ctx)
> }
>  }
>
> +
> +/**
> + * Fallback for when a driver does not call vbo_set_indirect_draw_func().
> + */
>  static void
>  vbo_draw_indirect_prims(struct gl_context *ctx,
>  GLuint mode,
> -struct gl_buffer_object *indirect_data,
> +struct gl_buffer_object *indirect_buffer,
>  GLsizeiptr indirect_offset,
>  unsigned draw_count,
>  unsigned stride,
> -struct gl_buffer_object *indirect_params,
> -GLsizeiptr indirect_params_offset,
> +struct gl_buffer_object *indirect_draw_count_buffer,
> +GLsizeiptr indirect_draw_count_offset,
>  const struct _mesa_index_buffer *ib)
>  {
> struct vbo_context *vbo = vbo_context(ctx);
> @@ -160,7 +164,7 @@ vbo_draw_indirect_prims(struct gl_context *ctx,
>_mesa_error(ctx, GL_OUT_OF_MEMORY, "gl%sDraw%sIndirect%s",
>(draw_count > 1) ? "Multi" : "",
>ib ? "Elements" : "Arrays",
> -  indirect_params ? "CountARB" : "");
> +  indirect_buffer ? "CountARB" : "");
>return;
> }
>
> @@ -174,10 +178,13 @@ vbo_draw_indirect_prims(struct gl_context *ctx,
>prim[i].draw_id = i;
> }
>
> +   /* This should always be true at this time */
> +   assert(indirect_buffer == ctx->DrawIndirectBuffer);
> +
> vbo->draw_prims(ctx, prim, draw_count,
> ib, false, 0, ~0,
> NULL, 0,
> -   ctx->DrawIndirectBuffer);
> +   indirect_buffer);
>
> free(prim);
>  }
> --
> 2.7.4
>
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[Mesa-dev] [PATCH 2/2] meson/swr: Updated copyright dates

[George Kyriazis]

cc: mesa-sta...@lists.freedesktop.org
cc: dy...@pnwbakers.com
---
 src/gallium/drivers/swr/meson.build  | 2 +-
 src/gallium/drivers/swr/rasterizer/codegen/meson.build   | 2 +-
 src/gallium/drivers/swr/rasterizer/core/backends/meson.build | 2 +-
 src/gallium/drivers/swr/rasterizer/jitter/meson.build| 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/swr/meson.build 
b/src/gallium/drivers/swr/meson.build
index c61fd73..12a32628 100644
--- a/src/gallium/drivers/swr/meson.build
+++ b/src/gallium/drivers/swr/meson.build
@@ -1,4 +1,4 @@
-# Copyright © 2017 Intel Corporation
+# Copyright © 2017-2018 Intel Corporation
 
 # Permission is hereby granted, free of charge, to any person obtaining a copy
 # of this software and associated documentation files (the "Software"), to deal
diff --git a/src/gallium/drivers/swr/rasterizer/codegen/meson.build 
b/src/gallium/drivers/swr/rasterizer/codegen/meson.build
index 2cef0d3..a6e127b 100644
--- a/src/gallium/drivers/swr/rasterizer/codegen/meson.build
+++ b/src/gallium/drivers/swr/rasterizer/codegen/meson.build
@@ -1,4 +1,4 @@
-# Copyright © 2017 Intel Corporation
+# Copyright © 2017-2018 Intel Corporation
 
 # Permission is hereby granted, free of charge, to any person obtaining a copy
 # of this software and associated documentation files (the "Software"), to deal
diff --git a/src/gallium/drivers/swr/rasterizer/core/backends/meson.build 
b/src/gallium/drivers/swr/rasterizer/core/backends/meson.build
index 0576212..4b06b28 100644
--- a/src/gallium/drivers/swr/rasterizer/core/backends/meson.build
+++ b/src/gallium/drivers/swr/rasterizer/core/backends/meson.build
@@ -1,4 +1,4 @@
-#jitter/ Copyright © 2017 Intel Corporation
+# Copyright © 2017-2018 Intel Corporation
 
 # Permission is hereby granted, free of charge, to any person obtaining a copy
 # of this software and associated documentation files (the "Software"), to deal
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/meson.build 
b/src/gallium/drivers/swr/rasterizer/jitter/meson.build
index 4930007..e7c9450 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/meson.build
+++ b/src/gallium/drivers/swr/rasterizer/jitter/meson.build
@@ -1,4 +1,4 @@
-# Copyright © 2017 Intel Corporation
+# Copyright © 2017-2018 Intel Corporation
 
 # Permission is hereby granted, free of charge, to any person obtaining a copy
 # of this software and associated documentation files (the "Software"), to deal
-- 
2.7.4

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[Mesa-dev] [PATCH 1/2] meson/swr: re-shuffle generated files

[George Kyriazis]

Move generated files from codegen/meson.build to other directories, in order
to satisfy generated include file dependencies

Add correct file lists for architecture-specific libraries.

cc: mesa-sta...@lists.freedesktop.org
cc: dy...@pnwbakers.com
---
 src/gallium/drivers/swr/meson.build| 10 +--
 .../drivers/swr/rasterizer/codegen/meson.build | 76 --
 .../swr/rasterizer/core/backends/meson.build   | 63 ++
 .../drivers/swr/rasterizer/jitter/meson.build  | 56 
 4 files changed, 125 insertions(+), 80 deletions(-)
 create mode 100644 src/gallium/drivers/swr/rasterizer/core/backends/meson.build
 create mode 100644 src/gallium/drivers/swr/rasterizer/jitter/meson.build

diff --git a/src/gallium/drivers/swr/meson.build 
b/src/gallium/drivers/swr/meson.build
index ae86c8e..c61fd73 100644
--- a/src/gallium/drivers/swr/meson.build
+++ b/src/gallium/drivers/swr/meson.build
@@ -151,7 +151,9 @@ files_swr_arch = files(
 swr_context_files = files('swr_context.h')
 swr_state_files = files('rasterizer/core/state.h')
 swr_event_proto_files = files('rasterizer/archrast/events.proto')
+subdir('rasterizer/jitter')
 subdir('rasterizer/codegen')
+subdir('rasterizer/core/backends')
 
 swr_incs = include_directories(
   'rasterizer/codegen', 'rasterizer/core', 'rasterizer/jitter',
@@ -180,7 +182,7 @@ if with_swr_arches.contains('avx')
   swr_arch_defines += '-DHAVE_SWR_AVX'
   swr_arch_libs += shared_library(
 'swrAVX',
-files_swr_common,
+[files_swr_common, files_swr_arch],
 cpp_args : [swr_cpp_args, swr_avx_args, '-DKNOB_ARCH=KNOB_ARCH_AVX'],
 link_args : [ld_args_gc_sections],
 include_directories : [swr_incs],
@@ -212,7 +214,7 @@ if with_swr_arches.contains('avx2')
   swr_arch_defines += '-DHAVE_SWR_AVX2'
   swr_arch_libs += shared_library(
 'swrAVX2',
-files_swr_common,
+[files_swr_common, files_swr_arch],
 cpp_args : [swr_cpp_args, swr_avx2_args, '-DKNOB_ARCH=KNOB_ARCH_AVX2'],
 link_args : [ld_args_gc_sections],
 include_directories : [swr_incs],
@@ -236,7 +238,7 @@ if with_swr_arches.contains('knl')
   swr_arch_defines += '-DHAVE_SWR_KNL'
   swr_arch_libs += shared_library(
 'swrKNL',
-files_swr_common,
+[files_swr_common, files_swr_arch],
 cpp_args : [
   swr_cpp_args, swr_knl_args, '-DKNOB_ARCH=KNOB_ARCH_AVX512',
   '-DKNOB_ARCH_KNIGHTS',
@@ -263,7 +265,7 @@ if with_swr_arches.contains('skx')
   swr_arch_defines += '-DHAVE_SWR_SKX'
   swr_arch_libs += shared_library(
 'swrSKX',
-files_swr_common,
+[files_swr_common, files_swr_arch],
 cpp_args : [swr_cpp_args, swr_skx_args, '-DKNOB_ARCH=KNOB_ARCH_AVX512'],
 link_args : [ld_args_gc_sections],
 include_directories : [swr_incs],
diff --git a/src/gallium/drivers/swr/rasterizer/codegen/meson.build 
b/src/gallium/drivers/swr/rasterizer/codegen/meson.build
index a21f405..2cef0d3 100644
--- a/src/gallium/drivers/swr/rasterizer/codegen/meson.build
+++ b/src/gallium/drivers/swr/rasterizer/codegen/meson.build
@@ -40,40 +40,6 @@ gen_knobs_h = custom_target(
   ),
 )
 
-gen_builder_hpp = custom_target(
-  'gen_builder.hpp',
-  input : [
-'gen_llvm_ir_macros.py',
-join_paths(
-  dep_llvm.get_configtool_variable('includedir'), 'llvm', 'IR',
-  'IRBuilder.h'
-)
-  ],
-  output : 'gen_builder.hpp',
-  command : [
-prog_python2, '@INPUT0@', '--input', '@INPUT1@', '--output', '@OUTPUT@',
-'--gen_h', '--output-dir', meson.current_build_dir()
-  ],
-  depend_files : files(
-'templates/gen_builder.hpp',
-'gen_common.py',
-  ),
-  build_by_default : true,
-)
-
-gen_builder_x86_hpp = custom_target(
-  'gen_builder_x86.hpp',
-  input : 'gen_llvm_ir_macros.py',
-  output : 'gen_builder_x86.hpp',
-  command : [
-prog_python2, '@INPUT0@', '--gen_x86_h', '--output', '@OUTPUT@',
-'--output-dir', meson.current_build_dir()
-  ],
-  depend_files : files(
-'templates/gen_builder.hpp',
-'gen_common.py',
-  ),
-)
 
 # The generators above this are needed individually, while the below generators
 # are all inputs to the same lib, so they don't need unique names.
@@ -114,45 +80,3 @@ foreach x : [['gen_ar_event.hpp', '--gen_event_hpp'],
   )
 endforeach
 
-files_swr_common += custom_target(
-  'gen_backend_pixel',
-  input : 'gen_backends.py',
-  output : [
-'gen_BackendPixelRate0.cpp', 'gen_BackendPixelRate1.cpp',
-'gen_BackendPixelRate2.cpp', 'gen_BackendPixelRate3.cpp',
-'gen_BackendPixelRate.hpp',
-  ],
-  command : [
-prog_python2, '@INPUT@',
-'--outdir', meson.current_build_dir(),
-'--dim', '5', '2', '3', '2', '2', '2',
-'--numfiles', '4',
-'--cpp', '--hpp',
-  ],
-  depend_files : files(
-'templates/gen_backend.cpp',
-'templates/gen_header_init.hpp',
-  ),
-)
-
-files_swr_common += custom_target(
-  'gen_backend_raster',
-  input : 'gen_backends.py',
-  output : [
-'gen_rasterizer0.cpp', 'gen_rasterizer1.cpp',
-'gen_rasterizer2.cpp', 

[Mesa-dev] [Bug 104908] Texture Compression Hint not converted to enum16

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104908

Bug ID: 104908
   Summary: Texture Compression Hint not converted to enum16
   Product: Mesa
   Version: git
  Hardware: All
OS: All
Status: NEW
  Severity: minor
  Priority: medium
 Component: Mesa core
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: bald...@baldurk.org
QA Contact: mesa-dev@lists.freedesktop.org

In commit f96a69f916a "mesa: replace GLenum with GLenum16 in common structures
(v4)" it looks like Hints.TextureCompression was missed, it's still listed as
an int which leads to 0x11001100 being returned instead of 0x1100 as it reads
into the next value.

This diff fixes it for me, but there might be something else that needs to
update:

diff --git a/src/mesa/main/get_hash_params.py
b/src/mesa/main/get_hash_params.py
index e10282a156..df082af207 100644
--- a/src/mesa/main/get_hash_params.py
+++ b/src/mesa/main/get_hash_params.py
@@ -783,7 +783,7 @@ descriptor=[
   [ "EDGE_FLAG_ARRAY_COUNT_EXT", "CONST(0), NO_EXTRA" ],

 # GL_ARB_texture_compression
-  [ "TEXTURE_COMPRESSION_HINT_ARB", "CONTEXT_INT(Hint.TextureCompression),
NO_EXTRA" ],
+  [ "TEXTURE_COMPRESSION_HINT_ARB", "CONTEXT_ENUM16(Hint.TextureCompression),
NO_EXTRA" ],

 # GL_EXT_compiled_vertex_array
   [ "ARRAY_ELEMENT_LOCK_FIRST_EXT", "CONTEXT_INT(Array.LockFirst), NO_EXTRA"
],

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Re: [Mesa-dev] [PATCH] glsl/lower_64bit: restrict int64 conversion to int64 instructions.

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Thu, Feb 1, 2018 at 4:57 AM, Dave Airlie  wrote:
> From: Dave Airlie 
>
> If the lowering flags for int64 were set we'd try and lower
> the wrong things sometimes.
>
> Signed-off-by: Dave Airlie 
> ---
>  src/compiler/glsl/lower_64bit.cpp | 12 
>  1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/src/compiler/glsl/lower_64bit.cpp 
> b/src/compiler/glsl/lower_64bit.cpp
> index a9b2b98f83..aac5c5a1c7 100644
> --- a/src/compiler/glsl/lower_64bit.cpp
> +++ b/src/compiler/glsl/lower_64bit.cpp
> @@ -390,7 +390,9 @@ lower_64bit_visitor::handle_rvalue(ir_rvalue **rvalue)
> switch (ir->operation) {
> case ir_unop_sign:
>if (lowering(SIGN64)) {
> - *rvalue = handle_op(ir, "__builtin_sign64", generate_ir::sign64);
> +   if (ir->type->base_type == GLSL_TYPE_UINT64 ||
> +   ir->type->base_type == GLSL_TYPE_INT64)
> +   *rvalue = handle_op(ir, "__builtin_sign64", generate_ir::sign64);
>}
>break;
>
> @@ -398,7 +400,7 @@ lower_64bit_visitor::handle_rvalue(ir_rvalue **rvalue)
>if (lowering(DIV64)) {
>   if (ir->type->base_type == GLSL_TYPE_UINT64) {
>  *rvalue = handle_op(ir, "__builtin_udiv64", generate_ir::udiv64);
> - } else {
> + } else if (ir->type->base_type == GLSL_TYPE_INT64) {
>  *rvalue = handle_op(ir, "__builtin_idiv64", generate_ir::idiv64);
>   }
>}
> @@ -408,7 +410,7 @@ lower_64bit_visitor::handle_rvalue(ir_rvalue **rvalue)
>if (lowering(MOD64)) {
>   if (ir->type->base_type == GLSL_TYPE_UINT64) {
>  *rvalue = handle_op(ir, "__builtin_umod64", generate_ir::umod64);
> - } else {
> + } else if (ir->type->base_type == GLSL_TYPE_INT64) {
>  *rvalue = handle_op(ir, "__builtin_imod64", generate_ir::imod64);
>   }
>}
> @@ -416,7 +418,9 @@ lower_64bit_visitor::handle_rvalue(ir_rvalue **rvalue)
>
> case ir_binop_mul:
>if (lowering(MUL64)) {
> - *rvalue = handle_op(ir, "__builtin_umul64", generate_ir::umul64);
> + if (ir->type->base_type == GLSL_TYPE_UINT64 ||
> + ir->type->base_type == GLSL_TYPE_INT64)
> +*rvalue = handle_op(ir, "__builtin_umul64", generate_ir::umul64);
>}
>break;
> case ir_unop_i2d:
> --
> 2.14.3
>
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Re: [Mesa-dev] [PATCH 0/8] Partly untangle pos/generic0 aliasing dependencies v2.

[Brian Paul]

On 02/01/2018 12:32 AM, mathias.froehl...@gmx.net wrote:

From: Mathias Fröhlich 

Hi,

Thanks for the review!

This is the starting point to a patch series that I intent to feed.
The aim is to get rid of some VERT_ATTRIB_MAX long loops that currently
happen at about any draw call.

The series tries to separate out one of the depencies of the attribute
aliasing code as a preparation of the above. It uses static const tables
for the aliasing mapping. Also there is some cleanup to make use of
these tables.

v2: Use GLubyte instead of unsigned char
 Remove _ from enum *_MAX values.
 Change comment style.
 Add Comments.
 Put 2 empty lines between functions.
 Change log message.

This series was now rebased to v1 several times during the past weeks.
Nevertheless the original v1 series past the rebases did not regress
piglit quick on radeonsi, i965 and classical swrast. The v2 version
incorporating the reiview comments was not yet run on piglit.
Please review.


Looks good.

Reviewed-by: Brian Paul 

I don't remember, do you need me to push these for you?

-Brian
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Re: [Mesa-dev] [PATCH] ac/nir: replace SI.buffer.load.dword with amdgcn.buffer.load

[Bas Nieuwenhuizen]

I'm surprised it does not do a idxen and swizzling, but with the current
code, this is

Reviewed-by:  Bas Nieuwenhuizen 

On Thu, Feb 1, 2018 at 4:37 PM, Samuel Pitoiset 
wrote:

> The old one generates useless instructions in there, found while
> comparing geometry shaders between RadeonSI and RADV.
>
> This improves all Vulkan demos that use geometry shaders, +4%
> for deferredshadows, +9% for viewportarray, +7% for
> geometryshader on Polaris10.
>
> This seems to also improve DOW3 a little bit (+1%).
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/common/ac_nir_to_llvm.c | 52 --
> ---
>  1 file changed, 20 insertions(+), 32 deletions(-)
>
> diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_
> llvm.c
> index 5c5594956b..f89012bfe9 100644
> --- a/src/amd/common/ac_nir_to_llvm.c
> +++ b/src/amd/common/ac_nir_to_llvm.c
> @@ -3063,7 +3063,6 @@ load_gs_input(struct ac_shader_abi *abi,
>  {
> struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(
> abi);
> LLVMValueRef vtx_offset;
> -   LLVMValueRef args[9];
> unsigned param, vtx_offset_param;
> LLVMValueRef value[4], result;
>
> @@ -3081,20 +3080,16 @@ load_gs_input(struct ac_shader_abi *abi,
>LLVMConstInt(ctx->ac.i32,
> param * 4 + i + const_index, 0), "");
> value[i] = ac_lds_load(>ac, dw_addr);
> } else {
> -   args[0] = ctx->esgs_ring;
> -   args[1] = vtx_offset;
> -   args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i
> + const_index) * 256, false);
> -   args[3] = ctx->ac.i32_0;
> -   args[4] = ctx->ac.i32_1; /* OFFEN */
> -   args[5] = ctx->ac.i32_0; /* IDXEN */
> -   args[6] = ctx->ac.i32_1; /* GLC */
> -   args[7] = ctx->ac.i32_0; /* SLC */
> -   args[8] = ctx->ac.i32_0; /* TFE */
> -
> -   value[i] = ac_build_intrinsic(>ac,
> "llvm.SI.buffer.load.dword.i32.i32",
> - ctx->ac.i32, args, 9,
> -
>  AC_FUNC_ATTR_READONLY |
> - AC_FUNC_ATTR_LEGACY);
> +   LLVMValueRef soffset =
> +   LLVMConstInt(ctx->ac.i32,
> +(param * 4 + i + const_index)
> * 256,
> +false);
> +
> +   value[i] = ac_build_buffer_load(>ac,
> +   ctx->esgs_ring, 1,
> +   ctx->ac.i32_0,
> +   vtx_offset,
> soffset,
> +   0, 1, 0, true,
> false);
> }
> }
> result = ac_build_varying_gather_values(>ac, value,
> num_components, component);
> @@ -7213,16 +7208,9 @@ void ac_compile_nir_shader(LLVMTargetMachineRef tm,
>  static void
>  ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
>  {
> -   LLVMValueRef args[9];
> -   args[0] = ctx->gsvs_ring;
> -   args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id,
> LLVMConstInt(ctx->ac.i32, 4, false), "");
> -   args[3] = ctx->ac.i32_0;
> -   args[4] = ctx->ac.i32_1;  /* OFFEN */
> -   args[5] = ctx->ac.i32_0; /* IDXEN */
> -   args[6] = ctx->ac.i32_1;  /* GLC */
> -   args[7] = ctx->ac.i32_1;  /* SLC */
> -   args[8] = ctx->ac.i32_0; /* TFE */
> -
> +   LLVMValueRef vtx_offset =
> +   LLVMBuildMul(ctx->builder, ctx->abi.vertex_id,
> +LLVMConstInt(ctx->ac.i32, 4, false), "");
> int idx = 0;
>
> for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
> @@ -7240,16 +7228,16 @@ ac_gs_copy_shader_emit(struct nir_to_llvm_context
> *ctx)
> }
>
> for (unsigned j = 0; j < length; j++) {
> -   LLVMValueRef value;
> -   args[2] = LLVMConstInt(ctx->ac.i32,
> +   LLVMValueRef value, soffset;
> +
> +   soffset = LLVMConstInt(ctx->ac.i32,
>(slot * 4 + j) *
>ctx->gs_max_out_vertices *
> 16 * 4, false);
>
> -   value = ac_build_intrinsic(>ac,
> -
> "llvm.SI.buffer.load.dword.i32.i32",
> -  ctx->ac.i32, args, 9,
> -  AC_FUNC_ATTR_READONLY |
> -  AC_FUNC_ATTR_LEGACY);
> +   value = ac_build_buffer_load(>ac,
> 

Re: [Mesa-dev] [PATCH] r600: initial attempt at gl_HelperInvocation (v3)

[Roland Scheidegger]

Am 01.02.2018 um 09:21 schrieb Dave Airlie:
> From: Dave Airlie 
> 
> This passes the CTS and piglit tests.
> 
> This also disable sb for helper invocations until it doesn't
> mess up the VPM flags.
> 
> Thanks to Ilia and Glenn for advice, and Roland for working
> out the working evergreen path.
> ---
>  src/gallium/drivers/r600/r600_asm.c|   7 +-
>  src/gallium/drivers/r600/r600_isa.c|   1 +
>  src/gallium/drivers/r600/r600_isa.h|   5 +-
>  src/gallium/drivers/r600/r600_shader.c | 113 
> +
>  src/gallium/drivers/r600/r600_shader.h |   1 +
>  src/gallium/drivers/r600/r600_sq.h |   2 +
>  6 files changed, 126 insertions(+), 3 deletions(-)
> 
> diff --git a/src/gallium/drivers/r600/r600_asm.c 
> b/src/gallium/drivers/r600/r600_asm.c
> index 21d069d..ec2d34e 100644
> --- a/src/gallium/drivers/r600/r600_asm.c
> +++ b/src/gallium/drivers/r600/r600_asm.c
> @@ -2099,9 +2099,12 @@ void r600_bytecode_disasm(struct r600_bytecode *bc)
>   fprintf(stderr, "%04d %08X %08X  %s ", id, 
> bc->bytecode[id],
>   bc->bytecode[id + 1], 
> cfop->name);
>   fprintf(stderr, "%d @%d ", cf->ndw / 4, 
> cf->addr);
> - fprintf(stderr, "\n");
> + if (cf->vpm)
> + fprintf(stderr, "VPM ");
>   if (cf->end_of_program)
>   fprintf(stderr, "EOP ");
> + fprintf(stderr, "\n");
> +
>   } else if (cfop->flags & CF_EXP) {
>   int o = 0;
>   const char *exp_type[] = {"PIXEL", "POS  ", 
> "PARAM"};
> @@ -2198,6 +2201,8 @@ void r600_bytecode_disasm(struct r600_bytecode *bc)
>   fprintf(stderr, "POP:%X ", 
> cf->pop_count);
>   if (cf->count && (cfop->flags & CF_EMIT))
>   fprintf(stderr, "STREAM%d ", cf->count);
> + if (cf->vpm)
> + fprintf(stderr, "VPM ");
>   if (cf->end_of_program)
>   fprintf(stderr, "EOP ");
>   fprintf(stderr, "\n");
> diff --git a/src/gallium/drivers/r600/r600_isa.c 
> b/src/gallium/drivers/r600/r600_isa.c
> index 2633cdc..611b370 100644
> --- a/src/gallium/drivers/r600/r600_isa.c
> +++ b/src/gallium/drivers/r600/r600_isa.c
> @@ -506,6 +506,7 @@ static const struct cf_op_info cf_op_table[] = {
>   {"ALU_EXT",   {   -1,   -1, 0x0C, 0x0C },  
> CF_CLAUSE | CF_ALU | CF_ALU_EXT  },
>   {"ALU_CONTINUE",  { 0x0D, 0x0D, 0x0D,   -1 },  
> CF_CLAUSE | CF_ALU  },
>   {"ALU_BREAK", { 0x0E, 0x0E, 0x0E,   -1 },  
> CF_CLAUSE | CF_ALU  },
> + {"ALU_VALID_PIXEL_MODE",  {   -1,   -1,   -1, 0x0E },  
> CF_CLAUSE | CF_ALU  },
>   {"ALU_ELSE_AFTER",{ 0x0F, 0x0F, 0x0F, 0x0F },  
> CF_CLAUSE | CF_ALU  },
>   {"CF_NATIVE", { 0x00, 0x00, 0x00, 0x00 },  
> 0  }
>  };
> diff --git a/src/gallium/drivers/r600/r600_isa.h 
> b/src/gallium/drivers/r600/r600_isa.h
> index f6e2697..fcaf1f7 100644
> --- a/src/gallium/drivers/r600/r600_isa.h
> +++ b/src/gallium/drivers/r600/r600_isa.h
> @@ -646,10 +646,11 @@ struct cf_op_info
>  #define CF_OP_ALU_EXT  84
>  #define CF_OP_ALU_CONTINUE 85
>  #define CF_OP_ALU_BREAK86
> -#define CF_OP_ALU_ELSE_AFTER   87
> +#define CF_OP_ALU_VALID_PIXEL_MODE 87
> +#define CF_OP_ALU_ELSE_AFTER   88
>  
>  /* CF_NATIVE means that r600_bytecode_cf contains pre-encoded native data */
> -#define CF_NATIVE  88
> +#define CF_NATIVE  89
>  
>  enum r600_chip_class {
>   ISA_CC_R600,
> diff --git a/src/gallium/drivers/r600/r600_shader.c 
> b/src/gallium/drivers/r600/r600_shader.c
> index a462691..9388db9 100644
> --- a/src/gallium/drivers/r600/r600_shader.c
> +++ b/src/gallium/drivers/r600/r600_shader.c
> @@ -197,6 +197,7 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
>  
>   use_sb &= !shader->shader.uses_atomics;
>   use_sb &= !shader->shader.uses_images;
> + use_sb &= !shader->shader.uses_helper_invocation;
>  
>   /* Check if the bytecode has already been built. */
>   if (!shader->shader.bc.bytecode) {
> @@ -346,6 +347,7 @@ struct r600_shader_ctx {
>   boolean clip_vertex_write;
>   unsignedcv_output;
>   unsignededgeflag_output;
> + int helper_invoc_reg;
>   int cs_block_size_reg;
>  

Re: [Mesa-dev] [PATCH v2] i965: check if upload is 0 explicitely, when downsizing a format

[Kenneth Graunke]

On Thursday, February 1, 2018 7:15:14 AM PST Andres Gomez wrote:
> downsize_format_if_needed takes an integer as number of uploads
> parameter. Hence, let's do an integer comparation instead of a boolean
> check, since that is confusing.
> 
> Since we are at it, fix a couple of wrongly tabbed indents.
> 
> Cc: Alejandro Piñeiro 
> Cc: Kenneth Graunke 
> Signed-off-by: Andres Gomez 
> ---
>  src/mesa/drivers/dri/i965/genX_state_upload.c | 16 
>  1 file changed, 8 insertions(+), 8 deletions(-)

Thanks!

Reviewed-by: Kenneth Graunke 


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[Mesa-dev] X.Org Foundation Membership Renewal

[Rob Clark]

On Feb 1st all xorg members were expired as part of the regular
process to remove inactive members.  If you would still like to be a
member of the X.Org Foundation, please renew your membership.  To
renew or to become a first time member, go to https://members.x.org/ .
For renewals, log in and click the renewal link.  For new members,
click the Join Now link.  The X.org Foundation is a non-profit
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renew or join today!

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Re: [Mesa-dev] [PATCH 3/4] vbo: add comments on the VBO draw function typedefs

[Brian Paul]

On 02/01/2018 03:49 AM, Ilia Mirkin wrote:

On Wed, Jan 31, 2018 at 10:39 PM, Brian Paul  wrote:

And rename indirect_params -> indirect_draw_count_buffer and
indirect_params_offset -> indirect_draw_count_offset to be more
specific.
---
  src/mesa/vbo/vbo.h | 57 --
  1 file changed, 55 insertions(+), 2 deletions(-)

diff --git a/src/mesa/vbo/vbo.h b/src/mesa/vbo/vbo.h
index 164477f..59c6a06 100644
--- a/src/mesa/vbo/vbo.h
+++ b/src/mesa/vbo/vbo.h
@@ -119,6 +119,43 @@ void
  vbo_save_EndCallList(struct gl_context *ctx);


+/**
+ * For indirect array drawing:
+ *
+ *typedef struct {
+ *   GLuint count;
+ *   GLuint primCount;
+ *   GLuint first;
+ *   GLuint reservedMustBeZero;


Actually that's baseInstance both here and below.


In GL 4.2 and later.  I'll add a comment about that.  Thanks.

-Brian




+ *} DrawArraysIndirectCommand;
+ *
+ * For indirect indexed drawing:
+ *
+ *typedef struct {
+ *   GLuint count;
+ *   GLuint primCount;
+ *   GLuint firstIndex;
+ *   GLint  baseVertex;
+ *   GLuint reservedMustBeZero;
+ *} DrawElementsIndirectCommand;
+ */


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Re: [Mesa-dev] [PATCH] meson: don't install windows headers on non-windowsplatforms

[Eric Engestrom]

On Thursday, 2018-02-01 15:29:25 +0100, Marc Dietrich wrote:
> Am Donnerstag, 1. Februar 2018, 15:07:55 CET schrieb Eric Engestrom:
> > On Thursday, 2018-02-01 13:27:28 +0100, Marc Dietrich wrote:
> > > Only dive into the windows subdir if windows platform is selected.
> > > 
> > > Signed-off-by: Marc Dietrich 
> > 
> > Good point, although if I'm reading it right, it only installs a couple
> > unnecessary headers right now; we got lucky :P
> 
> right.
> 
> > 
> > Fixes: 5ef75cb02b2b4db5506b8 "meson: build src/glx/windows"
> > Reviewed-by: Eric Engestrom 
> > 
> > Do you have commit access?
> 
> no, please apply.

4c5f0b4fd45a5ca96a0e pushed :)

> 
> Marc
> 
> > > ---
> > > 
> > >  src/glx/meson.build | 4 +++-
> > >  1 file changed, 3 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/src/glx/meson.build b/src/glx/meson.build
> > > index 04cd647ee4..e645b22b5f 100644
> > > --- a/src/glx/meson.build
> > > +++ b/src/glx/meson.build
> > > @@ -18,7 +18,9 @@
> > > 
> > >  # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> > >  IN THE # SOFTWARE.
> > > 
> > > -subdir('windows')
> > > +if with_dri_platform == 'windows'
> > > +  subdir('windows')
> > > +endif
> > > 
> > >  files_libglx = files(
> > >  
> > >'clientattrib.c',
> 


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[Mesa-dev] [PATCH] ac/nir: replace SI.buffer.load.dword with amdgcn.buffer.load

[Samuel Pitoiset]

The old one generates useless instructions in there, found while
comparing geometry shaders between RadeonSI and RADV.

This improves all Vulkan demos that use geometry shaders, +4%
for deferredshadows, +9% for viewportarray, +7% for
geometryshader on Polaris10.

This seems to also improve DOW3 a little bit (+1%).

Signed-off-by: Samuel Pitoiset 
---
 src/amd/common/ac_nir_to_llvm.c | 52 -
 1 file changed, 20 insertions(+), 32 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 5c5594956b..f89012bfe9 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3063,7 +3063,6 @@ load_gs_input(struct ac_shader_abi *abi,
 {
struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
LLVMValueRef vtx_offset;
-   LLVMValueRef args[9];
unsigned param, vtx_offset_param;
LLVMValueRef value[4], result;
 
@@ -3081,20 +3080,16 @@ load_gs_input(struct ac_shader_abi *abi,
   LLVMConstInt(ctx->ac.i32, param 
* 4 + i + const_index, 0), "");
value[i] = ac_lds_load(>ac, dw_addr);
} else {
-   args[0] = ctx->esgs_ring;
-   args[1] = vtx_offset;
-   args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + 
const_index) * 256, false);
-   args[3] = ctx->ac.i32_0;
-   args[4] = ctx->ac.i32_1; /* OFFEN */
-   args[5] = ctx->ac.i32_0; /* IDXEN */
-   args[6] = ctx->ac.i32_1; /* GLC */
-   args[7] = ctx->ac.i32_0; /* SLC */
-   args[8] = ctx->ac.i32_0; /* TFE */
-
-   value[i] = ac_build_intrinsic(>ac, 
"llvm.SI.buffer.load.dword.i32.i32",
- ctx->ac.i32, args, 9,
- AC_FUNC_ATTR_READONLY |
- AC_FUNC_ATTR_LEGACY);
+   LLVMValueRef soffset =
+   LLVMConstInt(ctx->ac.i32,
+(param * 4 + i + const_index) * 
256,
+false);
+
+   value[i] = ac_build_buffer_load(>ac,
+   ctx->esgs_ring, 1,
+   ctx->ac.i32_0,
+   vtx_offset, soffset,
+   0, 1, 0, true, false);
}
}
result = ac_build_varying_gather_values(>ac, value, 
num_components, component);
@@ -7213,16 +7208,9 @@ void ac_compile_nir_shader(LLVMTargetMachineRef tm,
 static void
 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
 {
-   LLVMValueRef args[9];
-   args[0] = ctx->gsvs_ring;
-   args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, 
LLVMConstInt(ctx->ac.i32, 4, false), "");
-   args[3] = ctx->ac.i32_0;
-   args[4] = ctx->ac.i32_1;  /* OFFEN */
-   args[5] = ctx->ac.i32_0; /* IDXEN */
-   args[6] = ctx->ac.i32_1;  /* GLC */
-   args[7] = ctx->ac.i32_1;  /* SLC */
-   args[8] = ctx->ac.i32_0; /* TFE */
-
+   LLVMValueRef vtx_offset =
+   LLVMBuildMul(ctx->builder, ctx->abi.vertex_id,
+LLVMConstInt(ctx->ac.i32, 4, false), "");
int idx = 0;
 
for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
@@ -7240,16 +7228,16 @@ ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
}
 
for (unsigned j = 0; j < length; j++) {
-   LLVMValueRef value;
-   args[2] = LLVMConstInt(ctx->ac.i32,
+   LLVMValueRef value, soffset;
+
+   soffset = LLVMConstInt(ctx->ac.i32,
   (slot * 4 + j) *
   ctx->gs_max_out_vertices * 16 * 
4, false);
 
-   value = ac_build_intrinsic(>ac,
-  
"llvm.SI.buffer.load.dword.i32.i32",
-  ctx->ac.i32, args, 9,
-  AC_FUNC_ATTR_READONLY |
-  AC_FUNC_ATTR_LEGACY);
+   value = ac_build_buffer_load(>ac, ctx->gsvs_ring,
+1, ctx->ac.i32_0,
+vtx_offset, soffset,
+0, 1, 1, true, false);
 
LLVMBuildStore(ctx->builder,
   ac_to_float(>ac, 

[Mesa-dev] [PATCH v2] i965: check if upload is 0 explicitely, when downsizing a format

[Andres Gomez]

downsize_format_if_needed takes an integer as number of uploads
parameter. Hence, let's do an integer comparation instead of a boolean
check, since that is confusing.

Since we are at it, fix a couple of wrongly tabbed indents.

Cc: Alejandro Piñeiro 
Cc: Kenneth Graunke 
Signed-off-by: Andres Gomez 
---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index a39a254dacd..45636fe69df 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -365,7 +365,7 @@ is_passthru_format(uint32_t format)
 
 UNUSED static int
 uploads_needed(uint32_t format,
-  bool is_dual_slot)
+   bool is_dual_slot)
 {
if (!is_passthru_format(format))
   return 1;
@@ -409,14 +409,14 @@ downsize_format_if_needed(uint32_t format,
 */
switch (format) {
case ISL_FORMAT_R64_PASSTHRU:
-  return !upload ? ISL_FORMAT_R32G32_FLOAT
- : ISL_FORMAT_R32_FLOAT;
+  return upload == 0 ? ISL_FORMAT_R32G32_FLOAT
+ : ISL_FORMAT_R32_FLOAT;
case ISL_FORMAT_R64G64_PASSTHRU:
-  return !upload ? ISL_FORMAT_R32G32B32A32_FLOAT
- : ISL_FORMAT_R32_FLOAT;
+  return upload == 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
+ : ISL_FORMAT_R32_FLOAT;
case ISL_FORMAT_R64G64B64_PASSTHRU:
-  return !upload ? ISL_FORMAT_R32G32B32A32_FLOAT
- : ISL_FORMAT_R32G32_FLOAT;
+  return upload == 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
+ : ISL_FORMAT_R32G32_FLOAT;
case ISL_FORMAT_R64G64B64A64_PASSTHRU:
   return ISL_FORMAT_R32G32B32A32_FLOAT;
default:
@@ -635,7 +635,7 @@ genX(emit_vertices)(struct brw_context *brw)
   uint32_t comp2 = VFCOMP_STORE_SRC;
   uint32_t comp3 = VFCOMP_STORE_SRC;
   const unsigned num_uploads = GEN_GEN < 8 ?
-uploads_needed(format, input->is_dual_slot) : 1;
+ uploads_needed(format, input->is_dual_slot) : 1;
 
 #if GEN_GEN >= 8
   /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
-- 
2.15.1

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[Mesa-dev] [PATCH] i965: check if compare is 0 explicitely, when downsizing a format

[Andres Gomez]

downsize_format_if_needed takes an integer as number of uploads
parameter. Hence, let's do an integer comparation instead of a boolean
check, since that is confusing.

Since we are at it, fix a couple of wrongly tabbed indents.

Cc: Alejandro Piñeiro 
Cc: Kenneth Graunke 
Signed-off-by: Andres Gomez 
---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index a39a254dacd..45636fe69df 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -365,7 +365,7 @@ is_passthru_format(uint32_t format)
 
 UNUSED static int
 uploads_needed(uint32_t format,
-  bool is_dual_slot)
+   bool is_dual_slot)
 {
if (!is_passthru_format(format))
   return 1;
@@ -409,14 +409,14 @@ downsize_format_if_needed(uint32_t format,
 */
switch (format) {
case ISL_FORMAT_R64_PASSTHRU:
-  return !upload ? ISL_FORMAT_R32G32_FLOAT
- : ISL_FORMAT_R32_FLOAT;
+  return upload == 0 ? ISL_FORMAT_R32G32_FLOAT
+ : ISL_FORMAT_R32_FLOAT;
case ISL_FORMAT_R64G64_PASSTHRU:
-  return !upload ? ISL_FORMAT_R32G32B32A32_FLOAT
- : ISL_FORMAT_R32_FLOAT;
+  return upload == 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
+ : ISL_FORMAT_R32_FLOAT;
case ISL_FORMAT_R64G64B64_PASSTHRU:
-  return !upload ? ISL_FORMAT_R32G32B32A32_FLOAT
- : ISL_FORMAT_R32G32_FLOAT;
+  return upload == 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
+ : ISL_FORMAT_R32G32_FLOAT;
case ISL_FORMAT_R64G64B64A64_PASSTHRU:
   return ISL_FORMAT_R32G32B32A32_FLOAT;
default:
@@ -635,7 +635,7 @@ genX(emit_vertices)(struct brw_context *brw)
   uint32_t comp2 = VFCOMP_STORE_SRC;
   uint32_t comp3 = VFCOMP_STORE_SRC;
   const unsigned num_uploads = GEN_GEN < 8 ?
-uploads_needed(format, input->is_dual_slot) : 1;
+ uploads_needed(format, input->is_dual_slot) : 1;
 
 #if GEN_GEN >= 8
   /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
-- 
2.15.1

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[Mesa-dev] [Bug 104905] SpvOpFOrdEqual doesn't return correct results for NaNs

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104905

Bug ID: 104905
   Summary: SpvOpFOrdEqual doesn't return correct results for NaNs
   Product: Mesa
   Version: git
  Hardware: All
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Vulkan/radeon
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: joseph.ku...@gmail.com
QA Contact: mesa-dev@lists.freedesktop.org

SpvOpFOrdEqual doesn't seem to perform ordered comparison, e.g. NaN and 1.0
gives true. I expect this to also be a problem for other ordered comparison
SPIR-V opcodes.

Mesa SPIR-V to NIR translator inserts additional nir_feq instructions in order
to detect NaNs, but those instructions are probably optimized out by LLVM.

The problem can be reproduced by running VKD3D tests:
https://source.winehq.org/git/vkd3d.git/blob/HEAD:/tests/d3d12.c#l6640

I can write a standalone test case, if needed.

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Re: [Mesa-dev] [PATCH] mesa: remove usage of alloca in externalobjects.c v3

[Andres Rodriguez]

On 2018-02-01 08:24 AM, Emil Velikov wrote:

On 31 January 2018 at 19:03, Andres Rodriguez  wrote:

Don't want an overly large numBufferBarriers/numTextureBarriers to blow
up the stack.

v2: handle malloc errors
v3: fix patch

Suggested-by: Emil Velikov 
Signed-off-by: Andres Rodriguez 
---
  src/mesa/main/externalobjects.c | 48 +++--
  1 file changed, 42 insertions(+), 6 deletions(-)

diff --git a/src/mesa/main/externalobjects.c b/src/mesa/main/externalobjects.c
index 463debd268..a28d6dba6f 100644
--- a/src/mesa/main/externalobjects.c
+++ b/src/mesa/main/externalobjects.c
@@ -713,91 +713,127 @@ _mesa_WaitSemaphoreEXT(GLuint semaphore,
 const GLuint *buffers,
 GLuint numTextureBarriers,
 const GLuint *textures,
 const GLenum *srcLayouts)
  {
 GET_CURRENT_CONTEXT(ctx);
 struct gl_semaphore_object *semObj;
 struct gl_buffer_object **bufObjs;
 struct gl_texture_object **texObjs;

Initialize texObjs (might as well do bufObjs) since on bufObjs
allocation failure we'll end up feeding junk to free().


-   bufObjs = alloca(sizeof(struct gl_buffer_object **) * numBufferBarriers);
+   bufObjs = malloc(sizeof(struct gl_buffer_object **) * numBufferBarriers);
+   if (!bufObjs) {
+  _mesa_error(ctx, GL_OUT_OF_MEMORY, "%s(numBufferBarriers=%u)",
+  func, numBufferBarriers);
+  goto end;
+   }
+



+end:
+   free(bufObjs);
+   free(texObjs);
  }

  void GLAPIENTRY
  _mesa_SignalSemaphoreEXT(GLuint semaphore,
   GLuint numBufferBarriers,
   const GLuint *buffers,
   GLuint numTextureBarriers,
   const GLuint *textures,
   const GLenum *dstLayouts)
  {
 GET_CURRENT_CONTEXT(ctx);
 struct gl_semaphore_object *semObj;
 struct gl_buffer_object **bufObjs;
 struct gl_texture_object **texObjs;


Ditto.

With the above nitpicks, patch is
Reviewed-by: Emil Velikov 


Those aren't nits, those are very real bugs. And I should've double 
checked the patch better before sending it out!


Thanks for the reviews, fixed with your feedback and pushed.

Regards,
Andres



-Emil


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Re: [Mesa-dev] [PATCH] meson: don't install windows headers on non-windowsplatforms

[Marc Dietrich]

Am Donnerstag, 1. Februar 2018, 15:07:55 CET schrieb Eric Engestrom:
> On Thursday, 2018-02-01 13:27:28 +0100, Marc Dietrich wrote:
> > Only dive into the windows subdir if windows platform is selected.
> > 
> > Signed-off-by: Marc Dietrich 
> 
> Good point, although if I'm reading it right, it only installs a couple
> unnecessary headers right now; we got lucky :P

right.

> 
> Fixes: 5ef75cb02b2b4db5506b8 "meson: build src/glx/windows"
> Reviewed-by: Eric Engestrom 
> 
> Do you have commit access?

no, please apply.

Marc

> > ---
> > 
> >  src/glx/meson.build | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> > 
> > diff --git a/src/glx/meson.build b/src/glx/meson.build
> > index 04cd647ee4..e645b22b5f 100644
> > --- a/src/glx/meson.build
> > +++ b/src/glx/meson.build
> > @@ -18,7 +18,9 @@
> > 
> >  # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> >  IN THE # SOFTWARE.
> > 
> > -subdir('windows')
> > +if with_dri_platform == 'windows'
> > +  subdir('windows')
> > +endif
> > 
> >  files_libglx = files(
> >  
> >'clientattrib.c',



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Re: [Mesa-dev] [PATCH 4/4] svga: remove unneeded #includes in svga_pipe_draw.c

[Neha Bhende]

For the series,

Reviewed-by: Neha Bhende

From: Brian Paul 
Sent: Wednesday, January 31, 2018 7:37:23 PM
To: mesa-dev@lists.freedesktop.org
Cc: Charmaine Lee; Neha Bhende
Subject: [PATCH 4/4] svga: remove unneeded #includes in svga_pipe_draw.c

---
 src/gallium/drivers/svga/svga_pipe_draw.c | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_pipe_draw.c 
b/src/gallium/drivers/svga/svga_pipe_draw.c
index 8cd7ab0..ee4a105 100644
--- a/src/gallium/drivers/svga/svga_pipe_draw.c
+++ b/src/gallium/drivers/svga/svga_pipe_draw.c
@@ -24,21 +24,14 @@
  **/


-#include "util/u_format.h"
 #include "util/u_helpers.h"
 #include "util/u_inlines.h"
 #include "util/u_prim.h"
 #include "util/u_prim_restart.h"
-#include "util/u_upload_mgr.h"
-#include "indices/u_indices.h"

-#include "svga_hw_reg.h"
-#include "svga_cmd.h"
 #include "svga_context.h"
-#include "svga_screen.h"
 #include "svga_draw.h"
 #include "svga_shader.h"
-#include "svga_state.h"
 #include "svga_surface.h"
 #include "svga_swtnl.h"
 #include "svga_debug.h"
--
2.7.4

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Re: [Mesa-dev] [PATCH] meson: don't install windows headers on non-windows platforms

[Eric Engestrom]

On Thursday, 2018-02-01 13:27:28 +0100, Marc Dietrich wrote:
> Only dive into the windows subdir if windows platform is selected.
> 
> Signed-off-by: Marc Dietrich 

Good point, although if I'm reading it right, it only installs a couple
unnecessary headers right now; we got lucky :P

Fixes: 5ef75cb02b2b4db5506b8 "meson: build src/glx/windows"
Reviewed-by: Eric Engestrom 

Do you have commit access?

> ---
>  src/glx/meson.build | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/src/glx/meson.build b/src/glx/meson.build
> index 04cd647ee4..e645b22b5f 100644
> --- a/src/glx/meson.build
> +++ b/src/glx/meson.build
> @@ -18,7 +18,9 @@
>  # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 
> THE
>  # SOFTWARE.
>  
> -subdir('windows')
> +if with_dri_platform == 'windows'
> +  subdir('windows')
> +endif
>  
>  files_libglx = files(
>'clientattrib.c',
> -- 
> 2.16.1
> 
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Re: [Mesa-dev] misc pahole repacking

[Emil Velikov]

On 1 February 2018 at 11:13, Adrian M Negreanu  wrote:
> There's a bug about quiting on unsupported tags:
> https://bugzilla.redhat.com/show_bug.cgi?id=1348200
>
> Should be fixed in v1.10
> http://pkgs.fedoraproject.org/cgit/rpms/dwarves.git/commit/?h=f25
>
Seems like distros should update their package and upstream URLs [1].
pahole v1.11 has been out for 7 months ;-)

Alternatively one can build/install it locally - it requires
libelf/libdwarf and zlib.

-Emil

[1] https://git.kernel.org/pub/scm/devel/pahole/pahole.git
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[Mesa-dev] [Bug 104732] [radv] Binding descriptor sets disturbs other pipeline bindings

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104732

Józef Kucia  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

--- Comment #2 from Józef Kucia  ---
It seems to work fine. Thanks!

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Re: [Mesa-dev] [PATCH] mesa: remove usage of alloca in externalobjects.c v3

[Emil Velikov]

On 31 January 2018 at 19:03, Andres Rodriguez  wrote:
> Don't want an overly large numBufferBarriers/numTextureBarriers to blow
> up the stack.
>
> v2: handle malloc errors
> v3: fix patch
>
> Suggested-by: Emil Velikov 
> Signed-off-by: Andres Rodriguez 
> ---
>  src/mesa/main/externalobjects.c | 48 
> +++--
>  1 file changed, 42 insertions(+), 6 deletions(-)
>
> diff --git a/src/mesa/main/externalobjects.c b/src/mesa/main/externalobjects.c
> index 463debd268..a28d6dba6f 100644
> --- a/src/mesa/main/externalobjects.c
> +++ b/src/mesa/main/externalobjects.c
> @@ -713,91 +713,127 @@ _mesa_WaitSemaphoreEXT(GLuint semaphore,
> const GLuint *buffers,
> GLuint numTextureBarriers,
> const GLuint *textures,
> const GLenum *srcLayouts)
>  {
> GET_CURRENT_CONTEXT(ctx);
> struct gl_semaphore_object *semObj;
> struct gl_buffer_object **bufObjs;
> struct gl_texture_object **texObjs;
Initialize texObjs (might as well do bufObjs) since on bufObjs
allocation failure we'll end up feeding junk to free().

> -   bufObjs = alloca(sizeof(struct gl_buffer_object **) * numBufferBarriers);
> +   bufObjs = malloc(sizeof(struct gl_buffer_object **) * numBufferBarriers);
> +   if (!bufObjs) {
> +  _mesa_error(ctx, GL_OUT_OF_MEMORY, "%s(numBufferBarriers=%u)",
> +  func, numBufferBarriers);
> +  goto end;
> +   }
> +

> +end:
> +   free(bufObjs);
> +   free(texObjs);
>  }
>
>  void GLAPIENTRY
>  _mesa_SignalSemaphoreEXT(GLuint semaphore,
>   GLuint numBufferBarriers,
>   const GLuint *buffers,
>   GLuint numTextureBarriers,
>   const GLuint *textures,
>   const GLenum *dstLayouts)
>  {
> GET_CURRENT_CONTEXT(ctx);
> struct gl_semaphore_object *semObj;
> struct gl_buffer_object **bufObjs;
> struct gl_texture_object **texObjs;
>
Ditto.

With the above nitpicks, patch is
Reviewed-by: Emil Velikov 

-Emil
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Re: [Mesa-dev] [PATCH 6/6] travis: add macOS meson build

[Emil Velikov]

On 28 January 2018 at 14:24, Jon Turney  wrote:
> ---
>  .travis.yml | 5 +
>  1 file changed, 5 insertions(+)
>
> diff --git a/.travis.yml b/.travis.yml
> index 9cecf2f615f..7e6bbfe306b 100644
> --- a/.travis.yml
> +++ b/.travis.yml
> @@ -403,6 +403,11 @@ matrix:
>  - MAKE_CHECK_COMMAND="make check"
>  - DRI_LOADERS="--with-platforms=x11 --disable-egl"
>os: osx
> +- env:
> +- LABEL="macOS meson"
> +- BUILD=meson
> +- MESON_OPTIONS="-Ddri-drivers=swrast -Dgallium-drivers= 
> -Dvulkan-drivers= -Dplatforms=x11,surfaceless -Dglx=dri -Degl=false"
Can we please have the same [explicit] set of toggles for both
automake and meson?
You can drop the surfaceless platform - there's no way to use it w/o
EGL. Speaking of which, did we merge all the patches for it on
Cygwin/OSX?

With surfaceless dropped, patches 1-4 and 6 are
Reviewed-by: Emil Velikov 

Thanks!
Emil
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Re: [Mesa-dev] [PATCH 0/6] Fix osx build and add to CI

[Emil Velikov]

Hats off for sorting these out Jon!

On 28 January 2018 at 14:18, Jon Turney  wrote:
> Jon Turney (6):
>   configure: Default to gbm=no on osx
>   osx: ld doesn't support --build-id
>   glx/apple: include util/debug.h for env_var_as_boolean prototype
>   glx/apple: locate dispatch table functions to wrap by name
Very nice. There's more cleanups/consolidation that could be done, but
that for another day.

>   glx/test: fix building for osx
Seems to be missing from the ML and Patchwork

>   travis: add osx autotools build
>
Please split the linux and pip->pip2 changes to separate patches.

1-4 and 6 (latter with the trivial split) are
Reviewed-by: Emil Velikov 

-Emil
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[Mesa-dev] [PATCH] meson: don't install windows headers on non-windows platforms

[Marc Dietrich]

Only dive into the windows subdir if windows platform is selected.

Signed-off-by: Marc Dietrich 
---
 src/glx/meson.build | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/glx/meson.build b/src/glx/meson.build
index 04cd647ee4..e645b22b5f 100644
--- a/src/glx/meson.build
+++ b/src/glx/meson.build
@@ -18,7 +18,9 @@
 # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 # SOFTWARE.
 
-subdir('windows')
+if with_dri_platform == 'windows'
+  subdir('windows')
+endif
 
 files_libglx = files(
   'clientattrib.c',
-- 
2.16.1

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Re: [Mesa-dev] [PATCH 1/6] meson: find python2 on macOS

[Emil Velikov]

On 28 January 2018 at 14:24, Jon Turney  wrote:
> From: Dylan Baker 
>
> ---
>  meson.build | 8 +++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/meson.build b/meson.build
> index 824e3c46bc5..178743eddb1 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -642,7 +642,13 @@ if with_platform_android
>pre_args += '-DHAVE_ANDROID_PLATFORM'
>  endif
>
> -prog_python2 = find_program('python2')
> +# Basically we can't trust Linux because one distro had decided that python
> +# should be python3. macOS doesn't have a python2 binary, however.
> +if build_machine.system() != 'darwin'
> +  prog_python2 = find_program('python2')
> +else
> +  prog_python2 = find_program('python')
> +endif

I think this is better suited in meson, thus everyone doesn't need to
reinvent the wheel.
Even if we're moving towards python2-free world ;-)

Until then, the patch looks reasonable.
Reviewed-by: Emil Velikov 

-Emil
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Re: [Mesa-dev] [PATCH v2] mesa: enable ASTC/ETC1 compressed 3D textures

[Juan A. Suarez Romero]

On Mon, 2018-01-29 at 16:25 -0800, Eric Anholt wrote:
> "Juan A. Suarez Romero"  writes:
> 
> > Enable these kind of 3D texture when proper extensions are available.
> > 
> > Fixes KHR-GLES2.texture_3d.* with these textures.
> > 
> > v2: add better clarification (Eric)
> > ---
> >  src/mesa/main/teximage.c | 31 ---
> >  1 file changed, 24 insertions(+), 7 deletions(-)
> > 
> > diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
> > index e5f8bb0718f..56235898c66 100644
> > --- a/src/mesa/main/teximage.c
> > +++ b/src/mesa/main/teximage.c
> > @@ -1487,6 +1487,9 @@ _mesa_target_can_be_compressed(const struct 
> > gl_context *ctx, GLenum target,
> >break;
> > case GL_TEXTURE_3D:
> >switch (layout) {
> > +  case MESA_FORMAT_LAYOUT_ETC1:
> > + target_can_be_compresed = 
> > ctx->Extensions.OES_compressed_ETC1_RGB8_texture;
> > + break;
> >case MESA_FORMAT_LAYOUT_ETC2:
> >   /* See ETC2/EAC comment in case GL_TEXTURE_CUBE_MAP_ARRAY. */
> 
> OK, I took a look at the ETC2/EAC comment above, this time, and it looks
> like 3D textures are supposed to be not supported with ETC2 or ASTC
> according to table 8.17 in GLES 3.2.
> 
> This is looking more like a testcase bug to me.


Yes, you're right. This is similar to another patch I sent for review
and that turned out it was wrong for the same reason (both patches are
related with the same test).

So I withdraw this patch, and I'll send a fix for the testcase instead.

Thanks.


J.A.

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Re: [Mesa-dev] [PATCH] i965: Call prepare_external after implicit window-system MSAA resolves

[Tapani Pälli]

This fixes the issue;
Tested-by: Tapani Pälli 

On 02/01/2018 03:41 AM, Jason Ekstrand wrote:

This fixes some rendering corruption in a couple of Android apps that
use window-system MSAA.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104741
Cc: mesa-sta...@lists.freedesktop.org
Cc: Chad Versace 
---
  src/mesa/drivers/dri/i965/brw_context.c | 15 +++
  1 file changed, 15 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index addacf2..e5d3b5c 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1283,6 +1283,21 @@ intel_resolve_for_dri2_flush(struct brw_context *brw,
   intel_miptree_prepare_external(brw, rb->mt);
} else {
   intel_renderbuffer_downsample(brw, rb);
+
+ /* Call prepare_external on the single-sample miptree to do any
+  * needed resolves prior to handing it off to the window system.
+  * This is needed in the case that rb->singlesample_mt is Y-tiled
+  * with CCS_E enabled but without I915_FORMAT_MOD_Y_TILED_CCS_E.  In
+  * this case, the MSAA resolve above will write compressed data into
+  * rb->singlesample_mt.
+  *
+  * TODO: Some day, if we decide to care about the tiny performance
+  * hit we're taking by doing the MSAA resolve and then a CCS resolve,
+  * we could detect this case and just allocate the single-sampled
+  * miptree without aux.  However, that would be a lot of plumbing and
+  * this is a rather exotic case so it's not really worth it.
+  */
+ intel_miptree_prepare_external(brw, rb->singlesample_mt);
}
 }
  }


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Re: [Mesa-dev] [Mesa-stable] [PATCH] util/build-id: Fix address comparison for binaries with LOAD vaddr > 0

[Emil Velikov]

On 25 January 2018 at 15:11, Stephan Gerhold  wrote:
> On Thu, Jan 25, 2018 at 11:22:10AM +, Emil Velikov wrote:
>> On 24 January 2018 at 14:13, Stephan Gerhold  wrote:
>> > build_id_find_nhdr_for_addr() fails to find the build-id if the first LOAD
>> > segment has a virtual address other than 0x0.
>> >
>> > For most shared libraries, the first LOAD segment has vaddr=0x0:
>> >
>> > Type   Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
>> > LOAD   0x00 0x 0x 0x2d2e26 0x2d2e26 R E 
>> > 0x1000
>> > LOAD   0x2d2e54 0x002d3e54 0x002d3e54 0x2e248 0x2f148 RW  
>> > 0x1000
>> >
>> > However, compiling the Intel Vulkan driver as 32-bit binary on Android 
>> > produces
>> > the following ELF header with vaddr=0x8000 instead:
>> >
>> > Type   Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
>> > PHDR   0x34 0x8034 0x8034 0x00100 0x00100 R   0x4
>> > LOAD   0x00 0x8000 0x8000 0x224a04 0x224a04 R E 
>> > 0x1000
>> > LOAD   0x225710 0x0022e710 0x0022e710 0x25988 0x27364 RW  
>> > 0x1000
>> >
>> > build_id_find_nhdr_callback() compares the address of dli_fbase from 
>> > dladdr()
>> > and dlpi_addr from dl_iterate_phdr(). With vaddr > 0, these point to a
>> > different memory address, e.g.:
>> >
>> > dli_fbase=0xd8395000 (offset 0x8000)
>> > dlpi_addr=0xd838d000
>> >
>> > At least on glibc and bionic (Android) dli_fbase refers to the address 
>> > where
>> > the shared object is mapped into the process space, whereas dlpi_addr is 
>> > just
>> > the base address for the vaddrs declared in the ELF header.
>> >
>> > To compare them correctly, we need to calculate the start of the mapping
>> > by adding the vaddr of the first LOAD segment to the base address.
>> >
>> > Cc: Chad Versace 
>> > Cc: Emil Velikov 
>> > Cc: Tapani Pälli 
>> > Cc: 
>> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104642
>> > Fixes: 5c98d38 "util: Query build-id by symbol address, not library name"
>> > ---
>> Based on my observation of glibc code and reading at the spec, I think
>> this is correct.
>> Admittedly the man page could be improved.
>>
>> FWIW I've poked the #musl people about this change last night, and
>> haven't heard any feedback yet.
>> Be that about a) our understanding of how it should work or b) musl's
>> implementation on the topic.
>
> I found a related discussion about the implementation of dli_fbase on the
> musl mailing list[1]. The FreeBSD man page for dladdr()[2] linked in the
> message on the musl mailing list is a bit more specific about dli_fbase:
>
> "The base address at which the shared object is mapped into the
> address space of the calling process."
>
> ... which is - at least as far as I understand it - exactly how glibc and
> bionic behave and the reason why we need this patch for LOAD vaddrs != 0.
>
> However, from what I've noticed when testing with musl, they seem to handle
> it unlike glibc/bionic/the FreeBSD man page. musl always returns the base
> address without the offset where the shared object is mapped.
>
> Technically, this means that this patch will break on musl in the rare
> situation that you actually link a shared library with LOAD vaddr != 0.
> However, considering that only they seem to handle it differently, this might
> be worth reporting to them instead?
>
musl does not have a bug tracker - according to the musl FAQ [A] and a
quick search.
Instead people should report bugs on IRC or ML :-\

I've poked the for the second time yesterday [on IRC] and will do a
final one tomorrow.
Modulo any objections (mesa or musl devs) I'll push this.

Thanks again Stephan.
Emil

[A] https://www.musl-libc.org/faq.html
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Re: [Mesa-dev] [PATCH] i965: Bump official kernel requirement to Linux v3.9.

[Emil Velikov]

On 31 January 2018 at 19:33, Kenneth Graunke  wrote:
> In commit 3f353342a6b6744773c26ed66b12afed42bd57af (present in 17.3.0)
> we started unconditionally using I915_EXEC_NO_RELOC, which was
> introduced in Linux v3.9.  ChromeOS kernel 3.8 has backported this,
> so it should work too.
>
> Running on older kernels would likely result in every single batch
> being rejected by the kernel, which is pretty catastrophic.  Yet, it
> appears that nobody noticed.  So, let's just bump the official
> requirement and move forward ever so slowly.
>
> Fixes: 3f353342a6b ("i965: Use I915_EXEC_NO_RELOC")
> ---

The 3.9 kernel was released nearly 5 years ago, with 5 LTS kernels since then.
IMHO, it is perfectly reasonable to have it as minimum requirement,
esp. with the 'side-effect' in mind.

Quick look at some distros/versions (via distrowatch) having a 3.9+ kernel
 - Debian 8 (oldstable)
 - Mint 16
 - Ubuntu 13.10 (already EOL)
 - elementary 0.3.2
 - Fedora 19
 - openSUSE 13.1
 - CentOS 7 (earlier versions list 2.6.x series kernel)

FWIW, the patch is
Acked-by: Emil Velikov 

-Emil
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Re: [Mesa-dev] misc pahole repacking

[Adrian M Negreanu]

There's a bug about quiting on unsupported tags:
https://bugzilla.redhat.com/show_bug.cgi?id=1348200

Should be fixed in v1.10
http://pkgs.fedoraproject.org/cgit/rpms/dwarves.git/commit/?h=f25

On Wed, Jan 31, 2018 at 5:57 PM, Brian Paul  wrote:

> On 01/31/2018 01:48 AM, Tapani Pälli wrote:
>
>> Reviewed-by: Tapani Pälli 
>>
>> (I verified the 1st one and I trust you on the 2nd one.)
>>
>> BTW I witnessed pahole crashing when processing visit() methods of
>> ir_print_visitor class, did you experience that? My pahole version is 1.9,
>> it dies in /lib64/libdwarves.so.1 after some prints like:
>>
>> --- 8< ---
>> die__process_unit: DW_TAG_restrict_type (0x37) @ <0x122be84> not handled!
>> die__process_unit: DW_TAG_unspecified_type (0x3b) @ <0x1230c68> not
>> handled!
>> die__process_unit: DW_TAG_restrict_type (0x37) @ <0x12312d3> not handled!
>> die__process_unit: DW_TAG_unspecified_type (0x3b) @ <0x1231bc4> not
>> handled!
>> die__process_unit: DW_TAG_restrict_type (0x37) @ <0x12340bb> not handled!
>> die__process_unit: DW_TAG_rvalue_reference_type (0x42) @ <0x123f984> not
>> handled!
>> die__process_unit: DW_TAG_rvalue_reference_type (0x42) @ <0x1242348> not
>> handled!
>> die__process_unit: DW_TAG_rvalue_reference_type (0x42) @ <0x1242398> not
>> handled!
>> die__process_unit: DW_TAG_rvalue_reference_type (0x42) @ <0x12423e8> not
>> handled!
>> die__process_unit: DW_TAG_rvalue_reference_type (0x42) @ <0x1242572> not
>> handled!
>> die__process_unit: DW_TAG_rvalue_reference_type (0x42) @ <0x12425c2> not
>> handled!
>> die__process_unit: DW_TAG_rvalue_reference_type (0x42) @ <0x12425ea> not
>> handled!
>> die__process_function: DW_TAG_rvalue_reference_type (0x42) @ <0x1247929>
>> not handled!
>>
>
> Me too.  I have v1.9 as well and it crashes pretty quickly, for example:
>
> $ pahole build-llvmpipe/lib/gallium/libGL.so.1.5.0
> struct xm_driver {
> struct pipe_screen *   (*create_pipe_screen)(Display *); /*
>  0   8 */
> struct st_api *(*create_st_api)(void); /* 8 8
> */
>
> /* size: 16, cachelines: 1, members: 2 */
> /* last cacheline: 16 bytes */
> };
> struct sw_winsys {
> void   (*destroy)(struct sw_winsys *); /*
>  0 8 */
> boolean(*is_displaytarget_format_supported)(struct
> sw_winsys *, unsigned int, enum pipe_format); /* 8 8 */
> struct sw_displaytarget *  (*displaytarget_create)(struct
> sw_winsys *, unsigned int, enum pipe_format, unsigned int, unsigned int,
> unsigned int, const void  *, unsigned int *); /*16 8 */
> struct sw_displaytarget *  (*displaytarget_from_handle)(struct
> sw_winsys *, const struct pipe_resource  *, struct winsys_handle *,
> unsigned int *); /*24 8 */
> boolean(*displaytarget_get_handle)(struct
> sw_winsys *, struct sw_displaytarget *, struct winsys_handle *); /*32
>8 */
> void * (*displaytarget_map)(struct sw_winsys
> *, struct sw_displaytarget *, unsigned int); /*40 8 */
> void   (*displaytarget_unmap)(struct sw_winsys
> *, struct sw_displaytarget *); /*48 8 */
> void   (*displaytarget_display)(struct
> sw_winsys *, struct sw_displaytarget *, void *, struct pipe_box *); /*
> 56 8 */
> /* --- cacheline 1 boundary (64 bytes) --- */
> void   (*displaytarget_destroy)(struct
> sw_winsys *, struct sw_displaytarget *); /*64 8 */
>
> /* size: 72, cachelines: 2, members: 9 */
> /* last cacheline: 8 bytes */
> };
> die__process_unit: DW_TAG_restrict_type (0x37) @ <0x3b09> not handled!
>
> -Brian
>
>
>
>>
>>
>> On 31.01.2018 01:41, Dave Airlie wrote:
>>
>>> This month's Dave hasn't got enough sleep to do real work, lets
>>> repack some structs.
>>>
>>> The format descriptions one is quite good though it reduces the
>>> radv binary data segment.
>>>
>>> Dave.
>>>
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