[Mesa-dev] [PATCH 06/24] i965/cnl: Add gen10 specific function declarations

[Anuj Phogat]

These declarations will help the code start compiling
once we wire up the makefiles for gen10. Later patches
will start using these functions for gen10.

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/isl/isl_priv.h  | 12 
 src/mesa/drivers/dri/i965/brw_blorp.h |  2 ++
 src/mesa/drivers/dri/i965/brw_state.h |  1 +
 3 files changed, 15 insertions(+)

diff --git a/src/intel/isl/isl_priv.h b/src/intel/isl/isl_priv.h
index 3c4cc1e..04adefa 100644
--- a/src/intel/isl/isl_priv.h
+++ b/src/intel/isl/isl_priv.h
@@ -178,6 +178,10 @@ isl_gen9_surf_fill_state_s(const struct isl_device *dev, 
void *state,
const struct isl_surf_fill_state_info *restrict 
info);
 
 void
+isl_gen10_surf_fill_state_s(const struct isl_device *dev, void *state,
+const struct isl_surf_fill_state_info *restrict 
info);
+
+void
 isl_gen4_buffer_fill_state_s(void *state,
  const struct isl_buffer_fill_state_info *restrict 
info);
 
@@ -206,6 +210,10 @@ isl_gen9_buffer_fill_state_s(void *state,
  const struct isl_buffer_fill_state_info *restrict 
info);
 
 void
+isl_gen10_buffer_fill_state_s(void *state,
+  const struct isl_buffer_fill_state_info 
*restrict info);
+
+void
 isl_gen4_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
   const struct isl_depth_stencil_hiz_emit_info 
*restrict info);
 
@@ -233,4 +241,8 @@ void
 isl_gen9_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
   const struct isl_depth_stencil_hiz_emit_info 
*restrict info);
 
+void
+isl_gen10_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
+   const struct 
isl_depth_stencil_hiz_emit_info *restrict info);
+
 #endif /* ISL_PRIV_H */
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index ee4bf3b..d635d79 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -82,6 +82,8 @@ void gen8_blorp_exec(struct blorp_batch *batch,
  const struct blorp_params *params);
 void gen9_blorp_exec(struct blorp_batch *batch,
  const struct blorp_params *params);
+void gen10_blorp_exec(struct blorp_batch *batch,
+  const struct blorp_params *params);
 
 #ifdef __cplusplus
 } /* extern "C" */
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 4727e2a..4592e3e 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -364,6 +364,7 @@ void gen7_init_atoms(struct brw_context *brw);
 void gen75_init_atoms(struct brw_context *brw);
 void gen8_init_atoms(struct brw_context *brw);
 void gen9_init_atoms(struct brw_context *brw);
+void gen10_init_atoms(struct brw_context *brw);
 
 void upload_gs_state_for_tf(struct brw_context *brw);
 
-- 
2.9.3

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[Mesa-dev] [PATCH 10/24] i965/cnl: Wire up android Mesa build files for gen10

[Anuj Phogat]

Note: This patch is untested.

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/Android.genxml.mk  |  5 +
 src/intel/Android.isl.mk | 20 
 src/intel/Android.vulkan.mk  | 21 +
 src/mesa/drivers/dri/i965/Android.mk | 24 +++-
 4 files changed, 69 insertions(+), 1 deletion(-)

diff --git a/src/intel/Android.genxml.mk b/src/intel/Android.genxml.mk
index 4b0746c..e4d8dd8 100644
--- a/src/intel/Android.genxml.mk
+++ b/src/intel/Android.genxml.mk
@@ -96,6 +96,11 @@ $(intermediates)/genxml/gen9_pack.h: PRIVATE_XML := 
$(LOCAL_PATH)/genxml/gen9.xm
 $(intermediates)/genxml/gen9_pack.h: $(LOCAL_PATH)/genxml/gen9.xml 
$(LOCAL_PATH)/genxml/gen_pack_header.py
$(call header-gen)
 
+$(intermediates)/genxml/gen10_pack.h: PRIVATE_SCRIPT := $(MESA_PYTHON2) 
$(LOCAL_PATH)/genxml/gen_pack_header.py
+$(intermediates)/genxml/gen10_pack.h: PRIVATE_XML := 
$(LOCAL_PATH)/genxml/gen10.xml
+$(intermediates)/genxml/gen10_pack.h: $(LOCAL_PATH)/genxml/gen10.xml 
$(LOCAL_PATH)/genxml/gen_pack_header.py
+   $(call header-gen)
+
 $(intermediates)/genxml/genX_xml.h: $(addprefix 
$(MESA_TOP)/src/intel/,$(GENXML_XML_FILES)) 
$(MESA_TOP)/src/intel/genxml/gen_zipped_file.py
@mkdir -p $(dir $@)
@echo "Gen Header: $(PRIVATE_MODULE) <= $(notdir $(@))"
diff --git a/src/intel/Android.isl.mk b/src/intel/Android.isl.mk
index 67e6d2d..516ac3a 100644
--- a/src/intel/Android.isl.mk
+++ b/src/intel/Android.isl.mk
@@ -161,6 +161,25 @@ include $(MESA_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)
 
 # ---
+# Build libmesa_isl_gen10
+# ---
+
+include $(CLEAR_VARS)
+
+LOCAL_MODULE := libmesa_isl_gen10
+
+LOCAL_SRC_FILES := $(ISL_GEN10_FILES)
+
+LOCAL_CFLAGS := -DGEN_VERSIONx10=100
+
+LOCAL_C_INCLUDES := $(LIBISL_GENX_COMMON_INCLUDES)
+
+LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_genxml
+
+include $(MESA_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)
+
+# ---
 # Build libmesa_isl
 # ---
 
@@ -187,6 +206,7 @@ LOCAL_WHOLE_STATIC_LIBRARIES := \
libmesa_isl_gen75 \
libmesa_isl_gen8 \
libmesa_isl_gen9 \
+   libmesa_isl_gen10 \
libmesa_genxml
 
 # Autogenerated sources
diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk
index 831b658..566db29 100644
--- a/src/intel/Android.vulkan.mk
+++ b/src/intel/Android.vulkan.mk
@@ -158,6 +158,26 @@ include $(MESA_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)
 
 #
+# libanv for gen10
+#
+
+include $(CLEAR_VARS)
+LOCAL_MODULE := libmesa_anv_gen10
+LOCAL_MODULE_CLASS := STATIC_LIBRARIES
+
+LOCAL_SRC_FILES := $(VULKAN_GEN10_FILES)
+LOCAL_CFLAGS := -DGEN_VERSIONx10=100
+
+LOCAL_C_INCLUDES := $(ANV_INCLUDES)
+
+LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_anv_entrypoints libmesa_genxml
+
+LOCAL_SHARED_LIBRARIES := libdrm
+
+include $(MESA_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)
+
+#
 # libmesa_vulkan_common
 #
 
@@ -228,6 +248,7 @@ LOCAL_WHOLE_STATIC_LIBRARIES := \
libmesa_anv_gen75 \
libmesa_anv_gen8 \
libmesa_anv_gen9 \
+   libmesa_anv_gen10 \
libmesa_intel_compiler \
libmesa_anv_entrypoints
 
diff --git a/src/mesa/drivers/dri/i965/Android.mk 
b/src/mesa/drivers/dri/i965/Android.mk
index 7c4fada..7ee9ab7 100644
--- a/src/mesa/drivers/dri/i965/Android.mk
+++ b/src/mesa/drivers/dri/i965/Android.mk
@@ -47,7 +47,8 @@ I965_PERGEN_LIBS := \
libmesa_i965_gen7 \
libmesa_i965_gen75 \
libmesa_i965_gen8 \
-   libmesa_i965_gen9
+   libmesa_i965_gen9 \
+   libmesa_i965_gen10
 
 # ---
 # Build libmesa_i965_gen4
@@ -218,6 +219,27 @@ include $(MESA_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)
 
 # ---
+# Build libmesa_i965_gen10
+# ---
+
+include $(CLEAR_VARS)
+
+LOCAL_MODULE := libmesa_i965_gen10
+
+LOCAL_C_INCLUDES := $(I965_PERGEN_COMMON_INCLUDES)
+
+LOCAL_SRC_FILES := $(i965_gen10_FILES)
+
+LOCAL_SHARED_LIBRARIES := $(I965_PERGEN_SHARED_LIBRARIES)
+
+LOCAL_STATIC_LIBRARIES := $(I965_PERGEN_STATIC_LIBRARIES)
+
+LOCAL_CFLAGS := -DGEN_VERSIONx10=100
+
+include $(MESA_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)
+
+# ---
 # Build i965_dri
 # ---
 
-- 
2.9.3

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[Mesa-dev] [PATCH 05/24] i965/cnl: Include gen10_pack.h

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/genxml/genX_pack.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/intel/genxml/genX_pack.h b/src/intel/genxml/genX_pack.h
index 2ec2226..187e75c 100644
--- a/src/intel/genxml/genX_pack.h
+++ b/src/intel/genxml/genX_pack.h
@@ -44,6 +44,8 @@
 #  include "genxml/gen8_pack.h"
 #elif (GEN_VERSIONx10 == 90)
 #  include "genxml/gen9_pack.h"
+#elif (GEN_VERSIONx10 == 100)
+#  include "genxml/gen10_pack.h"
 #else
 #  error "Need to add a pack header include for this gen"
 #endif
-- 
2.9.3

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[Mesa-dev] [PATCH 01/24] i965: Make feature macros gen8 based

[Anuj Phogat]

From: Ben Widawsky <benjamin.widaw...@intel.com>

All the "features" of the hardware are similar starting with GEN8, so remove as
much of the GEN9 uniqueness as possible. This makes implementing future gen
platforms a bit easier.

Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com>
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/common/gen_device_info.c | 13 +
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/src/intel/common/gen_device_info.c 
b/src/intel/common/gen_device_info.c
index 209b293..47aed9d 100644
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -378,15 +378,8 @@ static const struct gen_device_info gen_device_info_chv = {
}
 };
 
-#define GEN9_FEATURES   \
+#define GEN9_HW_INFO\
.gen = 9,\
-   .has_hiz_and_separate_stencil = true,\
-   .has_resource_streamer = true,   \
-   .must_use_separate_stencil = true,   \
-   .has_llc = true, \
-   .has_pln = true, \
-   .supports_simd16_3src = true,\
-   .has_surface_tile_offset = true, \
.max_vs_threads = 336,   \
.max_gs_threads = 336,   \
.max_tcs_threads = 336,  \
@@ -454,6 +447,10 @@ static const struct gen_device_info gen_device_info_chv = {
   },   \
}
 
+#define GEN9_FEATURES   \
+   GEN8_FEATURES,   \
+   GEN9_HW_INFO
+
 static const struct gen_device_info gen_device_info_skl_gt1 = {
GEN9_FEATURES, .gt = 1,
.num_slices = 1,
-- 
2.9.3

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[Mesa-dev] [PATCH 03/24] i965/cnl: Add gen10.xml

[Anuj Phogat]

From: Jason Ekstrand <jason.ekstr...@intel.com>

This patch is truncated due to the size. You can find the full
patch in my review branch.

V2(Anuj): Add default value for length of 3DPRIMITIVE command
  Add values for 'Attribute Active Component Format'
  Rename few fields to match gen9.xml

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/genxml/gen10.xml | 3563 
 1 file changed, 3563 insertions(+)
 create mode 100644 src/intel/genxml/gen10.xml

diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
new file mode 100644
index 000..685bd89
--- /dev/null
+++ b/src/intel/genxml/gen10.xml
-- 
2.9.3

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[Mesa-dev] [PATCH 02/24] i965/cnl: Add a preliminary device for Cannonlake

[Anuj Phogat]

From: Ben Widawsky <benjamin.widaw...@intel.com>

v2 (Anuj):
Rebased on master and updated pci ids
Remove redundant initialization of max_wm_threads to 64 * 12.
For gen9+ max_wm_threads are initialized in gen_get_device_info().

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com>
---
 include/pci_ids/i965_pci_ids.h | 12 
 src/intel/common/gen_device_info.c | 58 ++
 src/intel/common/gen_device_info.h |  1 +
 3 files changed, 71 insertions(+)

diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index 17504f5..b296359 100644
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -165,3 +165,15 @@ CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650 
(Kaby Lake GT3)")
 CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4")
 CHIPSET(0x3184, glk, "Intel(R) HD Graphics (Geminilake)")
 CHIPSET(0x3185, glk_2x6, "Intel(R) HD Graphics (Geminilake 2x6)")
+CHIPSET(0x5A49, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
+CHIPSET(0x5A4A, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
+CHIPSET(0x5A41, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
+CHIPSET(0x5A42, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
+CHIPSET(0x5A44, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
+CHIPSET(0x5A59, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)")
+CHIPSET(0x5A5A, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)")
+CHIPSET(0x5A5C, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)")
+CHIPSET(0x5A50, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
+CHIPSET(0x5A51, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
+CHIPSET(0x5A52, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
+CHIPSET(0x5A54, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
diff --git a/src/intel/common/gen_device_info.c 
b/src/intel/common/gen_device_info.c
index 47aed9d..87edb94 100644
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -555,6 +555,64 @@ static const struct gen_device_info 
gen_device_info_glk_2x6 = {
GEN9_LP_FEATURES_2X6
 };
 
+#define GEN10_HW_INFO   \
+   .gen = 10,   \
+   .max_vs_threads = 728,   \
+   .max_gs_threads = 432,   \
+   .max_tcs_threads = 432,  \
+   .max_tes_threads = 624,  \
+   .max_cs_threads = 56,\
+   .urb = { \
+  .size = 256,  \
+  .min_entries = {  \
+ [MESA_SHADER_VERTEX]= 64,  \
+ [MESA_SHADER_TESS_EVAL] = 34,  \
+  },\
+  .max_entries = {  \
+  [MESA_SHADER_VERTEX]   = 3936,\
+  [MESA_SHADER_TESS_CTRL]= 896, \
+  [MESA_SHADER_TESS_EVAL]= 2064,\
+  [MESA_SHADER_GEOMETRY] = 832, \
+  },\
+   }
+
+#define GEN10_FEATURES(_gt, _slices, _l3)   \
+   GEN8_FEATURES,   \
+   GEN10_HW_INFO,   \
+   .gt = _gt, .num_slices = _slices, .l3_banks = _l3
+
+static const struct gen_device_info gen_device_info_cnl_2x8 = {
+   /* GT0.5 */
+   GEN10_FEATURES(1, 1, 2)
+};
+
+static const struct gen_device_info gen_device_info_cnl_3x8 = {
+   /* GT1 */
+   GEN10_FEATURES(1, 1, 3)
+};
+
+static const struct gen_device_info gen_device_info_cnl_4x8 = {
+   /* GT 1.5 */
+   GEN10_FEATURES(1, 2, 6)
+};
+
+static const struct gen_device_info gen_device_info_cnl_5x8 = {
+   /* GT2 */
+   GEN10_FEATURES(2, 2, 6)
+};
+
+static const struct gen_device_info gen_device_info_cnl_gt1 = {
+   GEN10_FEATURES(1, 1, 3)
+};
+
+static const struct gen_device_info gen_device_info_cnl_gt2 = {
+   GEN10_FEATURES(2, 2, 6)
+};
+
+static const struct gen_device_info gen_device_info_cnl_gt3 = {
+   GEN10_FEATURES(3, 4, 12)
+};
+
 bool
 gen_get_device_info(int devid, struct gen_device_info *devinfo)
 {
diff --git a/src/intel/common/gen_device_info.h 
b/src/intel/common/gen_device_info.h
index 80676d0..6207630 100644
--- a/src/intel/common/gen_device_info.h
+++ b/src/intel/common/gen_device_info.h
@@ -96,6 +96,7 @@ struct gen_device_info
 * to change, so we program @max_cs_threads as the lower maximum.
 */
unsigned num_slices;
+   unsigned l3_banks;
unsigned max_vs_threads;   /**< Maximum Vertex Shader threads */
unsigned max_tcs_threads;  /**< Maximum Hull Shader threads */
  

[Mesa-dev] [PATCH V2 00/24] Add Cannonlake support

[Anuj Phogat]

This series adds support for Cannonlake.

Changes from V1 to V2:
- Incorporated the review comments from V1.
- Rebased 8 months old CNL branch on top of master
- Wired up Linux and Android build files for gen10
- Replaced the use of few gen9 functions with gen10 specific functions.
- Squashed few patches, dropped few and created new patches.

What's remaining:
- Add missing gen10 bits in Vulkan driver.
- Fix failing piglit, cts tests for GL and Vulkan.

You can also find this series at:
https://github.com/aphogat/mesa.git
branch: reviews

Anuj Phogat (18):
  i965/cnl: Define genX(x) and GENX(x) for gen10
  i965/cnl: Include gen10_pack.h
  i965/cnl: Add gen10 specific function declarations
  i965/cnl: Update the script generating genX_bits.h
  i965/cnl: Add isl_gen10 header and source files
  i965/cnl: Wire up Mesa build files for gen10
  i965/cnl: Wire up android Mesa build files for gen10
  i965/cnl: Add pci id for INTEL_DEVID_OVERRIDE
  i965/cnl: Add cnl bits in aubinator
  i965/cnl: Update few assertions
  i965/cnl: Handle gen10 in switch cases across the driver
  i965/cnl: Start using CNL MOCS defines
  i965/cnl: Start using gen10 specific functions
  i965/cnl: Don't resolve single sampled color rb in case of sRGB formats
  i965/cnl: Make URB {VS, GS, HS, DS} sizes non multiple of 3
  i965/cnl: Reformat surface_format_info table to accomodate gen10+
  i965/cnl: Enable CCS_E and RT support for few formats
  i965: Simplify get_l3_way_size() function

Ben Widawsky (5):
  i965: Make feature macros gen8 based
  i965/cnl: Add a preliminary device for Cannonlake
  i965/cnl: Implement new pipe control workaround
  i965/cnl: Implement depth count workaround
  i965/cnl: Restore lossless compression for sRGB formats

Jason Ekstrand (1):
  i965/cnl: Add gen10.xml

 include/pci_ids/i965_pci_ids.h   |   12 +
 src/intel/Android.genxml.mk  |5 +
 src/intel/Android.isl.mk |   20 +
 src/intel/Android.vulkan.mk  |   21 +
 src/intel/Makefile.isl.am|4 +
 src/intel/Makefile.sources   |   12 +-
 src/intel/Makefile.vulkan.am |7 +-
 src/intel/common/gen_device_info.c   |   71 +-
 src/intel/common/gen_device_info.h   |1 +
 src/intel/common/gen_l3_config.c |   11 +-
 src/intel/compiler/brw_compiler.h|2 +-
 src/intel/compiler/brw_eu.c  |2 +
 src/intel/compiler/brw_eu_compact.c  |1 +
 src/intel/genxml/gen10.xml   | 3563 ++
 src/intel/genxml/genX_pack.h |2 +
 src/intel/genxml/gen_bits_header.py  |6 +-
 src/intel/genxml/gen_macros.h|3 +
 src/intel/isl/isl.c  |9 +
 src/intel/isl/isl_format.c   |  498 +--
 src/intel/isl/isl_gen10.c|   41 +
 src/intel/isl/isl_gen10.h|   45 +
 src/intel/isl/isl_priv.h |   12 +
 src/intel/tools/aubinator.c  |8 +-
 src/intel/vulkan/anv_cmd_buffer.c|1 +
 src/intel/vulkan/anv_device.c|1 +
 src/intel/vulkan/anv_entrypoints_gen.py  |1 +
 src/mesa/drivers/dri/i965/Android.mk |   24 +-
 src/mesa/drivers/dri/i965/Makefile.am|6 +-
 src/mesa/drivers/dri/i965/Makefile.sources   |4 +
 src/mesa/drivers/dri/i965/brw_blorp.c|6 +
 src/mesa/drivers/dri/i965/brw_blorp.h|2 +
 src/mesa/drivers/dri/i965/brw_context.c  |2 +-
 src/mesa/drivers/dri/i965/brw_formatquery.c  |1 +
 src/mesa/drivers/dri/i965/brw_pipe_control.c |   11 +
 src/mesa/drivers/dri/i965/brw_program.c  |2 +-
 src/mesa/drivers/dri/i965/brw_queryobj.c |8 +
 src/mesa/drivers/dri/i965/brw_state.h|9 +
 src/mesa/drivers/dri/i965/brw_state_upload.c |4 +-
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |2 +
 src/mesa/drivers/dri/i965/gen7_urb.c |   12 +
 src/mesa/drivers/dri/i965/genX_state_upload.c|4 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c|2 +-
 src/mesa/drivers/dri/i965/intel_screen.c |2 +
 43 files changed, 4180 insertions(+), 280 deletions(-)
 create mode 100644 src/intel/genxml/gen10.xml
 create mode 100644 src/intel/isl/isl_gen10.c
 create mode 100644 src/intel/isl/isl_gen10.h

-- 
2.9.3

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[Mesa-dev] [PATCH 14/24] i965/cnl: Handle gen10 in switch cases across the driver

[Anuj Phogat]

We are still using some gen9 functions for gen10 in this patch.
They will be replaced by gen10 functions in later patches.

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/common/gen_l3_config.c| 1 +
 src/intel/compiler/brw_eu.c | 2 ++
 src/intel/compiler/brw_eu_compact.c | 1 +
 src/intel/isl/isl.c | 3 +++
 src/intel/vulkan/anv_cmd_buffer.c   | 1 +
 src/intel/vulkan/anv_device.c   | 1 +
 src/intel/vulkan/anv_entrypoints_gen.py | 1 +
 src/mesa/drivers/dri/i965/brw_blorp.c   | 1 +
 src/mesa/drivers/dri/i965/brw_formatquery.c | 1 +
 src/mesa/drivers/dri/i965/intel_screen.c| 1 +
 10 files changed, 13 insertions(+)

diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index 0783217..4fe3503 100644
--- a/src/intel/common/gen_l3_config.c
+++ b/src/intel/common/gen_l3_config.c
@@ -116,6 +116,7 @@ get_l3_configs(const struct gen_device_info *devinfo)
   return (devinfo->is_cherryview ? chv_l3_configs : bdw_l3_configs);
 
case 9:
+   case 10:
   return chv_l3_configs;
 
default:
diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c
index 77400c1..2c0dc27 100644
--- a/src/intel/compiler/brw_eu.c
+++ b/src/intel/compiler/brw_eu.c
@@ -412,6 +412,7 @@ enum gen {
GEN75 = (1 << 5),
GEN8  = (1 << 6),
GEN9  = (1 << 7),
+   GEN10  = (1 << 8),
GEN_ALL = ~0
 };
 
@@ -688,6 +689,7 @@ gen_from_devinfo(const struct gen_device_info *devinfo)
case 7: return devinfo->is_haswell ? GEN75 : GEN7;
case 8: return GEN8;
case 9: return GEN9;
+   case 10: return GEN10;
default:
   unreachable("not reached");
}
diff --git a/src/intel/compiler/brw_eu_compact.c 
b/src/intel/compiler/brw_eu_compact.c
index b2af76d..740a395 100644
--- a/src/intel/compiler/brw_eu_compact.c
+++ b/src/intel/compiler/brw_eu_compact.c
@@ -1362,6 +1362,7 @@ brw_init_compaction_tables(const struct gen_device_info 
*devinfo)
assert(gen8_src_index_table[ARRAY_SIZE(gen8_src_index_table) - 1] != 0);
 
switch (devinfo->gen) {
+   case 10:
case 9:
case 8:
   control_index_table = gen8_control_index_table;
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index f89f351..5dc41fa 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1672,6 +1672,7 @@ isl_surf_fill_state_s(const struct isl_device *dev, void 
*state,
   isl_gen8_surf_fill_state_s(dev, state, info);
   break;
case 9:
+   case 10:
   isl_gen9_surf_fill_state_s(dev, state, info);
   break;
default:
@@ -1703,6 +1704,7 @@ isl_buffer_fill_state_s(const struct isl_device *dev, 
void *state,
   isl_gen8_buffer_fill_state_s(state, info);
   break;
case 9:
+   case 10:
   isl_gen9_buffer_fill_state_s(state, info);
   break;
default:
@@ -1770,6 +1772,7 @@ isl_emit_depth_stencil_hiz_s(const struct isl_device 
*dev, void *batch,
   isl_gen8_emit_depth_stencil_hiz_s(dev, batch, info);
   break;
case 9:
+   case 10:
   isl_gen9_emit_depth_stencil_hiz_s(dev, batch, info);
   break;
default:
diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index 120b864..d34f9f8 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -334,6 +334,7 @@ anv_cmd_buffer_emit_state_base_address(struct 
anv_cmd_buffer *cmd_buffer)
case 8:
   return gen8_cmd_buffer_emit_state_base_address(cmd_buffer);
case 9:
+   case 10:
   return gen9_cmd_buffer_emit_state_base_address(cmd_buffer);
default:
   unreachable("unsupported gen\n");
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 35e4030..455c5f9 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1141,6 +1141,7 @@ VkResult anv_CreateDevice(
   result = gen8_init_device_state(device);
   break;
case 9:
+   case 10:
   result = gen9_init_device_state(device);
   break;
default:
diff --git a/src/intel/vulkan/anv_entrypoints_gen.py 
b/src/intel/vulkan/anv_entrypoints_gen.py
index a21228c..f293848 100644
--- a/src/intel/vulkan/anv_entrypoints_gen.py
+++ b/src/intel/vulkan/anv_entrypoints_gen.py
@@ -183,6 +183,7 @@ TEMPLATE_C = Template(textwrap.dedent(u"""\
}
 
switch (devinfo->gen) {
+   case 10:
case 9:
   if (gen9_layer.entrypoints[index])
  return gen9_layer.entrypoints[index];
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index b69cb4f..8a6cc66 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -94,6 +94,7 @@ brw_blorp_init(struct brw_context *brw)
   brw->blorp.exec = gen8_blorp_exec;
   break;
case 9:
+   case 10:
   brw->blorp.mocs.tex = SKL_MOCS_WB;
   brw->blorp.mocs.rb 

Re: [Mesa-dev] [PATCH 11/12] i965/cnl: Properly handle l3 configuration

[Anuj Phogat]

On Mon, Apr 24, 2017 at 9:15 PM, Ben Widawsky <b...@bwidawsk.net> wrote:

> On 17-04-18 18:18:39, Francisco Jerez wrote:
>
> Most, if not all of the unrelated changes that snuck in were due to rebase.
> Anuj, would you mind fixing those? I tried my best to address the rest,
> but I'm
> admittedly stumbling my way through some of the l3 programming.
>
> Anuj Phogat <anuj.pho...@gmail.com> writes:
>>
>> From: Ben Widawsky <benjamin.widaw...@intel.com>
>>>
>>> V2: Squash the changes in one patch and rebased on master (Anuj).
>>>
>>> Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
>>> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
>>> ---
>>>  src/intel/common/gen_l3_config.c | 43 ++
>>> --
>>>  1 file changed, 37 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/src/intel/common/gen_l3_config.c
>>> b/src/intel/common/gen_l3_config.c
>>> index 4fe3503..f3e8793 100644
>>> --- a/src/intel/common/gen_l3_config.c
>>> +++ b/src/intel/common/gen_l3_config.c
>>> @@ -102,6 +102,26 @@ static const struct gen_l3_config chv_l3_configs[]
>>> = {
>>>  };
>>>
>>>  /**
>>> + * On CNL, RO clients are merged and shared with read/write space. As a
>>> result
>>> + * we have fewer allocation parameters.
>>>
>>
>> The two sentences above make it sound like RO clients haven't been part
>> of the same partition until CNL.  They have.  I'd drop this.
>>
>>
> So the difference I was trying to spell out is that the previous "IS" "C"
> and
> "T" fields do not exist in a programmable way.
>
> Also, programming does not require any
>>> + * back scaling. Programming simply works in 2k increments and is
>>> scaled by the
>>> + * hardware.
>>>
>>
>> That's basically the case (up to the specific scale factor) on all
>> hardware, I'd drop this too.
>>
>>
> I personally think the existing code isn't as self-documenting to me as it
> is to
> you, and so I was trying to spell it out. I was trying to document, not
> show
> differentiation. In either event, I don't care if we keep this or leave it.
>
> + */
>>> +static const struct gen_l3_config cnl_l3_configs[] = {
>>> +   /* SLM URB Rest  DC  RO */
>>>
>>
>> s/Rest/ALL/ (these are L3 partition enum labels), and align to the
>> column boundaries below.
>>
>>
> Sure.
>
>
> +   {{  0, 64, 64,  0,  0 }},
>>> +   {{  0, 64,  0, 16, 48 }},
>>> +   {{  0, 48,  0, 16, 64 }},
>>> +   {{  0, 32,  0,  0, 96 }},
>>> +   {{  0, 32, 96,  0,  0 }},
>>> +   {{  0, 32,  0, 16, 80 }},
>>> +   {{ 32, 16, 80,  0,  0 }},
>>> +   {{ 32, 16,  0, 64, 16 }},
>>> +   {{ 32,  0, 96,  0,  0 }},
>>> +   {{ 0 }}
>>> +};
>>> +
>>> +/**
>>>   * Return a zero-terminated array of validated L3 configurations for the
>>>   * specified device.
>>>   */
>>> @@ -116,9 +136,11 @@ get_l3_configs(const struct gen_device_info
>>> *devinfo)
>>>return (devinfo->is_cherryview ? chv_l3_configs : bdw_l3_configs);
>>>
>>> case 9:
>>> -   case 10:
>>>return chv_l3_configs;
>>>
>>> +   case 10:
>>> +  return cnl_l3_configs;
>>> +
>>> default:
>>>unreachable("Not implemented");
>>> }
>>> @@ -258,13 +280,19 @@ get_l3_way_size(const struct gen_device_info
>>> *devinfo)
>>> if (devinfo->is_baytrail)
>>>return 2;
>>>
>>> -   else if (devinfo->gt == 1 ||
>>> -devinfo->is_cherryview ||
>>> -devinfo->is_broxton)
>>>
>>
>> Unrelated change sneaked in.
>>
>>
> See above reply (not sure how this got in other than rebase).
>
> +   /* Way size is actually 6 * num_slices, because it's 2k per bank, and
>>> +* normally 3 banks per slice. However, on CNL+ this information
>>> isn't
>>> +* needed to setup the URB/l3 configuration. We fudge the answer here
>>> +* and then use the scaling to fix it up later.
>>> +*/
>>>
>>
>> The comment makes it sound like you're lying to the caller and returning
>> a bogus way size you're going to fix up later.  That's not the case
>> though, the value you're returning below is accurate for all CNL
>> configs.  6 * num

Re: [Mesa-dev] [PATCH 07/12] i965/cnl: Restore lossless compression for sRGB formats

[Anuj Phogat]

On Mon, Apr 24, 2017 at 10:57 PM, Ben Widawsky <b...@bwidawsk.net> wrote:

> On 17-04-15 18:27:33, Jason Ekstrand wrote:
>
>> On April 14, 2017 5:37:55 PM Anuj Phogat <anuj.pho...@gmail.com> wrote:
>>
>> From: Ben Widawsky <b...@bwidawsk.net>
>>>
>>> This support was removed on gen9 (it worked before then) and was brought
>>> back
>>> for gen10.
>>>
>>> Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com>
>>> ---
>>> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
>>> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
>>> index 467ada5..c8014b9 100644
>>> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
>>> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
>>> @@ -207,7 +207,7 @@ intel_miptree_supports_non_msrt_fast_clear(struct
>>> brw_context *brw,
>>>if (!brw->format_supported_as_render_target[mt->format])
>>>   return false;
>>>
>>> -   if (brw->gen >= 9) {
>>> +   if (brw->gen == 9) {
>>>   mesa_format linear_format = _mesa_get_srgb_format_linear(m
>>> t->format);
>>>   const uint32_t brw_format = brw_isl_format_for_mesa_format
>>> (linear_format);
>>>   return isl_format_supports_ccs_e(>screen->devinfo,
>>> brw_format);
>>>
>>
>> I thought sRGB was supported for CCS_E on CNL.  If so, we should update
>> the table in isl_format_supports_ccs_e().  Also, I believe sRGB is
>> supported for CCS_D even on sky lake, you just can't sample from it.
>>
>>
> The patch predates ISL... yes, we should. Anuj, would you mind doing this?

​I'll update the table in v2. As sRGB now supports lossless compression,
don't we
also need to stop resolving single sampled color render buffers for sRGB
formats
in Gen 10? See i965/brw_context.c:329
[snip]
   /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
the
* single-sampled color renderbuffers because the CCS buffer isn't
* supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
* enabled because otherwise the surface state will be programmed with
the
* linear equivalent format anyway.
*/
   if (brw->gen >= 9 && ctx->Color.sRGBEnabled) {
  struct gl_framebuffer *fb = ctx->DrawBuffer;
  for (int i = 0; i < fb->_NumColorDrawBuffers; i++) {


​

>
>
> --
>>> 2.9.3
>>>
>>> ___
>>> mesa-dev mailing list
>>> mesa-dev@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>>>
>>
>>
>>
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Re: [Mesa-dev] [PATCH 11/12] i965/cnl: Properly handle l3 configuration

[Anuj Phogat]

On Mon, Apr 24, 2017 at 9:15 PM, Ben Widawsky <b...@bwidawsk.net> wrote:

> On 17-04-18 18:18:39, Francisco Jerez wrote:
>
> Most, if not all of the unrelated changes that snuck in were due to rebase.
> Anuj, would you mind fixing those? I tried my best to address the rest,
> but I'm
> admittedly stumbling my way through some of the l3 programming.

​Yes, unrelated changes are due to bad rebase. I'll fix them in V2.​

>
>
> Anuj Phogat <anuj.pho...@gmail.com> writes:
>>
>> From: Ben Widawsky <benjamin.widaw...@intel.com>
>>>
>>> V2: Squash the changes in one patch and rebased on master (Anuj).
>>>
>>> Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
>>> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
>>> ---
>>>  src/intel/common/gen_l3_config.c | 43 ++
>>> --
>>>  1 file changed, 37 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/src/intel/common/gen_l3_config.c
>>> b/src/intel/common/gen_l3_config.c
>>> index 4fe3503..f3e8793 100644
>>> --- a/src/intel/common/gen_l3_config.c
>>> +++ b/src/intel/common/gen_l3_config.c
>>> @@ -102,6 +102,26 @@ static const struct gen_l3_config chv_l3_configs[]
>>> = {
>>>  };
>>>
>>>  /**
>>> + * On CNL, RO clients are merged and shared with read/write space. As a
>>> result
>>> + * we have fewer allocation parameters.
>>>
>>
>> The two sentences above make it sound like RO clients haven't been part
>> of the same partition until CNL.  They have.  I'd drop this.
>>
>>
> So the difference I was trying to spell out is that the previous "IS" "C"
> and
> "T" fields do not exist in a programmable way.
>
> Also, programming does not require any
>>> + * back scaling. Programming simply works in 2k increments and is
>>> scaled by the
>>> + * hardware.
>>>
>>
>> That's basically the case (up to the specific scale factor) on all
>> hardware, I'd drop this too.
>>
>>
> I personally think the existing code isn't as self-documenting to me as it
> is to
> you, and so I was trying to spell it out. I was trying to document, not
> show
> differentiation. In either event, I don't care if we keep this or leave it.
>
> + */
>>> +static const struct gen_l3_config cnl_l3_configs[] = {
>>> +   /* SLM URB Rest  DC  RO */
>>>
>>
>> s/Rest/ALL/ (these are L3 partition enum labels), and align to the
>> column boundaries below.
>>
>>
> Sure.
>
>
> +   {{  0, 64, 64,  0,  0 }},
>>> +   {{  0, 64,  0, 16, 48 }},
>>> +   {{  0, 48,  0, 16, 64 }},
>>> +   {{  0, 32,  0,  0, 96 }},
>>> +   {{  0, 32, 96,  0,  0 }},
>>> +   {{  0, 32,  0, 16, 80 }},
>>> +   {{ 32, 16, 80,  0,  0 }},
>>> +   {{ 32, 16,  0, 64, 16 }},
>>> +   {{ 32,  0, 96,  0,  0 }},
>>> +   {{ 0 }}
>>> +};
>>> +
>>> +/**
>>>   * Return a zero-terminated array of validated L3 configurations for the
>>>   * specified device.
>>>   */
>>> @@ -116,9 +136,11 @@ get_l3_configs(const struct gen_device_info
>>> *devinfo)
>>>return (devinfo->is_cherryview ? chv_l3_configs : bdw_l3_configs);
>>>
>>> case 9:
>>> -   case 10:
>>>return chv_l3_configs;
>>>
>>> +   case 10:
>>> +  return cnl_l3_configs;
>>> +
>>> default:
>>>unreachable("Not implemented");
>>> }
>>> @@ -258,13 +280,19 @@ get_l3_way_size(const struct gen_device_info
>>> *devinfo)
>>> if (devinfo->is_baytrail)
>>>return 2;
>>>
>>> -   else if (devinfo->gt == 1 ||
>>> -devinfo->is_cherryview ||
>>> -devinfo->is_broxton)
>>>
>>
>> Unrelated change sneaked in.
>>
>>
> See above reply (not sure how this got in other than rebase).
>
> +   /* Way size is actually 6 * num_slices, because it's 2k per bank, and
>>> +* normally 3 banks per slice. However, on CNL+ this information
>>> isn't
>>> +* needed to setup the URB/l3 configuration. We fudge the answer here
>>> +* and then use the scaling to fix it up later.
>>> +*/
>>>
>>
>> The comment makes it sound like you're lying to the caller and returning
>> a bogus way size you're going to fix up later.  That's not the case
>> t

Re: [Mesa-dev] [PATCH 02/12] i965/cnl: Add gen10.xml

[Anuj Phogat]

On Thu, Apr 20, 2017 at 9:55 AM, Emil Velikov <emil.l.veli...@gmail.com> wrote:
> Hi Anuj,
>
> On 15 April 2017 at 01:35, Anuj Phogat <anuj.pho...@gmail.com> wrote:
>> From: Jason Ekstrand <jason.ekstr...@intel.com>
>>
>> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
>> ---
>>  src/intel/Makefile.sources |3 +-
>>  src/intel/genxml/gen10.xml | 3557 
>> 
>>  2 files changed, 3559 insertions(+), 1 deletion(-)
>>  create mode 100644 src/intel/genxml/gen10.xml
>>
>> diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
>> index c568916..57eb157 100644
>> --- a/src/intel/Makefile.sources
>> +++ b/src/intel/Makefile.sources
>> @@ -117,7 +117,8 @@ GENXML_XML_FILES = \
>> genxml/gen7.xml \
>> genxml/gen75.xml \
>> genxml/gen8.xml \
>> -   genxml/gen9.xml
>> +   genxml/gen9.xml \
>> +   genxml/gen10.xml
>>
> Please add a few lines analogous to src/intel/Android.genxml.mk.
> Copy the gen9.xml hunk and s/gen9/gen10/.
>
Yes, I'll update the Android.genxml.mk.

> Thanks
> Emil
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Re: [Mesa-dev] [PATCH 02/12] i965/cnl: Add gen10.xml

[Anuj Phogat]

On Sun, Apr 16, 2017 at 8:32 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote:
> On Fri, Apr 14, 2017 at 5:35 PM, Anuj Phogat <anuj.pho...@gmail.com> wrote:
>>
>> From: Jason Ekstrand <jason.ekstr...@intel.com>
>>
>> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
>> ---
>>  src/intel/Makefile.sources |3 +-
>>  src/intel/genxml/gen10.xml | 3557
>> 
>>  2 files changed, 3559 insertions(+), 1 deletion(-)
>>  create mode 100644 src/intel/genxml/gen10.xml
>>
>> diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
>> index c568916..57eb157 100644
>> --- a/src/intel/Makefile.sources
>> +++ b/src/intel/Makefile.sources
>> @@ -117,7 +117,8 @@ GENXML_XML_FILES = \
>> genxml/gen7.xml \
>> genxml/gen75.xml \
>> genxml/gen8.xml \
>> -   genxml/gen9.xml
>> +   genxml/gen9.xml \
>> +   genxml/gen10.xml
>
>
> I don't see any patches in this series that update genX_macros.h,
> genX_pack.h, isl, blorp, anv or anything else for that matter to actually
> use the gen10 XML.  How is isl_surf_fill_state_s, for instance, not failing?
As I mentioned in the cover letter we are still using gen9 paths for isl, blorp,
anv for cannonlake. We've glxgears and many piglit tests rendering correctly
with these patches. Using isl_gen9_surf_fill_state_s is not causing issues
possibly because of little changes in surface state from gen9 to gen10.
I have patches rebased on master that replace the gen9 paths and to update
genX_macros.h, genX_pack.h. But, things are not rendering as expected.
So, I sent this series out to start the review process while I work on the
rendering issues with cnl patches on master.
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[Mesa-dev] [PATCH 06/12] i965/cnl: Modify thread count shift for VS

[Anuj Phogat]

From: Ben Widawsky 

Signed-off-by: Ben Widawsky 
---
 src/mesa/drivers/dri/i965/brw_defines.h   | 1 +
 src/mesa/drivers/dri/i965/gen8_vs_state.c | 6 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 08106c0..688ff61 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -607,6 +607,7 @@ enum brw_wrap_mode {
 /* DW5 */
 # define GEN6_VS_MAX_THREADS_SHIFT 25
 # define HSW_VS_MAX_THREADS_SHIFT  23
+# define GEN10_VS_MAX_THREADS_SHIFT 22
 # define GEN6_VS_STATISTICS_ENABLE (1 << 10)
 # define GEN6_VS_CACHE_DISABLE (1 << 1)
 # define GEN6_VS_ENABLE(1 << 0)
diff --git a/src/mesa/drivers/dri/i965/gen8_vs_state.c 
b/src/mesa/drivers/dri/i965/gen8_vs_state.c
index 7b66da4..c4ad9cd 100644
--- a/src/mesa/drivers/dri/i965/gen8_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_vs_state.c
@@ -75,7 +75,11 @@ upload_vs_state(struct brw_context *brw)
uint32_t simd8_enable =
   vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 ?
   GEN8_VS_SIMD8_ENABLE : 0;
-   OUT_BATCH(((devinfo->max_vs_threads - 1) << HSW_VS_MAX_THREADS_SHIFT) |
+
+   uint32_t threads = (devinfo->max_vs_threads - 1);
+   threads <<= brw->gen >= 10 ? GEN10_VS_MAX_THREADS_SHIFT :
+HSW_VS_MAX_THREADS_SHIFT;
+   OUT_BATCH(threads |
  GEN6_VS_STATISTICS_ENABLE |
  simd8_enable |
  GEN6_VS_ENABLE);
-- 
2.9.3

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[Mesa-dev] [PATCH 11/12] i965/cnl: Properly handle l3 configuration

[Anuj Phogat]

From: Ben Widawsky <benjamin.widaw...@intel.com>

V2: Squash the changes in one patch and rebased on master (Anuj).

Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/common/gen_l3_config.c | 43 ++--
 1 file changed, 37 insertions(+), 6 deletions(-)

diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index 4fe3503..f3e8793 100644
--- a/src/intel/common/gen_l3_config.c
+++ b/src/intel/common/gen_l3_config.c
@@ -102,6 +102,26 @@ static const struct gen_l3_config chv_l3_configs[] = {
 };
 
 /**
+ * On CNL, RO clients are merged and shared with read/write space. As a result
+ * we have fewer allocation parameters. Also, programming does not require any
+ * back scaling. Programming simply works in 2k increments and is scaled by the
+ * hardware.
+ */
+static const struct gen_l3_config cnl_l3_configs[] = {
+   /* SLM URB Rest  DC  RO */
+   {{  0, 64, 64,  0,  0 }},
+   {{  0, 64,  0, 16, 48 }},
+   {{  0, 48,  0, 16, 64 }},
+   {{  0, 32,  0,  0, 96 }},
+   {{  0, 32, 96,  0,  0 }},
+   {{  0, 32,  0, 16, 80 }},
+   {{ 32, 16, 80,  0,  0 }},
+   {{ 32, 16,  0, 64, 16 }},
+   {{ 32,  0, 96,  0,  0 }},
+   {{ 0 }}
+};
+
+/**
  * Return a zero-terminated array of validated L3 configurations for the
  * specified device.
  */
@@ -116,9 +136,11 @@ get_l3_configs(const struct gen_device_info *devinfo)
   return (devinfo->is_cherryview ? chv_l3_configs : bdw_l3_configs);
 
case 9:
-   case 10:
   return chv_l3_configs;
 
+   case 10:
+  return cnl_l3_configs;
+
default:
   unreachable("Not implemented");
}
@@ -258,13 +280,19 @@ get_l3_way_size(const struct gen_device_info *devinfo)
if (devinfo->is_baytrail)
   return 2;
 
-   else if (devinfo->gt == 1 ||
-devinfo->is_cherryview ||
-devinfo->is_broxton)
+   /* Way size is actually 6 * num_slices, because it's 2k per bank, and
+* normally 3 banks per slice. However, on CNL+ this information isn't
+* needed to setup the URB/l3 configuration. We fudge the answer here
+* and then use the scaling to fix it up later.
+*/
+   if (devinfo->gen >= 10)
+  return 2 * devinfo->l3_banks;
+
+   /* XXX: Cherryview and Broxton are always gt1 */
+   if (devinfo->gt == 1)
   return 4;
 
-   else
-  return 8 * devinfo->num_slices;
+   return 8 * devinfo->num_slices;
 }
 
 /**
@@ -274,6 +302,9 @@ get_l3_way_size(const struct gen_device_info *devinfo)
 static unsigned
 get_urb_size_scale(const struct gen_device_info *devinfo)
 {
+   if (devinfo->gen == 10)
+  return devinfo->l3_banks;
+
return (devinfo->gen >= 8 ? devinfo->num_slices : 1);
 }
 
-- 
2.9.3

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[Mesa-dev] [PATCH 10/12] i965/cnl: Update memory barrier assert

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/mesa/drivers/dri/i965/brw_program.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
b/src/mesa/drivers/dri/i965/brw_program.c
index e1f9896..ab719ad 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -292,7 +292,7 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield 
barriers)
unsigned bits = (PIPE_CONTROL_DATA_CACHE_FLUSH |
 PIPE_CONTROL_NO_WRITE |
 PIPE_CONTROL_CS_STALL);
-   assert(brw->gen >= 7 && brw->gen <= 9);
+   assert(brw->gen >= 7 && brw->gen <= 10);
 
if (barriers & (GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT |
GL_ELEMENT_ARRAY_BARRIER_BIT |
-- 
2.9.3

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[Mesa-dev] [PATCH 12/12] i965/cnl: Add CNL MOCS defines

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/mesa/drivers/dri/i965/brw_blorp.c| 7 ++-
 src/mesa/drivers/dri/i965/brw_defines.h  | 8 
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 ++
 3 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 8a6cc66..eae925f 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -94,12 +94,17 @@ brw_blorp_init(struct brw_context *brw)
   brw->blorp.exec = gen8_blorp_exec;
   break;
case 9:
-   case 10:
   brw->blorp.mocs.tex = SKL_MOCS_WB;
   brw->blorp.mocs.rb = SKL_MOCS_PTE;
   brw->blorp.mocs.vb = SKL_MOCS_WB;
   brw->blorp.exec = gen9_blorp_exec;
   break;
+   case 10:
+  brw->blorp.mocs.tex = CNL_MOCS_WB;
+  brw->blorp.mocs.rb = CNL_MOCS_PTE;
+  brw->blorp.mocs.vb = CNL_MOCS_WB;
+  brw->blorp.exec = gen9_blorp_exec;
+  break;
default:
   unreachable("Invalid gen");
}
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 688ff61..afa13b4 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1408,6 +1408,14 @@ enum brw_pixel_shader_coverage_mask_mode {
 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
 #define SKL_MOCS_PTE (1 << 1)
 
+/* CannonLake: MOCS is now an index into an array of 62 different caching
+ * configurations programmed by the kernel.
+ */
+/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
+#define CNL_MOCS_WB  (2 << 1)
+/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
+#define CNL_MOCS_PTE (1 << 1)
+
 #define MEDIA_VFE_STATE 0x7000
 /* GEN7 DW2, GEN8+ DW3 */
 # define MEDIA_VFE_STATE_MAX_THREADS_SHIFT  16
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 1d4953e..68942f7 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -64,12 +64,14 @@ uint32_t tex_mocs[] = {
[7] = GEN7_MOCS_L3,
[8] = BDW_MOCS_WB,
[9] = SKL_MOCS_WB,
+   [10] = CNL_MOCS_WB,
 };
 
 uint32_t rb_mocs[] = {
[7] = GEN7_MOCS_L3,
[8] = BDW_MOCS_PTE,
[9] = SKL_MOCS_PTE,
+   [10] = CNL_MOCS_PTE,
 };
 
 static void
-- 
2.9.3

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[Mesa-dev] [PATCH 09/12] i965/cnl: URB {VS, GS, HS, DS} sizes cannot be a multiple of 3

[Anuj Phogat]

v1: By Ben Widawsky <benjamin.widaw...@intel.com>
v2: Add the restriction for GS, HS and DS and make sure
the allocated sizes are not multiple of 3.

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
Cc: Ben Widawsky <benjamin.widaw...@intel.com>
---
 src/mesa/drivers/dri/i965/gen7_urb.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c 
b/src/mesa/drivers/dri/i965/gen7_urb.c
index 028161d..dc6826a 100644
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -194,6 +194,17 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
   entry_size[i] = prog_data[i] ? prog_data[i]->urb_entry_size : 1;
}
 
+   /* For Cannonlake:
+* Software shall not program an allocation size that specifies a size
+* that is a multiple of 3 64B (512-bit) cachelines.
+*/
+   if (brw->gen == 10) {
+  for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
+ if (entry_size[i] % 3 == 0)
+entry_size[i]++;
+  }
+   }
+
/* If we're just switching between programs with the same URB requirements,
 * skip the rest of the logic.
 */
@@ -224,6 +235,7 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
 
BEGIN_BATCH(8);
for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
+  assert(brw->gen != 10 || entry_size[i] % 3);
   OUT_BATCH((_3DSTATE_URB_VS + i) << 16 | (2 - 2));
   OUT_BATCH(entries[i] |
 ((entry_size[i] - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
-- 
2.9.3

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[Mesa-dev] [PATCH 05/12] i965/cnl: Implement depth count workaround

[Anuj Phogat]

From: Ben Widawsky 

Signed-off-by: Ben Widawsky 
---
 src/mesa/drivers/dri/i965/brw_queryobj.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c 
b/src/mesa/drivers/dri/i965/brw_queryobj.c
index 5c3ecba..d0d0589 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -111,6 +111,14 @@ brw_write_depth_count(struct brw_context *brw, 
drm_intel_bo *query_bo, int idx)
if (brw->gen == 9 && brw->gt == 4)
   flags |= PIPE_CONTROL_CS_STALL;
 
+   if (brw->gen >= 10) {
+  /* "Driver must program PIPE_CONTROL with only Depth Stall Enable bit set
+   * prior to programming a PIPE_CONTROL with Write PS Depth Count Post 
sync
+   * operation."
+   */
+  brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
+   }
+
brw_emit_pipe_control_write(brw, flags,
query_bo, idx * sizeof(uint64_t),
0, 0);
-- 
2.9.3

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[Mesa-dev] [PATCH 07/12] i965/cnl: Restore lossless compression for sRGB formats

[Anuj Phogat]

From: Ben Widawsky 

This support was removed on gen9 (it worked before then) and was brought back
for gen10.

Signed-off-by: Ben Widawsky 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 467ada5..c8014b9 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -207,7 +207,7 @@ intel_miptree_supports_non_msrt_fast_clear(struct 
brw_context *brw,
if (!brw->format_supported_as_render_target[mt->format])
   return false;
 
-   if (brw->gen >= 9) {
+   if (brw->gen == 9) {
   mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
   const uint32_t brw_format = 
brw_isl_format_for_mesa_format(linear_format);
   return isl_format_supports_ccs_e(>screen->devinfo, brw_format);
-- 
2.9.3

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[Mesa-dev] [PATCH 08/12] i965/cnl: Add a preliminary device for CNL

[Anuj Phogat]

From: Ben Widawsky <benjamin.widaw...@intel.com>

Since we've implemented all the known quirks for supporting gen10 with none of
the new features (ie. functions like Skylake), it should be safe to actually
enable the device.

v2: rebased on top of master and updated pci ids (Anuj)

Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com>
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 include/pci_ids/i965_pci_ids.h  | 12 ++
 src/intel/common/gen_device_info.c  | 59 +
 src/intel/common/gen_device_info.h  |  1 +
 src/intel/common/gen_l3_config.c|  1 +
 src/intel/compiler/brw_compiler.h   |  2 +-
 src/intel/compiler/brw_eu.c |  2 +
 src/intel/compiler/brw_eu_compact.c |  1 +
 src/intel/isl/isl.c |  2 +
 src/intel/vulkan/anv_cmd_buffer.c   |  1 +
 src/intel/vulkan/anv_device.c   |  1 +
 src/intel/vulkan/anv_entrypoints_gen.py |  1 +
 src/mesa/drivers/dri/i965/brw_blorp.c   |  1 +
 src/mesa/drivers/dri/i965/brw_draw_upload.c |  1 +
 src/mesa/drivers/dri/i965/brw_formatquery.c |  1 +
 src/mesa/drivers/dri/i965/intel_screen.c|  1 +
 15 files changed, 86 insertions(+), 1 deletion(-)

diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index 17504f5..b296359 100644
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -165,3 +165,15 @@ CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650 
(Kaby Lake GT3)")
 CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4")
 CHIPSET(0x3184, glk, "Intel(R) HD Graphics (Geminilake)")
 CHIPSET(0x3185, glk_2x6, "Intel(R) HD Graphics (Geminilake 2x6)")
+CHIPSET(0x5A49, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
+CHIPSET(0x5A4A, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
+CHIPSET(0x5A41, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
+CHIPSET(0x5A42, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
+CHIPSET(0x5A44, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
+CHIPSET(0x5A59, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)")
+CHIPSET(0x5A5A, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)")
+CHIPSET(0x5A5C, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)")
+CHIPSET(0x5A50, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
+CHIPSET(0x5A51, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
+CHIPSET(0x5A52, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
+CHIPSET(0x5A54, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
diff --git a/src/intel/common/gen_device_info.c 
b/src/intel/common/gen_device_info.c
index 47aed9d..43d6f08 100644
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -555,6 +555,65 @@ static const struct gen_device_info 
gen_device_info_glk_2x6 = {
GEN9_LP_FEATURES_2X6
 };
 
+#define GEN10_HW_INFO   \
+   .gen = 10,   \
+   .max_vs_threads = 728,   \
+   .max_gs_threads = 432,   \
+   .max_tcs_threads = 432,  \
+   .max_tes_threads = 624,  \
+   .max_wm_threads = 64 * 12,   \
+   .max_cs_threads = 56,\
+   .urb = { \
+  .size = 256,  \
+  .min_entries = {  \
+ [MESA_SHADER_VERTEX]= 64,  \
+ [MESA_SHADER_TESS_EVAL] = 34,  \
+  },\
+  .max_entries = {  \
+  [MESA_SHADER_VERTEX]   = 3936,\
+  [MESA_SHADER_TESS_CTRL]= 896, \
+  [MESA_SHADER_TESS_EVAL]= 2064,\
+  [MESA_SHADER_GEOMETRY] = 832, \
+  },\
+   }
+
+#define GEN10_FEATURES(_gt, _slices, _l3)   \
+   GEN8_FEATURES,   \
+   GEN10_HW_INFO,   \
+   .gt = _gt, .num_slices = _slices, .l3_banks = _l3
+
+static const struct gen_device_info gen_device_info_cnl_2x8 = {
+   /* GT0.5 */
+   GEN10_FEATURES(1, 1, 2)
+};
+
+static const struct gen_device_info gen_device_info_cnl_3x8 = {
+   /* GT1 */
+   GEN10_FEATURES(1, 1, 3)
+};
+
+static const struct gen_device_info gen_device_info_cnl_4x8 = {
+   /* GT 1.5 */
+   GEN10_FEATURES(1, 2, 6)
+};
+
+static const struct gen_device_info gen_device_info_cnl_5x8 = {
+   /* GT2 */
+   GEN10_FEATURES(2, 2, 6)
+};
+
+static const struct gen_device_info gen_device_info_cnl_gt1 = {
+   GEN10_FEATURES(1, 1, 3)
+};
+
+static const struct gen_d

[Mesa-dev] [PATCH 03/12] i965/cnl: Update the script generating genX_bits.h

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/genxml/gen_bits_header.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/genxml/gen_bits_header.py 
b/src/intel/genxml/gen_bits_header.py
index 808e6cf..77cd966 100644
--- a/src/intel/genxml/gen_bits_header.py
+++ b/src/intel/genxml/gen_bits_header.py
@@ -84,6 +84,7 @@ static inline uint32_t ATTRIBUTE_PURE
 ${field.token_name}(const struct gen_device_info *devinfo)
 {
switch (devinfo->gen) {
+   case 10: return ${field.bits(10)};
case 9: return ${field.bits(9)};
case 8: return ${field.bits(8)};
case 7:
@@ -151,8 +152,7 @@ class Gen(object):
 def __init__(self, z):
 # Convert potential "major.minor" string
 z = float(z)
-if z < 10:
-z *= 10
+z *= 10
 self.tenx = int(z)
 
 def __lt__(self, other):
-- 
2.9.3

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[Mesa-dev] [PATCH 00/12] Add Cannonlake support

[Anuj Phogat]

This series adds a preliminary support for Cannonlake. We
still end up using gen9 paths in many cases. My upcoming
patches will change it by creating new functions, headers
for gen10. You can also find this series at:
https://github.com/aphogat/mesa.git
branch: reviews 

Anuj Phogat (4):
  i965/cnl: Update the script generating genX_bits.h
  i965/cnl: URB {VS, GS, HS, DS} sizes cannot be a multiple of 3
  i965/cnl: Update memory barrier assert
  i965/cnl: Add CNL MOCS defines

Ben Widawsky (7):
  i965: Make feature macros gen8 based
  i965/cnl: Implement new pipe control workaround
  i965/cnl: Implement depth count workaround
  i965/cnl: Modify thread count shift for VS
  i965/cnl: Restore lossless compression for sRGB formats
  i965/cnl: Add a preliminary device for CNL
  i965/cnl: Properly handle l3 configuration

Jason Ekstrand (1):
  i965/cnl: Add gen10.xml

 include/pci_ids/i965_pci_ids.h   |   12 +
 src/intel/Makefile.sources   |3 +-
 src/intel/common/gen_device_info.c   |   72 +-
 src/intel/common/gen_device_info.h   |1 +
 src/intel/common/gen_l3_config.c |   42 +-
 src/intel/compiler/brw_compiler.h|2 +-
 src/intel/compiler/brw_eu.c  |2 +
 src/intel/compiler/brw_eu_compact.c  |1 +
 src/intel/genxml/gen10.xml   | 3557 ++
 src/intel/genxml/gen_bits_header.py  |4 +-
 src/intel/isl/isl.c  |2 +
 src/intel/vulkan/anv_cmd_buffer.c|1 +
 src/intel/vulkan/anv_device.c|1 +
 src/intel/vulkan/anv_entrypoints_gen.py  |1 +
 src/mesa/drivers/dri/i965/brw_blorp.c|6 +
 src/mesa/drivers/dri/i965/brw_defines.h  |9 +
 src/mesa/drivers/dri/i965/brw_draw_upload.c  |1 +
 src/mesa/drivers/dri/i965/brw_formatquery.c  |1 +
 src/mesa/drivers/dri/i965/brw_pipe_control.c |   18 +
 src/mesa/drivers/dri/i965/brw_program.c  |2 +-
 src/mesa/drivers/dri/i965/brw_queryobj.c |8 +
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |2 +
 src/mesa/drivers/dri/i965/gen7_urb.c |   12 +
 src/mesa/drivers/dri/i965/gen8_vs_state.c|6 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c|2 +-
 src/mesa/drivers/dri/i965/intel_screen.c |1 +
 26 files changed, 3749 insertions(+), 20 deletions(-)
 create mode 100644 src/intel/genxml/gen10.xml

-- 
2.9.3

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[Mesa-dev] [PATCH 04/12] i965/cnl: Implement new pipe control workaround

[Anuj Phogat]

From: Ben Widawsky 

GEN10 requires flushing all previous pipe controls before issuing a render
target cache flush. The docs seem to fairly explicitly say this is gen10 only.

v2: Rebased on
commit 04f74d66293222d5e1905cfb930bfa083e30463c
Author: Francisco Jerez 
Date:   Thu Jun 30 19:39:24 2016 -0700

i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.

Cc: Francisco Jerez 
Signed-off-by: Ben Widawsky 
---
 src/mesa/drivers/dri/i965/brw_pipe_control.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c 
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index b8f7406..b921fe7 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -128,6 +128,24 @@ brw_emit_pipe_control_flush(struct brw_context *brw, 
uint32_t flags)
  brw_emit_pipe_control_flush(brw, 0);
   }
 
+  if (brw->gen == 10) {
+/* Hardware workaround: CNL
+ *
+ * "Before sending a PIPE_CONTROL command with bit 12 set, SW
+ * must issue another PIPE_CONTROL with Render Target Cache
+ * Flush Enable (bit 12) = 0 and Pipe Control Flush Enable (bit
+ * 7) = 1."
+ */
+ BEGIN_BATCH(6);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
+ OUT_BATCH(PIPE_CONTROL_FLUSH_ENABLE);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+  }
+
   BEGIN_BATCH(6);
   OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
   OUT_BATCH(flags);
-- 
2.9.3

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[Mesa-dev] [PATCH 01/12] i965: Make feature macros gen8 based

[Anuj Phogat]

From: Ben Widawsky <benjamin.widaw...@intel.com>

All the "features" of the hardware are similar starting with GEN8, so remove as
much of the GEN9 uniqueness as possible. This makes implementing future gen
platforms a bit easier.

Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com>
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/common/gen_device_info.c | 13 +
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/src/intel/common/gen_device_info.c 
b/src/intel/common/gen_device_info.c
index 209b293..47aed9d 100644
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -378,15 +378,8 @@ static const struct gen_device_info gen_device_info_chv = {
}
 };
 
-#define GEN9_FEATURES   \
+#define GEN9_HW_INFO\
.gen = 9,\
-   .has_hiz_and_separate_stencil = true,\
-   .has_resource_streamer = true,   \
-   .must_use_separate_stencil = true,   \
-   .has_llc = true, \
-   .has_pln = true, \
-   .supports_simd16_3src = true,\
-   .has_surface_tile_offset = true, \
.max_vs_threads = 336,   \
.max_gs_threads = 336,   \
.max_tcs_threads = 336,  \
@@ -454,6 +447,10 @@ static const struct gen_device_info gen_device_info_chv = {
   },   \
}
 
+#define GEN9_FEATURES   \
+   GEN8_FEATURES,   \
+   GEN9_HW_INFO
+
 static const struct gen_device_info gen_device_info_skl_gt1 = {
GEN9_FEATURES, .gt = 1,
.num_slices = 1,
-- 
2.9.3

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Re: [Mesa-dev] [PATCH] mesa/main: simplify _mesa_IsRenderbuffer()

[Anuj Phogat]

On Thu, Apr 6, 2017 at 9:05 AM, Samuel Pitoiset
<samuel.pitoi...@gmail.com> wrote:
> _mesa_lookup_renderbuffer() already checks if 'id' is non-zero.
>
> Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
> ---
>  src/mesa/main/fbobject.c | 13 ++---
>  1 file changed, 6 insertions(+), 7 deletions(-)
>
> diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
> index 5048327e5e..3289f86803 100644
> --- a/src/mesa/main/fbobject.c
> +++ b/src/mesa/main/fbobject.c
> @@ -1297,15 +1297,14 @@ _mesa_test_framebuffer_completeness(struct gl_context 
> *ctx,
>  GLboolean GLAPIENTRY
>  _mesa_IsRenderbuffer(GLuint renderbuffer)
>  {
> +   struct gl_renderbuffer *rb;
> +
> GET_CURRENT_CONTEXT(ctx);
> +
> ASSERT_OUTSIDE_BEGIN_END_WITH_RETVAL(ctx, GL_FALSE);
> -   if (renderbuffer) {
> -  struct gl_renderbuffer *rb =
> - _mesa_lookup_renderbuffer(ctx, renderbuffer);
> -  if (rb != NULL && rb != )
> - return GL_TRUE;
> -   }
> -   return GL_FALSE;
> +
> +   rb = _mesa_lookup_renderbuffer(ctx, renderbuffer);
> +   return rb != NULL && rb != 
>  }
>
>
> --
> 2.12.2
>
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Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [Mesa-stable] [PATCH] i965/fs: Always provide a default LOD of 0 for TXS and TXL

[Anuj Phogat]

On Tue, Apr 4, 2017 at 3:38 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote:
> We already provide a default LOD for textureQueryLevels and texture() on
> non-fragment stages.  However, there are more cases where one is needed
> such as textureSize(gsampler2DMS*) in SPIR-V.  Instead of trying to list
> out all of the cases one at a time, just provide the default for all TXS
> and TXL operations.  This fixes a shader validation error in the new
> Sascha deferredmultisampling demo which uses textureSize(gsampler2DMS).
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100391
> Cc: Lionel Landwerlin <lionel.g.landwer...@intel.com>
> Cc: "13.0 17.0" <mesa-sta...@lists.freedesktop.org>
> ---
>  src/intel/compiler/brw_fs_nir.cpp | 18 +-
>  1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/src/intel/compiler/brw_fs_nir.cpp 
> b/src/intel/compiler/brw_fs_nir.cpp
> index bc1ccfb..23cd4b7 100644
> --- a/src/intel/compiler/brw_fs_nir.cpp
> +++ b/src/intel/compiler/brw_fs_nir.cpp
> @@ -4380,15 +4380,6 @@ fs_visitor::nir_emit_texture(const fs_builder , 
> nir_tex_instr *instr)
> srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = 
> brw_imm_d(instr->coord_components);
> srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_d(lod_components);
>
> -   if (instr->op == nir_texop_query_levels ||
> -   (instr->op == nir_texop_tex && stage != MESA_SHADER_FRAGMENT)) {
> -  /* textureQueryLevels() and texture() are implemented in terms of TXS
> -   * and TXL respectively, so we need to pass a valid LOD argument.
> -   */
> -  assert(srcs[TEX_LOGICAL_SRC_LOD].file == BAD_FILE);
> -  srcs[TEX_LOGICAL_SRC_LOD] = brw_imm_ud(0u);
> -   }
> -
> enum opcode opcode;
> switch (instr->op) {
> case nir_texop_tex:
> @@ -4455,6 +4446,15 @@ fs_visitor::nir_emit_texture(const fs_builder , 
> nir_tex_instr *instr)
>unreachable("unknown texture opcode");
> }
>
> +   /* TXS and TXL require a LOD but not everything we implement using those
> +* two opcodes provides one.  Provide a default LOD of 0.
> +*/
> +   if ((opcode == SHADER_OPCODE_TXS_LOGICAL ||
> +opcode == SHADER_OPCODE_TXL_LOGICAL) &&
> +   srcs[TEX_LOGICAL_SRC_LOD].file == BAD_FILE) {
> +  srcs[TEX_LOGICAL_SRC_LOD] = brw_imm_ud(0u);
> +   }
> +
> if (instr->op == nir_texop_tg4) {
>if (instr->component == 1 &&
>key_tex->gather_channel_quirk_mask & (1 << texture)) {
> --
> 2.5.0.400.gff86faf
>
> ___
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Looks fine to me.
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] Need to know which branch

[Anuj Phogat]

Hi,

The default branch is 'master' when you clone the Mesa git repository
and that's what we use for development. Branches other than master
are for stable releases, proof of concept and developer's choice.

-Anuj

On Wed, Mar 22, 2017 at 10:44 AM, swapnil  wrote:
> Hi,
>
> I want to know which branch should I start working I have no idea. I read
> the doc.When I check there are lots of branches. But one is specific no
> idea.
>
> Thanks
> Swapnil
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[Mesa-dev] [PATCH 2/2] i965: Delete tile resource mode code

[Anuj Phogat]

Yf/Ys tiling never got used in i965 due to not delivering
the expected performance benefits. So, this patch is deleting
this dead code in favor of adding it later in ISL when we
actually find it useful. ISL can then share this code between
vulkan and GL.

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
Cc: Kenneth Graunke <kenn...@whitecape.org>
---
 src/mesa/drivers/dri/i965/brw_defines.h   |   9 --
 src/mesa/drivers/dri/i965/brw_misc_state.c|   3 +-
 src/mesa/drivers/dri/i965/brw_tex_layout.c| 130 ---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 143 ++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  17 +--
 5 files changed, 35 insertions(+), 267 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index efed5a6..08106c0 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -354,12 +354,6 @@
 #define GEN7_SURFACE_MOCS_SHIFT 16
 #define GEN7_SURFACE_MOCS_MASK  INTEL_MASK(19, 16)
 
-#define GEN9_SURFACE_TRMODE_SHIFT  18
-#define GEN9_SURFACE_TRMODE_MASK   INTEL_MASK(19, 18)
-#define GEN9_SURFACE_TRMODE_NONE   0
-#define GEN9_SURFACE_TRMODE_TILEYF 1
-#define GEN9_SURFACE_TRMODE_TILEYS 2
-
 #define GEN9_SURFACE_MIP_TAIL_START_LOD_SHIFT  8
 #define GEN9_SURFACE_MIP_TAIL_START_LOD_MASK   INTEL_MASK(11, 8)
 
@@ -1620,9 +1614,6 @@ enum brw_pixel_shader_coverage_mask_mode {
 #define BR13_16161616  (0x4 << 24)
 #define BR13_32323232  (0x5 << 24)
 
-#define XY_FAST_SRC_TRMODE_YF(1 << 31)
-#define XY_FAST_DST_TRMODE_YF(1 << 30)
-
 /* Pipeline Statistics Counter Registers */
 #define IA_VERTICES_COUNT   0x2310
 #define IA_PRIMITIVES_COUNT 0x2318
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 1cf6b04..83c1810 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -177,7 +177,7 @@ brw_get_depthstencil_tile_masks(struct intel_mipmap_tree 
*depth_mt,
uint32_t tile_mask_x = 0, tile_mask_y = 0;
 
if (depth_mt) {
-  intel_get_tile_masks(depth_mt->tiling, depth_mt->tr_mode,
+  intel_get_tile_masks(depth_mt->tiling,
depth_mt->cpp,
_mask_x, _mask_y);
   assert(!intel_miptree_level_has_hiz(depth_mt, depth_level));
@@ -194,7 +194,6 @@ brw_get_depthstencil_tile_masks(struct intel_mipmap_tree 
*depth_mt,
   } else {
  uint32_t stencil_tile_mask_x, stencil_tile_mask_y;
  intel_get_tile_masks(stencil_mt->tiling,
-  stencil_mt->tr_mode,
   stencil_mt->cpp,
   _tile_mask_x,
   _tile_mask_y);
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c 
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 8a528e0..bfa8afa 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -40,74 +40,6 @@
 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
 
 static unsigned int
-tr_mode_horizontal_texture_alignment(const struct intel_mipmap_tree *mt)
-{
-   unsigned ret_align, divisor, multiplier_ys;
-
-   /* Values in below tables specifiy the horizontal alignment requirement
-* in elements for TRMODE_YF surface. An element is defined as a pixel in
-* uncompressed surface formats, and as a compression block in compressed
-* surface formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an
-* element is a sample.
-*/
-   const unsigned align_1d_yf[] = {4096, 2048, 1024, 512, 256};
-   const unsigned align_2d_yf[] = {64, 64, 32, 32, 16};
-   const unsigned align_3d_yf[] = {16, 8, 8, 8, 4};
-
-   assert(mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE);
-
-   /* Alignment computations below assume a power of 2 cpp. */
-   assert (mt->cpp >= 1 && mt->cpp <= 16 && _mesa_is_pow_two(mt->cpp));
-   /* Compute array index. */
-   const int i = ffs(mt->cpp) - 1;
-
-   switch(mt->target) {
-   case GL_TEXTURE_1D:
-   case GL_TEXTURE_1D_ARRAY:
-  ret_align = align_1d_yf[i];
-  multiplier_ys = 16;
-  break;
-   case GL_TEXTURE_2D:
-   case GL_TEXTURE_RECTANGLE:
-   case GL_TEXTURE_2D_ARRAY:
-   case GL_TEXTURE_CUBE_MAP:
-   case GL_TEXTURE_CUBE_MAP_ARRAY:
-   case GL_TEXTURE_2D_MULTISAMPLE:
-   case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
-  ret_align = align_2d_yf[i];
-  multiplier_ys = 4;
-  break;
-   case GL_TEXTURE_3D:
-  ret_align = align_3d_yf[i];
-  multiplier_ys = 4;
-  break;
-   default:
-  unreachable("not reached");
-   }
-
-   if (mt->tr_mode == INTEL_MIPTREE_TRMODE_YS)
-  ret_align *= multiplier_ys;
-
-   assert(_mesa_is_pow_tw

[Mesa-dev] [PATCH 1/2] i965: Delete fast copy blit code

[Anuj Phogat]

Fast copy blit was primarily added to support Yf/Ys detiling.
But, Yf/Ys tiling never got used in i965 due to not delivering
the expected performance benefits. Also, replacing legacy blits
with fast copy blit didn't help the benchmarking numbers. This
is probably due to a h/w restriction that says "start pixel for
Fast Copy blit should be on an OWord boundary". This restriction
causes many blit operations to skip fast copy blit and use legacy
blits. So, this patch is deleting this dead code in favor of
adding it later when we actually find it useful.

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
Cc: Kenneth Graunke <kenn...@whitecape.org>
---
 src/mesa/drivers/dri/i965/intel_blit.c | 231 +++--
 src/mesa/drivers/dri/i965/intel_blit.h |   2 -
 2 files changed, 48 insertions(+), 185 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
b/src/mesa/drivers/dri/i965/intel_blit.c
index 4d4ab91..ca24abe 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -39,23 +39,6 @@
 
 #define FILE_DEBUG_FLAG DEBUG_BLIT
 
-#define SET_TILING_XY_FAST_COPY_BLT(tiling, tr_mode, type)   \
-({   \
-   switch (tiling) { \
-   case I915_TILING_X:   \
-  CMD |= type ## _TILED_X;   \
-  break; \
-   case I915_TILING_Y:   \
-  if (tr_mode == INTEL_MIPTREE_TRMODE_YS)\
- CMD |= type ## _TILED_64K;  \
-  else   \
- CMD |= type ## _TILED_Y;\
-  break; \
-   default:  \
-  unreachable("not reached");\
-   } \
-})
-
 static void
 intel_miptree_set_alpha_to_one(struct brw_context *brw,
struct intel_mipmap_tree *mt,
@@ -272,11 +255,9 @@ emit_miptree_blit(struct brw_context *brw,
 reverse ? -src_mt->pitch : src_mt->pitch,
 src_mt->bo, src_mt->offset + src_offset,
 src_mt->tiling,
-src_mt->tr_mode,
 dst_mt->pitch,
 dst_mt->bo, dst_mt->offset + dst_offset,
 dst_mt->tiling,
-dst_mt->tr_mode,
 src_tile_x, src_tile_y,
 dst_tile_x, dst_tile_y,
 chunk_w, chunk_h,
@@ -472,97 +453,30 @@ alignment_valid(struct brw_context *brw, unsigned offset, 
uint32_t tiling)
return true;
 }
 
-static bool
-can_fast_copy_blit(struct brw_context *brw,
-  drm_intel_bo *src_buffer,
-   int16_t src_x, int16_t src_y,
-   uintptr_t src_offset, int32_t src_pitch,
-   uint32_t src_tiling, uint32_t src_tr_mode,
-  drm_intel_bo *dst_buffer,
-   int16_t dst_x, int16_t dst_y,
-   uintptr_t dst_offset, int32_t dst_pitch,
-   uint32_t dst_tiling, uint32_t dst_tr_mode,
-   int16_t w, int16_t h, uint32_t cpp,
-   GLenum logic_op)
-{
-   const bool dst_tiling_none = dst_tiling == I915_TILING_NONE;
-   const bool src_tiling_none = src_tiling == I915_TILING_NONE;
-
-   if (brw->gen < 9)
-  return false;
-
-   /* Enable fast copy blit only if the surfaces are Yf/Ys tiled.
-* FIXME: Based on performance data, remove this condition later to
-* enable for all types of surfaces.
-*/
-   if (src_tr_mode == INTEL_MIPTREE_TRMODE_NONE &&
-   dst_tr_mode == INTEL_MIPTREE_TRMODE_NONE)
-  return false;
-
-   if (logic_op != GL_COPY)
-  return false;
-
-   /* The start pixel for Fast Copy blit should be on an OWord boundary. */
-   if ((dst_x * cpp | src_x * cpp) & 15)
-  return false;
-
-   /* For all surface types buffers must be cacheline-aligned. */
-   if ((dst_offset | src_offset) & 63)
-  return false;
-
-   /* Color depths which are not power of 2 or greater than 128 bits are
-* not supported.
-*/
-   if (!_mesa_is_pow_two(cpp) || cpp > 16)
-  return false;
-
-   /* For Fast Copy Blits the pitch cannot be a negative number. */
-   if (src_pitch < 0 || dst_pitch < 0)
-  return false;
-
-   /* For Linear surfaces, th

Re: [Mesa-dev] [Mesa-stable] [PATCH] intel: Correct the BDW surface state size

[Anuj Phogat]

On Thu, Mar 9, 2017 at 3:35 PM, Nanley Chery <nanleych...@gmail.com> wrote:
> The PRMs state that this packet is 16 DWORDS long. Ensure that the last
> three DWORDS are zeroed as required by the hardware when allocating a
> null surface state.
>
> Cc: <mesa-sta...@lists.freedesktop.org>
> Signed-off-by: Nanley Chery <nanley.g.ch...@intel.com>
> ---
>  src/intel/isl/isl.c| 2 +-
>  src/mesa/drivers/dri/i965/gen8_surface_state.c | 5 ++---
>  2 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
> index 6eb1e93efd..b4bdf2059a 100644
> --- a/src/intel/isl/isl.c
> +++ b/src/intel/isl/isl.c
> @@ -56,7 +56,7 @@ static const struct {
> [5] = {24, 32,  4},
> [6] = {24, 32,  4},
> [7] = {32, 32,  4, 24},
> -   [8] = {52, 64, 32, 40},
> +   [8] = {64, 64, 32, 40},
> [9] = {64, 64, 32, 40},
>  };
>
> diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c 
> b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> index 501531d4ad..f868293217 100644
> --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> @@ -46,10 +46,9 @@ static uint32_t *
>  gen8_allocate_surface_state(struct brw_context *brw,
>  uint32_t *out_offset, int index)
>  {
> -   int dwords = brw->gen >= 9 ? 16 : 13;
> uint32_t *surf = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
> -  dwords * 4, 64, index, out_offset);
> -   memset(surf, 0, dwords * 4);
> +  64, 64, index, out_offset);
> +   memset(surf, 0, 64);
> return surf;
>  }
>
> --
> 2.12.0
>
> _______
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> https://lists.freedesktop.org/mailman/listinfo/mesa-stable


Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH 0/6] isl: Fix requests for exact row pitch

[Anuj Phogat]

On Mon, Mar 6, 2017 at 10:12 AM, Chad Versace <chadvers...@chromium.org> wrote:
> All callers of isl_surf_init() that set 'min_row_pitch' wanted to
> request an *exact* row pitch, as evidenced by nearby asserts, but isl
> lacked API for doing so. This series fixes that by adding a field,
> isl_surf_init_info::row_pitch.
>
> This prepares for VK_MESAX_external_image_dma_buf, which requires
> support for create VkImages with an exact, user-provided row pitch.
>
> This patch series lives at:
> git://git.kiwitree.net/~chadv/mesa
> refs/tags/chadv/review/isl-request-exact-row-pitch-v01
> gitweb: 
> http://git.kiwitree.net/cgit/~chadv/mesa/tag/?h=chadv/review/isl-request-exact-row-pitch-v01
>
> Chad Versace (6):
>   isl: Fix s/pitch/row_pitch/ in comment
>   isl: Rename isl_surf_init_info::min_pitch -> min_row_pitch
>   isl: Refactor row pitch calculation
>   isl: Let isl_surf_init's caller set the exact row pitch
>   intel: Fix requests for exact surface row pitch
>   isl: Drop unused isl_surf_init_info::min_pitch
>
>  src/intel/blorp/blorp_blit.c |  3 +-
>  src/intel/isl/isl.c  | 65 
> +++-
>  src/intel/isl/isl.h  | 10 +--
>  src/intel/vulkan/anv_blorp.c |  3 +-
>  src/intel/vulkan/anv_image.c |  2 +-
>  5 files changed, 57 insertions(+), 26 deletions(-)
>
> --
> 2.12.0
>
> ___
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LGTM. Series is:
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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[Mesa-dev] [PATCH] i965: Rename brw_format_for_mesa_format() to brw_isl_format_for_mesa_format()

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/mesa/drivers/dri/i965/brw_blorp.c|  2 +-
 src/mesa/drivers/dri/i965/brw_context.c  |  2 +-
 src/mesa/drivers/dri/i965/brw_meta_util.c|  2 +-
 src/mesa/drivers/dri/i965/brw_state.h|  2 +-
 src/mesa/drivers/dri/i965/brw_surface_formats.c  | 14 +++---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  4 ++--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c|  2 +-
 7 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 9f7ba3d..fdc9dd1 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -294,7 +294,7 @@ brw_blorp_to_isl_format(struct brw_context *brw, 
mesa_format format,
  assert(brw->format_supported_as_render_target[format]);
  return brw->render_target_format[format];
   } else {
- return brw_format_for_mesa_format(format);
+ return brw_isl_format_for_mesa_format(format);
   }
   break;
}
diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 3688ba4..42dfed0 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -205,7 +205,7 @@ intel_texture_view_requires_resolve(struct brw_context *brw,
!intel_miptree_is_lossless_compressed(brw, intel_tex->mt))
  return false;
 
-   const uint32_t brw_format = brw_format_for_mesa_format(intel_tex->_Format);
+   const uint32_t brw_format = 
brw_isl_format_for_mesa_format(intel_tex->_Format);
 
if (isl_format_supports_ccs_e(>screen->devinfo, brw_format))
   return false;
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c 
b/src/mesa/drivers/dri/i965/brw_meta_util.c
index 07a160f..cbc2ded 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
@@ -288,7 +288,7 @@ brw_is_color_fast_clear_compatible(struct brw_context *brw,
 * this case. At least on Gen9 this really does seem to cause problems.
 */
if (brw->gen >= 9 &&
-   brw_format_for_mesa_format(mt->format) !=
+   brw_isl_format_for_mesa_format(mt->format) !=
brw->render_target_format[mt->format])
   return false;
 
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 4b7e3c2..bd05b60 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -267,7 +267,7 @@ void gen4_init_vtable_surface_functions(struct brw_context 
*brw);
 uint32_t brw_get_surface_tiling_bits(uint32_t tiling);
 uint32_t brw_get_surface_num_multisamples(unsigned num_samples);
 
-uint32_t brw_format_for_mesa_format(mesa_format mesa_format);
+uint32_t brw_isl_format_for_mesa_format(mesa_format mesa_format);
 
 GLuint translate_tex_target(GLenum target);
 
diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c 
b/src/mesa/drivers/dri/i965/brw_surface_formats.c
index 706818d..7b17e11 100644
--- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
+++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
@@ -29,7 +29,7 @@
 #include "brw_defines.h"
 
 uint32_t
-brw_format_for_mesa_format(mesa_format mesa_format)
+brw_isl_format_for_mesa_format(mesa_format mesa_format)
 {
/* This table is ordered according to the enum ordering in formats.h.  We do
 * expect that enum to be extended without our explicit initialization
@@ -303,7 +303,7 @@ brw_init_surface_formats(struct brw_context *brw)
   uint32_t texture, render;
   bool is_integer = _mesa_is_format_integer_color(format);
 
-  render = texture = brw_format_for_mesa_format(format);
+  render = texture = brw_isl_format_for_mesa_format(format);
 
   /* The value of ISL_FORMAT_R32G32B32A32_FLOAT is 0, so don't skip
* it.
@@ -536,7 +536,7 @@ translate_tex_format(struct brw_context *brw,
   return ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS;
 
case MESA_FORMAT_RGBA_FLOAT32:
-  /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
+  /* The value of this ISL surface format is 0, which tricks the
* assertion below.
*/
   return ISL_FORMAT_R32G32B32A32_FLOAT;
@@ -550,7 +550,7 @@ translate_tex_format(struct brw_context *brw,
  WARN_ONCE(true, "Demoting sRGB DXT1 texture to non-sRGB\n");
  mesa_format = MESA_FORMAT_RGB_DXT1;
   }
-  return brw_format_for_mesa_format(mesa_format);
+  return brw_isl_format_for_mesa_format(mesa_format);
 
case MESA_FORMAT_RGBA_ASTC_4x4:
case MESA_FORMAT_RGBA_ASTC_5x4:
@@ -566,7 +566,7 @@ translate_tex_format(struct brw_context *brw,
case MESA_FORMAT_RGBA_ASTC_10x10:
case MESA_FORMAT_RGBA_ASTC_12x10:
case MESA_FORMAT_RGBA_ASTC_12x12: {
-  GLuint brw_fmt = brw_format_for_mesa_format(mesa_fo

Re: [Mesa-dev] [PATCH] i965: Clamp texture buffer size to GL_MAX_TEXTURE_BUFFER_SIZE.

[Anuj Phogat]

On Fri, Mar 3, 2017 at 11:32 AM, Kenneth Graunke <kenn...@whitecape.org> wrote:
> The OpenGL 4.5 specification's description of TexBuffer says:
>
> "The number of texels in the texture image is then clamped to an
>  implementation-dependent limit, the value of MAX_TEXTURE_BUFFER_SIZE."
>
> We set GL_MAX_TEXTURE_BUFFER_SIZE to 2^27.  For buffers with a byte
> element size, this is the maximum possible size we can encode in
> SURFACE_STATE.  If you bind a buffer object larger than this as a
> texture buffer object, we'll exceed that limit and hit an isl assert:
>
>assert(num_elements <= (1ull << 27));
>
> To fix this, clamp the size in bytes to MaxTextureSize / texel_size.
>
> Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
> ---
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 18 ++
>  1 file changed, 18 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index 8ffbc0a5fd5..e48b1e1d2d1 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -695,6 +695,24 @@ brw_update_buffer_texture_surface(struct gl_context *ctx,
>bo = intel_bufferobj_buffer(brw, intel_obj, tObj->BufferOffset, size);
> }
>
> +   /* The ARB_texture_buffer_specification says:
> +*
> +*"The number of texels in the buffer texture's texel array is given 
> by
> +*
> +*   floor( / ( * sizeof()),
> +*
> +* where  is the size of the buffer object, in basic
> +* machine units and  and  are the element 
> count
> +* and base data type for elements, as specified in Table X.1.  The
> +* number of texels in the texel array is then clamped to the
> +* implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
> +*
> +* We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
> +* so that when ISL divides by stride to obtain the number of texels, that
> +* texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
> +*/
> +   size = MIN2(size, ctx->Const.MaxTextureBufferSize * (unsigned) 
> texel_size);
> +
> if (brw_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
>_mesa_problem(NULL, "bad format %s for texture buffer\n",
> _mesa_get_format_name(format));
> --
> 2.11.1
>
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LGTM.
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH v1] mesa: Avoid read of uninitialized variable

[Anuj Phogat]

On Wed, Mar 1, 2017 at 2:34 PM, Robert Foss <robert.f...@collabora.com> wrote:
> The is_color_attachement variable is later read when handling two
> separate error cases, where only one of the cases results in the
> variable being initialized.
>
> This can be avoided by giving the variable a safe default value.
>
> Coverity-Id: 1398631
> Signed-off-by: Robert Foss <robert.f...@collabora.com>
> ---
>  src/mesa/main/fbobject.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
> index c8ec8e68a1..f73a009d62 100644
> --- a/src/mesa/main/fbobject.c
> +++ b/src/mesa/main/fbobject.c
> @@ -3684,7 +3684,7 @@ _mesa_get_framebuffer_attachment_parameter(struct 
> gl_context *ctx,
> GLint *params, const char *caller)
>  {
> const struct gl_renderbuffer_attachment *att;
> -   bool is_color_attachment;
> +   bool is_color_attachment = false;
> GLenum err;
>
> /* The error code for an attachment type of GL_NONE differs between APIs.
> --
> 2.11.0.453.g787f75f05
>
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH 01/24] i965: Move a couple of #defines from brw_context to brw_compiler

[Anuj Phogat]

On Tue, Feb 28, 2017 at 9:03 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote:
> ---
>  src/mesa/drivers/dri/i965/brw_compiler.h | 16 
>  src/mesa/drivers/dri/i965/brw_context.h  | 18 --
>  2 files changed, 16 insertions(+), 18 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h 
> b/src/mesa/drivers/dri/i965/brw_compiler.h
> index 3b3b7e0..297d8f8 100644
> --- a/src/mesa/drivers/dri/i965/brw_compiler.h
> +++ b/src/mesa/drivers/dri/i965/brw_compiler.h
> @@ -492,6 +492,22 @@ typedef enum
>  } brw_varying_slot;
>
>  /**
> + * We always program SF to start reading at an offset of 1 (2 varying slots)
> + * from the start of the vertex URB entry.  This causes it to skip:
> + * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
> + * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
> + */
> +#define BRW_SF_URB_ENTRY_READ_OFFSET 1
> +
> +/**
> + * Bitmask indicating which fragment shader inputs represent varyings (and
> + * hence have to be delivered to the fragment shader by the SF/SBE stage).
> + */
> +#define BRW_FS_VARYING_INPUT_MASK \
> +   (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
> +~VARYING_BIT_POS & ~VARYING_BIT_FACE)
> +
> +/**
>   * Data structure recording the relationship between the gl_varying_slot enum
>   * and "slots" within the vertex URB entry (VUE).  A "slot" is defined as a
>   * single octaword within the VUE (128 bits).
> diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
> b/src/mesa/drivers/dri/i965/brw_context.h
> index 7ff7b74..c9a931c 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.h
> +++ b/src/mesa/drivers/dri/i965/brw_context.h
> @@ -328,15 +328,6 @@ struct brw_program {
>  };
>
>
> -/**
> - * Bitmask indicating which fragment shader inputs represent varyings (and
> - * hence have to be delivered to the fragment shader by the SF/SBE stage).
> - */
> -#define BRW_FS_VARYING_INPUT_MASK \
> -   (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
> -~VARYING_BIT_POS & ~VARYING_BIT_FACE)
> -
> -
>  struct brw_sf_prog_data {
> GLuint urb_read_length;
> GLuint total_grf;
> @@ -351,15 +342,6 @@ struct brw_sf_prog_data {
>  };
>
>
> -/**
> - * We always program SF to start reading at an offset of 1 (2 varying slots)
> - * from the start of the vertex URB entry.  This causes it to skip:
> - * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
> - * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
> - */
> -#define BRW_SF_URB_ENTRY_READ_OFFSET 1
> -
> -
>  struct brw_clip_prog_data {
> GLuint curb_read_length;/* user planes? */
> GLuint clip_mode;
> --
> 2.5.0.400.gff86faf
>
> ___
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Patches 1-7 are:
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>

I noticed that Matt and Ken have already finished reviewing this series.
So, I won't review rest of the series.
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Re: [Mesa-dev] [PATCH 05/24] i965: Move assign_common_binding_table_offsets to brw_program

[Anuj Phogat]

On Tue, Feb 28, 2017 at 9:03 PM, Jason Ekstrand  wrote:
> This isn't used by Vulkan and is specific to the way the GL driver
> works.  There's no reason to have it in common compiler code.  Also, it
> relies on BRW_MAX_* defines which are defined in brw_context.h
> ---
>  src/mesa/drivers/dri/i965/brw_program.c  | 87 
> 
>  src/mesa/drivers/dri/i965/brw_program.h  |  6 +++
>  src/mesa/drivers/dri/i965/brw_shader.cpp | 87 
> 
>  src/mesa/drivers/dri/i965/brw_shader.h   |  6 ---
>  4 files changed, 93 insertions(+), 93 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
> b/src/mesa/drivers/dri/i965/brw_program.c
> index 673dc502..fdd940d 100644
> --- a/src/mesa/drivers/dri/i965/brw_program.c
> +++ b/src/mesa/drivers/dri/i965/brw_program.c
> @@ -706,3 +706,90 @@ brw_setup_tex_for_precompile(struct brw_context *brw,
>}
> }
>  }
> +
> +/**
> + * Sets up the starting offsets for the groups of binding table entries
> + * commong to all pipeline stages.
s/commong/common
> + *
> + * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that 
> they're
> + * unused but also make sure that addition of small offsets to them will
> + * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
> + */
> +uint32_t
> +brw_assign_common_binding_table_offsets(const struct gen_device_info 
> *devinfo,
> +const struct gl_program *prog,
> +struct brw_stage_prog_data 
> *stage_prog_data,
> +uint32_t next_binding_table_offset)
> +{
> +   int num_textures = util_last_bit(prog->SamplersUsed);
> +
> +   stage_prog_data->binding_table.texture_start = next_binding_table_offset;
> +   next_binding_table_offset += num_textures;
> +
> +   if (prog->info.num_ubos) {
> +  assert(prog->info.num_ubos <= BRW_MAX_UBO);
> +  stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
> +  next_binding_table_offset += prog->info.num_ubos;
> +   } else {
> +  stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
> +   }
> +
> +   if (prog->info.num_ssbos) {
> +  assert(prog->info.num_ssbos <= BRW_MAX_SSBO);
> +  stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
> +  next_binding_table_offset += prog->info.num_ssbos;
> +   } else {
> +  stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
> +   }
> +
> +   if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
> +  stage_prog_data->binding_table.shader_time_start = 
> next_binding_table_offset;
> +  next_binding_table_offset++;
> +   } else {
> +  stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
> +   }
> +
> +   if (prog->nir->info->uses_texture_gather) {
> +  if (devinfo->gen >= 8) {
> + stage_prog_data->binding_table.gather_texture_start =
> +stage_prog_data->binding_table.texture_start;
> +  } else {
> + stage_prog_data->binding_table.gather_texture_start = 
> next_binding_table_offset;
> + next_binding_table_offset += num_textures;
> +  }
> +   } else {
> +  stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
> +   }
> +
> +   if (prog->info.num_abos) {
> +  stage_prog_data->binding_table.abo_start = next_binding_table_offset;
> +  next_binding_table_offset += prog->info.num_abos;
> +   } else {
> +  stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
> +   }
> +
> +   if (prog->info.num_images) {
> +  stage_prog_data->binding_table.image_start = next_binding_table_offset;
> +  next_binding_table_offset += prog->info.num_images;
> +   } else {
> +  stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
> +   }
> +
> +   /* This may or may not be used depending on how the compile goes. */
> +   stage_prog_data->binding_table.pull_constants_start = 
> next_binding_table_offset;
> +   next_binding_table_offset++;
> +
> +   /* Plane 0 is just the regular texture section */
> +   stage_prog_data->binding_table.plane_start[0] = 
> stage_prog_data->binding_table.texture_start;
> +
> +   stage_prog_data->binding_table.plane_start[1] = next_binding_table_offset;
> +   next_binding_table_offset += num_textures;
> +
> +   stage_prog_data->binding_table.plane_start[2] = next_binding_table_offset;
> +   next_binding_table_offset += num_textures;
> +
> +   /* prog_data->base.binding_table.size will be set by 
> brw_mark_surface_used. */
> +
> +   assert(next_binding_table_offset <= BRW_MAX_SURFACES);
> +   return next_binding_table_offset;
> +}
> diff --git a/src/mesa/drivers/dri/i965/brw_program.h 
> b/src/mesa/drivers/dri/i965/brw_program.h
> index 6eda165..56dca1f 100644
> --- a/src/mesa/drivers/dri/i965/brw_program.h
> +++ b/src/mesa/drivers/dri/i965/brw_program.h
> @@ -50,6 +50,12 @@ bool brw_debug_recompile_sampler_key(struct brw_context 
> *brw,
>   

Re: [Mesa-dev] [PATCH] i965: Move intel_debug.h to intel/common/gen_debug.h

[Anuj Phogat]

dri/i965/brw_vec4_generator.cpp
> index 83f5711..abf522a 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> @@ -24,7 +24,7 @@
>  #include "brw_cfg.h"
>  #include "brw_eu.h"
>  #include "brw_program.h"
> -#include "intel_debug.h"
> +#include "common/gen_debug.h"
>
>  using namespace brw;
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
> index 3a8bc77..4a8b5be 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
> @@ -31,7 +31,7 @@
>  #include "gen6_gs_visitor.h"
>  #include "brw_fs.h"
>  #include "brw_nir.h"
> -#include "intel_debug.h"
> +#include "common/gen_debug.h"
>
>  namespace brw {
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
> index d27074c..d4a647d 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
> @@ -30,7 +30,7 @@
>  #include "brw_nir.h"
>  #include "brw_vec4_tcs.h"
>  #include "brw_fs.h"
> -#include "intel_debug.h"
> +#include "common/gen_debug.h"
>
>  namespace brw {
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp
> index 0c05ab0..bcf9a87 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp
> @@ -29,7 +29,7 @@
>
>  #include "brw_vec4_tes.h"
>  #include "brw_cfg.h"
> -#include "intel_debug.h"
> +#include "common/gen_debug.h"
>
>  namespace brw {
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp
> index a80a61b..0cec779 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp
> @@ -23,7 +23,7 @@
>
>
>  #include "brw_vec4_vs.h"
> -#include "intel_debug.h"
> +#include "common/gen_debug.h"
>
>  namespace brw {
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vue_map.c 
> b/src/mesa/drivers/dri/i965/brw_vue_map.c
> index 8912068..e14cba8 100644
> --- a/src/mesa/drivers/dri/i965/brw_vue_map.c
> +++ b/src/mesa/drivers/dri/i965/brw_vue_map.c
> @@ -41,7 +41,7 @@
>
>
>  #include "brw_compiler.h"
> -#include "intel_debug.h"
> +#include "common/gen_debug.h"
>
>  static inline void
>  assign_vue_slot(struct brw_vue_map *vue_map, int varying, int slot)
> diff --git a/src/mesa/drivers/dri/i965/intel_asm_annotation.c 
> b/src/mesa/drivers/dri/i965/intel_asm_annotation.c
> index bb24e5e..1f3b784 100644
> --- a/src/mesa/drivers/dri/i965/intel_asm_annotation.c
> +++ b/src/mesa/drivers/dri/i965/intel_asm_annotation.c
> @@ -23,7 +23,7 @@
>
>  #include "brw_cfg.h"
>  #include "brw_eu.h"
> -#include "intel_debug.h"
> +#include "common/gen_debug.h"
>  #include "intel_asm_annotation.h"
>  #include "compiler/nir/nir.h"
>
> --
> 2.5.0.400.gff86faf
>
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> https://lists.freedesktop.org/mailman/listinfo/mesa-dev

With the suggested change:
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH] glsl: add has_shader_image_load_store()

[Anuj Phogat]

On Thu, Feb 23, 2017 at 10:04 AM, Samuel Pitoiset
<samuel.pitoi...@gmail.com> wrote:
> Preliminary work for ARB_bindless_texture which can interact
> with ARB_shader_image_load_store.
>
> Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
> ---
>  src/compiler/glsl/builtin_variables.cpp | 3 +--
>  src/compiler/glsl/glsl_parser.yy| 3 +--
>  src/compiler/glsl/glsl_parser_extras.h  | 5 +
>  3 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/src/compiler/glsl/builtin_variables.cpp 
> b/src/compiler/glsl/builtin_variables.cpp
> index db8418bbc7..fc0443e715 100644
> --- a/src/compiler/glsl/builtin_variables.cpp
> +++ b/src/compiler/glsl/builtin_variables.cpp
> @@ -840,8 +840,7 @@ builtin_variable_generator::generate_constants()
>  state->Const.MaxTransformFeedbackInterleavedComponents);
> }
>
> -   if (state->is_version(420, 310) ||
> -   state->ARB_shader_image_load_store_enable) {
> +   if (state->has_shader_image_load_store()) {
>add_const("gl_MaxImageUnits",
>  state->Const.MaxImageUnits);
>add_const("gl_MaxVertexImageUniforms",
> diff --git a/src/compiler/glsl/glsl_parser.yy 
> b/src/compiler/glsl/glsl_parser.yy
> index fd7edb28e7..d703f8 100644
> --- a/src/compiler/glsl/glsl_parser.yy
> +++ b/src/compiler/glsl/glsl_parser.yy
> @@ -1322,8 +1322,7 @@ layout_qualifier_id:
>}
>
>/* Layout qualifiers for ARB_shader_image_load_store. */
> -  if (state->ARB_shader_image_load_store_enable ||
> -  state->is_version(420, 310)) {
> +  if (state->has_shader_image_load_store()) {
>   if (!$$.flags.i) {
>  static const struct {
> const char *name;
> diff --git a/src/compiler/glsl/glsl_parser_extras.h 
> b/src/compiler/glsl/glsl_parser_extras.h
> index 8feef8cbcd..01acbb62e3 100644
> --- a/src/compiler/glsl/glsl_parser_extras.h
> +++ b/src/compiler/glsl/glsl_parser_extras.h
> @@ -330,6 +330,11 @@ struct _mesa_glsl_parse_state {
>   is_version(400, 320);
> }
>
> +   bool has_shader_image_load_store() const
> +   {
> +  return ARB_shader_image_load_store_enable || is_version(420, 310);
> +   }
> +
> void process_version_directive(YYLTYPE *locp, int version,
>    const char *ident);
>
> --
> 2.11.1
>
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Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH] mesa: Use _mesa_has_OES_geometry_shader() when validating draws

[Anuj Phogat]

On Thu, Feb 23, 2017 at 12:05 AM, Tomasz Figa <tf...@chromium.org> wrote:
> In validate_DrawElements_common() we need to check for OES_geometry_shader
> extension to determine if we should fail if transform feedback is
> unpaused. However current code reads ctx->Extensions.OES_geometry_shader
> directly, which does not take context version into account. This means
> that if the context is GLES 3.0, which makes the OES_geometry_shader
> inapplicable, we would not validate the draw properly. To fix it, let's
> replace the check with a call to _mesa_has_OES_geometry_shader().
>
> Fixes following dEQP tests on i965 with a GLES 3.0 context:
>
> dEQP-GLES3.functional.negative_api.vertex_array#draw_elements
> dEQP-GLES3.functional.negative_api.vertex_array#draw_elements_incomplete_primitive
> dEQP-GLES3.functional.negative_api.vertex_array#draw_elements_instanced
> dEQP-GLES3.functional.negative_api.vertex_array#draw_elements_instanced_incomplete_primitive
> dEQP-GLES3.functional.negative_api.vertex_array#draw_range_elements
> dEQP-GLES3.functional.negative_api.vertex_array#draw_range_elements_incomplete_primitive
>
> Change-Id: Iebc960b479fcd5f6c2b1501cb3e7798b575e6c4d
> Signed-off-by: Tomasz Figa <tf...@chromium.org>
> ---
>  src/mesa/main/api_validate.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/main/api_validate.c b/src/mesa/main/api_validate.c
> index 1e8a714067..184bf143ed 100644
> --- a/src/mesa/main/api_validate.c
> +++ b/src/mesa/main/api_validate.c
> @@ -664,7 +664,8 @@ validate_DrawElements_common(struct gl_context *ctx,
>  * to have been overlooked.  The body of the spec only explicitly allows
>  * the indirect versions.
>  */
> -   if (_mesa_is_gles3(ctx) && !ctx->Extensions.OES_geometry_shader &&
> +   if (_mesa_is_gles3(ctx) &&
> +   !_mesa_has_OES_geometry_shader(ctx) &&
> _mesa_is_xfb_active_and_unpaused(ctx)) {
>_mesa_error(ctx, GL_INVALID_OPERATION,
>"%s(transform feedback active)", caller);
> --
> 2.11.0.483.g087da7b7c-goog
>
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[Mesa-dev] [PATCH V2] mesa: Add EXT_frag_depth bits and enable it on all drivers

[Anuj Phogat]

Passes the newly added piglit test for this extension on i965.

V2: Fix comments by Ilia.

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/compiler/glsl/builtin_variables.cpp  | 3 +++
 src/compiler/glsl/glsl_parser_extras.cpp | 1 +
 src/compiler/glsl/glsl_parser_extras.h   | 2 ++
 src/mesa/main/extensions_table.h | 1 +
 4 files changed, 7 insertions(+)

diff --git a/src/compiler/glsl/builtin_variables.cpp 
b/src/compiler/glsl/builtin_variables.cpp
index 4eb275e..deab4f3 100644
--- a/src/compiler/glsl/builtin_variables.cpp
+++ b/src/compiler/glsl/builtin_variables.cpp
@@ -1193,6 +1193,9 @@ builtin_variable_generator::generate_fs_special_vars()
if (state->is_version(110, 300))
   add_output(FRAG_RESULT_DEPTH, float_t, "gl_FragDepth");
 
+   if (state->EXT_frag_depth_enable)
+  add_output(FRAG_RESULT_DEPTH, float_t, "gl_FragDepthEXT");
+
if (state->ARB_shader_stencil_export_enable) {
   ir_variable *const var =
  add_output(FRAG_RESULT_STENCIL, int_t, "gl_FragStencilRefARB");
diff --git a/src/compiler/glsl/glsl_parser_extras.cpp 
b/src/compiler/glsl/glsl_parser_extras.cpp
index e16d543..50b067d 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -677,6 +677,7 @@ static const _mesa_glsl_extension 
_mesa_glsl_supported_extensions[] = {
EXT(AMD_vertex_shader_viewport_index),
EXT(ANDROID_extension_pack_es31a),
EXT(EXT_blend_func_extended),
+   EXT(EXT_frag_depth),
EXT(EXT_draw_buffers),
EXT(EXT_clip_cull_distance),
EXT(EXT_geometry_point_size),
diff --git a/src/compiler/glsl/glsl_parser_extras.h 
b/src/compiler/glsl/glsl_parser_extras.h
index 424cab5..3f3adec 100644
--- a/src/compiler/glsl/glsl_parser_extras.h
+++ b/src/compiler/glsl/glsl_parser_extras.h
@@ -738,6 +738,8 @@ struct _mesa_glsl_parse_state {
bool EXT_blend_func_extended_warn;
bool EXT_clip_cull_distance_enable;
bool EXT_clip_cull_distance_warn;
+   bool EXT_frag_depth_enable;
+   bool EXT_frag_depth_warn;
bool EXT_draw_buffers_enable;
bool EXT_draw_buffers_warn;
bool EXT_geometry_point_size_enable;
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index 75f432b..7ea56c8 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -211,6 +211,7 @@ EXT(EXT_draw_elements_base_vertex   , 
ARB_draw_elements_base_vertex
 EXT(EXT_draw_instanced  , ARB_draw_instanced   
  , GLL, GLC,  x ,  x , 2006)
 EXT(EXT_draw_range_elements , dummy_true   
  , GLL,  x ,  x ,  x , 1997)
 EXT(EXT_fog_coord   , dummy_true   
  , GLL,  x ,  x ,  x , 1999)
+EXT(EXT_frag_depth  , dummy_true   
  ,  x ,  x ,  x , ES2, 2010)
 EXT(EXT_framebuffer_blit, dummy_true   
  , GLL, GLC,  x ,  x , 2005)
 EXT(EXT_framebuffer_multisample , EXT_framebuffer_multisample  
  , GLL, GLC,  x ,  x , 2005)
 EXT(EXT_framebuffer_multisample_blit_scaled , 
EXT_framebuffer_multisample_blit_scaled, GLL, GLC,  x ,  x , 2011)
-- 
2.9.3

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Re: [Mesa-dev] [PATCH] mesa: Add EXT_frag_depth bits and enable it on all drivers

[Anuj Phogat]

On Fri, Feb 10, 2017 at 1:38 PM, Ilia Mirkin <imir...@alum.mit.edu> wrote:
> On Fri, Feb 10, 2017 at 4:36 PM, Anuj Phogat <anuj.pho...@gmail.com> wrote:
>> On Fri, Feb 10, 2017 at 1:21 PM, Ilia Mirkin <imir...@alum.mit.edu> wrote:
>>> On Fri, Feb 10, 2017 at 4:15 PM, Anuj Phogat <anuj.pho...@gmail.com> wrote:
>>>> Passes the newly added piglit test for this extension on i965.
>>>>
>>>> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
>>>> ---
>>>> A quick look at other drivers didn't show any issues with
>>>> this new extension. Let me know if you think it won't work
>>>> for any driver.
>>>
>>> Out of curiousity, why do you need this?
>>>
>> I'm not aware of any application using it. It's just another ES
>> extension which can be enabled on Mesa with almost zero
>> efforts.
>>>> ---
>>>>  docs/features.txt| 3 +++
>>>>  src/compiler/glsl/builtin_variables.cpp  | 3 +++
>>>>  src/compiler/glsl/glsl_parser_extras.cpp | 1 +
>>>>  src/compiler/glsl/glsl_parser_extras.h   | 2 ++
>>>>  src/mesa/main/extensions_table.h | 1 +
>>>>  src/mesa/main/mtypes.h   | 1 +
>>>>  6 files changed, 11 insertions(+)
>>>>
>>>> diff --git a/docs/features.txt b/docs/features.txt
>>>> index 2f2d41d..aab35ac 100644
>>>> --- a/docs/features.txt
>>>> +++ b/docs/features.txt
>>>> @@ -221,6 +221,9 @@ GL 4.5, GLSL 4.50 -- all DONE: nvc0, radeonsi
>>>>GL_KHR_robustness DONE (i965)
>>>>GL_EXT_shader_integer_mix DONE (all drivers 
>>>> that support GLSL)
>>>>
>>>> +These are the extensions cherry-picked to make GLES 3.0
>>>> +  GL_EXT_frag_depth DONE (all drivers 
>>>> that support GLSL ES 1.00)
>>>
>>> Not sure what such a partial list gets you...
>>>
>> Added to document the extension support. I'll drop it in favor of doing it
>> sometime later with rest of gles 3.0 extensions.
>>
>>>> +
>>>>  These are the extensions cherry-picked to make GLES 3.1
>>>>  GLES3.1, GLSL ES 3.1 -- all DONE: i965/hsw+, nvc0, radeonsi
>>>>
>>>> diff --git a/src/compiler/glsl/builtin_variables.cpp 
>>>> b/src/compiler/glsl/builtin_variables.cpp
>>>> index 4eb275e..8f054c7 100644
>>>> --- a/src/compiler/glsl/builtin_variables.cpp
>>>> +++ b/src/compiler/glsl/builtin_variables.cpp
>>>> @@ -1193,6 +1193,9 @@ 
>>>> builtin_variable_generator::generate_fs_special_vars()
>>>> if (state->is_version(110, 300))
>>>>add_output(FRAG_RESULT_DEPTH, float_t, "gl_FragDepth");
>>>>
>>>> +   if (state->es_shader && state->language_version == 100 && 
>>>> state->EXT_frag_depth_enable)
>>>> +  add_output(FRAG_RESULT_DEPTH, float_t, "gl_FragDepthEXT");
>>>
>>> So wait, if I have a #version 300 es shader, and #extension
>>> GL_EXT_frag_depth: enable, I can't use gl_FragDepthEXT? Where is that
>>> specified?
>>>
>> You're right. I'll modify the condition to use state->language_version >= 100
>
> I think you just want
>
> if (state->EXT_frag_depth_enable)
>
> and nothing else...
>
Yes. I realized it after replying you. Thanks.
>>>> +
>>>> if (state->ARB_shader_stencil_export_enable) {
>>>>ir_variable *const var =
>>>>   add_output(FRAG_RESULT_STENCIL, int_t, "gl_FragStencilRefARB");
>>>> diff --git a/src/compiler/glsl/glsl_parser_extras.cpp 
>>>> b/src/compiler/glsl/glsl_parser_extras.cpp
>>>> index e16d543..50b067d 100644
>>>> --- a/src/compiler/glsl/glsl_parser_extras.cpp
>>>> +++ b/src/compiler/glsl/glsl_parser_extras.cpp
>>>> @@ -677,6 +677,7 @@ static const _mesa_glsl_extension 
>>>> _mesa_glsl_supported_extensions[] = {
>>>> EXT(AMD_vertex_shader_viewport_index),
>>>> EXT(ANDROID_extension_pack_es31a),
>>>> EXT(EXT_blend_func_extended),
>>>> +   EXT(EXT_frag_depth),
>>>> EXT(EXT_draw_buffers),
>>>> EXT(EXT_clip_cull_distance),
>>>> EXT(EXT_geometry_point_size),
>>>> diff --git a/src/compiler/glsl/glsl_parser_extras

Re: [Mesa-dev] [PATCH] mesa: Add EXT_frag_depth bits and enable it on all drivers

[Anuj Phogat]

On Fri, Feb 10, 2017 at 1:21 PM, Ilia Mirkin <imir...@alum.mit.edu> wrote:
> On Fri, Feb 10, 2017 at 4:15 PM, Anuj Phogat <anuj.pho...@gmail.com> wrote:
>> Passes the newly added piglit test for this extension on i965.
>>
>> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
>> ---
>> A quick look at other drivers didn't show any issues with
>> this new extension. Let me know if you think it won't work
>> for any driver.
>
> Out of curiousity, why do you need this?
>
I'm not aware of any application using it. It's just another ES
extension which can be enabled on Mesa with almost zero
efforts.
>> ---
>>  docs/features.txt| 3 +++
>>  src/compiler/glsl/builtin_variables.cpp  | 3 +++
>>  src/compiler/glsl/glsl_parser_extras.cpp | 1 +
>>  src/compiler/glsl/glsl_parser_extras.h   | 2 ++
>>  src/mesa/main/extensions_table.h | 1 +
>>  src/mesa/main/mtypes.h   | 1 +
>>  6 files changed, 11 insertions(+)
>>
>> diff --git a/docs/features.txt b/docs/features.txt
>> index 2f2d41d..aab35ac 100644
>> --- a/docs/features.txt
>> +++ b/docs/features.txt
>> @@ -221,6 +221,9 @@ GL 4.5, GLSL 4.50 -- all DONE: nvc0, radeonsi
>>GL_KHR_robustness DONE (i965)
>>GL_EXT_shader_integer_mix DONE (all drivers 
>> that support GLSL)
>>
>> +These are the extensions cherry-picked to make GLES 3.0
>> +  GL_EXT_frag_depth DONE (all drivers 
>> that support GLSL ES 1.00)
>
> Not sure what such a partial list gets you...
>
Added to document the extension support. I'll drop it in favor of doing it
sometime later with rest of gles 3.0 extensions.

>> +
>>  These are the extensions cherry-picked to make GLES 3.1
>>  GLES3.1, GLSL ES 3.1 -- all DONE: i965/hsw+, nvc0, radeonsi
>>
>> diff --git a/src/compiler/glsl/builtin_variables.cpp 
>> b/src/compiler/glsl/builtin_variables.cpp
>> index 4eb275e..8f054c7 100644
>> --- a/src/compiler/glsl/builtin_variables.cpp
>> +++ b/src/compiler/glsl/builtin_variables.cpp
>> @@ -1193,6 +1193,9 @@ builtin_variable_generator::generate_fs_special_vars()
>> if (state->is_version(110, 300))
>>add_output(FRAG_RESULT_DEPTH, float_t, "gl_FragDepth");
>>
>> +   if (state->es_shader && state->language_version == 100 && 
>> state->EXT_frag_depth_enable)
>> +  add_output(FRAG_RESULT_DEPTH, float_t, "gl_FragDepthEXT");
>
> So wait, if I have a #version 300 es shader, and #extension
> GL_EXT_frag_depth: enable, I can't use gl_FragDepthEXT? Where is that
> specified?
>
You're right. I'll modify the condition to use state->language_version >= 100
>> +
>> if (state->ARB_shader_stencil_export_enable) {
>>ir_variable *const var =
>>   add_output(FRAG_RESULT_STENCIL, int_t, "gl_FragStencilRefARB");
>> diff --git a/src/compiler/glsl/glsl_parser_extras.cpp 
>> b/src/compiler/glsl/glsl_parser_extras.cpp
>> index e16d543..50b067d 100644
>> --- a/src/compiler/glsl/glsl_parser_extras.cpp
>> +++ b/src/compiler/glsl/glsl_parser_extras.cpp
>> @@ -677,6 +677,7 @@ static const _mesa_glsl_extension 
>> _mesa_glsl_supported_extensions[] = {
>> EXT(AMD_vertex_shader_viewport_index),
>> EXT(ANDROID_extension_pack_es31a),
>> EXT(EXT_blend_func_extended),
>> +   EXT(EXT_frag_depth),
>> EXT(EXT_draw_buffers),
>> EXT(EXT_clip_cull_distance),
>> EXT(EXT_geometry_point_size),
>> diff --git a/src/compiler/glsl/glsl_parser_extras.h 
>> b/src/compiler/glsl/glsl_parser_extras.h
>> index 424cab5..3f3adec 100644
>> --- a/src/compiler/glsl/glsl_parser_extras.h
>> +++ b/src/compiler/glsl/glsl_parser_extras.h
>> @@ -738,6 +738,8 @@ struct _mesa_glsl_parse_state {
>> bool EXT_blend_func_extended_warn;
>> bool EXT_clip_cull_distance_enable;
>> bool EXT_clip_cull_distance_warn;
>> +   bool EXT_frag_depth_enable;
>> +   bool EXT_frag_depth_warn;
>> bool EXT_draw_buffers_enable;
>> bool EXT_draw_buffers_warn;
>> bool EXT_geometry_point_size_enable;
>> diff --git a/src/mesa/main/extensions_table.h 
>> b/src/mesa/main/extensions_table.h
>> index 75f432b..7ea56c8 100644
>> --- a/src/mesa/main/extensions_table.h
>> +++ b/src/mesa/main/extensions_table.h
>> @@ -211,6 +211,7 @@ EXT(EXT_draw_elements_base_vertex   , 
>> ARB_draw_elements_base_vertex
>>  EXT(EXT_draw_instanced  , ARB_dra

[Mesa-dev] [PATCH] mesa: Add EXT_frag_depth bits and enable it on all drivers

[Anuj Phogat]

Passes the newly added piglit test for this extension on i965.

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
A quick look at other drivers didn't show any issues with
this new extension. Let me know if you think it won't work
for any driver.
---
 docs/features.txt| 3 +++
 src/compiler/glsl/builtin_variables.cpp  | 3 +++
 src/compiler/glsl/glsl_parser_extras.cpp | 1 +
 src/compiler/glsl/glsl_parser_extras.h   | 2 ++
 src/mesa/main/extensions_table.h | 1 +
 src/mesa/main/mtypes.h   | 1 +
 6 files changed, 11 insertions(+)

diff --git a/docs/features.txt b/docs/features.txt
index 2f2d41d..aab35ac 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -221,6 +221,9 @@ GL 4.5, GLSL 4.50 -- all DONE: nvc0, radeonsi
   GL_KHR_robustness DONE (i965)
   GL_EXT_shader_integer_mix DONE (all drivers that 
support GLSL)
 
+These are the extensions cherry-picked to make GLES 3.0
+  GL_EXT_frag_depth DONE (all drivers that 
support GLSL ES 1.00)
+
 These are the extensions cherry-picked to make GLES 3.1
 GLES3.1, GLSL ES 3.1 -- all DONE: i965/hsw+, nvc0, radeonsi
 
diff --git a/src/compiler/glsl/builtin_variables.cpp 
b/src/compiler/glsl/builtin_variables.cpp
index 4eb275e..8f054c7 100644
--- a/src/compiler/glsl/builtin_variables.cpp
+++ b/src/compiler/glsl/builtin_variables.cpp
@@ -1193,6 +1193,9 @@ builtin_variable_generator::generate_fs_special_vars()
if (state->is_version(110, 300))
   add_output(FRAG_RESULT_DEPTH, float_t, "gl_FragDepth");
 
+   if (state->es_shader && state->language_version == 100 && 
state->EXT_frag_depth_enable)
+  add_output(FRAG_RESULT_DEPTH, float_t, "gl_FragDepthEXT");
+
if (state->ARB_shader_stencil_export_enable) {
   ir_variable *const var =
  add_output(FRAG_RESULT_STENCIL, int_t, "gl_FragStencilRefARB");
diff --git a/src/compiler/glsl/glsl_parser_extras.cpp 
b/src/compiler/glsl/glsl_parser_extras.cpp
index e16d543..50b067d 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -677,6 +677,7 @@ static const _mesa_glsl_extension 
_mesa_glsl_supported_extensions[] = {
EXT(AMD_vertex_shader_viewport_index),
EXT(ANDROID_extension_pack_es31a),
EXT(EXT_blend_func_extended),
+   EXT(EXT_frag_depth),
EXT(EXT_draw_buffers),
EXT(EXT_clip_cull_distance),
EXT(EXT_geometry_point_size),
diff --git a/src/compiler/glsl/glsl_parser_extras.h 
b/src/compiler/glsl/glsl_parser_extras.h
index 424cab5..3f3adec 100644
--- a/src/compiler/glsl/glsl_parser_extras.h
+++ b/src/compiler/glsl/glsl_parser_extras.h
@@ -738,6 +738,8 @@ struct _mesa_glsl_parse_state {
bool EXT_blend_func_extended_warn;
bool EXT_clip_cull_distance_enable;
bool EXT_clip_cull_distance_warn;
+   bool EXT_frag_depth_enable;
+   bool EXT_frag_depth_warn;
bool EXT_draw_buffers_enable;
bool EXT_draw_buffers_warn;
bool EXT_geometry_point_size_enable;
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index 75f432b..7ea56c8 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -211,6 +211,7 @@ EXT(EXT_draw_elements_base_vertex   , 
ARB_draw_elements_base_vertex
 EXT(EXT_draw_instanced  , ARB_draw_instanced   
  , GLL, GLC,  x ,  x , 2006)
 EXT(EXT_draw_range_elements , dummy_true   
  , GLL,  x ,  x ,  x , 1997)
 EXT(EXT_fog_coord   , dummy_true   
  , GLL,  x ,  x ,  x , 1999)
+EXT(EXT_frag_depth  , dummy_true   
  ,  x ,  x ,  x , ES2, 2010)
 EXT(EXT_framebuffer_blit, dummy_true   
  , GLL, GLC,  x ,  x , 2005)
 EXT(EXT_framebuffer_multisample , EXT_framebuffer_multisample  
  , GLL, GLC,  x ,  x , 2005)
 EXT(EXT_framebuffer_multisample_blit_scaled , 
EXT_framebuffer_multisample_blit_scaled, GLL, GLC,  x ,  x , 2011)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index a845a39..770bf72 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -3886,6 +3886,7 @@ struct gl_extensions
GLboolean EXT_blend_minmax;
GLboolean EXT_depth_bounds_test;
GLboolean EXT_draw_buffers2;
+   GLboolean EXT_frag_depth;
GLboolean EXT_framebuffer_multisample;
GLboolean EXT_framebuffer_multisample_blit_scaled;
GLboolean EXT_framebuffer_sRGB;
-- 
2.9.3

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Re: [Mesa-dev] [PATCH] util/disk_cache: stop using ralloc_asprintf() unnecessarily

[Anuj Phogat]

On Wed, Feb 8, 2017 at 2:06 PM, Timothy Arceri <tarc...@itsqueeze.com> wrote:
> ---
>  src/util/disk_cache.c | 25 -
>  1 file changed, 12 insertions(+), 13 deletions(-)
>
> diff --git a/src/util/disk_cache.c b/src/util/disk_cache.c
> index 7691621..edfff73 100644
> --- a/src/util/disk_cache.c
> +++ b/src/util/disk_cache.c
> @@ -400,11 +400,12 @@ static char *
>  get_cache_file(struct disk_cache *cache, cache_key key)
>  {
> char buf[41];
> +   char *filename;
>
> _mesa_sha1_format(buf, key);
> +   asprintf(, "%s/%c%c/%s", cache->path, buf[0], buf[1], buf + 2);
>
> -   return ralloc_asprintf(cache, "%s/%c%c/%s",
> -  cache->path, buf[0], buf[1], buf + 2);
> +   return filename;
>  }
>
>  /* Create the directory that will be needed for the cache file for \key.
> @@ -419,12 +420,10 @@ make_cache_file_directory(struct disk_cache *cache, 
> cache_key key)
> char buf[41];
>
> _mesa_sha1_format(buf, key);
> -
> -   dir = ralloc_asprintf(cache, "%s/%c%c", cache->path, buf[0], buf[1]);
> -
> +   asprintf(, "%s/%c%c", cache->path, buf[0], buf[1]);
> mkdir_if_needed(dir);
>
> -   ralloc_free(dir);
> +   free(dir);
>  }
>
>  /* Given a directory path and predicate function, count all entries in
> @@ -625,12 +624,12 @@ disk_cache_remove(struct disk_cache *cache, cache_key 
> key)
> }
>
> if (stat(filename, ) == -1) {
> -  ralloc_free(filename);
> +  free(filename);
>return;
> }
>
> unlink(filename);
> -   ralloc_free(filename);
> +   free(filename);
>
> if (sb.st_size)
>p_atomic_add(cache->size, - sb.st_size);
> @@ -655,7 +654,7 @@ disk_cache_put(struct disk_cache *cache,
>  * final destination filename, (to prevent any readers from seeing
>  * a partially written file).
>  */
> -   filename_tmp = ralloc_asprintf(cache, "%s.tmp", filename);
> +   asprintf(_tmp, "%s.tmp", filename);
> if (filename_tmp == NULL)
>goto done;
>
> @@ -727,9 +726,9 @@ disk_cache_put(struct disk_cache *cache,
> if (fd != -1)
>close(fd);
> if (filename_tmp)
> -  ralloc_free(filename_tmp);
> +  free(filename_tmp);
> if (filename)
> -  ralloc_free(filename);
> +  free(filename);
>  }
>
>  void *
> @@ -764,7 +763,7 @@ disk_cache_get(struct disk_cache *cache, cache_key key, 
> size_t *size)
>   goto fail;
> }
>
> -   ralloc_free(filename);
> +   free(filename);
> close(fd);
>
> if (size)
> @@ -776,7 +775,7 @@ disk_cache_get(struct disk_cache *cache, cache_key key, 
> size_t *size)
> if (data)
>free(data);
> if (filename)
> -  ralloc_free(filename);
> +  free(filename);
> if (fd != -1)
>close(fd);
>
> --
> 2.9.3
>
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> https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH 01/40] st/mesa/i965: create link status enum

[Anuj Phogat]

",
>shProg->Name, shProg->data->InfoLog);
> @@ -2095,7 +2095,7 @@ _mesa_ProgramBinary(GLuint program, GLenum binaryFormat,
>  * Since any value of binaryFormat passed "is not one of those specified 
> as
>  * allowable for [this] command, an INVALID_ENUM error is generated."
>  */
> -   shProg->data->LinkStatus = GL_FALSE;
> +   shProg->data->LinkStatus = linking_failure;
> _mesa_error(ctx, GL_INVALID_ENUM, "glProgramBinary");
>  }
>
> @@ -2270,7 +2270,7 @@ _mesa_CreateShaderProgramv(GLenum type, GLsizei count,
> /* Possibly... */
> if (active-user-defined-varyings-in-linked-program) {
>append-error-to-info-log;
> -   shProg->data->LinkStatus = GL_FALSE;
> +   shProg->data->LinkStatus = linking_failure;
> }
>  #endif
>  }
> diff --git a/src/mesa/main/uniforms.c b/src/mesa/main/uniforms.c
> index a954055..8376a95 100644
> --- a/src/mesa/main/uniforms.c
> +++ b/src/mesa/main/uniforms.c
> @@ -941,7 +941,7 @@ _mesa_GetUniformLocation(GLuint programObj, const 
> GLcharARB *name)
>  * "If program has not been successfully linked, the error
>  * INVALID_OPERATION is generated."
>  */
> -   if (shProg->data->LinkStatus == GL_FALSE) {
> +   if (shProg->data->LinkStatus == linking_failure) {
>_mesa_error(ctx, GL_INVALID_OPERATION,
>   "glGetUniformLocation(program not linked)");
>return -1;
> diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp
> index dc5f801..ce58fbb 100644
> --- a/src/mesa/program/ir_to_mesa.cpp
> +++ b/src/mesa/program/ir_to_mesa.cpp
> @@ -3096,7 +3096,7 @@ _mesa_glsl_link_shader(struct gl_context *ctx, struct 
> gl_shader_program *prog)
>
> _mesa_clear_shader_program_data(ctx, prog);
>
> -   prog->data->LinkStatus = GL_TRUE;
> +   prog->data->LinkStatus = linking_success;
>
> for (i = 0; i < prog->NumShaders; i++) {
>if (!prog->Shaders[i]->CompileStatus) {
> @@ -3110,7 +3110,7 @@ _mesa_glsl_link_shader(struct gl_context *ctx, struct 
> gl_shader_program *prog)
>
> if (prog->data->LinkStatus) {
>if (!ctx->Driver.LinkShader(ctx, prog)) {
> - prog->data->LinkStatus = GL_FALSE;
> + prog->data->LinkStatus = linking_failure;
>}
> }
>
> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> index 77a51d5..5a65f32 100644
> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> @@ -588,7 +588,7 @@ fail_link(struct gl_shader_program *prog, const char 
> *fmt, ...)
> ralloc_vasprintf_append(>data->InfoLog, fmt, args);
> va_end(args);
>
> -   prog->data->LinkStatus = GL_FALSE;
> +   prog->data->LinkStatus = linking_failure;
>  }
>
>  static int
> --
> 2.9.3
>
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Patches 1-4 are:

Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH 05/40] glsl: add initial implementation of shader cache

[Anuj Phogat]

On Mon, Feb 6, 2017 at 7:42 PM, Timothy Arceri  wrote:
> From: Timothy Arceri 
>
> This uses disk_cache.c to write out a serialization of various
> state that's required in order to successfully load and use a
> binary written out by a drivers backend, this state is referred to as
> "metadata" throughout the implementation.
>
> This initial version is intended to work with all stages beside
> compute.
>
> This patch is based on the initial work done by Carl.
>
> V2: extend the file's doxygen comment to cover some of the
> design decisions.
>
> V3:
> - skip cache for fixed function shaders
> - add int64 support
> - fix glsl IR program parameter caching/restore and cache the
>   parameter values which are used by gallium backends.
> - use new link status enum
> ---
>  src/compiler/Makefile.glsl.am  |   3 +-
>  src/compiler/Makefile.sources  |   4 +
>  src/compiler/glsl/shader_cache.cpp | 601 
> +
>  src/compiler/glsl/shader_cache.h   |  38 +++
>  4 files changed, 645 insertions(+), 1 deletion(-)
>  create mode 100644 src/compiler/glsl/shader_cache.cpp
>  create mode 100644 src/compiler/glsl/shader_cache.h
>
> diff --git a/src/compiler/Makefile.glsl.am b/src/compiler/Makefile.glsl.am
> index f673196..41edb3c 100644
> --- a/src/compiler/Makefile.glsl.am
> +++ b/src/compiler/Makefile.glsl.am
> @@ -131,7 +131,8 @@ glsl_libglsl_la_LIBADD = \
>
>  glsl_libglsl_la_SOURCES =  \
> $(LIBGLSL_GENERATED_FILES)  \
> -   $(LIBGLSL_FILES)
> +   $(LIBGLSL_FILES)\
> +   $(LIBGLSL_SHADER_CACHE_FILES)
>
>  glsl_libstandalone_la_SOURCES = \
> $(GLSL_COMPILER_CXX_FILES)
> diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
> index a8bb4d3..1e8edc0 100644
> --- a/src/compiler/Makefile.sources
> +++ b/src/compiler/Makefile.sources
> @@ -142,6 +142,10 @@ LIBGLSL_FILES = \
> glsl/s_expression.cpp \
> glsl/s_expression.h
>
> +LIBGLSL_SHADER_CACHE_FILES = \
> +   glsl/shader_cache.cpp \
> +   glsl/shader_cache.h
> +
>  # glsl_compiler
>
>  GLSL_COMPILER_CXX_FILES = \
> diff --git a/src/compiler/glsl/shader_cache.cpp 
> b/src/compiler/glsl/shader_cache.cpp
> new file mode 100644
> index 000..91f8d99
> --- /dev/null
> +++ b/src/compiler/glsl/shader_cache.cpp
> @@ -0,0 +1,601 @@
> +/*
> + * Copyright © 2014 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> + * DEALINGS IN THE SOFTWARE.
> + */
> +
> +/**
> + * \file shader_cache.c
s/shader_cache.c/shader_cache.cpp
> + *
> + * GLSL shader cache implementation
> + *
> + * This uses disk_cache.c to write out a serialization of various
> + * state that's required in order to successfully load and use a
> + * binary written out by a drivers backend, this state is referred to as
> + * "metadata" throughout the implementation.
> + *
> + * The hash key for glsl metadata is a hash of the hashes of each GLSL
> + * source string as well as some API settings that change the final shader
> + * such as SSO, attribute binding, frag data bindins, etc.
> + *
> + * In order to avoid caching any actual IR we use the put_key/get_key support
> + * in the disk_cache to put the SHA-1 hash for each successfully compiled
> + * shader into the cache, and optimisticly return early from glCompileShader
> + * (if the identical shader had been successfully compiled in the past),
> + * in the hope that the final linked shader will be found in the cache.
> + * If anything goes wrong (shader variant not found, backend cache item is
> + * corrupt, etc) we will use a fallback path to compile and link the IR.
> + */
> +
> +#include "blob.h"
> +#include "compiler/shader_info.h"
> +#include "glsl_symbol_table.h"
> +#include "glsl_parser_extras.h"
> +#include "ir.h"
> +#include 

Re: [Mesa-dev] [PATCH 10/40] glsl: add basic support for resource list to shader cache

[Anuj Phogat]

On Mon, Feb 6, 2017 at 7:42 PM, Timothy Arceri  wrote:
> From: Timothy Arceri 
>
> This initially adds support for simple uniforms and varyings.
> ---
>  src/compiler/glsl/shader_cache.cpp | 121 
> +
>  1 file changed, 121 insertions(+)
>
> diff --git a/src/compiler/glsl/shader_cache.cpp 
> b/src/compiler/glsl/shader_cache.cpp
> index ff8d150..56ea305 100644
> --- a/src/compiler/glsl/shader_cache.cpp
> +++ b/src/compiler/glsl/shader_cache.cpp
> @@ -392,6 +392,123 @@ read_hash_tables(struct blob_reader *metadata, struct 
> gl_shader_program *prog)
>  }
>
>  static void
> +write_program_resource_data(struct blob *metadata,
> +struct gl_shader_program *prog,
> +struct gl_program_resource *res)
> +{
> +   switch(res->Type) {
> +   case GL_PROGRAM_INPUT:
> +   case GL_PROGRAM_OUTPUT: {
> +  const gl_shader_variable *var = (gl_shader_variable *)res->Data;
> +  blob_write_bytes(metadata, var, sizeof(gl_shader_variable));
> +  encode_type_to_blob(metadata, var->type);
> +
> +  if (var->interface_type)
> + encode_type_to_blob(metadata, var->interface_type);
> +
> +  if (var->outermost_struct_type)
> + encode_type_to_blob(metadata, var->outermost_struct_type);
> +
> +  blob_write_string(metadata, var->name);
> +  break;
> +   }
> +   case GL_BUFFER_VARIABLE:
> +   case GL_VERTEX_SUBROUTINE_UNIFORM:
> +   case GL_GEOMETRY_SUBROUTINE_UNIFORM:
> +   case GL_FRAGMENT_SUBROUTINE_UNIFORM:
> +   case GL_COMPUTE_SUBROUTINE_UNIFORM:
> +   case GL_TESS_CONTROL_SUBROUTINE_UNIFORM:
> +   case GL_TESS_EVALUATION_SUBROUTINE_UNIFORM:
> +   case GL_UNIFORM:
> +  for (unsigned i = 0; i < prog->data->NumUniformStorage; i++) {
> + if (strcmp(((gl_uniform_storage *)res->Data)->name,
> +prog->data->UniformStorage[i].name) == 0) {
> +blob_write_uint32(metadata, i);
> +break;
> + }
> +  }
> +  break;
> +   default:
> +  assert(!"Support for writting resource not yet implemented.");
s/writting/writing
> +   }
> +}
> +
> +static void
> +read_program_resource_data(struct blob_reader *metadata,
> +   struct gl_shader_program *prog,
> +   struct gl_program_resource *res)
> +{
> +   switch(res->Type) {
> +   case GL_PROGRAM_INPUT:
> +   case GL_PROGRAM_OUTPUT: {
> +  gl_shader_variable *var = ralloc(prog, struct gl_shader_variable);
> +
> +  blob_copy_bytes(metadata, (uint8_t *) var, sizeof(gl_shader_variable));
> +  var->type = decode_type_from_blob(metadata);
> +
> +  if (var->interface_type)
> + var->interface_type = decode_type_from_blob(metadata);
> +
> +  if (var->outermost_struct_type)
> + var->outermost_struct_type = decode_type_from_blob(metadata);
> +
> +  var->name = ralloc_strdup(prog, blob_read_string(metadata));
> +
> +  res->Data = var;
> +  break;
> +   }
> +   case GL_BUFFER_VARIABLE:
> +   case GL_VERTEX_SUBROUTINE_UNIFORM:
> +   case GL_GEOMETRY_SUBROUTINE_UNIFORM:
> +   case GL_FRAGMENT_SUBROUTINE_UNIFORM:
> +   case GL_COMPUTE_SUBROUTINE_UNIFORM:
> +   case GL_TESS_CONTROL_SUBROUTINE_UNIFORM:
> +   case GL_TESS_EVALUATION_SUBROUTINE_UNIFORM:
> +   case GL_UNIFORM:
> +  res->Data = >data->UniformStorage[blob_read_uint32(metadata)];
> +  break;
> +   default:
> +  assert(!"Support for reading resource not yet implemented.");
> +   }
> +}
> +
> +static void
> +write_program_resource_list(struct blob *metadata,
> +struct gl_shader_program *prog)
> +{
> +   blob_write_uint32(metadata, prog->data->NumProgramResourceList);
> +
> +   for (unsigned i = 0; i < prog->data->NumProgramResourceList; i++) {
> +  blob_write_uint32(metadata, prog->data->ProgramResourceList[i].Type);
> +  write_program_resource_data(metadata, prog,
> +  >data->ProgramResourceList[i]);
> +  blob_write_bytes(metadata,
> +   >data->ProgramResourceList[i].StageReferences,
> +   
> sizeof(prog->data->ProgramResourceList[i].StageReferences));
> +   }
> +}
> +
> +static void
> +read_program_resource_list(struct blob_reader *metadata,
> +   struct gl_shader_program *prog)
> +{
> +   prog->data->NumProgramResourceList = blob_read_uint32(metadata);
> +
> +   prog->data->ProgramResourceList =
> +  ralloc_array(prog, gl_program_resource,
> +   prog->data->NumProgramResourceList);
> +
> +   for (unsigned i = 0; i < prog->data->NumProgramResourceList; i++) {
> +  prog->data->ProgramResourceList[i].Type = blob_read_uint32(metadata);
> +  read_program_resource_data(metadata, prog,
> + >data->ProgramResourceList[i]);
> +  blob_copy_bytes(metadata,
> +  (uint8_t *) 
> 

Re: [Mesa-dev] [PATCH 08/40] glsl: Serialize three additional hash tables with program metadata

[Anuj Phogat]

On Mon, Feb 6, 2017 at 7:42 PM, Timothy Arceri  wrote:
> From: Carl Worth 
>
> The three additional tables are AttributeBindings, FragDataBindings,
> and FragDataIndexBindings.
>
> The first table (AttributeBindings) was identified as missing by
> trying to test the shader cache with a program that called
> glGetAttribLocation.
>
> Many thanks to Tapani Pälli , as it was review
> of related work that he had done previously that pointed me to the
> necessity to also save and restore FragDataBindings and
> FragDataIndexBindings.
> ---
>  src/compiler/glsl/shader_cache.cpp | 74 
> ++
>  1 file changed, 74 insertions(+)
>
> diff --git a/src/compiler/glsl/shader_cache.cpp 
> b/src/compiler/glsl/shader_cache.cpp
> index 91f8d99..ba05655 100644
> --- a/src/compiler/glsl/shader_cache.cpp
> +++ b/src/compiler/glsl/shader_cache.cpp
> @@ -303,6 +303,76 @@ read_uniform_remap_table(struct blob_reader *metadata,
> }
>  }
>
> +struct whte_closure
> +{
> +   struct blob *blob;
> +   size_t num_entries;
> +};
> +
> +static void
> +write_hash_table_entry(const char *key, unsigned value, void *closure)
> +{
> +   struct whte_closure *whte = (struct whte_closure *) closure;
> +
> +   blob_write_string(whte->blob, key);
> +   blob_write_uint32(whte->blob, value);
> +
> +   whte->num_entries++;
> +}
> +
> +static void
> +write_hash_table(struct blob *metadata, struct string_to_uint_map *hash)
> +{
> +   size_t offset;
> +   struct whte_closure whte;
> +
> +   whte.blob = metadata;
> +   whte.num_entries = 0;
> +
> +   offset = metadata->size;
> +
> +   /* Write a placeholder for the hashtable size. */
> +   blob_write_uint32 (metadata, 0);
> +
> +   hash->iterate(write_hash_table_entry, );
> +
> +   /* Overwrite with the computed number of entires written. */
s/entires/entries
> +   blob_overwrite_uint32 (metadata, offset, whte.num_entries);
> +}
> +
> +static void
> +read_hash_table(struct blob_reader *metadata, struct string_to_uint_map 
> *hash)
> +{
> +   size_t i, num_entries;
> +   const char *key;
> +   uint32_t value;
> +
> +   num_entries = blob_read_uint32 (metadata);
> +
> +   for (i = 0; i < num_entries; i++) {
> +  key = blob_read_string(metadata);
> +  value = blob_read_uint32(metadata);
> +
> +  hash->put(value, key);
> +   }
> +}
> +
> +static void
> +write_hash_tables(struct blob *metadata, struct gl_shader_program *prog)
> +{
> +   write_hash_table(metadata, prog->AttributeBindings);
> +   write_hash_table(metadata, prog->FragDataBindings);
> +   write_hash_table(metadata, prog->FragDataIndexBindings);
> +}
> +
> +static void
> +read_hash_tables(struct blob_reader *metadata, struct gl_shader_program 
> *prog)
> +{
> +   read_hash_table(metadata, prog->AttributeBindings);
> +   read_hash_table(metadata, prog->FragDataBindings);
> +   read_hash_table(metadata, prog->FragDataIndexBindings);
> +}
> +
>  static void
>  write_shader_parameters(struct blob *metadata,
>  struct gl_program_parameter_list *params)
> @@ -445,6 +515,8 @@ shader_cache_write_program_metadata(struct gl_context 
> *ctx,
>
> write_uniforms(metadata, prog);
>
> +   write_hash_tables(metadata, prog);
> +
> blob_write_uint32(metadata, prog->data->Version);
> blob_write_uint32(metadata, prog->data->linked_stages);
>
> @@ -563,6 +635,8 @@ shader_cache_read_program_metadata(struct gl_context *ctx,
>
> read_uniforms(, prog);
>
> +   read_hash_tables(, prog);
> +
> prog->data->Version = blob_read_uint32();
> prog->data->linked_stages = blob_read_uint32();
>
> --
> 2.9.3
>
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Re: [Mesa-dev] [PATCH 05/40] glsl: add initial implementation of shader cache

[Anuj Phogat]

On Mon, Feb 6, 2017 at 7:42 PM, Timothy Arceri  wrote:
> From: Timothy Arceri 
>
> This uses disk_cache.c to write out a serialization of various
> state that's required in order to successfully load and use a
> binary written out by a drivers backend, this state is referred to as
> "metadata" throughout the implementation.
>
> This initial version is intended to work with all stages beside
> compute.
>
> This patch is based on the initial work done by Carl.
>
> V2: extend the file's doxygen comment to cover some of the
> design decisions.
>
> V3:
> - skip cache for fixed function shaders
> - add int64 support
> - fix glsl IR program parameter caching/restore and cache the
>   parameter values which are used by gallium backends.
> - use new link status enum
> ---
>  src/compiler/Makefile.glsl.am  |   3 +-
>  src/compiler/Makefile.sources  |   4 +
>  src/compiler/glsl/shader_cache.cpp | 601 
> +
>  src/compiler/glsl/shader_cache.h   |  38 +++
>  4 files changed, 645 insertions(+), 1 deletion(-)
>  create mode 100644 src/compiler/glsl/shader_cache.cpp
>  create mode 100644 src/compiler/glsl/shader_cache.h
>
> diff --git a/src/compiler/Makefile.glsl.am b/src/compiler/Makefile.glsl.am
> index f673196..41edb3c 100644
> --- a/src/compiler/Makefile.glsl.am
> +++ b/src/compiler/Makefile.glsl.am
> @@ -131,7 +131,8 @@ glsl_libglsl_la_LIBADD = \
>
>  glsl_libglsl_la_SOURCES =  \
> $(LIBGLSL_GENERATED_FILES)  \
> -   $(LIBGLSL_FILES)
> +   $(LIBGLSL_FILES)\
> +   $(LIBGLSL_SHADER_CACHE_FILES)
>
>  glsl_libstandalone_la_SOURCES = \
> $(GLSL_COMPILER_CXX_FILES)
> diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
> index a8bb4d3..1e8edc0 100644
> --- a/src/compiler/Makefile.sources
> +++ b/src/compiler/Makefile.sources
> @@ -142,6 +142,10 @@ LIBGLSL_FILES = \
> glsl/s_expression.cpp \
> glsl/s_expression.h
>
> +LIBGLSL_SHADER_CACHE_FILES = \
> +   glsl/shader_cache.cpp \
> +   glsl/shader_cache.h
> +
>  # glsl_compiler
>
>  GLSL_COMPILER_CXX_FILES = \
> diff --git a/src/compiler/glsl/shader_cache.cpp 
> b/src/compiler/glsl/shader_cache.cpp
> new file mode 100644
> index 000..91f8d99
> --- /dev/null
> +++ b/src/compiler/glsl/shader_cache.cpp
> @@ -0,0 +1,601 @@
> +/*
> + * Copyright © 2014 Intel Corporation
2017
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> + * DEALINGS IN THE SOFTWARE.
> + */
> +
> +/**
> + * \file shader_cache.c
> + *
> + * GLSL shader cache implementation
> + *
> + * This uses disk_cache.c to write out a serialization of various
> + * state that's required in order to successfully load and use a
> + * binary written out by a drivers backend, this state is referred to as
> + * "metadata" throughout the implementation.
> + *
> + * The hash key for glsl metadata is a hash of the hashes of each GLSL
> + * source string as well as some API settings that change the final shader
> + * such as SSO, attribute binding, frag data bindins, etc.
s/bindins/bindings
> + *
> + * In order to avoid caching any actual IR we use the put_key/get_key support
> + * in the disk_cache to put the SHA-1 hash for each successfully compiled
> + * shader into the cache, and optimisticly return early from glCompileShader
> + * (if the identical shader had been successfully compiled in the past),
> + * in the hope that the final linked shader will be found in the cache.
> + * If anything goes wrong (shader variant not found, backend cache item is
> + * corrupt, etc) we will use a fallback path to compile and link the IR.
> + */
> +
> +#include "blob.h"
> +#include "compiler/shader_info.h"
> +#include "glsl_symbol_table.h"
> +#include "glsl_parser_extras.h"
> +#include "ir.h"
> +#include "ir_optimization.h"
> 

Re: [Mesa-dev] [PATCH 1/3] main/framebuffer: refactor _mesa_get_color_read_format/type

[Anuj Phogat]

b->_ColorReadBuffer->Format;
>const GLenum data_type = _mesa_get_format_datatype(format);
>
>if (format == MESA_FORMAT_B8G8R8A8_UNORM)
> @@ -872,22 +905,34 @@ _mesa_get_color_read_format(struct gl_context *ctx)
>
>
>  /**
> - * Used to answer the GL_IMPLEMENTATION_COLOR_READ_TYPE_OES query.
> + * Used to answer the GL_IMPLEMENTATION_COLOR_READ_TYPE_OES queries (using
> + * GetIntegerv, GetFramebufferParameteriv, etc)
> + *
> + * If @fb is NULL, the method returns the value for the current bound
> + * framebuffer.
>   */
>  GLenum
> -_mesa_get_color_read_type(struct gl_context *ctx)
> +_mesa_get_color_read_type(struct gl_context *ctx,
> +  struct gl_framebuffer *fb,
> +  const char *caller)
>  {
> -   if (!ctx->ReadBuffer || !ctx->ReadBuffer->_ColorReadBuffer) {
> -  /* The spec is unclear how to handle this case, but NVIDIA's
> -   * driver generates GL_INVALID_OPERATION.
> +   if (ctx->NewState)
> +  _mesa_update_state(ctx);
> +
> +   if (fb == NULL)
> +  fb = ctx->ReadBuffer;
> +
> +   if (!fb || !fb->_ColorReadBuffer) {
> +  /*
> +   * See comment on _mesa_get_color_read_format
> */
>_mesa_error(ctx, GL_INVALID_OPERATION,
> -  "glGetIntegerv(GL_IMPLEMENTATION_COLOR_READ_TYPE: "
> -  "no GL_READ_BUFFER)");
> +  "%s(GL_IMPLEMENTATION_COLOR_READ_TYPE: no GL_READ_BUFFER)",
> +  caller);
>return GL_NONE;
> }
> else {
> -  const GLenum format = ctx->ReadBuffer->_ColorReadBuffer->Format;
> +  const GLenum format = fb->_ColorReadBuffer->Format;
>const GLenum data_type = _mesa_get_format_datatype(format);
>
>if (format == MESA_FORMAT_B5G6R5_UNORM)
> diff --git a/src/mesa/main/framebuffer.h b/src/mesa/main/framebuffer.h
> index 745c1da..ee0690b 100644
> --- a/src/mesa/main/framebuffer.h
> +++ b/src/mesa/main/framebuffer.h
> @@ -128,10 +128,14 @@ extern GLboolean
>  _mesa_dest_buffer_exists(struct gl_context *ctx, GLenum format);
>
>  extern GLenum
> -_mesa_get_color_read_type(struct gl_context *ctx);
> +_mesa_get_color_read_type(struct gl_context *ctx,
> +  struct gl_framebuffer *fb,
> +  const char *caller);
>
>  extern GLenum
> -_mesa_get_color_read_format(struct gl_context *ctx);
> +_mesa_get_color_read_format(struct gl_context *ctx,
> +struct gl_framebuffer *fb,
> +const char *caller);
>
>  extern struct gl_renderbuffer *
>  _mesa_get_read_renderbuffer_for_format(const struct gl_context *ctx,
> diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
> index f0bb041..397f4a3 100644
> --- a/src/mesa/main/get.c
> +++ b/src/mesa/main/get.c
> @@ -787,10 +787,10 @@ find_custom_value(struct gl_context *ctx, const struct 
> value_desc *d, union valu
>break;
>
> case GL_IMPLEMENTATION_COLOR_READ_TYPE_OES:
> -  v->value_int = _mesa_get_color_read_type(ctx);
> +  v->value_int = _mesa_get_color_read_type(ctx, NULL, "glGetIntegerv");
>break;
> case GL_IMPLEMENTATION_COLOR_READ_FORMAT_OES:
> -  v->value_int = _mesa_get_color_read_format(ctx);
> +  v->value_int = _mesa_get_color_read_format(ctx, NULL, "glGetIntegerv");
>break;
>
> case GL_CURRENT_MATRIX_STACK_DEPTH_ARB:
> diff --git a/src/mesa/main/readpix.c b/src/mesa/main/readpix.c
> index 1cb06c7..2582323 100644
> --- a/src/mesa/main/readpix.c
> +++ b/src/mesa/main/readpix.c
> @@ -1033,8 +1033,8 @@ _mesa_ReadnPixelsARB( GLint x, GLint y, GLsizei width, 
> GLsizei height,
> if (_mesa_is_gles(ctx)) {
>if (ctx->API == API_OPENGLES2 &&
>_mesa_is_color_format(format) &&
> -  _mesa_get_color_read_format(ctx) == format &&
> -  _mesa_get_color_read_type(ctx) == type) {
> +  _mesa_get_color_read_format(ctx, NULL, "glReadPixels") == format &&
> +  _mesa_get_color_read_type(ctx, NULL, "glReadPixels") == type) {
>   err = GL_NO_ERROR;
>} else if (ctx->Version < 30) {
>   err = _mesa_es_error_check_format_and_type(ctx, format, type, 2);
> --
> 2.9.3
>
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Series-is:
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH] glsl: correct compute shader checks for memoryBarrier functions

[Anuj Phogat]

On Fri, Feb 3, 2017 at 7:25 AM, Marc Di Luzio
<mdilu...@feralinteractive.com> wrote:
> As per the spec -
> "The functions memoryBarrierShared() and groupMemoryBarrier() are
> available only in compute shaders; the other functions are available
> in all shader types."
>
> Conform to this by adding another delegate to check for compute
> shader support instead of only whether the current stage is compute
>
> This allows some fragment shaders in Dirt Rally to compile
> ---
>  src/compiler/glsl/builtin_functions.cpp | 18 --
>  1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/src/compiler/glsl/builtin_functions.cpp 
> b/src/compiler/glsl/builtin_functions.cpp
> index 6d3b950..ac74636 100644
> --- a/src/compiler/glsl/builtin_functions.cpp
> +++ b/src/compiler/glsl/builtin_functions.cpp
> @@ -538,6 +538,12 @@ compute_shader(const _mesa_glsl_parse_state *state)
>  }
>
>  static bool
> +compute_shader_supported(const _mesa_glsl_parse_state *state)
> +{
> +   return state->has_compute_shader();
> +}
> +
> +static bool
>  buffer_atomics_supported(const _mesa_glsl_parse_state *state)
>  {
> return compute_shader(state) || shader_storage_buffer_object(state);
> @@ -1098,15 +1104,15 @@ builtin_builder::create_intrinsics()
>ir_intrinsic_group_memory_barrier),
>  NULL);
> add_function("__intrinsic_memory_barrier_atomic_counter",
> -_memory_barrier_intrinsic(compute_shader,
> +_memory_barrier_intrinsic(compute_shader_supported,
>
> ir_intrinsic_memory_barrier_atomic_counter),
>  NULL);
> add_function("__intrinsic_memory_barrier_buffer",
> -_memory_barrier_intrinsic(compute_shader,
> +_memory_barrier_intrinsic(compute_shader_supported,
>
> ir_intrinsic_memory_barrier_buffer),
>  NULL);
> add_function("__intrinsic_memory_barrier_image",
> -_memory_barrier_intrinsic(compute_shader,
> +_memory_barrier_intrinsic(compute_shader_supported,
>ir_intrinsic_memory_barrier_image),
>  NULL);
> add_function("__intrinsic_memory_barrier_shared",
> @@ -2958,15 +2964,15 @@ builtin_builder::create_builtins()
>  NULL);
> add_function("memoryBarrierAtomicCounter",
>  _memory_barrier("__intrinsic_memory_barrier_atomic_counter",
> -compute_shader),
> +compute_shader_supported),
>  NULL);
> add_function("memoryBarrierBuffer",
>  _memory_barrier("__intrinsic_memory_barrier_buffer",
> -compute_shader),
> +compute_shader_supported),
>  NULL);
> add_function("memoryBarrierImage",
>  _memory_barrier("__intrinsic_memory_barrier_image",
> -compute_shader),
> +compute_shader_supported),
>  NULL);
> add_function("memoryBarrierShared",
>  _memory_barrier("__intrinsic_memory_barrier_shared",
> --
> 2.9.3
>
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Cross checked the GLSL 4.5 spec. Please add:
Cc: 17.0 <mesa-sta...@lists.freedesktop.org>

Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH] intel/isl: Add a better comment for format_supports_ccs_e

[Anuj Phogat]

On Thu, Feb 2, 2017 at 9:52 AM, Jason Ekstrand <ja...@jlekstrand.net> wrote:
> Cc: Anuj Phogat <anuj.pho...@gmail.com>
> ---
>  src/intel/isl/isl_format.c | 6 ++
>  1 file changed, 6 insertions(+)
>
> diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
> index 1cd941c..0fdc716 100644
> --- a/src/intel/isl/isl_format.c
> +++ b/src/intel/isl/isl_format.c
> @@ -455,6 +455,12 @@ isl_format_supports_ccs_d(const struct gen_device_info 
> *devinfo,
> return fmtl->bpb == 32 || fmtl->bpb == 64 || fmtl->bpb == 128;
>  }
>
> +/**
> + * Returns true if the given format can support single-sample color
> + * compression.  This function only checks the format.  In order to determine
> + * if a surface supports CCS_E, several other factors need to be considered
> + * such as tiling and sample count.  See isl_surf_get_ccs_surf for details.
> + */
>  bool
>  isl_format_supports_ccs_e(const struct gen_device_info *devinfo,
>        enum isl_format format)
> --
> 2.5.0.400.gff86faf
>
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH 5/5] anv: Remove the finishme for CCS_E with storage images

[Anuj Phogat]

On Wed, Feb 1, 2017 at 2:40 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote:
> The data port can't handle CCS at all so replace the finishme with
> better comments.
> ---
>  src/intel/vulkan/anv_image.c | 21 +++--
>  1 file changed, 7 insertions(+), 14 deletions(-)
>
> diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
> index 94436ca..e59ef4d 100644
> --- a/src/intel/vulkan/anv_image.c
> +++ b/src/intel/vulkan/anv_image.c
> @@ -225,22 +225,15 @@ make_surface(const struct anv_device *dev,
>  /* For images created without MUTABLE_FORMAT_BIT set, we know 
> that
>   * they will always be used with the original format.  In
>   * particular, they will always be used with a format that
> - * supports color compression.  This means that it's safe to just
> - * leave compression on at all times for these formats.
> + * supports color compression.  If it's never used as a storage
> + * image, then it will only be used through the sampler or the as
> + * a render target.  This means that it's safe to just leave
> + * compression on at all times for these formats.
>   */
> -if (!(vk_info->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) &&
> +if (!(vk_info->usage & VK_IMAGE_USAGE_STORAGE_BIT) &&
> +!(vk_info->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) &&
>  isl_format_supports_ccs_e(>info, format)) {
> -   if (vk_info->usage & VK_IMAGE_USAGE_STORAGE_BIT) {
> -  /*
> -   * For now, we leave compression off for anything that may
> -   * be used as a storage image.  This is because accessing
> -   * storage images may involve ccs-incompatible views or 
> even
> -   * untyped messages which don't support compression at all.
> -   */
> -  anv_finishme("Enable CCS for storage images");
> -   } else {
> -  image->aux_usage = ISL_AUX_USAGE_CCS_E;
> -   }
> +   image->aux_usage = ISL_AUX_USAGE_CCS_E;
>  }
>   }
>}
> --
> 2.5.0.400.gff86faf
>
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[Patch v2 3/5] and rest of the series is:
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH 2/5] intel/isl: Add a supports_ccs_d helper

[Anuj Phogat]

On Thu, Feb 2, 2017 at 9:03 AM, Jason Ekstrand <ja...@jlekstrand.net> wrote:
> On Wed, Feb 1, 2017 at 4:07 PM, Anuj Phogat <anuj.pho...@gmail.com> wrote:
>>
>> On Wed, Feb 1, 2017 at 2:40 PM, Jason Ekstrand <ja...@jlekstrand.net>
>> wrote:
>> > Nothing uses this yet but it serves as a nice bit of documentation
>> > that's relatively easy to find.
>> > ---
>> >  src/intel/isl/isl.h|  2 ++
>> >  src/intel/isl/isl_format.c | 15 +++
>> >  2 files changed, 17 insertions(+)
>> >
>> > diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
>> > index bdc5ebf..47e4a1e 100644
>> > --- a/src/intel/isl/isl.h
>> > +++ b/src/intel/isl/isl.h
>> > @@ -1040,6 +1040,8 @@ bool isl_format_supports_filtering(const struct
>> > gen_device_info *devinfo,
>> > enum isl_format format);
>> >  bool isl_format_supports_vertex_fetch(const struct gen_device_info
>> > *devinfo,
>> >enum isl_format format);
>> > +bool isl_format_supports_ccs_d(const struct gen_device_info *devinfo,
>> > +   enum isl_format format);
>> >  bool isl_format_supports_ccs_e(const struct gen_device_info *devinfo,
>> > enum isl_format format);
>> >  bool isl_format_supports_multisampling(const struct gen_device_info
>> > *devinfo,
>> > diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
>> > index ebc8ec9..2705595 100644
>> > --- a/src/intel/isl/isl_format.c
>> > +++ b/src/intel/isl/isl_format.c
>> > @@ -437,6 +437,21 @@ isl_format_supports_vertex_fetch(const struct
>> > gen_device_info *devinfo,
>> > return format_gen(devinfo) >= format_info[format].input_vb;
>> >  }
>> >
>> > +/**
>> > + * Returns true if the given format can support single-sample fast
>> > clears.
>> > + */
>> > +bool
>> > +isl_format_supports_ccs_d(const struct gen_device_info *devinfo,
>> > +  enum isl_format format)
>> > +{
>> > +   if (!isl_format_supports_rendering(devinfo, format))
>> > +  return false;
>> > +
>> Add a check for non-MSRT?
>
>
> Maybe?  There are other things we could potentially check for such as tiling
> format, num samples, etc. in order to get a full "can this support
> fast-clears" check.  I intended this to be just a format check.  Thoughts?
>
I'm fine with leaving it as it is with an added comment saying:
It just checks for format. We need additional checks like tiling format,
num samples to determine if this can support fast clears.

As you're already here, you might want to add another helper to cover all
the checks. I'll leave it up to you.
>>
>> > +   const struct isl_format_layout *fmtl =
>> > isl_format_get_layout(format);
>> > +
>> > +   return fmtl->bpb == 32 || fmtl->bpb == 64 || fmtl->bpb == 128;
>> > +}
>> > +
>> >  bool
>> >  isl_format_supports_ccs_e(const struct gen_device_info *devinfo,
>> >enum isl_format format)
>> > --
>> > 2.5.0.400.gff86faf
>> >
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>
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Re: [Mesa-dev] [PATCH 2/5] intel/isl: Add a supports_ccs_d helper

[Anuj Phogat]

On Wed, Feb 1, 2017 at 2:40 PM, Jason Ekstrand  wrote:
> Nothing uses this yet but it serves as a nice bit of documentation
> that's relatively easy to find.
> ---
>  src/intel/isl/isl.h|  2 ++
>  src/intel/isl/isl_format.c | 15 +++
>  2 files changed, 17 insertions(+)
>
> diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
> index bdc5ebf..47e4a1e 100644
> --- a/src/intel/isl/isl.h
> +++ b/src/intel/isl/isl.h
> @@ -1040,6 +1040,8 @@ bool isl_format_supports_filtering(const struct 
> gen_device_info *devinfo,
> enum isl_format format);
>  bool isl_format_supports_vertex_fetch(const struct gen_device_info *devinfo,
>enum isl_format format);
> +bool isl_format_supports_ccs_d(const struct gen_device_info *devinfo,
> +   enum isl_format format);
>  bool isl_format_supports_ccs_e(const struct gen_device_info *devinfo,
> enum isl_format format);
>  bool isl_format_supports_multisampling(const struct gen_device_info *devinfo,
> diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
> index ebc8ec9..2705595 100644
> --- a/src/intel/isl/isl_format.c
> +++ b/src/intel/isl/isl_format.c
> @@ -437,6 +437,21 @@ isl_format_supports_vertex_fetch(const struct 
> gen_device_info *devinfo,
> return format_gen(devinfo) >= format_info[format].input_vb;
>  }
>
> +/**
> + * Returns true if the given format can support single-sample fast clears.
> + */
> +bool
> +isl_format_supports_ccs_d(const struct gen_device_info *devinfo,
> +  enum isl_format format)
> +{
> +   if (!isl_format_supports_rendering(devinfo, format))
> +  return false;
> +
Add a check for non-MSRT?

> +   const struct isl_format_layout *fmtl = isl_format_get_layout(format);
> +
> +   return fmtl->bpb == 32 || fmtl->bpb == 64 || fmtl->bpb == 128;
> +}
> +
>  bool
>  isl_format_supports_ccs_e(const struct gen_device_info *devinfo,
>enum isl_format format)
> --
> 2.5.0.400.gff86faf
>
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Re: [Mesa-dev] [PATCH] anv: Don't use bogus alpha swizzles

[Anuj Phogat]

On Wed, Feb 1, 2017 at 12:39 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote:
>
> For RGB formats in Vulkan, we use the corresponding RGBA format with a
> swizzle of RGB1.  While this swizzle is exactly what we want for
> texturing, it's not allowed for rendering according to the docs.  While
> we haven't been getting hangs or anything, we should probably obey the
> docs.  This commit just sanitizes all render swizzles so that the alpha
> channel maps to ALPHA.
>
> Cc: Anuj Phogat <anuj.pho...@gmail.com>
> ---
>  src/intel/vulkan/anv_blorp.c   |  9 ++---
>  src/intel/vulkan/anv_private.h | 15 +++
>  src/intel/vulkan/genX_cmd_buffer.c |  1 +
>  3 files changed, 22 insertions(+), 3 deletions(-)
>
> diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
> index 2edd071..2cf972b 100644
> --- a/src/intel/vulkan/anv_blorp.c
> +++ b/src/intel/vulkan/anv_blorp.c
> @@ -503,7 +503,8 @@ void anv_CmdBlitImage(
>   blorp_blit(, , src_res->mipLevel, src_z,
>  src_format.isl_format, src_format.swizzle,
>  , dst_res->mipLevel, dst_z,
> -dst_format.isl_format, dst_format.swizzle,
> +dst_format.isl_format,
> +anv_swizzle_for_render(dst_format.swizzle),
>  src_x0, src_y0, src_x1, src_y1,
>  dst_x0, dst_y0, dst_x1, dst_y1,
>  gl_filter, flip_x, flip_y);
> @@ -831,7 +832,8 @@ void anv_CmdClearColorImage(
>   }
>
>   blorp_clear(, ,
> - src_format.isl_format, src_format.swizzle,
> + src_format.isl_format,
> + anv_swizzle_for_render(src_format.swizzle),
>   level, base_layer, layer_count,
>   0, 0, level_width, level_height,
>   vk_to_isl_color(*pColor), color_write_disable);
> @@ -1216,7 +1218,8 @@ anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer 
> *cmd_buffer)
>   cmd_buffer->state.pending_pipe_bits |=
>  ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
>} else {
> - blorp_clear(, , iview->isl.format, iview->isl.swizzle,
> + blorp_clear(, , iview->isl.format,
> + anv_swizzle_for_render(iview->isl.swizzle),
>   iview->isl.base_level,
>   iview->isl.base_array_layer, fb->layers,
>   render_area.offset.x, render_area.offset.y,
> diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
> index 0cc6550..a0cb35c 100644
> --- a/src/intel/vulkan/anv_private.h
> +++ b/src/intel/vulkan/anv_private.h
> @@ -1552,6 +1552,21 @@ anv_get_isl_format(const struct gen_device_info 
> *devinfo, VkFormat vk_format,
> return anv_get_format(devinfo, vk_format, aspect, tiling).isl_format;
>  }
>
> +static inline struct isl_swizzle
> +anv_swizzle_for_render(struct isl_swizzle swizzle)
> +{
> +   /* Sometimes the swizzle will have alpha map to one.  We do this to fake
> +* RGB as RGBA for texturing
> +*/
> +   assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
> +  swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
> +
> +   /* But it doesn't matter what we render to that channel */
> +   swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
> +
> +   return swizzle;
> +}
> +
>  void
>  anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
>
> diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
> b/src/intel/vulkan/genX_cmd_buffer.c
> index 0ad7cd5..b6b7f74 100644
> --- a/src/intel/vulkan/genX_cmd_buffer.c
> +++ b/src/intel/vulkan/genX_cmd_buffer.c
> @@ -528,6 +528,7 @@ genX(cmd_buffer_setup_attachments)(struct anv_cmd_buffer 
> *cmd_buffer,
>
>  struct isl_view view = iview->isl;
>  view.usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
> +view.swizzle = anv_swizzle_for_render(view.swizzle);
>  isl_surf_fill_state(isl_dev,
>  state->attachments[i].color_rt_state.map,
>  .surf = >image->color_surface.isl,
> --
> 2.5.0.400.gff86faf
>
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH] isl: Add assertions for render target swizzle restrictions

[Anuj Phogat]

On Tue, Jan 31, 2017 at 6:51 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote:
> ---
>  src/intel/isl/isl_surface_state.c | 32 
>  1 file changed, 32 insertions(+)
>
> diff --git a/src/intel/isl/isl_surface_state.c 
> b/src/intel/isl/isl_surface_state.c
> index b735478..c7b220b 100644
> --- a/src/intel/isl/isl_surface_state.c
> +++ b/src/intel/isl/isl_surface_state.c
> @@ -453,6 +453,38 @@ isl_genX(surf_fill_state_s)(const struct isl_device 
> *dev, void *state,
>  #endif
>
>  #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
> +   if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
> +  /* From the Sky Lake PRM Vol. 2d,
> +   * RENDER_SURFACE_STATE::Shader Channel Select Red
> +   *
> +   *"For Render Target, Red, Green and Blue Shader Channel Selects
> +   *MUST be such that only valid components can be swapped i.e. only
> +   *change the order of components in the pixel. Any other values for
> +   *these Shader Channel Select fields are not valid for Render
> +   *Targets. This also means that there MUST not be multiple shader
> +   *channels mapped to the same RT channel."
> +   */
> +  assert(info->view->swizzle.r == ISL_CHANNEL_SELECT_RED ||
> + info->view->swizzle.r == ISL_CHANNEL_SELECT_GREEN ||
> + info->view->swizzle.r == ISL_CHANNEL_SELECT_BLUE);
> +  assert(info->view->swizzle.g == ISL_CHANNEL_SELECT_RED ||
> + info->view->swizzle.g == ISL_CHANNEL_SELECT_GREEN ||
> + info->view->swizzle.g == ISL_CHANNEL_SELECT_BLUE);
> +  assert(info->view->swizzle.b == ISL_CHANNEL_SELECT_RED ||
> + info->view->swizzle.b == ISL_CHANNEL_SELECT_GREEN ||
> + info->view->swizzle.b == ISL_CHANNEL_SELECT_BLUE);
> +  assert(info->view->swizzle.r != info->view->swizzle.g);
> +  assert(info->view->swizzle.r != info->view->swizzle.b);
> +  assert(info->view->swizzle.g != info->view->swizzle.b);
> +
> +  /* From the Sky Lake PRM Vol. 2d,
> +   * RENDER_SURFACE_STATE::Shader Channel Select Alpha
> +   *
> +   *"For Render Target, this field MUST be programmed to
> +   *value = SCS_ALPHA."
> +   */
> +  assert(info->view->swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
> +   }
> s.ShaderChannelSelectRed = info->view->swizzle.r;
> s.ShaderChannelSelectGreen = info->view->swizzle.g;
> s.ShaderChannelSelectBlue = info->view->swizzle.b;
> --
> 2.5.0.400.gff86faf
>
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Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH 7/7] anv: enable VK_KHR_shader_draw_parameters

[Anuj Phogat]

On Tue, Jan 31, 2017 at 7:00 AM, Lionel Landwerlin
<lionel.g.landwer...@intel.com> wrote:
> Enables 10 tests from:
>
>dEQP-VK.draw.shader_draw_parameters.*
and I assume they all pass with this series.
>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
> ---
>  src/intel/vulkan/anv_device.c   | 4 
>  src/intel/vulkan/anv_pipeline.c | 1 +
>  2 files changed, 5 insertions(+)
>
> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
> index 3403dc126a..91ee67f053 100644
> --- a/src/intel/vulkan/anv_device.c
> +++ b/src/intel/vulkan/anv_device.c
> @@ -272,6 +272,10 @@ static const VkExtensionProperties device_extensions[] = 
> {
>.extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
>.specVersion = 1,
> },
> +   {
> +  .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
> +  .specVersion = 1,
> +   }
>  };
>
>  static void *
> diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
> index 2060c6d2f6..ca3823c2b6 100644
> --- a/src/intel/vulkan/anv_pipeline.c
> +++ b/src/intel/vulkan/anv_pipeline.c
> @@ -127,6 +127,7 @@ anv_shader_compile_to_nir(struct anv_device *device,
> const struct nir_spirv_supported_extensions supported_ext = {
>.float64 = device->instance->physicalDevice.info.gen >= 8,
>.tessellation = true,
> +  .draw_parameters = true,
> };
>
> nir_function *entry_point =
> --
> 2.11.0
>
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 Series is doing what it says and changes look fine to me.

Series is:
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Re: [Mesa-dev] [PATCH] glsl: Allow compatibility shaders with MESA_GL_VERSION_OVERRIDE=...

[Anuj Phogat]

t; diff --git a/src/compiler/glsl/glsl_parser_extras.h 
> b/src/compiler/glsl/glsl_parser_extras.h
> index 424cab5..66a954f 100644
> --- a/src/compiler/glsl/glsl_parser_extras.h
> +++ b/src/compiler/glsl/glsl_parser_extras.h
> @@ -348,6 +348,7 @@ struct _mesa_glsl_parse_state {
> } supported_versions[16];
>
> bool es_shader;
> +   bool compat_shader;
> unsigned language_version;
> unsigned forced_language_version;
> bool zero_init;
> --
> 2.10.2
>
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LGTM.

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Re: [Mesa-dev] [PATCH v2] i965: Prevent coverity warning

[Anuj Phogat]

On Tue, Jan 31, 2017 at 6:46 AM, Robert Foss <robert.f...@collabora.com> wrote:
> Add assert checking that num_sources is never larger than 3.
>
> This prevents Coverity from concluding that the improperly handled
> cases of num_sources not being 0-3 are relevant.
>
You may change "improperly handled" to "unhandled".
> Coverity-Id: 1399480-1399489
> Signed-off-by: Robert Foss <robert.f...@collabora.com>
> ---
>  src/mesa/drivers/dri/i965/brw_eu_validate.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_eu_validate.c 
> b/src/mesa/drivers/dri/i965/brw_eu_validate.c
> index 226539445d..64615af44a 100644
> --- a/src/mesa/drivers/dri/i965/brw_eu_validate.c
> +++ b/src/mesa/drivers/dri/i965/brw_eu_validate.c
> @@ -177,6 +177,7 @@ num_sources_from_inst(const struct gen_device_info 
> *devinfo,
>   return 0;
>}
> } else {
> +  assert(desc->nsrc < 4);
>return desc->nsrc;
> }
>
> --
> 2.11.0.453.g787f75f05
>
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Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH] i965: Fix fast depth clears for surfaces with a dimension of 16384.

[Anuj Phogat]

On Tue, Jan 24, 2017 at 3:32 PM, Kenneth Graunke <kenn...@whitecape.org> wrote:
> I hadn't bothered to set this bit because I figured it would just
> paper over us getting the rectangle wrong.  But it turns out that
> there is a legitimate reason to use it, so let's do so.
>
> The alternative would be to chop up 16k clears to multiple 8k clears,
> which is pointlessly painful.
>
> Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
> ---
>  src/mesa/drivers/dri/i965/gen8_depth_state.c | 11 +++
>  1 file changed, 11 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c 
> b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> index ec296698267..de5a16e91bf 100644
> --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> @@ -477,6 +477,17 @@ gen8_hiz_exec(struct brw_context *brw, struct 
> intel_mipmap_tree *mt,
>break;
> case BLORP_HIZ_OP_DEPTH_CLEAR:
>dw1 |= GEN8_WM_HZ_DEPTH_CLEAR;
> +
> +  /* The "Clear Rectangle X Max" (and Y Max) fields are exclusive,
> +   * rather than inclusive, and limited to 16383.  This means that
> +   * for a 16384x16384 render target, we would miss the last pixel.
> +   *
> +   * To work around this, we have to set the "Full Surface Depth
> +   * and Stencil Clear" bit.  We can do this in all cases because
> +   * we always clear the full rectangle anyway.  We'll need to
> +   * change this if we ever add scissored clear support.
> +   */
> +  dw1 |= GEN8_WM_HZ_FULL_SURFACE_DEPTH_CLEAR;
>break;
> case BLORP_HIZ_OP_NONE:
>unreachable("Should not get here.");
> --
> 2.11.0
>
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Verified the restriction from PRM. Patch looks good to me.
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Re: [Mesa-dev] [PATCH] spirv: handle gl_SampleMask

[Anuj Phogat]

On Tue, Jan 24, 2017 at 4:48 AM, Iago Toral Quiroga <ito...@igalia.com> wrote:
> SPIR-V maps both gl_SampleMask and gl_SampleMaskIn to the same
> builtin (SampleMask). The only way to tell which one we are dealing with
> is to check if it is an input or an output.
>
> Fixes:
> dEQP-VK.pipeline.multisample_shader_builtin.sample_mask.write.*
> ---
> I am still waiting on Jenkins to report results from this patch, but for
> some reason it is taking surprisingly long so I figured I'd send it for
> review ahead of the results, I don't expect regressions, but I'll verify
> there aren't any when I get them in any case.
>
>  src/compiler/spirv/vtn_variables.c | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/src/compiler/spirv/vtn_variables.c 
> b/src/compiler/spirv/vtn_variables.c
> index d55f81e..4d1ec78 100644
> --- a/src/compiler/spirv/vtn_variables.c
> +++ b/src/compiler/spirv/vtn_variables.c
> @@ -975,8 +975,12 @@ vtn_get_builtin_location(struct vtn_builder *b,
>set_mode_system_value(mode);
>break;
> case SpvBuiltInSampleMask:
> -  *location = SYSTEM_VALUE_SAMPLE_MASK_IN; /* XXX out? */
> -  set_mode_system_value(mode);
> +  if (*mode == nir_var_shader_out) {
> + *location = FRAG_RESULT_SAMPLE_MASK;
> +  } else {
> + *location = SYSTEM_VALUE_SAMPLE_MASK_IN;
> + set_mode_system_value(mode);
> +  }
>break;
> case SpvBuiltInFragDepth:
>*location = FRAG_RESULT_DEPTH;
> --
> 2.7.4
>
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Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH v2] main/buffers: update error handling on DrawBuffers for 4.5

[Anuj Phogat]

& 
> buffers[output] == GL_BACK) {
Split in two lines. Exceeding the 80 character limit.
> +if (n != 1) {
> +   _mesa_error(ctx, GL_INVALID_OPERATION, "%s(with GL_BACK n 
> must be 1)",
> +   caller);
> +   return;
> +}
> + } else {
> +_mesa_error(ctx, GL_INVALID_ENUM, "%s(invalid buffer %s)",
> +    caller, _mesa_enum_to_string(buffers[output]));
> +return;
> + }
>}
>
>/* Section 4.2 (Whole Framebuffer Operations) of the OpenGL ES 3.0
> --
> 2.9.3
>
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With above comments fixed, both patches are:
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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[Mesa-dev] [PATCH 2/3] i965: Fix indentation in brw_miptree_layout_2d()

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/mesa/drivers/dri/i965/brw_tex_layout.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c 
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index bf8c338..2f4837e 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -322,9 +322,8 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
  minify(mt->physical_width0, 2);
}
 
-   if (mip1_width > mt->total_width) {
-   mt->total_width = mip1_width;
-   }
+  if (mip1_width > mt->total_width)
+ mt->total_width = mip1_width;
}
 
mt->total_width /= bw;
-- 
2.9.3

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[Mesa-dev] [PATCH 1/3] i965: Fix comment to include 3d textures

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/mesa/drivers/dri/i965/brw_tex_layout.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c 
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 768f8a8..bf8c338 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -295,7 +295,8 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
unsigned y = 0;
unsigned width = mt->physical_width0;
unsigned height = mt->physical_height0;
-   unsigned depth = mt->physical_depth0; /* number of array layers. */
+   /* Number of layers of array texture or slices of 3d texture (gen9+). */
+   unsigned depth = mt->physical_depth0;
unsigned int bw, bh;
 
_mesa_get_format_block_size(mt->format, , );
-- 
2.9.3

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[Mesa-dev] [PATCH 3/3] i965: Remove unnecessary mt->compressed checks

[Anuj Phogat]

It's harmless to use ALIGN_NPOT() for uncompressed formats
because they have block width/height = 1.

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/mesa/drivers/dri/i965/brw_tex_layout.c | 16 
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c 
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 2f4837e..684ae76 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -302,9 +302,7 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
_mesa_get_format_block_size(mt->format, , );
 
mt->total_width = mt->physical_width0;
-
-   if (mt->compressed)
-   mt->total_width = ALIGN_NPOT(mt->total_width, bw);
+   mt->total_width = ALIGN_NPOT(mt->total_width, bw);
 
/* May need to adjust width to accommodate the placement of
 * the 2nd mipmap.  This occurs when the alignment
@@ -314,13 +312,8 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
if (mt->first_level != mt->last_level) {
unsigned mip1_width;
 
-   if (mt->compressed) {
-  mip1_width = ALIGN_NPOT(minify(mt->physical_width0, 1), mt->halign) +
- ALIGN_NPOT(minify(mt->physical_width0, 2), bw);
-   } else {
-  mip1_width = ALIGN_NPOT(minify(mt->physical_width0, 1), mt->halign) +
- minify(mt->physical_width0, 2);
-   }
+  mip1_width = ALIGN_NPOT(minify(mt->physical_width0, 1), mt->halign) +
+   ALIGN_NPOT(minify(mt->physical_width0, 2), bw);
 
   if (mip1_width > mt->total_width)
  mt->total_width = mip1_width;
@@ -335,8 +328,7 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
   intel_miptree_set_level_info(mt, level, x, y, depth);
 
   img_height = ALIGN_NPOT(height, mt->valign);
-  if (mt->compressed)
-img_height /= bh;
+  img_height /= bh;
 
   if (mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
  /* Compact arrays with separated miplevels */
-- 
2.9.3

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Re: [Mesa-dev] [PATCH] i965: Properly flush in hsw_pause_transform_feedback().

[Anuj Phogat]

On Fri, Jan 6, 2017 at 12:09 AM, Kenneth Graunke <kenn...@whitecape.org> wrote:
> Fixes a number of transform feedback tests when run with Linux 4.8,
> which allows us to use the MI_LOAD_REGISTER_REG command, at which point
> we started using this new broken path.
>
> ES3-CTS.functional.transform_feedback.array_element.interleaved.lines.*
> and Piglit's arb_transform_feedback2/draw-auto are both fixed by this
> patch, for example.
>
> Thanks to Chris Wilson for catching this mistake!
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99030
> Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
> ---
>  src/mesa/drivers/dri/i965/hsw_sol.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/hsw_sol.c 
> b/src/mesa/drivers/dri/i965/hsw_sol.c
> index e299b022706..b0dd150b7df 100644
> --- a/src/mesa/drivers/dri/i965/hsw_sol.c
> +++ b/src/mesa/drivers/dri/i965/hsw_sol.c
> @@ -201,6 +201,9 @@ hsw_pause_transform_feedback(struct gl_context *ctx,
>(struct brw_transform_feedback_object *) obj;
>
> if (brw->is_haswell) {
> +  /* Flush any drawing so that the counters have the right values. */
> +  brw_emit_mi_flush(brw);
> +
>/* Save the SOL buffer offset register values. */
>for (int i = 0; i < BRW_MAX_XFB_STREAMS; i++) {
>   BEGIN_BATCH(3);
> --
> 2.11.0
>
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Looks reasonable to me.
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Re: [Mesa-dev] [PATCH 6/9] i965: Add support for tex upload using gpu

[Anuj Phogat]

On Mon, Jan 2, 2017 at 12:45 AM, Pohjolainen, Topi
<topi.pohjolai...@gmail.com> wrote:
> On Thu, Dec 29, 2016 at 11:55:37AM -0800, Anuj Phogat wrote:
>> On Tue, Dec 20, 2016 at 6:45 AM, Topi Pohjolainen
>> <topi.pohjolai...@gmail.com> wrote:
>> > Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
>> > ---
>> >  src/mesa/drivers/dri/i965/intel_tex.h  |   8 +
>> >  src/mesa/drivers/dri/i965/intel_tex_subimage.c | 194 
>> > +
>> >  2 files changed, 202 insertions(+)
>> >
>> > diff --git a/src/mesa/drivers/dri/i965/intel_tex.h 
>> > b/src/mesa/drivers/dri/i965/intel_tex.h
>> > index 376f075..c7d0937 100644
>> > --- a/src/mesa/drivers/dri/i965/intel_tex.h
>> > +++ b/src/mesa/drivers/dri/i965/intel_tex.h
>> > @@ -65,6 +65,14 @@ intel_texsubimage_tiled_memcpy(struct gl_context *ctx,
>> > bool for_glTexImage);
>> >
>> >  bool
>> > +intel_texsubimage_gpu_copy(struct brw_context *brw, GLuint dims,
>> > +   struct gl_texture_image *tex_image,
>> > +   unsigned x, unsigned y, unsigned z,
>> > +   unsigned w, unsigned h, unsigned d,
>> > +   GLenum format, GLenum type, const void *pixels,
>> > +   const struct gl_pixelstore_attrib *packing);
>> > +
>> > +bool
>> >  intel_gettexsubimage_tiled_memcpy(struct gl_context *ctx,
>> >struct gl_texture_image *texImage,
>> >GLint xoffset, GLint yofset,
>> > diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c 
>> > b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
>> > index b7e52bc..f999a93 100644
>> > --- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
>> > +++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
>> > @@ -24,6 +24,7 @@
>> >   */
>> >
>> >  #include "main/bufferobj.h"
>> > +#include "main/glformats.h"
>> >  #include "main/image.h"
>> >  #include "main/macros.h"
>> >  #include "main/mtypes.h"
>> > @@ -34,8 +35,10 @@
>> >  #include "main/enums.h"
>> >  #include "drivers/common/meta.h"
>> >
>> > +#include "brw_blorp.h"
>> >  #include "brw_context.h"
>> >  #include "intel_batchbuffer.h"
>> > +#include "intel_buffer_objects.h"
>> >  #include "intel_tex.h"
>> >  #include "intel_mipmap_tree.h"
>> >  #include "intel_blit.h"
>> > @@ -43,6 +46,197 @@
>> >
>> >  #define FILE_DEBUG_FLAG DEBUG_TEXTURE
>> >
>> > +static drm_intel_bo *
>> > +intel_texsubimage_get_src_as_bo(struct brw_context *brw, unsigned dims,
>> > +struct gl_texture_image *tex_image,
>> > +unsigned w, unsigned h, unsigned d,
>> > +GLenum format, GLenum type, const void 
>> > *pixels,
>> > +const struct gl_pixelstore_attrib 
>> > *packing)
>> > +{
>> > +   /* Account for SKIP_PIXELS, SKIP_ROWS, ALIGNMENT, and SKIP_IMAGES */
>> > +   const uint32_t first_pixel = _mesa_image_offset(dims, packing, w, h,
>> > +   format, type, 0, 0, 0);
>> > +   const uint32_t last_pixel =  _mesa_image_offset(dims, packing, w, h,
>> > +   format, type,
>> > +   d - 1, h - 1, w);
>> > +   const uint32_t size = last_pixel - first_pixel;
>> > +
>> > +   drm_intel_bo * const bo =
>> > +  drm_intel_bo_alloc(brw->bufmgr, "tmp_tex_subimage_src", size, 64);
>> > +
>> > +   if (bo == NULL) {
>> > +  perf_debug("intel_texsubimage: temp bo creation failed: size = 
>> > %u\n",
>> > + size);
>> > +  return false;
>> > +   }
>> > +
>> > +   if (drm_intel_bo_subdata(bo, 0, size, pixels + first_pixel)) {
>> > +  perf_debug("intel_texsubimage: temp bo upload failed\n");
>> > +  drm_intel_bo_unreference(bo);
>> > +  return NULL;
>> > +   }
>> > +
>> 

Re: [Mesa-dev] [PATCH] mesa: Make CopyImage check against BaseLevel, not 0, for mipmapping.

[Anuj Phogat]

On Mon, Jan 2, 2017 at 8:01 PM, Kenneth Graunke <kenn...@whitecape.org> wrote:
> The intention here is to allow "base complete" instead of "mipmap
> complete" as long as we're only copying from the base level (which
> is usually 0, but not always).
>
> Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
> ---
>  src/mesa/main/copyimage.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/main/copyimage.c b/src/mesa/main/copyimage.c
> index cf25159e880..d10bf8cc61c 100644
> --- a/src/mesa/main/copyimage.c
> +++ b/src/mesa/main/copyimage.c
> @@ -151,7 +151,7 @@ prepare_target(struct gl_context *ctx, GLuint name, 
> GLenum target,
>
>_mesa_test_texobj_completeness(ctx, texObj);
>if (!texObj->_BaseComplete ||
> -  (level != 0 && !texObj->_MipmapComplete)) {
> +  (level != texObj->BaseLevel && !texObj->_MipmapComplete)) {
>   _mesa_error(ctx, GL_INVALID_OPERATION,
>   "glCopyImageSubData(%sName incomplete)", dbg_prefix);
>   return false;
> --
> 2.11.0
>
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Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH 6/9] i965: Add support for tex upload using gpu

[Anuj Phogat]

On Tue, Dec 20, 2016 at 6:45 AM, Topi Pohjolainen
 wrote:
> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/intel_tex.h  |   8 +
>  src/mesa/drivers/dri/i965/intel_tex_subimage.c | 194 
> +
>  2 files changed, 202 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_tex.h 
> b/src/mesa/drivers/dri/i965/intel_tex.h
> index 376f075..c7d0937 100644
> --- a/src/mesa/drivers/dri/i965/intel_tex.h
> +++ b/src/mesa/drivers/dri/i965/intel_tex.h
> @@ -65,6 +65,14 @@ intel_texsubimage_tiled_memcpy(struct gl_context *ctx,
> bool for_glTexImage);
>
>  bool
> +intel_texsubimage_gpu_copy(struct brw_context *brw, GLuint dims,
> +   struct gl_texture_image *tex_image,
> +   unsigned x, unsigned y, unsigned z,
> +   unsigned w, unsigned h, unsigned d,
> +   GLenum format, GLenum type, const void *pixels,
> +   const struct gl_pixelstore_attrib *packing);
> +
> +bool
>  intel_gettexsubimage_tiled_memcpy(struct gl_context *ctx,
>struct gl_texture_image *texImage,
>GLint xoffset, GLint yofset,
> diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c 
> b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
> index b7e52bc..f999a93 100644
> --- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
> +++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
> @@ -24,6 +24,7 @@
>   */
>
>  #include "main/bufferobj.h"
> +#include "main/glformats.h"
>  #include "main/image.h"
>  #include "main/macros.h"
>  #include "main/mtypes.h"
> @@ -34,8 +35,10 @@
>  #include "main/enums.h"
>  #include "drivers/common/meta.h"
>
> +#include "brw_blorp.h"
>  #include "brw_context.h"
>  #include "intel_batchbuffer.h"
> +#include "intel_buffer_objects.h"
>  #include "intel_tex.h"
>  #include "intel_mipmap_tree.h"
>  #include "intel_blit.h"
> @@ -43,6 +46,197 @@
>
>  #define FILE_DEBUG_FLAG DEBUG_TEXTURE
>
> +static drm_intel_bo *
> +intel_texsubimage_get_src_as_bo(struct brw_context *brw, unsigned dims,
> +struct gl_texture_image *tex_image,
> +unsigned w, unsigned h, unsigned d,
> +GLenum format, GLenum type, const void 
> *pixels,
> +const struct gl_pixelstore_attrib *packing)
> +{
> +   /* Account for SKIP_PIXELS, SKIP_ROWS, ALIGNMENT, and SKIP_IMAGES */
> +   const uint32_t first_pixel = _mesa_image_offset(dims, packing, w, h,
> +   format, type, 0, 0, 0);
> +   const uint32_t last_pixel =  _mesa_image_offset(dims, packing, w, h,
> +   format, type,
> +   d - 1, h - 1, w);
> +   const uint32_t size = last_pixel - first_pixel;
> +
> +   drm_intel_bo * const bo =
> +  drm_intel_bo_alloc(brw->bufmgr, "tmp_tex_subimage_src", size, 64);
> +
> +   if (bo == NULL) {
> +  perf_debug("intel_texsubimage: temp bo creation failed: size = %u\n",
> + size);
> +  return false;
> +   }
> +
> +   if (drm_intel_bo_subdata(bo, 0, size, pixels + first_pixel)) {
> +  perf_debug("intel_texsubimage: temp bo upload failed\n");
> +  drm_intel_bo_unreference(bo);
> +  return NULL;
> +   }
> +
> +   return bo;
> +}
> +
> +static uint32_t
> +intel_texsubimage_get_src_offset(unsigned dims, unsigned w, unsigned h,
> + GLenum format, GLenum type,
> + const void *pixels,
> + const struct gl_pixelstore_attrib *packing)
> +{
> +   /* Account for SKIP_PIXELS, SKIP_ROWS, ALIGNMENT, and SKIP_IMAGES */
> +   const uint32_t first_pixel = _mesa_image_offset(dims, packing, w, h,
> +   format, type, 0, 0, 0);
> +
> +   /* In case of buffer object source 'pixels' represents offset in bytes. */
> +   return first_pixel + (intptr_t)pixels;
> +}
> +
> +/* Consider all the restrictions and determine the format of the source. */
> +static mesa_format
> +intel_texsubimage_check_upload(struct brw_context *brw,
> +   const struct gl_texture_image *tex_image,
> +   unsigned h, GLenum format, GLenum type,
> +   const struct gl_pixelstore_attrib *packing)
> +{
> +   /* TODO: Add support for buffer object upload 1D alignment or perhaps use
> +* flat 2D source.
> +*/
> +   if (tex_image->TexObject->Target == GL_TEXTURE_1D_ARRAY) {
> +  perf_debug("intel_texsubimage: 1D_ARRAY not supported\n");
> +  return MESA_FORMAT_NONE;
> +   }
> +
> +   if (brw->ctx._ImageTransferState)
> +  return MESA_FORMAT_NONE;
> +
> +   if 

Re: [Mesa-dev] [PATCH] anv: Handle vkGetPhysicalDeviceQueueFamilyProperties with count == 0

[Anuj Phogat]

On Tue, Dec 27, 2016 at 10:30 AM, Chad Versace <chadvers...@chromium.org> wrote:
>
> The spec implicitly allows the incoming count to be 0. From the Vulkan
> 1.0.38 spec, Section 4.1 Physical Devices:
>
> If the value referenced by pQueueFamilyPropertyCount is not 0 [then
> do stuff].
>
> Cc: Damien Grassart <dam...@grassart.com>
> ---
>  src/intel/vulkan/anv_device.c | 9 -
>  1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
> index 037ef827e1..323cae4029 100644
> --- a/src/intel/vulkan/anv_device.c
> +++ b/src/intel/vulkan/anv_device.c
> @@ -646,7 +646,14 @@ void anv_GetPhysicalDeviceQueueFamilyProperties(
>return;
> }
>
> -   assert(*pCount >= 1);
> +   /* The spec implicitly allows the incoming count to be 0. From the Vulkan
> +* 1.0.38 spec, Section 4.1 Physical Devices:
> +*
> +* If the value referenced by pQueueFamilyPropertyCount is not 0 [then
> +* do stuff].
> +*/
> +   if (*pCount == 0)
> +  return;
>
> *pQueueFamilyProperties = (VkQueueFamilyProperties) {
>.queueFlags = VK_QUEUE_GRAPHICS_BIT |
> --
> 2.11.0
>
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Re: [Mesa-dev] [PATCH 5/9] meta: Refactor texture format translation

[Anuj Phogat]

On Tue, Dec 20, 2016 at 6:45 AM, Topi Pohjolainen
<topi.pohjolai...@gmail.com> wrote:
> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
> ---
>  src/mesa/drivers/common/meta_tex_subimage.c |  9 +++--
>  src/mesa/main/glformats.c   | 15 +++
>  src/mesa/main/glformats.h   |  4 
>  3 files changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/src/mesa/drivers/common/meta_tex_subimage.c 
> b/src/mesa/drivers/common/meta_tex_subimage.c
> index 703efcd..b8c422b 100644
> --- a/src/mesa/drivers/common/meta_tex_subimage.c
> +++ b/src/mesa/drivers/common/meta_tex_subimage.c
> @@ -72,7 +72,8 @@ create_texture_for_pbo(struct gl_context *ctx,
> const struct gl_pixelstore_attrib *packing,
> struct gl_buffer_object **tmp_pbo, GLuint *tmp_tex)
>  {
> -   uint32_t pbo_format;
> +   const mesa_format pbo_format =
> +  _mesa_tex_format_from_format_and_type(ctx, format, type);
> GLenum internal_format;
> unsigned row_stride;
> struct gl_buffer_object *buffer_obj;
> @@ -85,11 +86,7 @@ create_texture_for_pbo(struct gl_context *ctx,
> packing->Invert)
>return NULL;
>
> -   pbo_format = _mesa_format_from_format_and_type(format, type);
> -   if (_mesa_format_is_mesa_array_format(pbo_format))
> -  pbo_format = _mesa_format_from_array_format(pbo_format);
> -
> -   if (!pbo_format || !ctx->TextureFormatSupported[pbo_format])
> +   if (pbo_format == MESA_FORMAT_NONE)
>return NULL;
>
> /* Account for SKIP_PIXELS, SKIP_ROWS, ALIGNMENT, and SKIP_IMAGES */
> diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
> index a95909c..4f24020 100644
> --- a/src/mesa/main/glformats.c
> +++ b/src/mesa/main/glformats.c
> @@ -3632,6 +3632,21 @@ _mesa_format_from_format_and_type(GLenum format, 
> GLenum type)
> unreachable("Unsupported format");
>  }
>
> +uint32_t
> +_mesa_tex_format_from_format_and_type(const struct gl_context *ctx,
> +  GLenum gl_format, GLenum type)
> +{
> +   mesa_format format = _mesa_format_from_format_and_type(gl_format, type);
> +
> +   if (_mesa_format_is_mesa_array_format(format))
> +  format = _mesa_format_from_array_format(format);
> +
> +   if (format == MESA_FORMAT_NONE || !ctx->TextureFormatSupported[format])
> +  return MESA_FORMAT_NONE;
> +
> +   return format;
> +}
> +
>  /**
>   * Returns true if \p internal_format is a sized internal format that
>   * is marked "Color Renderable" in Table 8.10 of the ES 3.2 specification.
> diff --git a/src/mesa/main/glformats.h b/src/mesa/main/glformats.h
> index 763307f..5c9d826 100644
> --- a/src/mesa/main/glformats.h
> +++ b/src/mesa/main/glformats.h
> @@ -148,6 +148,10 @@ _mesa_base_tex_format(const struct gl_context *ctx, 
> GLint internalFormat );
>  extern uint32_t
>  _mesa_format_from_format_and_type(GLenum format, GLenum type);
>
> +extern uint32_t
> +_mesa_tex_format_from_format_and_type(const struct gl_context *ctx,
> +  GLenum gl_format, GLenum type);
> +
>  extern bool
>  _mesa_is_es3_color_renderable(GLenum internal_format);
>
> --
> 2.5.5
>
> ___
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Re: [Mesa-dev] [PATCH 3/9] intel/blorp/dbg: Name blit shaders for easy recognition in dumps

[Anuj Phogat]

On Tue, Dec 20, 2016 at 6:45 AM, Topi Pohjolainen
<topi.pohjolai...@gmail.com> wrote:
> Blorp clears already have an equivalent.
>
> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
> ---
>  src/intel/blorp/blorp_blit.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
> index 8abe3a8..9dcd33f 100644
> --- a/src/intel/blorp/blorp_blit.c
> +++ b/src/intel/blorp/blorp_blit.c
> @@ -1299,6 +1299,8 @@ brw_blorp_get_blit_kernel(struct blorp_context *blorp,
> struct brw_wm_prog_data prog_data;
>
> nir_shader *nir = brw_blorp_build_nir_shader(blorp, mem_ctx, prog_key);
> +   nir->info->name = ralloc_strdup(nir, "BLORP-blit");
> +
> struct brw_wm_prog_key wm_key;
> brw_blorp_init_wm_prog_key(_key);
> wm_key.tex.compressed_multisample_layout_mask =
> --
> 2.5.5
>
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Patches 1-3 are:
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH 9/9] i965: Drop _mesa_meta_pbo_TexSubImage() even for gen < 6

[Anuj Phogat]

On Tue, Dec 20, 2016 at 6:45 AM, Topi Pohjolainen
 wrote:
>
> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/intel_tex_image.c| 24 +++-
>  src/mesa/drivers/dri/i965/intel_tex_subimage.c | 19 +--
>  2 files changed, 12 insertions(+), 31 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c 
> b/src/mesa/drivers/dri/i965/intel_tex_image.c
> index 67f83db..e503043 100644
> --- a/src/mesa/drivers/dri/i965/intel_tex_image.c
> +++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
> @@ -127,7 +127,6 @@ intelTexImage(struct gl_context * ctx,
>  {
> struct brw_context *brw = brw_context(ctx);
> struct intel_texture_image *intelImage = intel_texture_image(texImage);
> -   bool ok;
>
> bool tex_busy = intelImage->mt && drm_intel_bo_busy(intelImage->mt->bo);
>
> @@ -156,22 +155,13 @@ intelTexImage(struct gl_context * ctx,
>format, type, pixels, unpack))
>return;
>
> -   if (brw->gen < 6 &&
> -   _mesa_meta_pbo_TexSubImage(ctx, dims, texImage, 0, 0, 0,
> -  texImage->Width, texImage->Height,
> -  texImage->Depth,
> -  format, type, pixels,
> -  tex_busy, unpack))
> -  return;
> -
> -   ok = intel_texsubimage_tiled_memcpy(ctx, dims, texImage,
> -   0, 0, 0, /*x,y,z offsets*/
> -   texImage->Width,
> -   texImage->Height,
> -   texImage->Depth,
> -   format, type, pixels, unpack,
> -   false /*allocate_storage*/);
> -   if (ok)
> +   if (intel_texsubimage_tiled_memcpy(ctx, dims, texImage,
> +  0, 0, 0, /*x,y,z offsets*/
> +  texImage->Width,
> +  texImage->Height,
> +  texImage->Depth,
> +  format, type, pixels, unpack,
> +  false /*allocate_storage*/))
>return;
>
> DBG("%s: upload image %dx%dx%d pixels %p\n",
> diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c 
> b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
> index 741637a..60dc862 100644
> --- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
> +++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
> @@ -395,7 +395,6 @@ intelTexSubImage(struct gl_context * ctx,
>  {
> struct brw_context *brw = brw_context(ctx);
> struct intel_mipmap_tree *mt = intel_texture_image(texImage)->mt;
> -   bool ok;
>
> bool tex_busy = mt && drm_intel_bo_busy(mt->bo);
>
> @@ -416,19 +415,11 @@ intelTexSubImage(struct gl_context * ctx,
>format, type, pixels, packing))
>return;
>
> -   ok = _mesa_meta_pbo_TexSubImage(ctx, dims, texImage,
> -   xoffset, yoffset, zoffset,
> -   width, height, depth, format, type,
> -   pixels, tex_busy, packing);
> -   if (ok)
> -  return;
> -
> -   ok = intel_texsubimage_tiled_memcpy(ctx, dims, texImage,
> -   xoffset, yoffset, zoffset,
> -   width, height, depth,
> -   format, type, pixels, packing,
> -   false /*for_glTexImage*/);
> -   if (ok)
> +   if (intel_texsubimage_tiled_memcpy(ctx, dims, texImage,
> +  xoffset, yoffset, zoffset,
> +  width, height, depth,
> +  format, type, pixels, packing,
> +  false /*for_glTexImage*/))
>   return;
>
> _mesa_store_texsubimage(ctx, dims, texImage,
> --
> 2.5.5
>
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It'll be useful if you can add a commit message explaning why it is
okay to drop the meta path on pre-gen6 platforms.
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Re: [Mesa-dev] [PATCH] glsl: Drop bogus is_vertex_input from add_shader_variable().

[Anuj Phogat]

On Fri, Dec 16, 2016 at 9:46 PM, Kenneth Graunke <kenn...@whitecape.org> wrote:
>
> stage_mask is a bitmask of shader stages, so the proper comparison would
> be (1 << MESA_SHADER_VERTEX), not MESA_SHADER_VERTEX itself.
>
> But we only care for structure types, and VS inputs cannot be structs.
> So we can just drop this entirely.
>
> Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
> ---
>  src/compiler/glsl/linker.cpp | 7 +--
>  1 file changed, 1 insertion(+), 6 deletions(-)
>
> Sorry, I forgot I split this into two patches...apply this one before
> [PATCH] glsl: Fix program interface queries relating to interface blocks.
>
> diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
> index 3660257..5066014 100644
> --- a/src/compiler/glsl/linker.cpp
> +++ b/src/compiler/glsl/linker.cpp
> @@ -3735,10 +3735,6 @@ add_shader_variable(const struct gl_context *ctx,
>  bool use_implicit_location, int location,
>  const glsl_type *outermost_struct_type = NULL)
>  {
> -   const bool is_vertex_input =
> -  programInterface == GL_PROGRAM_INPUT &&
> -  stage_mask == MESA_SHADER_VERTEX;
> -
> switch (type->base_type) {
> case GLSL_TYPE_STRUCT: {
>/* The ARB_program_interface_query spec says:
> @@ -3764,8 +3760,7 @@ add_shader_variable(const struct gl_context *ctx,
>outermost_struct_type))
>  return false;
>
> - field_location +=
> -field->type->count_attribute_slots(is_vertex_input);
> + field_location += field->type->count_attribute_slots(false);
>}
>return true;
> }
> --
> 2.10.2
>
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Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [Mesa-stable] [PATCH 1/2] i965/mt: Disable aux surfaces after making miptree shareable

[Anuj Phogat]

On Fri, Dec 9, 2016 at 4:32 PM, Chad Versace <chadvers...@chromium.org> wrote:
>
> The entire goal of intel_miptree_make_shareable() is to permanently
> disable the miptree's aux surfaces. So set
> intel_mipmap_tree:disable_aux_buffers after the function's done with
> discarding down the aux surfaces.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=98329
> Cc: Haixia Shi <h...@chromium.org>
> Cc: Topi Pohjolainen <topi.pohjolai...@intel.com>
> Cc: Nanley Chery <nanley.g.ch...@intel.com
> Cc: mesa-sta...@lists.freedesktop.org
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 7cda0190b4..15404dae32 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -2330,6 +2330,8 @@ intel_miptree_make_shareable(struct brw_context *brw,
>free(mt->mcs_buf);
>mt->mcs_buf = NULL;
> }
> +
> +   mt->disable_aux_buffers = true;
>  }
>
>
> --
> 2.11.0.rc2
>
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For both patches:
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH] i965/blit: Remove Yf/Ys tiled check under a FIXME at can_fast_copy_blit

[Anuj Phogat]

On Wed, Dec 7, 2016 at 3:38 AM, Alejandro Piñeiro <apinhe...@igalia.com> wrote:
>
>
> On 07/12/16 09:36, Alejandro Piñeiro wrote:
>> On 06/12/16 22:26, Anuj Phogat wrote:
>>> On Tue, Dec 6, 2016 at 10:58 AM, Alejandro Piñeiro <apinhe...@igalia.com> 
>>> wrote:
>>>> The FIXME suggest that the check should be removed.
>>>>
>>> Only if we see any performance or feature benefits in doing that.
>>> Last I checked I didn't see any performance benefits on Skylake.
>> Ok, then I misunderstood the comment. I understood that the code was
>> there based on performance data, but that it could be removed in the future.
>>
>>> I also couldn't figure out the cause of random failure in a piglit test:
>>>  ./bin/texelFetch fs sampler2DMSArray 4 98x1x9-98x129x9 -auto -fbo
>>>
>>> I'm still seeing this failure when I tested your patch with Jenkins CI 
>>> system.
>>> Test passes when I run it locally on my system.
>> Initially I also thought that failure was a regression of this patch.
>> But then I tested back without it, and I got some random failures too.
>
> FWIW, this is also flaky with and without the patch:
> bin/texelFetch fs sampler2DMSArray 4 1x129x9-98x129x9 -auto -fbo
>
Thanks for the information. It will be useful if we want to upstream this patch
sometime later.

>>
>>>> This change helps the following test:
>>>> GL45-CTS.texture_cube_map_array.color_depth_attachments
>>>>
>>>> to pass consistently on Skylake GT3e. Without this patch, on
>>>> Skylake GT3e that test has a ~76% pass rate, with some random
>>>> intel_do_flush_locked errors now and then.
>>>>
>>> By removing this check you're actually enabling fast copy blit on SKL+
>>> for all the tiling formats. So, now the driver will use XY_FAST_COPY_BLT
>>> in place of XY_SRC_COPY_BLT. If this change is fixing a test case for
>>> you, that's not because this is the right fix, but that's because you're
>>> avoiding to use XY_SRC_COPY_BLT.
>>> XY_SRC_COPY_BLT might be causing intel_do_flush_locked errors
>>> and the test failure. We need to dig in there to find the real cause.
>> Ok, thanks for the hints. Will resume the work based on this paragraph.
>> Any help would be appreciated though.
>>>> It works fine on Skylake GT2, though.
>>>> ---
>>>>
>>>> I didn't analyze too much the code. It was more git history analysis.
>>>>
>>>> When I started to work to solve that test, I remembered that there was
>>>> a time in the past that worked, so I just did a git bisect. The more
>>>> recent bad commit I found was df210f. In any case, that one just fixed
>>>> that check, as became broken with commit 0c02d7. The one that added
>>>> the check (and the FIXME) was commit 412c8c.
>>>>
>>>> As the commit message says, that FIXME seems to suggest that is a
>>>> provisional change. Although I recognize that the failure is really
>>>> specific (for a Skylake model, not failing always), removing the check
>>>> gets the test pass consistently, and as far as I see, it didn't
>>>> introduce any regression.
>>>>
>>>>  src/mesa/drivers/dri/i965/intel_blit.c | 8 
>>>>  1 file changed, 8 deletions(-)
>>>>
>>>> diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
>>>> b/src/mesa/drivers/dri/i965/intel_blit.c
>>>> index 03a35ee..9f3b4d1 100644
>>>> --- a/src/mesa/drivers/dri/i965/intel_blit.c
>>>> +++ b/src/mesa/drivers/dri/i965/intel_blit.c
>>>> @@ -487,14 +487,6 @@ can_fast_copy_blit(struct brw_context *brw,
>>>> if (brw->gen < 9)
>>>>return false;
>>>>
>>>> -   /* Enable fast copy blit only if the surfaces are Yf/Ys tiled.
>>>> -* FIXME: Based on performance data, remove this condition later to
>>>> -* enable for all types of surfaces.
>>>> -*/
>>>> -   if (src_tr_mode == INTEL_MIPTREE_TRMODE_NONE &&
>>>> -   dst_tr_mode == INTEL_MIPTREE_TRMODE_NONE)
>>>> -  return false;
>>>> -
>>>> if (logic_op != GL_COPY)
>>>>return false;
>>>>
>>>> --
>>>> 2.9.3
>>>>
>>
>
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Re: [Mesa-dev] [PATCH] i965/blit: Remove Yf/Ys tiled check under a FIXME at can_fast_copy_blit

[Anuj Phogat]

On Tue, Dec 6, 2016 at 4:26 PM, Anuj Phogat <anuj.pho...@gmail.com> wrote:
> On Tue, Dec 6, 2016 at 10:58 AM, Alejandro Piñeiro <apinhe...@igalia.com> 
> wrote:
>> The FIXME suggest that the check should be removed.
>>
> Only if we see any performance or feature benefits in doing that.
> Last I checked I didn't see any performance benefits on Skylake.
and that was more than 6 months back. Things might be different now.

> I also couldn't figure out the cause of random failure in a piglit test:
>  ./bin/texelFetch fs sampler2DMSArray 4 98x1x9-98x129x9 -auto -fbo
>
> I'm still seeing this failure when I tested your patch with Jenkins CI system.
> Test passes when I run it locally on my system.
>
>> This change helps the following test:
>> GL45-CTS.texture_cube_map_array.color_depth_attachments
>>
>> to pass consistently on Skylake GT3e. Without this patch, on
>> Skylake GT3e that test has a ~76% pass rate, with some random
>> intel_do_flush_locked errors now and then.
>>
> By removing this check you're actually enabling fast copy blit on SKL+
> for all the tiling formats. So, now the driver will use XY_FAST_COPY_BLT
> in place of XY_SRC_COPY_BLT. If this change is fixing a test case for
> you, that's not because this is the right fix, but that's because you're
> avoiding to use XY_SRC_COPY_BLT.
> XY_SRC_COPY_BLT might be causing intel_do_flush_locked errors
> and the test failure. We need to dig in there to find the real cause.
>
>> It works fine on Skylake GT2, though.
>> ---
>>
>> I didn't analyze too much the code. It was more git history analysis.
>>
>> When I started to work to solve that test, I remembered that there was
>> a time in the past that worked, so I just did a git bisect. The more
>> recent bad commit I found was df210f. In any case, that one just fixed
>> that check, as became broken with commit 0c02d7. The one that added
>> the check (and the FIXME) was commit 412c8c.
>>
>> As the commit message says, that FIXME seems to suggest that is a
>> provisional change. Although I recognize that the failure is really
>> specific (for a Skylake model, not failing always), removing the check
>> gets the test pass consistently, and as far as I see, it didn't
>> introduce any regression.
>>
>>  src/mesa/drivers/dri/i965/intel_blit.c | 8 
>>  1 file changed, 8 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
>> b/src/mesa/drivers/dri/i965/intel_blit.c
>> index 03a35ee..9f3b4d1 100644
>> --- a/src/mesa/drivers/dri/i965/intel_blit.c
>> +++ b/src/mesa/drivers/dri/i965/intel_blit.c
>> @@ -487,14 +487,6 @@ can_fast_copy_blit(struct brw_context *brw,
>> if (brw->gen < 9)
>>return false;
>>
>> -   /* Enable fast copy blit only if the surfaces are Yf/Ys tiled.
>> -* FIXME: Based on performance data, remove this condition later to
>> -* enable for all types of surfaces.
>> -*/
>> -   if (src_tr_mode == INTEL_MIPTREE_TRMODE_NONE &&
>> -   dst_tr_mode == INTEL_MIPTREE_TRMODE_NONE)
>> -  return false;
>> -
>> if (logic_op != GL_COPY)
>>return false;
>>
>> --
>> 2.9.3
>>
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Re: [Mesa-dev] [PATCH] i965/blit: Remove Yf/Ys tiled check under a FIXME at can_fast_copy_blit

[Anuj Phogat]

On Tue, Dec 6, 2016 at 10:58 AM, Alejandro Piñeiro  wrote:
> The FIXME suggest that the check should be removed.
>
Only if we see any performance or feature benefits in doing that.
Last I checked I didn't see any performance benefits on Skylake.
I also couldn't figure out the cause of random failure in a piglit test:
 ./bin/texelFetch fs sampler2DMSArray 4 98x1x9-98x129x9 -auto -fbo

I'm still seeing this failure when I tested your patch with Jenkins CI system.
Test passes when I run it locally on my system.

> This change helps the following test:
> GL45-CTS.texture_cube_map_array.color_depth_attachments
>
> to pass consistently on Skylake GT3e. Without this patch, on
> Skylake GT3e that test has a ~76% pass rate, with some random
> intel_do_flush_locked errors now and then.
>
By removing this check you're actually enabling fast copy blit on SKL+
for all the tiling formats. So, now the driver will use XY_FAST_COPY_BLT
in place of XY_SRC_COPY_BLT. If this change is fixing a test case for
you, that's not because this is the right fix, but that's because you're
avoiding to use XY_SRC_COPY_BLT.
XY_SRC_COPY_BLT might be causing intel_do_flush_locked errors
and the test failure. We need to dig in there to find the real cause.

> It works fine on Skylake GT2, though.
> ---
>
> I didn't analyze too much the code. It was more git history analysis.
>
> When I started to work to solve that test, I remembered that there was
> a time in the past that worked, so I just did a git bisect. The more
> recent bad commit I found was df210f. In any case, that one just fixed
> that check, as became broken with commit 0c02d7. The one that added
> the check (and the FIXME) was commit 412c8c.
>
> As the commit message says, that FIXME seems to suggest that is a
> provisional change. Although I recognize that the failure is really
> specific (for a Skylake model, not failing always), removing the check
> gets the test pass consistently, and as far as I see, it didn't
> introduce any regression.
>
>  src/mesa/drivers/dri/i965/intel_blit.c | 8 
>  1 file changed, 8 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
> b/src/mesa/drivers/dri/i965/intel_blit.c
> index 03a35ee..9f3b4d1 100644
> --- a/src/mesa/drivers/dri/i965/intel_blit.c
> +++ b/src/mesa/drivers/dri/i965/intel_blit.c
> @@ -487,14 +487,6 @@ can_fast_copy_blit(struct brw_context *brw,
> if (brw->gen < 9)
>return false;
>
> -   /* Enable fast copy blit only if the surfaces are Yf/Ys tiled.
> -* FIXME: Based on performance data, remove this condition later to
> -* enable for all types of surfaces.
> -*/
> -   if (src_tr_mode == INTEL_MIPTREE_TRMODE_NONE &&
> -   dst_tr_mode == INTEL_MIPTREE_TRMODE_NONE)
> -  return false;
> -
> if (logic_op != GL_COPY)
>return false;
>
> --
> 2.9.3
>
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Re: [Mesa-dev] [PATCH] i965: Allocate at least some URB space even when max_vertices = 0.

[Anuj Phogat]

On Mon, Dec 5, 2016 at 1:39 PM, Kenneth Graunke <kenn...@whitecape.org> wrote:
> Allocating zero URB space is a really bad idea.  The hardware has to
> give threads a handle to their URB space, and threads have to use that
> to terminate the thread.  Having it be an empty region just breaks a
> lot of assumptions.  Hence, why we asserted that it isn't possible.
>
> Unfortunately, it /is/ possible prior to Gen8, if max_vertices = 0.
> In theory a geometry shader could do SSBO/image access and maybe
> still accomplish something.  In reality, this is tripped up by
> conformance tests.
>
> Gen8+ already avoids this problem by placing the vertex count DWord
> in the URB entry header.  This fixes things on earlier generations.
>
> Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
> ---
>  src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 8 +++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
> index 900d9d3..3894a63 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
> @@ -781,7 +781,13 @@ brw_compile_gs(const struct brw_compiler *compiler, void 
> *log_data,
> if (compiler->devinfo->gen >= 8)
>output_size_bytes += 32;
>
> -   assert(output_size_bytes >= 1);
> +   /* Shaders can technically set max_vertices = 0, at which point we
> +* may have a URB size of 0 bytes.  Nothing good can come from that,
> +* so enforce a minimum size.
> +*/
> +   if (output_size_bytes == 0)
> +  output_size_bytes = 1;
> +
> unsigned max_output_size_bytes = GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES;
> if (compiler->devinfo->gen == 6)
>max_output_size_bytes = GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES;
> --
> 2.10.2
>
> ___
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Sounds reasonable to me.
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Re: [Mesa-dev] [PATCH 3/3] i965: Delete the meta-base CopyImageSubData implementation

[Anuj Phogat]

ffer);
> -   if (status != GL_FRAMEBUFFER_COMPLETE)
> -  goto meta_end;
> -
> -   /* Explicitly disable sRGB encoding */
> -   ctx->DrawBuffer->Visual.sRGBCapable = false;
> -
> -   /* Since we've bound a new draw framebuffer, we need to update its
> -* derived state -- _Xmin, etc -- for BlitFramebuffer's clipping to
> -* be correct.
> -*/
> -   _mesa_update_state(ctx);
> -
> -   /* We skip the core BlitFramebuffer checks for format consistency.
> -* We have already created views to ensure that the texture formats
> -* match.
> -*/
> -   ctx->Driver.BlitFramebuffer(ctx, ctx->ReadBuffer, ctx->DrawBuffer,
> -   src_x, src_y,
> -   src_x + src_width, src_y + src_height,
> -   dst_x, dst_y,
> -   dst_x + src_width, dst_y + src_height,
> -   mask, GL_NEAREST);
> -
> -   success = true;
> -
> -meta_end:
> -   _mesa_reference_framebuffer(, NULL);
> -   _mesa_reference_framebuffer(, NULL);
> -   _mesa_meta_end(ctx);
> -
> -cleanup:
> -   _mesa_DeleteTextures(1, _view_texture);
> -
> -   /* If we got a renderbuffer source, delete the temporary texture */
> -   if (src_renderbuffer && src_tex_image)
> -  ctx->Driver.DeleteTexture(ctx, src_tex_image->TexObject);
> -
> -   return success;
> -}
> diff --git a/src/mesa/drivers/dri/i965/intel_copy_image.c 
> b/src/mesa/drivers/dri/i965/intel_copy_image.c
> index 56eaed6..85585c7 100644
> --- a/src/mesa/drivers/dri/i965/intel_copy_image.c
> +++ b/src/mesa/drivers/dri/i965/intel_copy_image.c
> @@ -183,16 +183,6 @@ intel_copy_image_sub_data(struct gl_context *ctx,
> struct intel_mipmap_tree *src_mt, *dst_mt;
> unsigned src_level, dst_level;
>
> -   if (brw->gen < 6 &&
> -   _mesa_meta_CopyImageSubData_uncompressed(ctx,
> -src_image, src_renderbuffer,
> -src_x, src_y, src_z,
> -dst_image, dst_renderbuffer,
> -dst_x, dst_y, dst_z,
> -src_width, src_height)) {
> -  return;
> -   }
> -
> if (src_image) {
>src_mt = intel_texture_image(src_image)->mt;
>src_level = src_image->Level + src_image->TexObject->MinLevel;
> --
> 2.5.0.400.gff86faf
>
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Series is:
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Re: [Mesa-dev] [Mesa-stable] [PATCH] i965: Fix compute shader crash.

[Anuj Phogat]

On Thu, Nov 17, 2016 at 11:37 AM, Kenneth Graunke <kenn...@whitecape.org> wrote:
> Fixes crashes when starting Deus Ex: Mankind Divided.
>
> Cc: mesa-sta...@lists.freedesktop.org
> Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
> ---
>  src/mesa/drivers/dri/i965/brw_cs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_cs.c 
> b/src/mesa/drivers/dri/i965/brw_cs.c
> index ab445ab..72b2dbe 100644
> --- a/src/mesa/drivers/dri/i965/brw_cs.c
> +++ b/src/mesa/drivers/dri/i965/brw_cs.c
> @@ -223,7 +223,7 @@ brw_upload_cs_prog(struct brw_context *brw)
>   >cs.base.prog_data)) {
>bool success =
>   brw_codegen_cs_prog(brw,
> - ctx->Shader.CurrentProgram[MESA_SHADER_COMPUTE],
> + 
> ctx->_Shader->CurrentProgram[MESA_SHADER_COMPUTE],
>   cp, );
>(void) success;
>assert(success);
> --
> 2.10.2
>
> ___
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Re: [Mesa-dev] [PATCH] i965: Disable depth writes when depth test is GL_EQUAL.

[Anuj Phogat]

if (ctx->Depth.Test)
>   lookup |= IZ_DEPTH_TEST_ENABLE_BIT;
>
> -  if (ctx->Depth.Test && ctx->Depth.Mask) /* ?? */
> +  if (brw_depth_writes_enabled(brw))
>   lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
>
>/* _NEW_STENCIL | _NEW_BUFFERS */
> diff --git a/src/mesa/drivers/dri/i965/gen6_depthstencil.c 
> b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
> index a3de844..79d4d5d 100644
> --- a/src/mesa/drivers/dri/i965/gen6_depthstencil.c
> +++ b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
> @@ -83,7 +83,7 @@ gen6_upload_depth_stencil_state(struct brw_context *brw)
> if (ctx->Depth.Test && depth_irb) {
>ds->ds2.depth_test_enable = ctx->Depth.Test;
>ds->ds2.depth_test_func = 
> intel_translate_compare_func(ctx->Depth.Func);
> -  ds->ds2.depth_write_enable = ctx->Depth.Mask;
> +  ds->ds2.depth_write_enable = brw_depth_writes_enabled(brw);
> }
>
> /* Point the GPU at the new indirect state. */
> diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c 
> b/src/mesa/drivers/dri/i965/gen7_misc_state.c
> index 7bd5cd5..af9be66 100644
> --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
> +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
> @@ -109,7 +109,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
>   (depthbuffer_format << 18) |
>   ((hiz ? 1 : 0) << 22) |
>   ((stencil_mt != NULL && ctx->Stencil._WriteEnabled) << 27) |
> - ((ctx->Depth.Mask != 0) << 28) |
> + (brw_depth_writes_enabled(brw) << 28) |
>   (surftype << 29));
>
> /* 3DSTATE_DEPTH_BUFFER dw2 */
> diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c 
> b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> index 3604aee..14689f4 100644
> --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> @@ -218,7 +218,7 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
> }
>
> emit_depth_packets(brw, depth_mt, brw_depthbuffer_format(brw), surftype,
> -  ctx->Depth.Mask != 0,
> +  brw_depth_writes_enabled(brw),
>stencil_mt, ctx->Stencil._WriteEnabled,
>hiz, width, height, depth, lod, min_array_element);
>  }
> @@ -280,7 +280,7 @@ pma_fix_enable(const struct brw_context *brw)
>  * 3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
>  * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE.
>  */
> -   const bool depth_writes_enabled = ctx->Depth.Mask;
> +   const bool depth_writes_enabled = brw_depth_writes_enabled(brw);
>
> /* _NEW_STENCIL:
>  * !DEPTH_STENCIL_STATE::Stencil Buffer Write Enable ||
> diff --git a/src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c 
> b/src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c
> index e49103c..9a6c9e0 100644
> --- a/src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c
> +++ b/src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c
> @@ -90,7 +90,7 @@ gen8_upload_wm_depth_stencil(struct brw_context *brw)
>   GEN8_WM_DS_DEPTH_TEST_ENABLE |
>   FUNC(ctx->Depth.Func) << GEN8_WM_DS_DEPTH_FUNC_SHIFT;
>
> -  if (ctx->Depth.Mask)
> +  if (brw_depth_writes_enabled(brw))
>   dw1 |= GEN8_WM_DS_DEPTH_BUFFER_WRITE_ENABLE;
> }
>
> --
> 2.10.2
>
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Awesome. The changes look good to me.

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Re: [Mesa-dev] [PATCH 3/3] i965: Fix KBL typo in string

[Anuj Phogat]

On Thu, Nov 10, 2016 at 10:24 AM, Ben Widawsky <b...@bwidawsk.net> wrote:
> On 16-11-10 10:20:13, Ben Widawsky wrote:
>>
>> From: Ben Widawsky <b...@bwidawsk.net>
>>
>> Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
>> ---
>> include/pci_ids/i965_pci_ids.h | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/include/pci_ids/i965_pci_ids.h
>> b/include/pci_ids/i965_pci_ids.h
>> index fbc3999..b938332 100644
>> --- a/include/pci_ids/i965_pci_ids.h
>> +++ b/include/pci_ids/i965_pci_ids.h
>> @@ -153,7 +153,7 @@ CHIPSET(0x5913, kbl_gt1_5, "Intel(R) Kabylake GT1.5")
>> CHIPSET(0x5915, kbl_gt1_5, "Intel(R) Kabylake GT1.5")
>> CHIPSET(0x5917, kbl_gt1_5, "Intel(R) Kabylake GT1.5")
>> CHIPSET(0x5912, kbl_gt2, "Intel(R) Kabylake GT2")
>> -CHIPSET(0x5916, kbl_gt2, "Intel(R) HD Graphics 620 (Intel(R) Kabylake
>> GT2)")
>> +CHIPSET(0x5916, kbl_gt2, "Intel(R) HD Graphics 620 Kabylake GT2)")
>
>
> I suck.
> +CHIPSET(0x5916, kbl_gt2, "Intel(R) HD Graphics 620 (Kabylake GT2)")
>
>
>> CHIPSET(0x591A, kbl_gt2, "Intel(R) Kabylake GT2")
>> CHIPSET(0x591B, kbl_gt2, "Intel(R) Kabylake GT2")
>> CHIPSET(0x591D, kbl_gt2, "Intel(R) Kabylake GT2")
>> --
>> 2.10.2
>>
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Series is:
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Re: [Mesa-dev] [Intel-gfx] [PATCH] intel: Add Geminilake PCI IDs

[Anuj Phogat]

On Thu, Nov 10, 2016 at 10:28 AM, Ben Widawsky
<benjamin.widaw...@intel.com> wrote:
>
> From: Ben Widawsky <b...@bwidawsk.net>
>
> Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
> ---
>  intel/intel_chipset.h | 13 ++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
> index 514f659..41fc0da 100644
> --- a/intel/intel_chipset.h
> +++ b/intel/intel_chipset.h
> @@ -218,6 +218,9 @@
>  #define PCI_CHIP_BROXTON_3 0x1A85
>  #define PCI_CHIP_BROXTON_4 0x5A85
>
> +#define PCI_CHIP_GLK   0x3184
> +#define PCI_CHIP_GLK_2X6   0x3185
> +
>  #define IS_MOBILE(devid)   ((devid) == PCI_CHIP_I855_GM || \
>  (devid) == PCI_CHIP_I915_GM || \
>  (devid) == PCI_CHIP_I945_GM || \
> @@ -446,9 +449,13 @@
>  (devid) == PCI_CHIP_BROXTON_3  || \
>  (devid) == PCI_CHIP_BROXTON_4)
>
> -#define IS_GEN9(devid) (IS_SKYLAKE(devid) || \
> -IS_BROXTON(devid) || \
> -IS_KABYLAKE(devid))
> +#define IS_GEMINILAKE(devid)   ((devid) == PCI_CHIP_GLK || \
> +(devid) == PCI_CHIP_GLK_2X6)
> +
> +#define IS_GEN9(devid) (IS_SKYLAKE(devid)  || \
> +IS_BROXTON(devid)  || \
> +IS_KABYLAKE(devid) || \
> +IS_GEMINILAKE(devid))
>
>  #define IS_9XX(dev)(IS_GEN3(dev) || \
>  IS_GEN4(dev) || \
> --
> 2.10.2
>
> ___
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IDs cross checked in graphics specs.

Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH 2/2] i965/compiler: Disable trig workarounds on KBL+

[Anuj Phogat]

On Tue, Nov 8, 2016 at 1:21 PM, Jason Ekstrand  wrote:

> The precision of our trig instructions instructions appears to have been
>
​s/​instructions instructions/instructions

> fixed on Kaby Lake.  Neither Ben nor I can find any documentation for this.
> However, the dEQP precision tests now pass with INTEL_PRECISE_TRIG=0 where
> they fail on Sky Lake.
>
> Signed-off-by: Jason Ekstrand 
> ---
>  src/mesa/drivers/dri/i965/brw_nir.c   | 5 -
>  src/mesa/drivers/dri/i965/brw_nir_trig_workarounds.py | 7 ---
>  2 files changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_nir.c
> b/src/mesa/drivers/dri/i965/brw_nir.c
> index a93d825..1069438 100644
> --- a/src/mesa/drivers/dri/i965/brw_nir.c
> +++ b/src/mesa/drivers/dri/i965/brw_nir.c
> @@ -449,6 +449,7 @@ nir_optimize(nir_shader *nir, bool is_scalar)
>  nir_shader *
>  brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir)
>  {
> +   const struct gen_device_info *devinfo = compiler->devinfo;
> bool progress; /* Written by OPT and OPT_V */
> (void)progress;
>
> @@ -457,7 +458,9 @@ brw_preprocess_nir(const struct brw_compiler
> *compiler, nir_shader *nir)
> if (nir->stage == MESA_SHADER_GEOMETRY)
>OPT(nir_lower_gs_intrinsics);
>
> -   if (compiler->precise_trig)
> +   /* See also brw_nir_trig_workarounds.py */
> +   if (compiler->precise_trig &&
> +   !(devinfo->gen >= 10 || devinfo->is_kabylake))
>OPT(brw_nir_apply_trig_workarounds);
>
> static const nir_lower_tex_options tex_options = {
> diff --git a/src/mesa/drivers/dri/i965/brw_nir_trig_workarounds.py
> b/src/mesa/drivers/dri/i965/brw_nir_trig_workarounds.py
> index 67dab9a..3b8d0ce 100755
> --- a/src/mesa/drivers/dri/i965/brw_nir_trig_workarounds.py
> +++ b/src/mesa/drivers/dri/i965/brw_nir_trig_workarounds.py
> @@ -23,9 +23,10 @@
>
>  import nir_algebraic
>
> -# The SIN and COS instructions on Intel hardware can produce values
> -# slightly outside of the [-1.0, 1.0] range for a small set of values.
> -# Obviously, this can break everyone's expectations about trig functions.
> +# Prior to Kaby Lake, The SIN and COS instructions on Intel hardware can
> +# produce values slightly outside of the [-1.0, 1.0] range for a small
> set of
> +# values.  Obviously, this can break everyone's expectations about trig
> +# functions.  This appears to be fixed in Kaby Lake.
>  #
>  # According to an internal presentation, the COS instruction can produce
>  # a value up to 1.27 for inputs in the range (0.08296, 0.09888).  One
> --
> 2.5.0.400.gff86faf
>
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Re: [Mesa-dev] [PATCH 2/2] i965: Advertise 8 subpixel bits always.

[Anuj Phogat]

On Sun, Nov 6, 2016 at 10:45 PM, Chris Forbes <chr...@ijw.co.nz> wrote:

> The mesa default is 4, but we program the hardware for 8 on all
> generations.
>
> Signed-off-by: Chris Forbes <chrisfor...@google.com>
> ---
>  src/mesa/drivers/dri/i965/brw_context.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c
> b/src/mesa/drivers/dri/i965/brw_context.c
> index 3085a98..d8174c6 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -538,6 +538,7 @@ brw_initialize_context_constants(struct brw_context
> *brw)
>ctx->Const.MaxProgramTextureGatherComponents = 1;
>
> ctx->Const.MaxUniformBlockSize = 65536;
> +   ctx->Const.SubPixelBits = 8;
>
> for (int i = 0; i < MESA_SHADER_STAGES; i++) {
>struct gl_program_constants *prog = >Const.Program[i];
> --
> 2.10.2
>
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​Both patches are:
​

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Re: [Mesa-dev] [Mesa-stable] [PATCH] nir: Flip gl_SamplePosition in nir_lower_wpos_ytransform().

[Anuj Phogat]

On Tue, Nov 1, 2016 at 2:25 PM, Francisco Jerez <curroje...@riseup.net> wrote:
> Assuming the hardware is set-up to use a screen coordinate system
> flipped vertically with respect to the GL's window coordinate system,
> the SYSTEM_VALUE_SAMPLE_POS vector will also be flipped vertically
> with respect to the value expected by the GL, so we need to give it
> the same treatment as gl_FragCoord.  Fixes the following CTS tests on
> i965:
Makes sense.
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>

>
>  
> ES31-CTS.functional.shaders.multisample_interpolation.interpolate_at_offset.at_sample_position.default_framebuffer
>  
> ES31-CTS.functional.shaders.sample_variables.sample_pos.correctness.default_framebuffer
>
> when run with any multisample configuration, e.g. rgbad24s8ms4.
>
> Cc: <mesa-sta...@lists.freedesktop.org>
> ---
>  src/compiler/nir/nir_lower_wpos_ytransform.c | 24 
>  1 file changed, 24 insertions(+)
>
> diff --git a/src/compiler/nir/nir_lower_wpos_ytransform.c 
> b/src/compiler/nir/nir_lower_wpos_ytransform.c
> index 173f058..f211c73 100644
> --- a/src/compiler/nir/nir_lower_wpos_ytransform.c
> +++ b/src/compiler/nir/nir_lower_wpos_ytransform.c
> @@ -273,6 +273,26 @@ lower_interp_var_at_offset(lower_wpos_ytransform_state 
> *state,
>  }
>
>  static void
> +lower_load_sample_pos(lower_wpos_ytransform_state *state,
> +  nir_intrinsic_instr *intr)
> +{
> +   nir_builder *b = >b;
> +   b->cursor = nir_after_instr(>instr);
> +
> +   nir_ssa_def *pos = >dest.ssa;
> +   nir_ssa_def *scale = nir_channel(b, get_transform(state), 0);
> +   nir_ssa_def *neg_scale = nir_channel(b, get_transform(state), 2);
> +   /* Either y or 1-y for scale equal to 1 or -1 respectively. */
> +   nir_ssa_def *flipped_y =
> +   nir_fadd(b, nir_fmax(b, neg_scale, nir_imm_float(b, 0.0)),
> +nir_fmul(b, nir_channel(b, pos, 1), scale));
> +   nir_ssa_def *flipped_pos = nir_vec2(b, nir_channel(b, pos, 0), flipped_y);
> +
> +   nir_ssa_def_rewrite_uses_after(>dest.ssa, 
> nir_src_for_ssa(flipped_pos),
> +  flipped_pos->parent_instr);
> +}
> +
> +static void
>  lower_wpos_ytransform_block(lower_wpos_ytransform_state *state, nir_block 
> *block)
>  {
> nir_foreach_instr_safe(instr, block) {
> @@ -287,6 +307,10 @@ lower_wpos_ytransform_block(lower_wpos_ytransform_state 
> *state, nir_block *block
> /* gl_FragCoord should not have array/struct deref's: */
> assert(dvar->deref.child == NULL);
> lower_fragcoord(state, intr);
> +} else if (var->data.mode == nir_var_system_value &&
> +   var->data.location == SYSTEM_VALUE_SAMPLE_POS) {
> +   assert(dvar->deref.child == NULL);
> +   lower_load_sample_pos(state, intr);
>  }
>   } else if (intr->intrinsic == nir_intrinsic_interp_var_at_offset) {
>  lower_interp_var_at_offset(state, intr);
> --
> 2.10.1
>
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Re: [Mesa-dev] [PATCH] anv/device: Return DEVICE_LOST if execbuf2 fails

[Anuj Phogat]

On Mon, Oct 31, 2016 at 9:53 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote:
> This makes more sense than OUT_OF_HOST_MEMORY.  Technically, you can
> recover from a failed execbuf2 but the batch you just submitted didn't
> fully execute so things are in an ill-defined state.  The app doesn't want
> to continue from that point anyway.
> ---
>  src/intel/vulkan/anv_device.c | 10 --
>  1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
> index c995630..37615ef 100644
> --- a/src/intel/vulkan/anv_device.c
> +++ b/src/intel/vulkan/anv_device.c
> @@ -812,7 +812,7 @@ anv_device_submit_simple_batch(struct anv_device *device,
> ret = anv_gem_execbuffer(device, );
> if (ret != 0) {
>/* We don't know the real error. */
> -  result = vk_errorf(VK_ERROR_OUT_OF_DEVICE_MEMORY, "execbuf2 failed: 
> %m");
> +  result = vk_errorf(VK_ERROR_DEVICE_LOST, "execbuf2 failed: %m");
>goto fail;
> }
>
> @@ -820,7 +820,7 @@ anv_device_submit_simple_batch(struct anv_device *device,
> ret = anv_gem_wait(device, bo.gem_handle, );
> if (ret != 0) {
>/* We don't know the real error. */
> -  result = vk_errorf(VK_ERROR_OUT_OF_DEVICE_MEMORY, "execbuf2 failed: 
> %m");
> +  result = vk_errorf(VK_ERROR_DEVICE_LOST, "execbuf2 failed: %m");
>goto fail;
> }
>
> @@ -1090,8 +1090,7 @@ VkResult anv_QueueSubmit(
>   ret = anv_gem_execbuffer(device, _buffer->execbuf2.execbuf);
>   if (ret != 0) {
>  /* We don't know the real error. */
> -return vk_errorf(VK_ERROR_OUT_OF_DEVICE_MEMORY,
> - "execbuf2 failed: %m");
> +return vk_errorf(VK_ERROR_DEVICE_LOST, "execbuf2 failed: %m");
>   }
>
>   for (uint32_t k = 0; k < cmd_buffer->execbuf2.bo_count; k++)
> @@ -1103,8 +1102,7 @@ VkResult anv_QueueSubmit(
>ret = anv_gem_execbuffer(device, >execbuf);
>if (ret != 0) {
>   /* We don't know the real error. */
> - return vk_errorf(VK_ERROR_OUT_OF_DEVICE_MEMORY,
> -  "execbuf2 failed: %m");
> + return vk_errorf(VK_ERROR_DEVICE_LOST, "execbuf2 failed: %m");
>}
> }
>
> --
> 2.5.0.400.gff86faf
>
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Re: [Mesa-dev] [PATCH 1/3] intel: aubinator: don't print out blocks twice

[Anuj Phogat]

On Tue, Oct 25, 2016 at 4:49 AM, Lionel Landwerlin
<llandwer...@gmail.com> wrote:
> Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
> ---
>  src/intel/tools/aubinator.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
> index 31c1f89..11709c8 100644
> --- a/src/intel/tools/aubinator.c
> +++ b/src/intel/tools/aubinator.c
> @@ -974,7 +974,6 @@ aub_file_decode_batch(struct aub_file *file, struct 
> gen_spec *spec)
>break;
> case MAKE_HEADER(TYPE_AUB, OPCODE_AUB, SUBOPCODE_BLOCK):
>payload_size = p[4];
> -  handle_trace_block(spec, p);
>break;
> default:
>break;
> --
> 2.9.3
>
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Re: [Mesa-dev] [PATCH 2/2] i965: Move gen8_disable_stages to brw_upload_initial_gpu_state

[Anuj Phogat]

   BEGIN_BATCH(5);
> -   OUT_BATCH(_3DSTATE_WM_HZ_OP << 16 | (5 - 2));
> -   OUT_BATCH(0);
> -   OUT_BATCH(0);
> -   OUT_BATCH(0);
> -   OUT_BATCH(0);
> -   ADVANCE_BATCH();
> -
> -   BEGIN_BATCH(2);
> -   OUT_BATCH(_3DSTATE_WM_CHROMAKEY << 16 | (2 - 2));
> -   OUT_BATCH(0);
> -   ADVANCE_BATCH();
> -}
> -
> -const struct brw_tracked_state gen8_disable_stages = {
> -   .dirty = {
> -  .mesa  = 0,
> -  .brw   = BRW_NEW_BLORP |
> -   BRW_NEW_CONTEXT,
> -   },
> -   .emit = disable_stages,
> -};
> --
> 2.10.1
>
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LGTM.
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Re: [Mesa-dev] [PATCH 1/2] i965: Program 3DSTATE_AA_LINE_PARAMETERS in upload_invariant_state

[Anuj Phogat]

On Wed, Oct 26, 2016 at 11:23 AM, Nanley Chery <nanleych...@gmail.com> wrote:
> This packet is non-pipelined and doesn't ever change across emissions.
>
> Signed-off-by: Nanley Chery <nanley.g.ch...@intel.com>
> ---
>  src/mesa/drivers/dri/i965/brw_misc_state.c   | 41 
> +++-
>  src/mesa/drivers/dri/i965/brw_state.h|  1 -
>  src/mesa/drivers/dri/i965/brw_state_upload.c |  4 ---
>  3 files changed, 10 insertions(+), 36 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
> b/src/mesa/drivers/dri/i965/brw_misc_state.c
> index cc62dab..9997db6 100644
> --- a/src/mesa/drivers/dri/i965/brw_misc_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
> @@ -795,37 +795,6 @@ const struct brw_tracked_state 
> brw_polygon_stipple_offset = {
>  };
>
>  /**
> - * AA Line parameters
> - */
> -static void
> -upload_aa_line_parameters(struct brw_context *brw)
> -{
> -   struct gl_context *ctx = >ctx;
> -
> -   if (!ctx->Line.SmoothFlag)
> -  return;
> -
> -   /* Original Gen4 doesn't have 3DSTATE_AA_LINE_PARAMETERS. */
> -   if (brw->gen == 4 && !brw->is_g4x)
> -  return;
> -
> -   BEGIN_BATCH(3);
> -   OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS << 16 | (3 - 2));
> -   /* use legacy aa line coverage computation */
> -   OUT_BATCH(0);
> -   OUT_BATCH(0);
> -   ADVANCE_BATCH();
> -}
> -
> -const struct brw_tracked_state brw_aa_line_parameters = {
> -   .dirty = {
> -  .mesa = _NEW_LINE,
> -  .brw = BRW_NEW_CONTEXT,
> -   },
> -   .emit = upload_aa_line_parameters
> -};
> -
> -/**
>   * Line stipple packet
>   */
>  static void
> @@ -1029,6 +998,16 @@ brw_upload_invariant_state(struct brw_context *brw)
>ADVANCE_BATCH();
> }
>
> +   /* Original Gen4 doesn't have 3DSTATE_AA_LINE_PARAMETERS. */
> +   if (!is_965) {
> +  BEGIN_BATCH(3);
> +  OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS << 16 | (3 - 2));
> +  /* use legacy aa line coverage computation */
> +  OUT_BATCH(0);
> +  OUT_BATCH(0);
> +  ADVANCE_BATCH();
> +   }
> +
> const uint32_t _3DSTATE_VF_STATISTICS =
>is_965 ? GEN4_3DSTATE_VF_STATISTICS : GM45_3DSTATE_VF_STATISTICS;
> BEGIN_BATCH(1);
> diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
> b/src/mesa/drivers/dri/i965/brw_state.h
> index 1420aab..75e497f 100644
> --- a/src/mesa/drivers/dri/i965/brw_state.h
> +++ b/src/mesa/drivers/dri/i965/brw_state.h
> @@ -57,7 +57,6 @@ extern const struct brw_tracked_state brw_invariant_state;
>  extern const struct brw_tracked_state brw_fs_samplers;
>  extern const struct brw_tracked_state brw_gs_unit;
>  extern const struct brw_tracked_state brw_line_stipple;
> -extern const struct brw_tracked_state brw_aa_line_parameters;
>  extern const struct brw_tracked_state brw_binding_table_pointers;
>  extern const struct brw_tracked_state brw_depthbuffer;
>  extern const struct brw_tracked_state brw_polygon_stipple_offset;
> diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
> b/src/mesa/drivers/dri/i965/brw_state_upload.c
> index 015ea6e..2461ee5 100644
> --- a/src/mesa/drivers/dri/i965/brw_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
> @@ -90,7 +90,6 @@ static const struct brw_tracked_state *gen4_atoms[] =
> _polygon_stipple_offset,
>
> _line_stipple,
> -   _aa_line_parameters,
>
> _psp_urb_cbs,
>
> @@ -160,7 +159,6 @@ static const struct brw_tracked_state *gen6_atoms[] =
> _polygon_stipple_offset,
>
> _line_stipple,
> -   _aa_line_parameters,
>
> _drawing_rect,
>
> @@ -251,7 +249,6 @@ static const struct brw_tracked_state 
> *gen7_render_atoms[] =
> _polygon_stipple_offset,
>
> _line_stipple,
> -   _aa_line_parameters,
>
> _drawing_rect,
>
> @@ -360,7 +357,6 @@ static const struct brw_tracked_state 
> *gen8_render_atoms[] =
> _polygon_stipple_offset,
>
> _line_stipple,
> -   _aa_line_parameters,
>
> _drawing_rect,
>
> --
> 2.10.1
>
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I think it should be fine programming it in brw_upload_invariant_state().

Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH v2 4/6] i965/blit: Break blits into chunks in set_alpha_to_one

[Anuj Phogat]

SET_FIELD(x + chunk_x + chunk_w, BLT_X));
> + if (brw->gen >= 8) {
> +OUT_RELOC64(mt->bo,
> +I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
> +offset);
> + } else {
> +OUT_RELOC(mt->bo,
> +  I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
> +  offset);
> + }
> + OUT_BATCH(0x); /* white, but only alpha gets written */
> + ADVANCE_BATCH_TILED(dst_y_tiled, false);
> +  }
> }
> -   OUT_BATCH(0x); /* white, but only alpha gets written */
> -   ADVANCE_BATCH_TILED(dst_y_tiled, false);
>
> brw_emit_mi_flush(brw);
>  }
> --
> 2.5.0.400.gff86faf
>
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Re: [Mesa-dev] [PATCH 4/4] mesa: rename gl_client_array -> gl_vertex_array

[Anuj Phogat]

 struct gl_client_array *arrays[],
> +   const struct gl_vertex_array *arrays[],
> const struct _mesa_prim *prim,
> GLuint nr_prims,
> const struct _mesa_index_buffer *ib,
> @@ -62,7 +62,7 @@ void vbo_split_inplace( struct gl_context *ctx,
>  /* Requires ib != NULL:
>   */
>  void vbo_split_copy( struct gl_context *ctx,
> -const struct gl_client_array *arrays[],
> +const struct gl_vertex_array *arrays[],
>  const struct _mesa_prim *prim,
>  GLuint nr_prims,
>  const struct _mesa_index_buffer *ib,
> diff --git a/src/mesa/vbo/vbo_split_copy.c b/src/mesa/vbo/vbo_split_copy.c
> index ac4fe9e..ce8831d 100644
> --- a/src/mesa/vbo/vbo_split_copy.c
> +++ b/src/mesa/vbo/vbo_split_copy.c
> @@ -52,7 +52,7 @@
>  struct copy_context {
>
> struct gl_context *ctx;
> -   const struct gl_client_array **array;
> +   const struct gl_vertex_array **array;
> const struct _mesa_prim *prim;
> GLuint nr_prims;
> const struct _mesa_index_buffer *ib;
> @@ -63,15 +63,15 @@ struct copy_context {
> struct {
>GLuint attr;
>GLuint size;
> -  const struct gl_client_array *array;
> +  const struct gl_vertex_array *array;
>const GLubyte *src_ptr;
>
> -  struct gl_client_array dstarray;
> +  struct gl_vertex_array dstarray;
>
> } varying[VERT_ATTRIB_MAX];
> GLuint nr_varying;
>
> -   const struct gl_client_array *dstarray_ptr[VERT_ATTRIB_MAX];
> +   const struct gl_vertex_array *dstarray_ptr[VERT_ATTRIB_MAX];
> struct _mesa_index_buffer dstib;
>
> GLuint *translated_elt_buf;
> @@ -104,7 +104,7 @@ struct copy_context {
>  };
>
>
> -static GLuint attr_size( const struct gl_client_array *array )
> +static GLuint attr_size( const struct gl_vertex_array *array )
>  {
> return array->Size * _mesa_sizeof_type(array->Type);
>  }
> @@ -140,7 +140,7 @@ check_flush( struct copy_context *copy )
>   */
>  static void
>  dump_draw_info(struct gl_context *ctx,
> -   const struct gl_client_array **arrays,
> + 

Re: [Mesa-dev] [PATCH 4/4] i965: Fix alpha-to-coverage and alpha test enabled checks

[Anuj Phogat]

On Tue, Oct 25, 2016 at 4:36 PM, Ilia Mirkin <imir...@alum.mit.edu> wrote:
> On Tue, Oct 25, 2016 at 7:09 PM, Anuj Phogat <anuj.pho...@gmail.com> wrote:
>> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
>> ---
>>  src/mesa/drivers/dri/i965/brw_wm.c   | 4 ++--
>>  src/mesa/drivers/dri/i965/gen6_wm_state.c| 5 +++--
>>  src/mesa/drivers/dri/i965/gen7_wm_state.c| 5 +++--
>>  src/mesa/drivers/dri/i965/gen8_depth_state.c | 4 ++--
>>  4 files changed, 10 insertions(+), 8 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_wm.c 
>> b/src/mesa/drivers/dri/i965/brw_wm.c
>> index f782da1..df54fb4 100644
>> --- a/src/mesa/drivers/dri/i965/brw_wm.c
>> +++ b/src/mesa/drivers/dri/i965/brw_wm.c
>> @@ -529,7 +529,8 @@ brw_wm_populate_key(struct brw_context *brw, struct 
>> brw_wm_prog_key *key)
>>
>> /* _NEW_MULTISAMPLE, _NEW_COLOR, _NEW_BUFFERS */
>> key->replicate_alpha = ctx->DrawBuffer->_NumColorDrawBuffers > 1 &&
>> -  (ctx->Multisample.SampleAlphaToCoverage || ctx->Color.AlphaEnabled);
>> +  (_mesa_is_alpha_test_enabled(ctx) ||
>> +   _mesa_is_alpha_to_coverage_enabled(ctx));
>>
>> /* _NEW_BUFFERS _NEW_MULTISAMPLE */
>> /* Ignore sample qualifier while computing this flag. */
>> @@ -549,7 +550,6 @@ brw_wm_populate_key(struct brw_context *brw, struct 
>> brw_wm_prog_key *key)
>>key->input_slots_valid = brw->vue_map_geom_out.slots_valid;
>> }
>>
>> -
>> /* _NEW_COLOR | _NEW_BUFFERS */
>> /* Pre-gen6, the hardware alpha test always used each render
>>  * target's alpha to do alpha test, as opposed to render target 0's alpha
>> diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c 
>> b/src/mesa/drivers/dri/i965/gen6_wm_state.c
>> index 711e2fd..28fcc1c 100644
>> --- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
>> +++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
>> @@ -253,8 +253,9 @@ upload_wm_state(struct brw_context *brw)
>>ctx->Color.Blend[0]._UsesDualSrc;
>>
>> /* _NEW_COLOR, _NEW_MULTISAMPLE */
>
> Should probably update this to include _NEW_BUFFERS, otherwise you'll
> miss updates. (Too lazy to check on whether the atom lists that
> already for other reasons.) Similar comment for gen7_wm_state and
> gen8_depth_state.
>
_NEW_BUFFERS is already the part of state atoms in all three changes.
I've anyways added it locally in the comments. Thanks.

>> -   const bool kill_enable = prog_data->uses_kill || ctx->Color.AlphaEnabled 
>> ||
>> -ctx->Multisample.SampleAlphaToCoverage ||
>> +   const bool kill_enable = prog_data->uses_kill ||
>> +_mesa_is_alpha_test_enabled(ctx) ||
>> +_mesa_is_alpha_to_coverage_enabled(ctx) ||
>>  prog_data->uses_omask;
>>
>> /* Rendering against the gl-context is always taken into account. */
>> diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c 
>> b/src/mesa/drivers/dri/i965/gen7_wm_state.c
>> index 110c02c..7226196 100644
>> --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
>> +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
>> @@ -72,8 +72,9 @@ upload_wm_state(struct brw_context *brw)
>> /* _NEW_COLOR, _NEW_MULTISAMPLE */
>> /* Enable if the pixel shader kernel generates and outputs oMask.
>>  */
>> -   if (prog_data->uses_kill || ctx->Color.AlphaEnabled ||
>> -   ctx->Multisample.SampleAlphaToCoverage ||
>> +   if (prog_data->uses_kill ||
>> +   _mesa_is_alpha_test_enabled(ctx) ||
>> +   _mesa_is_alpha_to_coverage_enabled(ctx) ||
>> prog_data->uses_omask) {
>>dw1 |= GEN7_WM_KILL_ENABLE;
>> }
>> diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c 
>> b/src/mesa/drivers/dri/i965/gen8_depth_state.c
>> index 73b2186..8249694 100644
>> --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
>> +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
>> @@ -304,8 +304,8 @@ pma_fix_enable(const struct brw_context *brw)
>> const bool kill_pixel =
>>wm_prog_data->uses_kill ||
>>wm_prog_data->uses_omask ||
>> -  (_mesa_is_multisample_enabled(ctx) && 
>> ctx->Multisample.SampleAlphaToCoverage) ||
>> -  ctx->Color.AlphaEnabled;
>> +  _mesa_is_alpha_test_enabled(ctx) ||
>> +  _mesa_is_alpha_to_coverage_enabled(ctx);
>>
>> /* The big formula in CACHE_MODE_1::NP PMA FIX ENABLE. */
>> return !wm_force_thread_dispatch &&
>> --
>> 2.5.5
>>
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Re: [Mesa-dev] [PATCH 2/4] mesa: Add helper function _mesa_is_alpha_test_enabled()

[Anuj Phogat]

On Tue, Oct 25, 2016 at 5:14 PM, Brian Paul <bri...@vmware.com> wrote:
> On 10/25/2016 04:09 PM, Anuj Phogat wrote:
>>
>> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
>> ---
>>   src/mesa/main/framebuffer.c | 7 +++
>>   src/mesa/main/framebuffer.h | 3 +++
>>   2 files changed, 10 insertions(+)
>>
>> diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c
>> index e1505fa..f19f3af 100644
>> --- a/src/mesa/main/framebuffer.c
>> +++ b/src/mesa/main/framebuffer.c
>> @@ -1005,3 +1005,10 @@ _mesa_is_multisample_enabled(const struct
>> gl_context *ctx)
>> ctx->DrawBuffer &&
>> _mesa_geometric_nonvalidated_samples(ctx->DrawBuffer) > 1;
>>   }
>> +
>> +bool
>> +_mesa_is_alpha_test_enabled(const struct gl_context *ctx)
>> +{
>> +   bool buffer0_is_integer = ctx->DrawBuffer->_IntegerBuffers & 0x1;
>> +   return (ctx->Color.AlphaEnabled && !buffer0_is_integer);
>> +}
>> diff --git a/src/mesa/main/framebuffer.h b/src/mesa/main/framebuffer.h
>> index 384f749..a6adb1c 100644
>> --- a/src/mesa/main/framebuffer.h
>> +++ b/src/mesa/main/framebuffer.h
>> @@ -149,4 +149,7 @@ _mesa_is_front_buffer_drawing(const struct
>> gl_framebuffer *fb);
>>   extern bool
>>   _mesa_is_multisample_enabled(const struct gl_context *ctx);
>>
>> +extern bool
>> +_mesa_is_alpha_test_enabled(const struct gl_context *ctx);
>> +
>>   #endif /* FRAMEBUFFER_H */
>>
>
> Could you add a comment on this function such as:
>
> /**
>  * Is alpha testing enabled and applicable to the currently bound
> framebuffer?
>  */
>
> Same thing for _mesa_is_alpha_to_coverage_enabled()?
Added locally. Thanks.
>
> For patches 1-3, Reviewed-by: Brian Paul <bri...@vmware.com>
>
>
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[Mesa-dev] [PATCH 3/4] mesa: Add helper function _mesa_is_alpha_to_coverage_enabled()

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/mesa/main/framebuffer.c | 9 +
 src/mesa/main/framebuffer.h | 3 +++
 2 files changed, 12 insertions(+)

diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c
index f19f3af..3aff102 100644
--- a/src/mesa/main/framebuffer.c
+++ b/src/mesa/main/framebuffer.c
@@ -1012,3 +1012,12 @@ _mesa_is_alpha_test_enabled(const struct gl_context *ctx)
bool buffer0_is_integer = ctx->DrawBuffer->_IntegerBuffers & 0x1;
return (ctx->Color.AlphaEnabled && !buffer0_is_integer);
 }
+
+bool
+_mesa_is_alpha_to_coverage_enabled(const struct gl_context *ctx)
+{
+   bool buffer0_is_integer = ctx->DrawBuffer->_IntegerBuffers & 0x1;
+   return (ctx->Multisample.SampleAlphaToCoverage &&
+   _mesa_is_multisample_enabled(ctx) &&
+   !buffer0_is_integer);
+}
diff --git a/src/mesa/main/framebuffer.h b/src/mesa/main/framebuffer.h
index a6adb1c..745c1da 100644
--- a/src/mesa/main/framebuffer.h
+++ b/src/mesa/main/framebuffer.h
@@ -152,4 +152,7 @@ _mesa_is_multisample_enabled(const struct gl_context *ctx);
 extern bool
 _mesa_is_alpha_test_enabled(const struct gl_context *ctx);
 
+extern bool
+_mesa_is_alpha_to_coverage_enabled(const struct gl_context *ctx);
+
 #endif /* FRAMEBUFFER_H */
-- 
2.5.5

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[Mesa-dev] [PATCH 2/4] mesa: Add helper function _mesa_is_alpha_test_enabled()

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/mesa/main/framebuffer.c | 7 +++
 src/mesa/main/framebuffer.h | 3 +++
 2 files changed, 10 insertions(+)

diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c
index e1505fa..f19f3af 100644
--- a/src/mesa/main/framebuffer.c
+++ b/src/mesa/main/framebuffer.c
@@ -1005,3 +1005,10 @@ _mesa_is_multisample_enabled(const struct gl_context 
*ctx)
   ctx->DrawBuffer &&
   _mesa_geometric_nonvalidated_samples(ctx->DrawBuffer) > 1;
 }
+
+bool
+_mesa_is_alpha_test_enabled(const struct gl_context *ctx)
+{
+   bool buffer0_is_integer = ctx->DrawBuffer->_IntegerBuffers & 0x1;
+   return (ctx->Color.AlphaEnabled && !buffer0_is_integer);
+}
diff --git a/src/mesa/main/framebuffer.h b/src/mesa/main/framebuffer.h
index 384f749..a6adb1c 100644
--- a/src/mesa/main/framebuffer.h
+++ b/src/mesa/main/framebuffer.h
@@ -149,4 +149,7 @@ _mesa_is_front_buffer_drawing(const struct gl_framebuffer 
*fb);
 extern bool
 _mesa_is_multisample_enabled(const struct gl_context *ctx);
 
+extern bool
+_mesa_is_alpha_test_enabled(const struct gl_context *ctx);
+
 #endif /* FRAMEBUFFER_H */
-- 
2.5.5

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[Mesa-dev] [PATCH 4/4] i965: Fix alpha-to-coverage and alpha test enabled checks

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/mesa/drivers/dri/i965/brw_wm.c   | 4 ++--
 src/mesa/drivers/dri/i965/gen6_wm_state.c| 5 +++--
 src/mesa/drivers/dri/i965/gen7_wm_state.c| 5 +++--
 src/mesa/drivers/dri/i965/gen8_depth_state.c | 4 ++--
 4 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm.c 
b/src/mesa/drivers/dri/i965/brw_wm.c
index f782da1..df54fb4 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -529,7 +529,8 @@ brw_wm_populate_key(struct brw_context *brw, struct 
brw_wm_prog_key *key)
 
/* _NEW_MULTISAMPLE, _NEW_COLOR, _NEW_BUFFERS */
key->replicate_alpha = ctx->DrawBuffer->_NumColorDrawBuffers > 1 &&
-  (ctx->Multisample.SampleAlphaToCoverage || ctx->Color.AlphaEnabled);
+  (_mesa_is_alpha_test_enabled(ctx) ||
+   _mesa_is_alpha_to_coverage_enabled(ctx));
 
/* _NEW_BUFFERS _NEW_MULTISAMPLE */
/* Ignore sample qualifier while computing this flag. */
@@ -549,7 +550,6 @@ brw_wm_populate_key(struct brw_context *brw, struct 
brw_wm_prog_key *key)
   key->input_slots_valid = brw->vue_map_geom_out.slots_valid;
}
 
-
/* _NEW_COLOR | _NEW_BUFFERS */
/* Pre-gen6, the hardware alpha test always used each render
 * target's alpha to do alpha test, as opposed to render target 0's alpha
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c 
b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index 711e2fd..28fcc1c 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -253,8 +253,9 @@ upload_wm_state(struct brw_context *brw)
   ctx->Color.Blend[0]._UsesDualSrc;
 
/* _NEW_COLOR, _NEW_MULTISAMPLE */
-   const bool kill_enable = prog_data->uses_kill || ctx->Color.AlphaEnabled ||
-ctx->Multisample.SampleAlphaToCoverage ||
+   const bool kill_enable = prog_data->uses_kill ||
+_mesa_is_alpha_test_enabled(ctx) ||
+_mesa_is_alpha_to_coverage_enabled(ctx) ||
 prog_data->uses_omask;
 
/* Rendering against the gl-context is always taken into account. */
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c 
b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 110c02c..7226196 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -72,8 +72,9 @@ upload_wm_state(struct brw_context *brw)
/* _NEW_COLOR, _NEW_MULTISAMPLE */
/* Enable if the pixel shader kernel generates and outputs oMask.
 */
-   if (prog_data->uses_kill || ctx->Color.AlphaEnabled ||
-   ctx->Multisample.SampleAlphaToCoverage ||
+   if (prog_data->uses_kill ||
+   _mesa_is_alpha_test_enabled(ctx) ||
+   _mesa_is_alpha_to_coverage_enabled(ctx) ||
prog_data->uses_omask) {
   dw1 |= GEN7_WM_KILL_ENABLE;
}
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c 
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 73b2186..8249694 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -304,8 +304,8 @@ pma_fix_enable(const struct brw_context *brw)
const bool kill_pixel =
   wm_prog_data->uses_kill ||
   wm_prog_data->uses_omask ||
-  (_mesa_is_multisample_enabled(ctx) && 
ctx->Multisample.SampleAlphaToCoverage) ||
-  ctx->Color.AlphaEnabled;
+  _mesa_is_alpha_test_enabled(ctx) ||
+  _mesa_is_alpha_to_coverage_enabled(ctx);
 
/* The big formula in CACHE_MODE_1::NP PMA FIX ENABLE. */
return !wm_force_thread_dispatch &&
-- 
2.5.5

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