[Qemu-devel] [Bug 1513234] Re: Cannot ping guest from host after closing laptop lid, and re-opening
[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1513234 Title: Cannot ping guest from host after closing laptop lid, and re-opening Status in QEMU: Expired Bug description: I am running Ubuntu 15.10 (this issue also exists on 15.04) x64. Desktop environment to re-produce is either GNOME 3.16 or OpenBox-3. I have a Windows 8.1 VM that I run with QEMU and I will work out of that for my job most of the day. When I am going to leave I like to just close my laptop lid, come home, and then get back at it. Unfortunately whenever I get home and open back up my laptop, I can no longer RDP into my VM and can no longer ping it from the host. If I open up Virt-Manager I can see the desktop via the Console page but cannot RDP into it with FreeRDP (I use FreeRDP all day on this machine so I know this works fine). If I use the Console tab to login to the Windows VM again, I notice that I can ping the host from the guest and am connected to the internet. Just can't seem to communicate with the VM via its IP anymore. I have a NIC NAT virtual card and am using a Bridge To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1513234/+subscriptions
[Qemu-devel] [Bug 1800786] Re: USB assertion `s->csw.sig == cpu_to_le32(0x53425355)' failed
[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1800786 Title: USB assertion `s->csw.sig == cpu_to_le32(0x53425355)' failed Status in QEMU: Expired Bug description: Qemu crashed after starting and stopping VM for many times, and the final log shows below. qemu-system-x86_64: hw/usb/dev-storage.c:236: usb_msd_send_status: Assertion `s->csw.sig == cpu_to_le32(0x53425355)' failed. 2018-10-05 15:33:11.261+: shutting down I got the back trace in coredump file: ---back trace #0 0x7fc890e6cff9 in __GI_raise (sig=sig@entry=6) at ../nptl/sysdeps/unix/sysv/linux/raise.c:56 #1 0x7fc890e700f8 in __GI_abort () at abort.c:89 #2 0x7fc890e66216 in __assert_fail_base ( fmt=0x7fc890f9dfc0 "%s%s%s:%u: %s%sAssertion `%s' failed.\n%n", assertion=assertion@entry=0x7fc8957cd460 "s->csw.sig == cpu_to_le32(0x53425355)", file=file@entry=0x7fc8957cd2d0 "hw/usb/dev-storage.c", line=line@entry=236, function=function@entry=0x7fc8957cd5e0 <__PRETTY_FUNCTION__.29765> "usb_msd_send_status") at assert.c:92 #3 0x7fc890e662c2 in __GI___assert_fail ( assertion=assertion@entry=0x7fc8957cd460 "s->csw.sig == cpu_to_le32(0x53425355)", file=file@entry=0x7fc8957cd2d0 "hw/usb/dev-storage.c", line=line@entry=236, function=function@entry=0x7fc8957cd5e0 <__PRETTY_FUNCTION__.29765> "usb_msd_send_status") at assert.c:101 #4 0x7fc8955dee12 in usb_msd_send_status (s=0x7fc8961588f0, p=) at hw/usb/dev-storage.c:236 #5 0x7fc8955df092 in usb_msd_handle_data (dev=0x7fc8961588f0, p=0x7fc896105260) at hw/usb/dev-storage.c:507 #6 0x7fc8955d5940 in usb_handle_packet (dev=, p=p@entry=0x7fc896105260) at hw/usb/core.c:407 #7 0x7fc8955ea8a8 in uhci_handle_td (s=s@entry=0x7fc896133080, ---Type to continue, or q to quit--- q=0x7fc896197c90, q@entry=0x0, qh_addr=qh_addr@entry=253943810, td=td@entry=0x7ffcc646c0e0, td_addr=, int_mask=int_mask@entry=0x7ffcc646c0cc) at hw/usb/hcd-uhci.c:911 #8 0x7fc8955eada9 in uhci_process_frame (s=s@entry=0x7fc896133080) at hw/usb/hcd-uhci.c:1091 #9 0x7fc8955eaff5 in uhci_frame_timer (opaque=0x7fc896133080) at hw/usb/hcd-uhci.c:1190 #10 0x7fc895636c69 in timerlist_run_timers (timer_list=0x7fc896093af0) at qemu-timer.c:491 #11 0x7fc895636f01 in qemu_clock_run_timers (type=) at qemu-timer.c:502 #12 qemu_clock_run_all_timers () at qemu-timer.c:608 #13 0x7fc8955f9b0c in main_loop_wait (nonblocking=) at main-loop.c:507 #14 0x7fc8954bc750 in main_loop () at vl.c:2021 #15 main (argc=, argv=, envp=) at vl.c:4447 --- QEMU release version: 1.7.2 QEMU command: qemu-system-x86_64 -enable-kvm -name guest=guest,debug-threads=on -S -object secret,id=masterKey0,format=raw,file=/var/lib/libvirt/qemu/domain-42-guest /master-key.aes -machine pc-i440fx-xenial,accel=kvm,usb=off,dump- guest-core=off -cpu IvyBridge- IBRS,ss=on,vmx=on,pcid=on,hypervisor=on,arat=on,tsc_adjust=on,ssbd=on,xsaveopt=on -m 1024 -realtime mlock=off -smp 1,sockets=1,cores=1,threads=1 -uuid f4fdccb5-8c59-441f-9a78-83d23fbc34f6 -no-user-config -nodefaults -chardev socket,id=charmonitor,path=/var/lib/libvirt/qemu/domain-42-guest/monitor.sock,server,nowait -mon chardev=charmonitor,id=monitor,mode=control -rtc base=utc,driftfix=slew -global kvm-pit.lost_tick_policy=delay -no-hpet -no-shutdown -global PIIX4_PM.disable_s3=1 -global PIIX4_PM.disable_s4=1 -boot menu=off,strict=on -kernel /nfsroot/rootfs/root/bzImage -initrd /nfsroot/rootfs/root/wrlinux- image-initramfs-x86-64-kvm-guest.cpio.gz -device piix3-usb- uhci,id=usb,bus=pci.0,addr=0x1.0x2 -device lsi,id=scsi0,bus=pci.0,addr=0x7 -device ahci,id=sata0,bus=pci.0,addr=0x6 -device virtio-serial-pci,id=virtio- serial0,bus=pci.0,addr=0x5 -drive file=/nfsroot/rootfs.ovp6/wrlinux- image-ovp-kvm- intel-x86-64-20181015084008.rootfs.ext3,format=raw,if=none,id=drive- usb-disk0 -device usb-storage,bus=usb.0,port=1,drive=drive-usb- disk0,id=usb-disk0,bootindex=1,removable=off -netdev tap,fd=26,id=hostnet0 -device e1000,netdev=hostnet0,id=net0,mac=52:54:00:93:6b:0c,bus=pci.0,addr=0x3 -chardev pty,id=charserial0 -device isa- serial,chardev=charserial0,id=serial0 -chardev spicevmc,id=charchannel0,name=vdagent -device virtserialport,bus =virtio- serial0.0,nr=1,chardev=charchannel0,id=channel0,name=com.redhat.spice.0 -spice port=5900,addr=127.0.0.1,disable-ticketing,image- compression=off,seamless-migration=on -device qxl-
Re: [Qemu-devel] [PATCH v2 1/4] hostmem-memfd: disable for systems wihtout sealing support
On Tue, Dec 11, 2018 at 04:48:23PM +0100, Igor Mammedov wrote:
> On Tue, 11 Dec 2018 13:29:19 +0300
> Ilya Maximets wrote:
>
> CCing libvirt folk for an opinion
>
> > On 10.12.2018 19:18, Igor Mammedov wrote:
> > > On Tue, 27 Nov 2018 16:50:27 +0300
> > > Ilya Maximets wrote:
> > >
> > > s/wihtout/without/ in subj
> > >
> > >> If seals are not supported, memfd_create() will fail.
> > >> Furthermore, there is no way to disable it in this case because
> > >> '.seal' property is not registered.
> > >>
> > >> This issue leads to vhost-user-test failures on RHEL 7.2:
> > >>
> > >> qemu-system-x86_64: -object memory-backend-memfd,id=mem,size=2M,: \
> > >> failed to create memfd: Invalid argument
> > >>
> > >> and actually breaks the feature on such systems.
> > >>
> > >> Let's restrict memfd backend to systems with sealing support.
> > >>
> [...]
> > >> @@ -177,7 +175,7 @@ static const TypeInfo memfd_backend_info = {
> > >>
> > >> static void register_types(void)
> > >> {
> > >> -if (qemu_memfd_check(0)) {
> > >> +if (qemu_memfd_check(MFD_ALLOW_SEALING)) {
> > >> type_register_static(_backend_info);
> > > that would either lead to not clear error that type doesn't exist.
> > > it could be better to report sensible error from
> > > memfd_backend_memory_alloc() if
> > > the feature is required but not supported by host
> >
> > I'm not sure, but this could break the libvirt capability discovering.
> >
> > Current patch changes behaviour probably only for RHEL/CentOS 7.2.
> > All other systems are not affected. Do you think that we need to
> > change behaviour on all the systems?
> you are changing behavior anyways, so when users start getting
> on some of 'All other systems' start getting 'type doesn't exist'
> error, they won't have a clue what's wrong. In case where we are
> fixing broken defaults, shouldn't we at least do it the way that
> would inform user about misconfiguration.
>
> But I'm not insisting since memfd is fairly new, it might be fine
> for device to just disappear.
(Sorry for taking so long to reply on this series. I couldn't
review the code yet.)
I'd like to make the QOM type hierarchy static, and not depend on
any runtime host capability checks. But this is not a new
problem in the code, so I don't think it should block this
series.
--
Eduardo
[Qemu-devel] [PATCH] ioapic: use TYPE_FOO MACRO than constant string
Make them more QOMConventional.
Cc:qemu-triv...@nongnu.org
Signed-off-by: Li Qiang
---
hw/i386/kvm/ioapic.c | 2 +-
hw/i386/pc.c | 4 ++--
hw/intc/ioapic.c | 2 +-
include/hw/i386/ioapic.h | 3 +++
4 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/hw/i386/kvm/ioapic.c b/hw/i386/kvm/ioapic.c
index 5b40d75439..e453692199 100644
--- a/hw/i386/kvm/ioapic.c
+++ b/hw/i386/kvm/ioapic.c
@@ -163,7 +163,7 @@ static void kvm_ioapic_class_init(ObjectClass *klass, void
*data)
}
static const TypeInfo kvm_ioapic_info = {
-.name = "kvm-ioapic",
+.name = TYPE_KVM_IOAPIC,
.parent = TYPE_IOAPIC_COMMON,
.instance_size = sizeof(KVMIOAPICState),
.class_init = kvm_ioapic_class_init,
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index f248662e97..af68a61615 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1665,9 +1665,9 @@ void ioapic_init_gsi(GSIState *gsi_state, const char
*parent_name)
unsigned int i;
if (kvm_ioapic_in_kernel()) {
-dev = qdev_create(NULL, "kvm-ioapic");
+dev = qdev_create(NULL, TYPE_KVM_IOAPIC);
} else {
-dev = qdev_create(NULL, "ioapic");
+dev = qdev_create(NULL, TYPE_IOAPIC);
}
if (parent_name) {
object_property_add_child(object_resolve_path(parent_name, NULL),
diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c
index 4e529729b4..9d75f84d3b 100644
--- a/hw/intc/ioapic.c
+++ b/hw/intc/ioapic.c
@@ -429,7 +429,7 @@ static void ioapic_class_init(ObjectClass *klass, void
*data)
}
static const TypeInfo ioapic_info = {
-.name = "ioapic",
+.name = TYPE_IOAPIC,
.parent= TYPE_IOAPIC_COMMON,
.instance_size = sizeof(IOAPICCommonState),
.class_init= ioapic_class_init,
diff --git a/include/hw/i386/ioapic.h b/include/hw/i386/ioapic.h
index 9c8816f11f..59fcb158a7 100644
--- a/include/hw/i386/ioapic.h
+++ b/include/hw/i386/ioapic.h
@@ -23,6 +23,9 @@
#define IOAPIC_NUM_PINS 24
#define IO_APIC_DEFAULT_ADDRESS 0xfec0
+#define TYPE_KVM_IOAPIC "kvm-ioapic"
+#define TYPE_IOAPIC "ioapic"
+
void ioapic_eoi_broadcast(int vector);
#endif /* HW_IOAPIC_H */
--
2.17.1
Re: [Qemu-devel] [PATCH] i386: mark the 'INTEL_PT' CPUID bit as unmigratable
On Wed, Jan 02, 2019 at 01:30:28AM +, Kang, Luwei wrote:
> > > On 25/12/18 09:23, Kang, Luwei wrote:
> > > >> From: Qemu-devel
> > > >> [mailto:qemu-devel-bounces+luwei.kang=intel@nongnu.org] On
> > > >> Behalf Of Paolo Bonzini
> > > >> Sent: Friday, December 21, 2018 8:44 PM
> > > >> To: qemu-devel@nongnu.org
> > > >> Cc: ehabk...@redhat.com; qemu-sta...@nongnu.org
> > > >> Subject: [Qemu-devel] [PATCH] i386: mark the 'INTEL_PT' CPUID bit
> > > >> as unmigratable
> > > >>
> > > >> Marshaling of processor tracing MSRs is not yet implemented in QEMU,
> > > >> mark the feature as unmigratable.
> > > >
> > > > Hi Paolo,
> > > > I think Intel PT has supported live migration. I don't understand
> > > > what you mean.
> > > >
> > > > commit b77146e9a129bcdb60edc23639211679ae846a92
> > > > Author: Chao Peng
> > > > Date: Mon Mar 5 00:48:36 2018 +0800
> > > > i386: Add support to get/set/migrate Intel Processor Trace
> > > > feature
> > >
> > > Indeed. I had forgotten this patch because it was committed so long
> > > before the kernel parts (which really should not happen, but Eduardo
> > > and I miscommunicated on it). Can you check that it still works?
> >
> > My mistake, sorry. I should have checked the status of the kernel code
> > before merging the original series, or waited for your review.
> >
> > I'm re-reading the code now and I'm worried about two things:
> >
> > The code will break if GET_SUPPORTED_CPUID returns INTEL_PT, but the MSR
> > emulation code is not present yet. Maybe it won't be an
> > issue in practice because it happens only between the two Linux commits
> > (commit 86f5201df0d3 "KVM: x86: Add Intel Processor Trace
> > cpuid emulation" and commit bf8c55d8dc09 "KVM: x86: Implement Intel PT MSRs
> > read/write emulation") and shipping a kernel with the
> > CPUID code without the MSR commit seems pointless.
> >
> > The kvm_arch_get_supported_cpuid() call inside kvm_get_msrs() looks
> > suspicious. What should happen if we try to migrate to a host that
> > returns a smaller number on kvm_arch_get_supported_cpuid(0x14, 1, R_EAX)?
>
> Hi Eduardo,
> I think we have some discussion on this feature about live migration safe
> about two years ago. In order to make live migration safe, we set all the
> values of PT CPUID as constant.
>I think what your concern is the number of address range
> (CPUID:14H.01.EAX[bit02:00]). Currently, it is a constant value (#define
> INTEL_PT_ADDR_RANGES_NUM 0x2) for guest.
>1. if the hardware support < 2, Intel PT will not exposed to guest;
>2. if the hardware support >= 2, we just expose 2 to guest.
>So the number of address range in guest is always 2 if Intel PT is
> supported in guest (there also have other pre-condition check).
Right, I forgot about that part of the code. So the CPU state
save/load code simply saves/loads everything supported by the
host, and the responsibility of keeping guest ABI is lies on
target/i386/cpu.c.
The code looks safe to me. The only unexpected side-effect is
unnecessarily loading/saving of MSR_IA32_RTIT_ADDR[123]*, which
should be harmless. Thanks for the explanation!
>
> The value of guest Intel PT CPUID information.
> +if (count == 0) {
> +*eax = INTEL_PT_MAX_SUBLEAF;
> +*ebx = INTEL_PT_MINIMAL_EBX;
> +*ecx = INTEL_PT_MINIMAL_ECX;
> +} else if (count == 1) {
> +*eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
> +*ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
> +}
>
> The condition check if we can expose Intel PT to guest.
> +if (!eax_0 ||
> + ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
> + ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
> + ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
> + ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
> + INTEL_PT_ADDR_RANGES_NUM) ||
> + ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
> +(INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP))) {
> +/*
> + * Processor Trace capabilities aren't configurable, so if the
> + * host can't emulate the capabilities we report on
> + * cpu_x86_cpuid(), intel-pt can't be enabled on the current
> host.
> + */
> +env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
> +cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
> +rv = 1;
> +}
>
>
> Thanks,
> Luwei Kang
--
Eduardo
Re: [Qemu-devel] [RFC PATCH] osdep: Make MIN/MAX evaluate arguments only once
Hi,
I have a similar patch in my queue[1]
On 2019-01-04 16:39, Eric Blake wrote:
> Use the __auto_type keyword to make sure our min/max macros only
> evaluate their arguments once.
>
> Signed-off-by: Eric Blake
> ---
>
> RFC because __auto_type didn't exist until gcc 4.9, and I don't know
> which clang version introduced it (other than that it went in
> during 2015: https://reviews.llvm.org/D12686). Our minimum gcc
> version is 4.8, which has typeof; I'm not sure if our minimum clang
> version supports typeof.
>
> I'm considering adding a snippet to compiler.h that looks like:
>
> #if // new enough gcc/clang
> #define QEMU_TYPEOF(a) __auto_type
> #else
> #define QEMU_TYPEOF(a) typeof(a)
> #endif
>
> at which point we could blindly use QEMU_TYPEOF(a)=(a) anywhere we
> need automatic typing, for the benefit of smaller macro expansion
> [and proper handling of VLA types, although I don't think we use
> those to care about that aspect of __auto_type] in newer compilers,
> while still getting automatic type deduction in older compilers for
> macros that want single evaluation, and where we've localized the
> version checks to one spot instead of everywhere. But for that to
> work, again, I need to know whether typeof is supported in our
> minimum clang version, and how to properly spell the version check
> for clang on when to prefer __auto_type over typeof (at least I
> know how to spell it for gcc).
>
> While at it, the comments to MIN_NON_ZERO() state that callers should
> only compare unsigned types; I suspect we don't actually obey that
> rule, but I also think the comment is over-strict - the macro works
> as long as both arguments are non-negative, and when called with a
> mix of signed and unsigned types, as long as the type promotion
> preserves the fact that the value is still non-negative. But it
> might be interesting to add compile-time checking (or maybe runtime
> asserts) that the macro is indeed only used on non-negative values.
>
> include/qemu/osdep.h | 22 ++
> 1 file changed, 18 insertions(+), 4 deletions(-)
>
> diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
> index 3bf48bcdec0..b941572b808 100644
> --- a/include/qemu/osdep.h
> +++ b/include/qemu/osdep.h
> @@ -233,17 +233,31 @@ extern int daemon(int, int);
> #endif
>
> #ifndef MIN
> -#define MIN(a, b) (((a) < (b)) ? (a) : (b))
> +#define MIN(a, b) \
> +({ \
> +__auto_type _a = (a); \
> +__auto_type _b = (b); \
> +_a < _b ? _a : _b; \
> +})
> #endif
> #ifndef MAX
> -#define MAX(a, b) (((a) > (b)) ? (a) : (b))
> +#define MAX(a, b) \
> +({ \
> +__auto_type _a = (a); \
> +__auto_type _b = (b); \
> +_a > _b ? _a : _b; \
> +})
> #endif
I tried this[2], but apparently random linux headers define their own
MIN/MAX and in case this version won't be used. And the version above
with __auto_type and statement expression doesn't work on bitfields and
when not in functions (for example struct XHCIState has
USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)];
as one of its member). It only works because currently glib/gmacros.h or
sys/param.h defines it's own MIN/MAX which is identical to the old version.
Now that I think about it, instead of undefining the old macro or only
conditionally defining it, maybe the best course of action would be to
rename MIN/MAX to something more unique so it won't clash with random
system headers.
>
> /* Minimum function that returns zero only iff both values are zero.
> * Intended for use with unsigned values only. */
> #ifndef MIN_NON_ZERO
> -#define MIN_NON_ZERO(a, b) ((a) == 0 ? (b) : \
> -((b) == 0 ? (a) : (MIN(a, b
> +#define MIN_NON_ZERO(a, b) \
> +({ \
> +__auto_type _a = (a); \
> +__auto_type _b = (b); \
> +_a == 0 ? _b : (_b == 0 || _b > _a) ? _a : _b; \
> +})
> #endif
>
> /* Round number down to multiple */
>
[1]: https://lists.gnu.org/archive/html/qemu-devel/2018-12/msg05718.html
[2]: https://lists.gnu.org/archive/html/qemu-devel/2018-12/msg06006.html
Regards,
Zoltan
Re: [Qemu-devel] [PATCH v2 07/22] qemu-nbd: Avoid strtol open-coding
On 12/18/18 9:11 AM, Vladimir Sementsov-Ogievskiy wrote: > 15.12.2018 16:53, Eric Blake wrote: >> Our copy-and-pasted open-coding of strtol handling forgot to >> handle overflow conditions. Use qemu_strto*() instead. >> >> In the case of --partition, since we insist on a user-supplied >> partition to be non-zero, we can use 0 rather than -1 for our >> initial value to distinguish when a partition is not being >> served, for slightly more optimal code. >> >> The error messages for out-of-bounds values are less specific, >> but should not be a terrible loss in quality. >> >> Signed-off-by: Eric Blake >> >> --- >> v2: Retitle, catch more uses of strtol >> [Hmm - this depends on int64_t and off_t being compatible; if they >> aren't that way on all platforms, I'll need a temporary variable] > > hmm, as I understand, even if this compatibility exists, it's not a part > of standard and nothing about off_t size in POSIX.. off_t allows you to run on older systems with 32-bit offsets and newer systems with 64-bit offsets; but these days, even on 32-bit systems, we compile qemu to always ask for 64-bit off_t. Using off_t instead of int64_t is probably a separate cleanup, but one that may be worth making prior to this patch, so I'll defer this one to my v3. > > Moreover: what is the reason for using off_t in NBD code? We don't have it > in NBD protocol, we don't have it in generic block layer interface. Isn't it > always casted to int64_t or like this? > -- Eric Blake, Principal Software Engineer Red Hat, Inc. +1-919-301-3226 Virtualization: qemu.org | libvirt.org signature.asc Description: OpenPGP digital signature
Re: [Qemu-devel] [PATCH v2 04/22] qemu-nbd: Enhance man page
On 12/17/18 9:19 AM, Eric Blake wrote: >> >>> +@c man begin EXAMPLES >>> +Start a server listening on port 10809 that exposes only the >>> +guest-visible contents of a qcow2 file, with no TLS encryption, and >>> +with the default export name (an empty string). The command will block >>> +until the first successful client disconnects: >> >> TBH I'd always include the -t option in every example. I don't >> understand (except for backwards compatibility) why it isn't the >> default since it's something I always trip over when using qemu-nbd. > > I'd still like one example without -t, to call out specifically that it > creates a one-shot server that goes away after the first client, but > don't mind fixing the rest of the examples to use -t. > > Using -e for read-only connections makes sense, using -e for writable > exports is a bit more questionable - we _don't_ advertise the > NBD_FLAG_CAN_MULTI_CONN which states that caches are kept consistent > between simultaneous write connections, although maybe we should see if > qemu-nbd can start promising multi-write consistency in future patches? And I see you've just posted patches for nbdkit to start advertising CAN_MULTI_CONN - so I really need to spend some time figuring out when it makes sense for qemu to advertise the flag. -- Eric Blake, Principal Software Engineer Red Hat, Inc. +1-919-301-3226 Virtualization: qemu.org | libvirt.org signature.asc Description: OpenPGP digital signature
Re: [Qemu-devel] [PATCH v2 03/22] maint: Allow for EXAMPLES in texi2pod
On 12/18/18 7:46 AM, Vladimir Sementsov-Ogievskiy wrote: > 15.12.2018 16:53, Eric Blake wrote: >> The next commit will add an EXAMPLES section to qemu-nbd.8; >> for that to work, we need to recognize EXAMPLES in texi2pod, >> and we need to make all man pages be regenerated since the >> output of texi2pod can be different. >> >> Signed-off-by: Eric Blake >> >> +qemu.1: qemu-doc.texi qemu-options.texi qemu-monitor.texi \ >> +qemu-monitor-info.texi scripts/texi2pod.pl >> +qemu.1: qemu-option-trace.texi scripts/texi2pod.pl > > I think, no needs to add scripts/texi2pod.pl to both qemu.1: lines, as they > should be > merged anyway. And if you want to add line breaking anyway, it looks better > to use one qemu.1: > dependency line. Easy to fix. > > On the other hand, it may be better to add MANS variable as subset of DOCS to > combine all man page targets, > and than do like $(MANS): scripts/texi2pod.pl.. (and recombine DOCS, using > MANS ofcourse) > Hm, and I don't see here docs/interop/qemu-ga-ref.7 and > docs/interop/qemu-qmp-ref.7, > which exist in DOCS. Oh, good point. The .txt files should also have the dependency - in general, ALL generated documentation should depend on the generator, not just the man pages. I'll have to think about respinning this patch. -- Eric Blake, Principal Software Engineer Red Hat, Inc. +1-919-301-3226 Virtualization: qemu.org | libvirt.org signature.asc Description: OpenPGP digital signature
Re: [Qemu-devel] AVX support for TCG
Right, that makes sense, thanks for the explanations. As someone with very little x86 experience (zero experience from this perspective) it's kind of daunting that I'd have to refactor all this stuff. All these helpers via macros to get around C's 'minimalism' also seem like something I'd have to get accustomed to. I will think about it. Just curious, why is gvec-desc a bitfield instead of a normal struct? Surely it'd be more readable that way. Also this is C, so it's not even a typed bitfield, just a uint32. I'm guessing there's a reason behind this?
Re: [Qemu-devel] [PATCH] compat: Use explicit type names on HW_COMPAT_2_6
On Fri, Jan 04, 2019 at 04:13:15PM -0500, Michael S. Tsirkin wrote:
> On Fri, Jan 04, 2019 at 07:06:56PM -0200, Eduardo Habkost wrote:
> > On Fri, Jan 04, 2019 at 03:48:02PM -0500, Michael S. Tsirkin wrote:
> > > On Fri, Jan 04, 2019 at 06:09:52PM -0200, Eduardo Habkost wrote:
> > > > On Fri, Jan 04, 2019 at 03:54:39PM -0200, Eduardo Habkost wrote:
> > > > > On Fri, Jan 04, 2019 at 10:12:00AM +, Dr. David Alan Gilbert
> > > > > wrote:
> > > > > > * Michael S. Tsirkin (m...@redhat.com) wrote:
> > > > > > > On Fri, Jan 04, 2019 at 01:22:26AM -0200, Eduardo Habkost wrote:
> > > > > > > > The virtio-pci entries in HW_COMPAT_2_6 had an implicit
> > > > > > > > assumption: that all virtio-pci subclasses support the
> > > > > > > > disable-legacy and disable-modern options.
> > > > > > > >
> > > > > > > > That assumption was broken by commit f6e501a28ef9 ("virtio:
> > > > > > > > Provide version-specific variants of virtio PCI devices"). This
> > > > > > > > caused QEMU to crash if using the new -non-transitional or
> > > > > > > > -transitional device types:
> > > > > > > >
> > > > > > > > $ qemu-system-x86_64 -machine pc-i440fx-2.6 \
> > > > > > > > -device virtio-net-pci-non-transitional
> > > > > > > > Unexpected error in object_property_find() at
> > > > > > > > qom/object.c:1092:
> > > > > > > > qemu-system-x86_64: -device virtio-net-pci-non-transitional:
> > > > > > > > can't apply \
> > > > > > > > global virtio-pci.disable-modern=on: Property
> > > > > > > > '.disable-modern' not found
> > > > > > > > Aborted (core dumped)
> > > > > > > >
> > > > > > > > Replace the virtio-pci.disable-legacy=off and
> > > > > > > > virtio-pci.disable-modern=on entries on HW_COMPAT_2_6 with
> > > > > > > > explicit entries for each generic virtio device type.
> > > > > > > >
> > > > > > > > The full list of generic virtio device types was extracted by
> > > > > > > > just grepping for ".generic_name". Note that we don't need to
> > > > > > > > worry about listing new virtio-pci devices in HW_COMPAT_2_6 in
> > > > > > > > the future, because new devices won't require QEMU 2.6
> > > > > > > > compatibility.
> > > > > > >
> > > > > > > I fully expect that e.g. packed ring support will need
> > > > > > > to affect all virtio devices too. And it's likely
> > > > > > > that we'll have some new virtio-pci transport features too.
> > > > > > >
> > > > > > > > This makes the compat entries annoyingly verbose, but is simpler
> > > > > > > > than the alternative of making the virtio-pci type inheritance
> > > > > > > > rules even more complex.
> > > > > > >
> > > > > > > God forbid we forgot something, the only way to notice is to
> > > > > > > run a cross version migration with an old qemu.
> > > > > > > I think we need to come up with something less verbose and
> > > > > > > fragile.
> > > > > >
> > > > > > I guess we could use a script like
> > > > > > tests/acceptance/virtio_version.py to
> > > > > > do a check?
> > > > >
> > > > > That's a good idea. On test code we can try additional tricks to
> > > > > detect the hybrid virtio devices without increasing the
> > > > > complexity of QEMU code. I'll give it a try.
> > > >
> > > > I did it but I'm not happy with the result: many of the virtio
> > > > devices can't be tested without extra arguments. Some of them
> > > > (like vhost-*) require extra privileges on the host that might be
> > > > unavailable.
> > > >
> > > > Anyway, while writing this I noticed another issue: many of the
> > > > virtio devices in QEMU 2.6 were already modern-only!
> > > >
> > > > Setting disable-modern=off on modern-only devices like virtio-vga
> > > > or virtio-tablet-pci doesn't make sense. This means setting
> > > > virtio-pci.disable-modern=off on HW_COMPAT_2_6 was incorrect even
> > > > before the -non-transitional and -transitional device types were
> > > > introduced.
> > >
> > >
> > > It did create an opportunity to create non working devices.
> > >
> > > Whether that's incorrect as such I'm not sure.
> >
> > This is not just creating the opportunity for an user to
> > disable-modern=on. HW_COMPAT_2_6 is actually setting
> > disable-modern=on on virtio-vga and other modern-only devices.
> > Sounds like a mistake to me.
> >
> > Luckily those modern-only devices silently ignore the
> > disable-modern/disable-legacy properties, but this might change
> > in the future.
>
> Worry about it then?
Right, we don't need to worry about it today. But if a solution
to the crash reported by Thomas will make the problem go away,
that's even better.
--
Eduardo
[Qemu-devel] [PATCH v1 3/3] RISC-V: Implement existential predicates for CSRs
From: Michael Clark
CSR predicate functions are added to the CSR table.
mstatus.FS and counter enable checks are moved
to predicate functions and two new predicates are
added to check misa.S for s* CSRs and a new PMP
CPU feature for pmp* CSRs.
Processors that don't implement S-mode will trap
on access to s* CSRs and processors that don't
implement PMP will trap on accesses to pmp* CSRs.
PMP checks are disabled in riscv_cpu_handle_mmu_fault
when the PMP CPU feature is not present.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c| 6 ++
target/riscv/cpu.h| 6 +-
target/riscv/cpu_helper.c | 3 +-
target/riscv/csr.c| 169 +-
4 files changed, 105 insertions(+), 79 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5e8a2cb2ba..28d7e5302f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -126,6 +126,7 @@ static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_09_1);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_MMU);
+set_feature(env, RISCV_FEATURE_PMP);
}
static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
@@ -135,6 +136,7 @@ static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_MMU);
+set_feature(env, RISCV_FEATURE_PMP);
}
static void rv32imacu_nommu_cpu_init(Object *obj)
@@ -143,6 +145,7 @@ static void rv32imacu_nommu_cpu_init(Object *obj)
set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
+set_feature(env, RISCV_FEATURE_PMP);
}
#elif defined(TARGET_RISCV64)
@@ -154,6 +157,7 @@ static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_09_1);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_MMU);
+set_feature(env, RISCV_FEATURE_PMP);
}
static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
@@ -163,6 +167,7 @@ static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_MMU);
+set_feature(env, RISCV_FEATURE_PMP);
}
static void rv64imacu_nommu_cpu_init(Object *obj)
@@ -171,6 +176,7 @@ static void rv64imacu_nommu_cpu_init(Object *obj)
set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
+set_feature(env, RISCV_FEATURE_PMP);
}
#endif
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4aeaa32049..743f02c8b9 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -83,9 +83,10 @@
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
is currently no bit in misa to indicate whether an MMU exists or not
- so a cpu features bitfield is required */
+ so a cpu features bitfield is required, likewise for optional PMP support */
enum {
-RISCV_FEATURE_MMU
+RISCV_FEATURE_MMU,
+RISCV_FEATURE_PMP
};
#define USER_VERSION_2_02_0 0x00020200
@@ -314,6 +315,7 @@ typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int
csrno,
target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
typedef struct {
+riscv_csr_predicate_fn predicate;
riscv_csr_read_fn read;
riscv_csr_write_fn write;
riscv_csr_op_fn op;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 4ef7f5c1f9..f257050f12 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -404,7 +404,8 @@ int riscv_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
int size,
qemu_log_mask(CPU_LOG_MMU,
"%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
" prot %d\n", __func__, address, ret, pa, prot);
-if (!pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << rw)) {
+if (riscv_feature(env, RISCV_FEATURE_PMP) &&
+!pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << rw)) {
ret = TRANSLATE_FAIL;
}
if (ret == TRANSLATE_SUCCESS) {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 44ea8b7cb6..5e7e7d16b8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -42,6 +42,46 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
}
+/* Predicates */
+static int fs(CPURISCVState *env, int csrno)
+{
+#if !defined(CONFIG_USER_ONLY)
+if (!(env->mstatus & MSTATUS_FS)) {
+return -1;
+}
+#endif
+return 0;
+}
[Qemu-devel] [PATCH v1 2/3] RISC-V: Implement atomic mip/sip CSR updates
From: Michael Clark
Use the new CSR read/modify/write interface to implement
atomic updates to mip/sip.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 56 +++---
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index b61b0ef379..44ea8b7cb6 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -487,25 +487,31 @@ static int write_mbadaddr(CPURISCVState *env, int csrno,
target_ulong val)
return 0;
}
-static int read_mip(CPURISCVState *env, int csrno, target_ulong *val)
-{
-*val = atomic_read(>mip);
-return 0;
-}
-
-static int write_mip(CPURISCVState *env, int csrno, target_ulong val)
+static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+ target_ulong new_value, target_ulong write_mask)
{
RISCVCPU *cpu = riscv_env_get_cpu(env);
+target_ulong mask = write_mask & delegable_ints;
+uint32_t old_mip;
+
+/* We can't allow the supervisor to control SEIP as this would allow the
+ * supervisor to clear a pending external interrupt which will result in
+ * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
+ * hardware controlled when a PLIC is attached. This should be an option
+ * for CPUs with software-delegated Supervisor External Interrupts. */
+mask &= ~MIP_SEIP;
+
+if (mask) {
+qemu_mutex_lock_iothread();
+old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
+qemu_mutex_unlock_iothread();
+} else {
+old_mip = atomic_read(>mip);
+}
-/*
- * csrs, csrc on mip.SEIP is not decomposable into separate read and
- * write steps, so a different implementation is needed
- */
-
-qemu_mutex_lock_iothread();
-riscv_cpu_update_mip(cpu, MIP_SSIP | MIP_STIP,
- (val & (MIP_SSIP | MIP_STIP)));
-qemu_mutex_unlock_iothread();
+if (ret_value) {
+*ret_value = old_mip;
+}
return 0;
}
@@ -623,17 +629,11 @@ static int write_sbadaddr(CPURISCVState *env, int csrno,
target_ulong val)
return 0;
}
-static int read_sip(CPURISCVState *env, int csrno, target_ulong *val)
-{
-*val = atomic_read(>mip) & env->mideleg;
-return 0;
-}
-
-static int write_sip(CPURISCVState *env, int csrno, target_ulong val)
+static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+ target_ulong new_value, target_ulong write_mask)
{
-target_ulong newval = (atomic_read(>mip) & ~env->mideleg)
- | (val & env->mideleg);
-return write_mip(env, CSR_MIP, newval);
+return rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
+ write_mask & env->mideleg);
}
/* Supervisor Protection and Translation */
@@ -812,7 +812,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MEPC] ={ read_mepc,write_mepc},
[CSR_MCAUSE] = { read_mcause, write_mcause },
[CSR_MBADADDR] ={ read_mbadaddr,write_mbadaddr},
-[CSR_MIP] = { read_mip, write_mip },
+[CSR_MIP] = { NULL, NULL, rmw_mip },
/* Supervisor Trap Setup */
[CSR_SSTATUS] = { read_sstatus, write_sstatus },
@@ -825,7 +825,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_SEPC] ={ read_sepc,write_sepc},
[CSR_SCAUSE] = { read_scause, write_scause },
[CSR_SBADADDR] ={ read_sbadaddr,write_sbadaddr},
-[CSR_SIP] = { read_sip, write_sip },
+[CSR_SIP] = { NULL, NULL, rmw_sip },
/* Supervisor Protection and Translation */
[CSR_SATP] ={ read_satp,write_satp},
--
2.19.1
[Qemu-devel] [PATCH v1 1/3] RISC-V: Implement modular CSR helper interface
From: Michael Clark
Previous CSR code uses csr_read_helper and csr_write_helper
to update CSR registers however this interface prevents
atomic read/modify/write CSR operations; in addition
there is no trap-free method to access to CSRs due
to the monolithic CSR functions call longjmp.
The current iCSR interface is not safe to be called by
target/riscv/gdbstub.c as privilege checks or missing CSRs
may call longjmp to generate exceptions. It needs to
indicate existence so traps can be generated in the
CSR instruction helpers.
This commit moves CSR access from the monolithic switch
statements in target/riscv/op_helper.c into modular
read/write functions in target/riscv/csr.c using a new
function pointer table for dispatch (which can later
be used to allow CPUs to hook up model specific CSRs).
A read/modify/write interface is added to support atomic
CSR operations and a non-trapping interface is added
to allow exception-free access to CSRs by the debugger.
The CSR functions and CSR dispatch table are ordered
to match The RISC-V Instruction Set Manual, Volume II:
Privileged Architecture Version 1.10, 2.2 CSR Listing.
An API is added to allow derived cpu instances to modify
or implement new CSR operations.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
---
target/riscv/Makefile.objs | 2 +-
target/riscv/cpu.h | 35 +-
target/riscv/cpu_helper.c | 4 +-
target/riscv/csr.c | 846 +
target/riscv/gdbstub.c | 10 +-
target/riscv/op_helper.c | 613 +--
6 files changed, 904 insertions(+), 606 deletions(-)
create mode 100644 target/riscv/csr.c
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index fcc5d34c1f..4072abe3e4 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -1 +1 @@
-obj-y += translate.o op_helper.o cpu_helper.o cpu.o fpu_helper.o gdbstub.o
pmp.o
+obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o
gdbstub.o pmp.o
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4ee09b9cff..4aeaa32049 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -289,9 +289,38 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState
*env, target_ulong *pc,
#endif
}
-void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
-target_ulong csrno);
-target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno);
+int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
+target_ulong new_value, target_ulong write_mask);
+
+static inline void csr_write_helper(CPURISCVState *env, target_ulong val,
+int csrno)
+{
+riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
+}
+
+static inline target_ulong csr_read_helper(CPURISCVState *env, int csrno)
+{
+target_ulong val = 0;
+riscv_csrrw(env, csrno, , 0, 0);
+return val;
+}
+
+typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno);
+typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
+target_ulong *ret_value);
+typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
+target_ulong new_value);
+typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
+target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
+
+typedef struct {
+riscv_csr_read_fn read;
+riscv_csr_write_fn write;
+riscv_csr_op_fn op;
+} riscv_csr_operations;
+
+void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
+void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
#include "exec/cpu-all.h"
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 0234c2d528..4ef7f5c1f9 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -528,7 +528,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE <<
env->priv));
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
-csr_write_helper(env, s, CSR_MSTATUS);
+env->mstatus = s;
riscv_set_mode(env, PRV_S);
} else {
/* No need to check MTVEC for misaligned - lower 2 bits cannot be set
*/
@@ -553,7 +553,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE <<
env->priv));
s = set_field(s, MSTATUS_MPP, env->priv);
s = set_field(s, MSTATUS_MIE, 0);
-csr_write_helper(env, s, CSR_MSTATUS);
+env->mstatus = s;
riscv_set_mode(env, PRV_M);
}
/* TODO yield load reservation */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
new file mode 100644
index 00..b61b0ef379
--- /dev/null
+++ b/target/riscv/csr.c
@@ -0,0 +1,846 @@
+/*
+ * RISC-V Control and Status Registers.
+ *
+ * Copyright (c) 2016-2017
[Qemu-devel] [PATCH v1 0/3] Upstream more RISC-V fork patches
This is one of the big patches that the RISC-V fork has that we don't. After this it should be straight forward to upstream the remaining patches. Michael Clark (3): RISC-V: Implement modular CSR helper interface RISC-V: Implement atomic mip/sip CSR updates RISC-V: Implement existential predicates for CSRs target/riscv/Makefile.objs | 2 +- target/riscv/cpu.c | 6 + target/riscv/cpu.h | 41 +- target/riscv/cpu_helper.c | 7 +- target/riscv/csr.c | 863 + target/riscv/gdbstub.c | 10 +- target/riscv/op_helper.c | 613 +- 7 files changed, 933 insertions(+), 609 deletions(-) create mode 100644 target/riscv/csr.c -- 2.19.1
Re: [Qemu-devel] AVX support for TCG
On 1/5/19 8:09 AM, Nick Renieris wrote: > Στις Παρ, 4 Ιαν 2019 στις 11:51 μ.μ., ο/η Richard Henderson > έγραψε: >> As an integer it is always passed by value. As a structure some host abis >> pass >> it by reference, and the TCG compiler doesn't know about that. > > Ah so they modify it? If so it could surely be worked around with > explicit stack copies, right? No, it's just calling conventions. And it could be worked around, but I think what we have is convenient enough. Especially since the sizes are encoded as (n+1)*8, which also shows the compiler that the size is positive, so the for loop must iterate at least once. r~
Re: [Qemu-devel] [PATCH v1 2/2] target/microblaze: Add props enabling exceptions on failed bus accesses
On Fri, Jan 4, 2019 at 6:28 AM Edgar E. Iglesias
wrote:
>
> From: "Edgar E. Iglesias"
>
> Add MicroBlaze CPU properties to enable exceptions on failed
> bus accesses.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Alistair
> ---
> target/microblaze/cpu.c | 12 +++-
> target/microblaze/cpu.h | 2 ++
> 2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 49876b19b3..5596cd5485 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -202,7 +202,11 @@ static void mb_cpu_realizefn(DeviceState *dev, Error
> **errp)
> (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
> (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
> (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) |
> -(cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0);
> +(cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) |
> +(cpu->cfg.dopb_bus_exception ?
> + PVR2_DOPB_BUS_EXC_MASK : 0)
> |
> +(cpu->cfg.iopb_bus_exception ?
> + PVR2_IOPB_BUS_EXC_MASK : 0);
>
> env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
> PVR5_DCACHE_WRITEBACK_MASK : 0;
> @@ -265,6 +269,12 @@ static Property mb_properties[] = {
> DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
> false),
> DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
> +/* Enables bus exceptions on failed data accesses (load/stores). */
> +DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU,
> + cfg.dopb_bus_exception, false),
> +/* Enables bus exceptions on failed instruction fetches. */
> +DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
> + cfg.iopb_bus_exception, false),
> DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
> DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
> DEFINE_PROP_END_OF_LIST(),
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 03ca91007d..792bbc97c7 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -308,6 +308,8 @@ struct MicroBlazeCPU {
> bool use_mmu;
> bool dcache_writeback;
> bool endi;
> +bool dopb_bus_exception;
> +bool iopb_bus_exception;
> char *version;
> uint8_t pvr;
> } cfg;
> --
> 2.17.1
>
>
[Qemu-devel] [PATCH v2 06/10] tcg/i386: Split subroutines out of tcg_expand_vec_op
This routine was becoming too large.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.inc.c | 459 +++---
1 file changed, 232 insertions(+), 227 deletions(-)
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index c21c3272f2..ad97386d06 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -3079,253 +3079,258 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
}
}
+static void expand_vec_shi(TCGType type, unsigned vece, bool shr,
+ TCGv_vec v0, TCGv_vec v1, TCGArg imm)
+{
+TCGv_vec t1, t2;
+
+tcg_debug_assert(vece == MO_8);
+
+t1 = tcg_temp_new_vec(type);
+t2 = tcg_temp_new_vec(type);
+
+/* Unpack to W, shift, and repack. Tricky bits:
+ (1) Use punpck*bw x,x to produce DDCCBBAA,
+ i.e. duplicate in other half of the 16-bit lane.
+ (2) For right-shift, add 8 so that the high half of
+ the lane becomes zero. For left-shift, we must
+ shift up and down again.
+ (3) Step 2 leaves high half zero such that PACKUSWB
+ (pack with unsigned saturation) does not modify
+ the quantity. */
+vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
+ tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1));
+vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
+ tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1));
+
+if (shr) {
+tcg_gen_shri_vec(MO_16, t1, t1, imm + 8);
+tcg_gen_shri_vec(MO_16, t2, t2, imm + 8);
+} else {
+tcg_gen_shli_vec(MO_16, t1, t1, imm + 8);
+tcg_gen_shli_vec(MO_16, t2, t2, imm + 8);
+tcg_gen_shri_vec(MO_16, t1, t1, 8);
+tcg_gen_shri_vec(MO_16, t2, t2, 8);
+}
+
+vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8,
+ tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2));
+tcg_temp_free_vec(t1);
+tcg_temp_free_vec(t2);
+}
+
+static void expand_vec_sari(TCGType type, unsigned vece,
+TCGv_vec v0, TCGv_vec v1, TCGArg imm)
+{
+TCGv_vec t1, t2;
+
+switch (vece) {
+case MO_8:
+/* Unpack to W, shift, and repack, as in expand_vec_shi. */
+t1 = tcg_temp_new_vec(type);
+t2 = tcg_temp_new_vec(type);
+vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
+ tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1));
+vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
+ tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1));
+tcg_gen_sari_vec(MO_16, t1, t1, imm + 8);
+tcg_gen_sari_vec(MO_16, t2, t2, imm + 8);
+vec_gen_3(INDEX_op_x86_packss_vec, type, MO_8,
+ tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2));
+tcg_temp_free_vec(t1);
+tcg_temp_free_vec(t2);
+break;
+
+case MO_64:
+if (imm <= 32) {
+/* We can emulate a small sign extend by performing an arithmetic
+ * 32-bit shift and overwriting the high half of a 64-bit logical
+ * shift (note that the ISA says shift of 32 is valid).
+ */
+t1 = tcg_temp_new_vec(type);
+tcg_gen_sari_vec(MO_32, t1, v1, imm);
+tcg_gen_shri_vec(MO_64, v0, v1, imm);
+vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32,
+ tcgv_vec_arg(v0), tcgv_vec_arg(v0),
+ tcgv_vec_arg(t1), 0xaa);
+tcg_temp_free_vec(t1);
+} else {
+/* Otherwise we will need to use a compare vs 0 to produce
+ * the sign-extend, shift and merge.
+ */
+t1 = tcg_const_zeros_vec(type);
+tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1, t1, v1);
+tcg_gen_shri_vec(MO_64, v0, v1, imm);
+tcg_gen_shli_vec(MO_64, t1, t1, 64 - imm);
+tcg_gen_or_vec(MO_64, v0, v0, t1);
+tcg_temp_free_vec(t1);
+}
+break;
+
+default:
+g_assert_not_reached();
+}
+}
+
+static void expand_vec_mul(TCGType type, unsigned vece,
+ TCGv_vec v0, TCGv_vec v1, TCGv_vec v2)
+{
+TCGv_vec t1, t2, t3, t4;
+
+tcg_debug_assert(vece == MO_8);
+
+/*
+ * Unpack v1 bytes to words, 0 | x.
+ * Unpack v2 bytes to words, y | 0.
+ * This leaves the 8-bit result, x * y, with 8 bits of right padding.
+ * Shift logical right by 8 bits to clear the high 8 bytes before
+ * using an unsigned saturated pack.
+ *
+ * The difference between the V64, V128 and V256 cases is merely how
+ * we distribute the expansion between temporaries.
+ */
+switch (type) {
+case TCG_TYPE_V64:
+t1 = tcg_temp_new_vec(TCG_TYPE_V128);
+t2 = tcg_temp_new_vec(TCG_TYPE_V128);
+tcg_gen_dup16i_vec(t2, 0);
+vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8,
+ tcgv_vec_arg(t1), tcgv_vec_arg(v1),
[Qemu-devel] [PATCH v2 05/10] tcg: Add opcodes for vector minmax arithmetic
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime.h | 20
tcg/aarch64/tcg-target.h | 1 +
tcg/i386/tcg-target.h| 1 +
tcg/tcg-op-gvec.h| 10 ++
tcg/tcg-op.h | 4 +
tcg/tcg-opc.h| 4 +
tcg/tcg.h| 1 +
accel/tcg/tcg-runtime-gvec.c | 224 +++
tcg/tcg-op-gvec.c| 108 +
tcg/tcg-op-vec.c | 20
tcg/tcg.c| 5 +
11 files changed, 398 insertions(+)
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index 835ddfebb2..dfe325625c 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -200,6 +200,26 @@ DEF_HELPER_FLAGS_4(gvec_ussub16, TCG_CALL_NO_RWG, void,
ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_ussub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_ussub64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_smin8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_smin16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_smin32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_smin64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_smax8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_smax16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_smax32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_smax64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_umin8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_umin16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_umin32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_umin64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_umax8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_umax16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_umax32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_umax64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_3(gvec_neg8, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_neg16, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_neg32, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 98556bcf22..545a6eec75 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -136,6 +136,7 @@ typedef enum {
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 0
+#define TCG_TARGET_HAS_minmax_vec 0
#define TCG_TARGET_DEFAULT_MO (0)
#define TCG_TARGET_HAS_MEMORY_BSWAP 1
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 44381062e6..7bd7eae672 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -186,6 +186,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 0
+#define TCG_TARGET_HAS_minmax_vec 0
#define TCG_TARGET_deposit_i32_valid(ofs, len) \
(((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index 2cb447112e..4734eef7de 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -234,6 +234,16 @@ void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs,
uint32_t aofs,
void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+/* Min/max. */
+void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+
void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs,
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 4a93d730e8..2d98868d8f 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -971,6 +971,10 @@ void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec
a, TCGv_vec b);
void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_smin_vec(unsigned vece, TCGv_vec r, TCGv_vec a,
[Qemu-devel] [PATCH v2 00/10] tcg vector improvements
I've split this out from the target/ppc patch set in which it was developed. r~ Richard Henderson (10): tcg: Add logical simplifications during gvec expand tcg: Add gvec expanders for nand, nor, eqv tcg: Add write_aofs to GVecGen4 tcg: Add opcodes for vector saturated arithmetic tcg: Add opcodes for vector minmax arithmetic tcg/i386: Split subroutines out of tcg_expand_vec_op tcg/i386: Implement vector saturating arithmetic tcg/i386: Implement vector minmax arithmetic tcg/aarch64: Implement vector saturating arithmetic tcg/aarch64: Implement vector minmax arithmetic accel/tcg/tcg-runtime.h | 23 ++ tcg/aarch64/tcg-target.h | 2 + tcg/i386/tcg-target.h| 2 + tcg/tcg-op-gvec.h| 18 ++ tcg/tcg-op.h | 11 + tcg/tcg-opc.h| 8 + tcg/tcg.h| 2 + accel/tcg/tcg-runtime-gvec.c | 257 tcg/aarch64/tcg-target.inc.c | 48 +++ tcg/i386/tcg-target.inc.c| 580 +-- tcg/tcg-op-gvec.c| 305 -- tcg/tcg-op-vec.c | 75 - tcg/tcg.c| 10 + 13 files changed, 1078 insertions(+), 263 deletions(-) -- 2.17.2
Re: [Qemu-devel] AVX support for TCG
On 1/5/19 7:43 AM, Nick Renieris wrote: > Just curious, why is gvec-desc a bitfield instead of a normal struct? > Surely it'd be more readable that way. Also this is C, so it's not > even a typed bitfield, just a uint32. I'm guessing there's a reason > behind this? As an integer it is always passed by value. As a structure some host abis pass it by reference, and the TCG compiler doesn't know about that. r~
[Qemu-devel] [PATCH v2 03/10] tcg: Add write_aofs to GVecGen4
This allows writing 2 output, 3 input operations.
Signed-off-by: Richard Henderson
---
tcg/tcg-op-gvec.h | 2 ++
tcg/tcg-op-gvec.c | 27 +++
2 files changed, 21 insertions(+), 8 deletions(-)
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index d65b9d9d4c..2cb447112e 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -181,6 +181,8 @@ typedef struct {
uint8_t vece;
/* Prefer i64 to v64. */
bool prefer_i64;
+/* Write aofs as a 2nd dest operand. */
+bool write_aofs;
} GVecGen4;
void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 81689d02f7..c10d3d7b26 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -665,7 +665,7 @@ static void expand_3_i32(uint32_t dofs, uint32_t aofs,
/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
static void expand_4_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
- uint32_t cofs, uint32_t oprsz,
+ uint32_t cofs, uint32_t oprsz, bool write_aofs,
void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32))
{
TCGv_i32 t0 = tcg_temp_new_i32();
@@ -680,6 +680,9 @@ static void expand_4_i32(uint32_t dofs, uint32_t aofs,
uint32_t bofs,
tcg_gen_ld_i32(t3, cpu_env, cofs + i);
fni(t0, t1, t2, t3);
tcg_gen_st_i32(t0, cpu_env, dofs + i);
+if (write_aofs) {
+tcg_gen_st_i32(t1, cpu_env, aofs + i);
+}
}
tcg_temp_free_i32(t3);
tcg_temp_free_i32(t2);
@@ -769,7 +772,7 @@ static void expand_3_i64(uint32_t dofs, uint32_t aofs,
/* Expand OPSZ bytes worth of three-operand operations using i64 elements. */
static void expand_4_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
- uint32_t cofs, uint32_t oprsz,
+ uint32_t cofs, uint32_t oprsz, bool write_aofs,
void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
{
TCGv_i64 t0 = tcg_temp_new_i64();
@@ -784,6 +787,9 @@ static void expand_4_i64(uint32_t dofs, uint32_t aofs,
uint32_t bofs,
tcg_gen_ld_i64(t3, cpu_env, cofs + i);
fni(t0, t1, t2, t3);
tcg_gen_st_i64(t0, cpu_env, dofs + i);
+if (write_aofs) {
+tcg_gen_st_i64(t1, cpu_env, aofs + i);
+}
}
tcg_temp_free_i64(t3);
tcg_temp_free_i64(t2);
@@ -880,7 +886,7 @@ static void expand_3_vec(unsigned vece, uint32_t dofs,
uint32_t aofs,
/* Expand OPSZ bytes worth of four-operand operations using host vectors. */
static void expand_4_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t cofs, uint32_t oprsz,
- uint32_t tysz, TCGType type,
+ uint32_t tysz, TCGType type, bool write_aofs,
void (*fni)(unsigned, TCGv_vec, TCGv_vec,
TCGv_vec, TCGv_vec))
{
@@ -896,6 +902,9 @@ static void expand_4_vec(unsigned vece, uint32_t dofs,
uint32_t aofs,
tcg_gen_ld_vec(t3, cpu_env, cofs + i);
fni(vece, t0, t1, t2, t3);
tcg_gen_st_vec(t0, cpu_env, dofs + i);
+if (write_aofs) {
+tcg_gen_st_vec(t1, cpu_env, aofs + i);
+}
}
tcg_temp_free_vec(t3);
tcg_temp_free_vec(t2);
@@ -1187,7 +1196,7 @@ void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t cofs,
*/
some = QEMU_ALIGN_DOWN(oprsz, 32);
expand_4_vec(g->vece, dofs, aofs, bofs, cofs, some,
- 32, TCG_TYPE_V256, g->fniv);
+ 32, TCG_TYPE_V256, g->write_aofs, g->fniv);
if (some == oprsz) {
break;
}
@@ -1200,18 +1209,20 @@ void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t cofs,
/* fallthru */
case TCG_TYPE_V128:
expand_4_vec(g->vece, dofs, aofs, bofs, cofs, oprsz,
- 16, TCG_TYPE_V128, g->fniv);
+ 16, TCG_TYPE_V128, g->write_aofs, g->fniv);
break;
case TCG_TYPE_V64:
expand_4_vec(g->vece, dofs, aofs, bofs, cofs, oprsz,
- 8, TCG_TYPE_V64, g->fniv);
+ 8, TCG_TYPE_V64, g->write_aofs, g->fniv);
break;
case 0:
if (g->fni8 && check_size_impl(oprsz, 8)) {
-expand_4_i64(dofs, aofs, bofs, cofs, oprsz, g->fni8);
+expand_4_i64(dofs, aofs, bofs, cofs, oprsz,
+ g->write_aofs, g->fni8);
} else if (g->fni4 && check_size_impl(oprsz, 4)) {
-expand_4_i32(dofs, aofs, bofs, cofs, oprsz, g->fni4);
+expand_4_i32(dofs, aofs, bofs, cofs, oprsz,
+ g->write_aofs, g->fni4);
} else {
assert(g->fno != NULL);
tcg_gen_gvec_4_ool(dofs, aofs, bofs, cofs,
--
2.17.2
[Qemu-devel] [PATCH v2 07/10] tcg/i386: Implement vector saturating arithmetic
Only MO_8 and MO_16 are implemented, since that's all the
instruction set provides.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 2 +-
tcg/i386/tcg-target.inc.c | 42 +++
2 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 7bd7eae672..efbd5a6fc9 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -185,7 +185,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 1
-#define TCG_TARGET_HAS_sat_vec 0
+#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 0
#define TCG_TARGET_deposit_i32_valid(ofs, len) \
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index ad97386d06..feec40a412 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -377,6 +377,10 @@ static inline int tcg_target_const_match(tcg_target_long
val, TCGType type,
#define OPC_PADDW (0xfd | P_EXT | P_DATA16)
#define OPC_PADDD (0xfe | P_EXT | P_DATA16)
#define OPC_PADDQ (0xd4 | P_EXT | P_DATA16)
+#define OPC_PADDSB (0xec | P_EXT | P_DATA16)
+#define OPC_PADDSW (0xed | P_EXT | P_DATA16)
+#define OPC_PADDUB (0xdc | P_EXT | P_DATA16)
+#define OPC_PADDUW (0xdd | P_EXT | P_DATA16)
#define OPC_PAND(0xdb | P_EXT | P_DATA16)
#define OPC_PANDN (0xdf | P_EXT | P_DATA16)
#define OPC_PBLENDW (0x0e | P_EXT3A | P_DATA16)
@@ -408,6 +412,10 @@ static inline int tcg_target_const_match(tcg_target_long
val, TCGType type,
#define OPC_PSUBW (0xf9 | P_EXT | P_DATA16)
#define OPC_PSUBD (0xfa | P_EXT | P_DATA16)
#define OPC_PSUBQ (0xfb | P_EXT | P_DATA16)
+#define OPC_PSUBSB (0xe8 | P_EXT | P_DATA16)
+#define OPC_PSUBSW (0xe9 | P_EXT | P_DATA16)
+#define OPC_PSUBUB (0xd8 | P_EXT | P_DATA16)
+#define OPC_PSUBUW (0xd9 | P_EXT | P_DATA16)
#define OPC_PUNPCKLBW (0x60 | P_EXT | P_DATA16)
#define OPC_PUNPCKLWD (0x61 | P_EXT | P_DATA16)
#define OPC_PUNPCKLDQ (0x62 | P_EXT | P_DATA16)
@@ -2591,9 +2599,21 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static int const add_insn[4] = {
OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ
};
+static int const ssadd_insn[4] = {
+OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2
+};
+static int const usadd_insn[4] = {
+OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2
+};
static int const sub_insn[4] = {
OPC_PSUBB, OPC_PSUBW, OPC_PSUBD, OPC_PSUBQ
};
+static int const sssub_insn[4] = {
+OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2
+};
+static int const ussub_insn[4] = {
+OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2
+};
static int const mul_insn[4] = {
OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_UD2
};
@@ -2631,9 +2651,21 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_add_vec:
insn = add_insn[vece];
goto gen_simd;
+case INDEX_op_ssadd_vec:
+insn = ssadd_insn[vece];
+goto gen_simd;
+case INDEX_op_usadd_vec:
+insn = usadd_insn[vece];
+goto gen_simd;
case INDEX_op_sub_vec:
insn = sub_insn[vece];
goto gen_simd;
+case INDEX_op_sssub_vec:
+insn = sssub_insn[vece];
+goto gen_simd;
+case INDEX_op_ussub_vec:
+insn = ussub_insn[vece];
+goto gen_simd;
case INDEX_op_mul_vec:
insn = mul_insn[vece];
goto gen_simd;
@@ -3007,6 +3039,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_or_vec:
case INDEX_op_xor_vec:
case INDEX_op_andc_vec:
+case INDEX_op_ssadd_vec:
+case INDEX_op_usadd_vec:
+case INDEX_op_sssub_vec:
+case INDEX_op_ussub_vec:
case INDEX_op_cmp_vec:
case INDEX_op_x86_shufps_vec:
case INDEX_op_x86_blend_vec:
@@ -3074,6 +3110,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
}
return 1;
+case INDEX_op_ssadd_vec:
+case INDEX_op_usadd_vec:
+case INDEX_op_sssub_vec:
+case INDEX_op_ussub_vec:
+return vece <= MO_16;
+
default:
return 0;
}
--
2.17.2
Re: [Qemu-devel] AVX support for TCG
Στις Σάβ, 5 Ιαν 2019 στις 12:14 π.μ., ο/η Richard Henderson έγραψε: > No, it's just calling conventions. And it could be worked around, but I think > what we have is convenient enough. > > Especially since the sizes are encoded as (n+1)*8, which also shows the > compiler that the size is positive, so the for loop must iterate at least > once. I know host ABI's can differ like that, but I don't understand why that should matter. Everything (TCG compiler included) is compiled with the same way, right? For the host arch. Or is that a host ABI vs guest ABI thing? Though I don't understand why that would matter either. All this is stuff that runs on the host, right? Oh or does it have to do with JIT'ted tcg helper functions where ABI would matter? No real need to explain, I'm just curious.
Re: [Qemu-devel] AVX support for TCG
Ohh got it, thanks. Στις Σάβ, 5 Ιαν 2019 στις 12:38 π.μ., ο/η Richard Henderson έγραψε: > > On 1/5/19 8:33 AM, Nick Renieris wrote: > > I know host ABI's can differ like that, but I don't understand why > > that should matter. Everything (TCG compiler included) is compiled > > with the same way, right? For the host arch. > > No, not all of the pieces are compiled the same way. TCG generates machine > instructions to perform a call from generated code into compiler generated > code. So TCG needs to know about the host compiler ABI. > > > r~
[Qemu-devel] [PATCH v2 04/10] tcg: Add opcodes for vector saturated arithmetic
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 1 +
tcg/i386/tcg-target.h| 1 +
tcg/tcg-op.h | 4 ++
tcg/tcg-opc.h| 4 ++
tcg/tcg.h| 1 +
tcg/tcg-op-gvec.c| 84 ++--
tcg/tcg-op-vec.c | 34 ++--
tcg/tcg.c| 5 +++
8 files changed, 110 insertions(+), 24 deletions(-)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index f966a4fcb3..98556bcf22 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -135,6 +135,7 @@ typedef enum {
#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 1
+#define TCG_TARGET_HAS_sat_vec 0
#define TCG_TARGET_DEFAULT_MO (0)
#define TCG_TARGET_HAS_MEMORY_BSWAP 1
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index f378d29568..44381062e6 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -185,6 +185,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 1
+#define TCG_TARGET_HAS_sat_vec 0
#define TCG_TARGET_deposit_i32_valid(ofs, len) \
(((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index f6ef1cd690..4a93d730e8 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -967,6 +967,10 @@ void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec
a, TCGv_vec b);
void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
+void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 7a8a3edb5b..94b2ed80af 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -222,6 +222,10 @@ DEF(add_vec, 1, 2, 0, IMPLVEC)
DEF(sub_vec, 1, 2, 0, IMPLVEC)
DEF(mul_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_mul_vec))
DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec))
+DEF(ssadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
+DEF(usadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
+DEF(sssub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
+DEF(ussub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
DEF(and_vec, 1, 2, 0, IMPLVEC)
DEF(or_vec, 1, 2, 0, IMPLVEC)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 3a629991ca..df24afa425 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -183,6 +183,7 @@ typedef uint64_t TCGRegSet;
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_mul_vec 0
+#define TCG_TARGET_HAS_sat_vec 0
#else
#define TCG_TARGET_MAYBE_vec1
#endif
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index c10d3d7b26..0a33f51065 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -1678,10 +1678,22 @@ void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs,
uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
{
static const GVecGen3 g[4] = {
-{ .fno = gen_helper_gvec_ssadd8, .vece = MO_8 },
-{ .fno = gen_helper_gvec_ssadd16, .vece = MO_16 },
-{ .fno = gen_helper_gvec_ssadd32, .vece = MO_32 },
-{ .fno = gen_helper_gvec_ssadd64, .vece = MO_64 }
+{ .fniv = tcg_gen_ssadd_vec,
+ .fno = gen_helper_gvec_ssadd8,
+ .opc = INDEX_op_ssadd_vec,
+ .vece = MO_8 },
+{ .fniv = tcg_gen_ssadd_vec,
+ .fno = gen_helper_gvec_ssadd16,
+ .opc = INDEX_op_ssadd_vec,
+ .vece = MO_16 },
+{ .fniv = tcg_gen_ssadd_vec,
+ .fno = gen_helper_gvec_ssadd32,
+ .opc = INDEX_op_ssadd_vec,
+ .vece = MO_32 },
+{ .fniv = tcg_gen_ssadd_vec,
+ .fno = gen_helper_gvec_ssadd64,
+ .opc = INDEX_op_ssadd_vec,
+ .vece = MO_64 },
};
tcg_debug_assert(vece <= MO_64);
tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, [vece]);
@@ -1691,16 +1703,28 @@ void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs,
uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
{
static const GVecGen3 g[4] = {
-{ .fno = gen_helper_gvec_sssub8, .vece = MO_8 },
-{ .fno = gen_helper_gvec_sssub16, .vece = MO_16 },
-{ .fno = gen_helper_gvec_sssub32, .vece = MO_32 },
-{ .fno = gen_helper_gvec_sssub64, .vece = MO_64 }
+{ .fniv = tcg_gen_sssub_vec,
+
[Qemu-devel] [PATCH v2 10/10] tcg/aarch64: Implement vector minmax arithmetic
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 2 +-
tcg/aarch64/tcg-target.inc.c | 24
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index a1884543d0..2d93cf404e 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -136,7 +136,7 @@ typedef enum {
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
-#define TCG_TARGET_HAS_minmax_vec 0
+#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_DEFAULT_MO (0)
#define TCG_TARGET_HAS_MEMORY_BSWAP 1
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index b2b011f130..ee0d5819af 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -528,8 +528,12 @@ typedef enum {
I3616_CMHI = 0x2e203400,
I3616_CMHS = 0x2e203c00,
I3616_CMEQ = 0x2e208c00,
+I3616_SMAX = 0x0e206400,
+I3616_SMIN = 0x0e206c00,
I3616_SQADD = 0x0e200c00,
I3616_SQSUB = 0x0e202c00,
+I3616_UMAX = 0x2e206400,
+I3616_UMIN = 0x2e206c00,
I3616_UQADD = 0x2e200c00,
I3616_UQSUB = 0x2e202c00,
@@ -2153,6 +2157,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_ussub_vec:
tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2);
break;
+case INDEX_op_smax_vec:
+tcg_out_insn(s, 3616, SMAX, is_q, vece, a0, a1, a2);
+break;
+case INDEX_op_smin_vec:
+tcg_out_insn(s, 3616, SMIN, is_q, vece, a0, a1, a2);
+break;
+case INDEX_op_umax_vec:
+tcg_out_insn(s, 3616, UMAX, is_q, vece, a0, a1, a2);
+break;
+case INDEX_op_umin_vec:
+tcg_out_insn(s, 3616, UMIN, is_q, vece, a0, a1, a2);
+break;
case INDEX_op_not_vec:
tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1);
break;
@@ -2227,6 +2243,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_sssub_vec:
case INDEX_op_usadd_vec:
case INDEX_op_ussub_vec:
+case INDEX_op_smax_vec:
+case INDEX_op_smin_vec:
+case INDEX_op_umax_vec:
+case INDEX_op_umin_vec:
return 1;
case INDEX_op_mul_vec:
return vece < MO_64;
@@ -2410,6 +2430,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_sssub_vec:
case INDEX_op_usadd_vec:
case INDEX_op_ussub_vec:
+case INDEX_op_smax_vec:
+case INDEX_op_smin_vec:
+case INDEX_op_umax_vec:
+case INDEX_op_umin_vec:
return _w_w;
case INDEX_op_not_vec:
case INDEX_op_neg_vec:
--
2.17.2
Re: [Qemu-devel] [RFC PATCH] osdep: Make MIN/MAX evaluate arguments only once
Patchew URL: https://patchew.org/QEMU/20190104153951.32306-1-ebl...@redhat.com/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN === #!/bin/bash time make docker-test-quick@centos7 SHOW_ENV=1 J=8 === TEST SCRIPT END === libpmem support no libudev no WARNING: Use of SDL 1.2 is deprecated and will be removed in WARNING: future releases. Please switch to using SDL 2.0 NOTE: cross-compilers enabled: 'cc' GEN x86_64-softmmu/config-devices.mak.tmp --- CC block/commit.o In file included from /tmp/qemu-test/src/block/block-backend.c:13:0: /tmp/qemu-test/src/block/block-backend.c: In function 'blk_get_max_transfer': /tmp/qemu-test/src/include/qemu/osdep.h:257:9: error: unknown type name '__auto_type' __auto_type _a = (a); \ ^ /tmp/qemu-test/src/block/block-backend.c:1817:12: note: in expansion of macro 'MIN_NON_ZERO' return MIN_NON_ZERO(max, INT_MAX); ^ /tmp/qemu-test/src/include/qemu/osdep.h:258:9: error: unknown type name '__auto_type' __auto_type _b = (b); \ ^ /tmp/qemu-test/src/block/block-backend.c:1817:12: note: in expansion of macro 'MIN_NON_ZERO' return MIN_NON_ZERO(max, INT_MAX); ^ /tmp/qemu-test/src/block/block-backend.c: At top level: cc1: error: unrecognized command line option "-Wno-format-truncation" [-Werror] cc1: all warnings being treated as errors make: *** [block/block-backend.o] Error 1 make: *** Waiting for unfinished jobs The full log is available at http://patchew.org/logs/20190104153951.32306-1-ebl...@redhat.com/testing.docker-quick@centos7/?type=message. --- Email generated automatically by Patchew [http://patchew.org/]. Please send your feedback to patchew-de...@redhat.com
Re: [Qemu-devel] AVX support for TCG
On 1/5/19 8:33 AM, Nick Renieris wrote: > I know host ABI's can differ like that, but I don't understand why > that should matter. Everything (TCG compiler included) is compiled > with the same way, right? For the host arch. No, not all of the pieces are compiled the same way. TCG generates machine instructions to perform a call from generated code into compiler generated code. So TCG needs to know about the host compiler ABI. r~
Re: [Qemu-devel] [PATCH 00/34] tcg, target/ppc vector improvements
On 1/4/19 4:31 AM, Mark Cave-Ayland wrote: > Fixing the vsplt instruction now gives a readable display in my MacOS tests, > but I'm > still seeing "shadows" such as > https://www.ilande.co.uk/tmp/qemu/badapple4.png which > I've bisected down to: > > > commit 71f229eb331e979971a0a79e5a2fcdfb9380bd06 > Author: Richard Henderson > Date: Mon Dec 17 22:39:10 2018 -0800 > > target/ppc: convert vadd*s and vsub*s to vector operations > > Signed-off-by: Richard Henderson > > > So looks like there's something still not quite right with the saturation > flag/vector > saturation implementation. > Ok, I'll try and set up some RISU tests to track this down next week. r~
[Qemu-devel] [PATCH v2 02/10] tcg: Add gvec expanders for nand, nor, eqv
Reviewed-by: David Gibson
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime.h | 3 +++
tcg/tcg-op-gvec.h| 6 +
tcg/tcg-op.h | 3 +++
accel/tcg/tcg-runtime-gvec.c | 33 +++
tcg/tcg-op-gvec.c| 51
tcg/tcg-op-vec.c | 21 +++
6 files changed, 117 insertions(+)
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index 1bd39d136d..835ddfebb2 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -211,6 +211,9 @@ DEF_HELPER_FLAGS_4(gvec_or, TCG_CALL_NO_RWG, void, ptr,
ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_xor, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_andc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_orc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_nand, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_nor, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_eqv, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_ands, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_xors, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index ff43a29a0b..d65b9d9d4c 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -242,6 +242,12 @@ void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs,
uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_nand(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_nor(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_eqv(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t c, uint32_t oprsz, uint32_t maxsz);
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 7007ec0d4d..f6ef1cd690 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -962,6 +962,9 @@ void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a,
TCGv_vec b);
void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index 90340e56e0..d1802467d5 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -512,6 +512,39 @@ void HELPER(gvec_orc)(void *d, void *a, void *b, uint32_t
desc)
clear_high(d, oprsz, desc);
}
+void HELPER(gvec_nand)(void *d, void *a, void *b, uint32_t desc)
+{
+intptr_t oprsz = simd_oprsz(desc);
+intptr_t i;
+
+for (i = 0; i < oprsz; i += sizeof(vec64)) {
+*(vec64 *)(d + i) = ~(*(vec64 *)(a + i) & *(vec64 *)(b + i));
+}
+clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_nor)(void *d, void *a, void *b, uint32_t desc)
+{
+intptr_t oprsz = simd_oprsz(desc);
+intptr_t i;
+
+for (i = 0; i < oprsz; i += sizeof(vec64)) {
+*(vec64 *)(d + i) = ~(*(vec64 *)(a + i) | *(vec64 *)(b + i));
+}
+clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_eqv)(void *d, void *a, void *b, uint32_t desc)
+{
+intptr_t oprsz = simd_oprsz(desc);
+intptr_t i;
+
+for (i = 0; i < oprsz; i += sizeof(vec64)) {
+*(vec64 *)(d + i) = ~(*(vec64 *)(a + i) ^ *(vec64 *)(b + i));
+}
+clear_high(d, oprsz, desc);
+}
+
void HELPER(gvec_ands)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index ec231b78fb..81689d02f7 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -1920,6 +1920,57 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs,
uint32_t aofs,
}
}
+void tcg_gen_gvec_nand(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+static const GVecGen3 g = {
+.fni8 = tcg_gen_nand_i64,
+.fniv = tcg_gen_nand_vec,
+.fno = gen_helper_gvec_nand,
+.prefer_i64 = TCG_TARGET_REG_BITS == 64,
+};
+
+if (aofs == bofs) {
+tcg_gen_gvec_not(vece, dofs, aofs, oprsz, maxsz);
+} else {
+
[Qemu-devel] [PATCH v2 09/10] tcg/aarch64: Implement vector saturating arithmetic
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 2 +-
tcg/aarch64/tcg-target.inc.c | 24
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 545a6eec75..a1884543d0 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -135,7 +135,7 @@ typedef enum {
#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 1
-#define TCG_TARGET_HAS_sat_vec 0
+#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 0
#define TCG_TARGET_DEFAULT_MO (0)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 0562e0aa40..b2b011f130 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -528,6 +528,10 @@ typedef enum {
I3616_CMHI = 0x2e203400,
I3616_CMHS = 0x2e203c00,
I3616_CMEQ = 0x2e208c00,
+I3616_SQADD = 0x0e200c00,
+I3616_SQSUB = 0x0e202c00,
+I3616_UQADD = 0x2e200c00,
+I3616_UQSUB = 0x2e202c00,
/* AdvSIMD two-reg misc. */
I3617_CMGT0 = 0x0e208800,
@@ -2137,6 +2141,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_orc_vec:
tcg_out_insn(s, 3616, ORN, is_q, 0, a0, a1, a2);
break;
+case INDEX_op_ssadd_vec:
+tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2);
+break;
+case INDEX_op_sssub_vec:
+tcg_out_insn(s, 3616, SQSUB, is_q, vece, a0, a1, a2);
+break;
+case INDEX_op_usadd_vec:
+tcg_out_insn(s, 3616, UQADD, is_q, vece, a0, a1, a2);
+break;
+case INDEX_op_ussub_vec:
+tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2);
+break;
case INDEX_op_not_vec:
tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1);
break;
@@ -2207,6 +2223,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
+case INDEX_op_ssadd_vec:
+case INDEX_op_sssub_vec:
+case INDEX_op_usadd_vec:
+case INDEX_op_ussub_vec:
return 1;
case INDEX_op_mul_vec:
return vece < MO_64;
@@ -2386,6 +2406,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_xor_vec:
case INDEX_op_andc_vec:
case INDEX_op_orc_vec:
+case INDEX_op_ssadd_vec:
+case INDEX_op_sssub_vec:
+case INDEX_op_usadd_vec:
+case INDEX_op_ussub_vec:
return _w_w;
case INDEX_op_not_vec:
case INDEX_op_neg_vec:
--
2.17.2
[Qemu-devel] [PATCH v2 08/10] tcg/i386: Implement vector minmax arithmetic
The avx instruction set does not directly provide MO_64.
We can still implement 64-bit with comparison and vpblendvb.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 2 +-
tcg/i386/tcg-target.inc.c | 81 +++
2 files changed, 82 insertions(+), 1 deletion(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index efbd5a6fc9..7995fe3eab 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -186,7 +186,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
-#define TCG_TARGET_HAS_minmax_vec 0
+#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_deposit_i32_valid(ofs, len) \
(((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index feec40a412..94007c7aa5 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -392,6 +392,18 @@ static inline int tcg_target_const_match(tcg_target_long
val, TCGType type,
#define OPC_PCMPGTW (0x65 | P_EXT | P_DATA16)
#define OPC_PCMPGTD (0x66 | P_EXT | P_DATA16)
#define OPC_PCMPGTQ (0x37 | P_EXT38 | P_DATA16)
+#define OPC_PMAXSB (0x3c | P_EXT38 | P_DATA16)
+#define OPC_PMAXSW (0xee | P_EXT | P_DATA16)
+#define OPC_PMAXSD (0x3d | P_EXT38 | P_DATA16)
+#define OPC_PMAXUB (0xde | P_EXT | P_DATA16)
+#define OPC_PMAXUW (0x3e | P_EXT38 | P_DATA16)
+#define OPC_PMAXUD (0x3f | P_EXT38 | P_DATA16)
+#define OPC_PMINSB (0x38 | P_EXT38 | P_DATA16)
+#define OPC_PMINSW (0xea | P_EXT | P_DATA16)
+#define OPC_PMINSD (0x39 | P_EXT38 | P_DATA16)
+#define OPC_PMINUB (0xda | P_EXT | P_DATA16)
+#define OPC_PMINUW (0x3a | P_EXT38 | P_DATA16)
+#define OPC_PMINUD (0x3b | P_EXT38 | P_DATA16)
#define OPC_PMOVSXBW(0x20 | P_EXT38 | P_DATA16)
#define OPC_PMOVSXWD(0x23 | P_EXT38 | P_DATA16)
#define OPC_PMOVSXDQ(0x25 | P_EXT38 | P_DATA16)
@@ -2638,6 +2650,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static int const packus_insn[4] = {
OPC_PACKUSWB, OPC_PACKUSDW, OPC_UD2, OPC_UD2
};
+static int const smin_insn[4] = {
+OPC_PMINSB, OPC_PMINSW, OPC_PMINSD, OPC_UD2
+};
+static int const smax_insn[4] = {
+OPC_PMAXSB, OPC_PMAXSW, OPC_PMAXSD, OPC_UD2
+};
+static int const umin_insn[4] = {
+OPC_PMINUB, OPC_PMINUW, OPC_PMINUD, OPC_UD2
+};
+static int const umax_insn[4] = {
+OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2
+};
TCGType type = vecl + TCG_TYPE_V64;
int insn, sub;
@@ -2678,6 +2702,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_xor_vec:
insn = OPC_PXOR;
goto gen_simd;
+case INDEX_op_smin_vec:
+insn = smin_insn[vece];
+goto gen_simd;
+case INDEX_op_umin_vec:
+insn = umin_insn[vece];
+goto gen_simd;
+case INDEX_op_smax_vec:
+insn = smax_insn[vece];
+goto gen_simd;
+case INDEX_op_umax_vec:
+insn = umax_insn[vece];
+goto gen_simd;
case INDEX_op_x86_punpckl_vec:
insn = punpckl_insn[vece];
goto gen_simd;
@@ -3043,6 +3079,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_usadd_vec:
case INDEX_op_sssub_vec:
case INDEX_op_ussub_vec:
+case INDEX_op_smin_vec:
+case INDEX_op_umin_vec:
+case INDEX_op_smax_vec:
+case INDEX_op_umax_vec:
case INDEX_op_cmp_vec:
case INDEX_op_x86_shufps_vec:
case INDEX_op_x86_blend_vec:
@@ -3115,6 +3155,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_sssub_vec:
case INDEX_op_ussub_vec:
return vece <= MO_16;
+case INDEX_op_smin_vec:
+case INDEX_op_smax_vec:
+case INDEX_op_umin_vec:
+case INDEX_op_umax_vec:
+return vece <= MO_32 ? 1 : -1;
default:
return 0;
@@ -3343,6 +3388,25 @@ static void expand_vec_cmp(TCGType type, unsigned vece,
TCGv_vec v0,
}
}
+static void expand_vec_minmax(TCGType type, unsigned vece,
+ TCGCond cond, bool min,
+ TCGv_vec v0, TCGv_vec v1, TCGv_vec v2)
+{
+TCGv_vec t1 = tcg_temp_new_vec(type);
+
+tcg_debug_assert(vece == MO_64);
+
+tcg_gen_cmp_vec(cond, vece, t1, v1, v2);
+if (min) {
+TCGv_vec t2;
+t2 = v1, v1 = v2, v2 = t2;
+}
+vec_gen_4(INDEX_op_x86_vpblendvb_vec, type, vece,
+ tcgv_vec_arg(v0), tcgv_vec_arg(v1),
+ tcgv_vec_arg(v2), tcgv_vec_arg(t1));
+tcg_temp_free_vec(t1);
+}
+
void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
TCGArg a0, ...)
{
@@ -3375,6 +3439,23 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,
unsigned vece,
expand_vec_cmp(type, vece, v0, v1,
[Qemu-devel] [PATCH v2 01/10] tcg: Add logical simplifications during gvec expand
We handle many of these during integer expansion, and the
rest of them during integer optimization.
Reviewed-by: David Gibson
Signed-off-by: Richard Henderson
---
tcg/tcg-op-gvec.c | 35 ++-
1 file changed, 30 insertions(+), 5 deletions(-)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 61c25f5784..ec231b78fb 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -1840,7 +1840,12 @@ void tcg_gen_gvec_and(unsigned vece, uint32_t dofs,
uint32_t aofs,
.opc = INDEX_op_and_vec,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
};
-tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, );
+
+if (aofs == bofs) {
+tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);
+} else {
+tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, );
+}
}
void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs,
@@ -1853,7 +1858,12 @@ void tcg_gen_gvec_or(unsigned vece, uint32_t dofs,
uint32_t aofs,
.opc = INDEX_op_or_vec,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
};
-tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, );
+
+if (aofs == bofs) {
+tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);
+} else {
+tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, );
+}
}
void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs,
@@ -1866,7 +1876,12 @@ void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs,
uint32_t aofs,
.opc = INDEX_op_xor_vec,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
};
-tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, );
+
+if (aofs == bofs) {
+tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, 0);
+} else {
+tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, );
+}
}
void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs,
@@ -1879,7 +1894,12 @@ void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs,
uint32_t aofs,
.opc = INDEX_op_andc_vec,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
};
-tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, );
+
+if (aofs == bofs) {
+tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, 0);
+} else {
+tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, );
+}
}
void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
@@ -1892,7 +1912,12 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs,
uint32_t aofs,
.opc = INDEX_op_orc_vec,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
};
-tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, );
+
+if (aofs == bofs) {
+tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, -1);
+} else {
+tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, );
+}
}
static const GVecGen2s gop_ands = {
--
2.17.2
Re: [Qemu-devel] [Qemu-ppc] [PATCH 02/16] hw: Remove unused 'hw/devices.h' include
On Fri, 4 Jan 2019, Philippe Mathieu-Daudé wrote: diff --git a/hw/display/sm501.c b/hw/display/sm501.c index 4a8686f0f5..2122291308 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -32,7 +32,6 @@ #include "hw/hw.h" #include "hw/char/serial.h" #include "ui/console.h" -#include "hw/devices.h" #include "hw/sysbus.h" #include "hw/pci/pci.h" #include "hw/i2c/i2c.h" Looks like I forgot to drop this include in ca8a110470 Reviewed-by: BALATON Zoltan
Re: [Qemu-devel] [PATCH v4 08/10] block/nbd: add cmdline and qapi parameter reconnect-delay
On 7/31/18 12:30 PM, Vladimir Sementsov-Ogievskiy wrote:
> Reconnect will be implemented in the following commit, so for now,
> in semantics below, disconnect itself is a "serious error".
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
> qapi/block-core.json | 12 +++-
> block/nbd-client.h | 1 +
> block/nbd-client.c | 1 +
> block/nbd.c | 16 +++-
> 4 files changed, 28 insertions(+), 2 deletions(-)
>
> diff --git a/qapi/block-core.json b/qapi/block-core.json
> index 5b9084a394..cf03402ec5 100644
> --- a/qapi/block-core.json
> +++ b/qapi/block-core.json
> @@ -3511,13 +3511,23 @@
> # traditional "base:allocation" block status (see
> # NBD_OPT_LIST_META_CONTEXT in the NBD protocol) (since 3.0)
> #
> +# @reconnect-delay: Reconnect delay. On disconnect, nbd client tries to
> connect
Maybe 'On unexpected disconnect', since intentional disconnect is not
unexpected.
> +# again, until success or serious error. During first
> +# @reconnect-delay seconds of reconnecting loop all
> requests
> +# are paused and have a chance to rerun, if successful
> +# connect occures during this time. After @reconnect-delay
occurs
> +# seconds all delayed requests are failed and all following
> +# requests will be failed to (until successfull reconnect).
successful
> +# Default 300 seconds (Since 3.1)
My delay in reviewing means this now has to be 4.0.
I'm guessing that a delay of 0 means disable auto-reconnect. From a
backwards-compatibility standpoint, no auto-reconnect is more in line
with what we previously had - but from a usability standpoint, trying to
reconnect can avoid turning transient network hiccups into permanent
loss of a device to EIO errors, especially if the retry timeout is long
enough to allow an administrator to reroute the network to an
alternative server. So I'm probably okay with the default being
non-zero - but it DOES mean that where you used to get instant EIO
failures when a network connection was severed, you now have to wait for
the reconnect delay to expire, and 5 minutes can be a long wait. Since
the long delay is guest-observable, can we run into issues where a guest
that is currently used to instant EIO and total loss of the device could
instead get confused by not getting any response for up to 5 minutes,
whether or not that response eventually turns out to be EIO or a
successful recovery?
> +++ b/block/nbd.c
> @@ -360,6 +360,18 @@ static QemuOptsList nbd_runtime_opts = {
> .help = "experimental: expose named dirty bitmap in place of "
> "block status",
> },
> +{
> +.name = "reconnect-delay",
> +.type = QEMU_OPT_NUMBER,
> +.help = "Reconnect delay. On disconnect, nbd client tries to"
> +"connect again, until success or serious error. During"
> +"first @reconnect-delay seconds of reconnecting loop all"
> +"requests are paused and have a chance to rerun, if"
> +"successful connect occures during this time. After"
> +"@reconnect-delay seconds all delayed requests are
> failed"
> +"and all following requests will be failed to (until"
> +"successfull reconnect). Default 300 seconds",
Same typos as in qapi.
The UI aspects look fine, now I need to review the patch series for code
issues :)
--
Eric Blake, Principal Software Engineer
Red Hat, Inc. +1-919-301-3226
Virtualization: qemu.org | libvirt.org
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Description: OpenPGP digital signature
Re: [Qemu-devel] AVX support for TCG
Στις Παρ, 4 Ιαν 2019 στις 11:51 μ.μ., ο/η Richard Henderson έγραψε: > As an integer it is always passed by value. As a structure some host abis > pass > it by reference, and the TCG compiler doesn't know about that. Ah so they modify it? If so it could surely be worked around with explicit stack copies, right?
Re: [Qemu-devel] [PATCH v2 00/52] Audio 5.1 patches
On 2019-01-01 17:17, Programmingkid wrote: > >> On Jan 1, 2019, at 7:27 AM, Zoltán Kővágó wrote: >> >> On 2019-01-01 05:24, Programmingkid wrote: On 2018-12-29 01:49, Programmingkid wrote: >> [snip] > > I tried ac97 with a Windows 2000 guest in qemu-system-i386 - same demonic > sound. > With the above configuration but with an es1370 sound card I heard the > same sound. I kept seeing "es1370: warning: non looping mode" being > printed in the terminal. This problem might need its own patch. > Using the sb16 sound card I heard the same unsettling sound. > > I could not test the HDA driver due to problems with my Windows 7 VM. > I have a feeling that bf870a0cf5e2c2dd7438e65473b4fca1fb0ca5d1 (coreaudio: port to the new audio backend api) is the commit which breaks it, but without a mac I don't know how could I debug it. The way it initializes coreaudio changed a bit, that can cause problems. Could you please test whether this commit is the culprit or not? Regards, Zoltan >>> >>> >>> Hi how do you want me to test your theory? Revert the patch? If I did I >>> don't think QEMU would still compile. >> >> No, don't revert it, that would generate too many conflicts. Just >> >> git checkout bf870a0c > > This causes the very disturbing sound to play. > >> >> and >> >> git checkout bf870a0c~ > > This also causes the very disturbing sound to play. > >> >> should give you two versions that you can compare. >> >> Regards, >> Zoltan > > Thank you. > That's worrying, since before that commit I didn't really do any big refactoring on coreaudio itself, and without a Mac I have no idea how could I debug it. Could you at least try a git bisect and figure out which commit broke it? Thanks, Zoltan
Re: [Qemu-devel] [PATCH 1/1] include: Auto-generate the sizes lookup table
On 1/4/19 12:31 PM, Alberto Garcia wrote: > On Thu 03 Jan 2019 10:42:30 PM CET, Eric Blake wrote: > >> In my view, code generators make sense when used on code that is >> expected to change over time (a good example is QAPI because we add >> new commands every release; other places might be a generator to help >> deal with syscall handlers since newer kernels can add a syscall; or >> even the fact that we have used some powerful GNU make textual >> processing to make it easy to add files to particular subsets of the >> build with as few lines edited as possible), where the goal is that >> the generator gives you both a compact representation that is easier >> to edit, and that the expansion from the generator ensures that >> repetitive boilerplate is formed without typos. In short, if a >> generator results in a net reduction in lines of edited source in >> relation to the lines it produces, AND if the source that gets >> regenerated is likely to change, then it makes total sense to spend >> time on the generator. But when the amount of effort to write a >> generator costs as much as just hard-coding the list outright, >> especially when the list is not going to change (there really aren't >> any other powers of 2 within 64 bits), I'm not sure a generator adds >> any value. > > I agree with Eric. Fine with me. I just thought that in the previous conversation (https://patchwork.kernel.org/patch/10666975/#22302435) we have agreed that I'll send this patch. I've sent v2 already with Phil's suggestions included, please feel free to pull it if desired. Leonid. > > Berto >
Re: [Qemu-devel] [PATCH] compat: Use explicit type names on HW_COMPAT_2_6
On Fri, Jan 04, 2019 at 07:06:56PM -0200, Eduardo Habkost wrote:
> On Fri, Jan 04, 2019 at 03:48:02PM -0500, Michael S. Tsirkin wrote:
> > On Fri, Jan 04, 2019 at 06:09:52PM -0200, Eduardo Habkost wrote:
> > > On Fri, Jan 04, 2019 at 03:54:39PM -0200, Eduardo Habkost wrote:
> > > > On Fri, Jan 04, 2019 at 10:12:00AM +, Dr. David Alan Gilbert wrote:
> > > > > * Michael S. Tsirkin (m...@redhat.com) wrote:
> > > > > > On Fri, Jan 04, 2019 at 01:22:26AM -0200, Eduardo Habkost wrote:
> > > > > > > The virtio-pci entries in HW_COMPAT_2_6 had an implicit
> > > > > > > assumption: that all virtio-pci subclasses support the
> > > > > > > disable-legacy and disable-modern options.
> > > > > > >
> > > > > > > That assumption was broken by commit f6e501a28ef9 ("virtio:
> > > > > > > Provide version-specific variants of virtio PCI devices"). This
> > > > > > > caused QEMU to crash if using the new -non-transitional or
> > > > > > > -transitional device types:
> > > > > > >
> > > > > > > $ qemu-system-x86_64 -machine pc-i440fx-2.6 \
> > > > > > > -device virtio-net-pci-non-transitional
> > > > > > > Unexpected error in object_property_find() at qom/object.c:1092:
> > > > > > > qemu-system-x86_64: -device virtio-net-pci-non-transitional:
> > > > > > > can't apply \
> > > > > > > global virtio-pci.disable-modern=on: Property '.disable-modern'
> > > > > > > not found
> > > > > > > Aborted (core dumped)
> > > > > > >
> > > > > > > Replace the virtio-pci.disable-legacy=off and
> > > > > > > virtio-pci.disable-modern=on entries on HW_COMPAT_2_6 with
> > > > > > > explicit entries for each generic virtio device type.
> > > > > > >
> > > > > > > The full list of generic virtio device types was extracted by
> > > > > > > just grepping for ".generic_name". Note that we don't need to
> > > > > > > worry about listing new virtio-pci devices in HW_COMPAT_2_6 in
> > > > > > > the future, because new devices won't require QEMU 2.6
> > > > > > > compatibility.
> > > > > >
> > > > > > I fully expect that e.g. packed ring support will need
> > > > > > to affect all virtio devices too. And it's likely
> > > > > > that we'll have some new virtio-pci transport features too.
> > > > > >
> > > > > > > This makes the compat entries annoyingly verbose, but is simpler
> > > > > > > than the alternative of making the virtio-pci type inheritance
> > > > > > > rules even more complex.
> > > > > >
> > > > > > God forbid we forgot something, the only way to notice is to
> > > > > > run a cross version migration with an old qemu.
> > > > > > I think we need to come up with something less verbose and fragile.
> > > > >
> > > > > I guess we could use a script like tests/acceptance/virtio_version.py
> > > > > to
> > > > > do a check?
> > > >
> > > > That's a good idea. On test code we can try additional tricks to
> > > > detect the hybrid virtio devices without increasing the
> > > > complexity of QEMU code. I'll give it a try.
> > >
> > > I did it but I'm not happy with the result: many of the virtio
> > > devices can't be tested without extra arguments. Some of them
> > > (like vhost-*) require extra privileges on the host that might be
> > > unavailable.
> > >
> > > Anyway, while writing this I noticed another issue: many of the
> > > virtio devices in QEMU 2.6 were already modern-only!
> > >
> > > Setting disable-modern=off on modern-only devices like virtio-vga
> > > or virtio-tablet-pci doesn't make sense. This means setting
> > > virtio-pci.disable-modern=off on HW_COMPAT_2_6 was incorrect even
> > > before the -non-transitional and -transitional device types were
> > > introduced.
> >
> >
> > It did create an opportunity to create non working devices.
> >
> > Whether that's incorrect as such I'm not sure.
>
> This is not just creating the opportunity for an user to
> disable-modern=on. HW_COMPAT_2_6 is actually setting
> disable-modern=on on virtio-vga and other modern-only devices.
> Sounds like a mistake to me.
>
> Luckily those modern-only devices silently ignore the
> disable-modern/disable-legacy properties, but this might change
> in the future.
Worry about it then?
--
MST
Re: [Qemu-devel] [PATCH] compat: Use explicit type names on HW_COMPAT_2_6
On Fri, Jan 04, 2019 at 03:48:02PM -0500, Michael S. Tsirkin wrote:
> On Fri, Jan 04, 2019 at 06:09:52PM -0200, Eduardo Habkost wrote:
> > On Fri, Jan 04, 2019 at 03:54:39PM -0200, Eduardo Habkost wrote:
> > > On Fri, Jan 04, 2019 at 10:12:00AM +, Dr. David Alan Gilbert wrote:
> > > > * Michael S. Tsirkin (m...@redhat.com) wrote:
> > > > > On Fri, Jan 04, 2019 at 01:22:26AM -0200, Eduardo Habkost wrote:
> > > > > > The virtio-pci entries in HW_COMPAT_2_6 had an implicit
> > > > > > assumption: that all virtio-pci subclasses support the
> > > > > > disable-legacy and disable-modern options.
> > > > > >
> > > > > > That assumption was broken by commit f6e501a28ef9 ("virtio:
> > > > > > Provide version-specific variants of virtio PCI devices"). This
> > > > > > caused QEMU to crash if using the new -non-transitional or
> > > > > > -transitional device types:
> > > > > >
> > > > > > $ qemu-system-x86_64 -machine pc-i440fx-2.6 \
> > > > > > -device virtio-net-pci-non-transitional
> > > > > > Unexpected error in object_property_find() at qom/object.c:1092:
> > > > > > qemu-system-x86_64: -device virtio-net-pci-non-transitional:
> > > > > > can't apply \
> > > > > > global virtio-pci.disable-modern=on: Property '.disable-modern'
> > > > > > not found
> > > > > > Aborted (core dumped)
> > > > > >
> > > > > > Replace the virtio-pci.disable-legacy=off and
> > > > > > virtio-pci.disable-modern=on entries on HW_COMPAT_2_6 with
> > > > > > explicit entries for each generic virtio device type.
> > > > > >
> > > > > > The full list of generic virtio device types was extracted by
> > > > > > just grepping for ".generic_name". Note that we don't need to
> > > > > > worry about listing new virtio-pci devices in HW_COMPAT_2_6 in
> > > > > > the future, because new devices won't require QEMU 2.6
> > > > > > compatibility.
> > > > >
> > > > > I fully expect that e.g. packed ring support will need
> > > > > to affect all virtio devices too. And it's likely
> > > > > that we'll have some new virtio-pci transport features too.
> > > > >
> > > > > > This makes the compat entries annoyingly verbose, but is simpler
> > > > > > than the alternative of making the virtio-pci type inheritance
> > > > > > rules even more complex.
> > > > >
> > > > > God forbid we forgot something, the only way to notice is to
> > > > > run a cross version migration with an old qemu.
> > > > > I think we need to come up with something less verbose and fragile.
> > > >
> > > > I guess we could use a script like tests/acceptance/virtio_version.py to
> > > > do a check?
> > >
> > > That's a good idea. On test code we can try additional tricks to
> > > detect the hybrid virtio devices without increasing the
> > > complexity of QEMU code. I'll give it a try.
> >
> > I did it but I'm not happy with the result: many of the virtio
> > devices can't be tested without extra arguments. Some of them
> > (like vhost-*) require extra privileges on the host that might be
> > unavailable.
> >
> > Anyway, while writing this I noticed another issue: many of the
> > virtio devices in QEMU 2.6 were already modern-only!
> >
> > Setting disable-modern=off on modern-only devices like virtio-vga
> > or virtio-tablet-pci doesn't make sense. This means setting
> > virtio-pci.disable-modern=off on HW_COMPAT_2_6 was incorrect even
> > before the -non-transitional and -transitional device types were
> > introduced.
>
>
> It did create an opportunity to create non working devices.
>
> Whether that's incorrect as such I'm not sure.
This is not just creating the opportunity for an user to
disable-modern=on. HW_COMPAT_2_6 is actually setting
disable-modern=on on virtio-vga and other modern-only devices.
Sounds like a mistake to me.
Luckily those modern-only devices silently ignore the
disable-modern/disable-legacy properties, but this might change
in the future.
--
Eduardo
[Qemu-devel] [Bug 1701835] Re: floating-point operation bugs in qemu-alpha
Most likely some bits are initialized differently in the FPCR. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1701835 Title: floating-point operation bugs in qemu-alpha Status in QEMU: New Bug description: When running the gnulib testsuite, I'm seeing test failures in the tests for libm functions cbrt cbrtf ceil ceilf coshf exp2 exp2f floor floorf fma fmaf fmal frexp frexpf hypot hypotf hypotl ilogb ilogbf isfinite isinf isnan isnand isnanf ldexp ldexpf ldexpl log1p log1pf log2 log2f logb logbf logbl rint rintf rintl signbit sqrt sqrtf strtod that I don't see when running the same (statically linked) executables in a VM, through qemu-system-alpha. How to reproduce: - Using gnulib, run ./gnulib-tool --create-testdir --dir=../testdir-math --single-configure cbrt cbrtf ceil ceilf coshf exp2 exp2f float floor floorf fma fmaf fmal frexp frexpf hypot hypotf hypotl ilogb ilogbf isfinite isinf isnan isnand isnanf ldexp ldexpf ldexpl log1p log1pf log2 log2f logb logbf logbl math printf-frexp rint rintf rintl round roundf signbit sqrt sqrtf strtod trunc truncf - Copy the resulting directory to a VM running Linux 2.6.26 with qemu-system-alpha. - There, configure and build the package: mkdir build-native-static; cd build-native-static; ../configure CPPFLAGS="-Wall" LDFLAGS="-static"; make; make check Only 4 tests fail. - Copy the resulting binaries back to the original x86_64 machine. - Set environment variables for using qemu-alpha. - Here, 50 tests fail that did not fail originally: $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-cbrt ../../gltests/test-cbrt.h:39: assertion 'err > - L_(4.0) * L_(16.0) / TWO_MANT_DIG && err < L_(4.0) * L_(16.0) / TWO_MANT_DIG' failed Aborted (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-ceil1 Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-ceil2 Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-ceilf1 Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-ceilf2 Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-coshf ../../gltests/test-coshf.c:37: assertion 'y >= 1.1854652f && y <= 1.1854653f' failed Aborted (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-float Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-floor1 Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-floor2 Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-floorf1 Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-floorf2 Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-fma1 Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-fma2 ../../gltests/test-fma2.h:116: assertion 'result == expected' failed Aborted (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-fmaf1 Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-fmaf2 ../../gltests/test-fma2.h:116: assertion 'result == expected' failed Aborted (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-fmal2 ../../gltests/test-fma2.h:116: assertion 'result == expected' failed Aborted (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-frexp Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-frexpf Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-hypot Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-hypotf Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-hypotl ../../gltests/test-hypot.h:41: assertion 'z == HUGEVAL' failed Aborted (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-ilogb Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-ilogbf Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-isfinite Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-isinf Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-isnan Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-isnand-nolibm Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-isnand Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-isnanf-nolibm Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-isnanf Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-ldexp Floating point
Re: [Qemu-devel] [PATCH] compat: Use explicit type names on HW_COMPAT_2_6
On Fri, Jan 04, 2019 at 06:09:52PM -0200, Eduardo Habkost wrote:
> On Fri, Jan 04, 2019 at 03:54:39PM -0200, Eduardo Habkost wrote:
> > On Fri, Jan 04, 2019 at 10:12:00AM +, Dr. David Alan Gilbert wrote:
> > > * Michael S. Tsirkin (m...@redhat.com) wrote:
> > > > On Fri, Jan 04, 2019 at 01:22:26AM -0200, Eduardo Habkost wrote:
> > > > > The virtio-pci entries in HW_COMPAT_2_6 had an implicit
> > > > > assumption: that all virtio-pci subclasses support the
> > > > > disable-legacy and disable-modern options.
> > > > >
> > > > > That assumption was broken by commit f6e501a28ef9 ("virtio:
> > > > > Provide version-specific variants of virtio PCI devices"). This
> > > > > caused QEMU to crash if using the new -non-transitional or
> > > > > -transitional device types:
> > > > >
> > > > > $ qemu-system-x86_64 -machine pc-i440fx-2.6 \
> > > > > -device virtio-net-pci-non-transitional
> > > > > Unexpected error in object_property_find() at qom/object.c:1092:
> > > > > qemu-system-x86_64: -device virtio-net-pci-non-transitional: can't
> > > > > apply \
> > > > > global virtio-pci.disable-modern=on: Property '.disable-modern' not
> > > > > found
> > > > > Aborted (core dumped)
> > > > >
> > > > > Replace the virtio-pci.disable-legacy=off and
> > > > > virtio-pci.disable-modern=on entries on HW_COMPAT_2_6 with
> > > > > explicit entries for each generic virtio device type.
> > > > >
> > > > > The full list of generic virtio device types was extracted by
> > > > > just grepping for ".generic_name". Note that we don't need to
> > > > > worry about listing new virtio-pci devices in HW_COMPAT_2_6 in
> > > > > the future, because new devices won't require QEMU 2.6
> > > > > compatibility.
> > > >
> > > > I fully expect that e.g. packed ring support will need
> > > > to affect all virtio devices too. And it's likely
> > > > that we'll have some new virtio-pci transport features too.
> > > >
> > > > > This makes the compat entries annoyingly verbose, but is simpler
> > > > > than the alternative of making the virtio-pci type inheritance
> > > > > rules even more complex.
> > > >
> > > > God forbid we forgot something, the only way to notice is to
> > > > run a cross version migration with an old qemu.
> > > > I think we need to come up with something less verbose and fragile.
> > >
> > > I guess we could use a script like tests/acceptance/virtio_version.py to
> > > do a check?
> >
> > That's a good idea. On test code we can try additional tricks to
> > detect the hybrid virtio devices without increasing the
> > complexity of QEMU code. I'll give it a try.
>
> I did it but I'm not happy with the result: many of the virtio
> devices can't be tested without extra arguments. Some of them
> (like vhost-*) require extra privileges on the host that might be
> unavailable.
>
> Anyway, while writing this I noticed another issue: many of the
> virtio devices in QEMU 2.6 were already modern-only!
>
> Setting disable-modern=off on modern-only devices like virtio-vga
> or virtio-tablet-pci doesn't make sense. This means setting
> virtio-pci.disable-modern=off on HW_COMPAT_2_6 was incorrect even
> before the -non-transitional and -transitional device types were
> introduced.
It did create an opportunity to create non working devices.
Whether that's incorrect as such I'm not sure.
> ---
> diff --git a/tests/acceptance/virtio_version.py
> b/tests/acceptance/virtio_version.py
> index ce990250d8..9157a1b173 100644
> --- a/tests/acceptance/virtio_version.py
> +++ b/tests/acceptance/virtio_version.py
> @@ -55,6 +55,18 @@ def get_pci_interfaces(vm, devtype):
> interfaces = ('pci-express-device', 'conventional-pci-device')
> return [i for i in interfaces if devtype_implements(vm, devtype, i)]
>
> +def is_hybrid_dev(vm, devtype):
> +props = [p['name'] for p in vm.command('device-list-properties',
> + typename=devtype)]
> +return 'disable-legacy' in props
> +
> +def get_all_hybrid_devs(vm):
> +"""Return list of all hybrid virtio device types (the ones that can be
> +configured using the disable-legacy & disable-modern properties)"""
> +alldevs = [d['name'] for d in vm.command('qom-list-types',
> + implements='virtio-pci')]
> +return [d for d in alldevs if is_hybrid_dev(vm, d)]
> +
> class VirtioVersionCheck(Test):
> """
> Check if virtio-version-specific device types result in the
> @@ -174,3 +186,33 @@ class VirtioVersionCheck(Test):
> self.check_modern_only('virtio-mouse-pci', VIRTIO_INPUT)
> self.check_modern_only('virtio-tablet-pci', VIRTIO_INPUT)
> self.check_modern_only('virtio-keyboard-pci', VIRTIO_INPUT)
> +
> +def get_all_hybrid_devs(self):
> +with QEMUMachine(self.qemu_bin) as vm:
> +vm.set_machine('none')
> +vm.add_args('-S')
> +vm.launch()
> +return get_all_hybrid_devs(vm)
>
[Qemu-devel] [Bug 1701835] Re: floating-point operation bugs in qemu-alpha
> You should try building with -mieee. When I build with ../configure CFLAGS="-mieee -O2 -g" CPPFLAGS=-Wall LDFLAGS="-static -lieee" I observe the exact same behaviour: Only 4 tests fail in a VM executed with qemu-system-alpha, whereas the same test failures (from test-cbrt to test-truncf1) are seen with qemu-alpha. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1701835 Title: floating-point operation bugs in qemu-alpha Status in QEMU: New Bug description: When running the gnulib testsuite, I'm seeing test failures in the tests for libm functions cbrt cbrtf ceil ceilf coshf exp2 exp2f floor floorf fma fmaf fmal frexp frexpf hypot hypotf hypotl ilogb ilogbf isfinite isinf isnan isnand isnanf ldexp ldexpf ldexpl log1p log1pf log2 log2f logb logbf logbl rint rintf rintl signbit sqrt sqrtf strtod that I don't see when running the same (statically linked) executables in a VM, through qemu-system-alpha. How to reproduce: - Using gnulib, run ./gnulib-tool --create-testdir --dir=../testdir-math --single-configure cbrt cbrtf ceil ceilf coshf exp2 exp2f float floor floorf fma fmaf fmal frexp frexpf hypot hypotf hypotl ilogb ilogbf isfinite isinf isnan isnand isnanf ldexp ldexpf ldexpl log1p log1pf log2 log2f logb logbf logbl math printf-frexp rint rintf rintl round roundf signbit sqrt sqrtf strtod trunc truncf - Copy the resulting directory to a VM running Linux 2.6.26 with qemu-system-alpha. - There, configure and build the package: mkdir build-native-static; cd build-native-static; ../configure CPPFLAGS="-Wall" LDFLAGS="-static"; make; make check Only 4 tests fail. - Copy the resulting binaries back to the original x86_64 machine. - Set environment variables for using qemu-alpha. - Here, 50 tests fail that did not fail originally: $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-cbrt ../../gltests/test-cbrt.h:39: assertion 'err > - L_(4.0) * L_(16.0) / TWO_MANT_DIG && err < L_(4.0) * L_(16.0) / TWO_MANT_DIG' failed Aborted (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-ceil1 Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-ceil2 Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-ceilf1 Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-ceilf2 Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-coshf ../../gltests/test-coshf.c:37: assertion 'y >= 1.1854652f && y <= 1.1854653f' failed Aborted (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-float Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-floor1 Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-floor2 Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-floorf1 Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-floorf2 Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-fma1 Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-fma2 ../../gltests/test-fma2.h:116: assertion 'result == expected' failed Aborted (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-fmaf1 Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-fmaf2 ../../gltests/test-fma2.h:116: assertion 'result == expected' failed Aborted (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-fmal2 ../../gltests/test-fma2.h:116: assertion 'result == expected' failed Aborted (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-frexp Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-frexpf Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-hypot Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-hypotf Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-hypotl ../../gltests/test-hypot.h:41: assertion 'z == HUGEVAL' failed Aborted (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-ilogb Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-ilogbf Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-isfinite Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-isinf Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-isnan Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-isnand-nolibm Floating point exception (core dumped) $ ~/inst-qemu/2.9.0/bin/qemu-alpha test-isnand Floating point exception (core dumped) $
Re: [Qemu-devel] [Qemu-ppc] [PATCH v2] spapr: return from post_load method when RTC import fails
On Fri, 4 Jan 2019 14:30:50 +0100
Cédric Le Goater wrote:
> The error value can be squashed by the section handling radix migration.
> Simply bail out if an error occurs when the RTC offset is imported.
>
> This fixes the Coverity issue CID 1398591.
>
> Fixes: d39c90f5f3ae ("spapr: Fix migration of Radix guests")
> Signed-off-by: Cédric Le Goater
> ---
>
Reviewed-by: Greg Kurz
> Changes since v1 :
>
> - Added Coverity issue CID
>
> hw/ppc/spapr.c | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index f1725313e979..64397ee91ef0 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -1748,12 +1748,17 @@ static int spapr_post_load(void *opaque, int
> version_id)
> return err;
> }
>
> -/* In earlier versions, there was no separate qdev for the PAPR
> +/*
> + * In earlier versions, there was no separate qdev for the PAPR
> * RTC, so the RTC offset was stored directly in sPAPREnvironment.
> * So when migrating from those versions, poke the incoming offset
> - * value into the RTC device */
> + * value into the RTC device
> + */
> if (version_id < 3) {
> err = spapr_rtc_import_offset(>rtc, spapr->rtc_offset);
> +if (err) {
> +return err;
> +}
> }
>
> if (kvm_enabled() && spapr->patb_entry) {
[Qemu-devel] Why one virtio-pci device has two different DeviceState?
Hi, I was wondering why one virtio-pci device has two different DeviceState? - one directly from VirtIOPCIProxy and the other from VirtIO such as VirtIONet. As an example, they are denoted as qdev and vdev respectively in virtio_net_pci_realize(). I thought that just one DeviceState is enough for any device in QEMU. Maybe I'm missing something fundamental here. *Just* for people who wonder why I'm asking this question, I'd like to find a device in the list of SaveStateEntry on a MMIO operation to a PCI device. For virtio devices, I only have qdev information in the MMIO handler while I need to have vdev information to find the virtio device in the SaveStateEntry list. I can possibly do this by converting qdev to vdev knowing this is a virtio device as in virtio_net_pci_realize(), but I'd like to find a way to do it without knowing the device is a virtio device. Thanks, Jintack
Re: [Qemu-devel] [PATCH v2 3/3] util/cutils: Move function documentations to the header
On 1/4/19 12:12 PM, Philippe Mathieu-Daudé wrote: > Many functions have documentation before the implementation in > cutils.c. Since we expect documentation around the prototype > declaration in headers, move the comments in cutils.h. > > Signed-off-by: Philippe Mathieu-Daudé > --- > include/qemu/cutils.h | 224 ++ > util/cutils.c | 185 -- > 2 files changed, 224 insertions(+), 185 deletions(-) I find documentation in .c files slightly easier to use (you can then read the code right below to see if the documentation is still accurate); but as we had an inconsistent mix, I'm also okay with your patch consolidating all the documentation to one of the two files, rather than the bad mix of half-and-half. -- Eric Blake, Principal Software Engineer Red Hat, Inc. +1-919-301-3226 Virtualization: qemu.org | libvirt.org signature.asc Description: OpenPGP digital signature
Re: [Qemu-devel] [PATCH v2 2/3] util/cutils: Move ctype macros to "cutils.h"
On 1/4/19 12:12 PM, Philippe Mathieu-Daudé wrote: > Introduced in cd390083ad1, these macros don't need to be in > a generic header. > Add documentation to justify their use. > > Reviewed-by: Stefano Garzarella > Signed-off-by: Philippe Mathieu-Daudé > --- > +++ b/include/qemu/cutils.h > @@ -3,6 +3,31 @@ > > #include "qemu/fprintf-fn.h" > > +/** > + * unsigned ctype macros: > + * > + * The standards require that the argument for these functions > + * is either EOF or a value that is representable in the type > + * unsigned char. If the argument is of type char, it must be > + * cast to unsigned char. This is what these macros do, > + * avoiding 'signed to unsigned' conversion warnings. I would also mention that these macros are ONLY intended for use with char arguments (as they CANNOT handle EOF); if you are doing int c = getchar() or similar, you still want to call the original ctype macro. Otherwise, the move and added comments makes sense to me. -- Eric Blake, Principal Software Engineer Red Hat, Inc. +1-919-301-3226 Virtualization: qemu.org | libvirt.org signature.asc Description: OpenPGP digital signature
Re: [Qemu-devel] [PATCH] compat: Use explicit type names on HW_COMPAT_2_6
On Fri, Jan 04, 2019 at 03:54:39PM -0200, Eduardo Habkost wrote:
> On Fri, Jan 04, 2019 at 10:12:00AM +, Dr. David Alan Gilbert wrote:
> > * Michael S. Tsirkin (m...@redhat.com) wrote:
> > > On Fri, Jan 04, 2019 at 01:22:26AM -0200, Eduardo Habkost wrote:
> > > > The virtio-pci entries in HW_COMPAT_2_6 had an implicit
> > > > assumption: that all virtio-pci subclasses support the
> > > > disable-legacy and disable-modern options.
> > > >
> > > > That assumption was broken by commit f6e501a28ef9 ("virtio:
> > > > Provide version-specific variants of virtio PCI devices"). This
> > > > caused QEMU to crash if using the new -non-transitional or
> > > > -transitional device types:
> > > >
> > > > $ qemu-system-x86_64 -machine pc-i440fx-2.6 \
> > > > -device virtio-net-pci-non-transitional
> > > > Unexpected error in object_property_find() at qom/object.c:1092:
> > > > qemu-system-x86_64: -device virtio-net-pci-non-transitional: can't
> > > > apply \
> > > > global virtio-pci.disable-modern=on: Property '.disable-modern' not
> > > > found
> > > > Aborted (core dumped)
> > > >
> > > > Replace the virtio-pci.disable-legacy=off and
> > > > virtio-pci.disable-modern=on entries on HW_COMPAT_2_6 with
> > > > explicit entries for each generic virtio device type.
> > > >
> > > > The full list of generic virtio device types was extracted by
> > > > just grepping for ".generic_name". Note that we don't need to
> > > > worry about listing new virtio-pci devices in HW_COMPAT_2_6 in
> > > > the future, because new devices won't require QEMU 2.6
> > > > compatibility.
> > >
> > > I fully expect that e.g. packed ring support will need
> > > to affect all virtio devices too. And it's likely
> > > that we'll have some new virtio-pci transport features too.
> > >
> > > > This makes the compat entries annoyingly verbose, but is simpler
> > > > than the alternative of making the virtio-pci type inheritance
> > > > rules even more complex.
> > >
> > > God forbid we forgot something, the only way to notice is to
> > > run a cross version migration with an old qemu.
> > > I think we need to come up with something less verbose and fragile.
> >
> > I guess we could use a script like tests/acceptance/virtio_version.py to
> > do a check?
>
> That's a good idea. On test code we can try additional tricks to
> detect the hybrid virtio devices without increasing the
> complexity of QEMU code. I'll give it a try.
I did it but I'm not happy with the result: many of the virtio
devices can't be tested without extra arguments. Some of them
(like vhost-*) require extra privileges on the host that might be
unavailable.
Anyway, while writing this I noticed another issue: many of the
virtio devices in QEMU 2.6 were already modern-only!
Setting disable-modern=off on modern-only devices like virtio-vga
or virtio-tablet-pci doesn't make sense. This means setting
virtio-pci.disable-modern=off on HW_COMPAT_2_6 was incorrect even
before the -non-transitional and -transitional device types were
introduced.
---
diff --git a/tests/acceptance/virtio_version.py
b/tests/acceptance/virtio_version.py
index ce990250d8..9157a1b173 100644
--- a/tests/acceptance/virtio_version.py
+++ b/tests/acceptance/virtio_version.py
@@ -55,6 +55,18 @@ def get_pci_interfaces(vm, devtype):
interfaces = ('pci-express-device', 'conventional-pci-device')
return [i for i in interfaces if devtype_implements(vm, devtype, i)]
+def is_hybrid_dev(vm, devtype):
+props = [p['name'] for p in vm.command('device-list-properties',
+ typename=devtype)]
+return 'disable-legacy' in props
+
+def get_all_hybrid_devs(vm):
+"""Return list of all hybrid virtio device types (the ones that can be
+configured using the disable-legacy & disable-modern properties)"""
+alldevs = [d['name'] for d in vm.command('qom-list-types',
+ implements='virtio-pci')]
+return [d for d in alldevs if is_hybrid_dev(vm, d)]
+
class VirtioVersionCheck(Test):
"""
Check if virtio-version-specific device types result in the
@@ -174,3 +186,33 @@ class VirtioVersionCheck(Test):
self.check_modern_only('virtio-mouse-pci', VIRTIO_INPUT)
self.check_modern_only('virtio-tablet-pci', VIRTIO_INPUT)
self.check_modern_only('virtio-keyboard-pci', VIRTIO_INPUT)
+
+def get_all_hybrid_devs(self):
+with QEMUMachine(self.qemu_bin) as vm:
+vm.set_machine('none')
+vm.add_args('-S')
+vm.launch()
+return get_all_hybrid_devs(vm)
+
+def check_legacy_compat(self, qemu_devtype):
+# these device types can't be run with extra arguments, so we can't
+# test them directly:
+if qemu_devtype in ('virtio-input-host-pci', 'virtio-blk-pci',
+'virtio-crypto-pci', 'virtio-9p-pci',
+'vhost-vsock-pci', 'vhost-scsi-pci',
+
[Qemu-devel] [PATCH 2/3] target/ppc: Add GDB callbacks for SPRs
These will be used to let GDB know about PPC's Special Purpose
Registers (SPR).
They take an index based on the order the registers appear in the XML
file sent by QEMU to GDB. This index does not match the actual
location of the registers in the env->spr array so the
gdb_find_spr_idx function does that conversion.
Signed-off-by: Fabiano Rosas
---
target/ppc/translate_init.inc.c | 50 +
1 file changed, 50 insertions(+)
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 03f1d34a97..f10a3637d9 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -9483,6 +9483,56 @@ static bool avr_need_swap(CPUPPCState *env)
#endif
}
+#if !defined(CONFIG_USER_ONLY)
+static int gdb_find_spr_idx(CPUPPCState *env, int n)
+{
+int idx = -1;
+int i;
+
+for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
+ppc_spr_t *spr = >spr_cb[i];
+
+if (spr->name && ++idx == n) {
+break;
+}
+}
+return i;
+}
+
+static int gdb_get_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
+{
+int reg;
+int len;
+
+reg = gdb_find_spr_idx(env, n);
+if (!reg) {
+return 0;
+}
+
+len = TARGET_LONG_SIZE;
+stn_p(mem_buf, len, env->spr[reg]);
+ppc_maybe_bswap_register(env, mem_buf, len);
+return len;
+}
+
+static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
+{
+int reg;
+int len;
+
+reg = gdb_find_spr_idx(env, n);
+if (!reg) {
+return 0;
+}
+
+len = TARGET_LONG_SIZE;
+ppc_maybe_bswap_register(env, mem_buf, len);
+env->spr[reg] = ldn_p(mem_buf, len);
+
+return len;
+}
+#endif
+
static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
--
2.17.1
Re: [Qemu-devel] [RFC PATCH 23/25] x86_64-softmmu.mak: remove i386-softmmu.mak include
On 2018-12-27 07:34, Yang Zhong wrote: > Only keep same boards definitions as i386-softmmu.mak in > x86_64-softmmu.mak. > > Signed-off-by: Yang Zhong > --- > default-configs/x86_64-softmmu.mak | 6 +- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/default-configs/x86_64-softmmu.mak > b/default-configs/x86_64-softmmu.mak > index 64b2ee2960..0c69c2930c 100644 > --- a/default-configs/x86_64-softmmu.mak > +++ b/default-configs/x86_64-softmmu.mak > @@ -1,3 +1,7 @@ > # Default configuration for x86_64-softmmu > > -include i386-softmmu.mak > +# Boards: > +# > +CONFIG_ISAPC=y > +CONFIG_I440FX=y > +CONFIG_Q35=y Not sure whether this patch is really necessary since the two configs are currently really the same. Anyway, in case you want to keep the patch: Reviewed-by: Thomas Huth
[Qemu-devel] [PATCH 0/3] ppc/gdbstub: Expose SPRs to GDB
This series implements the reading and writing of Special Purpose
Registers in PPC's gdbstub.
* How it works generally [1]:
GDB asks for the target.xml file which contains the target description
along with the list of available feature XMLs. GDB then asks for each
of the XML files in sequence.
The XML files contain a list of registers descriptions:
When the user tries to access a register, GDB looks for the register
name in the XML file and sends QEMU the index of the register. This
index is sequential across all feature files.
The index provided by GDB must be converted by QEMU to match QEMU's
internal representation.
A set of callbacks are implemented to read/write the register.
* In this series:
The first patch implements the dynamic generation of the power-spr.xml
file. Making it dynamically facilitates converting the GDB index to an
index useful for addressing the env->spr array.
The second patch implements the gdb_{get,set}_spr_reg callbacks along
with the convertion from GDB index to QEMU index.
The third patch enables the functionality.
1- https://sourceware.org/gdb/current/onlinedocs/gdb/Target-Descriptions.html
Fabiano Rosas (3):
target/ppc: Add SPRs XML generation code for gdbstub
target/ppc: Add GDB callbacks for SPRs
target/ppc: Enable reporting of SPRs to GDB
target/ppc/cpu.h| 7
target/ppc/gdbstub.c| 45 +
target/ppc/translate_init.inc.c | 59 +++--
3 files changed, 109 insertions(+), 2 deletions(-)
--
2.17.1
[Qemu-devel] [PATCH 3/3] target/ppc: Enable reporting of SPRs to GDB
This allows reading and writing of SPRs via GDB: (gdb) p/x $srr1 $1 = 0x82803033 (gdb) p/x $pvr $2 = 0x4b0201 (gdb) set $pvr=0x4b (gdb) p/x $pvr $3 = 0x4b They can also be shown as a group: (gdb) info reg spr Signed-off-by: Fabiano Rosas --- target/ppc/translate_init.inc.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index f10a3637d9..5771ef5386 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -9760,7 +9760,10 @@ static void ppc_cpu_realize(DeviceState *dev, Error **errp) gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg, 32, "power-vsx.xml", 0); } - +#ifndef CONFIG_USER_ONLY +gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg, + ppc_gdb_gen_spr_xml(cs), "power-spr.xml", 0); +#endif qemu_init_vcpu(cs); pcc->parent_realize(dev, errp); @@ -10523,7 +10526,9 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) #endif cc->gdb_num_core_regs = 71; - +#ifndef CONFIG_USER_ONLY +cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; +#endif #ifdef USE_APPLE_GDB cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; -- 2.17.1
[Qemu-devel] [PATCH 1/3] target/ppc: Add SPRs XML generation code for gdbstub
A following patch will add support for handling the Special Purpose
Registers (SPR) in GDB via gdbstub. For that purpose, GDB needs to be
provided with an XML description of the registers (see gdb-xml
directory).
This patch adds the code that generates the XML dynamically based on
the SPRs already defined in the machine. This eliminates the need for
several XML files to match each possible ppc machine.
A "group" is defined so that the GDB command `info registers spr` can
be used.
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu.h | 7 +++
target/ppc/gdbstub.c | 45
2 files changed, 52 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index d5f99f1fc7..365bca2248 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1052,6 +1052,9 @@ struct CPUPPCState {
/* Special purpose registers */
target_ulong spr[1024];
ppc_spr_t spr_cb[1024];
+#if !defined(CONFIG_USER_ONLY)
+const char *gdb_spr_xml;
+#endif
/* Altivec registers */
ppc_avr_t avr[32];
uint32_t vscr;
@@ -1264,6 +1267,10 @@ int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t
*buf, int reg);
int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
+#ifndef CONFIG_USER_ONLY
+int ppc_gdb_gen_spr_xml(CPUState *cpu);
+const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name);
+#endif
int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, void *opaque);
int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c
index b6f6693583..82db500457 100644
--- a/target/ppc/gdbstub.c
+++ b/target/ppc/gdbstub.c
@@ -319,3 +319,48 @@ int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t
*mem_buf, int n)
}
return r;
}
+
+#ifndef CONFIG_USER_ONLY
+int ppc_gdb_gen_spr_xml(CPUState *cs)
+{
+PowerPCCPU *cpu = POWERPC_CPU(cs);
+CPUPPCState *env = >env;
+GString *s = g_string_new(NULL);
+int num_regs = 0;
+int i;
+
+g_string_printf(s, "");
+g_string_append_printf(s, "");
+g_string_append_printf(s, "");
+
+for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
+ppc_spr_t *spr = >spr_cb[i];
+
+if (!spr->name) {
+continue;
+}
+
+g_string_append_printf(s, "name, -1));
+g_string_append_printf(s, " bitsize=\"%d\"", TARGET_LONG_BITS);
+g_string_append_printf(s, " group=\"spr\"/>");
+
+num_regs++;
+}
+
+g_string_append_printf(s, "");
+env->gdb_spr_xml = g_string_free(s, false);
+return num_regs;
+}
+
+const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name)
+{
+PowerPCCPU *cpu = POWERPC_CPU(cs);
+CPUPPCState *env = >env;
+
+if (strcmp(xml_name, "power-spr.xml") == 0) {
+return env->gdb_spr_xml;
+}
+return NULL;
+}
+#endif
--
2.17.1
Re: [Qemu-devel] [PATCH] tests/hexloader-test: Don't pass -nographic to the QEMU under test
On 04/01/19 15:50, Peter Maydell wrote:
> The hexloader test invokes QEMU with the -nographic argument. This
> is unnecessary, because the qtest_initf() function will pass it
> -display none, which suffices to disable the graphical window.
> It also means that the QEMU process will make the stdin/stdout
> O_NONBLOCK. Since O_NONBLOCK is not per-file descriptor but per
> "file description", this non-blocking behaviour is then shared
> with any other process that's using the stdin/stdout of the
> 'make check' run, including make itself. This can result in make
> falling over with "make: write error: stdout" because it got
> an unexpected EINTR trying to write output messages to the terminal.
> This is particularly noticable if running 'make check' in a loop with
> while make check; do true; done
> (It does not affect single make check runs so much because the
> shell will remove the O_NONBLOCK status before it reads the
> terminal for interactive input.)
>
> Remove the unwanted -nographic argument.
>
> Signed-off-by: Peter Maydell
> ---
> This seems to be sufficient to resolve my "make falls over"
> issues with the current test harness and a build done for
> arm targets; I haven't checked whether other test cases which
> are specific to other target architectures might have similar
> accidental O_NONBLOCK behaviour.
>
> tests/hexloader-test.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tests/hexloader-test.c b/tests/hexloader-test.c
> index 834ed52c22b..8b7aa2d72d0 100644
> --- a/tests/hexloader-test.c
> +++ b/tests/hexloader-test.c
> @@ -23,7 +23,7 @@ static void hex_loader_test(void)
> const unsigned int base_addr = 0x0001;
>
> QTestState *s = qtest_initf(
> -"-M vexpress-a9 -nographic -device
> loader,file=tests/data/hex-loader/test.hex");
> +"-M vexpress-a9 -device loader,file=tests/data/hex-loader/test.hex");
>
> for (i = 0; i < 256; ++i) {
> uint8_t val = qtest_readb(s, base_addr + i);
>
Great, I'll put it in my pull request together with the TAP driver
(however, I'll also put in the
Re: [Qemu-devel] [RFC PATCH 21/25] virtio: make virtio dependencies with Kconfig
On 2018-12-27 07:34, Yang Zhong wrote: > Signed-off-by: Yang Zhong > --- > default-configs/i386-softmmu.mak | 1 - > hw/9pfs/Kconfig | 2 ++ > hw/block/Kconfig | 2 ++ > hw/char/Kconfig | 2 ++ > hw/display/Kconfig | 5 + > hw/input/Kconfig | 2 ++ > hw/net/Kconfig | 2 ++ > hw/pci-host/Kconfig | 2 ++ > hw/virtio/Kconfig| 10 +- > 9 files changed, 26 insertions(+), 2 deletions(-) Shouldn't this patch also get rid of default-configs/virtio.mak ? [...] > diff --git a/hw/virtio/Kconfig b/hw/virtio/Kconfig > index aabd6d4d96..9127daed5e 100644 > --- a/hw/virtio/Kconfig > +++ b/hw/virtio/Kconfig > @@ -3,18 +3,26 @@ config VIRTIO > > config VIRTIO_RNG > bool > +default y > +depends on VIRTIO > > config VIRTIO_PCI > bool > default y > depends on PCI > -select VIRTIO > +depends on VIRTIO > > config VIRTIO_MMIO > bool > +default y > +depends on VIRTIO I don't think we should enable VIRTIO_MMIO by default - it's only used on arm and riscv, but not on x86 and the other architectures. > config VIRTIO_BALLOON > bool > +default y > +depends on VIRTIO > > config VIRTIO_CRYPTO > bool > +default y > +depends on VIRTIO > Thomas
Re: [Qemu-devel] [RFC PATCH 20/25] hyperv: express dependencies with kconfig
On 04/01/19 16:38, Thomas Huth wrote: > On 2018-12-27 07:34, Yang Zhong wrote: >> remove default-configs/hyperv.mak and make dependencies >> with Kconfig. >> >> Signed-off-by: Yang Zhong >> --- >> default-configs/hyperv.mak | 2 -- >> default-configs/i386-softmmu.mak | 1 - >> hw/hyperv/Kconfig| 1 + >> hw/i386/Kconfig | 2 ++ >> 4 files changed, 3 insertions(+), 3 deletions(-) >> delete mode 100644 default-configs/hyperv.mak >> >> diff --git a/default-configs/hyperv.mak b/default-configs/hyperv.mak >> deleted file mode 100644 >> index 5d0d9fd830..00 >> --- a/default-configs/hyperv.mak >> +++ /dev/null >> @@ -1,2 +0,0 @@ >> -CONFIG_HYPERV=$(CONFIG_KVM) >> -CONFIG_HYPERV_TESTDEV=y >> diff --git a/default-configs/i386-softmmu.mak >> b/default-configs/i386-softmmu.mak >> index d2e58edd17..eb2d22de3c 100644 >> --- a/default-configs/i386-softmmu.mak >> +++ b/default-configs/i386-softmmu.mak >> @@ -1,6 +1,5 @@ >> # Default configuration for i386-softmmu >> >> -include hyperv.mak >> CONFIG_VMXNET3_PCI=y >> CONFIG_VIRTIO_VGA=y >> CONFIG_IPMI=y >> diff --git a/hw/hyperv/Kconfig b/hw/hyperv/Kconfig >> index be724b7f8b..632c3a675b 100644 >> --- a/hw/hyperv/Kconfig >> +++ b/hw/hyperv/Kconfig >> @@ -1,5 +1,6 @@ >> config HYPERV >> bool >> +depends on KVM >> >> config HYPERV_TESTDEV >> bool > > Should HYPERV_TESTDEV maybe get a "depends on HYPERV", too? Yes, and also a "default y if PC". That makes the "select HYPERV_TESTDEV" unnecessary below. Paolo >> diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig >> index 695a67f88d..af4b81bae1 100644 >> --- a/hw/i386/Kconfig >> +++ b/hw/i386/Kconfig >> @@ -11,6 +11,8 @@ config PC >> select I8257 >> select MC146818RTC >> select TPM_TIS if TPM >> +select HYPERV >> +select HYPERV_TESTDEV >> >> config PC_PCI >> bool >> > > Reviewed-by: Thomas Huth >
Re: [Qemu-devel] [PATCH] hw/char/stm32f2xx_usart: Do not update data register when device is disabled
On Fri, Jan 4, 2019 at 10:31 AM Philippe Mathieu-Daudé
wrote:
>
> On 1/4/19 7:20 PM, Philippe Mathieu-Daudé wrote:
> > When the device is disable, the internal circuitry keep the data
>
> "keep" -> "keeps"
>
> > register loaded and doesn't update it.
> >
> > Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> > ---
> > hw/char/stm32f2xx_usart.c | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c
> > index f3363a2952..10392c70e2 100644
> > --- a/hw/char/stm32f2xx_usart.c
> > +++ b/hw/char/stm32f2xx_usart.c
> > @@ -53,14 +53,13 @@ static void stm32f2xx_usart_receive(void *opaque, const
> > uint8_t *buf, int size)
> > {
> > STM32F2XXUsartState *s = opaque;
> >
> > -s->usart_dr = *buf;
> > -
> > if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {
> > /* USART not enabled - drop the chars */
> > DB_PRINT("Dropping the chars\n");
> > return;
> > }
> >
> > +s->usart_dr = *buf;
> > s->usart_sr |= USART_SR_RXNE;
> >
> > if (s->usart_cr1 & USART_CR1_RXNEIE) {
> >
>
Re: [Qemu-devel] [PATCH v2 1/3] util/cutils: Move size_to_str() from "qemu-common.h" to "cutils.h"
On 1/4/19 12:12 PM, Philippe Mathieu-Daudé wrote: > The size_to_str() function doesn't need to be in a generic header. > > It makes also sens to find this function in the same header than s/sens/sense/ s/than/as/ > the opposite string to size functions: qemu_strtosz*(). > Note than this function is already implemented in util/cutils.c. s/than/that/ > > Since we introduce a new function in a header, we document it, > using the previous comment from the source file. > > Signed-off-by: Philippe Mathieu-Daudé > --- Reviewed-by: Eric Blake -- Eric Blake, Principal Software Engineer Red Hat, Inc. +1-919-301-3226 Virtualization: qemu.org | libvirt.org signature.asc Description: OpenPGP digital signature
Re: [Qemu-devel] [PATCH 01/16] hw/arm/aspeed: Use TYPE_TMP105/TYPE_PCA9552 instead of hardcoded string
On 2019-01-04 18:58, Philippe Mathieu-Daudé wrote: > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/arm/aspeed.c | 13 + > 1 file changed, 9 insertions(+), 4 deletions(-) > > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > index 5158985482..817f9e1400 100644 > --- a/hw/arm/aspeed.c > +++ b/hw/arm/aspeed.c > @@ -19,6 +19,8 @@ > #include "hw/arm/aspeed_soc.h" > #include "hw/boards.h" > #include "hw/i2c/smbus.h" > +#include "hw/misc/pca9552.h" > +#include "hw/misc/tmp105.h" > #include "qemu/log.h" > #include "sysemu/block-backend.h" > #include "hw/loader.h" > @@ -267,7 +269,8 @@ static void ast2500_evb_i2c_init(AspeedBoardState *bmc) >eeprom_buf); > > /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ > -i2c_create_slave(aspeed_i2c_get_bus(DEVICE(>i2c), 7), "tmp105", > 0x4d); > +i2c_create_slave(aspeed_i2c_get_bus(DEVICE(>i2c), 7), TYPE_TMP105, > + 0x4d); > > /* The AST2500 EVB does not have an RTC. Let's pretend that one is > * plugged on the I2C bus header */ > @@ -288,13 +291,15 @@ static void witherspoon_bmc_i2c_init(AspeedBoardState > *bmc) > AspeedSoCState *soc = >soc; > uint8_t *eeprom_buf = g_malloc0(8 * 1024); > > -i2c_create_slave(aspeed_i2c_get_bus(DEVICE(>i2c), 3), "pca9552", > 0x60); > +i2c_create_slave(aspeed_i2c_get_bus(DEVICE(>i2c), 3), TYPE_PCA9552, > + 0x60); > > i2c_create_slave(aspeed_i2c_get_bus(DEVICE(>i2c), 4), "tmp423", > 0x4c); > i2c_create_slave(aspeed_i2c_get_bus(DEVICE(>i2c), 5), "tmp423", > 0x4c); > > /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ > -i2c_create_slave(aspeed_i2c_get_bus(DEVICE(>i2c), 9), "tmp105", > 0x4a); > +i2c_create_slave(aspeed_i2c_get_bus(DEVICE(>i2c), 9), TYPE_TMP105, > + 0x4a); > > /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is > * good enough */ > @@ -302,7 +307,7 @@ static void witherspoon_bmc_i2c_init(AspeedBoardState > *bmc) > > smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(>i2c), 11), 0x51, >eeprom_buf); > -i2c_create_slave(aspeed_i2c_get_bus(DEVICE(>i2c), 11), "pca9552", > +i2c_create_slave(aspeed_i2c_get_bus(DEVICE(>i2c), 11), TYPE_PCA9552, > 0x60); > } > > Reviewed-by: Thomas Huth
Re: [Qemu-devel] [PATCH 16/16] RFC hw/net/smc91c111: Convert init helper into an inline function
On 2019-01-04 18:58, Philippe Mathieu-Daudé wrote: > Signed-off-by: Philippe Mathieu-Daudé > --- > As init helper in "hw/char/pl011.h" > --- > hw/net/smc91c111.c | 17 - > include/hw/net/smc91c111.h | 25 - > 2 files changed, 24 insertions(+), 18 deletions(-) Why? If you move code around like this, you should mention the reason in the patch description. Thomas
[Qemu-devel] [Bug 1810545] Re: [alpha] Strange exception address reported
Hmm, qemu-system-alpha ? The guest kernel should be doing the same thing
it would on real hardware -- I guess we're getting the value of the
exception address wrong when we deliver the exception to it.
--
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https://bugs.launchpad.net/bugs/1810545
Title:
[alpha] Strange exception address reported
Status in QEMU:
New
Bug description:
For some reason the SIGILL handler receives a different address under
qemu than it used to on real hardware. I don't know specifics about
the hardware used back then – it was some sort of 21264a somewhere
between 600-800 MHz –, and I cannot say anything about the kernel as
well, but I know that it delivered the faulting address +4, while
under qemu it receives +8. I know because CACAO, an early Java JIT
compiler extracts the address from the SIGILL handler and inspects the
code at the faulting site, and it has substracted 4 from the handler
address since the dawn of time, and this used to produce the desired
result on the Alpha hardware. It actually ran on two different Alpha
machines over the years, and both behaved identically.
The handler looks like this:
void handler_sigill(int sig, siginfo_t *siginfo, void *_p)
{
uintptr_t trap_address = (uintptr_t) (((ucontext_t*)
_p)->uc_mcontext.sc_pc) - 4;
}
(paraphrasing, the actual code is here: https://bitbucket.org/cacaovm
/cacao-
staging/src/c8d3fbab864c3243f97629fcfa8d84ba71f38157/src/vm/jit/alpha/linux
/md-os.cpp?at=default=file-view-default#md-os.cpp-65)
I don't know much about the qemu source code and cannot say where this
is coming from at first glance. The gen_invalid function uses pc_next,
which sounds like the next instruction, not the next-to-next ;). In
theory it could actually be the kernel's fault, although I consider
this unlikely.
This is qemu-system-alpha with apparently the last Debian which
existed for Alpha (lenny). The kernel is 2.6.26-2-alpha-generic
(Debian 2.6.26-29). Observed with qemu git 1b3e80082b, but I guess it
is the same with any version.
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1810545/+subscriptions
Re: [Qemu-devel] [PULL 0/4] fw_cfg 20190104 patches
On Fri, 4 Jan 2019 at 16:32, Philippe Mathieu-Daudé wrote: > > Hi Peter, > > The following changes since commit 6395fe0c2c7d9f336d87960a7c9924b630c57c91: > > Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' > into staging (2019-01-04 13:22:51 +) > > are available in the Git repository at: > > https://github.com/philmd/qemu.git tags/fw_cfg-20190104-pull-request > > for you to fetch changes up to 19bcc4bc3213e78c303ad480a7a578f62258252d: > > fw_cfg: Make qemu_extra_params_fw locally (2019-01-04 15:30:52 +0100) > > > > fw_cfg patches for 2019-01-04 > > Two fixes from Li Qiang: > - Improve error message when can't load splash file > - Fix boot bootsplash and reboot-timeout error checking > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/4.0 for any user-visible changes. -- PMM
Re: [Qemu-devel] [PATCH v2 16/27] target/arm: Introduce arm_stage1_mmu_idx
On Fri, 14 Dec 2018 at 05:24, Richard Henderson wrote: > > While we could expose stage_1_mmu_idx, the combination is > probably going to be more useful. > > Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell thanks -- PMM
Re: [Qemu-devel] [PATCH v2 13/27] target/arm: Decode Load/store register (pac)
On Fri, 14 Dec 2018 at 05:24, Richard Henderson
wrote:
>
> Not that there are any stores involved, but why argue with ARM's
> naming convention.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/translate-a64.c | 62 ++
> 1 file changed, 62 insertions(+)
>
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index e62d248894..c57c89d98a 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -3146,6 +3146,65 @@ static void disas_ldst_atomic(DisasContext *s,
> uint32_t insn,
> s->be_data | size | MO_ALIGN);
> }
>
> +/* PAC memory operations
> + *
> + * 31 30 27 262422 21 12 11 105 0
> + * +--+---+---+-+-+---++---+---++-+
> + * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
> + * +--+---+---+-+-++---+---++-+
> + *
> + * Rt: the result register
> + * Rn: base address or SP
> + * Rs: the source register for the operation
> + * V: vector flag (always 0 as of v8.3)
> + * M: clear for key DA, set for key DB
> + * W: pre-indexing flag
> + * S: sign for imm9.
> + */
> +static void disas_ldst_pac(DisasContext *s, uint32_t insn,
> + int size, int rt, bool is_vector)
> +{
> +int rn = extract32(insn, 5, 5);
> +bool is_wback = extract32(insn, 11, 1);
> +bool use_key_a = !extract32(insn, 23, 1);
> +int offset, memidx;
> +TCGv_i64 tcg_addr, tcg_rt;
> +
> +if (size != 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) {
> +unallocated_encoding(s);
> +return;
> +}
> +
> +if (rn == 31) {
> +gen_check_sp_alignment(s);
> +}
> +tcg_addr = read_cpu_reg_sp(s, rn, 1);
> +
> +if (s->pauth_active) {
> +if (use_key_a) {
> +gen_helper_autda(tcg_addr, cpu_env, tcg_addr, cpu_X[31]);
> +} else {
> +gen_helper_autdb(tcg_addr, cpu_env, tcg_addr, cpu_X[31]);
> +}
> +}
> +
> +/* Form the 10-bit signed, scaled offset. */
> +offset = (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9);
> +offset = sextract32(offset << size, 10 + size, 0);
> +tcg_gen_addi_i64(tcg_addr, tcg_addr, offset);
> +
> +tcg_rt = cpu_reg(s, rt);
> +memidx = get_mem_index(s);
> +do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size,
> + /* is_signed */ false, /* extend */ false, memidx,
> + /* iss_valid */ true, /* iss_srt */ rt,
> + /* iss_sf */ true, /* iss_ar */ false);
Since you don't have the "memidx might be something other than
the result of get_mem_index()" case to worry about, you could
use do_gpr_ld() here.
ISS information is not valid for accesses which do writeback.
(We seem to get this wrong in the existing disas_ldst_reg_imm9()...)
> +
> +if (is_wback) {
> +tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr);
> +}
> +}
> +
> /* Load/store register (all forms) */
> static void disas_ldst_reg(DisasContext *s, uint32_t insn)
> {
> @@ -3171,6 +3230,9 @@ static void disas_ldst_reg(DisasContext *s, uint32_t
> insn)
> case 2:
> disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector);
> return;
> +default:
> +disas_ldst_pac(s, insn, size, rt, is_vector);
> +return;
> }
> break;
> case 1:
> --
> 2.17.2
>
thanks
-- PMM
Re: [Qemu-devel] [PATCH] hw/char/stm32f2xx_usart: Do not update data register when device is disabled
On 1/4/19 7:20 PM, Philippe Mathieu-Daudé wrote:
> When the device is disable, the internal circuitry keep the data
"keep" -> "keeps"
> register loaded and doesn't update it.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/char/stm32f2xx_usart.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c
> index f3363a2952..10392c70e2 100644
> --- a/hw/char/stm32f2xx_usart.c
> +++ b/hw/char/stm32f2xx_usart.c
> @@ -53,14 +53,13 @@ static void stm32f2xx_usart_receive(void *opaque, const
> uint8_t *buf, int size)
> {
> STM32F2XXUsartState *s = opaque;
>
> -s->usart_dr = *buf;
> -
> if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {
> /* USART not enabled - drop the chars */
> DB_PRINT("Dropping the chars\n");
> return;
> }
>
> +s->usart_dr = *buf;
> s->usart_sr |= USART_SR_RXNE;
>
> if (s->usart_cr1 & USART_CR1_RXNEIE) {
>
[Qemu-devel] [Bug 1810545] [NEW] [alpha] Strange exception address reported
Public bug reported:
For some reason the SIGILL handler receives a different address under
qemu than it used to on real hardware. I don't know specifics about the
hardware used back then – it was some sort of 21264a somewhere between
600-800 MHz –, and I cannot say anything about the kernel as well, but I
know that it delivered the faulting address +4, while under qemu it
receives +8. I know because CACAO, an early Java JIT compiler extracts
the address from the SIGILL handler and inspects the code at the
faulting site, and it has substracted 4 from the handler address since
the dawn of time, and this used to produce the desired result on the
Alpha hardware. It actually ran on two different Alpha machines over the
years, and both behaved identically.
The handler looks like this:
void handler_sigill(int sig, siginfo_t *siginfo, void *_p)
{
uintptr_t trap_address = (uintptr_t) (((ucontext_t*) _p)->uc_mcontext.sc_pc)
- 4;
}
(paraphrasing, the actual code is here: https://bitbucket.org/cacaovm
/cacao-
staging/src/c8d3fbab864c3243f97629fcfa8d84ba71f38157/src/vm/jit/alpha/linux
/md-os.cpp?at=default=file-view-default#md-os.cpp-65)
I don't know much about the qemu source code and cannot say where this
is coming from at first glance. The gen_invalid function uses pc_next,
which sounds like the next instruction, not the next-to-next ;). In
theory it could actually be the kernel's fault, although I consider this
unlikely.
This is qemu-system-alpha with apparently the last Debian which existed
for Alpha (lenny). The kernel is 2.6.26-2-alpha-generic (Debian
2.6.26-29). Observed with qemu git 1b3e80082b, but I guess it is the
same with any version.
** Affects: qemu
Importance: Undecided
Status: New
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1810545
Title:
[alpha] Strange exception address reported
Status in QEMU:
New
Bug description:
For some reason the SIGILL handler receives a different address under
qemu than it used to on real hardware. I don't know specifics about
the hardware used back then – it was some sort of 21264a somewhere
between 600-800 MHz –, and I cannot say anything about the kernel as
well, but I know that it delivered the faulting address +4, while
under qemu it receives +8. I know because CACAO, an early Java JIT
compiler extracts the address from the SIGILL handler and inspects the
code at the faulting site, and it has substracted 4 from the handler
address since the dawn of time, and this used to produce the desired
result on the Alpha hardware. It actually ran on two different Alpha
machines over the years, and both behaved identically.
The handler looks like this:
void handler_sigill(int sig, siginfo_t *siginfo, void *_p)
{
uintptr_t trap_address = (uintptr_t) (((ucontext_t*)
_p)->uc_mcontext.sc_pc) - 4;
}
(paraphrasing, the actual code is here: https://bitbucket.org/cacaovm
/cacao-
staging/src/c8d3fbab864c3243f97629fcfa8d84ba71f38157/src/vm/jit/alpha/linux
/md-os.cpp?at=default=file-view-default#md-os.cpp-65)
I don't know much about the qemu source code and cannot say where this
is coming from at first glance. The gen_invalid function uses pc_next,
which sounds like the next instruction, not the next-to-next ;). In
theory it could actually be the kernel's fault, although I consider
this unlikely.
This is qemu-system-alpha with apparently the last Debian which
existed for Alpha (lenny). The kernel is 2.6.26-2-alpha-generic
(Debian 2.6.26-29). Observed with qemu git 1b3e80082b, but I guess it
is the same with any version.
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1810545/+subscriptions
Re: [Qemu-devel] [PULL v3 00/44] MIPS pull request for December 2018 - v3
On Fri, 4 Jan 2019 at 17:41, Aleksandar Markovic wrote: > > > Applied, thanks. > > > > Please update the changelog at https://wiki.qemu.org/ChangeLog/4.0 > > for any user-visible changes. > > I updated the change log with a single item, as I mentioned in the pull > request cover letter: > > https://wiki.qemu.org/ChangeLog/4.0#MIPS That's fine, thanks. My 'applied this' emails for pull requests are standard templates, so they'll always ask for changelog updates even when that isn't necessarily applicable to a particular pull. It's just intended as a reminder that we're trying to do updates of the changelog as we go along this release cycle. -- PMM
[Qemu-devel] [PATCH v2 1/3] util/cutils: Move size_to_str() from "qemu-common.h" to "cutils.h"
The size_to_str() function doesn't need to be in a generic header.
It makes also sens to find this function in the same header than
the opposite string to size functions: qemu_strtosz*().
Note than this function is already implemented in util/cutils.c.
Since we introduce a new function in a header, we document it,
using the previous comment from the source file.
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu-common.h| 1 -
include/qemu/cutils.h| 13 +
qapi/string-output-visitor.c | 2 +-
util/cutils.c| 6 --
4 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/include/qemu-common.h b/include/qemu-common.h
index ed60ba251d..760527294f 100644
--- a/include/qemu-common.h
+++ b/include/qemu-common.h
@@ -153,7 +153,6 @@ void qemu_hexdump(const char *buf, FILE *fp, const char
*prefix, size_t size);
int parse_debug_env(const char *name, int max, int initial);
const char *qemu_ether_ntoa(const MACAddr *mac);
-char *size_to_str(uint64_t val);
void page_size_init(void);
/* returns non-zero if dump is in progress, otherwise zero is
diff --git a/include/qemu/cutils.h b/include/qemu/cutils.h
index d2dad3057c..9ee40470e3 100644
--- a/include/qemu/cutils.h
+++ b/include/qemu/cutils.h
@@ -157,6 +157,19 @@ int qemu_strtosz(const char *nptr, const char **end,
uint64_t *result);
int qemu_strtosz_MiB(const char *nptr, const char **end, uint64_t *result);
int qemu_strtosz_metric(const char *nptr, const char **end, uint64_t *result);
+/**
+ * size_to_str:
+ *
+ * Return human readable string for size @val.
+ * Use IEC binary units like KiB, MiB, and so forth.
+ *
+ * @val: The value to format.
+ * Can be anything that uint64_t allows (no more than "16 EiB").
+ *
+ * Caller is responsible for passing it to g_free().
+ */
+char *size_to_str(uint64_t val);
+
/* used to print char* safely */
#define STR_OR_NULL(str) ((str) ? (str) : "null")
diff --git a/qapi/string-output-visitor.c b/qapi/string-output-visitor.c
index 7ab64468d9..edf268b373 100644
--- a/qapi/string-output-visitor.c
+++ b/qapi/string-output-visitor.c
@@ -11,9 +11,9 @@
*/
#include "qemu/osdep.h"
-#include "qemu-common.h"
#include "qapi/string-output-visitor.h"
#include "qapi/visitor-impl.h"
+#include "qemu/cutils.h"
#include "qemu/host-utils.h"
#include
#include "qemu/range.h"
diff --git a/util/cutils.c b/util/cutils.c
index e098debdc0..a8a3a3ba3b 100644
--- a/util/cutils.c
+++ b/util/cutils.c
@@ -816,12 +816,6 @@ const char *qemu_ether_ntoa(const MACAddr *mac)
return ret;
}
-/*
- * Return human readable string for size @val.
- * @val can be anything that uint64_t allows (no more than "16 EiB").
- * Use IEC binary units like KiB, MiB, and so forth.
- * Caller is responsible for passing it to g_free().
- */
char *size_to_str(uint64_t val)
{
static const char *suffixes[] = { "", "Ki", "Mi", "Gi", "Ti", "Pi", "Ei" };
--
2.17.2
[Qemu-devel] [PATCH] hw/char/stm32f2xx_usart: Do not update data register when device is disabled
When the device is disable, the internal circuitry keep the data
register loaded and doesn't update it.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/stm32f2xx_usart.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c
index f3363a2952..10392c70e2 100644
--- a/hw/char/stm32f2xx_usart.c
+++ b/hw/char/stm32f2xx_usart.c
@@ -53,14 +53,13 @@ static void stm32f2xx_usart_receive(void *opaque, const
uint8_t *buf, int size)
{
STM32F2XXUsartState *s = opaque;
-s->usart_dr = *buf;
-
if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {
/* USART not enabled - drop the chars */
DB_PRINT("Dropping the chars\n");
return;
}
+s->usart_dr = *buf;
s->usart_sr |= USART_SR_RXNE;
if (s->usart_cr1 & USART_CR1_RXNEIE) {
--
2.17.2
[Qemu-devel] [PATCH 16/16] RFC hw/net/smc91c111: Convert init helper into an inline function
Signed-off-by: Philippe Mathieu-Daudé
---
As init helper in "hw/char/pl011.h"
---
hw/net/smc91c111.c | 17 -
include/hw/net/smc91c111.h | 25 -
2 files changed, 24 insertions(+), 18 deletions(-)
diff --git a/hw/net/smc91c111.c b/hw/net/smc91c111.c
index d19ea0750d..3472852270 100644
--- a/hw/net/smc91c111.c
+++ b/hw/net/smc91c111.c
@@ -18,7 +18,6 @@
/* Number of 2k memory pages available. */
#define NUM_PACKETS 4
-#define TYPE_SMC91C111 "smc91c111"
#define SMC91C111(obj) OBJECT_CHECK(smc91c111_state, (obj), TYPE_SMC91C111)
typedef struct {
@@ -809,20 +808,4 @@ static void smc91c111_register_types(void)
type_register_static(_info);
}
-/* Legacy helper function. Should go away when machine config files are
- implemented. */
-void smc91c111_init(NICInfo *nd, uint32_t base, qemu_irq irq)
-{
-DeviceState *dev;
-SysBusDevice *s;
-
-qemu_check_nic_model(nd, "smc91c111");
-dev = qdev_create(NULL, TYPE_SMC91C111);
-qdev_set_nic_properties(dev, nd);
-qdev_init_nofail(dev);
-s = SYS_BUS_DEVICE(dev);
-sysbus_mmio_map(s, 0, base);
-sysbus_connect_irq(s, 0, irq);
-}
-
type_init(smc91c111_register_types)
diff --git a/include/hw/net/smc91c111.h b/include/hw/net/smc91c111.h
index 46f7d9a5d4..0a1097ddd2 100644
--- a/include/hw/net/smc91c111.h
+++ b/include/hw/net/smc91c111.h
@@ -10,9 +10,32 @@
#ifndef HW_NET_SMC91C111_H
#define HW_NET_SMC91C111_H
+#include "hw/qdev.h"
#include "hw/irq.h"
+#include "hw/sysbus.h"
#include "net/net.h"
-void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
+#define TYPE_SMC91C111 "smc91c111"
+
+/*
+ * Legacy helper function. Should go away when machine config files are
+ * implemented.
+ */
+static inline DeviceState *smc91c111_init(NICInfo *nd,
+ uint32_t base, qemu_irq irq)
+{
+DeviceState *dev;
+SysBusDevice *s;
+
+qemu_check_nic_model(nd, "smc91c111");
+dev = qdev_create(NULL, TYPE_SMC91C111);
+qdev_set_nic_properties(dev, nd);
+qdev_init_nofail(dev);
+s = SYS_BUS_DEVICE(dev);
+sysbus_mmio_map(s, 0, base);
+sysbus_connect_irq(s, 0, irq);
+
+return dev;
+}
#endif
--
2.17.2
[Qemu-devel] [PATCH 15/16] hw/devices: Move SMSC 91C111 declaration into a new header
This commit finally deletes "hw/devices.h". Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/gumstix.c | 2 +- hw/arm/integratorcp.c | 2 +- hw/arm/mainstone.c | 2 +- hw/arm/realview.c | 2 +- hw/arm/versatilepb.c | 2 +- hw/net/smc91c111.c | 2 +- include/hw/devices.h | 11 --- include/hw/net/smc91c111.h | 18 ++ 8 files changed, 24 insertions(+), 17 deletions(-) delete mode 100644 include/hw/devices.h create mode 100644 include/hw/net/smc91c111.h diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c index 56cb763c4e..98c3e6d41c 100644 --- a/hw/arm/gumstix.c +++ b/hw/arm/gumstix.c @@ -40,7 +40,7 @@ #include "hw/arm/pxa.h" #include "net/net.h" #include "hw/block/flash.h" -#include "hw/devices.h" +#include "hw/net/smc91c111.h" #include "hw/boards.h" #include "exec/address-spaces.h" #include "sysemu/qtest.h" diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index 4eceebb9ea..0b6f24465e 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -12,10 +12,10 @@ #include "qemu-common.h" #include "cpu.h" #include "hw/sysbus.h" -#include "hw/devices.h" #include "hw/boards.h" #include "hw/arm/arm.h" #include "hw/misc/arm_integrator_debug.h" +#include "hw/net/smc91c111.h" #include "net/net.h" #include "exec/address-spaces.h" #include "sysemu/sysemu.h" diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c index 0beb5c426b..fbe8d5cbd4 100644 --- a/hw/arm/mainstone.c +++ b/hw/arm/mainstone.c @@ -18,7 +18,7 @@ #include "hw/arm/pxa.h" #include "hw/arm/arm.h" #include "net/net.h" -#include "hw/devices.h" +#include "hw/net/smc91c111.h" #include "hw/boards.h" #include "hw/block/flash.h" #include "hw/sysbus.h" diff --git a/hw/arm/realview.c b/hw/arm/realview.c index e9983c8763..05a244df25 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -14,8 +14,8 @@ #include "hw/sysbus.h" #include "hw/arm/arm.h" #include "hw/arm/primecell.h" -#include "hw/devices.h" #include "hw/net/lan9118.h" +#include "hw/net/smc91c111.h" #include "hw/pci/pci.h" #include "net/net.h" #include "sysemu/sysemu.h" diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index 22b09a1e61..70b5fda737 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -13,7 +13,7 @@ #include "cpu.h" #include "hw/sysbus.h" #include "hw/arm/arm.h" -#include "hw/devices.h" +#include "hw/net/smc91c111.h" #include "net/net.h" #include "sysemu/sysemu.h" #include "hw/pci/pci.h" diff --git a/hw/net/smc91c111.c b/hw/net/smc91c111.c index 99da2d9297..d19ea0750d 100644 --- a/hw/net/smc91c111.c +++ b/hw/net/smc91c111.c @@ -10,7 +10,7 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" #include "net/net.h" -#include "hw/devices.h" +#include "hw/net/smc91c111.h" #include "qemu/log.h" /* For crc32 */ #include diff --git a/include/hw/devices.h b/include/hw/devices.h deleted file mode 100644 index ebc45c8799..00 --- a/include/hw/devices.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef QEMU_DEVICES_H -#define QEMU_DEVICES_H - -/* Devices that have nowhere better to go. */ - -#include "hw/hw.h" - -/* smc91c111.c */ -void smc91c111_init(NICInfo *, uint32_t, qemu_irq); - -#endif diff --git a/include/hw/net/smc91c111.h b/include/hw/net/smc91c111.h new file mode 100644 index 00..46f7d9a5d4 --- /dev/null +++ b/include/hw/net/smc91c111.h @@ -0,0 +1,18 @@ +/* + * SMSC 91C111 Ethernet interface emulation + * + * Copyright (c) 2005 CodeSourcery, LLC. + * Written by Paul Brook + * + * This code is licensed under the GPL + */ + +#ifndef HW_NET_SMC91C111_H +#define HW_NET_SMC91C111_H + +#include "hw/irq.h" +#include "net/net.h" + +void smc91c111_init(NICInfo *, uint32_t, qemu_irq); + +#endif -- 2.17.2
[Qemu-devel] [PATCH 13/16] hw/net/ne2000-isa: Add guards to the header
Signed-off-by: Philippe Mathieu-Daudé --- include/hw/net/ne2000-isa.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/hw/net/ne2000-isa.h b/include/hw/net/ne2000-isa.h index ff2bed9c95..527337c454 100644 --- a/include/hw/net/ne2000-isa.h +++ b/include/hw/net/ne2000-isa.h @@ -6,6 +6,10 @@ * This work is licensed under the terms of the GNU GPL, version 2 or later. * See the COPYING file in the top-level directory. */ + +#ifndef HW_NET_NE2K_ISA_H +#define HW_NET_NE2K_ISA_H + #include "hw/hw.h" #include "hw/qdev.h" #include "hw/isa/isa.h" @@ -31,3 +35,5 @@ static inline ISADevice *isa_ne2000_init(ISABus *bus, int base, int irq, } return d; } + +#endif -- 2.17.2
[Qemu-devel] [PATCH v2 3/3] util/cutils: Move function documentations to the header
Many functions have documentation before the implementation in
cutils.c. Since we expect documentation around the prototype
declaration in headers, move the comments in cutils.h.
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/cutils.h | 224 ++
util/cutils.c | 185 --
2 files changed, 224 insertions(+), 185 deletions(-)
diff --git a/include/qemu/cutils.h b/include/qemu/cutils.h
index 644f2d75bd..f41b00ad37 100644
--- a/include/qemu/cutils.h
+++ b/include/qemu/cutils.h
@@ -47,6 +47,7 @@
*bytes and then add a NUL
*/
void pstrcpy(char *buf, int buf_size, const char *str);
+
/**
* strpadcpy:
* @buf: buffer to copy string into
@@ -60,6 +61,7 @@ void pstrcpy(char *buf, int buf_size, const char *str);
* first @buf_size characters of @str, with no terminator.
*/
void strpadcpy(char *buf, int buf_size, const char *str, char pad);
+
/**
* pstrcat:
* @buf: buffer containing existing string
@@ -77,6 +79,7 @@ void strpadcpy(char *buf, int buf_size, const char *str, char
pad);
* Returns: @buf.
*/
char *pstrcat(char *buf, int buf_size, const char *s);
+
/**
* strstart:
* @str: string to test
@@ -94,6 +97,7 @@ char *pstrcat(char *buf, int buf_size, const char *s);
* Returns: true if @str starts with prefix @val, false otherwise.
*/
int strstart(const char *str, const char *val, const char **ptr);
+
/**
* stristart:
* @str: string to test
@@ -110,6 +114,7 @@ int strstart(const char *str, const char *val, const char
**ptr);
* false otherwise.
*/
int stristart(const char *str, const char *val, const char **ptr);
+
/**
* qemu_strnlen:
* @s: string
@@ -126,6 +131,7 @@ int stristart(const char *str, const char *val, const char
**ptr);
* Returns: length of @s in bytes, or @max_len, whichever is smaller.
*/
int qemu_strnlen(const char *s, int max_len);
+
/**
* qemu_strsep:
* @input: pointer to string to parse
@@ -147,6 +153,16 @@ int qemu_strnlen(const char *s, int max_len);
* Returns: the pointer originally in @input.
*/
char *qemu_strsep(char **input, const char *delim);
+
+/**
+ * qemu_strchrnul:
+ *
+ * @s: String to parse.
+ * @c: Character to find.
+ *
+ * Searches for the first occurrence of @c in @s, and returns a pointer
+ * to the trailing null byte if none was found.
+ */
#ifdef HAVE_STRCHRNUL
static inline const char *qemu_strchrnul(const char *s, int c)
{
@@ -155,27 +171,235 @@ static inline const char *qemu_strchrnul(const char *s,
int c)
#else
const char *qemu_strchrnul(const char *s, int c);
#endif
+
time_t mktimegm(struct tm *tm);
int qemu_fdatasync(int fd);
int fcntl_setfl(int fd, int flag);
int qemu_parse_fd(const char *param);
+
+/**
+ * qemu_strtoi:
+ *
+ * Convert string @nptr to an integer, and store it in @result.
+ *
+ * This is a wrapper around strtol() that is harder to misuse.
+ * Semantics of @nptr, @endptr, @base match strtol() with differences
+ * noted below.
+ *
+ * @nptr may be null, and no conversion is performed then.
+ *
+ * If no conversion is performed, store @nptr in *@endptr and return
+ * -EINVAL.
+ *
+ * If @endptr is null, and the string isn't fully converted, return
+ * -EINVAL. This is the case when the pointer that would be stored in
+ * a non-null @endptr points to a character other than '\0'.
+ *
+ * If the conversion overflows @result, store INT_MAX in @result,
+ * and return -ERANGE.
+ *
+ * If the conversion underflows @result, store INT_MIN in @result,
+ * and return -ERANGE.
+ *
+ * Else store the converted value in @result, and return zero.
+ */
int qemu_strtoi(const char *nptr, const char **endptr, int base,
int *result);
+
+/**
+ * qemu_strtoui:
+ *
+ * Convert string @nptr to an unsigned integer, and store it in @result.
+ *
+ * This is a wrapper around strtoul() that is harder to misuse.
+ * Semantics of @nptr, @endptr, @base match strtoul() with differences
+ * noted below.
+ *
+ * @nptr may be null, and no conversion is performed then.
+ *
+ * If no conversion is performed, store @nptr in *@endptr and return
+ * -EINVAL.
+ *
+ * If @endptr is null, and the string isn't fully converted, return
+ * -EINVAL. This is the case when the pointer that would be stored in
+ * a non-null @endptr points to a character other than '\0'.
+ *
+ * If the conversion overflows @result, store UINT_MAX in @result,
+ * and return -ERANGE.
+ *
+ * Else store the converted value in @result, and return zero.
+ *
+ * Note that a number with a leading minus sign gets converted without
+ * the minus sign, checked for overflow (see above), then negated (in
+ * @result's type). This is exactly how strtoul() works.
+ */
int qemu_strtoui(const char *nptr, const char **endptr, int base,
unsigned int *result);
+
+/**
+ * qemu_strtol:
+ *
+ * Convert string @nptr to a long integer, and store it in @result.
+ *
+ * This is a wrapper around strtol() that is harder to misuse.
+ *
[Qemu-devel] [PATCH v2 2/3] util/cutils: Move ctype macros to "cutils.h"
Introduced in cd390083ad1, these macros don't need to be in a generic header. Add documentation to justify their use. Reviewed-by: Stefano Garzarella Signed-off-by: Philippe Mathieu-Daudé --- v2: Fixed checkpatch warnings (tabs) --- hw/core/bus.c | 2 +- hw/core/qdev-properties.c | 1 + hw/s390x/s390-virtio-ccw.c | 1 + hw/scsi/scsi-generic.c | 2 +- include/qemu-common.h | 16 include/qemu/cutils.h | 25 + qapi/qapi-util.c | 2 +- qobject/json-parser.c | 1 - target/ppc/monitor.c | 1 + ui/keymaps.c | 1 + util/id.c | 2 +- util/readline.c| 1 - 12 files changed, 33 insertions(+), 22 deletions(-) diff --git a/hw/core/bus.c b/hw/core/bus.c index 4651f24486..dceb144075 100644 --- a/hw/core/bus.c +++ b/hw/core/bus.c @@ -18,7 +18,7 @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" +#include "qemu/cutils.h" #include "hw/qdev.h" #include "qapi/error.h" diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c index 943dc2654b..3bdebac361 100644 --- a/hw/core/qdev-properties.c +++ b/hw/core/qdev-properties.c @@ -1,4 +1,5 @@ #include "qemu/osdep.h" +#include "qemu/cutils.h" #include "net/net.h" #include "hw/qdev.h" #include "qapi/error.h" diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index fd9d0b0542..ed23bb7b3a 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -11,6 +11,7 @@ */ #include "qemu/osdep.h" +#include "qemu/cutils.h" #include "qapi/error.h" #include "cpu.h" #include "hw/boards.h" diff --git a/hw/scsi/scsi-generic.c b/hw/scsi/scsi-generic.c index 7237b4162e..86f65fd474 100644 --- a/hw/scsi/scsi-generic.c +++ b/hw/scsi/scsi-generic.c @@ -12,8 +12,8 @@ */ #include "qemu/osdep.h" +#include "qemu/cutils.h" #include "qapi/error.h" -#include "qemu-common.h" #include "qemu/error-report.h" #include "hw/scsi/scsi.h" #include "hw/scsi/emulation.h" diff --git a/include/qemu-common.h b/include/qemu-common.h index 760527294f..ed43ae286d 100644 --- a/include/qemu-common.h +++ b/include/qemu-common.h @@ -33,22 +33,6 @@ int qemu_main(int argc, char **argv, char **envp); void qemu_get_timedate(struct tm *tm, int offset); int qemu_timedate_diff(struct tm *tm); -#define qemu_isalnum(c)isalnum((unsigned char)(c)) -#define qemu_isalpha(c)isalpha((unsigned char)(c)) -#define qemu_iscntrl(c)iscntrl((unsigned char)(c)) -#define qemu_isdigit(c)isdigit((unsigned char)(c)) -#define qemu_isgraph(c)isgraph((unsigned char)(c)) -#define qemu_islower(c)islower((unsigned char)(c)) -#define qemu_isprint(c)isprint((unsigned char)(c)) -#define qemu_ispunct(c)ispunct((unsigned char)(c)) -#define qemu_isspace(c)isspace((unsigned char)(c)) -#define qemu_isupper(c)isupper((unsigned char)(c)) -#define qemu_isxdigit(c) isxdigit((unsigned char)(c)) -#define qemu_tolower(c)tolower((unsigned char)(c)) -#define qemu_toupper(c)toupper((unsigned char)(c)) -#define qemu_isascii(c)isascii((unsigned char)(c)) -#define qemu_toascii(c)toascii((unsigned char)(c)) - void *qemu_oom_check(void *ptr); ssize_t qemu_write_full(int fd, const void *buf, size_t count) diff --git a/include/qemu/cutils.h b/include/qemu/cutils.h index 9ee40470e3..644f2d75bd 100644 --- a/include/qemu/cutils.h +++ b/include/qemu/cutils.h @@ -3,6 +3,31 @@ #include "qemu/fprintf-fn.h" +/** + * unsigned ctype macros: + * + * The standards require that the argument for these functions + * is either EOF or a value that is representable in the type + * unsigned char. If the argument is of type char, it must be + * cast to unsigned char. This is what these macros do, + * avoiding 'signed to unsigned' conversion warnings. + */ +#define qemu_isalnum(c) isalnum((unsigned char)(c)) +#define qemu_isalpha(c) isalpha((unsigned char)(c)) +#define qemu_iscntrl(c) iscntrl((unsigned char)(c)) +#define qemu_isdigit(c) isdigit((unsigned char)(c)) +#define qemu_isgraph(c) isgraph((unsigned char)(c)) +#define qemu_islower(c) islower((unsigned char)(c)) +#define qemu_isprint(c) isprint((unsigned char)(c)) +#define qemu_ispunct(c) ispunct((unsigned char)(c)) +#define qemu_isspace(c) isspace((unsigned char)(c)) +#define qemu_isupper(c) isupper((unsigned char)(c)) +#define qemu_isxdigit(c)isxdigit((unsigned char)(c)) +#define qemu_tolower(c) tolower((unsigned char)(c)) +#define qemu_toupper(c) toupper((unsigned char)(c)) +#define qemu_isascii(c) isascii((unsigned char)(c)) +#define qemu_toascii(c) toascii((unsigned char)(c)) + /** * pstrcpy: * @buf: buffer to copy string into diff --git a/qapi/qapi-util.c b/qapi/qapi-util.c index e9b266bb70..ea93ae05d9 100644 ---
[Qemu-devel] [PATCH v2 0/3] cutils: Cleanup, improve documentation
This series is a fairly trivial cleanup of "cutils.h" (size_to_str() and ctype macros moved into it), and some documentation improvements. Since v1: - Fixed checkpatch errors (patchew) - Added Stefano R-b There are still checkpatch warnings (due to 8c06fbdf36b) for using the Doxygen '/**' comment opening: WARNING: Block comments use a leading /* on a separate line #42: FILE: include/qemu/cutils.h:160: +/** v1: https://lists.gnu.org/archive/html/qemu-devel/2018-12/msg05927.html Regards, Phil. Philippe Mathieu-Daudé (3): util/cutils: Move size_to_str() from "qemu-common.h" to "cutils.h" util/cutils: Move ctype macros to "cutils.h" util/cutils: Move function documentations to the header hw/core/bus.c| 2 +- hw/core/qdev-properties.c| 1 + hw/s390x/s390-virtio-ccw.c | 1 + hw/scsi/scsi-generic.c | 2 +- include/qemu-common.h| 17 --- include/qemu/cutils.h| 262 +++ qapi/qapi-util.c | 2 +- qapi/string-output-visitor.c | 2 +- qobject/json-parser.c| 1 - target/ppc/monitor.c | 1 + ui/keymaps.c | 1 + util/cutils.c| 191 - util/id.c| 2 +- util/readline.c | 1 - 14 files changed, 271 insertions(+), 215 deletions(-) -- 2.17.2
[Qemu-devel] [PATCH 10/16] typedefs: Remove MouseTransformInfo
MouseTransformInfo is only used in "ui/console.h", there is no
need to expose it via "qemu/typedefs.h".
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/typedefs.h | 1 -
include/ui/console.h| 4 ++--
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index 5d2b2925fb..927b340bb4 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -56,7 +56,6 @@ typedef struct MigrationIncomingState MigrationIncomingState;
typedef struct MigrationState MigrationState;
typedef struct Monitor Monitor;
typedef struct MonitorDef MonitorDef;
-typedef struct MouseTransformInfo MouseTransformInfo;
typedef struct MSIMessage MSIMessage;
typedef struct NetClientState NetClientState;
typedef struct NetFilterState NetFilterState;
diff --git a/include/ui/console.h b/include/ui/console.h
index c17803c530..28fd76c1c5 100644
--- a/include/ui/console.h
+++ b/include/ui/console.h
@@ -65,13 +65,13 @@ void qemu_remove_led_event_handler(QEMUPutLEDEntry *entry);
void kbd_put_ledstate(int ledstate);
-struct MouseTransformInfo {
+typedef struct MouseTransformInfo {
/* Touchscreen resolution */
int x;
int y;
/* Calibration values as used/generated by tslib */
int a[7];
-};
+} MouseTransformInfo;
void hmp_mouse_set(Monitor *mon, const QDict *qdict);
--
2.17.2
[Qemu-devel] [PATCH 12/16] hw/devices: Move LAN9118 declarations into a new header
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/kzm.c | 2 +-
hw/arm/mps2.c| 2 +-
hw/arm/realview.c| 1 +
hw/arm/vexpress.c| 2 +-
hw/net/lan9118.c | 2 +-
include/hw/devices.h | 3 ---
include/hw/net/lan9118.h | 21 +
7 files changed, 26 insertions(+), 7 deletions(-)
create mode 100644 include/hw/net/lan9118.h
diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c
index 864c7bd411..139934c4ec 100644
--- a/hw/arm/kzm.c
+++ b/hw/arm/kzm.c
@@ -22,7 +22,7 @@
#include "qemu/error-report.h"
#include "exec/address-spaces.h"
#include "net/net.h"
-#include "hw/devices.h"
+#include "hw/net/lan9118.h"
#include "hw/char/serial.h"
#include "sysemu/qtest.h"
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index e3d698ba6c..54b7395849 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -36,7 +36,7 @@
#include "hw/timer/cmsdk-apb-timer.h"
#include "hw/timer/cmsdk-apb-dualtimer.h"
#include "hw/misc/mps2-scc.h"
-#include "hw/devices.h"
+#include "hw/net/lan9118.h"
#include "net/net.h"
typedef enum MPS2FPGAType {
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index 242f5a87b6..e9983c8763 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -15,6 +15,7 @@
#include "hw/arm/arm.h"
#include "hw/arm/primecell.h"
#include "hw/devices.h"
+#include "hw/net/lan9118.h"
#include "hw/pci/pci.h"
#include "net/net.h"
#include "sysemu/sysemu.h"
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index c02d18ee61..12e2c3986f 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -28,7 +28,7 @@
#include "hw/sysbus.h"
#include "hw/arm/arm.h"
#include "hw/arm/primecell.h"
-#include "hw/devices.h"
+#include "hw/net/lan9118.h"
#include "hw/i2c/i2c.h"
#include "net/net.h"
#include "sysemu/sysemu.h"
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
index a6269d9463..a428b16eda 100644
--- a/hw/net/lan9118.c
+++ b/hw/net/lan9118.c
@@ -14,7 +14,7 @@
#include "hw/sysbus.h"
#include "net/net.h"
#include "net/eth.h"
-#include "hw/devices.h"
+#include "hw/net/lan9118.h"
#include "sysemu/sysemu.h"
#include "hw/ptimer.h"
#include "qemu/log.h"
diff --git a/include/hw/devices.h b/include/hw/devices.h
index ba9034050b..ebc45c8799 100644
--- a/include/hw/devices.h
+++ b/include/hw/devices.h
@@ -8,7 +8,4 @@
/* smc91c111.c */
void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
-/* lan9118.c */
-void lan9118_init(NICInfo *, uint32_t, qemu_irq);
-
#endif
diff --git a/include/hw/net/lan9118.h b/include/hw/net/lan9118.h
new file mode 100644
index 00..340d6681b7
--- /dev/null
+++ b/include/hw/net/lan9118.h
@@ -0,0 +1,21 @@
+/*
+ * SMSC LAN9118 Ethernet interface emulation
+ *
+ * Copyright (c) 2009 CodeSourcery, LLC.
+ * Written by Paul Brook
+ *
+ * This code is licensed under the GNU GPL v2
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
+ */
+
+#ifndef HW_NET_LAN9118_H
+#define HW_NET_LAN9118_H
+
+#include "hw/irq.h"
+#include "net/net.h"
+
+void lan9118_init(NICInfo *, uint32_t, qemu_irq);
+
+#endif
--
2.17.2
[Qemu-devel] [PATCH 09/16] hw/devices: Move TI touchscreen declarations into a new header
Since uWireSlave is only used in this new header, there is no
need to expose it via "qemu/typedefs.h".
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 2 ++
hw/arm/nseries.c| 2 +-
hw/arm/palm.c | 2 +-
hw/input/tsc2005.c | 2 +-
hw/input/tsc210x.c | 4 ++--
include/hw/arm/omap.h | 6 +-
include/hw/devices.h| 14 --
include/hw/input/ti_uwire_tsc.h | 28
include/qemu/typedefs.h | 1 -
9 files changed, 36 insertions(+), 25 deletions(-)
create mode 100644 include/hw/input/ti_uwire_tsc.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 03872552ee..4722805d9e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -642,6 +642,7 @@ S: Odd Fixes
F: hw/arm/nseries.c
F: hw/input/tsc2*.c
F: include/hw/display/blizzard.h
+F: include/hw/input/ti_uwire_tsc.h
F: include/hw/misc/cbus.h
Palm
@@ -651,6 +652,7 @@ L: qemu-...@nongnu.org
S: Odd Fixes
F: hw/arm/palm.c
F: hw/input/tsc2*.c
+F: include/hw/input/ti_uwire_tsc.h
Raspberry Pi
M: Peter Maydell
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
index ac876b5878..f1c94ca607 100644
--- a/hw/arm/nseries.c
+++ b/hw/arm/nseries.c
@@ -30,8 +30,8 @@
#include "ui/console.h"
#include "hw/boards.h"
#include "hw/i2c/i2c.h"
-#include "hw/devices.h"
#include "hw/display/blizzard.h"
+#include "hw/input/ti_uwire_tsc.h"
#include "hw/misc/cbus.h"
#include "hw/block/flash.h"
#include "hw/hw.h"
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
index 285f43709d..2327a25be3 100644
--- a/hw/arm/palm.c
+++ b/hw/arm/palm.c
@@ -26,7 +26,7 @@
#include "hw/arm/omap.h"
#include "hw/boards.h"
#include "hw/arm/arm.h"
-#include "hw/devices.h"
+#include "hw/input/ti_uwire_tsc.h"
#include "hw/loader.h"
#include "exec/address-spaces.h"
#include "cpu.h"
diff --git a/hw/input/tsc2005.c b/hw/input/tsc2005.c
index 2b9108a193..d3c79f7825 100644
--- a/hw/input/tsc2005.c
+++ b/hw/input/tsc2005.c
@@ -23,7 +23,7 @@
#include "hw/hw.h"
#include "qemu/timer.h"
#include "ui/console.h"
-#include "hw/devices.h"
+#include "hw/input/ti_uwire_tsc.h"
#include "trace.h"
#define TSC_CUT_RESOLUTION(value, p) ((value) >> (16 - (p ? 12 : 10)))
diff --git a/hw/input/tsc210x.c b/hw/input/tsc210x.c
index 1cad57f644..8e4c282989 100644
--- a/hw/input/tsc210x.c
+++ b/hw/input/tsc210x.c
@@ -24,8 +24,8 @@
#include "audio/audio.h"
#include "qemu/timer.h"
#include "ui/console.h"
-#include "hw/arm/omap.h" /* For I2SCodec and uWireSlave */
-#include "hw/devices.h"
+#include "hw/arm/omap.h"/* For I2SCodec */
+#include "hw/input/ti_uwire_tsc.h"
#define TSC_DATA_REGISTERS_PAGE0x0
#define TSC_CONTROL_REGISTERS_PAGE 0x1
diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
index e7fbd340f3..fc0fe4f7a2 100644
--- a/include/hw/arm/omap.h
+++ b/include/hw/arm/omap.h
@@ -20,6 +20,7 @@
#include "exec/memory.h"
# define hw_omap_h "omap.h"
#include "hw/irq.h"
+#include "hw/input/ti_uwire_tsc.h"
#include "target/arm/cpu-qom.h"
#include "qemu/log.h"
@@ -679,11 +680,6 @@ qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
-struct uWireSlave {
-uint16_t (*receive)(void *opaque);
-void (*send)(void *opaque, uint16_t data);
-void *opaque;
-};
struct omap_uwire_s;
void omap_uwire_attach(struct omap_uwire_s *s,
uWireSlave *slave, int chipselect);
diff --git a/include/hw/devices.h b/include/hw/devices.h
index d9c06de7ab..ba9034050b 100644
--- a/include/hw/devices.h
+++ b/include/hw/devices.h
@@ -11,18 +11,4 @@ void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
/* lan9118.c */
void lan9118_init(NICInfo *, uint32_t, qemu_irq);
-/* tsc210x.c */
-uWireSlave *tsc2102_init(qemu_irq pint);
-uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav);
-I2SCodec *tsc210x_codec(uWireSlave *chip);
-uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len);
-void tsc210x_set_transform(uWireSlave *chip,
-MouseTransformInfo *info);
-void tsc210x_key_event(uWireSlave *chip, int key, int down);
-
-/* tsc2005.c */
-void *tsc2005_init(qemu_irq pintdav);
-uint32_t tsc2005_txrx(void *opaque, uint32_t value, int len);
-void tsc2005_set_transform(void *opaque, MouseTransformInfo *info);
-
#endif
diff --git a/include/hw/input/ti_uwire_tsc.h b/include/hw/input/ti_uwire_tsc.h
new file mode 100644
index 00..0f8f296bc3
--- /dev/null
+++ b/include/hw/input/ti_uwire_tsc.h
@@ -0,0 +1,28 @@
+#ifndef HW_INPUT_TI_UWIRE_TOUCHSCREEN_H
+#define HW_INPUT_TI_UWIRE_TOUCHSCREEN_H
+
+/* TI 4/8-wire resistive touch screen converters */
+
+#include "hw/irq.h"
+#include "ui/console.h"
+
+typedef struct uWireSlave {
+uint16_t (*receive)(void *opaque);
+void (*send)(void *opaque, uint16_t data);
+void *opaque;
[Qemu-devel] [PATCH 14/16] hw/net/lan9118: Export TYPE_LAN9118 and use it instead of hardcoded string
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/exynos4_boards.c | 3 ++-
hw/arm/mps2-tz.c | 3 ++-
hw/net/lan9118.c | 1 -
include/hw/net/lan9118.h | 2 ++
4 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index 750162cc95..ea8100f65a 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -32,6 +32,7 @@
#include "hw/arm/arm.h"
#include "exec/address-spaces.h"
#include "hw/arm/exynos4210.h"
+#include "hw/net/lan9118.h"
#include "hw/boards.h"
#undef DEBUG
@@ -92,7 +93,7 @@ static void lan9215_init(uint32_t base, qemu_irq irq)
/* This should be a 9215 but the 9118 is close enough */
if (nd_table[0].used) {
qemu_check_nic_model(_table[0], "lan9118");
-dev = qdev_create(NULL, "lan9118");
+dev = qdev_create(NULL, TYPE_LAN9118);
qdev_set_nic_properties(dev, _table[0]);
qdev_prop_set_uint32(dev, "mode_16bit", 1);
qdev_init_nofail(dev);
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index 1232d6ff95..b6a8693d7c 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -49,6 +49,7 @@
#include "hw/arm/iotkit.h"
#include "hw/dma/pl080.h"
#include "hw/ssi/pl022.h"
+#include "hw/net/lan9118.h"
#include "net/net.h"
#include "hw/core/split-irq.h"
@@ -219,7 +220,7 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms,
void *opaque,
* except that it doesn't support the checksum-offload feature.
*/
qemu_check_nic_model(nd, "lan9118");
-mms->lan9118 = qdev_create(NULL, "lan9118");
+mms->lan9118 = qdev_create(NULL, TYPE_LAN9118);
qdev_set_nic_properties(mms->lan9118, nd);
qdev_init_nofail(mms->lan9118);
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
index a428b16eda..b29e3fee49 100644
--- a/hw/net/lan9118.c
+++ b/hw/net/lan9118.c
@@ -175,7 +175,6 @@ static const VMStateDescription vmstate_lan9118_packet = {
}
};
-#define TYPE_LAN9118 "lan9118"
#define LAN9118(obj) OBJECT_CHECK(lan9118_state, (obj), TYPE_LAN9118)
typedef struct {
diff --git a/include/hw/net/lan9118.h b/include/hw/net/lan9118.h
index 340d6681b7..2a3e2b0dea 100644
--- a/include/hw/net/lan9118.h
+++ b/include/hw/net/lan9118.h
@@ -16,6 +16,8 @@
#include "hw/irq.h"
#include "net/net.h"
+#define TYPE_LAN9118 "lan9118"
+
void lan9118_init(NICInfo *, uint32_t, qemu_irq);
#endif
--
2.17.2
[Qemu-devel] [PATCH 11/16] typedefs: Remove PS2State
PS2State is only used in "hw/input/ps2.h", there is no need to expose it via "qemu/typedefs.h". Signed-off-by: Philippe Mathieu-Daudé --- include/hw/input/ps2.h | 2 ++ include/qemu/typedefs.h | 1 - 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/hw/input/ps2.h b/include/hw/input/ps2.h index 213aa16aa3..b60455d4f6 100644 --- a/include/hw/input/ps2.h +++ b/include/hw/input/ps2.h @@ -31,6 +31,8 @@ #define PS2_MOUSE_BUTTON_SIDE 0x08 #define PS2_MOUSE_BUTTON_EXTRA 0x10 +typedef struct PS2State PS2State; + /* ps2.c */ void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg); void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg); diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 927b340bb4..181f8fa68e 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -82,7 +82,6 @@ typedef struct PixelFormat PixelFormat; typedef struct PostcopyDiscardState PostcopyDiscardState; typedef struct Property Property; typedef struct PropertyInfo PropertyInfo; -typedef struct PS2State PS2State; typedef struct QEMUBH QEMUBH; typedef struct QemuConsole QemuConsole; typedef struct QemuDmaBuf QemuDmaBuf; -- 2.17.2
[Qemu-devel] [PATCH 05/16] hw/devices: Move Blizzard declarations into a new header
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1 +
hw/arm/nseries.c | 1 +
hw/display/blizzard.c | 2 +-
include/hw/devices.h | 7 ---
include/hw/display/blizzard.h | 21 +
5 files changed, 24 insertions(+), 8 deletions(-)
create mode 100644 include/hw/display/blizzard.h
diff --git a/MAINTAINERS b/MAINTAINERS
index dff4b98401..156ce9a698 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -640,6 +640,7 @@ M: Peter Maydell
L: qemu-...@nongnu.org
S: Odd Fixes
F: hw/arm/nseries.c
+F: include/hw/display/blizzard.h
Palm
M: Andrzej Zaborowski
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
index 906b7ca22d..9521be1cef 100644
--- a/hw/arm/nseries.c
+++ b/hw/arm/nseries.c
@@ -31,6 +31,7 @@
#include "hw/boards.h"
#include "hw/i2c/i2c.h"
#include "hw/devices.h"
+#include "hw/display/blizzard.h"
#include "hw/block/flash.h"
#include "hw/hw.h"
#include "hw/bt.h"
diff --git a/hw/display/blizzard.c b/hw/display/blizzard.c
index 291abe6fca..471bd0ed99 100644
--- a/hw/display/blizzard.c
+++ b/hw/display/blizzard.c
@@ -21,7 +21,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "ui/console.h"
-#include "hw/devices.h"
+#include "hw/display/blizzard.h"
#include "ui/pixel_ops.h"
typedef void (*blizzard_fn_t)(uint8_t *, const uint8_t *, unsigned int);
diff --git a/include/hw/devices.h b/include/hw/devices.h
index 5ad134232c..25f895b330 100644
--- a/include/hw/devices.h
+++ b/include/hw/devices.h
@@ -28,13 +28,6 @@ void tsc2005_set_transform(void *opaque, MouseTransformInfo
*info);
/* stellaris_input.c */
void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode);
-/* blizzard.c */
-void *s1d13745_init(qemu_irq gpio_int);
-void s1d13745_write(void *opaque, int dc, uint16_t value);
-void s1d13745_write_block(void *opaque, int dc,
-void *buf, size_t len, int pitch);
-uint16_t s1d13745_read(void *opaque, int dc);
-
/* cbus.c */
typedef struct {
qemu_irq clk;
diff --git a/include/hw/display/blizzard.h b/include/hw/display/blizzard.h
new file mode 100644
index 00..8132557da1
--- /dev/null
+++ b/include/hw/display/blizzard.h
@@ -0,0 +1,21 @@
+/*
+ * Epson S1D13744/S1D13745 (Blizzard/Hailstorm/Tornado) LCD/TV controller.
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Written by Andrzej Zaborowski
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#ifndef HW_DISPLAY_BLIZZARD_H
+#define HW_DISPLAY_BLIZZARD_H
+
+#include "hw/irq.h"
+
+void *s1d13745_init(qemu_irq gpio_int);
+void s1d13745_write(void *opaque, int dc, uint16_t value);
+void s1d13745_write_block(void *opaque, int dc,
+ void *buf, size_t len, int pitch);
+uint16_t s1d13745_read(void *opaque, int dc);
+
+#endif
--
2.17.2
[Qemu-devel] [PATCH 07/16] hw/devices: Move Gamepad declarations into a new header
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS| 1 +
hw/arm/stellaris.c | 2 +-
hw/input/stellaris_input.c | 2 +-
include/hw/devices.h | 3 ---
include/hw/input/gamepad.h | 11 +++
5 files changed, 14 insertions(+), 5 deletions(-)
create mode 100644 include/hw/input/gamepad.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 63ed6636ef..f571b29077 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -714,6 +714,7 @@ M: Peter Maydell
L: qemu-...@nongnu.org
S: Maintained
F: hw/*/stellaris*
+F: include/hw/input/gamepad.h
Versatile Express
M: Peter Maydell
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 6c69ce79b2..0b4b382cdc 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -12,7 +12,6 @@
#include "hw/sysbus.h"
#include "hw/ssi/ssi.h"
#include "hw/arm/arm.h"
-#include "hw/devices.h"
#include "qemu/timer.h"
#include "hw/i2c/i2c.h"
#include "net/net.h"
@@ -22,6 +21,7 @@
#include "sysemu/sysemu.h"
#include "hw/arm/armv7m.h"
#include "hw/char/pl011.h"
+#include "hw/input/gamepad.h"
#include "hw/misc/unimp.h"
#include "cpu.h"
diff --git a/hw/input/stellaris_input.c b/hw/input/stellaris_input.c
index 99168bfeef..20c87d86f4 100644
--- a/hw/input/stellaris_input.c
+++ b/hw/input/stellaris_input.c
@@ -8,7 +8,7 @@
*/
#include "qemu/osdep.h"
#include "hw/hw.h"
-#include "hw/devices.h"
+#include "hw/input/gamepad.h"
#include "ui/console.h"
typedef struct {
diff --git a/include/hw/devices.h b/include/hw/devices.h
index 8b649541b1..d9c06de7ab 100644
--- a/include/hw/devices.h
+++ b/include/hw/devices.h
@@ -25,7 +25,4 @@ void *tsc2005_init(qemu_irq pintdav);
uint32_t tsc2005_txrx(void *opaque, uint32_t value, int len);
void tsc2005_set_transform(void *opaque, MouseTransformInfo *info);
-/* stellaris_input.c */
-void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode);
-
#endif
diff --git a/include/hw/input/gamepad.h b/include/hw/input/gamepad.h
new file mode 100644
index 00..5cd33a55bd
--- /dev/null
+++ b/include/hw/input/gamepad.h
@@ -0,0 +1,11 @@
+#ifndef HW_INPUT_GAMEPAD_H
+#define HW_INPUT_GAMEPAD_H
+
+/* Gamepad devices that have nowhere better to go. */
+
+#include "hw/irq.h"
+
+/* stellaris_input.c */
+void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode);
+
+#endif
--
2.17.2
[Qemu-devel] [PATCH 04/16] hw/devices: Move TC6393XB declarations into a new header
Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + hw/arm/tosa.c | 2 +- hw/display/tc6393xb.c | 2 +- include/hw/devices.h | 9 - include/hw/display/tc6393xb.h | 25 + 5 files changed, 28 insertions(+), 11 deletions(-) create mode 100644 include/hw/display/tc6393xb.h diff --git a/MAINTAINERS b/MAINTAINERS index 19792cfb2d..dff4b98401 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -685,6 +685,7 @@ F: hw/gpio/zaurus.c F: hw/misc/mst_fpga.c F: include/hw/arm/pxa.h F: include/hw/arm/sharpsl.h +F: include/hw/display/tc6393xb.h SABRELITE / i.MX6 M: Peter Maydell diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c index 7a925fa5e6..b6d464ab16 100644 --- a/hw/arm/tosa.c +++ b/hw/arm/tosa.c @@ -16,10 +16,10 @@ #include "hw/hw.h" #include "hw/arm/pxa.h" #include "hw/arm/arm.h" -#include "hw/devices.h" #include "hw/arm/sharpsl.h" #include "hw/pcmcia.h" #include "hw/boards.h" +#include "hw/display/tc6393xb.h" #include "hw/i2c/i2c.h" #include "hw/ssi/ssi.h" #include "hw/sysbus.h" diff --git a/hw/display/tc6393xb.c b/hw/display/tc6393xb.c index 3360be6f84..2a59af2dc3 100644 --- a/hw/display/tc6393xb.c +++ b/hw/display/tc6393xb.c @@ -14,7 +14,7 @@ #include "qapi/error.h" #include "qemu/host-utils.h" #include "hw/hw.h" -#include "hw/devices.h" +#include "hw/display/tc6393xb.h" #include "hw/block/flash.h" #include "ui/console.h" #include "ui/pixel_ops.h" diff --git a/include/hw/devices.h b/include/hw/devices.h index 4019b3be17..5ad134232c 100644 --- a/include/hw/devices.h +++ b/include/hw/devices.h @@ -49,13 +49,4 @@ void *tahvo_init(qemu_irq irq, int betty); void retu_key_event(void *retu, int state); -/* tc6393xb.c */ -typedef struct TC6393xbState TC6393xbState; -TC6393xbState *tc6393xb_init(struct MemoryRegion *sysmem, - uint32_t base, qemu_irq irq); -void tc6393xb_gpio_out_set(TC6393xbState *s, int line, -qemu_irq handler); -qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s); -qemu_irq tc6393xb_l3v_get(TC6393xbState *s); - #endif diff --git a/include/hw/display/tc6393xb.h b/include/hw/display/tc6393xb.h new file mode 100644 index 00..434c345aa1 --- /dev/null +++ b/include/hw/display/tc6393xb.h @@ -0,0 +1,25 @@ +/* + * Toshiba TC6393XB I/O Controller. + * Found in Sharp Zaurus SL-6000 (tosa) or some + * Toshiba e-Series PDAs. + * + * Copyright (c) 2007 Hervé Poussineau + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ +#ifndef HW_DISPLAY_TC6393XB_H +#define HW_DISPLAY_TC6393XB_H + +#include "exec/memory.h" +#include "hw/irq.h" + +typedef struct TC6393xbState TC6393xbState; + +TC6393xbState *tc6393xb_init(struct MemoryRegion *sysmem, + uint32_t base, qemu_irq irq); +void tc6393xb_gpio_out_set(TC6393xbState *s, int line, qemu_irq handler); +qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s); +qemu_irq tc6393xb_l3v_get(TC6393xbState *s); + +#endif -- 2.17.2
[Qemu-devel] [PATCH 06/16] hw/devices: Move CBus declarations into a new header
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS| 1 +
hw/arm/nseries.c | 1 +
hw/misc/cbus.c | 2 +-
include/hw/devices.h | 14 --
include/hw/misc/cbus.h | 31 +++
5 files changed, 34 insertions(+), 15 deletions(-)
create mode 100644 include/hw/misc/cbus.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 156ce9a698..63ed6636ef 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -641,6 +641,7 @@ L: qemu-...@nongnu.org
S: Odd Fixes
F: hw/arm/nseries.c
F: include/hw/display/blizzard.h
+F: include/hw/misc/cbus.h
Palm
M: Andrzej Zaborowski
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
index 9521be1cef..ac876b5878 100644
--- a/hw/arm/nseries.c
+++ b/hw/arm/nseries.c
@@ -32,6 +32,7 @@
#include "hw/i2c/i2c.h"
#include "hw/devices.h"
#include "hw/display/blizzard.h"
+#include "hw/misc/cbus.h"
#include "hw/block/flash.h"
#include "hw/hw.h"
#include "hw/bt.h"
diff --git a/hw/misc/cbus.c b/hw/misc/cbus.c
index 25e337ea77..16ee704bca 100644
--- a/hw/misc/cbus.c
+++ b/hw/misc/cbus.c
@@ -23,7 +23,7 @@
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/irq.h"
-#include "hw/devices.h"
+#include "hw/misc/cbus.h"
#include "sysemu/sysemu.h"
//#define DEBUG
diff --git a/include/hw/devices.h b/include/hw/devices.h
index 25f895b330..8b649541b1 100644
--- a/include/hw/devices.h
+++ b/include/hw/devices.h
@@ -28,18 +28,4 @@ void tsc2005_set_transform(void *opaque, MouseTransformInfo
*info);
/* stellaris_input.c */
void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode);
-/* cbus.c */
-typedef struct {
-qemu_irq clk;
-qemu_irq dat;
-qemu_irq sel;
-} CBus;
-CBus *cbus_init(qemu_irq dat_out);
-void cbus_attach(CBus *bus, void *slave_opaque);
-
-void *retu_init(qemu_irq irq, int vilma);
-void *tahvo_init(qemu_irq irq, int betty);
-
-void retu_key_event(void *retu, int state);
-
#endif
diff --git a/include/hw/misc/cbus.h b/include/hw/misc/cbus.h
new file mode 100644
index 00..1ce1855ccf
--- /dev/null
+++ b/include/hw/misc/cbus.h
@@ -0,0 +1,31 @@
+/*
+ * CBUS three-pin bus and the Retu / Betty / Tahvo / Vilma / Avilma /
+ * Hinku / Vinku / Ahne / Pihi chips used in various Nokia platforms.
+ * Based on reverse-engineering of a linux driver.
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Written by Andrzej Zaborowski
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#ifndef HW_MISC_CBUS_H
+#define HW_MISC_CBUS_H
+
+#include "hw/irq.h"
+
+typedef struct {
+qemu_irq clk;
+qemu_irq dat;
+qemu_irq sel;
+} CBus;
+
+CBus *cbus_init(qemu_irq dat_out);
+void cbus_attach(CBus *bus, void *slave_opaque);
+
+void *retu_init(qemu_irq irq, int vilma);
+void *tahvo_init(qemu_irq irq, int betty);
+
+void retu_key_event(void *retu, int state);
+
+#endif
--
2.17.2
[Qemu-devel] [PATCH 08/16] MAINTAINERS: Add missing entries for the TI touchscreen devices
Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f571b29077..03872552ee 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -640,6 +640,7 @@ M: Peter Maydell L: qemu-...@nongnu.org S: Odd Fixes F: hw/arm/nseries.c +F: hw/input/tsc2*.c F: include/hw/display/blizzard.h F: include/hw/misc/cbus.h @@ -649,6 +650,7 @@ M: Peter Maydell L: qemu-...@nongnu.org S: Odd Fixes F: hw/arm/palm.c +F: hw/input/tsc2*.c Raspberry Pi M: Peter Maydell -- 2.17.2
[Qemu-devel] [PATCH 03/16] hw/devices: Remove unused TC6393XB_RAM definition
Introduced in 64b40bc54a9, this definition is no more used since a0b753dfd39. Remove it. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/devices.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/hw/devices.h b/include/hw/devices.h index 0e27feb0c2..4019b3be17 100644 --- a/include/hw/devices.h +++ b/include/hw/devices.h @@ -51,7 +51,6 @@ void retu_key_event(void *retu, int state); /* tc6393xb.c */ typedef struct TC6393xbState TC6393xbState; -#define TC6393XB_RAM 0x11 /* amount of ram for Video and USB */ TC6393xbState *tc6393xb_init(struct MemoryRegion *sysmem, uint32_t base, qemu_irq irq); void tc6393xb_gpio_out_set(TC6393xbState *s, int line, -- 2.17.2
[Qemu-devel] [PATCH 02/16] hw: Remove unused 'hw/devices.h' include
Signed-off-by: Philippe Mathieu-Daudé --- hw/alpha/typhoon.c | 1 - hw/arm/allwinner-a10.c | 1 - hw/arm/collie.c | 1 - hw/arm/cubieboard.c | 1 - hw/arm/highbank.c| 1 - hw/arm/mps2-tz.c | 1 - hw/arm/musicpal.c| 1 - hw/arm/nrf51_soc.c | 1 - hw/arm/spitz.c | 1 - hw/arm/virt.c| 1 - hw/arm/z2.c | 1 - hw/display/sm501.c | 1 - hw/hppa/dino.c | 1 - hw/intc/allwinner-a10-pic.c | 1 - hw/lm32/lm32_boards.c| 1 - hw/lm32/milkymist.c | 1 - hw/microblaze/petalogix_ml605_mmu.c | 1 - hw/microblaze/petalogix_s3adsp1800_mmu.c | 1 - hw/net/dp8393x.c | 1 - hw/ppc/virtex_ml507.c| 1 - hw/sh4/r2d.c | 1 - hw/tricore/tricore_testboard.c | 1 - hw/usb/tusb6010.c| 1 - 23 files changed, 23 deletions(-) diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index 8004afe45b..90aa71eb01 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -11,7 +11,6 @@ #include "qapi/error.h" #include "cpu.h" #include "hw/hw.h" -#include "hw/devices.h" #include "sysemu/sysemu.h" #include "alpha_sys.h" #include "exec/address-spaces.h" diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index 9fe875cdb5..8c07086a01 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -20,7 +20,6 @@ #include "qemu-common.h" #include "cpu.h" #include "hw/sysbus.h" -#include "hw/devices.h" #include "hw/arm/allwinner-a10.h" static void aw_a10_init(Object *obj) diff --git a/hw/arm/collie.c b/hw/arm/collie.c index 48b732c176..3ca4e078fe 100644 --- a/hw/arm/collie.c +++ b/hw/arm/collie.c @@ -12,7 +12,6 @@ #include "hw/hw.h" #include "hw/sysbus.h" #include "hw/boards.h" -#include "hw/devices.h" #include "strongarm.h" #include "hw/arm/arm.h" #include "hw/block/flash.h" diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index 32f1edd2fa..84187d3916 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -20,7 +20,6 @@ #include "qemu-common.h" #include "cpu.h" #include "hw/sysbus.h" -#include "hw/devices.h" #include "hw/boards.h" #include "hw/arm/allwinner-a10.h" diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index fb9efa02c3..96ccf18d86 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -21,7 +21,6 @@ #include "qapi/error.h" #include "hw/sysbus.h" #include "hw/arm/arm.h" -#include "hw/devices.h" #include "hw/loader.h" #include "net/net.h" #include "sysemu/kvm.h" diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 82b1d020a5..1232d6ff95 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -49,7 +49,6 @@ #include "hw/arm/iotkit.h" #include "hw/dma/pl080.h" #include "hw/ssi/pl022.h" -#include "hw/devices.h" #include "net/net.h" #include "hw/core/split-irq.h" diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index d22532a11c..de4a12e496 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -15,7 +15,6 @@ #include "cpu.h" #include "hw/sysbus.h" #include "hw/arm/arm.h" -#include "hw/devices.h" #include "net/net.h" #include "sysemu/sysemu.h" #include "hw/boards.h" diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index b89c1bdea0..d53b45a094 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -14,7 +14,6 @@ #include "hw/arm/arm.h" #include "hw/sysbus.h" #include "hw/boards.h" -#include "hw/devices.h" #include "hw/misc/unimp.h" #include "exec/address-spaces.h" #include "sysemu/sysemu.h" diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index c4bc3deedf..22f5958b9d 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -21,7 +21,6 @@ #include "hw/ssi/ssi.h" #include "hw/block/flash.h" #include "qemu/timer.h" -#include "hw/devices.h" #include "hw/arm/sharpsl.h" #include "ui/console.h" #include "hw/audio/wm8750.h" diff --git a/hw/arm/virt.c b/hw/arm/virt.c index c2641e56ea..f02d157be6 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -37,7 +37,6 @@ #include "hw/vfio/vfio-calxeda-xgmac.h" #include "hw/vfio/vfio-amd-xgbe.h" #include "hw/display/ramfb.h" -#include "hw/devices.h" #include "net/net.h" #include "sysemu/device_tree.h" #include "sysemu/numa.h" diff --git a/hw/arm/z2.c b/hw/arm/z2.c index 697a822f1e..7afa352a96 100644 --- a/hw/arm/z2.c +++ b/hw/arm/z2.c @@ -15,7 +15,6 @@ #include "hw/hw.h" #include "hw/arm/pxa.h" #include "hw/arm/arm.h" -#include "hw/devices.h" #include "hw/i2c/i2c.h" #include "hw/ssi/ssi.h" #include "hw/boards.h" diff --git a/hw/display/sm501.c b/hw/display/sm501.c index 4a8686f0f5..2122291308 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -32,7 +32,6 @@ #include "hw/hw.h" #include "hw/char/serial.h" #include "ui/console.h"
[Qemu-devel] [PATCH 01/16] hw/arm/aspeed: Use TYPE_TMP105/TYPE_PCA9552 instead of hardcoded string
Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/aspeed.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 5158985482..817f9e1400 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -19,6 +19,8 @@ #include "hw/arm/aspeed_soc.h" #include "hw/boards.h" #include "hw/i2c/smbus.h" +#include "hw/misc/pca9552.h" +#include "hw/misc/tmp105.h" #include "qemu/log.h" #include "sysemu/block-backend.h" #include "hw/loader.h" @@ -267,7 +269,8 @@ static void ast2500_evb_i2c_init(AspeedBoardState *bmc) eeprom_buf); /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ -i2c_create_slave(aspeed_i2c_get_bus(DEVICE(>i2c), 7), "tmp105", 0x4d); +i2c_create_slave(aspeed_i2c_get_bus(DEVICE(>i2c), 7), TYPE_TMP105, + 0x4d); /* The AST2500 EVB does not have an RTC. Let's pretend that one is * plugged on the I2C bus header */ @@ -288,13 +291,15 @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) AspeedSoCState *soc = >soc; uint8_t *eeprom_buf = g_malloc0(8 * 1024); -i2c_create_slave(aspeed_i2c_get_bus(DEVICE(>i2c), 3), "pca9552", 0x60); +i2c_create_slave(aspeed_i2c_get_bus(DEVICE(>i2c), 3), TYPE_PCA9552, + 0x60); i2c_create_slave(aspeed_i2c_get_bus(DEVICE(>i2c), 4), "tmp423", 0x4c); i2c_create_slave(aspeed_i2c_get_bus(DEVICE(>i2c), 5), "tmp423", 0x4c); /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ -i2c_create_slave(aspeed_i2c_get_bus(DEVICE(>i2c), 9), "tmp105", 0x4a); +i2c_create_slave(aspeed_i2c_get_bus(DEVICE(>i2c), 9), TYPE_TMP105, + 0x4a); /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is * good enough */ @@ -302,7 +307,7 @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(>i2c), 11), 0x51, eeprom_buf); -i2c_create_slave(aspeed_i2c_get_bus(DEVICE(>i2c), 11), "pca9552", +i2c_create_slave(aspeed_i2c_get_bus(DEVICE(>i2c), 11), TYPE_PCA9552, 0x60); } -- 2.17.2
[Qemu-devel] [PATCH 00/16] hw: Remove "hw/devices.h"
Hi, As the first comment describes, the "hw/devices.h" contains declarations for "Devices that have nowhere better to go." This series remove it, creating new headers for devices covered there. MAINTAINERS is updated. I also included 2 cleanups while working on this, in "qemu/typedefs.h" and "hw/net/ne2000-isa.h" header guard. Please review. Phil. Philippe Mathieu-Daudé (16): hw/arm/aspeed: Use TYPE_TMP105/TYPE_PCA9552 instead of hardcoded string hw: Remove unused 'hw/devices.h' include hw/devices: Remove unused TC6393XB_RAM definition hw/devices: Move TC6393XB declarations into a new header hw/devices: Move Blizzard declarations into a new header hw/devices: Move CBus declarations into a new header hw/devices: Move Gamepad declarations into a new header MAINTAINERS: Add missing entries for the TI touchscreen devices hw/devices: Move TI touchscreen declarations into a new header typedefs: Remove MouseTransformInfo typedefs: Remove PS2State hw/devices: Move LAN9118 declarations into a new header hw/net/ne2000-isa: Add guards to the header hw/net/lan9118: Export TYPE_LAN9118 and use it instead of hardcoded string hw/devices: Move SMSC 91C111 declaration into a new header RFC hw/net/smc91c111: Convert init helper into an inline function MAINTAINERS | 8 +++ hw/alpha/typhoon.c | 1 - hw/arm/allwinner-a10.c | 1 - hw/arm/aspeed.c | 13 +++-- hw/arm/collie.c | 1 - hw/arm/cubieboard.c | 1 - hw/arm/exynos4_boards.c | 3 +- hw/arm/gumstix.c | 2 +- hw/arm/highbank.c| 1 - hw/arm/integratorcp.c| 2 +- hw/arm/kzm.c | 2 +- hw/arm/mainstone.c | 2 +- hw/arm/mps2-tz.c | 4 +- hw/arm/mps2.c| 2 +- hw/arm/musicpal.c| 1 - hw/arm/nrf51_soc.c | 1 - hw/arm/nseries.c | 4 +- hw/arm/palm.c| 2 +- hw/arm/realview.c| 3 +- hw/arm/spitz.c | 1 - hw/arm/stellaris.c | 2 +- hw/arm/tosa.c| 2 +- hw/arm/versatilepb.c | 2 +- hw/arm/vexpress.c| 2 +- hw/arm/virt.c| 1 - hw/arm/z2.c | 1 - hw/display/blizzard.c| 2 +- hw/display/sm501.c | 1 - hw/display/tc6393xb.c| 2 +- hw/hppa/dino.c | 1 - hw/input/stellaris_input.c | 2 +- hw/input/tsc2005.c | 2 +- hw/input/tsc210x.c | 4 +- hw/intc/allwinner-a10-pic.c | 1 - hw/lm32/lm32_boards.c| 1 - hw/lm32/milkymist.c | 1 - hw/microblaze/petalogix_ml605_mmu.c | 1 - hw/microblaze/petalogix_s3adsp1800_mmu.c | 1 - hw/misc/cbus.c | 2 +- hw/net/dp8393x.c | 1 - hw/net/lan9118.c | 3 +- hw/net/smc91c111.c | 19 +--- hw/ppc/virtex_ml507.c| 1 - hw/sh4/r2d.c | 1 - hw/tricore/tricore_testboard.c | 1 - hw/usb/tusb6010.c| 1 - include/hw/arm/omap.h| 6 +-- include/hw/devices.h | 62 include/hw/display/blizzard.h| 21 include/hw/display/tc6393xb.h| 25 ++ include/hw/input/gamepad.h | 11 + include/hw/input/ps2.h | 2 + include/hw/input/ti_uwire_tsc.h | 28 +++ include/hw/misc/cbus.h | 31 include/hw/net/lan9118.h | 23 + include/hw/net/ne2000-isa.h | 6 +++ include/hw/net/smc91c111.h | 41 include/qemu/typedefs.h | 3 -- include/ui/console.h | 4 +- 59 files changed, 236 insertions(+), 140 deletions(-) delete mode 100644 include/hw/devices.h create mode 100644 include/hw/display/blizzard.h create mode 100644 include/hw/display/tc6393xb.h create mode 100644 include/hw/input/gamepad.h create mode 100644 include/hw/input/ti_uwire_tsc.h create mode 100644 include/hw/misc/cbus.h create mode 100644 include/hw/net/lan9118.h create mode 100644 include/hw/net/smc91c111.h -- 2.17.2
[Qemu-devel] [PULL 26/28] qdev-props: call object_apply_global_props()
It's now possible to use the common function.
Teach object_apply_global_props() to warn if Error argument is NULL.
Signed-off-by: Marc-André Lureau
Reviewed-by: Igor Mammedov
Reviewed-by: Cornelia Huck
Acked-by: Eduardo Habkost
---
hw/core/qdev-properties.c | 24 ++--
qom/object.c | 12 +++-
2 files changed, 13 insertions(+), 23 deletions(-)
diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c
index 5f9046b84a..5da1439a8b 100644
--- a/hw/core/qdev-properties.c
+++ b/hw/core/qdev-properties.c
@@ -1223,28 +1223,8 @@ int qdev_prop_check_globals(void)
void qdev_prop_set_globals(DeviceState *dev)
{
-int i;
-
-for (i = 0; i < global_props()->len; i++) {
-GlobalProperty *prop;
-Error *err = NULL;
-
-prop = g_ptr_array_index(global_props(), i);
-if (object_dynamic_cast(OBJECT(dev), prop->driver) == NULL) {
-continue;
-}
-prop->used = true;
-object_property_parse(OBJECT(dev), prop->value, prop->property, );
-if (err != NULL) {
-error_prepend(, "can't apply global %s.%s=%s: ",
- prop->driver, prop->property, prop->value);
-if (!dev->hotplugged) {
-error_propagate(_fatal, err);
-} else {
-warn_report_err(err);
-}
-}
-}
+object_apply_global_props(OBJECT(dev), global_props(),
+ dev->hotplugged ? NULL : _fatal);
}
/* --- 64bit unsigned int 'size' type --- */
diff --git a/qom/object.c b/qom/object.c
index dbdab0aead..aa6f3a2a71 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -390,7 +390,17 @@ void object_apply_global_props(Object *obj, const
GPtrArray *props, Error **errp
if (err != NULL) {
error_prepend(, "can't apply global %s.%s=%s: ",
p->driver, p->property, p->value);
-error_propagate(errp, err);
+/*
+ * If errp != NULL, propagate error and return.
+ * If errp == NULL, report a warning, but keep going
+ * with the remaining globals.
+ */
+if (errp) {
+error_propagate(errp, err);
+return;
+} else {
+warn_report_err(err);
+}
}
}
}
--
2.20.1.2.gb21ebb671b
Re: [Qemu-devel] [PATCH] compat: Use explicit type names on HW_COMPAT_2_6
On Fri, Jan 04, 2019 at 10:12:00AM +, Dr. David Alan Gilbert wrote:
> * Michael S. Tsirkin (m...@redhat.com) wrote:
> > On Fri, Jan 04, 2019 at 01:22:26AM -0200, Eduardo Habkost wrote:
> > > The virtio-pci entries in HW_COMPAT_2_6 had an implicit
> > > assumption: that all virtio-pci subclasses support the
> > > disable-legacy and disable-modern options.
> > >
> > > That assumption was broken by commit f6e501a28ef9 ("virtio:
> > > Provide version-specific variants of virtio PCI devices"). This
> > > caused QEMU to crash if using the new -non-transitional or
> > > -transitional device types:
> > >
> > > $ qemu-system-x86_64 -machine pc-i440fx-2.6 \
> > > -device virtio-net-pci-non-transitional
> > > Unexpected error in object_property_find() at qom/object.c:1092:
> > > qemu-system-x86_64: -device virtio-net-pci-non-transitional: can't
> > > apply \
> > > global virtio-pci.disable-modern=on: Property '.disable-modern' not
> > > found
> > > Aborted (core dumped)
> > >
> > > Replace the virtio-pci.disable-legacy=off and
> > > virtio-pci.disable-modern=on entries on HW_COMPAT_2_6 with
> > > explicit entries for each generic virtio device type.
> > >
> > > The full list of generic virtio device types was extracted by
> > > just grepping for ".generic_name". Note that we don't need to
> > > worry about listing new virtio-pci devices in HW_COMPAT_2_6 in
> > > the future, because new devices won't require QEMU 2.6
> > > compatibility.
> >
> > I fully expect that e.g. packed ring support will need
> > to affect all virtio devices too. And it's likely
> > that we'll have some new virtio-pci transport features too.
> >
> > > This makes the compat entries annoyingly verbose, but is simpler
> > > than the alternative of making the virtio-pci type inheritance
> > > rules even more complex.
> >
> > God forbid we forgot something, the only way to notice is to
> > run a cross version migration with an old qemu.
> > I think we need to come up with something less verbose and fragile.
>
> I guess we could use a script like tests/acceptance/virtio_version.py to
> do a check?
That's a good idea. On test code we can try additional tricks to
detect the hybrid virtio devices without increasing the
complexity of QEMU code. I'll give it a try.
>
> As for something less verbose, I guess something is doable with a few
> macros (more complex but less verbose); or I guess you could add these
> properties to the other devices but just refuse to operate when they
> were set the wrong way.
Adding the properties to all virtio-pci devices is the kind of
complexity I would like to avoid. If we need to define rules for
when disable-modern/disable-legacy is set to unexpected values,
we'll have to maintain the code that implement those rules
forever.
--
Eduardo
[Qemu-devel] [PULL 18/28] compat: replace PC_COMPAT_2_2 & HW_COMPAT_2_2 macros
Use static arrays instead. I decided to rename the conflicting
pc_compat_2_2() function with pc_compat_2_2_fn().
Suggested-by: Eduardo Habkost
Signed-off-by: Marc-André Lureau
Reviewed-by: Igor Mammedov
Reviewed-by: Cornelia Huck
Acked-by: Eduardo Habkost
---
include/hw/boards.h | 3 ++
include/hw/compat.h | 3 --
include/hw/i386/pc.h | 97 ++--
hw/core/machine.c| 3 ++
hw/i386/pc.c | 95 +++
hw/i386/pc_piix.c| 12 +++---
hw/ppc/spapr.c | 2 +-
7 files changed, 110 insertions(+), 105 deletions(-)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index e7e3d2bc3c..2d82d80107 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -324,4 +324,7 @@ extern const size_t hw_compat_2_4_len;
extern GlobalProperty hw_compat_2_3[];
extern const size_t hw_compat_2_3_len;
+extern GlobalProperty hw_compat_2_2[];
+extern const size_t hw_compat_2_2_len;
+
#endif
diff --git a/include/hw/compat.h b/include/hw/compat.h
index fbe64d5983..3bd91908e4 100644
--- a/include/hw/compat.h
+++ b/include/hw/compat.h
@@ -1,9 +1,6 @@
#ifndef HW_COMPAT_H
#define HW_COMPAT_H
-#define HW_COMPAT_2_2 \
-/* empty */
-
#define HW_COMPAT_2_1 \
{\
.driver = "intel-hda",\
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index def40cd545..49b45bb79d 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -330,6 +330,9 @@ extern const size_t pc_compat_2_4_len;
extern GlobalProperty pc_compat_2_3[];
extern const size_t pc_compat_2_3_len;
+extern GlobalProperty pc_compat_2_2[];
+extern const size_t pc_compat_2_2_len;
+
/* Helper for setting model-id for CPU models that changed model-id
* depending on QEMU versions up to QEMU 2.4.
*/
@@ -350,100 +353,6 @@ extern const size_t pc_compat_2_3_len;
.value= "QEMU Virtual CPU version " v,\
},
-#define PC_COMPAT_2_2 \
-HW_COMPAT_2_2 \
-PC_CPU_MODEL_IDS("2.2.0") \
-{\
-.driver = "kvm64" "-" TYPE_X86_CPU,\
-.property = "vme",\
-.value = "off",\
-},\
-{\
-.driver = "kvm32" "-" TYPE_X86_CPU,\
-.property = "vme",\
-.value = "off",\
-},\
-{\
-.driver = "Conroe" "-" TYPE_X86_CPU,\
-.property = "vme",\
-.value = "off",\
-},\
-{\
-.driver = "Penryn" "-" TYPE_X86_CPU,\
-.property = "vme",\
-.value = "off",\
-},\
-{\
-.driver = "Nehalem" "-" TYPE_X86_CPU,\
-.property = "vme",\
-.value = "off",\
-},\
-{\
-.driver = "Westmere" "-" TYPE_X86_CPU,\
-.property = "vme",\
-.value = "off",\
-},\
-{\
-.driver = "SandyBridge" "-" TYPE_X86_CPU,\
-.property = "vme",\
-.value = "off",\
-},\
-{\
-.driver = "Haswell" "-" TYPE_X86_CPU,\
-.property = "vme",\
-.value = "off",\
-},\
-{\
-.driver = "Broadwell" "-" TYPE_X86_CPU,\
-.property = "vme",\
-.value = "off",\
-},\
-{\
-.driver = "Opteron_G1" "-" TYPE_X86_CPU,\
-.property = "vme",\
-.value = "off",\
-},\
-{\
-.driver = "Opteron_G2" "-" TYPE_X86_CPU,\
-.property = "vme",\
-.value = "off",\
-},\
-{\
-.driver = "Opteron_G3" "-" TYPE_X86_CPU,\
-.property = "vme",\
-.value = "off",\
-},\
-{\
-.driver = "Opteron_G4" "-" TYPE_X86_CPU,\
-.property = "vme",\
-.value = "off",\
-},\
-{\
-.driver = "Opteron_G5" "-" TYPE_X86_CPU,\
-.property = "vme",\
-.value = "off",\
-},\
-{\
-.driver = "Haswell" "-" TYPE_X86_CPU,\
-.property = "f16c",\
-.value = "off",\
-},\
-{\
-.driver = "Haswell" "-" TYPE_X86_CPU,\
-.property = "rdrand",\
-.value = "off",\
-},\
-{\
-.driver = "Broadwell" "-" TYPE_X86_CPU,\
-.property = "f16c",\
-.value = "off",\
-},\
-{\
-.driver = "Broadwell" "-" TYPE_X86_CPU,\
-.property = "rdrand",\
-.value = "off",\
-},
-
#define PC_COMPAT_2_1 \
HW_COMPAT_2_1 \
PC_CPU_MODEL_IDS("2.1.0") \
diff --git a/hw/core/machine.c b/hw/core/machine.c
index d37cdc3153..cfa9a5d95f 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -306,6 +306,9 @@ GlobalProperty hw_compat_2_3[] = {
};
const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3);
+GlobalProperty hw_compat_2_2[] = {};
+const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2);
+
static char *machine_get_accel(Object *obj, Error **errp)
{
MachineState *ms = MACHINE(obj);
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 1f6d7809ce..b92d1900da 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -441,6 +441,101 @@ GlobalProperty pc_compat_2_3[] = {
};
const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
+GlobalProperty
Re: [Qemu-devel] [PULL v3 00/44] MIPS pull request for December 2018 - v3
> Applied, thanks. > > Please update the changelog at https://wiki.qemu.org/ChangeLog/4.0 > for any user-visible changes. I updated the change log with a single item, as I mentioned in the pull request cover letter: https://wiki.qemu.org/ChangeLog/4.0#MIPS Thanks, Aleksandar > -- PMM
[Qemu-devel] [PULL 25/28] qdev-props: remove errp from GlobalProperty
All qdev_prop_register_global() set _fatal for errp, except
'-rtc driftfix=slew', which arguably should also use _fatal, as
otherwise failing to apply the property would only report a warning.
Signed-off-by: Marc-André Lureau
Reviewed-by: Igor Mammedov
Reviewed-by: Cornelia Huck
Acked-by: Eduardo Habkost
---
include/hw/qdev-core.h| 8 ++--
hw/core/qdev-properties.c | 4 ++--
qom/cpu.c | 1 -
target/i386/cpu.c | 1 -
target/sparc/cpu.c| 1 -
vl.c | 1 -
6 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index 86b05baeeb..bc014c1c9f 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -250,18 +250,14 @@ struct PropertyInfo {
/**
* GlobalProperty:
* @used: Set to true if property was used when initializing a device.
- * @errp: Error destination, used like first argument of error_setg()
- *in case property setting fails later. If @errp is NULL, we
- *print warnings instead of ignoring errors silently. For
- *hotplugged devices, errp is always ignored and warnings are
- *printed instead.
+ *
+ * An error is fatal for non-hotplugged devices, when the global is applied.
*/
typedef struct GlobalProperty {
const char *driver;
const char *property;
const char *value;
bool used;
-Error **errp;
} GlobalProperty;
static inline void
diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c
index fa47f39584..5f9046b84a 100644
--- a/hw/core/qdev-properties.c
+++ b/hw/core/qdev-properties.c
@@ -1238,8 +1238,8 @@ void qdev_prop_set_globals(DeviceState *dev)
if (err != NULL) {
error_prepend(, "can't apply global %s.%s=%s: ",
prop->driver, prop->property, prop->value);
-if (!dev->hotplugged && prop->errp) {
-error_propagate(prop->errp, err);
+if (!dev->hotplugged) {
+error_propagate(_fatal, err);
} else {
warn_report_err(err);
}
diff --git a/qom/cpu.c b/qom/cpu.c
index 9ad1372d57..5442a7323b 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -312,7 +312,6 @@ static void cpu_common_parse_features(const char *typename,
char *features,
prop->driver = typename;
prop->property = g_strdup(featurestr);
prop->value = g_strdup(val);
-prop->errp = _fatal;
qdev_prop_register_global(prop);
} else {
error_setg(errp, "Expected key=value format, found %s.",
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 677a3bd5fb..fa37203d89 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3568,7 +3568,6 @@ static void x86_cpu_parse_featurestr(const char
*typename, char *features,
prop->driver = typename;
prop->property = g_strdup(name);
prop->value = g_strdup(val);
-prop->errp = _fatal;
qdev_prop_register_global(prop);
}
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 0f090ece54..4a4445bdf5 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -111,7 +111,6 @@ cpu_add_feat_as_prop(const char *typename, const char
*name, const char *val)
prop->driver = typename;
prop->property = g_strdup(name);
prop->value = g_strdup(val);
-prop->errp = _fatal;
qdev_prop_register_global(prop);
}
diff --git a/vl.c b/vl.c
index 18b3b5727c..03438cd886 100644
--- a/vl.c
+++ b/vl.c
@@ -2965,7 +2965,6 @@ static int global_init_func(void *opaque, QemuOpts *opts,
Error **errp)
g->driver = qemu_opt_get(opts, "driver");
g->property = qemu_opt_get(opts, "property");
g->value= qemu_opt_get(opts, "value");
-g->errp = _fatal;
qdev_prop_register_global(g);
return 0;
}
--
2.20.1.2.gb21ebb671b
[Qemu-devel] [PULL 28/28] hostmem: use object id for memory region name with >= 4.0
hostmem-file and hostmem-memfd use the whole object path for the
memory region name, and hostname-ram uses only the path component (the
object id, or canonical path basename):
qemu -m 1024 -object memory-backend-file,id=mem,size=1G,mem-path=/tmp/foo -numa
node,memdev=mem -monitor stdio
(qemu) info ramblock
Block NamePSize Offset Used
Total
/objects/mem4 KiB 0x 0x4000
0x4000
qemu -m 1024 -object memory-backend-memfd,id=mem,size=1G -numa node,memdev=mem
-monitor stdio
(qemu) info ramblock
Block NamePSize Offset Used
Total
/objects/mem4 KiB 0x 0x4000
0x4000
qemu -m 1024 -object memory-backend-ram,id=mem,size=1G -numa node,memdev=mem
-monitor stdio
(qemu) info ramblock
Block NamePSize Offset Used
Total
mem4 KiB 0x 0x4000
0x4000
For consistency, change to use object id for -file and -memfd as well
with >= 4.0.
Having a consistent naming allows to migrate to different hostmem
backends.
Signed-off-by: Marc-André Lureau
Reviewed-by: Igor Mammedov
Acked-by: Eduardo Habkost
---
include/sysemu/hostmem.h | 3 ++-
backends/hostmem-file.c | 8
backends/hostmem-memfd.c | 2 +-
backends/hostmem-ram.c | 9 -
backends/hostmem.c | 36
hw/core/machine.c| 8
6 files changed, 55 insertions(+), 11 deletions(-)
diff --git a/include/sysemu/hostmem.h b/include/sysemu/hostmem.h
index 6e6bd2c1cb..a023b372a4 100644
--- a/include/sysemu/hostmem.h
+++ b/include/sysemu/hostmem.h
@@ -53,7 +53,7 @@ struct HostMemoryBackend {
/* protected */
uint64_t size;
-bool merge, dump;
+bool merge, dump, use_canonical_path;
bool prealloc, force_prealloc, is_mapped, share;
DECLARE_BITMAP(host_nodes, MAX_NODES + 1);
HostMemPolicy policy;
@@ -67,5 +67,6 @@ MemoryRegion
*host_memory_backend_get_memory(HostMemoryBackend *backend);
void host_memory_backend_set_mapped(HostMemoryBackend *backend, bool mapped);
bool host_memory_backend_is_mapped(HostMemoryBackend *backend);
size_t host_memory_backend_pagesize(HostMemoryBackend *memdev);
+char *host_memory_backend_get_name(HostMemoryBackend *backend);
#endif
diff --git a/backends/hostmem-file.c b/backends/hostmem-file.c
index 78f058dee2..7a34e25c43 100644
--- a/backends/hostmem-file.c
+++ b/backends/hostmem-file.c
@@ -43,7 +43,7 @@ file_backend_memory_alloc(HostMemoryBackend *backend, Error
**errp)
{
HostMemoryBackendFile *fb = MEMORY_BACKEND_FILE(backend);
#ifdef CONFIG_POSIX
-gchar *path;
+gchar *name;
#endif
if (!backend->size) {
@@ -58,14 +58,14 @@ file_backend_memory_alloc(HostMemoryBackend *backend, Error
**errp)
error_setg(errp, "-mem-path not supported on this host");
#else
backend->force_prealloc = mem_prealloc;
-path = object_get_canonical_path(OBJECT(backend));
+name = host_memory_backend_get_name(backend);
memory_region_init_ram_from_file(>mr, OBJECT(backend),
- path,
+ name,
backend->size, fb->align,
(backend->share ? RAM_SHARED : 0) |
(fb->is_pmem ? RAM_PMEM : 0),
fb->mem_path, errp);
-g_free(path);
+g_free(name);
#endif
}
diff --git a/backends/hostmem-memfd.c b/backends/hostmem-memfd.c
index 2eb9c827a5..98c9bf3240 100644
--- a/backends/hostmem-memfd.c
+++ b/backends/hostmem-memfd.c
@@ -53,7 +53,7 @@ memfd_backend_memory_alloc(HostMemoryBackend *backend, Error
**errp)
return;
}
-name = object_get_canonical_path(OBJECT(backend));
+name = host_memory_backend_get_name(backend);
memory_region_init_ram_from_fd(>mr, OBJECT(backend),
name, backend->size,
backend->share, fd, errp);
diff --git a/backends/hostmem-ram.c b/backends/hostmem-ram.c
index 7ddd08d370..24b65d9ae3 100644
--- a/backends/hostmem-ram.c
+++ b/backends/hostmem-ram.c
@@ -16,21 +16,20 @@
#define TYPE_MEMORY_BACKEND_RAM "memory-backend-ram"
-
static void
ram_backend_memory_alloc(HostMemoryBackend *backend, Error **errp)
{
-char *path;
+char *name;
if (!backend->size) {
error_setg(errp, "can't create backend with size 0");
return;
}
-path = object_get_canonical_path_component(OBJECT(backend));
-memory_region_init_ram_shared_nomigrate(>mr, OBJECT(backend),
path,
+name = host_memory_backend_get_name(backend);
+memory_region_init_ram_shared_nomigrate(>mr, OBJECT(backend),
name,
[Qemu-devel] [PULL 20/28] include: remove compat.h
The header is now empty. Signed-off-by: Marc-André Lureau Reviewed-by: Igor Mammedov Reviewed-by: Cornelia Huck Acked-by: Eduardo Habkost --- include/hw/compat.h| 4 include/hw/i386/pc.h | 1 - hw/arm/virt.c | 1 - hw/ppc/spapr.c | 1 - hw/s390x/s390-virtio-ccw.c | 1 - 5 files changed, 8 deletions(-) delete mode 100644 include/hw/compat.h diff --git a/include/hw/compat.h b/include/hw/compat.h deleted file mode 100644 index b2d0bdd599..00 --- a/include/hw/compat.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef HW_COMPAT_H -#define HW_COMPAT_H - -#endif /* HW_COMPAT_H */ diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 784ea7a92c..6b7bf334cd 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -13,7 +13,6 @@ #include "qemu/bitmap.h" #include "sysemu/sysemu.h" #include "hw/pci/pci.h" -#include "hw/compat.h" #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" #include "hw/acpi/acpi_dev_interface.h" diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d3174f1402..99c2b6e60d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -43,7 +43,6 @@ #include "sysemu/numa.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" -#include "hw/compat.h" #include "hw/loader.h" #include "exec/address-spaces.h" #include "qemu/bitops.h" diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 8aba66a32f..5671608cea 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -70,7 +70,6 @@ #include "hw/nmi.h" #include "hw/intc/intc.h" -#include "hw/compat.h" #include "qemu/cutils.h" #include "hw/ppc/spapr_cpu_core.h" #include "hw/mem/memory-device.h" diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index bf5f2f463c..c737507053 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -28,7 +28,6 @@ #include "hw/s390x/storage-keys.h" #include "hw/s390x/storage-attributes.h" #include "hw/s390x/event-facility.h" -#include "hw/compat.h" #include "ipl.h" #include "hw/s390x/s390-virtio-ccw.h" #include "hw/s390x/css-bridge.h" -- 2.20.1.2.gb21ebb671b
[Qemu-devel] [PULL 16/28] compat: replace PC_COMPAT_2_4 & HW_COMPAT_2_4 macros
Use static arrays instead.
Suggested-by: Eduardo Habkost
Signed-off-by: Marc-André Lureau
Reviewed-by: Igor Mammedov
Reviewed-by: Cornelia Huck
Acked-by: Eduardo Habkost
---
include/hw/boards.h| 3 ++
include/hw/compat.h| 27 --
include/hw/i386/pc.h | 74 ++
hw/core/machine.c | 29 +++
hw/i386/pc.c | 71
hw/i386/pc_piix.c | 6 ++--
hw/i386/pc_q35.c | 6 ++--
hw/ppc/spapr.c | 5 +--
hw/s390x/s390-virtio-ccw.c | 2 +-
9 files changed, 112 insertions(+), 111 deletions(-)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 0023b72b02..254b7d8919 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -318,4 +318,7 @@ extern const size_t hw_compat_2_6_len;
extern GlobalProperty hw_compat_2_5[];
extern const size_t hw_compat_2_5_len;
+extern GlobalProperty hw_compat_2_4[];
+extern const size_t hw_compat_2_4_len;
+
#endif
diff --git a/include/hw/compat.h b/include/hw/compat.h
index a6eced34c6..05ff05e159 100644
--- a/include/hw/compat.h
+++ b/include/hw/compat.h
@@ -1,33 +1,6 @@
#ifndef HW_COMPAT_H
#define HW_COMPAT_H
-#define HW_COMPAT_2_4 \
-{\
-.driver = "virtio-blk-device",\
-.property = "scsi",\
-.value= "true",\
-},{\
-.driver = "e1000",\
-.property = "extra_mac_registers",\
-.value= "off",\
-},{\
-.driver = "virtio-pci",\
-.property = "x-disable-pcie",\
-.value= "on",\
-},{\
-.driver = "virtio-pci",\
-.property = "migrate-extra",\
-.value= "off",\
-},{\
-.driver = "fw_cfg_mem",\
-.property = "dma_enabled",\
-.value= "off",\
-},{\
-.driver = "fw_cfg_io",\
-.property = "dma_enabled",\
-.value= "off",\
-},
-
#define HW_COMPAT_2_3 \
{\
.driver = "virtio-blk-pci",\
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 9a32031f25..a9045f6bea 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -324,6 +324,9 @@ extern const size_t pc_compat_2_6_len;
extern GlobalProperty pc_compat_2_5[];
extern const size_t pc_compat_2_5_len;
+extern GlobalProperty pc_compat_2_4[];
+extern const size_t pc_compat_2_4_len;
+
/* Helper for setting model-id for CPU models that changed model-id
* depending on QEMU versions up to QEMU 2.4.
*/
@@ -344,77 +347,6 @@ extern const size_t pc_compat_2_5_len;
.value= "QEMU Virtual CPU version " v,\
},
-#define PC_COMPAT_2_4 \
-HW_COMPAT_2_4 \
-PC_CPU_MODEL_IDS("2.4.0") \
-{\
-.driver = "Haswell-" TYPE_X86_CPU,\
-.property = "abm",\
-.value= "off",\
-},\
-{\
-.driver = "Haswell-noTSX-" TYPE_X86_CPU,\
-.property = "abm",\
-.value= "off",\
-},\
-{\
-.driver = "Broadwell-" TYPE_X86_CPU,\
-.property = "abm",\
-.value= "off",\
-},\
-{\
-.driver = "Broadwell-noTSX-" TYPE_X86_CPU,\
-.property = "abm",\
-.value= "off",\
-},\
-{\
-.driver = "host" "-" TYPE_X86_CPU,\
-.property = "host-cache-info",\
-.value= "on",\
-},\
-{\
-.driver = TYPE_X86_CPU,\
-.property = "check",\
-.value= "off",\
-},\
-{\
-.driver = "qemu64" "-" TYPE_X86_CPU,\
-.property = "sse4a",\
-.value= "on",\
-},\
-{\
-.driver = "qemu64" "-" TYPE_X86_CPU,\
-.property = "abm",\
-.value= "on",\
-},\
-{\
-.driver = "qemu64" "-" TYPE_X86_CPU,\
-.property = "popcnt",\
-.value= "on",\
-},\
-{\
-.driver = "qemu32" "-" TYPE_X86_CPU,\
-.property = "popcnt",\
-.value= "on",\
-},{\
-.driver = "Opteron_G2" "-" TYPE_X86_CPU,\
-.property = "rdtscp",\
-.value= "on",\
-},{\
-.driver = "Opteron_G3" "-" TYPE_X86_CPU,\
-.property = "rdtscp",\
-.value= "on",\
-},{\
-.driver = "Opteron_G4" "-" TYPE_X86_CPU,\
-.property = "rdtscp",\
-.value= "on",\
-},{\
-.driver = "Opteron_G5" "-" TYPE_X86_CPU,\
-.property = "rdtscp",\
-.value= "on",\
-},
-
-
#define PC_COMPAT_2_3 \
HW_COMPAT_2_3 \
PC_CPU_MODEL_IDS("2.3.0") \
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 4d05501775..1808900c3a 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -236,6 +236,35 @@ GlobalProperty hw_compat_2_5[] = {
};
const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5);
+GlobalProperty hw_compat_2_4[] = {
+{
+.driver = "virtio-blk-device",
+.property = "scsi",
+.value= "true",
+},{
+.driver = "e1000",
+
[Qemu-devel] [PULL 27/28] arm: replace instance_post_init()
Replace arm_cpu_post_init() instance callback by calling it from leaf
classes, to avoid potential ordering issue with other post_init callbacks.
Signed-off-by: Marc-André Lureau
Suggested-by: Igor Mammedov
Reviewed-by: Igor Mammedov
Acked-by: Eduardo Habkost
---
target/arm/cpu-qom.h | 3 +++
target/arm/cpu.h | 2 ++
target/arm/cpu.c | 30 --
target/arm/cpu64.c | 24
4 files changed, 49 insertions(+), 10 deletions(-)
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index d135ff8e06..2049fa9612 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -35,6 +35,8 @@ struct arm_boot_info;
#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
+typedef struct ARMCPUInfo ARMCPUInfo;
+
/**
* ARMCPUClass:
* @parent_realize: The parent class' realize handler.
@@ -47,6 +49,7 @@ typedef struct ARMCPUClass {
CPUClass parent_class;
/*< public >*/
+const ARMCPUInfo *info;
DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
} ARMCPUClass;
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c943f35dd9..3aedfeeaf1 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -884,6 +884,8 @@ static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
return container_of(env, ARMCPU, env);
}
+void arm_cpu_post_init(Object *obj);
+
uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index c8505eaaee..baf430c092 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -740,7 +740,7 @@ static Property arm_cpu_pmsav7_dregion_property =
static Property arm_cpu_initsvtor_property =
DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0);
-static void arm_cpu_post_init(Object *obj)
+void arm_cpu_post_init(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -1457,8 +1457,10 @@ static void cortex_m33_initfn(Object *obj)
static void arm_v7m_class_init(ObjectClass *oc, void *data)
{
+ARMCPUClass *acc = ARM_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
+acc->info = data;
#ifndef CONFIG_USER_ONLY
cc->do_interrupt = arm_v7m_cpu_do_interrupt;
#endif
@@ -1959,11 +1961,11 @@ static void arm_max_initfn(Object *obj)
#endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
-typedef struct ARMCPUInfo {
+struct ARMCPUInfo {
const char *name;
void (*initfn)(Object *obj);
void (*class_init)(ObjectClass *oc, void *data);
-} ARMCPUInfo;
+};
static const ARMCPUInfo arm_cpus[] = {
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
@@ -2113,6 +2115,7 @@ static void arm_host_initfn(Object *obj)
ARMCPU *cpu = ARM_CPU(obj);
kvm_arm_set_cpu_features_from_host(cpu);
+arm_cpu_post_init(ARM_CPU(obj));
}
static const TypeInfo host_arm_cpu_type_info = {
@@ -2127,14 +2130,30 @@ static const TypeInfo host_arm_cpu_type_info = {
#endif
+static void arm_cpu_instance_init(Object *obj)
+{
+ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
+
+acc->info->initfn(obj);
+arm_cpu_post_init(obj);
+}
+
+static void cpu_register_class_init(ObjectClass *oc, void *data)
+{
+ARMCPUClass *acc = ARM_CPU_CLASS(oc);
+
+acc->info = data;
+}
+
static void cpu_register(const ARMCPUInfo *info)
{
TypeInfo type_info = {
.parent = TYPE_ARM_CPU,
.instance_size = sizeof(ARMCPU),
-.instance_init = info->initfn,
+.instance_init = arm_cpu_instance_init,
.class_size = sizeof(ARMCPUClass),
-.class_init = info->class_init,
+.class_init = info->class_init ?: cpu_register_class_init,
+.class_data = (void *)info,
};
type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
@@ -2147,7 +2166,6 @@ static const TypeInfo arm_cpu_type_info = {
.parent = TYPE_CPU,
.instance_size = sizeof(ARMCPU),
.instance_init = arm_cpu_initfn,
-.instance_post_init = arm_cpu_post_init,
.instance_finalize = arm_cpu_finalizefn,
.abstract = true,
.class_size = sizeof(ARMCPUClass),
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 1d57be0c91..4b544a1c58 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -364,11 +364,11 @@ static void aarch64_max_initfn(Object *obj)
}
}
-typedef struct ARMCPUInfo {
+struct ARMCPUInfo {
const char *name;
void (*initfn)(Object *obj);
void (*class_init)(ObjectClass *oc, void *data);
-} ARMCPUInfo;
+};
static const ARMCPUInfo aarch64_cpus[] = {
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
@@ -452,14 +452,30 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void
*data)
cc->gdb_arch_name = aarch64_gdb_arch_name;
}
+static void aarch64_cpu_instance_init(Object *obj)
+{
+ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
+
+acc->info->initfn(obj);
+arm_cpu_post_init(obj);
+}
+
+static void cpu_register_class_init(ObjectClass *oc, void
[Qemu-devel] [PULL 19/28] compat: replace PC_COMPAT_2_1 & HW_COMPAT_2_1 macros
Use static arrays instead. I decided to rename the conflicting
pc_compat_2_1() function with pc_compat_2_1_fn().
Suggested-by: Eduardo Habkost
Signed-off-by: Marc-André Lureau
Reviewed-by: Igor Mammedov
Reviewed-by: Cornelia Huck
Acked-by: Eduardo Habkost
---
include/hw/boards.h | 3 +++
include/hw/compat.h | 31 ---
include/hw/i386/pc.h | 17 +++--
hw/core/machine.c| 33 +
hw/i386/pc.c | 15 +++
hw/i386/pc_piix.c| 12 +---
hw/ppc/spapr.c | 6 +-
7 files changed, 60 insertions(+), 57 deletions(-)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 2d82d80107..02f114085f 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -327,4 +327,7 @@ extern const size_t hw_compat_2_3_len;
extern GlobalProperty hw_compat_2_2[];
extern const size_t hw_compat_2_2_len;
+extern GlobalProperty hw_compat_2_1[];
+extern const size_t hw_compat_2_1_len;
+
#endif
diff --git a/include/hw/compat.h b/include/hw/compat.h
index 3bd91908e4..b2d0bdd599 100644
--- a/include/hw/compat.h
+++ b/include/hw/compat.h
@@ -1,35 +1,4 @@
#ifndef HW_COMPAT_H
#define HW_COMPAT_H
-#define HW_COMPAT_2_1 \
-{\
-.driver = "intel-hda",\
-.property = "old_msi_addr",\
-.value= "on",\
-},{\
-.driver = "VGA",\
-.property = "qemu-extended-regs",\
-.value= "off",\
-},{\
-.driver = "secondary-vga",\
-.property = "qemu-extended-regs",\
-.value= "off",\
-},{\
-.driver = "virtio-scsi-pci",\
-.property = "any_layout",\
-.value= "off",\
-},{\
-.driver = "usb-mouse",\
-.property = "usb_version",\
-.value= stringify(1),\
-},{\
-.driver = "usb-kbd",\
-.property = "usb_version",\
-.value= stringify(1),\
-},{\
-.driver = "virtio-pci",\
-.property = "virtio-pci-bus-master-bug-migration",\
-.value= "on",\
-},
-
#endif /* HW_COMPAT_H */
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 49b45bb79d..784ea7a92c 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -333,6 +333,9 @@ extern const size_t pc_compat_2_3_len;
extern GlobalProperty pc_compat_2_2[];
extern const size_t pc_compat_2_2_len;
+extern GlobalProperty pc_compat_2_1[];
+extern const size_t pc_compat_2_1_len;
+
/* Helper for setting model-id for CPU models that changed model-id
* depending on QEMU versions up to QEMU 2.4.
*/
@@ -353,20 +356,6 @@ extern const size_t pc_compat_2_2_len;
.value= "QEMU Virtual CPU version " v,\
},
-#define PC_COMPAT_2_1 \
-HW_COMPAT_2_1 \
-PC_CPU_MODEL_IDS("2.1.0") \
-{\
-.driver = "coreduo" "-" TYPE_X86_CPU,\
-.property = "vmx",\
-.value = "on",\
-},\
-{\
-.driver = "core2duo" "-" TYPE_X86_CPU,\
-.property = "vmx",\
-.value = "on",\
-},
-
#define PC_COMPAT_2_0 \
PC_CPU_MODEL_IDS("2.0.0") \
{\
diff --git a/hw/core/machine.c b/hw/core/machine.c
index cfa9a5d95f..84a4c8cdc3 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -309,6 +309,39 @@ const size_t hw_compat_2_3_len =
G_N_ELEMENTS(hw_compat_2_3);
GlobalProperty hw_compat_2_2[] = {};
const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2);
+GlobalProperty hw_compat_2_1[] = {
+{
+.driver = "intel-hda",
+.property = "old_msi_addr",
+.value= "on",
+},{
+.driver = "VGA",
+.property = "qemu-extended-regs",
+.value= "off",
+},{
+.driver = "secondary-vga",
+.property = "qemu-extended-regs",
+.value= "off",
+},{
+.driver = "virtio-scsi-pci",
+.property = "any_layout",
+.value= "off",
+},{
+.driver = "usb-mouse",
+.property = "usb_version",
+.value= stringify(1),
+},{
+.driver = "usb-kbd",
+.property = "usb_version",
+.value= stringify(1),
+},{
+.driver = "virtio-pci",
+.property = "virtio-pci-bus-master-bug-migration",
+.value= "on",
+},
+};
+const size_t hw_compat_2_1_len = G_N_ELEMENTS(hw_compat_2_1);
+
static char *machine_get_accel(Object *obj, Error **errp)
{
MachineState *ms = MACHINE(obj);
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index b92d1900da..731d2010c8 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -536,6 +536,21 @@ GlobalProperty pc_compat_2_2[] = {
};
const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
+GlobalProperty pc_compat_2_1[] = {
+PC_CPU_MODEL_IDS("2.1.0")
+{
+.driver = "coreduo" "-" TYPE_X86_CPU,
+.property = "vmx",
+.value = "on",
+},
+{
+.driver = "core2duo" "-" TYPE_X86_CPU,
+.property = "vmx",
+.value = "on",
+},
+};
+const size_t
