[PULL 0/7] target-arm queue

2024-03-25 Thread Peter Maydell 
It's been quiet on the arm front this week, so all I have is
these coverity fixes I posted a while back...

-- PMM

The following changes since commit 853546f8128476eefb701d4a55b2781bb3a46faa:

  Merge tag 'pull-loongarch-20240322' of https://gitlab.com/gaosong/qemu into 
staging (2024-03-22 10:59:57 +)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20240325

for you to fetch changes up to 55c79639d553c1b7a82b4cde781ad5f316f45b0e:

  tests/qtest/libqtest.c: Check for g_setenv() failure (2024-03-25 10:41:01 
+)


target-arm queue:
 * Fixes for seven minor coverity issues


Peter Maydell (7):
  tests/qtest/npcm7xx_emc_test: Don't leak cmd_line
  tests/unit/socket-helpers: Don't close(-1)
  net/af-xdp.c: Don't leak sock_fds array in net_init_af_xdp()
  hw/misc/pca9554: Correct error check bounds in get/set pin functions
  hw/nvram/mac_nvram: Report failure to write data
  tests/unit/test-throttle: Avoid unintended integer division
  tests/qtest/libqtest.c: Check for g_setenv() failure

 hw/misc/pca9554.c  | 4 ++--
 hw/nvram/mac_nvram.c   | 5 -
 net/af-xdp.c   | 3 +--
 tests/qtest/libqtest.c | 6 +-
 tests/qtest/npcm7xx_emc-test.c | 4 ++--
 tests/unit/socket-helpers.c| 4 +++-
 tests/unit/test-throttle.c | 4 ++--
 7 files changed, 19 insertions(+), 11 deletions(-)

Re: [PULL 0/7] target-arm queue

2023-07-17 Thread Richard Henderson 

On 7/17/23 13:47, Peter Maydell wrote:

A last small test of bug fixes before rc1.

thanks
-- PMM

The following changes since commit ed8ad9728a9c0eec34db9dff61dfa2f1dd625637:

   Merge tag 'pull-tpm-2023-07-14-1' ofhttps://github.com/stefanberger/qemu-tpm 
 into staging (2023-07-15 14:54:04 +0100)

are available in the Git repository at:

   https://git.linaro.org/people/pmaydell/qemu-arm.git  
tags/pull-target-arm-20230717

for you to fetch changes up to c2c1c4a35c7c2b1a4140b0942b9797c857e476a4:

   hw/nvram: Avoid unnecessary Xilinx eFuse backstore write (2023-07-17 
11:05:52 +0100)


target-arm queue:
  * hw/arm/sbsa-ref: set 'slots' property of xhci
  * linux-user: Remove pointless NULL check in clock_adjtime handling
  * ptw: Fix S1_ptw_translate() debug path
  * ptw: Account for FEAT_RME when applying {N}SW, SA bits
  * accel/tcg: Zero-pad PC in TCG CPU exec trace lines
  * hw/nvram: Avoid unnecessary Xilinx eFuse backstore write


Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/8.1 as 
appropriate.


r~

[PULL 0/7] target-arm queue

2023-07-17 Thread Peter Maydell 
A last small test of bug fixes before rc1.

thanks
-- PMM

The following changes since commit ed8ad9728a9c0eec34db9dff61dfa2f1dd625637:

  Merge tag 'pull-tpm-2023-07-14-1' of https://github.com/stefanberger/qemu-tpm 
into staging (2023-07-15 14:54:04 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20230717

for you to fetch changes up to c2c1c4a35c7c2b1a4140b0942b9797c857e476a4:

  hw/nvram: Avoid unnecessary Xilinx eFuse backstore write (2023-07-17 11:05:52 
+0100)


target-arm queue:
 * hw/arm/sbsa-ref: set 'slots' property of xhci
 * linux-user: Remove pointless NULL check in clock_adjtime handling
 * ptw: Fix S1_ptw_translate() debug path
 * ptw: Account for FEAT_RME when applying {N}SW, SA bits
 * accel/tcg: Zero-pad PC in TCG CPU exec trace lines
 * hw/nvram: Avoid unnecessary Xilinx eFuse backstore write


Peter Maydell (5):
  linux-user: Remove pointless NULL check in clock_adjtime handling
  target/arm/ptw.c: Add comments to S1Translate struct fields
  target/arm: Fix S1_ptw_translate() debug path
  target/arm/ptw.c: Account for FEAT_RME when applying {N}SW, SA bits
  accel/tcg: Zero-pad PC in TCG CPU exec trace lines

Tong Ho (1):
  hw/nvram: Avoid unnecessary Xilinx eFuse backstore write

Yuquan Wang (1):
  hw/arm/sbsa-ref: set 'slots' property of xhci

 accel/tcg/cpu-exec.c  |  4 +--
 accel/tcg/translate-all.c |  2 +-
 hw/arm/sbsa-ref.c |  1 +
 hw/nvram/xlnx-efuse.c | 11 --
 linux-user/syscall.c  | 12 +++
 target/arm/ptw.c  | 90 +--
 6 files changed, 98 insertions(+), 22 deletions(-)

Re: [PULL 0/7] target-arm queue

2022-11-07 Thread Stefan Hajnoczi 
Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any 
user-visible changes.


signature.asc
Description: PGP signature

[PULL 0/7] target-arm queue

2022-11-04 Thread Peter Maydell 
Hi; this pull request has a collection of bug fixes for rc0.
The big one is the trusted firmware boot regression fix.

thanks
-- PMM

The following changes since commit ece5f8374d0416a339f0c0a9399faa2c42d4ad6f:

  Merge tag 'linux-user-for-7.2-pull-request' of 
https://gitlab.com/laurent_vivier/qemu into staging (2022-11-03 10:55:05 -0400)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20221104

for you to fetch changes up to cead7fa4c06087c86c67c5ce815cc1ff0bfeac3a:

  target/arm: Two fixes for secure ptw (2022-11-04 10:58:58 +)


target-arm queue:
 * Fix regression booting Trusted Firmware
 * Honor HCR_E2H and HCR_TGE in ats_write64()
 * Copy the entire vector in DO_ZIP
 * Fix Privileged Access Never (PAN) for aarch32
 * Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLB
 * Set SCR_EL3.HXEn when direct booting kernel
 * Set SME and SVE EL3 vector lengths when direct booting kernel


Ake Koomsin (1):
  target/arm: Honor HCR_E2H and HCR_TGE in ats_write64()

Peter Maydell (3):
  hw/arm/boot: Set SME and SVE EL3 vector lengths when booting kernel
  hw/arm/boot: Set SCR_EL3.HXEn when booting kernel
  target/arm: Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLB

Richard Henderson (2):
  target/arm: Copy the entire vector in DO_ZIP
  target/arm: Two fixes for secure ptw

Timofey Kutergin (1):
  target/arm: Fix Privileged Access Never (PAN) for aarch32

 hw/arm/boot.c   |  5 
 target/arm/helper.c | 64 +
 target/arm/ptw.c| 50 --
 target/arm/sve_helper.c |  4 ++--
 4 files changed, 83 insertions(+), 40 deletions(-)

Re: [PULL 0/7] target-arm queue

2021-03-23 Thread Peter Maydell 
On Tue, 23 Mar 2021 at 14:26, Peter Maydell  wrote:
>
> Small pullreq with some bug fixes to go into rc1.
>
> -- PMM
>
> The following changes since commit 5ca634afcf83215a9a54ca6e66032325b5ffb5f6:
>
>   Merge remote-tracking branch 'remotes/philmd/tags/sdmmc-20210322' into 
> staging (2021-03-22 18:50:25 +)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20210323
>
> for you to fetch changes up to dad90de78e9e9d47cefcbcd30115706b98e6ec87:
>
>   target/arm: Set ARMMMUFaultInfo.level in user-only arm_cpu_tlb_fill 
> (2021-03-23 14:07:55 +)
>
> 
> target-arm queue:
>  * hw/arm/virt: Disable pl011 clock migration if needed
>  * target/arm: Make M-profile VTOR loads on reset handle memory aliasing
>  * target/arm: Set ARMMMUFaultInfo.level in user-only arm_cpu_tlb_fill
>
> 


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.

-- PMM

[PULL 0/7] target-arm queue

2021-03-23 Thread Peter Maydell 
Small pullreq with some bug fixes to go into rc1.

-- PMM

The following changes since commit 5ca634afcf83215a9a54ca6e66032325b5ffb5f6:

  Merge remote-tracking branch 'remotes/philmd/tags/sdmmc-20210322' into 
staging (2021-03-22 18:50:25 +)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20210323

for you to fetch changes up to dad90de78e9e9d47cefcbcd30115706b98e6ec87:

  target/arm: Set ARMMMUFaultInfo.level in user-only arm_cpu_tlb_fill 
(2021-03-23 14:07:55 +)


target-arm queue:
 * hw/arm/virt: Disable pl011 clock migration if needed
 * target/arm: Make M-profile VTOR loads on reset handle memory aliasing
 * target/arm: Set ARMMMUFaultInfo.level in user-only arm_cpu_tlb_fill


Gavin Shan (1):
  hw/arm/virt: Disable pl011 clock migration if needed

Peter Maydell (5):
  memory: Make flatview_cb return bool, not int
  memory: Document flatview_for_each_range()
  memory: Add offset_in_region to flatview_cb arguments
  hw/core/loader: Add new function rom_ptr_for_as()
  target/arm: Make M-profile VTOR loads on reset handle memory aliasing

Richard Henderson (1):
  target/arm: Set ARMMMUFaultInfo.level in user-only arm_cpu_tlb_fill

 include/exec/memory.h   | 32 +++---
 include/hw/char/pl011.h |  1 +
 include/hw/loader.h | 31 +
 hw/char/pl011.c |  9 +
 hw/core/loader.c| 75 +
 hw/core/machine.c   |  1 +
 softmmu/memory.c|  4 ++-
 target/arm/cpu.c|  2 +-
 target/arm/tlb_helper.c |  1 +
 tests/qtest/fuzz/generic_fuzz.c | 11 +++---
 10 files changed, 157 insertions(+), 10 deletions(-)

Re: [PULL 0/7] target-arm queue

2020-07-28 Thread Peter Maydell 
On Mon, 27 Jul 2020 at 16:19, Peter Maydell  wrote:
>
> Just some bugfixes this time around.
>
> -- PMM
>
> The following changes since commit 4215d3413272ad6d1c6c9d0234450b602e46a74c:
>
>   Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.1-20200727' 
> into staging (2020-07-27 09:33:04 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20200727
>
> for you to fetch changes up to d4f6dda182e19afa75706936805e18397cb95f07:
>
>   target/arm: Improve IMPDEF algorithm for IRG (2020-07-27 16:12:11 +0100)
>
> 
> target-arm queue:
>  * ACPI: Assert that we don't run out of the preallocated memory
>  * hw/misc/aspeed_sdmc: Fix incorrect memory size
>  * target/arm: Always pass cacheattr in S1_ptw_translate
>  * docs/system/arm/virt: Document 'mte' machine option
>  * hw/arm/boot: Fix PAUTH, MTE for EL3 direct kernel boot
>  * target/arm: Improve IMPDEF algorithm for IRG
>

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.1
for any user-visible changes.

-- PMM

[PULL 0/7] target-arm queue

2020-07-27 Thread Peter Maydell 
Just some bugfixes this time around.

-- PMM

The following changes since commit 4215d3413272ad6d1c6c9d0234450b602e46a74c:

  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.1-20200727' into 
staging (2020-07-27 09:33:04 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20200727

for you to fetch changes up to d4f6dda182e19afa75706936805e18397cb95f07:

  target/arm: Improve IMPDEF algorithm for IRG (2020-07-27 16:12:11 +0100)


target-arm queue:
 * ACPI: Assert that we don't run out of the preallocated memory
 * hw/misc/aspeed_sdmc: Fix incorrect memory size
 * target/arm: Always pass cacheattr in S1_ptw_translate
 * docs/system/arm/virt: Document 'mte' machine option
 * hw/arm/boot: Fix PAUTH, MTE for EL3 direct kernel boot
 * target/arm: Improve IMPDEF algorithm for IRG


Dongjiu Geng (1):
  ACPI: Assert that we don't run out of the preallocated memory

Peter Maydell (1):
  docs/system/arm/virt: Document 'mte' machine option

Philippe Mathieu-Daudé (1):
  hw/misc/aspeed_sdmc: Fix incorrect memory size

Richard Henderson (4):
  target/arm: Always pass cacheattr in S1_ptw_translate
  hw/arm/boot: Fix PAUTH for EL3 direct kernel boot
  hw/arm/boot: Fix MTE for EL3 direct kernel boot
  target/arm: Improve IMPDEF algorithm for IRG

 docs/system/arm/virt.rst |  4 
 hw/acpi/ghes.c   | 12 
 hw/arm/boot.c|  6 ++
 hw/misc/aspeed_sdmc.c|  7 ---
 target/arm/helper.c  | 19 ++-
 target/arm/mte_helper.c  | 37 ++---
 6 files changed, 54 insertions(+), 31 deletions(-)

Re: [PULL 0/7] target-arm queue

2019-11-19 Thread Peter Maydell 
On Tue, 19 Nov 2019 at 13:31, Peter Maydell  wrote:
>
> Target-arm queue for rc2 -- just some minor bugfixes.
>
> thanks
> -- PMM
>
> The following changes since commit 6e5d4999c761ffa082f60d72a14e5c953515b417:
>
>   Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-11-19' 
> into staging (2019-11-19 11:29:01 +)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20191119
>
> for you to fetch changes up to 04c9c81b8fa2ee33f59a26265700fae6fc646062:
>
>   target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY (2019-11-19 
> 13:20:28 +)
>
> 
> target-arm queue:
>  * Support EL0 v7m msr/mrs for CONFIG_USER_ONLY
>  * Relax r13 restriction for ldrex/strex for v8.0
>  * Do not reject rt == rt2 for strexd
>  * net/cadence_gem: Set PHY autonegotiation restart status
>  * ssi: xilinx_spips: Skip spi bus update for a few register writes
>  * pl031: Expose RTCICR as proper WC register
>



Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/4.2
for any user-visible changes.

-- PMM

[PULL 0/7] target-arm queue

2019-11-19 Thread Peter Maydell 
Target-arm queue for rc2 -- just some minor bugfixes.

thanks
-- PMM

The following changes since commit 6e5d4999c761ffa082f60d72a14e5c953515b417:

  Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-11-19' 
into staging (2019-11-19 11:29:01 +)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20191119

for you to fetch changes up to 04c9c81b8fa2ee33f59a26265700fae6fc646062:

  target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY (2019-11-19 13:20:28 
+)


target-arm queue:
 * Support EL0 v7m msr/mrs for CONFIG_USER_ONLY
 * Relax r13 restriction for ldrex/strex for v8.0
 * Do not reject rt == rt2 for strexd
 * net/cadence_gem: Set PHY autonegotiation restart status
 * ssi: xilinx_spips: Skip spi bus update for a few register writes
 * pl031: Expose RTCICR as proper WC register


Alexander Graf (1):
  pl031: Expose RTCICR as proper WC register

Linus Ziegert (1):
  net/cadence_gem: Set PHY autonegotiation restart status

Richard Henderson (4):
  target/arm: Merge arm_cpu_vq_map_next_smaller into sole caller
  target/arm: Do not reject rt == rt2 for strexd
  target/arm: Relax r13 restriction for ldrex/strex for v8.0
  target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY

Sai Pavan Boddu (1):
  ssi: xilinx_spips: Skip spi bus update for a few register writes

 target/arm/cpu.h   |   5 +--
 hw/net/cadence_gem.c   |   9 ++--
 hw/rtc/pl031.c |   6 +--
 hw/ssi/xilinx_spips.c  |  22 --
 target/arm/cpu64.c |  15 ---
 target/arm/helper.c|   9 +++-
 target/arm/m_helper.c  | 114 ++---
 target/arm/translate.c |  14 +++---
 8 files changed, 113 insertions(+), 81 deletions(-)

Re: [Qemu-devel] [PULL 0/7] target-arm queue

2017-11-07 Thread Peter Maydell 
On 7 November 2017 at 13:35, Peter Maydell  wrote:
> A small set of arm bugfixes for rc0.
>
>
>
> The following changes since commit 5853e92207193e967abf5e4c25b4a551c7604725:
>
>   Merge remote-tracking branch 'remotes/pmaydell/tags/pull-cocoa-20171107' 
> into staging (2017-11-07 12:19:48 +)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20171107
>
> for you to fetch changes up to 8a7348b5d62d7ea16807e6bea54b448a0184bb0f:
>
>   hw/intc/arm_gicv3_its: Don't abort on table save failure (2017-11-07 
> 13:03:52 +)
>
> 
> target-arm queue:
>  * arm_gicv3_its: Don't abort on table save failure
>  * arm_gicv3_its: Fix the VM termination in vm_change_state_handler()
>  * translate.c: Fix usermode big-endian AArch32 LDREXD and STREXD
>  * hw/arm: Mark the "fsl,imx31/25/6" devices with user_creatable = false
>  * arm: implement cache/shareability attribute bits for PAR registers
>
> 
> Andrew Baumann (1):
>   arm: implement cache/shareability attribute bits for PAR registers
>
> Eric Auger (1):
>   hw/intc/arm_gicv3_its: Don't abort on table save failure
>
> Peter Maydell (1):
>   translate.c: Fix usermode big-endian AArch32 LDREXD and STREXD
>
> Shanker Donthineni (1):
>   hw/intc/arm_gicv3_its: Fix the VM termination in 
> vm_change_state_handler()
>
> Thomas Huth (3):
>   hw/arm: Mark the "fsl,imx6" device with user_creatable = false
>   hw/arm: Mark the "fsl,imx25" device with user_creatable = false
>   hw/arm: Mark the "fsl,imx31" device with user_creatable = false

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/7] target-arm queue

2017-11-07 Thread Peter Maydell 
A small set of arm bugfixes for rc0.



The following changes since commit 5853e92207193e967abf5e4c25b4a551c7604725:

  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-cocoa-20171107' into 
staging (2017-11-07 12:19:48 +)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20171107

for you to fetch changes up to 8a7348b5d62d7ea16807e6bea54b448a0184bb0f:

  hw/intc/arm_gicv3_its: Don't abort on table save failure (2017-11-07 13:03:52 
+)


target-arm queue:
 * arm_gicv3_its: Don't abort on table save failure
 * arm_gicv3_its: Fix the VM termination in vm_change_state_handler()
 * translate.c: Fix usermode big-endian AArch32 LDREXD and STREXD
 * hw/arm: Mark the "fsl,imx31/25/6" devices with user_creatable = false
 * arm: implement cache/shareability attribute bits for PAR registers


Andrew Baumann (1):
  arm: implement cache/shareability attribute bits for PAR registers

Eric Auger (1):
  hw/intc/arm_gicv3_its: Don't abort on table save failure

Peter Maydell (1):
  translate.c: Fix usermode big-endian AArch32 LDREXD and STREXD

Shanker Donthineni (1):
  hw/intc/arm_gicv3_its: Fix the VM termination in vm_change_state_handler()

Thomas Huth (3):
  hw/arm: Mark the "fsl,imx6" device with user_creatable = false
  hw/arm: Mark the "fsl,imx25" device with user_creatable = false
  hw/arm: Mark the "fsl,imx31" device with user_creatable = false

 hw/arm/fsl-imx25.c  |   6 +-
 hw/arm/fsl-imx31.c  |   6 +-
 hw/arm/fsl-imx6.c   |   3 +-
 hw/intc/arm_gicv3_its_kvm.c |  12 +--
 target/arm/helper.c | 178 
 target/arm/translate.c  |  39 --
 6 files changed, 214 insertions(+), 30 deletions(-)

Re: [Qemu-devel] [PULL 0/7] target-arm queue

2017-07-31 Thread Peter Maydell 
On 31 July 2017 at 13:22, Peter Maydell  wrote:
> ARM queue for 2.10: all M profile bugfixes...
>
> thanks
> -- PMM
>
> The following changes since commit 25dd0e77898c3e10796d4cbeb35e8af5ba6ce975:
>
>   Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into 
> staging (2017-07-31 11:27:43 +0100)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20170731
>
> for you to fetch changes up to 89cbc3778a3d61761e2231e740269218c9a8a41d:
>
>   hw/mps2_scc: fix incorrect properties (2017-07-31 13:11:56 +0100)
>
> 
> target-arm queue:
>  * fix broken properties on MPS2 SCC device
>  * fix MPU trace handling of write vs exec
>  * fix MPU M profile bugs:
>- not handling system space or PPB region correctly
>- not resetting state
>- not migrating MPU_RNR
>
> 
> Peter Maydell (6):
>   target/arm: Correct MPU trace handling of write vs execute
>   target/arm: Don't do MPU lookups for addresses in M profile PPB region
>   target/arm: Don't allow guest to make System space executable for M 
> profile
>   target/arm: Rename cp15.c6_rgnr to pmsav7.rnr
>   target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs 
> get reset
>   target/arm: Migrate MPU_RNR register state for M profile cores
>
> Philippe Mathieu-Daudé (1):
>   hw/mps2_scc: fix incorrect properties

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/7] target-arm queue

2017-07-31 Thread Peter Maydell 
ARM queue for 2.10: all M profile bugfixes...

thanks
-- PMM

The following changes since commit 25dd0e77898c3e10796d4cbeb35e8af5ba6ce975:

  Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into 
staging (2017-07-31 11:27:43 +0100)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20170731

for you to fetch changes up to 89cbc3778a3d61761e2231e740269218c9a8a41d:

  hw/mps2_scc: fix incorrect properties (2017-07-31 13:11:56 +0100)


target-arm queue:
 * fix broken properties on MPS2 SCC device
 * fix MPU trace handling of write vs exec
 * fix MPU M profile bugs:
   - not handling system space or PPB region correctly
   - not resetting state
   - not migrating MPU_RNR


Peter Maydell (6):
  target/arm: Correct MPU trace handling of write vs execute
  target/arm: Don't do MPU lookups for addresses in M profile PPB region
  target/arm: Don't allow guest to make System space executable for M 
profile
  target/arm: Rename cp15.c6_rgnr to pmsav7.rnr
  target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get 
reset
  target/arm: Migrate MPU_RNR register state for M profile cores

Philippe Mathieu-Daudé (1):
  hw/mps2_scc: fix incorrect properties

 target/arm/cpu.h  |  3 +--
 hw/intc/armv7m_nvic.c | 14 +-
 hw/misc/mps2-scc.c|  4 +--
 target/arm/cpu.c  | 14 ++
 target/arm/helper.c   | 71 ++-
 target/arm/machine.c  | 30 +-
 6 files changed, 101 insertions(+), 35 deletions(-)

Re: [Qemu-devel] [PULL 0/7] target-arm queue

2015-11-10 Thread Peter Maydell 
On 10 November 2015 at 13:51, Peter Maydell  wrote:
> A small set of ARM patches, notably fixing bugs in breakpoint
> and singlestep code, and repairing the long-broken highbank model.
>
> The only other ARM thing I have on my radar for 2.5 is the Zynq
> ADC controller, which I'll send separately if it makes it before
> the freeze deadline.
>
> thanks
> -- PMM
>
> The following changes since commit a8b4f9585a0bf5186fca793ce2c5d754cd8ec49a:
>
>   Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2015-11-10' 
> into staging (2015-11-10 09:39:24 +)
>
> are available in the git repository at:
>
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20151110
>
> for you to fetch changes up to 577bf808958d06497928c639efaa473bf8c5e099:
>
>   target-arm: Clean up DISAS_UPDATE usage in AArch32 translation code 
> (2015-11-10 13:37:33 +)
>
> 
> target-arm queue:
>  * fix bugs in gdb singlestep handling and breakpoints
>  * minor code cleanup in arm_gic
>  * clean up error messages in hw/arm/virt
>  * fix highbank kernel booting by adding a board-setup blob
>

Applied, thanks.

-- PMM

Re: [Qemu-devel] [PULL 0/7] target-arm queue

2015-11-10 Thread Peter Maydell 
On 10 November 2015 at 17:12, Peter Crosthwaite
 wrote:
> On Tue, Nov 10, 2015 at 8:38 AM, Peter Maydell  
> wrote:
>> On 10 November 2015 at 13:51, Peter Maydell  wrote:
>>> A small set of ARM patches, notably fixing bugs in breakpoint
>>> and singlestep code, and repairing the long-broken highbank model.
>>>
>>> The only other ARM thing I have on my radar for 2.5 is the Zynq
>>> ADC controller, which I'll send separately if it makes it before
>>> the freeze deadline.
>>>
>
> It is on list I think. I don't see further review:
>
> [PATCH for-2.5 v4 1/1] hw/misc: Add support for ADC controller in
> Xilinx Zynq 7000

Ah yes, found it -- not sure why my search didn't turn it up earlier.

thanks
-- PMM

Re: [Qemu-devel] [PULL 0/7] target-arm queue

2015-11-10 Thread Peter Crosthwaite 
On Tue, Nov 10, 2015 at 8:38 AM, Peter Maydell  wrote:
> On 10 November 2015 at 13:51, Peter Maydell  wrote:
>> A small set of ARM patches, notably fixing bugs in breakpoint
>> and singlestep code, and repairing the long-broken highbank model.
>>
>> The only other ARM thing I have on my radar for 2.5 is the Zynq
>> ADC controller, which I'll send separately if it makes it before
>> the freeze deadline.
>>

It is on list I think. I don't see further review:

[PATCH for-2.5 v4 1/1] hw/misc: Add support for ADC controller in
Xilinx Zynq 7000

Regards,
Peter

>> thanks
>> -- PMM
>>
>> The following changes since commit a8b4f9585a0bf5186fca793ce2c5d754cd8ec49a:
>>
>>   Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2015-11-10' 
>> into staging (2015-11-10 09:39:24 +)
>>
>> are available in the git repository at:
>>
>>
>>   git://git.linaro.org/people/pmaydell/qemu-arm.git 
>> tags/pull-target-arm-20151110
>>
>> for you to fetch changes up to 577bf808958d06497928c639efaa473bf8c5e099:
>>
>>   target-arm: Clean up DISAS_UPDATE usage in AArch32 translation code 
>> (2015-11-10 13:37:33 +)
>>
>> 
>> target-arm queue:
>>  * fix bugs in gdb singlestep handling and breakpoints
>>  * minor code cleanup in arm_gic
>>  * clean up error messages in hw/arm/virt
>>  * fix highbank kernel booting by adding a board-setup blob
>>
>
> Applied, thanks.
>
> -- PMM
>

[Qemu-devel] [PULL 0/7] target-arm queue

2015-11-10 Thread Peter Maydell 
A small set of ARM patches, notably fixing bugs in breakpoint
and singlestep code, and repairing the long-broken highbank model.

The only other ARM thing I have on my radar for 2.5 is the Zynq
ADC controller, which I'll send separately if it makes it before
the freeze deadline.

thanks
-- PMM

The following changes since commit a8b4f9585a0bf5186fca793ce2c5d754cd8ec49a:

  Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2015-11-10' into 
staging (2015-11-10 09:39:24 +)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20151110

for you to fetch changes up to 577bf808958d06497928c639efaa473bf8c5e099:

  target-arm: Clean up DISAS_UPDATE usage in AArch32 translation code 
(2015-11-10 13:37:33 +)


target-arm queue:
 * fix bugs in gdb singlestep handling and breakpoints
 * minor code cleanup in arm_gic
 * clean up error messages in hw/arm/virt
 * fix highbank kernel booting by adding a board-setup blob


Andrew Jones (1):
  hw/arm/virt: error_report cleanups

Peter Crosthwaite (3):
  arm: boot: Add secure_board_setup flag
  arm: highbank: Defeature CPU override
  arm: highbank: Implement PSCI and dummy monitor

Sergey Fedorov (2):
  target-arm: Fix gdb singlestep handling in arm_debug_excp_handler()
  target-arm: Clean up DISAS_UPDATE usage in AArch32 translation code

Wei Huang (1):
  hw/intc/arm_gic: Remove the definition of NUM_CPU

 hw/arm/boot.c  | 10 +-
 hw/arm/highbank.c  | 91 +-
 hw/arm/virt.c  | 10 +++---
 hw/intc/arm_gic.c  |  8 ++---
 include/hw/arm/arm.h   |  6 
 target-arm/op_helper.c |  8 -
 target-arm/translate.c | 25 --
 7 files changed, 111 insertions(+), 47 deletions(-)

Re: [Qemu-devel] [PULL 0/7] target-arm queue

2015-09-24 Thread Pavel Fedin 
 Hello!

 Thank you very much for your support and cooperation. I am back from my 
vacation and continuing my
work on live migration. Actually i already have working code, but need to 
settle down kernel API
first.

Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia

Re: [Qemu-devel] [PULL 0/7] target-arm queue

2015-09-24 Thread Peter Maydell 
On 23 September 2015 at 17:31, Peter Maydell  wrote:
> Try number 2 with format string fix...
>
> -- PMM
>
> The following changes since commit fefa4b128de06cec6d513f00ee61e8208aed4a87:
>
>   Merge remote-tracking branch 'remotes/awilliam/tags/vfio-update-20150923.0' 
> into staging (2015-09-23 21:39:46 +0100)
>
> are available in the git repository at:
>
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20150924
>
> for you to fetch changes up to 85b4d5dae12580ecdd446c0f71afa04a95641c91:
>
>   MAINTAINERS: update Allwinner A10 maintainer (2015-09-24 01:29:37 +0100)
>
> 
> target-arm queue:
>  * support VGICv3 in KVM
>  * fix bug in ACPI table entries for flash devices in virt board
>  * update Allwinner entry in MAINTAINERS
>
> 

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/7] target-arm queue

2015-09-23 Thread Peter Maydell 
A small pullreq, but I don't have anything else pending and I wanted
to get the GICv3 patches in this week.

-- PMM


The following changes since commit 684bb5770ec5d72a66620f64fc5d9672bf8d3509:

  Merge remote-tracking branch 'remotes/dgibson/tags/spapr-next-20150923' into 
staging (2015-09-23 16:52:54 +0100)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20150923-1

for you to fetch changes up to 5d23e959fc6c8604d3c19b39b71c5a1effb2c347:

  MAINTAINERS: update Allwinner A10 maintainer (2015-09-23 22:37:40 +0100)


target-arm queue:
 * support VGICv3 in KVM
 * fix bug in ACPI table entries for flash devices in virt board
 * update Allwinner entry in MAINTAINERS


Beniamino Galvani (1):
  MAINTAINERS: update Allwinner A10 maintainer

Pavel Fedin (4):
  intc/gic: Extract some reusable vGIC code
  arm_kvm: Do not assume particular GIC type in kvm_arch_irqchip_create()
  hw/intc: Initial implementation of vGICv3
  hw/arm/virt: Add gic-version option to virt machine

Shannon Zhao (1):
  hw/arm/virt-acpi-build: Fix wrong size of flash in ACPI table

Shlomo Pongratz (1):
  hw/intc: Implement GIC-500 base class

 MAINTAINERS|   6 +-
 hw/arm/virt-acpi-build.c   |  56 --
 hw/arm/virt.c  | 124 --
 hw/intc/Makefile.objs  |   2 +
 hw/intc/arm_gic_kvm.c  |  98 
 hw/intc/arm_gicv3_common.c | 140 ++
 hw/intc/arm_gicv3_kvm.c| 149 +
 hw/intc/vgic_common.h  |  35 +
 include/hw/acpi/acpi-defs.h|   9 +++
 include/hw/arm/virt-acpi-build.h   |   1 +
 include/hw/arm/virt.h  |   4 +-
 include/hw/intc/arm_gicv3_common.h |  68 +
 include/sysemu/kvm.h   |  26 +++
 kvm-all.c  |  34 +
 target-arm/kvm.c   |  19 +++--
 target-arm/kvm_arm.h   |  19 +
 target-arm/machine.c   |  18 +
 17 files changed, 686 insertions(+), 122 deletions(-)
 create mode 100644 hw/intc/arm_gicv3_common.c
 create mode 100644 hw/intc/arm_gicv3_kvm.c
 create mode 100644 hw/intc/vgic_common.h
 create mode 100644 include/hw/intc/arm_gicv3_common.h

Re: [Qemu-devel] [PULL 0/7] target-arm queue

2015-09-23 Thread Peter Maydell 
On 23 September 2015 at 14:43, Peter Maydell  wrote:
> A small pullreq, but I don't have anything else pending and I wanted
> to get the GICv3 patches in this week.
>
> -- PMM
>
>
> The following changes since commit 684bb5770ec5d72a66620f64fc5d9672bf8d3509:
>
>   Merge remote-tracking branch 'remotes/dgibson/tags/spapr-next-20150923' 
> into staging (2015-09-23 16:52:54 +0100)
>
> are available in the git repository at:
>
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20150923-1
>
> for you to fetch changes up to 5d23e959fc6c8604d3c19b39b71c5a1effb2c347:
>
>   MAINTAINERS: update Allwinner A10 maintainer (2015-09-23 22:37:40 +0100)
>
> 
> target-arm queue:
>  * support VGICv3 in KVM
>  * fix bug in ACPI table entries for flash devices in virt board
>  * update Allwinner entry in MAINTAINERS
>
> 

Minor fixup required to get it to compile on 32-bit:

--- a/kvm-all.c
+++ b/kvm-all.c
@@ -2036,7 +2036,7 @@ void kvm_device_access(int fd, int group, uint64_t attr,
);
 if (err < 0) {
 error_report("KVM_%s_DEVICE_ATTR failed: %s\n"
- "Group %d attr 0x%016zX", write ? "SET" : "GET",
+ "Group %d attr 0x%016" PRIx64 , write ? "SET" : "GET",
  strerror(-err), group, attr);
 abort();
 }


-- PMM

[Qemu-devel] [PULL 0/7] target-arm queue

2015-09-23 Thread Peter Maydell 
Try number 2 with format string fix...

-- PMM

The following changes since commit fefa4b128de06cec6d513f00ee61e8208aed4a87:

  Merge remote-tracking branch 'remotes/awilliam/tags/vfio-update-20150923.0' 
into staging (2015-09-23 21:39:46 +0100)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20150924

for you to fetch changes up to 85b4d5dae12580ecdd446c0f71afa04a95641c91:

  MAINTAINERS: update Allwinner A10 maintainer (2015-09-24 01:29:37 +0100)


target-arm queue:
 * support VGICv3 in KVM
 * fix bug in ACPI table entries for flash devices in virt board
 * update Allwinner entry in MAINTAINERS


Beniamino Galvani (1):
  MAINTAINERS: update Allwinner A10 maintainer

Pavel Fedin (4):
  intc/gic: Extract some reusable vGIC code
  arm_kvm: Do not assume particular GIC type in kvm_arch_irqchip_create()
  hw/intc: Initial implementation of vGICv3
  hw/arm/virt: Add gic-version option to virt machine

Shannon Zhao (1):
  hw/arm/virt-acpi-build: Fix wrong size of flash in ACPI table

Shlomo Pongratz (1):
  hw/intc: Implement GIC-500 base class

 MAINTAINERS|   6 +-
 hw/arm/virt-acpi-build.c   |  56 --
 hw/arm/virt.c  | 124 --
 hw/intc/Makefile.objs  |   2 +
 hw/intc/arm_gic_kvm.c  |  98 
 hw/intc/arm_gicv3_common.c | 140 ++
 hw/intc/arm_gicv3_kvm.c| 149 +
 hw/intc/vgic_common.h  |  35 +
 include/hw/acpi/acpi-defs.h|   9 +++
 include/hw/arm/virt-acpi-build.h   |   1 +
 include/hw/arm/virt.h  |   4 +-
 include/hw/intc/arm_gicv3_common.h |  68 +
 include/sysemu/kvm.h   |  26 +++
 kvm-all.c  |  34 +
 target-arm/kvm.c   |  19 +++--
 target-arm/kvm_arm.h   |  19 +
 target-arm/machine.c   |  18 +
 17 files changed, 686 insertions(+), 122 deletions(-)
 create mode 100644 hw/intc/arm_gicv3_common.c
 create mode 100644 hw/intc/arm_gicv3_kvm.c
 create mode 100644 hw/intc/vgic_common.h
 create mode 100644 include/hw/intc/arm_gicv3_common.h

[Qemu-devel] [PULL 0/7] target-arm queue

2015-07-06 Thread Peter Maydell 
target-arm queue before hardfreeze: these are pretty much all
bugfixes.

-- PMM

The following changes since commit f50a1640fb82708a5d528dee1ace42a224b95b15:

  Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into 
staging (2015-07-05 20:35:47 +0100)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20150706

for you to fetch changes up to 257621a9566054472d1d55a819880d0f9da02bda:

  arm_mptimer: Respect IT bit state (2015-07-06 10:26:35 +0100)


target-arm queue:
 * TLBI ALLEI1IS should operate on all CPUs, not just this one
 * Fix interval interrupt of cadence ttc in decrement mode
 * Implement YIELD insn to yield in ARM and Thumb translators
 * ARM GIC: reset all registers
 * arm_mptimer: fix timer shutdown and mode change
 * arm_mptimer: respect IT bit state


Dmitry Osipenko (2):
  arm_mptimer: Fix timer shutdown and mode change
  arm_mptimer: Respect IT bit state

Johannes Schlatow (1):
  Fix interval interrupt of cadence ttc when timer is in decrement mode

Peter Maydell (3):
  target-arm: Split DISAS_YIELD from DISAS_WFE
  target-arm: Implement YIELD insn to yield in ARM and Thumb translators
  hw/intc/arm_gic_common.c: Reset all registers

Sergey Fedorov (1):
  target-arm: fix write helper for TLBI ALLE1IS

 hw/intc/arm_gic_common.c   | 21 ++---
 hw/timer/arm_mptimer.c | 13 ++---
 hw/timer/cadence_ttc.c |  9 -
 target-arm/helper.c|  2 +-
 target-arm/helper.h|  1 +
 target-arm/op_helper.c | 18 +++---
 target-arm/translate-a64.c |  6 ++
 target-arm/translate.c |  7 +++
 target-arm/translate.h |  1 +
 9 files changed, 63 insertions(+), 15 deletions(-)

Re: [Qemu-devel] [PULL 0/7] target-arm queue

2015-07-06 Thread Peter Maydell 
On 6 July 2015 at 10:59, Peter Maydell peter.mayd...@linaro.org wrote:
 target-arm queue before hardfreeze: these are pretty much all
 bugfixes.

 -- PMM

 The following changes since commit f50a1640fb82708a5d528dee1ace42a224b95b15:

   Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into 
 staging (2015-07-05 20:35:47 +0100)

 are available in the git repository at:


   git://git.linaro.org/people/pmaydell/qemu-arm.git 
 tags/pull-target-arm-20150706

 for you to fetch changes up to 257621a9566054472d1d55a819880d0f9da02bda:

   arm_mptimer: Respect IT bit state (2015-07-06 10:26:35 +0100)

 
 target-arm queue:
  * TLBI ALLEI1IS should operate on all CPUs, not just this one
  * Fix interval interrupt of cadence ttc in decrement mode
  * Implement YIELD insn to yield in ARM and Thumb translators
  * ARM GIC: reset all registers
  * arm_mptimer: fix timer shutdown and mode change
  * arm_mptimer: respect IT bit state

Applied, thanks.

-- PMM

Re: [Qemu-devel] [PULL 0/7] target-arm queue

2015-06-26 Thread Peter Maydell 
On 26 June 2015 at 14:31, Peter Maydell peter.mayd...@linaro.org wrote:
 target-arm queue: a few new features, but all minor stuff.

 thanks
 -- PMM


 The following changes since commit ccb0c7e122db72d3a5da798c6414d4912bba828f:

   Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150626' into 
 staging (2015-06-26 11:32:58 +0100)

 are available in the git repository at:


   git://git.linaro.org/people/pmaydell/qemu-arm.git 
 tags/pull-target-arm-20150626

 for you to fetch changes up to 4e2c0b2a4ab810c8989e181a010e75aeaa1c55f3:

   hw/arm/virt: Make block devices default to virtio (2015-06-26 14:22:37 
 +0100)

 
 target-arm queue:
  * Change the virt board's default interface type for block devices to virtio
  * Improve some error messages that will now be triggered by some incorrect
but previously worked-by-accident command lines
  * Print ELR if we're doing debug logging of AArch64 exception entry
  * Handle the completely empty semihosting commandline correctly for
softmmu (we already did for linux-user)
  * Add GICv2m description to ACPI tables for virt board
  * Fix some incorrect table revision entries in virt board ACPI tables

 

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/7] target-arm queue

2015-06-26 Thread Peter Maydell 
target-arm queue: a few new features, but all minor stuff.

thanks
-- PMM


The following changes since commit ccb0c7e122db72d3a5da798c6414d4912bba828f:

  Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150626' into staging 
(2015-06-26 11:32:58 +0100)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20150626

for you to fetch changes up to 4e2c0b2a4ab810c8989e181a010e75aeaa1c55f3:

  hw/arm/virt: Make block devices default to virtio (2015-06-26 14:22:37 +0100)


target-arm queue:
 * Change the virt board's default interface type for block devices to virtio
 * Improve some error messages that will now be triggered by some incorrect
   but previously worked-by-accident command lines
 * Print ELR if we're doing debug logging of AArch64 exception entry
 * Handle the completely empty semihosting commandline correctly for
   softmmu (we already did for linux-user)
 * Add GICv2m description to ACPI tables for virt board
 * Fix some incorrect table revision entries in virt board ACPI tables


Liviu Ionescu (1):
  target-arm: default empty semihosting cmdline

Peter Maydell (3):
  qdev-properties-system: Change set_pointer's parse callback to use Error
  qdev-properties-system: Improve error message for drive assignment 
conflict
  hw/arm/virt: Make block devices default to virtio

Shannon Zhao (2):
  hw/arm/virt-acpi-build: Fix table revision and some comments
  hw/arm/virt-acpi-build: Add GICv2m description in ACPI MADT table

Soren Brinkmann (1):
  target-arm: A64: Print ELR when taking exceptions

 hw/arm/virt-acpi-build.c | 22 -
 hw/arm/virt.c|  2 ++
 hw/core/qdev-properties-system.c | 42 +++-
 include/hw/acpi/acpi-defs.h  | 12 
 target-arm/arm-semi.c| 11 +--
 target-arm/helper-a64.c  |  2 ++
 6 files changed, 71 insertions(+), 20 deletions(-)

Re: [Qemu-devel] [PULL 0/7] target-arm queue

2015-03-16 Thread Peter Maydell 
On 16 March 2015 at 12:40, Peter Maydell peter.mayd...@linaro.org wrote:
 Last batch of bugfixes before hardfreeze...

 -- PMM

 The following changes since commit f421f05754ac5aabe15f12051390204116408b00:

   Merge remote-tracking branch 
 'remotes/kraxel/tags/pull-seabios-1.8.1-20150316-1' into staging (2015-03-16 
 10:58:11 +)

 are available in the git repository at:


   git://git.linaro.org/people/pmaydell/qemu-arm.git 
 tags/pull-target-arm-20150316

 for you to fetch changes up to b8d43285a4db12156c40ba6fdbd8002c383fcbca:

   linux-user: Access correct register for get/set_tls syscalls on ARM TZ CPUs 
 (2015-03-16 12:30:47 +)

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/7] target-arm queue

2015-03-16 Thread Peter Maydell 
Last batch of bugfixes before hardfreeze...

-- PMM

The following changes since commit f421f05754ac5aabe15f12051390204116408b00:

  Merge remote-tracking branch 
'remotes/kraxel/tags/pull-seabios-1.8.1-20150316-1' into staging (2015-03-16 
10:58:11 +)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20150316

for you to fetch changes up to b8d43285a4db12156c40ba6fdbd8002c383fcbca:

  linux-user: Access correct register for get/set_tls syscalls on ARM TZ CPUs 
(2015-03-16 12:30:47 +)


target-arm queue:
 * fix handling of execute-never bits in page table walks
 * tell kernel to initialize KVM GIC in realize function
 * fix handling of STM (user) with r15 in register list
 * ignore low bit of PC in M-profile exception return
 * fix linux-user get/set_tls syscalls on CPUs with TZ


Andrew Jones (3):
  target-arm: convert check_ap to ap_to_rw_prot
  target-arm: fix get_phys_addr_v6/SCTLR_AFE access check
  target-arm: get_phys_addr_lpae: more xn control

Eric Auger (1):
  hw/intc/arm_gic: Initialize the vgic in the realize function

Mikhail Ilyin (1):
  linux-user: Access correct register for get/set_tls syscalls on ARM TZ 
CPUs

Peter Maydell (2):
  target-arm: Fix handling of STM (user) with r15 in register list
  target-arm: Ignore low bit of PC in M-profile exception return

 hw/intc/arm_gic_kvm.c   |   7 ++
 linux-user/arm/target_cpu.h |  15 ++-
 linux-user/main.c   |   2 +-
 target-arm/helper.c | 222 
 target-arm/translate.c  |  18 ++--
 5 files changed, 197 insertions(+), 67 deletions(-)

[Qemu-devel] [PULL 0/7] target-arm queue

2014-11-04 Thread Peter Maydell 
Last handful of patches before hardfreeze; these are just
refactoring/cleanup, but I'd like to get them in to avoid
clashes and merge conflicts with other series like TZ.

thanks
-- PMM

The following changes since commit 949ca9e479c381a63ddb257adca1a6f0c44d898e:

  Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging 
(2014-11-03 22:51:08 +)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20141104

for you to fetch changes up to 9fae24f55496ea178e9e8e351f82a02f34ddaf4d:

  target-arm: Correct condition for taking VIRQ and VFIQ (2014-11-04 12:05:23 
+)


target-arm queue:
 * avoid passing CPU env pointer around in A32/T32 decoders
 * split M profile exception masking out from A/R profile


Peter Maydell (7):
  target-arm/translate.c: Use arm_dc_feature() in ENABLE_ARCH_ macros
  target-arm/translate.c: Use arm_dc_feature() rather than arm_feature()
  target-arm/translate.c: Don't use IS_M()
  target-arm/translate.c: Don't pass CPUARMState around in the decoder
  target-arm/translate.c: Don't pass CPUARMState * to disas_arm_insn()
  target-arm: Separate out M profile cpu_exec_interrupt handling
  target-arm: Correct condition for taking VIRQ and VFIQ

 target-arm/cpu.c   |  49 +++--
 target-arm/cpu.h   |  20 +---
 target-arm/translate.c | 280 +++--
 3 files changed, 197 insertions(+), 152 deletions(-)

Re: [Qemu-devel] [PULL 0/7] target-arm queue

2014-11-04 Thread Peter Maydell 
On 4 November 2014 12:30, Peter Maydell peter.mayd...@linaro.org wrote:
 Last handful of patches before hardfreeze; these are just
 refactoring/cleanup, but I'd like to get them in to avoid
 clashes and merge conflicts with other series like TZ.

 thanks
 -- PMM

 The following changes since commit 949ca9e479c381a63ddb257adca1a6f0c44d898e:

   Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging 
 (2014-11-03 22:51:08 +)

 are available in the git repository at:


   git://git.linaro.org/people/pmaydell/qemu-arm.git 
 tags/pull-target-arm-20141104

 for you to fetch changes up to 9fae24f55496ea178e9e8e351f82a02f34ddaf4d:

   target-arm: Correct condition for taking VIRQ and VFIQ (2014-11-04 12:05:23 
 +)

 
 target-arm queue:
  * avoid passing CPU env pointer around in A32/T32 decoders
  * split M profile exception masking out from A/R profile

 

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/7] target-arm queue

2011-10-20 Thread Peter Maydell 
Hi; these are the pending target-arm patches I'd like to get in for 1.0;
a couple of minor ones plus the A15 insn work. Please pull.

PS: I'm not sure who the best person to cc on target-arm pull requests
is; any suggestions?

thanks
-- PMM

The following changes since commit cfce6d8934243871c4dc6d0c5248b0b27a1b8d80:

  i8259: Move to hw library (2011-10-16 11:11:56 +)

are available in the git repository at:
  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream

Christophe LYON (1):
  rsqrte_f32: No need to copy sign bit.

Dmitry Koshelev (1):
  target-arm/machine.c: Restore VFP registers correctly

Peter Maydell (5):
  target-arm: v6 media multiply space: UNDEF on unassigned encodings
  target-arm: Rename ARM_FEATURE_DIV to _THUMB_DIV
  target-arm: Add ARM UDIV/SDIV support
  softfloat: Implement fused multiply-add
  target-arm: Implement VFPv4 fused multiply-accumulate insns

 fpu/softfloat-specialize.h |  178 ++
 fpu/softfloat.c|  427 
 fpu/softfloat.h|   14 ++
 target-arm/cpu.h   |4 +-
 target-arm/helper.c|   24 ++-
 target-arm/helper.h|3 +
 target-arm/machine.c   |2 +-
 target-arm/translate.c |  118 -
 8 files changed, 759 insertions(+), 11 deletions(-)