Re: Adapt to Allwinner device tree changes in linux >= 5.0-rc1
> Date: Mon, 21 Jan 2019 11:39:42 +1100
> From: Jonathan Gray
>
> Adapt to allwinner device tree changes in linux >= 5.0-rc1
> "allwinner,sun6i-a31-rtc" has been removed from h3/h5/r40/a64
>
> 507c6e89d6c4b2cd68a8e7ff69d1a00cf74b15dd
> ARM: dts: sunxi: h3/h5: Fix up RTC device node and clock references
>
> 44ff3cafcd7f413e7710a58ac40cfdc3a9380097
> arm64: dts: allwinner: a64: Fix up RTC device node and clock references
>
> 5f9e882825467105acafd208520b69bf95adb963
> ARM: dts: sun8i: r40: Add RTC device node
>
> compile tested only
Sure. Can't do any harm.
> Index: sxirtc.c
> ===
> RCS file: /cvs/src/sys/dev/fdt/sxirtc.c,v
> retrieving revision 1.2
> diff -u -p -r1.2 sxirtc.c
> --- sxirtc.c 27 Mar 2017 14:03:19 - 1.2
> +++ sxirtc.c 21 Jan 2019 00:16:02 -
> @@ -76,7 +76,9 @@ sxirtc_match(struct device *parent, void
>
> return (OF_is_compatible(faa->fa_node, "allwinner,sun4i-a10-rtc") ||
> OF_is_compatible(faa->fa_node, "allwinner,sun7i-a20-rtc") ||
> - OF_is_compatible(faa->fa_node, "allwinner,sun6i-a31-rtc"));
> + OF_is_compatible(faa->fa_node, "allwinner,sun6i-a31-rtc") ||
> + OF_is_compatible(faa->fa_node, "allwinner,sun8i-h3-rtc") ||
> + OF_is_compatible(faa->fa_node, "allwinner,sun50i-h5-rtc"));
> }
>
> void
> @@ -98,7 +100,9 @@ sxirtc_attach(struct device *parent, str
> faa->fa_reg[0].size, 0, >sc_ioh))
> panic("sxirtc_attach: bus_space_map failed!");
>
> - if (OF_is_compatible(faa->fa_node, "allwinner,sun6i-a31-rtc")) {
> + if (OF_is_compatible(faa->fa_node, "allwinner,sun6i-a31-rtc") ||
> + OF_is_compatible(faa->fa_node, "allwinner,sun8i-h3-rtc") ||
> + OF_is_compatible(faa->fa_node, "allwinner,sun50i-h5-rtc")) {
> sc->sc_yymmdd = SXIRTC_YYMMDD_A31;
> sc->sc_hhmmss = SXIRTC_HHMMSS_A31;
> } else {
>
>
Adapt to Allwinner device tree changes in linux >= 5.0-rc1
Adapt to allwinner device tree changes in linux >= 5.0-rc1
"allwinner,sun6i-a31-rtc" has been removed from h3/h5/r40/a64
507c6e89d6c4b2cd68a8e7ff69d1a00cf74b15dd
ARM: dts: sunxi: h3/h5: Fix up RTC device node and clock references
44ff3cafcd7f413e7710a58ac40cfdc3a9380097
arm64: dts: allwinner: a64: Fix up RTC device node and clock references
5f9e882825467105acafd208520b69bf95adb963
ARM: dts: sun8i: r40: Add RTC device node
compile tested only
Index: sxirtc.c
===
RCS file: /cvs/src/sys/dev/fdt/sxirtc.c,v
retrieving revision 1.2
diff -u -p -r1.2 sxirtc.c
--- sxirtc.c27 Mar 2017 14:03:19 - 1.2
+++ sxirtc.c21 Jan 2019 00:16:02 -
@@ -76,7 +76,9 @@ sxirtc_match(struct device *parent, void
return (OF_is_compatible(faa->fa_node, "allwinner,sun4i-a10-rtc") ||
OF_is_compatible(faa->fa_node, "allwinner,sun7i-a20-rtc") ||
- OF_is_compatible(faa->fa_node, "allwinner,sun6i-a31-rtc"));
+ OF_is_compatible(faa->fa_node, "allwinner,sun6i-a31-rtc") ||
+ OF_is_compatible(faa->fa_node, "allwinner,sun8i-h3-rtc") ||
+ OF_is_compatible(faa->fa_node, "allwinner,sun50i-h5-rtc"));
}
void
@@ -98,7 +100,9 @@ sxirtc_attach(struct device *parent, str
faa->fa_reg[0].size, 0, >sc_ioh))
panic("sxirtc_attach: bus_space_map failed!");
- if (OF_is_compatible(faa->fa_node, "allwinner,sun6i-a31-rtc")) {
+ if (OF_is_compatible(faa->fa_node, "allwinner,sun6i-a31-rtc") ||
+ OF_is_compatible(faa->fa_node, "allwinner,sun8i-h3-rtc") ||
+ OF_is_compatible(faa->fa_node, "allwinner,sun50i-h5-rtc")) {
sc->sc_yymmdd = SXIRTC_YYMMDD_A31;
sc->sc_hhmmss = SXIRTC_HHMMSS_A31;
} else {
testing of changes to clocks and switwi for Allwinner H3
I have tested changes described in: https://marc.info/?l=openbsd-tech <https://marc.info/?l=openbsd-tech=150642773703623=2> =150642773703623=2 on an orange pi one (Allwinner H3 device). These changes were tested with a driver that Artturi has built for a BME280 temperature, pressure and humidity sensor that he has integrated into sysctl hw.sensors.bme0 and sites on an i2c bus: # sysctl hw.sensors.bme0 hw.sensors.bme0.temp0=21.80 degC hw.sensors.bme0.humidity0=46.64% hw.sensors.bme0.pressure0=101.45 Pa # The attached dmesg also shows results of some testing on sxipio that needs further work and also for the dwxe driver that needs work for H3 devices. dmesg.boot Description: Binary data
Re: sunxi: add Allwinner A64 support for USB and USB clocks
On Sat, Jan 21, 2017 at 10:50:20AM +1000, Patrick Wildt wrote:
> Hi,
>
> so this diff makes the Pine64 work with EHCI. The only not nice thing
> is the switch. It would be better if this depends on the compatible
> since the A64 and H3 have different numbers (and clock parents) for the
> APB2 clock.
>
> I would still like to go ahead with this version since I don't think
> that the switch without the compatible check is going to hurt for now.
>
> ok?
>
> Patrick
After discussion with kettenis@ and his commit I have updated the diff.
I also added the clocks for MMC, which means that we now have a usable
USB port and MMC.
ok?
Patrick
diff --git a/sys/arch/armv7/sunxi/sxiccmu.c b/sys/arch/armv7/sunxi/sxiccmu.c
index 921b1dd4fe4..e0146cb0164 100644
--- a/sys/arch/armv7/sunxi/sxiccmu.c
+++ b/sys/arch/armv7/sunxi/sxiccmu.c
@@ -25,8 +25,6 @@
#include
#include
-#include
-
#include
#include
#include
@@ -88,6 +86,8 @@ int sxiccmu_ccu_set_frequency(void *, uint32_t *, uint32_t);
void sxiccmu_ccu_enable(void *, uint32_t *, int);
void sxiccmu_ccu_reset(void *, uint32_t *, int);
+uint32_t sxiccmu_a64_get_frequency(struct sxiccmu_softc *, uint32_t);
+intsxiccmu_a64_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
uint32_t sxiccmu_h3_get_frequency(struct sxiccmu_softc *, uint32_t);
intsxiccmu_h3_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
@@ -102,12 +102,14 @@ sxiccmu_match(struct device *parent, void *match, void
*aux)
return (OF_is_compatible(node, "allwinner,sun4i-a10") ||
OF_is_compatible(node, "allwinner,sun5i-a10s") ||
OF_is_compatible(node, "allwinner,sun5i-r8") ||
+ OF_is_compatible(node, "allwinner,sun50i-a64") ||
OF_is_compatible(node, "allwinner,sun7i-a20") ||
OF_is_compatible(node, "allwinner,sun8i-h3") ||
OF_is_compatible(node, "allwinner,sun9i-a80"));
}
- return OF_is_compatible(faa->fa_node, "allwinner,sun8i-h3-ccu");
+ return (OF_is_compatible(faa->fa_node, "allwinner,sun50i-a64-ccu") ||
+ OF_is_compatible(faa->fa_node, "allwinner,sun8i-h3-ccu"));
}
void
@@ -124,7 +126,15 @@ sxiccmu_attach(struct device *parent, struct device *self,
void *aux)
printf("\n");
- if (OF_is_compatible(node, "allwinner,sun8i-h3-ccu")) {
+ if (OF_is_compatible(node, "allwinner,sun50i-a64-ccu")) {
+ KASSERT(faa->fa_nreg > 0);
+ sc->sc_gates = sun50i_a64_gates;
+ sc->sc_ngates = nitems(sun50i_a64_gates);
+ sc->sc_resets = sun50i_a64_resets;
+ sc->sc_nresets = nitems(sun50i_a64_resets);
+ sc->sc_get_frequency = sxiccmu_a64_get_frequency;
+ sc->sc_set_frequency = sxiccmu_a64_set_frequency;
+ } else if (OF_is_compatible(node, "allwinner,sun8i-h3-ccu")) {
KASSERT(faa->fa_nreg > 0);
sc->sc_gates = sun8i_h3_gates;
sc->sc_ngates = nitems(sun8i_h3_gates);
@@ -653,6 +663,24 @@ sxiccmu_ccu_get_frequency(void *cookie, uint32_t *cells)
}
uint32_t
+sxiccmu_a64_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
+{
+ switch (idx) {
+ case A64_CLK_PLL_PERIPH0:
+ /* XXX default value. */
+ return 6;
+ case A64_CLK_PLL_PERIPH0_2X:
+ return sxiccmu_a64_get_frequency(sc, A64_CLK_PLL_PERIPH0) * 2;
+ case A64_CLK_APB2:
+ /* XXX Controlled by a MUX. */
+ return 2400;
+ }
+
+ printf("%s: 0x%08x\n", __func__, idx);
+ return 0;
+}
+
+uint32_t
sxiccmu_h3_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
{
switch (idx) {
@@ -678,6 +706,28 @@ sxiccmu_ccu_set_frequency(void *cookie, uint32_t *cells,
uint32_t freq)
}
int
+sxiccmu_a64_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t
freq)
+{
+ struct sxiccmu_clock clock;
+ uint32_t parent, parent_freq;
+
+ switch (idx) {
+ case A64_CLK_MMC0:
+ case A64_CLK_MMC1:
+ case A64_CLK_MMC2:
+ clock.sc_iot = sc->sc_iot;
+ bus_space_subregion(sc->sc_iot, sc->sc_ioh,
+ sc->sc_gates[idx].reg, 4, _ioh);
+ parent = A64_CLK_PLL_PERIPH0_2X;
+ parent_freq = sxiccmu_ccu_get_frequency(sc, );
+ return sxiccmu_mmc_do_set_frequency(, freq, parent_freq);
+ }
+
+ printf("%s: 0x%08x\n", __func__, idx);
+ return -1;
+}
+
+int
sxiccmu_h3_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)
{
struct sxiccmu_clock clock;
diff --git a/
sunxi: add Allwinner A64 support for USB and USB clocks
Hi,
so this diff makes the Pine64 work with EHCI. The only not nice thing
is the switch. It would be better if this depends on the compatible
since the A64 and H3 have different numbers (and clock parents) for the
APB2 clock.
I would still like to go ahead with this version since I don't think
that the switch without the compatible check is going to hurt for now.
ok?
Patrick
diff --git a/sys/arch/armv7/sunxi/sxiccmu.c b/sys/arch/armv7/sunxi/sxiccmu.c
index 7b67f749ff4..397349cd27a 100644
--- a/sys/arch/armv7/sunxi/sxiccmu.c
+++ b/sys/arch/armv7/sunxi/sxiccmu.c
@@ -25,8 +25,6 @@
#include
#include
-#include
-
#include
#include
#include
@@ -94,12 +92,14 @@ sxiccmu_match(struct device *parent, void *match, void *aux)
return (OF_is_compatible(node, "allwinner,sun4i-a10") ||
OF_is_compatible(node, "allwinner,sun5i-a10s") ||
OF_is_compatible(node, "allwinner,sun5i-r8") ||
+ OF_is_compatible(node, "allwinner,sun50i-a64") ||
OF_is_compatible(node, "allwinner,sun7i-a20") ||
OF_is_compatible(node, "allwinner,sun8i-h3") ||
OF_is_compatible(node, "allwinner,sun9i-a80"));
}
- return OF_is_compatible(faa->fa_node, "allwinner,sun8i-h3-ccu");
+ return (OF_is_compatible(faa->fa_node, "allwinner,sun50i-a64-ccu") ||
+ OF_is_compatible(faa->fa_node, "allwinner,sun8i-h3-ccu"));
}
void
@@ -116,7 +116,13 @@ sxiccmu_attach(struct device *parent, struct device *self,
void *aux)
printf("\n");
- if (OF_is_compatible(node, "allwinner,sun8i-h3-ccu")) {
+ if (OF_is_compatible(node, "allwinner,sun50i-a64-ccu")) {
+ KASSERT(faa->fa_nreg > 0);
+ sc->sc_gates = sun50i_a64_gates;
+ sc->sc_ngates = nitems(sun50i_a64_gates);
+ sc->sc_resets = sun50i_a64_resets;
+ sc->sc_nresets = nitems(sun50i_a64_resets);
+ } else if (OF_is_compatible(node, "allwinner,sun8i-h3-ccu")) {
KASSERT(faa->fa_nreg > 0);
sc->sc_gates = sun8i_h3_gates;
sc->sc_ngates = nitems(sun8i_h3_gates);
@@ -643,6 +649,7 @@ sxiccmu_ccu_get_frequency(void *cookie, uint32_t *cells)
case H3_CLK_PLL_PERIPH0:
/* XXX default value. */
return 6;
+ case A64_CLK_APB2:
case H3_CLK_APB2:
/* XXX Controlled by a MUX. */
return 2400;
diff --git a/sys/arch/armv7/sunxi/sxiccmu_clocks.h
b/sys/arch/armv7/sunxi/sxiccmu_clocks.h
index 84791762035..256da5f1f03 100644
--- a/sys/arch/armv7/sunxi/sxiccmu_clocks.h
+++ b/sys/arch/armv7/sunxi/sxiccmu_clocks.h
@@ -5,6 +5,40 @@
* Clocks Signals
*/
+#define A64_CLK_APB2 26
+
+#define A64_CLK_BUS_EHCI0 42
+#define A64_CLK_BUS_EHCI1 43
+#define A64_CLK_BUS_OHCI0 44
+#define A64_CLK_BUS_OHCI1 45
+
+#define A64_CLK_BUS_UART0 67
+#define A64_CLK_BUS_UART1 68
+#define A64_CLK_BUS_UART2 69
+#define A64_CLK_BUS_UART3 70
+#define A64_CLK_BUS_UART4 71
+
+#define A64_CLK_USB_OHCI0 91
+#define A64_CLK_USB_OHCI1 93
+#define A64_CLK_USB_PHY0 86
+#define A64_CLK_USB_PHY1 87
+
+struct sxiccmu_ccu_bit sun50i_a64_gates[] = {
+ [A64_CLK_BUS_EHCI0] = { 0x0060, 24 },
+ [A64_CLK_BUS_EHCI1] = { 0x0060, 25 },
+ [A64_CLK_BUS_OHCI0] = { 0x0060, 28 },
+ [A64_CLK_BUS_OHCI1] = { 0x0060, 29 },
+ [A64_CLK_BUS_UART0] = { 0x006c, 16, A64_CLK_APB2 },
+ [A64_CLK_BUS_UART1] = { 0x006c, 17, A64_CLK_APB2 },
+ [A64_CLK_BUS_UART2] = { 0x006c, 18, A64_CLK_APB2 },
+ [A64_CLK_BUS_UART3] = { 0x006c, 19, A64_CLK_APB2 },
+ [A64_CLK_BUS_UART4] = { 0x006c, 20, A64_CLK_APB2 },
+ [A64_CLK_USB_OHCI0] = { 0x00cc, 16 },
+ [A64_CLK_USB_OHCI1] = { 0x00cc, 17 },
+ [A64_CLK_USB_PHY0] = { 0x00cc, 8 },
+ [A64_CLK_USB_PHY1] = { 0x00cc, 9 },
+};
+
#define H3_CLK_PLL_PERIPH0 9
#define H3_CLK_APB218
@@ -68,6 +102,23 @@ struct sxiccmu_ccu_bit sun8i_h3_gates[] = {
* Reset Signals
*/
+#define A64_RST_USB_PHY0 0
+#define A64_RST_USB_PHY1 1
+
+#define A64_RST_BUS_EHCI0 19
+#define A64_RST_BUS_EHCI1 20
+#define A64_RST_BUS_OHCI0 21
+#define A64_RST_BUS_OHCI1 22
+
+struct sxiccmu_ccu_bit sun50i_a64_resets[] = {
+ [A64_RST_USB_PHY0] = { 0x00cc, 0 },
+ [A64_RST_USB_PHY1] = { 0x00cc, 1 },
+ [A64_RST_BUS_EHCI0] = { 0x02c0, 24 },
+ [A64_RST_BUS_EHCI1] = { 0x02c0, 25 },
+ [A64_RST_BUS_OHCI0] = { 0x02c0, 28 },
+ [A64_RST_BUS_OHCI1] = { 0x02c0, 29 },
+};
+
#define H3_RST_USB_PHY00
#define H3_RST_USB_PHY11
#define H3_RST_USB_PHY2
Re: arm: support Allwinner A20 Ethernet
> On Fri, Mar 04, 2016 at 11:19:37AM -0300, Daniel Bolgheroni wrote: > > On Sat, Feb 27, 2016 at 11:09:10PM +0100, Patrick Wildt wrote: > > > > > > + /* print interrupt state */ > > > + snprintb(buf, sizeof(buf), "\177\20" > > > + "b\x10""NI\0" ... > > I don't have a quick solution for this too, but it's worth noticing that > > snprintb() is NetBSD-specific. ... > That's correct. So far it's in an ifdef DEBUG. I could've just removed > all that code but thought it was better to keep it in for now. Like every BSD since 4.1, the kernel printf functions support %b, and we never went down the road of adding a different function just to please a compiler that whines.
Re: arm: support Allwinner A20 Ethernet
On Fri, Mar 04, 2016 at 11:19:37AM -0300, Daniel Bolgheroni wrote: > On Sat, Feb 27, 2016 at 11:09:10PM +0100, Patrick Wildt wrote: > > > > + /* print interrupt state */ > > + snprintb(buf, sizeof(buf), "\177\20" > > + "b\x10""NI\0" > > + "b\x0f""AI\0" > > + "b\x0e""ER\0" > > + "b\x0d""FB\0" > > + "b\x0a""ET\0" > > + "b\x09""RW\0" > > + "b\x08""RS\0" > > + "b\x07""RU\0" > > + "b\x06""RI\0" > > + "b\x05""UN\0" > > + "b\x04""OV\0" > > + "b\x03""TJ\0" > > + "b\x02""TU\0" > > + "b\x01""TS\0" > > + "b\x00""TI\0" > > + "\0", dma_status); > > > + /* print filter setup */ > > + snprintb(buf, sizeof(buf), "\177\20" > > + "b\x1f""RA\0" > > + "b\x0a""HPF\0" > > + "b\x09""SAF\0" > > + "b\x08""SAIF\0" > > + "b\x05""DBF\0" > > + "b\x04""PM\0" > > + "b\x03""DAIF\0" > > + "b\x02""HMC\0" > > + "b\x01""HUC\0" > > + "b\x00""PR\0" > > + "\0", ffilt); > > Hi Patrick, > > I don't have a quick solution for this too, but it's worth noticing that > snprintb() is NetBSD-specific. > > Thank you. > > -- > db That's correct. So far it's in an ifdef DEBUG. I could've just removed all that code but thought it was better to keep it in for now.
Re: arm: support Allwinner A20 Ethernet
On Sat, Feb 27, 2016 at 11:09:10PM +0100, Patrick Wildt wrote: > > + /* print interrupt state */ > + snprintb(buf, sizeof(buf), "\177\20" > + "b\x10""NI\0" > + "b\x0f""AI\0" > + "b\x0e""ER\0" > + "b\x0d""FB\0" > + "b\x0a""ET\0" > + "b\x09""RW\0" > + "b\x08""RS\0" > + "b\x07""RU\0" > + "b\x06""RI\0" > + "b\x05""UN\0" > + "b\x04""OV\0" > + "b\x03""TJ\0" > + "b\x02""TU\0" > + "b\x01""TS\0" > + "b\x00""TI\0" > + "\0", dma_status); > + /* print filter setup */ > + snprintb(buf, sizeof(buf), "\177\20" > + "b\x1f""RA\0" > + "b\x0a""HPF\0" > + "b\x09""SAF\0" > + "b\x08""SAIF\0" > + "b\x05""DBF\0" > + "b\x04""PM\0" > + "b\x03""DAIF\0" > + "b\x02""HMC\0" > + "b\x01""HUC\0" > + "b\x00""PR\0" > + "\0", ffilt); Hi Patrick, I don't have a quick solution for this too, but it's worth noticing that snprintb() is NetBSD-specific. Thank you. -- db
Re: arm: support Allwinner A20 Ethernet
On Wed, Mar 02, 2016 at 05:22:50PM +0100, Patrick Wildt wrote: > Nice, glad to hear that! > > Looks like you're in a DDB panic? What happened? Can you > do "show panic" in DDB? Yes, it's in ddb. There is a trace in the previous message also, but here it is a new one. This happens everytime when ssh'ing to something, maybe in other cases also. The previous one was within a cvs update. After the ssh command is entered, the console freezes, but I can still receive the replies from ping for 2 to 4 minutes. Then, it panics. Hope this helps. Thank you. # ssh 192.168.1.5 panic: _bus_dmamap_sync: bad length Stopped at Debugger+0x4: ldrbr15, [r15, r15, ror r15]! TIDPIDUID PRFLAGS PFLAGS CPU COMMAND *16145 16145 0 0x14000 0x2100 softnet panic+0x18 scp=0xc03c44c0 rlv=0xc0537eb8 (_bus_dmamap_sync+0xb8) rsp=0xcc3d2db0 rfp=0xcc3d2df4 _bus_dmamap_sync+0xc scp=0xc0537e0c rlv=0xc030edb4 (dwc_gmac_txdesc_sync+0xa8) rsp=0xcc3d2df8 rfp=0xcc3d2e1c r10=0x r9=0x00ff r8=0xc54c119c r7=0xc0537e00 r6=0x0005 r5=0x r4=0xc54c1000 dwc_gmac_txdesc_sync+0x10 scp=0xc030ed1c rlv=0xc0310a38 (dwc_gmac_start+0xec) rsp=0xcc3d2e20 rfp=0xcc3d2e4c r7=0xc54c1000 r6=0xc54c103c r5=0x r4=0x dwc_gmac_start+0x10 scp=0xc031095c rlv=0xc040c278 (if_start_locked+0x34) rsp=0xcc3d2e50 rfp=0xcc3d2e6c r10=0xc54c129c r9=0x r8=0x r7=0x0062 r6=0xc069274c r5=0x0003 r4=0xc54c103c if_start_locked+0xc scp=0xc040c250 rlv=0xc0410168 (if_enqueue+0x98) rsp=0xcc3d2e70 rfp=0xcc3d2e94 r6=0x0002 r5=0xc54c103c r4=0x if_enqueue+0x10 scp=0xc04100e0 rlv=0xc0411cf4 (ether_output+0x188) rsp=0xcc3d2e98 rfp=0xcc3d2ecc r8=0xcc3d2e9e r7=0x0008 r6=0xca4ba400 r5=0xc54c103c r4=0xca4ba456 ether_output+0xc scp=0xc0411b78 rlv=0xc0467ea8 (ip_output+0x6d0) rsp=0xcc3d2ed0 rfp=0xcc3d2f40 r10=0x r8=0xc54c103c r7=0xcc3d2f04 r6=0xcc3d2efc r5=0xc068e658 r4=0xca4ba464 ip_output+0xc scp=0xc04677e4 rlv=0xc04613a4 (ip_send+0x80) rsp=0xcc3d2f44 rfp=0xcc3d2f78 r10=0xc06e6190 r9=0x r8=0xc06e632c r7=0xcc3d2f7c r6=0xc069274c r5=0x r4=0xcc3d2f50 ip_send+0x48 scp=0xc046136c rlv=0xc03b7770 (taskq_thread+0x90) rsp=0xcc3d2f7c rfp=0xcc3d2fb0 r6=0x0001 r5=0xc53dc040 r4=0xc03b7648 taskq_thread+0xc scp=0xc03b76ec rlv=0xc0538878 (proc_trampoline+0x18) rsp=0xcc3d2fb4 rfp=0xc07a6edc r7=0x r6=0x r5=0xc53dc040 r4=0xc03b76e0 Bad frame pointer: 0xc07a6edc http://www.openbsd.org/ddb.html describes the minimum info required in bug reports. Insufficient info makes it difficult to find and fix bugs. ddb> ps TID PPID PGRPUID S FLAGS WAIT COMMAND 18687 6725 18687 0 30x83 selectssh 6725 1 6725 0 30x10008b pause ksh 13129 1 13129 0 30x100098 poll cron 145 1145 99 30x100090 poll sndiod 29303 1 29303110 30x100090 poll sndiod 4161 1012 1012 95 30x100090 kqreadsmtpd 28657 1012 1012 95 30x100090 kqreadsmtpd 14144 1012 1012 95 30x100090 kqreadsmtpd 1517 1012 1012 95 30x100090 kqreadsmtpd 23185 1012 1012 95 30x100090 kqreadsmtpd 475 1012 1012103 30x100090 kqreadsmtpd 1012 1 1012 0 30x100080 kqreadsmtpd 10113 1 10113 0 30x80 selectsshd 631 4499 24054 83 30x100090 poll ntpd 4499 24054 24054 83 30x100090 poll ntpd 24054 1 24054 0 30x100080 poll ntpd 24258 17591 17591 74 30x100090 bpf pflogd 17591 1 17591 0 30x80 netio pflogd 6153 26767 26767 73 30x100090 kqreadsyslogd 26767 1 26767 0 30x100080 netio syslogd 5764 1 5764 77 30x100090 poll dhclient 9406 1 9406 0 30x80 poll dhclient 19407 0 0 0 3 0x14200 pgzerozerothread 7013 0 0 0 3 0x14200 aiodoned aiodoned 3359 0 0 0 3 0x14200 syncerupdate 4092 0 0 0 3 0x14200 cleaner cleaner 2344 0 0 0 3 0x14200 reaperreaper 7077 0 0 0 3 0x14200 pgdaemon pagedaemon 29027 0 0 0 3 0x14200 bored crypto 6851 0 0 0 3 0x14200 pftm pfpurge 24135 0 0 0 3 0x14200 usbtskusbtask 6548 0 0 0 3
Re: arm: support Allwinner A20 Ethernet
On Sat, Feb 27, 2016 at 11:09:10PM +0100, Patrick Wildt wrote: > Hi, > > the Allwinner A10 and A20 SoC include an EMAC, but it's only used in > few devices like the Cubieboard. The A20, like the A31 and A80, contain > a GMAC, which is a Synopsys Designware controller. This is commonly > used on the Banana Pi, Lamobo R1, Cubieboard 2 and more. This diff > is the complete diff I worked on to support the GMAC. It's based on > NetBSD's DWC driver plus some glue code. > > Unfortunately this diff currently (probably) only works on the > Cubieboard 2, or devices similarly wired. Not every device is wired > the same, and we currently have no way to distinguish A20 based devices. > Once we are able to parse a device tree it will be much easier to set up > the clock and tx delay per board. Cubieboard 2, also with the workaround patch from arm@. Thank you. dmesg OpenBSD/sunxi booting ... arg0 0x0 arg1 0x10bb arg2 0x4100 atag core flags 0 pagesize 0 rootdev 0 atag serial 0x16516616:0b01944c atag mem start 0x4000 size 0x4000 bootfile: bootargs: memory size derived from u-boot bootconf.mem[0].address = 4000 pages 262144/0x4000 Allocating page tables freestart = 0x40774000, free_pages = 260236 (0x0003f88c) IRQ stack: p0x407a2000 v0xc07a2000 ABT stack: p0x407a3000 v0xc07a3000 UND stack: p0x407a4000 v0xc07a4000 SVC stack: p0x407a5000 v0xc07a5000 Creating L1 page table at 0x40774000 Mapping kernel Constructing L2 page tables undefined page pmap [ using 398344 bytes of bsd ELF symbol table ] board type: 4283 Copyright (c) 1982, 1986, 1989, 1991, 1993 The Regents of the University of California. All rights reserved. Copyright (c) 1995-2016 OpenBSD. All rights reserved. http://www.OpenBSD.org OpenBSD 5.9-current (GENERIC) #2: Mon Feb 29 01:35:57 BRT 2016 dbolgher...@bbb.my.domain:/usr/src/sys/arch/armv7/compile/GENERIC real mem = 1073741824 (1024MB) avail mem = 1044967424 (996MB) warning: no entropy supplied by boot loader mainbus0 at root cortex0 at mainbus0 ampintc0 at cortex0 nirq 160 agtimer0 at cortex0: tick rate 24000 KHz cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core) cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache sunxi0 at mainbus0: Allwinner A20 sxipio0 at sunxi0 sxiccmu0 at sunxi0 sxidog0 at sunxi0 sxirtc0 at sunxi0 sxiuart0 at sunxi0: console sxiuart1 at sunxi0 sxiuart2 at sunxi0 sxiuart3 at sunxi0 sxiuart4 at sunxi0 sxiuart5 at sunxi0 sxiuart6 at sunxi0 sxiuart7 at sunxi0 awge0 at sunxi0 awge0: Ethernet address: 02:16:0b:01:94:4c rlphy0 at awge0 phy 1: RTL8201L 10/100 PHY, rev. 1 ahci0 at sunxi0 AHCI 1.1 ahci0: port 0: 1.5Gb/s scsibus0 at ahci0: 32 targets sd0 at scsibus0 targ 0 lun 0: <ATA, TOSHIBA MK3265GS, GJ00> SCSI3 0/direct fixed naa.5393138822a0 sd0: 305245MB, 512 bytes/sector, 625142448 sectors ehci0 at sunxi0 usb0 at ehci0: USB revision 2.0 uhub0 at usb0 "Allwinner EHCI root hub" rev 2.00/1.00 addr 1 ehci1 at sunxi0 usb1 at ehci1: USB revision 2.0 uhub1 at usb1 "Allwinner EHCI root hub" rev 2.00/1.00 addr 1 gpio0 at sxipio0: 18 pins gpio1 at sxipio0: 24 pins gpio2 at sxipio0: 25 pins gpio3 at sxipio0: 28 pins gpio4 at sxipio0: 12 pins gpio5 at sxipio0: 6 pins gpio6 at sxipio0: 12 pins gpio7 at sxipio0: 28 pins gpio8 at sxipio0: 22 pins vscsi0 at root scsibus1 at vscsi0: 256 targets softraid0 at root scsibus2 at softraid0: 256 targets boot device: lookup '' failed. root device: sd0a swap device (default sd0b): root on sd0a swap on sd0b dump on sd0b WARNING: preposterous time in file system WARNING: CHECK AND RESET THE DATE! Automatic boot in progress: starting file system checks. /dev/sd0a (0d3d29f19b4e9e54.a): file system is clean; not checking /dev/sd0l (0d3d29f19b4e9e54.l): file system is clean; not checking /dev/sd0d (0d3d29f19b4e9e54.d): file system is clean; not checking /dev/sd0f (0d3d29f19b4e9e54.f): file system is clean; not checking /dev/sd0g (0d3d29f19b4e9e54.g): file system is clean; not checking /dev/sd0h (0d3d29f19b4e9e54.h): file system is clean; not checking /dev/sd0k (0d3d29f19b4e9e54.k): file system is clean; not checking /dev/sd0j (0d3d29f19b4e9e54.j): file system is clean; not checking /dev/sd0e (0d3d29f19b4e9e54.e): file system is clean; not checking setting tty flags pf enabled starting network DHCPDISCOVER on awge0 - interval 3 DHCPOFFER from 192.168.1.1 (14:cc:20:de:4b:cc) DHCPREQUEST on awge0 to 255.255.255.255 DHCPACK from 192.168.1.1 (14:cc:20:de:4b:cc) bound to 192.168.1.69 -- renewal in 3600 seconds. starting early daemons: syslogd pflogd ntpd. starting RPC daemons:. savecore: no core dump checking quotas: done. clearing /tmp kern.securelevel: 0 -> 1 creating runtime link editor directory cache. preserving editor files. starting network daemons: sshd smtpd sndiod. starting local daemons: cron. Thu Jan 1 07:47:54 BRT 1970 OpenBSD/armv7 (cb2.my.dom
arm: support Allwinner A20 Ethernet
Hi,
the Allwinner A10 and A20 SoC include an EMAC, but it's only used in
few devices like the Cubieboard. The A20, like the A31 and A80, contain
a GMAC, which is a Synopsys Designware controller. This is commonly
used on the Banana Pi, Lamobo R1, Cubieboard 2 and more. This diff
is the complete diff I worked on to support the GMAC. It's based on
NetBSD's DWC driver plus some glue code.
Unfortunately this diff currently (probably) only works on the
Cubieboard 2, or devices similarly wired. Not every device is wired
the same, and we currently have no way to distinguish A20 based devices.
Once we are able to parse a device tree it will be much easier to set up
the clock and tx delay per board.
Patrick
diff --git sys/arch/armv7/conf/GENERIC sys/arch/armv7/conf/GENERIC
index b55771d..6858d75 100644
--- sys/arch/armv7/conf/GENERIC
+++ sys/arch/armv7/conf/GENERIC
@@ -93,6 +93,7 @@ sxidog* at sunxi? # watchdog timer
sxirtc*at sunxi? # Real Time Clock
sxiuart* at sunxi? # onboard UARTs
sxie* at sunxi?
+awge* at sunxi?
ahci* at sunxi? # AHCI/SATA (shim)
ehci* at sunxi? # EHCI (shim)
usb* at ehci?#flags 0x1
diff --git sys/arch/armv7/conf/RAMDISK sys/arch/armv7/conf/RAMDISK
index 8c0c22b..d857d2b 100644
--- sys/arch/armv7/conf/RAMDISK
+++ sys/arch/armv7/conf/RAMDISK
@@ -91,6 +91,7 @@ sxidog* at sunxi? # watchdog timer
sxirtc*at sunxi? # Real Time Clock
sxiuart* at sunxi? # onboard UARTs
sxie* at sunxi?
+awge* at sunxi?
ahci* at sunxi? # AHCI/SATA (shim)
ehci* at sunxi? # EHCI (shim)
usb* at ehci?#flags 0x1
diff --git sys/arch/armv7/sunxi/files.sunxi sys/arch/armv7/sunxi/files.sunxi
index 80c4ba4..96f8832 100644
--- sys/arch/armv7/sunxi/files.sunxi
+++ sys/arch/armv7/sunxi/files.sunxi
@@ -48,3 +48,7 @@ file arch/armv7/sunxi/sxiuart.c sxiuart
device sxie: ether, ifnet, mii, ifmedia
attach sxie at sunxi
file arch/armv7/sunxi/sxie.c sxie
+
+# A20 GMAC
+attach awge at sunxi with sxige
+file arch/armv7/sunxi/sxige.csxige
diff --git sys/arch/armv7/sunxi/sun7i.c sys/arch/armv7/sunxi/sun7i.c
index 53978f3..73ecd24 100644
--- sys/arch/armv7/sunxi/sun7i.c
+++ sys/arch/armv7/sunxi/sun7i.c
@@ -100,12 +100,11 @@ struct armv7_dev sxia20_devs[] = {
.irq = { UART7_IRQ }
},
- /* EMAC */
- { .name = "sxie",
+ /* GMAC */
+ { .name = "awge",
.unit = 0,
- .mem = { { EMAC_ADDR, EMAC_SIZE },
- { SXIESRAM_ADDR, SXIESRAM_SIZE } },
- .irq = { EMAC_IRQ}
+ .mem = { { GMAC_ADDR, GMAC_SIZE } },
+ .irq = { GMAC_IRQ }
},
/* SATA/AHCI */
diff --git sys/arch/armv7/sunxi/sunxi.c sys/arch/armv7/sunxi/sunxi.c
index dac0348..256169e 100644
--- sys/arch/armv7/sunxi/sunxi.c
+++ sys/arch/armv7/sunxi/sunxi.c
@@ -77,7 +77,7 @@ struct board_dev sun7i_devs[] = {
{ "sxiuart",5 },
{ "sxiuart",6 },
{ "sxiuart",7 },
- { "sxie", 0 },
+ { "awge", 0 },
{ "ahci", 0 },
{ "ehci", 0 },
{ "ehci", 1 },
diff --git sys/arch/armv7/sunxi/sxiccmu.c sys/arch/armv7/sunxi/sxiccmu.c
index ddfc415..16481a1 100644
--- sys/arch/armv7/sunxi/sxiccmu.c
+++ sys/arch/armv7/sunxi/sxiccmu.c
@@ -64,6 +64,24 @@
#defineCCMU_AHB_GATING_EMAC(1 << 17)
#defineCCMU_AHB_GATING_SATA(1 << 25)
+#defineCCMU_AHB_GATING10x64
+#defineCCMU_AHB_GATING_MALI400 (1 << 20)
+#defineCCMU_AHB_GATING_MP (1 << 18)
+#defineCCMU_AHB_GATING_GMAC(1 << 17)
+#defineCCMU_AHB_GATING_DE_FE1 (1 << 15)
+#defineCCMU_AHB_GATING_DE_FE0 (1 << 14)
+#defineCCMU_AHB_GATING_DE_BE1 (1 << 13)
+#defineCCMU_AHB_GATING_DE_BE0 (1 << 12)
+#defineCCMU_AHB_GATING_HDMI(1 << 11)
+#defineCCMU_AHB_GATING_CSI1(1 << 9)
+#defineCCMU_AHB_GATING_CSI0(1 << 8)
+#defineCCMU_AHB_GATING_LCD1(1 << 5)
+#defineCCMU_AHB_GATING_LCD0(1 << 4)
+#defineCCMU_AHB_GATING_TVE1(1 << 3)
+#defineCCMU_AHB_GATING_TVE0(1 << 2)
+#defineCCMU_AHB_GATING_TVD (1 << 1)
+#defineCCMU_AHB_GATING_VE (1 << 0)
+
#defineCCMU_APB_GATING00x68
#defineCCMU_APB_GATING_PI
Re: armv7: banana pi, Allwinner A20 board
On Mon, Oct 20, 2014 at 12:15:42PM +0200, Raphael Graf wrote:
On Thu, October 16, 2014 11:40 pm, Patrick Wildt wrote:
I do believe that this is a pmap issue.
I just got hands on an Allwinner A20 and suffered the same issues:
pool_setlowat crashing randomly, same for ahci and so on.
I believe we are not syncing the PTEs correctly.
Here?s the snippet from PTE_SYNC(), but PTE_SYNC_RANGE() has
the same issue:
#define PTE_SYNC(pte)
\
do {
\
if (PMAP_NEEDS_PTE_SYNC) { \
paddr_t pa; \
cpu_drain_writebuf(); \
cpu_dcache_wb_range((vaddr_t)(pte), sizeof(pt_entry_t));\
if (cpu_sdcache_enabled()) {\
(void)pmap_extract(pmap_kernel(), (vaddr_t)(pte), pa); \
cpu_sdcache_wb_range((vaddr_t)(pte), (paddr_t)(pa), \
sizeof(pt_entry_t));\
}; \
cpu_drain_writebuf(); \
} \
} while (/*CONSTCOND*/0)
I believe that when we change things in the pagetables, we need to make
sure the tables are synced before we?re going to use them. In our case
we believe that we are using uncached pagetables, which means that
every write will directly hit the tables.
But that does not have an affect on the write buffer. The write buffer is
still
there and has to be cleared manually. If it isn?t, and something accesses
an area which was just mapped, then we?re fucked.
Therefore I firmly believe that the cpu_drain_writebuf() call has to be made
regardless of PMAP_NEEDS_PTE_SYNC and that it has to be called before
that if-clause.
Doing that fixes my issues.
\Patrick
I think this is correct. With the diff below, my A20 board doesn't panic
anymore.
I still get a lot of messages like the following though:
pmap_fault_fixup: va 8000 ftype 1 u pte 7f24f02e
http://permalink.gmane.org/gmane.comp.hardware.netbook.arm.sunxi/3342
It seems Cortex A8/Allwinner A10 allocates cache lines on read and
Cortex A7/Allwinner A20 allocates on write.
Or rather the A7/A15 have inner shareable L2 unlike the
A9/A8 which have external outer shareable L2 that affects the coherency.
The current snapshot has this diff included, and was built on
a kernel running it.
Index: sys/arch/arm/include/pmap.h
===
RCS file: /cvs/src/sys/arch/arm/include/pmap.h,v
retrieving revision 1.27
diff -u -p -u -p -r1.27 pmap.h
--- sys/arch/arm/include/pmap.h 7 Oct 2014 10:10:58 - 1.27
+++ sys/arch/arm/include/pmap.h 20 Oct 2014 09:33:14 -
@@ -328,9 +328,9 @@ extern int pmap_needs_pte_sync;
#define PTE_SYNC(pte)
\
do { \
+ cpu_drain_writebuf(); \
if (PMAP_NEEDS_PTE_SYNC) { \
paddr_t pa; \
- cpu_drain_writebuf(); \
cpu_dcache_wb_range((vaddr_t)(pte), sizeof(pt_entry_t));\
if (cpu_sdcache_enabled()) {\
(void)pmap_extract(pmap_kernel(), (vaddr_t)(pte), pa); \
@@ -343,9 +343,9 @@ do {
\
#define PTE_SYNC_RANGE(pte, cnt)
\
do { \
+ cpu_drain_writebuf(); \
if (PMAP_NEEDS_PTE_SYNC) { \
paddr_t pa; \
- cpu_drain_writebuf(); \
cpu_dcache_wb_range((vaddr_t)(pte), \
(cnt) 2); /* * sizeof(pt_entry_t) */ \
if (cpu_sdcache_enabled()) {\
Re: armv7: banana pi, Allwinner A20 board
On Thu, October 16, 2014 11:40 pm, Patrick Wildt wrote:
I do believe that this is a pmap issue.
I just got hands on an Allwinner A20 and suffered the same issues:
pool_setlowat crashing randomly, same for ahci and so on.
I believe we are not syncing the PTEs correctly.
Here?s the snippet from PTE_SYNC(), but PTE_SYNC_RANGE() has
the same issue:
#define PTE_SYNC(pte)
\
do { \
if (PMAP_NEEDS_PTE_SYNC) { \
paddr_t pa; \
cpu_drain_writebuf(); \
cpu_dcache_wb_range((vaddr_t)(pte), sizeof(pt_entry_t));\
if (cpu_sdcache_enabled()) {\
(void)pmap_extract(pmap_kernel(), (vaddr_t)(pte), pa); \
cpu_sdcache_wb_range((vaddr_t)(pte), (paddr_t)(pa), \
sizeof(pt_entry_t));\
}; \
cpu_drain_writebuf(); \
} \
} while (/*CONSTCOND*/0)
I believe that when we change things in the pagetables, we need to make
sure the tables are synced before we?re going to use them. In our case
we believe that we are using uncached pagetables, which means that
every write will directly hit the tables.
But that does not have an affect on the write buffer. The write buffer is
still
there and has to be cleared manually. If it isn?t, and something accesses
an area which was just mapped, then we?re fucked.
Therefore I firmly believe that the cpu_drain_writebuf() call has to be made
regardless of PMAP_NEEDS_PTE_SYNC and that it has to be called before
that if-clause.
Doing that fixes my issues.
\Patrick
I think this is correct. With the diff below, my A20 board doesn't panic
anymore.
I still get a lot of messages like the following though:
pmap_fault_fixup: va 8000 ftype 1 u pte 7f24f02e
Index: sys/arch/arm/include/pmap.h
===
RCS file: /cvs/src/sys/arch/arm/include/pmap.h,v
retrieving revision 1.27
diff -u -p -u -p -r1.27 pmap.h
--- sys/arch/arm/include/pmap.h 7 Oct 2014 10:10:58 - 1.27
+++ sys/arch/arm/include/pmap.h 20 Oct 2014 09:33:14 -
@@ -328,9 +328,9 @@ extern int pmap_needs_pte_sync;
#definePTE_SYNC(pte)
\
do { \
+ cpu_drain_writebuf(); \
if (PMAP_NEEDS_PTE_SYNC) { \
paddr_t pa; \
- cpu_drain_writebuf(); \
cpu_dcache_wb_range((vaddr_t)(pte), sizeof(pt_entry_t));\
if (cpu_sdcache_enabled()) {\
(void)pmap_extract(pmap_kernel(), (vaddr_t)(pte), pa); \
@@ -343,9 +343,9 @@ do {
\
#definePTE_SYNC_RANGE(pte, cnt)
\
do { \
+ cpu_drain_writebuf(); \
if (PMAP_NEEDS_PTE_SYNC) { \
paddr_t pa; \
- cpu_drain_writebuf(); \
cpu_dcache_wb_range((vaddr_t)(pte), \
(cnt) 2); /* * sizeof(pt_entry_t) */ \
if (cpu_sdcache_enabled()) {\
Re: armv7: banana pi, Allwinner A20 board
Hello, Theo gave a hint to check early console code and I found something curious. Here is a diff to printf debug... Index: sxiuart.c === RCS file: /cvs/src/sys/arch/armv7/sunxi/sxiuart.c,v retrieving revision 1.3 diff -u -p -r1.3 sxiuart.c --- sxiuart.c 6 Nov 2013 19:03:07 - 1.3 +++ sxiuart.c 18 Oct 2014 20:39:38 - @@ -971,15 +971,18 @@ sxiuartcngetc(dev_t dev) uint8_t c; s = splhigh(); - +bus_space_write_1(sxiuartconsiot, sxiuartconsioh, SXIUART_THR, 'a'); while (!ISSET(bus_space_read_1(sxiuartconsiot, sxiuartconsioh, SXIUART_LSR), LSR_RXRDY)) continue; +bus_space_write_1(sxiuartconsiot, sxiuartconsioh, SXIUART_THR, 'b'); c = bus_space_read_1(sxiuartconsiot, sxiuartconsioh, SXIUART_RBR); /* clear any pending interrupts */ +bus_space_write_1(sxiuartconsiot, sxiuartconsioh, SXIUART_THR, 'c'); (void)bus_space_read_1(sxiuartconsiot, sxiuartconsioh, SXIUART_IIR); +bus_space_write_1(sxiuartconsiot, sxiuartconsioh, SXIUART_THR, 'd'); splx(s); return (c); } UKC stalls at polling LSR_RXRDY flag. User Kernel Config UKC a but ddb works no problem. panic: uvm_fault: fault on non-pageable map (0xc0af328c, 0xc55aa000) Stopped at 0xc0a1d4ac: ldrbr15, [r15, r15, ror r15]! RUN AT LEAST 'trace' AND 'ps' AND INCLUDE OUTPUT WHEN REPORTING THIS PANIC! DO NOT EVEN BOTHER REPORTING THIS WITHOUT INCLUDING THAT INFORMATION! ddbabd I think sxiuartcngetc() have no problem and something makes worse. Do I have to check page table (memory attribute of ARMv7 MMU) when running UKC? -- SASANO Takayoshi u...@mx5.nisiq.net
Re: armv7: banana pi, Allwinner A20 board
I do believe that this is a pmap issue.
I just got hands on an Allwinner A20 and suffered the same issues:
pool_setlowat crashing randomly, same for ahci and so on.
I believe we are not syncing the PTEs correctly.
Here’s the snippet from PTE_SYNC(), but PTE_SYNC_RANGE() has
the same issue:
#define PTE_SYNC(pte) \
do {\
if (PMAP_NEEDS_PTE_SYNC) { \
paddr_t pa; \
cpu_drain_writebuf(); \
cpu_dcache_wb_range((vaddr_t)(pte), sizeof(pt_entry_t));\
if (cpu_sdcache_enabled()) {\
(void)pmap_extract(pmap_kernel(), (vaddr_t)(pte), pa); \
cpu_sdcache_wb_range((vaddr_t)(pte), (paddr_t)(pa), \
sizeof(pt_entry_t));\
}; \
cpu_drain_writebuf(); \
} \
} while (/*CONSTCOND*/0)
I believe that when we change things in the pagetables, we need to make
sure the tables are synced before we’re going to use them. In our case
we believe that we are using uncached pagetables, which means that
every write will directly hit the tables.
But that does not have an affect on the write buffer. The write buffer is still
there and has to be cleared manually. If it isn’t, and something accesses
an area which was just mapped, then we’re fucked.
Therefore I firmly believe that the cpu_drain_writebuf() call has to be made
regardless of PMAP_NEEDS_PTE_SYNC and that it has to be called before
that if-clause.
Doing that fixes my issues.
\Patrick
Am 09.10.2014 um 22:55 schrieb SASANO Takayoshi u...@mx5.nisiq.net:
Hello,
Here is the log of new image.
Booting with -c option, UKC still hangs up.
I hope the log helps debugging.
Regards,
--
SASANO Takayoshi u...@mx5.nisiq.net
U-Boot SPL 2014.04-10694-g2ae8b32-dirty (Oct 01 2014 - 17:40:04)
Board: Bananapi
DRAM: 1024 MiB
CPU: 96000Hz, AXI/AHB/APB: 3/2/2
spl: not an uImage at 1600
U-Boot 2014.04-10694-g2ae8b32-dirty (Oct 01 2014 - 17:40:04) Allwinner
Technology
CPU: Allwinner A20 (SUN7I)
Board: Bananapi
I2C: ready
DRAM: 1 GiB
MMC: SUNXI SD/MMC: 0
*** Warning - bad CRC, using default environment
In:serial
Out: serial
Err: serial
Net: dwmac.1c5
Hit any key to stop autoboot: 0
reading uEnv.txt
118 bytes read in 16 ms (6.8 KiB/s)
Loaded environment from uEnv.txt
Running uenvcmd ...
reading bsd.umg
7386560 bytes read in 364 ms (19.4 MiB/s)
## Booting kernel from Legacy Image at 6000 ...
Image Name: boot
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size:7386496 Bytes = 7 MiB
Load Address: 4080
Entry Point: 4080
Verifying Checksum ... OK
Loading Kernel Image ... OK
Starting kernel ...
OpenBSD/sunxi booting ...
arg0 0x0 arg1 0x10bb arg2 0x4100
atag core flags 0 pagesize 0 rootdev 0
atag cmdline [sd0i:/bsd -c]
atag mem start 0x4000 size 0x4000
bootfile: sd0i:/bsd
bootargs: -c
memory size derived from u-boot
bootconf.mem[0].address = 4000 pages 262144/0x4000
Allocating page tables
freestart = 0x40f0c000, free_pages = 258292 (0x0003f0f4)
IRQ stack: p0x40f3a000 v0xc0f3a000
ABT stack: p0x40f3b000 v0xc0f3b000
UND stack: p0x40f3c000 v0xc0f3c000
SVC stack: p0x40f3d000 v0xc0f3d000
Creating L1 page table at 0x40f0c000
Mapping kernel
Constructing L2 page tables
undefined page pmap [ using 170728 bytes of bsd ELF symbol table ]
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
Copyright (c) 1995-2014 OpenBSD. All rights reserved. http://www.OpenBSD.org
kernel does not support -c; continuing..
OpenBSD 5.6-current (RAMDISK-SUNXI) #1: Thu Oct 9 21:03:32 AEDT 2014
r...@armv7.jsg.id.au:/usr/src/sys/arch/armv7/compile/RAMDISK-SUNXI
real mem = 1073741824 (1024MB)
avail mem = 1036165120 (988MB)
warning: no entropy supplied by boot loader
mainbus0 at root
cortex0 at mainbus0
ampintc0 at cortex0 nirq 160
cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
sunxi0 at mainbus0: A20
sxipio0 at sunxi0
sxiccmu0 at sunxi0
sxitimer0 at sunxi0: ticktimer 100hz @ 32KHz
sxitimer1 at sunxi0: stattimer 128hz @ 32KHz
sxitimer2 at sunxi0: cntrtimer @ 32KHz
sxidog0 at sunxi0
sxirtc0 at sunxi0
sxiuart0 at sunxi0: console
sxiuart1 at sunxi0
sxiuart2 at sunxi0
sxiuart3 at sunxi0
sxiuart4 at sunxi0
sxiuart5 at sunxi0
sxiuart6
Re: armv7: banana pi, Allwinner A20 board
Here are some updated images with the fix for the interrupt controller on cortex a7/15. http://marc.info/?l=openbsd-cvsm=141278003609690w=2 http://jsg.id.au/openbsd/armv7/bsd.SUNXI.umg http://jsg.id.au/openbsd/armv7/bsd.rd.SUNXI.umg Though it sounds like A20/sun7i handles the timer in a different way to A10/sun4i, and there is no driver in the tree for the 'gmac' Ethernet. On Wed, Oct 08, 2014 at 11:11:48AM +0900, SASANO Takayoshi wrote: Hi, here is the log using bsd.SUNXI.umg instead of bsd.rd.SUNXI.img. (thanks to Theo) -c invokes UKC, but hangs up at there. -- OpenBSD/sunxi booting ... arg0 0x0 arg1 0x10bb arg2 0x4100 atag core flags 0 pagesize 0 rootdev 0 atag cmdline [sd0i:/bsd -c] atag mem start 0x4000 size 0x4000 bootfile: sd0i:/bsd bootargs: -c memory size derived from u-boot bootconf.mem[0].address = 4000 pages 262144/0x4000 Allocating page tables freestart = 0x40b9a000, free_pages = 259174 (0x0003f466) IRQ stack: p0x40bc8000 v0xc0bc8000 ABT stack: p0x40bc9000 v0xc0bc9000 UND stack: p0x40bca000 v0xc0bca000 SVC stack: p0x40bcb000 v0xc0bcb000 Creating L1 page table at 0x40b9c000 Mapping kernel Constructing L2 page tables undefined page pmap [ using 300196 bytes of bsd ELF symbol table ] Copyright (c) 1982, 1986, 1989, 1991, 1993 The Regents of the University of California. All rights reserved. Copyright (c) 1995-2014 OpenBSD. All rights reserved. http://www.OpenBSD.org User Kernel Config UKC -- SASANO Takayoshi u...@mx5.nisiq.net
Re: armv7: banana pi, Allwinner A20 board
Hello, Here is the log of new image. Booting with -c option, UKC still hangs up. I hope the log helps debugging. Regards, -- SASANO Takayoshi u...@mx5.nisiq.net U-Boot SPL 2014.04-10694-g2ae8b32-dirty (Oct 01 2014 - 17:40:04) Board: Bananapi DRAM: 1024 MiB CPU: 96000Hz, AXI/AHB/APB: 3/2/2 spl: not an uImage at 1600 U-Boot 2014.04-10694-g2ae8b32-dirty (Oct 01 2014 - 17:40:04) Allwinner Technology CPU: Allwinner A20 (SUN7I) Board: Bananapi I2C: ready DRAM: 1 GiB MMC: SUNXI SD/MMC: 0 *** Warning - bad CRC, using default environment In:serial Out: serial Err: serial Net: dwmac.1c5 Hit any key to stop autoboot: 0 reading uEnv.txt 118 bytes read in 16 ms (6.8 KiB/s) Loaded environment from uEnv.txt Running uenvcmd ... reading bsd.umg 7386560 bytes read in 364 ms (19.4 MiB/s) ## Booting kernel from Legacy Image at 6000 ... Image Name: boot Image Type: ARM Linux Kernel Image (uncompressed) Data Size:7386496 Bytes = 7 MiB Load Address: 4080 Entry Point: 4080 Verifying Checksum ... OK Loading Kernel Image ... OK Starting kernel ... OpenBSD/sunxi booting ... arg0 0x0 arg1 0x10bb arg2 0x4100 atag core flags 0 pagesize 0 rootdev 0 atag cmdline [sd0i:/bsd -c] atag mem start 0x4000 size 0x4000 bootfile: sd0i:/bsd bootargs: -c memory size derived from u-boot bootconf.mem[0].address = 4000 pages 262144/0x4000 Allocating page tables freestart = 0x40f0c000, free_pages = 258292 (0x0003f0f4) IRQ stack: p0x40f3a000 v0xc0f3a000 ABT stack: p0x40f3b000 v0xc0f3b000 UND stack: p0x40f3c000 v0xc0f3c000 SVC stack: p0x40f3d000 v0xc0f3d000 Creating L1 page table at 0x40f0c000 Mapping kernel Constructing L2 page tables undefined page pmap [ using 170728 bytes of bsd ELF symbol table ] Copyright (c) 1982, 1986, 1989, 1991, 1993 The Regents of the University of California. All rights reserved. Copyright (c) 1995-2014 OpenBSD. All rights reserved. http://www.OpenBSD.org kernel does not support -c; continuing.. OpenBSD 5.6-current (RAMDISK-SUNXI) #1: Thu Oct 9 21:03:32 AEDT 2014 r...@armv7.jsg.id.au:/usr/src/sys/arch/armv7/compile/RAMDISK-SUNXI real mem = 1073741824 (1024MB) avail mem = 1036165120 (988MB) warning: no entropy supplied by boot loader mainbus0 at root cortex0 at mainbus0 ampintc0 at cortex0 nirq 160 cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core) cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache sunxi0 at mainbus0: A20 sxipio0 at sunxi0 sxiccmu0 at sunxi0 sxitimer0 at sunxi0: ticktimer 100hz @ 32KHz sxitimer1 at sunxi0: stattimer 128hz @ 32KHz sxitimer2 at sunxi0: cntrtimer @ 32KHz sxidog0 at sunxi0 sxirtc0 at sunxi0 sxiuart0 at sunxi0: console sxiuart1 at sunxi0 sxiuart2 at sunxi0 sxiuart3 at sunxi0 sxiuart4 at sunxi0 sxiuart5 at sunxi0 sxiuart6 at sunxi0 sxiuart7 at sunxi0 sxie0 at sunxi0, address 02:99:03:c2:d2:6e ukphy0 at sxie0 phy 0: Generic IEEE 802.3u media interface, rev. 5: OUI 0x000732, model 0x0011 ukphy1 at sxie0 phy 1: Generic IEEE 802.3u media interface, rev. 5: OUI 0x000732, model 0x0011 ahci0 at sunxi0 AHCI 1.1 pmap_fault_fixup: va c5544000 ftype 2 s pte 7ff9301e panic: uvm_fault: fault on non-pageable map (0xc0e7f28c, 0xc5544000) Stopped at Debugger+0x4: ldrbr15, [r15, r15, ror r15]! panic+0x18 scp=0xc083a39c rlv=0xc08c2f54 (uvm_fault+0xca8) rsp=0xc0f3eaec rfp=0xc0f3ec0c uvm_fault+0xc scp=0xc08c22b8 rlv=0xc08fe588 (data_abort_handler+0x248) rsp=0xc0f3ec10 rfp=0xc0f3ec64 r10=0xc0f3ec68 r9=0xc0f3d000 r8=0x r7=0xc0e9f764 r6=0x0002 r5=0xc0ebc7b4 r4=0xc5544000 data_abort_handler+0xc scp=0xc08fe34c rlv=0xc08fdd54 (address_exception_entry+0x50) rsp=0xc0f3ec68 rfp=0xc0f3eccc r10=0xc0ebd1b4 r9=0x0200 r8=0x014c r7=0x000a r6=0x0009 r5=0xc5544e00 r4=0x0010 poison_mem+0xc scp=0xc0835bb8 rlv=0xc081df20 (malloc+0x2ec) rsp=0xc0f3ecd0 rfp=0xc0f3ed38 r5=0xc5544000 r4=0xc5544e00 malloc+0x10 scp=0xc081dc44 rlv=0xc08fcee8 (_bus_dmamap_create+0x40) rsp=0xc0f3ed3c rfp=0xc0f3ed5c r10=0x r9=0x7ff97000 r8=0x r7=0x0003 r6=0x0001 r5=0x0040 r4=0x0018 _bus_dmamap_create+0x10 scp=0xc08fceb8 rlv=0xc0804384 (ahci_port_alloc+0x34c) rsp=0xc0f3ed60 rfp=0xc0f3edb0 r7=0xc553b300 r6=0xc548a200 r5=0xc5542000 r4=0x ahci_port_alloc+0x10 scp=0xc0804048 rlv=0xc0804814 (ahci_attach+0x80) rsp=0xc0f3edb4 rfp=0xc0f3ede8 r10=0xc0f3ee5c r9=0xc0f3ee5c r8=0x r7=0xc553b300 r6=0xc553b300 r5=0x0001 r4=0x ahci_attach+0xc scp=0xc08047a0 rlv=0xc0931fb0 (sxiahci_attach+0x480) rsp=0xc0f3edec rfp=0xc0f3ee18 r6=0xc0904420 r5=0x r4=0xd1135000 sxiahci_attach+0x10 scp=0xc0931b40 rlv=0xc08309e0 (config_attach+0x1d4) rsp=0xc0f3ee1c
Re: armv7: banana pi, Allwinner A20 board
Hi,
Did you try disabling ehci to see if that makes a difference?
Curiously, -c option in bootargs seems to be ignored.
I tried it both uEnv.txt and U-Boot console. Here is the log.
There is no problem to pass -c string to kernel.
What is happening?
Regards,
U-Boot SPL 2014.04-10694-g2ae8b32-dirty (Oct 01 2014 - 17:40:04)
Board: Bananapi
DRAM: 1024 MiB
CPU: 96000Hz, AXI/AHB/APB: 3/2/2
spl: not an uImage at 1600
U-Boot 2014.04-10694-g2ae8b32-dirty (Oct 01 2014 - 17:40:04) Allwinner
Technology
CPU: Allwinner A20 (SUN7I)
Board: Bananapi
I2C: ready
DRAM: 1 GiB
MMC: SUNXI SD/MMC: 0
*** Warning - bad CRC, using default environment
In:serial
Out: serial
Err: serial
Net: dwmac.1c5
Hit any key to stop autoboot: 0
sun7i# setenv bootargs sd0i:/bsd -c
sun7i# printenv
autoboot=run loadkernel run setargs true bootm 0x4800
baudrate=115200
boot_ram=saved_stdout=$stdout;setenv stdout nc;if iminfo 0x4100; then true;
setenv stdout $saved_stdout; source 0x4100;else setenv stdout
$saved_stdout;fi
bootargs=sd0i:/bsd -c
bootcmd=if run loadbootenv; then echo Loaded environment from ${bootenv};env
import -t ${scriptaddr} ${filesize};fi;if test -n ${uenvcmd}; then echo
Running uenvcmd ...;run uenvcmd;fi;if run loadbootscr; then echo Jumping to
${bootscr};source ${scriptaddr};fi;run autoboot;
bootdelay=2
bootenv=uEnv.txt
bootm_size=0x1000
bootscr=boot.scr
console=ttyS0,115200
device=mmc
ethact=dwmac.1c5
ethaddr=02:99:03:c2:d2:6e
kernel=uImage
loadbootenv=fatload $device $partition $scriptaddr ${bootenv} || ext2load
$device $partition $scriptaddr boot/${bootenv} || ext2load $device $partition
$scriptaddr ${bootenv}
loadbootscr=fatload $device $partition $scriptaddr ${bootscr} || ext2load
$device $partition $scriptaddr boot/${bootscr} ||ext2load $device $partition
$scriptaddr ${bootscr}
loadkernel=if bootpath=/boot/ ext2load $device $partition 0x4300
${bootpath}${script} ext2load $device $partition 0x4800
${bootpath}${kernel};then true; elif bootpath=/ fatload $device $partition
0x4300 ${script} fatload $device $partition 0x4800 ${kernel};then
true; elif bootpath=/ ext2load $device $partition 0x4300
${bootpath}${script} ext2load $device $partition 0x4800
${bootpath}${kernel};then true; else false;fi
loglevel=8
panicarg=panic=10
partition=0:1
script=script.bin
scriptaddr=0x4400
setargs=if test -z \\$root\\; then if test \\$bootpath\\ = /boot/; then
root=/dev/mmcblk0p1 rootwait; else root=/dev/mmcblk0p2 rootwait; fi; fi;
setenv bootargs console=${console} root=${root} loglevel=${loglevel}
${panicarg} ${extraargs}
stderr=serial
stdin=serial
stdout=serial
Environment size: 1943/131068 bytes
sun7i# mmc rescan
sun7i# fatload mmc 0 0x6000 bsd.umg
reading bsd.umg
7386496 bytes read in 364 ms (19.4 MiB/s)
sun7i# bootm 0x6000
## Booting kernel from Legacy Image at 6000 ...
Image Name: boot
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size:7386432 Bytes = 7 MiB
Load Address: 4080
Entry Point: 4080
Verifying Checksum ... OK
Loading Kernel Image ... OK
Starting kernel ...
OpenBSD/sunxi booting ...
arg0 0x0 arg1 0x10bb arg2 0x4100
atag core flags 0 pagesize 0 rootdev 0
atag cmdline [sd0i:/bsd -c]
atag mem start 0x4000 size 0x4000
bootfile: sd0i:/bsd
bootargs: -c
memory size derived from u-boot
bootconf.mem[0].address = 4000 pages 262144/0x4000
Allocating page tables
freestart = 0x40f0c000, free_pages = 258292 (0x0003f0f4)
IRQ stack: p0x40f3a000 v0xc0f3a000
ABT stack: p0x40f3b000 v0xc0f3b000
UND stack: p0x40f3c000 v0xc0f3c000
SVC stack: p0x40f3d000 v0xc0f3d000
Creating L1 page table at 0x40f0c000
Mapping kernel
Constructing L2 page tables
undefined page pmap [ using 170664 bytes of bsd ELF symbol table ]
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
Copyright (c) 1995-2014 OpenBSD. All rights reserved. http://www.OpenBSD.org
kernel does not support -c; continuing..
OpenBSD 5.6-current (RAMDISK-SUNXI) #0: Sun Oct 5 13:50:18 AEDT 2014
r...@armv7.jsg.id.au:/usr/src/sys/arch/armv7/compile/RAMDISK-SUNXI
real mem = 1073741824 (1024MB)
avail mem = 1036165120 (988MB)
warning: no entropy supplied by boot loader
mainbus0 at root
cortex0 at mainbus0
ampintc0 at cortex0 nirq 160
cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
sunxi0 at mainbus0: A20
sxipio0 at sunxi0
sxiccmu0 at sunxi0
sxitimer0 at sunxi0: ticktimer 100hz @ 32KHz
sxitimer1 at sunxi0: stattimer 128hz @ 32KHz
sxitimer2 at sunxi0: cntrtimer @ 32KHz
sxidog0 at sunxi0
sxirtc0 at sunxi0
sxiuart0 at sunxi0: console
sxiuart1 at sunxi0
sxiuart2 at sunxi0
sxiuart3 at sunxi0
sxiuart4 at sunxi0
sxiuart5 at sunxi0
sxiuart6 at sunxi0
sxiuart7 at sunxi0
sxie0 at sunxi0, address 02:99:03:c2:d2:6e
Re: armv7: banana pi, Allwinner A20 board
Hi, here is the log using bsd.SUNXI.umg instead of bsd.rd.SUNXI.img. (thanks to Theo) -c invokes UKC, but hangs up at there. -- OpenBSD/sunxi booting ... arg0 0x0 arg1 0x10bb arg2 0x4100 atag core flags 0 pagesize 0 rootdev 0 atag cmdline [sd0i:/bsd -c] atag mem start 0x4000 size 0x4000 bootfile: sd0i:/bsd bootargs: -c memory size derived from u-boot bootconf.mem[0].address = 4000 pages 262144/0x4000 Allocating page tables freestart = 0x40b9a000, free_pages = 259174 (0x0003f466) IRQ stack: p0x40bc8000 v0xc0bc8000 ABT stack: p0x40bc9000 v0xc0bc9000 UND stack: p0x40bca000 v0xc0bca000 SVC stack: p0x40bcb000 v0xc0bcb000 Creating L1 page table at 0x40b9c000 Mapping kernel Constructing L2 page tables undefined page pmap [ using 300196 bytes of bsd ELF symbol table ] Copyright (c) 1982, 1986, 1989, 1991, 1993 The Regents of the University of California. All rights reserved. Copyright (c) 1995-2014 OpenBSD. All rights reserved. http://www.OpenBSD.org User Kernel Config UKC -- SASANO Takayoshi u...@mx5.nisiq.net
Re: armv7: banana pi, Allwinner A20 board
On Sat, Oct 04, 2014 at 06:26:29AM +0900, SASANO Takayoshi wrote: Hi, When using OpenBSD 5.6 (RAMDISK-SUNXI) #3: Sun Aug 31 18:46:49 EDT 2014 could you drop into config (pass -c to boot) and try to disable echi? What shoud I do pass boot -c string to armv7 kernel? On i386/amd64 bootloader simply type it but armv7 uses U-Boot. Tweak uEnv.txt? setenv bootargs sd0i:/bsd -c Note the kernel part in the above isn't used as there isn't a second stage bootloader as you point out. I've put up a recently built ramdisk with the l1 pte change here: http://jsg.id.au/openbsd/bsd.rd.SUNXI.umg
Re: armv7: banana pi, Allwinner A20 board
Hi, I've put up a recently built ramdisk with the l1 pte change here: http://jsg.id.au/openbsd/bsd.rd.SUNXI.umg Thanks but not worked... And, Ethernet PHY(RTL8211E) is recognized as ukphy. I heard that the power of PHY is controlled by GPIO PH23. (see http://www.srchack.org/article.php?story=20140501232036142 it is written in Japanese but maybe good hint) Regards, -- SASANO Takayoshi u...@mx5.nisiq.net [case 1] U-Boot SPL 2014.04-10694-g2ae8b32-dirty (Oct 01 2014 - 17:40:04) Board: Bananapi DRAM: 1024 MiB CPU: 96000Hz, AXI/AHB/APB: 3/2/2 spl: not an uImage at 1600 U-Boot 2014.04-10694-g2ae8b32-dirty (Oct 01 2014 - 17:40:04) Allwinner Technology CPU: Allwinner A20 (SUN7I) Board: Bananapi I2C: ready DRAM: 1 GiB MMC: SUNXI SD/MMC: 0 *** Warning - bad CRC, using default environment In:serial Out: serial Err: serial Net: dwmac.1c5 Hit any key to stop autoboot: 0 reading uEnv.txt 116 bytes read in 16 ms (6.8 KiB/s) Loaded environment from uEnv.txt Running uenvcmd ... reading bsd.umg 7386496 bytes read in 365 ms (19.3 MiB/s) ## Booting kernel from Legacy Image at 6000 ... Image Name: boot Image Type: ARM Linux Kernel Image (uncompressed) Data Size:7386432 Bytes = 7 MiB Load Address: 4080 Entry Point: 4080 Verifying Checksum ... OK Loading Kernel Image ... OK Starting kernel ... OpenBSD/sunxi booting ... arg0 0x0 arg1 0x10bb arg2 0x4100 atag core flags 0 pagesize 0 rootdev 0 atag cmdline [sd0i:/bsd;] atag mem start 0x4000 size 0x4000 bootfile: sd0i:/bsd; bootargs: memory size derived from u-boot bootconf.mem[0].address = 4000 pages 262144/0x4000 Allocating page tables freestart = 0x40f0c000, free_pages = 258292 (0x0003f0f4) IRQ stack: p0x40f3a000 v0xc0f3a000 ABT stack: p0x40f3b000 v0xc0f3b000 UND stack: p0x40f3c000 v0xc0f3c000 SVC stack: p0x40f3d000 v0xc0f3d000 Creating L1 page table at 0x40f0c000 Mapping kernel Constructing L2 page tables undefined page pmap [ using 170664 bytes of bsd ELF symbol table ] Copyright (c) 1982, 1986, 1989, 1991, 1993 The Regents of the University of California. All rights reserved. Copyright (c) 1995-2014 OpenBSD. All rights reserved. http://www.OpenBSD.org OpenBSD 5.6-current (RAMDISK-SUNXI) #0: Sun Oct 5 13:50:18 AEDT 2014 r...@armv7.jsg.id.au:/usr/src/sys/arch/armv7/compile/RAMDISK-SUNXI real mem = 1073741824 (1024MB) avail mem = 1036165120 (988MB) warning: no entropy supplied by boot loader mainbus0 at root cortex0 at mainbus0 ampintc0 at cortex0 nirq 160 cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core) cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache sunxi0 at mainbus0: A20 sxipio0 at sunxi0 sxiccmu0 at sunxi0 sxitimer0 at sunxi0: ticktimer 100hz @ 32KHz sxitimer1 at sunxi0: stattimer 128hz @ 32KHz sxitimer2 at sunxi0: cntrtimer @ 32KHz sxidog0 at sunxi0 sxirtc0 at sunxi0 sxiuart0 at sunxi0: console sxiuart1 at sunxi0 sxiuart2 at sunxi0 sxiuart3 at sunxi0 sxiuart4 at sunxi0 sxiuart5 at sunxi0 sxiuart6 at sunxi0 sxiuart7 at sunxi0 sxie0 at sunxi0, address 02:99:03:c2:d2:6e ukphy0 at sxie0 phy 0: Generic IEEE 802.3u media interface, rev. 5: OUI 0x000732, model 0x0011 ukphy1 at sxie0 phy 1: Generic IEEE 802.3u media interface, rev. 5: OUI 0x000732, model 0x0011 ahci0 at sunxi0 AHCI 1.1 scsibus0 at ahci0: 32 targets ehci0 at sunxi0 pmap_fault_fixup: va c5549000 ftype 2 s pte 7ff8f01e panic: uvm_fault: fault on non-pageable map (0xc0e7f28c, 0xc5549000) Stopped at Debugger+0x4: ldrbr15, [r15, r15, ror r15]! panic+0x18 scp=0xc083a2e8 rlv=0xc08c2ea4 (uvm_fault+0xca8) rsp=0xc0f3eb6c rfp=0xc0f3ec8c uvm_fault+0xc scp=0xc08c2208 rlv=0xc08fe258 (data_abort_handler+0x248) rsp=0xc0f3ec90 rfp=0xc0f3ece4 r10=0xc0f3ece8 r9=0xc0f3d000 r8=0x r7=0xc0e9f764 r6=0x0002 r5=0xc0ebc7b4 r4=0xc5549000 data_abort_handler+0xc scp=0xc08fe01c rlv=0xc08fda24 (address_exception_entry+0x50) rsp=0xc0f3ece8 rfp=0xc0f3ed4c r10=0xc0ebd268 r9=0x1000 r8=0x1000 r7=0x000a r6=0x000c r5=0xc5549000 r4=0x0010 poison_mem+0xc scp=0xc0835b04 rlv=0xc081de6c (malloc+0x2ec) rsp=0xc0f3ed50 rfp=0xc0f3edb8 r5=0xc5549000 r4=0xc5549000 malloc+0x10 scp=0xc081db90 rlv=0xc0808a98 (ehci_init+0x184) rsp=0xc0f3edbc rfp=0xc0f3edf4 r10=0xc5548294 r9=0xc5548000 r8=0x r7=0xc553d0c0 r6=0xc5548014 r5=0xc5548000 r4=0xc0eb9ebc ehci_init+0x10 scp=0xc0808924 rlv=0xc0931f94 (sxiehci_attach+0x110) rsp=0xc0f3edf8 rfp=0xc0f3ee18 r10=0x r9=0xc0f3ee5c r8=0xc0ec0290 r7=0xc553d0c0 r6=0xc5548014 r5=0xc5548000 r4=0x sxiehci_attach+0x10 scp=0xc0931e94 rlv=0xc083092c (config_attach+0x1d4) rsp=0xc0f3ee1c rfp=0xc0f3ee54 r6=0xc0970778 r5=0xc5548014 r4=0xc5548000 config_attach+0xc scp
Re: armv7: banana pi, Allwinner A20 board
On Mon, Oct 06, 2014 at 05:10:58AM +0900, SASANO Takayoshi wrote: Hi, I've put up a recently built ramdisk with the l1 pte change here: http://jsg.id.au/openbsd/bsd.rd.SUNXI.umg Thanks but not worked... And, Ethernet PHY(RTL8211E) is recognized as ukphy. I heard that the power of PHY is controlled by GPIO PH23. (see http://www.srchack.org/article.php?story=20140501232036142 it is written in Japanese but maybe good hint) The phy would be recognised as rgephy(4) if the driver were compiled in. The GPIO phy enable quirk aside it isn't clear if the 'gmac' style ethernet needs a different driver to 'emac'. The sxie(4) driver does not have a match routine it just blindly attaches... Did you try disabling ehci to see if that makes a difference?
Re: armv7: banana pi, Allwinner A20 board
On Thu, Oct 02, 2014 at 09:16:43PM +0200, Patrick Wildt wrote: Hi, I remember that there has been an issue, only seen on Cortex-A7/A15, like the Allwinner A20. The fix for that issue is somewhere here[0]. Try this[1] kernel and have a look if it has the same issue or not. I do not have an A20, so I canât test it, sorry. But Iâll probably buy this[2][3] one once itâs available. \Patrick [0] https://github.com/bitrig/bitrig/commit/f1932308435a4b2c3daf0e880dc0adc829f5803d [1] https://www.blueri.se/bitrig/armv7/20140925/bsd.rd.SUNXI.umg [2] http://www.allnet.de/at/allnet-brand/produkte/neuheiten/p/banana-pi-router-board/ [3] http://www.sinovoip.com.cn/ecp_view.asp?id=554 Here is a diff against -current that handles the L1 pte bits for v7 in the same manner as L2 as suggested by Patrick. Note that the armv7 snapshot won't install correctly at the moment as it is missing etc56.tgz Index: arm/pmap.c === RCS file: /cvs/src/sys/arch/arm/arm/pmap.c,v retrieving revision 1.46 diff -u -p -r1.46 pmap.c --- arm/pmap.c 29 Mar 2014 18:09:28 - 1.46 +++ arm/pmap.c 3 Oct 2014 06:54:02 - @@ -4585,6 +4585,12 @@ pt_entry_t pte_l1_s_coherent; pt_entry_t pte_l2_l_coherent; pt_entry_t pte_l2_s_coherent; +pt_entry_t pte_l1_s_prot_ur; +pt_entry_t pte_l1_s_prot_uw; +pt_entry_t pte_l1_s_prot_kr; +pt_entry_t pte_l1_s_prot_kw; +pt_entry_t pte_l1_s_prot_mask; + pt_entry_t pte_l2_s_prot_ur; pt_entry_t pte_l2_s_prot_uw; pt_entry_t pte_l2_s_prot_kr; @@ -4631,6 +4637,12 @@ pmap_pte_init_generic(void) pte_l2_l_coherent = L2_L_COHERENT_generic; pte_l2_s_coherent = L2_S_COHERENT_generic; + pte_l1_s_prot_ur = L1_S_PROT_UR_generic; + pte_l1_s_prot_uw = L1_S_PROT_UW_generic; + pte_l1_s_prot_kr = L1_S_PROT_KR_generic; + pte_l1_s_prot_kw = L1_S_PROT_KW_generic; + pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; + pte_l2_s_prot_ur = L2_S_PROT_UR_generic; pte_l2_s_prot_uw = L2_S_PROT_UW_generic; pte_l2_s_prot_kr = L2_S_PROT_KR_generic; @@ -4754,6 +4766,12 @@ pmap_pte_init_armv7(void) pte_l2_l_coherent = L2_L_COHERENT_v7; pte_l2_s_coherent = L2_S_COHERENT_v7; + pte_l1_s_prot_ur = L1_S_PROT_UR_v7; + pte_l1_s_prot_uw = L1_S_PROT_UW_v7; + pte_l1_s_prot_kr = L1_S_PROT_KR_v7; + pte_l1_s_prot_kw = L1_S_PROT_KW_v7; + pte_l1_s_prot_mask = L1_S_PROT_MASK_v7; + pte_l2_s_prot_ur = L2_S_PROT_UR_v7; pte_l2_s_prot_uw = L2_S_PROT_UW_v7; pte_l2_s_prot_kr = L2_S_PROT_KR_v7; @@ -4885,6 +4903,12 @@ pmap_pte_init_xscale(void) pte_l1_s_coherent = L1_S_COHERENT_xscale; pte_l2_l_coherent = L2_L_COHERENT_xscale; pte_l2_s_coherent = L2_S_COHERENT_xscale; + + pte_l1_s_prot_ur = L1_S_PROT_UR_xscale; + pte_l1_s_prot_uw = L1_S_PROT_UW_xscale; + pte_l1_s_prot_kr = L1_S_PROT_KR_xscale; + pte_l1_s_prot_kw = L1_S_PROT_KW_xscale; + pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; pte_l2_s_prot_ur = L2_S_PROT_UR_xscale; pte_l2_s_prot_uw = L2_S_PROT_UW_xscale; Index: arm/pmap7.c === RCS file: /cvs/src/sys/arch/arm/arm/pmap7.c,v retrieving revision 1.15 diff -u -p -r1.15 pmap7.c --- arm/pmap7.c 12 Jul 2014 18:44:41 - 1.15 +++ arm/pmap7.c 3 Oct 2014 06:19:40 - @@ -3418,6 +3418,12 @@ pt_entry_t pte_l1_s_coherent; pt_entry_t pte_l2_l_coherent; pt_entry_t pte_l2_s_coherent; +pt_entry_t pte_l1_s_prot_ur; +pt_entry_t pte_l1_s_prot_uw; +pt_entry_t pte_l1_s_prot_kr; +pt_entry_t pte_l1_s_prot_kw; +pt_entry_t pte_l1_s_prot_mask; + pt_entry_t pte_l2_s_prot_ur; pt_entry_t pte_l2_s_prot_uw; pt_entry_t pte_l2_s_prot_kr; @@ -3463,6 +3469,12 @@ pmap_pte_init_generic(void) pte_l2_l_coherent = L2_L_COHERENT_generic; pte_l2_s_coherent = L2_S_COHERENT_generic; + pte_l1_s_prot_ur = L1_S_PROT_UR_generic; + pte_l1_s_prot_uw = L1_S_PROT_UW_generic; + pte_l1_s_prot_kr = L1_S_PROT_KR_generic; + pte_l1_s_prot_kw = L1_S_PROT_KW_generic; + pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; + pte_l2_s_prot_ur = L2_S_PROT_UR_generic; pte_l2_s_prot_uw = L2_S_PROT_UW_generic; pte_l2_s_prot_kr = L2_S_PROT_KR_generic; @@ -3505,6 +3517,12 @@ pmap_pte_init_armv7(void) pte_l1_s_coherent = L1_S_COHERENT_v7; pte_l2_l_coherent = L2_L_COHERENT_v7; pte_l2_s_coherent = L2_S_COHERENT_v7; + + pte_l1_s_prot_ur = L1_S_PROT_UR_v7; + pte_l1_s_prot_uw = L1_S_PROT_UW_v7; + pte_l1_s_prot_kr = L1_S_PROT_KR_v7; + pte_l1_s_prot_kw = L1_S_PROT_KW_v7; + pte_l1_s_prot_mask = L1_S_PROT_MASK_v7; pte_l2_s_prot_ur = L2_S_PROT_UR_v7; pte_l2_s_prot_uw = L2_S_PROT_UW_v7; Index: include/pmap.h
Re: armv7: banana pi, Allwinner A20 board
Hi, When using OpenBSD 5.6 (RAMDISK-SUNXI) #3: Sun Aug 31 18:46:49 EDT 2014 could you drop into config (pass -c to boot) and try to disable echi? What shoud I do pass boot -c string to armv7 kernel? On i386/amd64 bootloader simply type it but armv7 uses U-Boot. Tweak uEnv.txt? -- SASANO Takayoshi u...@mx5.nisiq.net
armv7: banana pi, Allwinner A20 board
Hello, I tried bsd.rd.SUNXI.umg snapshot on Banana Pi, cheap Allwinner A20 board like Raspberry Pi (see http://www.lemaker.org/). It booted but something wrong. Arch Linux (for Banana Pi) works fine so I think the board is not broken. This is my first OpenBSD/armv7 experience and I don't know what is happening. What can I do for solving this problem? -- SASANO Takayoshi u...@mx5.nisiq.net [uEnv.txt] mmcboot=mmc rescan; fatload mmc 0 0x6000 bsd.umg bootm 0x6000; bootargs=sd0a:/bsd; uenvcmd=run mmcboot; [1st try - hang up] U-Boot SPL 2014.04-10694-g2ae8b32-dirty (Oct 01 2014 - 17:40:04) Board: Bananapi DRAM: 1024 MiB CPU: 96000Hz, AXI/AHB/APB: 3/2/2 spl: not an uImage at 1600 U-Boot 2014.04-10694-g2ae8b32-dirty (Oct 01 2014 - 17:40:04) Allwinner Technology CPU: Allwinner A20 (SUN7I) Board: Bananapi I2C: ready DRAM: 1 GiB MMC: SUNXI SD/MMC: 0 *** Warning - bad CRC, using default environment In:serial Out: serial Err: serial Net: dwmac.1c5 Hit any key to stop autoboot: 0 reading uEnv.txt 116 bytes read in 16 ms (6.8 KiB/s) Loaded environment from uEnv.txt Running uenvcmd ... reading bsd.umg 7387788 bytes read in 367 ms (19.2 MiB/s) ## Booting kernel from Legacy Image at 6000 ... Image Name: boot Image Type: ARM Linux Kernel Image (uncompressed) Data Size:7387724 Bytes = 7 MiB Load Address: 4080 Entry Point: 4080 Verifying Checksum ... OK Loading Kernel Image ... OK Starting kernel ... OpenBSD/sunxi booting ... arg0 0x0 arg1 0x10bb arg2 0x4100 atag core flags 0 pagesize 0 rootdev 0 atag cmdline [sd0a:/bsd;] atag mem start 0x4000 size 0x4000 bootfile: sd0a:/bsd; bootargs: memory size derived from u-boot bootconf.mem[0].address = 4000 pages 262144/0x4000 Allocating page tables freestart = 0x40f0c000, free_pages = 258292 (0x0003f0f4) IRQ stack: p0x40f3a000 v0xc0f3a000 ABT stack: p0x40f3b000 v0xc0f3b000 UND stack: p0x40f3c000 v0xc0f3c000 SVC stack: p0x40f3d000 v0xc0f3d000 Creating L1 page table at 0x40f0c000 Mapping kernel Constructing L2 page tables undefined page pmap [ using 169296 bytes of bsd ELF symbol table ] Copyright (c) 1982, 1986, 1989, 1991, 1993 The Regents of the University of California. All rights reserved. Copyright (c) 1995-2014 OpenBSD. All rights reserved. http://www.OpenBSD.org OpenBSD 5.6 (RAMDISK-SUNXI) #3: Sun Aug 31 18:46:49 EDT 2014 r...@pandaes.in.nickh.org:/usr/src/sys/arch/armv7/compile/RAMDISK-SUNXI real mem = 1073741824 (1024MB) avail mem = 1036165120 (988MB) warning: no entropy supplied by boot loader mainbus0 at root cortex0 at mainbus0 ampintc0 at cortex0 nirq 160 cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core) cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache sunxi0 at mainbus0: A20 sxipio0 at sunxi0 sxiccmu0 at sunxi0 sxitimer0 at sunxi0: ticktimer 100hz @ 32KHz sxitimer1 at sunxi0: stattimer 128hz @ 32KHz sxitimer2 at sunxi0: cntrtimer @ 32KHz sxidog0 at sunxi0 sxirtc0 at sunxi0 sxiuart0 at sunxi0: console sxiuart1 at sunxi0 sxiuart2 at sunxi0 sxiuart3 at sunxi0 sxiuart4 at sunxi0 sxiuart5 at sunxi0 sxiuart6 at sunxi0 sxiuart7 at sunxi0 sxie0 at sunxi0, address 02:99:03:c2:d2:6e ukphy0 at sxie0 phy 0: Generic IEEE 802.3u media interface, rev. 5: OUI 0x000732, model 0x0011 ukphy1 at sxie0 phy 1: Generic IEEE 802.3u media interface, rev. 5: OUI 0x000732, model 0x0011 ahci0 at sunxi0 AHCI 1.1 scsibus0 at ahci0: 32 targets ehci0 at sunxi0 usb0 at ehci0: USB revision 2.0 uhub0 at usb0 Allwinner EHCI root hub rev 2.00/1.00 addr 1 ehci1 at sunxi0 usb1 at ehci1: USB revision 2.0 uhub1 at usb1 Allwinner EHCI root hub rev 2.00/1.00 addr 1 (hang up here) [2nd try - ddb invoked] U-Boot SPL 2014.04-10694-g2ae8b32-dirty (Oct 01 2014 - 17:40:04) Board: Bananapi DRAM: 1024 MiB CPU: 96000Hz, AXI/AHB/APB: 3/2/2 spl: not an uImage at 1600 U-Boot 2014.04-10694-g2ae8b32-dirty (Oct 01 2014 - 17:40:04) Allwinner Technology CPU: Allwinner A20 (SUN7I) Board: Bananapi I2C: ready DRAM: 1 GiB MMC: SUNXI SD/MMC: 0 *** Warning - bad CRC, using default environment In:serial Out: serial Err: serial Net: dwmac.1c5 Hit any key to stop autoboot: 0 reading uEnv.txt 116 bytes read in 16 ms (6.8 KiB/s) Loaded environment from uEnv.txt Running uenvcmd ... reading bsd.umg 7387788 bytes read in 370 ms (19 MiB/s) ## Booting kernel from Legacy Image at 6000 ... Image Name: boot Image Type: ARM Linux Kernel Image (uncompressed) Data Size:7387724 Bytes = 7 MiB Load Address: 4080 Entry Point: 4080 Verifying Checksum ... OK Loading Kernel Image ... OK Starting kernel ... OpenBSD/sunxi booting ... arg0 0x0 arg1 0x10bb arg2 0x4100 atag core flags 0 pagesize 0 rootdev 0 atag cmdline [sd0a:/bsd;] atag mem start 0x4000 size
Re: armv7: banana pi, Allwinner A20 board
Hi, I remember that there has been an issue, only seen on Cortex-A7/A15, like the Allwinner A20. The fix for that issue is somewhere here[0]. Try this[1] kernel and have a look if it has the same issue or not. I do not have an A20, so I can’t test it, sorry. But I’ll probably buy this[2][3] one once it’s available. \Patrick [0] https://github.com/bitrig/bitrig/commit/f1932308435a4b2c3daf0e880dc0adc829f5803d [1] https://www.blueri.se/bitrig/armv7/20140925/bsd.rd.SUNXI.umg [2] http://www.allnet.de/at/allnet-brand/produkte/neuheiten/p/banana-pi-router-board/ [3] http://www.sinovoip.com.cn/ecp_view.asp?id=554 Am 02.10.2014 um 20:56 schrieb SASANO Takayoshi u...@mx5.nisiq.net: Hello, I tried bsd.rd.SUNXI.umg snapshot on Banana Pi, cheap Allwinner A20 board like Raspberry Pi (see http://www.lemaker.org/). It booted but something wrong. Arch Linux (for Banana Pi) works fine so I think the board is not broken. This is my first OpenBSD/armv7 experience and I don't know what is happening. What can I do for solving this problem? -- SASANO Takayoshi u...@mx5.nisiq.net [uEnv.txt] mmcboot=mmc rescan; fatload mmc 0 0x6000 bsd.umg bootm 0x6000; bootargs=sd0a:/bsd; uenvcmd=run mmcboot; [1st try - hang up] U-Boot SPL 2014.04-10694-g2ae8b32-dirty (Oct 01 2014 - 17:40:04) Board: Bananapi DRAM: 1024 MiB CPU: 96000Hz, AXI/AHB/APB: 3/2/2 spl: not an uImage at 1600 U-Boot 2014.04-10694-g2ae8b32-dirty (Oct 01 2014 - 17:40:04) Allwinner Technology CPU: Allwinner A20 (SUN7I) Board: Bananapi I2C: ready DRAM: 1 GiB MMC: SUNXI SD/MMC: 0 *** Warning - bad CRC, using default environment In:serial Out: serial Err: serial Net: dwmac.1c5 Hit any key to stop autoboot: 0 reading uEnv.txt 116 bytes read in 16 ms (6.8 KiB/s) Loaded environment from uEnv.txt Running uenvcmd ... reading bsd.umg 7387788 bytes read in 367 ms (19.2 MiB/s) ## Booting kernel from Legacy Image at 6000 ... Image Name: boot Image Type: ARM Linux Kernel Image (uncompressed) Data Size:7387724 Bytes = 7 MiB Load Address: 4080 Entry Point: 4080 Verifying Checksum ... OK Loading Kernel Image ... OK Starting kernel ... OpenBSD/sunxi booting ... arg0 0x0 arg1 0x10bb arg2 0x4100 atag core flags 0 pagesize 0 rootdev 0 atag cmdline [sd0a:/bsd;] atag mem start 0x4000 size 0x4000 bootfile: sd0a:/bsd; bootargs: memory size derived from u-boot bootconf.mem[0].address = 4000 pages 262144/0x4000 Allocating page tables freestart = 0x40f0c000, free_pages = 258292 (0x0003f0f4) IRQ stack: p0x40f3a000 v0xc0f3a000 ABT stack: p0x40f3b000 v0xc0f3b000 UND stack: p0x40f3c000 v0xc0f3c000 SVC stack: p0x40f3d000 v0xc0f3d000 Creating L1 page table at 0x40f0c000 Mapping kernel Constructing L2 page tables undefined page pmap [ using 169296 bytes of bsd ELF symbol table ] Copyright (c) 1982, 1986, 1989, 1991, 1993 The Regents of the University of California. All rights reserved. Copyright (c) 1995-2014 OpenBSD. All rights reserved. http://www.OpenBSD.org OpenBSD 5.6 (RAMDISK-SUNXI) #3: Sun Aug 31 18:46:49 EDT 2014 r...@pandaes.in.nickh.org:/usr/src/sys/arch/armv7/compile/RAMDISK-SUNXI real mem = 1073741824 (1024MB) avail mem = 1036165120 (988MB) warning: no entropy supplied by boot loader mainbus0 at root cortex0 at mainbus0 ampintc0 at cortex0 nirq 160 cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core) cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache sunxi0 at mainbus0: A20 sxipio0 at sunxi0 sxiccmu0 at sunxi0 sxitimer0 at sunxi0: ticktimer 100hz @ 32KHz sxitimer1 at sunxi0: stattimer 128hz @ 32KHz sxitimer2 at sunxi0: cntrtimer @ 32KHz sxidog0 at sunxi0 sxirtc0 at sunxi0 sxiuart0 at sunxi0: console sxiuart1 at sunxi0 sxiuart2 at sunxi0 sxiuart3 at sunxi0 sxiuart4 at sunxi0 sxiuart5 at sunxi0 sxiuart6 at sunxi0 sxiuart7 at sunxi0 sxie0 at sunxi0, address 02:99:03:c2:d2:6e ukphy0 at sxie0 phy 0: Generic IEEE 802.3u media interface, rev. 5: OUI 0x000732, model 0x0011 ukphy1 at sxie0 phy 1: Generic IEEE 802.3u media interface, rev. 5: OUI 0x000732, model 0x0011 ahci0 at sunxi0 AHCI 1.1 scsibus0 at ahci0: 32 targets ehci0 at sunxi0 usb0 at ehci0: USB revision 2.0 uhub0 at usb0 Allwinner EHCI root hub rev 2.00/1.00 addr 1 ehci1 at sunxi0 usb1 at ehci1: USB revision 2.0 uhub1 at usb1 Allwinner EHCI root hub rev 2.00/1.00 addr 1 (hang up here) [2nd try - ddb invoked] U-Boot SPL 2014.04-10694-g2ae8b32-dirty (Oct 01 2014 - 17:40:04) Board: Bananapi DRAM: 1024 MiB CPU: 96000Hz, AXI/AHB/APB: 3/2/2 spl: not an uImage at 1600 U-Boot 2014.04-10694-g2ae8b32-dirty (Oct 01 2014 - 17:40:04) Allwinner Technology CPU: Allwinner A20 (SUN7I) Board
Re: armv7: banana pi, Allwinner A20 board
iirc this is the core of the issue: The L1 Section descriptors access permissions are still the old ones, not the v7 versions. arm/include/pmap.h: #define L1_S_PROT_U (L1_S_AP(AP_U)) #define L1_S_PROT_W (L1_S_AP(AP_W)) #define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) #define L1_S_PROT(ku, pr) ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ (((pr) VM_PROT_WRITE) ? L1_S_PROT_W : 0)) arm/include/pte.h: #define L1_S_AP(x) ((x) 10) /* access permissions */ #define L1_S_V7_AP(x) x) 0x4) 13) | (((x) 3) 10)) /* AP */ \Patrick Am 02.10.2014 um 21:16 schrieb Patrick Wildt m...@patrick-wildt.de: Hi, I remember that there has been an issue, only seen on Cortex-A7/A15, like the Allwinner A20. The fix for that issue is somewhere here[0]. Try this[1] kernel and have a look if it has the same issue or not. I do not have an A20, so I can’t test it, sorry. But I’ll probably buy this[2][3] one once it’s available. \Patrick [0] https://github.com/bitrig/bitrig/commit/f1932308435a4b2c3daf0e880dc0adc829f5803d [1] https://www.blueri.se/bitrig/armv7/20140925/bsd.rd.SUNXI.umg [2] http://www.allnet.de/at/allnet-brand/produkte/neuheiten/p/banana-pi-router-board/ [3] http://www.sinovoip.com.cn/ecp_view.asp?id=554 Am 02.10.2014 um 20:56 schrieb SASANO Takayoshi u...@mx5.nisiq.net: Hello, I tried bsd.rd.SUNXI.umg snapshot on Banana Pi, cheap Allwinner A20 board like Raspberry Pi (see http://www.lemaker.org/). It booted but something wrong. Arch Linux (for Banana Pi) works fine so I think the board is not broken. This is my first OpenBSD/armv7 experience and I don't know what is happening. What can I do for solving this problem? -- SASANO Takayoshi u...@mx5.nisiq.net [uEnv.txt] mmcboot=mmc rescan; fatload mmc 0 0x6000 bsd.umg bootm 0x6000; bootargs=sd0a:/bsd; uenvcmd=run mmcboot; [1st try - hang up] U-Boot SPL 2014.04-10694-g2ae8b32-dirty (Oct 01 2014 - 17:40:04) Board: Bananapi DRAM: 1024 MiB CPU: 96000Hz, AXI/AHB/APB: 3/2/2 spl: not an uImage at 1600 U-Boot 2014.04-10694-g2ae8b32-dirty (Oct 01 2014 - 17:40:04) Allwinner Technology CPU: Allwinner A20 (SUN7I) Board: Bananapi I2C: ready DRAM: 1 GiB MMC: SUNXI SD/MMC: 0 *** Warning - bad CRC, using default environment In:serial Out: serial Err: serial Net: dwmac.1c5 Hit any key to stop autoboot: 0 reading uEnv.txt 116 bytes read in 16 ms (6.8 KiB/s) Loaded environment from uEnv.txt Running uenvcmd ... reading bsd.umg 7387788 bytes read in 367 ms (19.2 MiB/s) ## Booting kernel from Legacy Image at 6000 ... Image Name: boot Image Type: ARM Linux Kernel Image (uncompressed) Data Size:7387724 Bytes = 7 MiB Load Address: 4080 Entry Point: 4080 Verifying Checksum ... OK Loading Kernel Image ... OK Starting kernel ... OpenBSD/sunxi booting ... arg0 0x0 arg1 0x10bb arg2 0x4100 atag core flags 0 pagesize 0 rootdev 0 atag cmdline [sd0a:/bsd;] atag mem start 0x4000 size 0x4000 bootfile: sd0a:/bsd; bootargs: memory size derived from u-boot bootconf.mem[0].address = 4000 pages 262144/0x4000 Allocating page tables freestart = 0x40f0c000, free_pages = 258292 (0x0003f0f4) IRQ stack: p0x40f3a000 v0xc0f3a000 ABT stack: p0x40f3b000 v0xc0f3b000 UND stack: p0x40f3c000 v0xc0f3c000 SVC stack: p0x40f3d000 v0xc0f3d000 Creating L1 page table at 0x40f0c000 Mapping kernel Constructing L2 page tables undefined page pmap [ using 169296 bytes of bsd ELF symbol table ] Copyright (c) 1982, 1986, 1989, 1991, 1993 The Regents of the University of California. All rights reserved. Copyright (c) 1995-2014 OpenBSD. All rights reserved. http://www.OpenBSD.org OpenBSD 5.6 (RAMDISK-SUNXI) #3: Sun Aug 31 18:46:49 EDT 2014 r...@pandaes.in.nickh.org:/usr/src/sys/arch/armv7/compile/RAMDISK-SUNXI real mem = 1073741824 (1024MB) avail mem = 1036165120 (988MB) warning: no entropy supplied by boot loader mainbus0 at root cortex0 at mainbus0 ampintc0 at cortex0 nirq 160 cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core) cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache sunxi0 at mainbus0: A20 sxipio0 at sunxi0 sxiccmu0 at sunxi0 sxitimer0 at sunxi0: ticktimer 100hz @ 32KHz sxitimer1 at sunxi0: stattimer 128hz @ 32KHz sxitimer2 at sunxi0: cntrtimer @ 32KHz sxidog0 at sunxi0 sxirtc0 at sunxi0 sxiuart0 at sunxi0: console sxiuart1 at sunxi0 sxiuart2 at sunxi0 sxiuart3 at sunxi0 sxiuart4 at sunxi0 sxiuart5 at sunxi0 sxiuart6 at sunxi0 sxiuart7 at sunxi0 sxie0 at sunxi0, address 02:99:03:c2:d2:6e ukphy0 at sxie0 phy 0: Generic IEEE 802.3u media interface, rev. 5: OUI 0x000732, model 0x0011 ukphy1 at sxie0 phy 1: Generic IEEE 802.3u media
Re: armv7: banana pi, Allwinner A20 board
Hi, Try this[1] kernel and have a look if it has the same issue or not. Kernel did not started... U-Boot says checksum is ok, so maybe .umg file is not corrupted. Regards, -- SASANO Takayoshi u...@mx5.nisiq.net U-Boot SPL 2014.04-10694-g2ae8b32-dirty (Oct 01 2014 - 17:40:04) Board: Bananapi DRAM: 1024 MiB CPU: 96000Hz, AXI/AHB/APB: 3/2/2 spl: not an uImage at 1600 U-Boot 2014.04-10694-g2ae8b32-dirty (Oct 01 2014 - 17:40:04) Allwinner Technology CPU: Allwinner A20 (SUN7I) Board: Bananapi I2C: ready DRAM: 1 GiB MMC: SUNXI SD/MMC: 0 *** Warning - bad CRC, using default environment In:serial Out: serial Err: serial Net: dwmac.1c5 Hit any key to stop autoboot: 0 reading uEnv.txt 116 bytes read in 16 ms (6.8 KiB/s) Loaded environment from uEnv.txt Running uenvcmd ... reading bsd.umg 9584704 bytes read in 473 ms (19.3 MiB/s) ## Booting kernel from Legacy Image at 6000 ... Image Name: boot Image Type: ARM Linux Kernel Image (uncompressed) Data Size:9584640 Bytes = 9.1 MiB Load Address: 4080 Entry Point: 4080 Verifying Checksum ... OK Loading Kernel Image ... OK Starting kernel ... (halt here)
Re: armv7: banana pi, Allwinner A20 board
SASANO Takayoshi uaa at mx5.nisiq.net writes: Try this[1] kernel and have a look if it has the same issue or not. Kernel did not started... U-Boot says checksum is ok, so maybe .umg file is not corrupted. When using OpenBSD 5.6 (RAMDISK-SUNXI) #3: Sun Aug 31 18:46:49 EDT 2014 could you drop into config (pass -c to boot) and try to disable echi?
Re: armv7: banana pi, Allwinner A20 board
On Thu, Oct 02, 2014 at 10:01:59PM +, Alexey Suslikov wrote: SASANO Takayoshi uaa at mx5.nisiq.net writes: Try this[1] kernel and have a look if it has the same issue or not. Kernel did not started... U-Boot says checksum is ok, so maybe .umg file is not corrupted. When using OpenBSD 5.6 (RAMDISK-SUNXI) #3: Sun Aug 31 18:46:49 EDT 2014 could you drop into config (pass -c to boot) and try to disable echi? ITYM 'disable ehci' there.. Landry
Re: Allwinner
On Fri, Oct 11, 2013 at 11:46:39PM +0300, Artturi Alm wrote: On 10/11/13 20:39, Markus Hennecke wrote: On Sat, 5 Oct 2013, Artturi Alm wrote: Current version attached, extract to /sys/arch/armv7 and read the short notes file, no more out of allwinner/ patches needed thanks to armv7. A20 support still needs a workaround under /sys/arch/arm/cortex/ which i didn't include as i think support is still 'subtly' broken anyway.. And ahci is still not working for me, but there's a couple of new drivers included. Ethernet driver survived make build of userland with /usr/src mounted via nfs, fwiw. Now this is totally usable for me as-is already, so any feedback is welcome, be it finding out possible bugs and/or confirming it's working. Great work! I made a few changes to fix the timer code for the A20 CPU, the diff to your code is attached. With this I am almost booting the kernel on a cubieboard 2: Copyright (c) 1982, 1986, 1989, 1991, 1993 The Regents of the University of California. All rights reserved. Copyright (c) 1995-2013 OpenBSD. All rights reserved. http://www.OpenBSD.org OpenBSD 5.4-current (GENERIC-ALLWINNER) #22: Fri Oct 11 19:17:11 CEST 2013 mar...@antigone.markus-hennecke.de:/usr/src/sys/arch/armv7/compile/GENERIC-ALLWINNER real mem = 1073741824 (1024MB) avail mem = 1040007168 (991MB) mainbus0 at root cortex0 at mainbus0 ampintc0 at cortex0 nirq 160 cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core) cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache allwinner0 at mainbus0: A20 awpio0 at allwinner0 awccmu0 at allwinner0 awtimer0 at allwinner0: tick rate 32KHz hz 100 stat rate 32KHz stathz 128 counter 24000 KHz awdog0 at allwinner0 awrtc0 at allwinner0 awuart0 at allwinner0: console awe0 at allwinner0 awe0: address 00:00:00:00:00:00 rlphy0 at awe0 phy 1: RTL8201L 10/100 PHY, rev. 1 ahci0 at allwinner0 GHC 0x8000AE AHCI 1.1 ahci0: capabilities 0x6726ff80NCQ,SSNTF,SALP,SAL,SCLO,SAM,SPM,PMD,SSC,PSC,CCCS, 1 ports, 32 cmds, gen 1 (1.5Gbps) and 2 (3Gbps) ahci0: ports implemented: 0x0001 ahci0.0: port reset ahci0: no device detected on port 0 scsibus0 at ahci0: 32 targets ehci0 at allwinner0 usb0 at ehci0: USB revision 2.0 uhub0 at usb0 Allwinner EHCI root hub rev 2.00/1.00 addr 1 ehci1 at allwinner0 usb1 at ehci1: USB revision 2.0 uhub1 at usb1 Allwinner EHCI root hub rev 2.00/1.00 addr 1 gpio0 at awpio0: 18 pins gpio1 at awpio0: 24 pins gpio2 at awpio0: 25 pins gpio3 at awpio0: 28 pins gpio4 at awpio0: 12 pins gpio5 at awpio0: 6 pins gpio6 at awpio0: 12 pins gpio7 at awpio0: 28 pins gpio8 at awpio0: 22 pins /dev/ksyms: Symbol table not valid. Here the output stops, I will look into that later. At this point I am unable to figure out how to set the ethaddr in the u-boot version I am using. setenv ethaddr xx:xx:xx:xx:xx:xx doesn't seem to have any effect. Kind regards Markus Hi, Thanks for the patch, it looks correct when compared to the user manual and shows how ugly sources may get when not paid enough attention, will fix the whitespaces there also. Note that Cortex-A7 should support agtimer found in arch/arm/cortex, which would allow cleaning up awtimer.c from the 'added on'-kind of hacks to support A20, priorities have kept me from trying that one out so far. To allow it to boot further you would have to change ICP_ADDR and ICD_ADDR in ampintc, iirc. possibly 0x1000 and 0x2000 respectively, which is not the fix that would ever get commited even if allwinner would be on cvs, as it'll break Cortex-A9, and unfortunately, masking by cpu is not working option either, there is example of where it would fail already (exynos). FDT is the only clean solution i can think of, when there is priority on keeping arch/arm/cortex free of SoC-dependent code. About ethaddr, have you tried pinging another host from u-boot? Does your u-boot support emac? the one i initially downloaded for cubieboard2 did not iirc., if you can boot the bsd.umg over network, and still get 00:00:00:00:00:00, i will power up my cb2 to fix awe, as it's so far untested on A20 afaik. -Artturi I'm going to commit the initial allwinner diff along with Martin's diff tomorrow unless strong objection is raised. This needs to be worked on intree instead of letting it rot on the mailinglist. -- Cheers, Jasper Stay Hungry. Stay Foolish
Re: Allwinner
On 10/21/13 18:04, Jasper Lievisse Adriaanse wrote: On Fri, Oct 11, 2013 at 11:46:39PM +0300, Artturi Alm wrote: On 10/11/13 20:39, Markus Hennecke wrote: On Sat, 5 Oct 2013, Artturi Alm wrote: Current version attached, extract to /sys/arch/armv7 and read the short notes file, no more out of allwinner/ patches needed thanks to armv7. A20 support still needs a workaround under /sys/arch/arm/cortex/ which i didn't include as i think support is still 'subtly' broken anyway.. And ahci is still not working for me, but there's a couple of new drivers included. Ethernet driver survived make build of userland with /usr/src mounted via nfs, fwiw. Now this is totally usable for me as-is already, so any feedback is welcome, be it finding out possible bugs and/or confirming it's working. Great work! I made a few changes to fix the timer code for the A20 CPU, the diff to your code is attached. With this I am almost booting the kernel on a cubieboard 2: Copyright (c) 1982, 1986, 1989, 1991, 1993 The Regents of the University of California. All rights reserved. Copyright (c) 1995-2013 OpenBSD. All rights reserved. http://www.OpenBSD.org OpenBSD 5.4-current (GENERIC-ALLWINNER) #22: Fri Oct 11 19:17:11 CEST 2013 mar...@antigone.markus-hennecke.de:/usr/src/sys/arch/armv7/compile/GENERIC-ALLWINNER real mem = 1073741824 (1024MB) avail mem = 1040007168 (991MB) mainbus0 at root cortex0 at mainbus0 ampintc0 at cortex0 nirq 160 cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core) cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache allwinner0 at mainbus0: A20 awpio0 at allwinner0 awccmu0 at allwinner0 awtimer0 at allwinner0: tick rate 32KHz hz 100 stat rate 32KHz stathz 128 counter 24000 KHz awdog0 at allwinner0 awrtc0 at allwinner0 awuart0 at allwinner0: console awe0 at allwinner0 awe0: address 00:00:00:00:00:00 rlphy0 at awe0 phy 1: RTL8201L 10/100 PHY, rev. 1 ahci0 at allwinner0 GHC 0x8000AE AHCI 1.1 ahci0: capabilities 0x6726ff80NCQ,SSNTF,SALP,SAL,SCLO,SAM,SPM,PMD,SSC,PSC,CCCS, 1 ports, 32 cmds, gen 1 (1.5Gbps) and 2 (3Gbps) ahci0: ports implemented: 0x0001 ahci0.0: port reset ahci0: no device detected on port 0 scsibus0 at ahci0: 32 targets ehci0 at allwinner0 usb0 at ehci0: USB revision 2.0 uhub0 at usb0 Allwinner EHCI root hub rev 2.00/1.00 addr 1 ehci1 at allwinner0 usb1 at ehci1: USB revision 2.0 uhub1 at usb1 Allwinner EHCI root hub rev 2.00/1.00 addr 1 gpio0 at awpio0: 18 pins gpio1 at awpio0: 24 pins gpio2 at awpio0: 25 pins gpio3 at awpio0: 28 pins gpio4 at awpio0: 12 pins gpio5 at awpio0: 6 pins gpio6 at awpio0: 12 pins gpio7 at awpio0: 28 pins gpio8 at awpio0: 22 pins /dev/ksyms: Symbol table not valid. Here the output stops, I will look into that later. At this point I am unable to figure out how to set the ethaddr in the u-boot version I am using. setenv ethaddr xx:xx:xx:xx:xx:xx doesn't seem to have any effect. Kind regards Markus Hi, Thanks for the patch, it looks correct when compared to the user manual and shows how ugly sources may get when not paid enough attention, will fix the whitespaces there also. Note that Cortex-A7 should support agtimer found in arch/arm/cortex, which would allow cleaning up awtimer.c from the 'added on'-kind of hacks to support A20, priorities have kept me from trying that one out so far. To allow it to boot further you would have to change ICP_ADDR and ICD_ADDR in ampintc, iirc. possibly 0x1000 and 0x2000 respectively, which is not the fix that would ever get commited even if allwinner would be on cvs, as it'll break Cortex-A9, and unfortunately, masking by cpu is not working option either, there is example of where it would fail already (exynos). FDT is the only clean solution i can think of, when there is priority on keeping arch/arm/cortex free of SoC-dependent code. About ethaddr, have you tried pinging another host from u-boot? Does your u-boot support emac? the one i initially downloaded for cubieboard2 did not iirc., if you can boot the bsd.umg over network, and still get 00:00:00:00:00:00, i will power up my cb2 to fix awe, as it's so far untested on A20 afaik. -Artturi I'm going to commit the initial allwinner diff along with Martin's diff tomorrow unless strong objection is raised. This needs to be worked on intree instead of letting it rot on the mailinglist. I got around 2,5k line diff to previous allwinner.tar.gz already. It has the diff by Markus to fix timer on A20, besides major cleanup on awtimer(mainly in _attach()) that definately should go in. It has also ugly hacks to support ethernetusb on Hackberry, possibly doable in not so ugly way before FDT with boardids. And dma controller usable as is likely to just ethernet driver, which still has align issues with it so it's disabled there, and fixed the ethernet to use second fifo on tx. possibly i forgot something. I'll run a round of tests on what i have now once i've
Re: Allwinner
On Sat, 12 Oct 2013, Patrick Wildt wrote: Am 11.10.2013 um 22:46 schrieb Artturi Alm artturi@gmail.com: On 10/11/13 20:39, Markus Hennecke wrote: About ethaddr, have you tried pinging another host from u-boot? Does your u-boot support emac? the one i initially downloaded for cubieboard2 did not iirc., if you can boot the bsd.umg over network, and still get 00:00:00:00:00:00, i will power up my cb2 to fix awe, as it's so far untested on A20 afaik. Maybe Allwinner stores the mac address in some magic register? i.MX6 does that. u-boot might be able to push the ethaddr env using the FDT. I took the u-boot from a linux sd-card image, it supports emac: U-Boot 2013.07-07795-g645e901-dirty (Aug 18 2013 - 16:15:54) Allwinner Technology CPU: Allwinner A20 (SUN7I) Board: Cubieboard2 I2C: ready DRAM: 1 GiB MMC: SUNXI SD/MMC: 0 *** Warning - bad CRC, using default environment In:serial Out: serial Err: serial Net: emac Hit any key to stop autoboot: 0 It will set the mac address as soon as I do network stuff from within u-boot, not if only booting the bsd.umg. So looks like it works within the limited options we have right now. Kind regards Markus
Re: Allwinner
On Sat, 5 Oct 2013, Artturi Alm wrote:
Current version attached, extract to /sys/arch/armv7 and read the short
notes file, no more out of allwinner/ patches needed thanks to armv7.
A20 support still needs a workaround under /sys/arch/arm/cortex/ which
i didn't include as i think support is still 'subtly' broken anyway..
And ahci is still not working for me, but there's a couple of
new drivers included.
Ethernet driver survived make build of userland with /usr/src mounted
via nfs, fwiw.
Now this is totally usable for me as-is already, so any feedback is
welcome, be it finding out possible bugs and/or confirming it's working.
Great work! I made a few changes to fix the timer code for the A20 CPU,
the diff to your code is attached. With this I am almost booting the
kernel on a cubieboard 2:
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
Copyright (c) 1995-2013 OpenBSD. All rights reserved. http://www.OpenBSD.org
OpenBSD 5.4-current (GENERIC-ALLWINNER) #22: Fri Oct 11 19:17:11 CEST 2013
mar...@antigone.markus-hennecke.de:/usr/src/sys/arch/armv7/compile/GENERIC-ALLWINNER
real mem = 1073741824 (1024MB)
avail mem = 1040007168 (991MB)
mainbus0 at root
cortex0 at mainbus0
ampintc0 at cortex0 nirq 160
cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
allwinner0 at mainbus0: A20
awpio0 at allwinner0
awccmu0 at allwinner0
awtimer0 at allwinner0: tick rate 32KHz hz 100 stat rate 32KHz stathz 128
counter 24000 KHz
awdog0 at allwinner0
awrtc0 at allwinner0
awuart0 at allwinner0: console
awe0 at allwinner0
awe0: address 00:00:00:00:00:00
rlphy0 at awe0 phy 1: RTL8201L 10/100 PHY, rev. 1
ahci0 at allwinner0 GHC 0x8000AE AHCI 1.1
ahci0: capabilities
0x6726ff80NCQ,SSNTF,SALP,SAL,SCLO,SAM,SPM,PMD,SSC,PSC,CCCS, 1 ports, 32 cmds,
gen 1 (1.5Gbps) and 2 (3Gbps)
ahci0: ports implemented: 0x0001
ahci0.0: port reset
ahci0: no device detected on port 0
scsibus0 at ahci0: 32 targets
ehci0 at allwinner0
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 Allwinner EHCI root hub rev 2.00/1.00 addr 1
ehci1 at allwinner0
usb1 at ehci1: USB revision 2.0
uhub1 at usb1 Allwinner EHCI root hub rev 2.00/1.00 addr 1
gpio0 at awpio0: 18 pins
gpio1 at awpio0: 24 pins
gpio2 at awpio0: 25 pins
gpio3 at awpio0: 28 pins
gpio4 at awpio0: 12 pins
gpio5 at awpio0: 6 pins
gpio6 at awpio0: 12 pins
gpio7 at awpio0: 28 pins
gpio8 at awpio0: 22 pins
/dev/ksyms: Symbol table not valid.
Here the output stops, I will look into that later. At this point I am
unable to figure out how to set the ethaddr in the u-boot version I am
using. setenv ethaddr xx:xx:xx:xx:xx:xx doesn't seem to have any effect.
Kind regards
Markusdiff -u ./GENERIC-ALLWINNER /usr/src/sys/arch/armv7/allwinner/GENERIC-ALLWINNER
--- ./GENERIC-ALLWINNER Sat Oct 5 13:31:15 2013
+++ /usr/src/sys/arch/armv7/allwinner/GENERIC-ALLWINNER Fri Oct 11 19:17:46 2013
@@ -136,6 +136,7 @@
# XXX missing usable drivers, like run(4).
ukphy* at mii? # unknown PHYs
+rlphy* at mii?
scsibus* at scsi?
sd*at scsibus?
diff -u ./allwinnerreg.h /usr/src/sys/arch/armv7/allwinner/allwinnerreg.h
--- ./allwinnerreg.hThu Oct 3 02:33:30 2013
+++ /usr/src/sys/arch/armv7/allwinner/allwinnerreg.hFri Oct 11 16:34:06 2013
@@ -69,7 +69,7 @@
/* A20 / Cortex-A7 */
#define GIC_ADDR 0x01c8 /* = periphbase */
#define GIC_SIZE 0x8000
-#define CPUCONFG_ADDR 0x01c25000 /* not in use */
+#define CPUCONFG_ADDR 0x01c25c00 /* not in use */
#defineCPUCONFG_SIZE 0x200
-#defineCPUCNTRS_ADDR 0x01c25200 /* used by awtimer */
+#defineCPUCNTRS_ADDR 0x01c25e00 /* used by awtimer */
#defineCPUCNTRS_SIZE 0x200
diff -u ./awtimer.c /usr/src/sys/arch/armv7/allwinner/awtimer.c
--- ./awtimer.c Fri Oct 4 13:25:23 2013
+++ /usr/src/sys/arch/armv7/allwinner/awtimer.c Fri Oct 11 19:16:40 2013
@@ -57,15 +57,16 @@
#define TIMER_CTRL(_t) (0x10 + ((_t) * 0x10))
/* A20 counter */
-#define OSC24M_CNT64_CTRL 0x280
-#define OSC24M_CNT64_LOW 0x284
-#define OSC24M_CNT64_HIGH 0x288
+#define OSC24M_CNT64_CTRL 0x80
+#define OSC24M_CNT64_LOW 0x84
+#define OSC24M_CNT64_HIGH 0x88
/* A1X counter */
#define CNT64_CTRL 0xa0
#define CNT64_LOW 0xa4
#define CNT64_HIGH 0xa8
+#define CNT64_SYNCH(1 4) /* sync to OSC24M counter */
#define CNT64_RL_EN(1 1) /* read latch enable */
#define CNT64_CLR_EN (1 0) /* clear enable */
@@ -153,7 +154,7 @@
awtimer_attach(struct device *parent, struct device *self, void *args)
{
struct aw_attach_args *aw = args;
- uint32_t now, cr;
+ uint32_t now, cr, v
Re: Allwinner
On 10/11/13 20:39, Markus Hennecke wrote: On Sat, 5 Oct 2013, Artturi Alm wrote: Current version attached, extract to /sys/arch/armv7 and read the short notes file, no more out of allwinner/ patches needed thanks to armv7. A20 support still needs a workaround under /sys/arch/arm/cortex/ which i didn't include as i think support is still 'subtly' broken anyway.. And ahci is still not working for me, but there's a couple of new drivers included. Ethernet driver survived make build of userland with /usr/src mounted via nfs, fwiw. Now this is totally usable for me as-is already, so any feedback is welcome, be it finding out possible bugs and/or confirming it's working. Great work! I made a few changes to fix the timer code for the A20 CPU, the diff to your code is attached. With this I am almost booting the kernel on a cubieboard 2: Copyright (c) 1982, 1986, 1989, 1991, 1993 The Regents of the University of California. All rights reserved. Copyright (c) 1995-2013 OpenBSD. All rights reserved. http://www.OpenBSD.org OpenBSD 5.4-current (GENERIC-ALLWINNER) #22: Fri Oct 11 19:17:11 CEST 2013 mar...@antigone.markus-hennecke.de:/usr/src/sys/arch/armv7/compile/GENERIC-ALLWINNER real mem = 1073741824 (1024MB) avail mem = 1040007168 (991MB) mainbus0 at root cortex0 at mainbus0 ampintc0 at cortex0 nirq 160 cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core) cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache allwinner0 at mainbus0: A20 awpio0 at allwinner0 awccmu0 at allwinner0 awtimer0 at allwinner0: tick rate 32KHz hz 100 stat rate 32KHz stathz 128 counter 24000 KHz awdog0 at allwinner0 awrtc0 at allwinner0 awuart0 at allwinner0: console awe0 at allwinner0 awe0: address 00:00:00:00:00:00 rlphy0 at awe0 phy 1: RTL8201L 10/100 PHY, rev. 1 ahci0 at allwinner0 GHC 0x8000AE AHCI 1.1 ahci0: capabilities 0x6726ff80NCQ,SSNTF,SALP,SAL,SCLO,SAM,SPM,PMD,SSC,PSC,CCCS, 1 ports, 32 cmds, gen 1 (1.5Gbps) and 2 (3Gbps) ahci0: ports implemented: 0x0001 ahci0.0: port reset ahci0: no device detected on port 0 scsibus0 at ahci0: 32 targets ehci0 at allwinner0 usb0 at ehci0: USB revision 2.0 uhub0 at usb0 Allwinner EHCI root hub rev 2.00/1.00 addr 1 ehci1 at allwinner0 usb1 at ehci1: USB revision 2.0 uhub1 at usb1 Allwinner EHCI root hub rev 2.00/1.00 addr 1 gpio0 at awpio0: 18 pins gpio1 at awpio0: 24 pins gpio2 at awpio0: 25 pins gpio3 at awpio0: 28 pins gpio4 at awpio0: 12 pins gpio5 at awpio0: 6 pins gpio6 at awpio0: 12 pins gpio7 at awpio0: 28 pins gpio8 at awpio0: 22 pins /dev/ksyms: Symbol table not valid. Here the output stops, I will look into that later. At this point I am unable to figure out how to set the ethaddr in the u-boot version I am using. setenv ethaddr xx:xx:xx:xx:xx:xx doesn't seem to have any effect. Kind regards Markus Hi, Thanks for the patch, it looks correct when compared to the user manual and shows how ugly sources may get when not paid enough attention, will fix the whitespaces there also. Note that Cortex-A7 should support agtimer found in arch/arm/cortex, which would allow cleaning up awtimer.c from the 'added on'-kind of hacks to support A20, priorities have kept me from trying that one out so far. To allow it to boot further you would have to change ICP_ADDR and ICD_ADDR in ampintc, iirc. possibly 0x1000 and 0x2000 respectively, which is not the fix that would ever get commited even if allwinner would be on cvs, as it'll break Cortex-A9, and unfortunately, masking by cpu is not working option either, there is example of where it would fail already (exynos). FDT is the only clean solution i can think of, when there is priority on keeping arch/arm/cortex free of SoC-dependent code. About ethaddr, have you tried pinging another host from u-boot? Does your u-boot support emac? the one i initially downloaded for cubieboard2 did not iirc., if you can boot the bsd.umg over network, and still get 00:00:00:00:00:00, i will power up my cb2 to fix awe, as it's so far untested on A20 afaik. -Artturi
Re: Allwinner
Am 11.10.2013 um 22:46 schrieb Artturi Alm artturi@gmail.com: On 10/11/13 20:39, Markus Hennecke wrote: On Sat, 5 Oct 2013, Artturi Alm wrote: Current version attached, extract to /sys/arch/armv7 and read the short notes file, no more out of allwinner/ patches needed thanks to armv7. A20 support still needs a workaround under /sys/arch/arm/cortex/ which i didn't include as i think support is still 'subtly' broken anyway.. And ahci is still not working for me, but there's a couple of new drivers included. Ethernet driver survived make build of userland with /usr/src mounted via nfs, fwiw. Now this is totally usable for me as-is already, so any feedback is welcome, be it finding out possible bugs and/or confirming it's working. Great work! I made a few changes to fix the timer code for the A20 CPU, the diff to your code is attached. With this I am almost booting the kernel on a cubieboard 2: Copyright (c) 1982, 1986, 1989, 1991, 1993 The Regents of the University of California. All rights reserved. Copyright (c) 1995-2013 OpenBSD. All rights reserved. http://www.OpenBSD.org OpenBSD 5.4-current (GENERIC-ALLWINNER) #22: Fri Oct 11 19:17:11 CEST 2013 mar...@antigone.markus-hennecke.de:/usr/src/sys/arch/armv7/compile/GENERIC-ALLWINNER real mem = 1073741824 (1024MB) avail mem = 1040007168 (991MB) mainbus0 at root cortex0 at mainbus0 ampintc0 at cortex0 nirq 160 cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core) cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache allwinner0 at mainbus0: A20 awpio0 at allwinner0 awccmu0 at allwinner0 awtimer0 at allwinner0: tick rate 32KHz hz 100 stat rate 32KHz stathz 128 counter 24000 KHz awdog0 at allwinner0 awrtc0 at allwinner0 awuart0 at allwinner0: console awe0 at allwinner0 awe0: address 00:00:00:00:00:00 rlphy0 at awe0 phy 1: RTL8201L 10/100 PHY, rev. 1 ahci0 at allwinner0 GHC 0x8000AE AHCI 1.1 ahci0: capabilities 0x6726ff80NCQ,SSNTF,SALP,SAL,SCLO,SAM,SPM,PMD,SSC,PSC,CCCS, 1 ports, 32 cmds, gen 1 (1.5Gbps) and 2 (3Gbps) ahci0: ports implemented: 0x0001 ahci0.0: port reset ahci0: no device detected on port 0 scsibus0 at ahci0: 32 targets ehci0 at allwinner0 usb0 at ehci0: USB revision 2.0 uhub0 at usb0 Allwinner EHCI root hub rev 2.00/1.00 addr 1 ehci1 at allwinner0 usb1 at ehci1: USB revision 2.0 uhub1 at usb1 Allwinner EHCI root hub rev 2.00/1.00 addr 1 gpio0 at awpio0: 18 pins gpio1 at awpio0: 24 pins gpio2 at awpio0: 25 pins gpio3 at awpio0: 28 pins gpio4 at awpio0: 12 pins gpio5 at awpio0: 6 pins gpio6 at awpio0: 12 pins gpio7 at awpio0: 28 pins gpio8 at awpio0: 22 pins /dev/ksyms: Symbol table not valid. Here the output stops, I will look into that later. At this point I am unable to figure out how to set the ethaddr in the u-boot version I am using. setenv ethaddr xx:xx:xx:xx:xx:xx doesn't seem to have any effect. Kind regards Markus Hi, Thanks for the patch, it looks correct when compared to the user manual and shows how ugly sources may get when not paid enough attention, will fix the whitespaces there also. Note that Cortex-A7 should support agtimer found in arch/arm/cortex, which would allow cleaning up awtimer.c from the 'added on'-kind of hacks to support A20, priorities have kept me from trying that one out so far. To allow it to boot further you would have to change ICP_ADDR and ICD_ADDR in ampintc, iirc. possibly 0x1000 and 0x2000 respectively, which is not the fix that would ever get commited even if allwinner would be on cvs, as it'll break Cortex-A9, and unfortunately, masking by cpu is not working option either, there is example of where it would fail already (exynos). FDT is the only clean solution i can think of, when there is priority on keeping arch/arm/cortex free of SoC-dependent code. Exactly. We have already talked and discussed that a lot. :) There is no other way around it. About ethaddr, have you tried pinging another host from u-boot? Does your u-boot support emac? the one i initially downloaded for cubieboard2 did not iirc., if you can boot the bsd.umg over network, and still get 00:00:00:00:00:00, i will power up my cb2 to fix awe, as it's so far untested on A20 afaik. Maybe Allwinner stores the mac address in some magic register? i.MX6 does that. u-boot might be able to push the ethaddr env using the FDT. -Artturi
Re: Allwinner
On Sat, Oct 05, 2013 at 03:58:39PM +0300, Artturi Alm wrote: awe0: address 92:1f:3d:86:69:10 ukphy0 at awe0 phy 1: Generic IEEE 802.3u media interface, rev. 1: OUI 0x20, model 0x0020 That is an RTL8201L compatible PHY which would be handled by rlphy(4) if you had it in your config.
Re: Allwinner wip
On 20/07/13(Sat) 14:10, Artturi Alm wrote: Hi, work-in-progress-quality 'port' to add support for Allwinner A10, tested on cubieboard only. Nice work. For what I've seen this port is really similar to the beagle one. Do you think it's possible to merge your work into this port or is there any technical issue? M.
Re: Allwinner wip
Am 20.07.2013 um 14:20 schrieb Martin Pieuchot mpieuc...@nolizard.org: On 20/07/13(Sat) 14:10, Artturi Alm wrote: Hi, work-in-progress-quality 'port' to add support for Allwinner A10, tested on cubieboard only. Nice work. For what I've seen this port is really similar to the beagle one. Do you think it's possible to merge your work into this port or is there any technical issue? M. I guess the biggest issue would be the load address, which currently is statically set in the kernel config. Sure, we could add a new config file for that SoC, but I'd rather not put multiple SoCs into the beagle/omap SoC port. I'm working on a generic arm(v7) arch, but that'll still take some time.
Re: Allwinner wip
On 07/20/13 15:20, Martin Pieuchot wrote: On 20/07/13(Sat) 14:10, Artturi Alm wrote: Hi, work-in-progress-quality 'port' to add support for Allwinner A10, tested on cubieboard only. Nice work. For what I've seen this port is really similar to the beagle one. Do you think it's possible to merge your work into this port or is there any technical issue? M. That was my initial suggestion to Patrick, but I agree with him that having separate configs is not the way to go. This might also be beneficial if support for Allwinner A20 is added, going MP in allwinner-arch alone without possibly having so many Cortex-A9(pandaboard es) vs Cortex-A7(cubieboard2 w/A20 chip) issues to solve, this is purely speculation thought, i have not looked up on what kind of differences there is, nor if they would be at '/arch/arm-level' anyway. Inspired by Patrick's question about timer frequency, i found what was missing from awtimer.c, and with USELOWSPEEDOSC + related changes, times are finally reported correctly :) I was also given a possible direction to go with uart problems, so the horrible comdiff can be dropped i think, this is nr1 on my todo. i think i need to rework all the diffs outside arch/allwinner(including those that i did not send as they are not useful for anything as is) too, as i realized i had not rebuilt /usr/cross/allwinner as often as i updated /usr/src and it seems not to build the cross-env for me anymore, will sort this out with clean install or something after uart is working and the code is backed up somewhere before even trying native compilation. if anyone is really going to give it a try soonish, ask for current copy off list, as anything i could send now is most likely old by tomorrow morning. -Artturi
