Re: [time-nuts] How to properly simulate PLLs?
Hi Attila, have a look at CPPSim. http://www.cppsim.com/Tutorials/synthesizer_tutorial.pdf Sebastian On 07.03.2018 17:42, Attila Kinali wrote: > Hi, > > I have a small side task, where I need to design a PLL system > As it is a bit non-conventional, I am not confident that my > pen and paper analysis is correct and the usuall tool I use > (Analog's ADPLLsim) doesn't cover it. So my first thought > was to use spice to simulate the loop. But I am not sure > how the non-linear effects of the PLL, the divider chains etc > affect the whole system and whether a spice simulation (which > would use a linear approximation of a few components) would > model the system faithfully. Not to mention that this would > be only valid simulation of the locked state and anything > that involves the PLL being unlocked (initial lock in process, > large phase and frequency jumps that cause unlocks) cannot > be handled at all. Neither would it give me a proper estimate > of the noise propagation through the system. > > So, is there any canonical way how to simulate PLLs? > If yes, what should I read? (My google foo didn't return > anything helpful). > > Thanks in advance > > Attila Kinali > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] How to properly simulate PLLs?
Hi, On 03/07/2018 05:42 PM, Attila Kinali wrote: > Hi, > > I have a small side task, where I need to design a PLL system > As it is a bit non-conventional, I am not confident that my > pen and paper analysis is correct and the usuall tool I use > (Analog's ADPLLsim) doesn't cover it. So my first thought > was to use spice to simulate the loop. But I am not sure > how the non-linear effects of the PLL, the divider chains etc > affect the whole system and whether a spice simulation (which > would use a linear approximation of a few components) would > model the system faithfully. Not to mention that this would > be only valid simulation of the locked state and anything > that involves the PLL being unlocked (initial lock in process, > large phase and frequency jumps that cause unlocks) cannot > be handled at all. Neither would it give me a proper estimate > of the noise propagation through the system. > > So, is there any canonical way how to simulate PLLs? > If yes, what should I read? (My google foo didn't return > anything helpful). > > Thanks in advance Now, I called Attila to ask what he was trying to do and crash coarse him into some stuff. The discussion drifted from there. I end up writing simulators in C, over and over again, dedicated to each design. When dealing with phase accumulators, I use a rather simple acceleration trick which I thought I would share. Rather than simulating each of the cycles of the phase accumulator, I can fast forward the time by estimate how many cycles it takes for it to wrap, so if I have the current phase phi, and the phase accumulator wrap-point phi_w, then the remaining phase for the cycle is phi_w - phi. Now, the steering word for the phase accumulator phi_s is what is accumulated each cycle, so we can figure out how many n cycles it take simply by n = (phi_w - phi) / phi_s As this division is assumed to be rounded down, it is actually not sufficient to wrap the phase around, it would only give the phase just before wrapping, so it would need one more cycle n = (phi_w - phi) / phi_s + 1 OK, with this we can update the phase by phi = phi + n * phi_s By simulate as if the phase accumulator just wrapped, this method fast-forwards the simulation and allows to simulate each update of the PLL. You typically also update the time of the system using T = T + n * T_s where T_0 is the period of the phase accumulators clock, to T_0 = 1/fs somewhere in the initiation code. Now, typically phase and time needs to be unwrapped over a few variables not to run into overflow issues that mess with the numerical issues of simulation, but that is relatively trivial code. Phase comparison typically is V_d = phi_in - phi The PI-loop is trivial V_i = V_i + I * V_d V_f = V_i + P * V_d You want an offset frequency typically phi_s = V_f + V_f0 Adjust I and P for dynamics as you please. That's the basics for building a PI loop simulation. phi will be the phase-state and V_i the frequency state of the loop. The phase-state is however best viewed as V_d, the detected phase difference. Enjoy. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] How to properly simulate PLLs?
Attila wrote: my first thought was to use spice to simulate the loop. But I am not sure how the non-linear effects of the PLL, the divider chains etc affect the whole system and whether a spice simulation (which would use a linear approximation of a few components) would model the system faithfully. Not to mention that this would be only valid simulation of the locked state and anything that involves the PLL being unlocked (initial lock in process, large phase and frequency jumps that cause unlocks) cannot be handled at all. Neither would it give me a proper estimate of the noise propagation through the system. I have had good results with Spice, including simulating high-order loop filters and staged (stepped) loop time constants (for acquisition/run). My simulations include an initial unlocked condition, acquisition, loop dynamics tests that progress to driving the loop out of lock, and reacquisition. I use behavioral models for digital dividers. I have working models of regenerative dividers and mixers, which can be imported as subcircuits when needed. Test loop dynamics by putting a step function (or other function of interest) into the loop. Stepping the reference frequency is an easy method, but it can be done any number of ways depending on the need. I also use sine, ramp, and filtered noise functions to simulate drift, etc. I find that the results are well within "simulation expectation." Best regards, Charles ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] How to properly simulate PLLs?
http://www.aholme.co.uk/Frac2/Simulate.htm might be useful. bob -Original Message- From: time-nuts <time-nuts-boun...@febo.com> On Behalf Of Attila Kinali Sent: Wednesday, March 7, 2018 11:43 AM To: Discussion of precise time and frequency measurement <time-nuts@febo.com> Subject: [time-nuts] How to properly simulate PLLs? Hi, I have a small side task, where I need to design a PLL system As it is a bit non-conventional, I am not confident that my pen and paper analysis is correct and the usuall tool I use (Analog's ADPLLsim) doesn't cover it. So my first thought was to use spice to simulate the loop. But I am not sure how the non-linear effects of the PLL, the divider chains etc affect the whole system and whether a spice simulation (which would use a linear approximation of a few components) would model the system faithfully. Not to mention that this would be only valid simulation of the locked state and anything that involves the PLL being unlocked (initial lock in process, large phase and frequency jumps that cause unlocks) cannot be handled at all. Neither would it give me a proper estimate of the noise propagation through the system. So, is there any canonical way how to simulate PLLs? If yes, what should I read? (My google foo didn't return anything helpful). Thanks in advance Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] How to properly simulate PLLs?
Hi, I have a small side task, where I need to design a PLL system As it is a bit non-conventional, I am not confident that my pen and paper analysis is correct and the usuall tool I use (Analog's ADPLLsim) doesn't cover it. So my first thought was to use spice to simulate the loop. But I am not sure how the non-linear effects of the PLL, the divider chains etc affect the whole system and whether a spice simulation (which would use a linear approximation of a few components) would model the system faithfully. Not to mention that this would be only valid simulation of the locked state and anything that involves the PLL being unlocked (initial lock in process, large phase and frequency jumps that cause unlocks) cannot be handled at all. Neither would it give me a proper estimate of the noise propagation through the system. So, is there any canonical way how to simulate PLLs? If yes, what should I read? (My google foo didn't return anything helpful). Thanks in advance Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
