my first thought was to use spice to simulate the loop. But I am not sure how the non-linear effects of the PLL, the divider chains etc affect the whole system and whether a spice simulation (which would use a linear approximation of a few components) would model the system faithfully. Not to mention that this would be only valid simulation of the locked state and anything that involves the PLL being unlocked (initial lock in process, large phase and frequency jumps that cause unlocks) cannot be handled at all. Neither would it give me a proper estimate of the noise propagation through the system.
I have had good results with Spice, including simulating high-order loop filters and staged (stepped) loop time constants (for acquisition/run). My simulations include an initial unlocked condition, acquisition, loop dynamics tests that progress to driving the loop out of lock, and reacquisition. I use behavioral models for digital dividers. I have working models of regenerative dividers and mixers, which can be imported as subcircuits when needed.
Test loop dynamics by putting a step function (or other function of interest) into the loop. Stepping the reference frequency is an easy method, but it can be done any number of ways depending on the need. I also use sine, ramp, and filtered noise functions to simulate drift, etc.
I find that the results are well within "simulation expectation." Best regards, Charles _______________________________________________ time-nuts mailing list -- firstname.lastname@example.org To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.