Re: [time-nuts] MV89A / MTI-260 / HP10811 carrier board

[Hal Murray]

kb...@n1k.org said:
> … and that’s not a completely crazy thing to do for the older parts. Get a
> copy of the stuff that worked with them and freeze it on a (possibly
> virtual) machine.  

We used to just push the PC that ran the software into a corner.  That was 
back when PCs were expensive, but by the time the project was wrapping up, 
the system was close to obsolete.  The real cost was storage space and 
keeping track of it.  With a small group, a note taped to the top was 
probably good enough.

One of the complications is software licensing.  Back in the days of physical 
dongles it was easy to keep the dongle with a PC.  It gets much more 
complicated with network licensing servers.


-- 
These are my opinions.  I hate spam.



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Re: [time-nuts] MV89A / MTI-260 / HP10811 carrier board

[Bob Camp]

Hi

> On Feb 27, 2016, at 2:10 PM, jimlux  wrote:
> 
> On 2/27/16 10:16 AM, Gerhard Hoffmann wrote:
>> Am 27.02.2016 um 16:15 schrieb Bob Camp:
>>> Hi
>>> 
>>> You will run into the same problem on the Altera side. Their “super
>>> suite” is called Quartus and
>>> the latest free version only supports the newer parts. Once you get a
>>> few generations back, you
>>> need to download an older version. That’s not impossible to do or
>>> crazy to work with. The newer
>>> stuff is a bit better. The generation to generation transitions are
>>> not insane, but they will take up
>>> time working this and that out. Much better (if possible) to start
>>> with a part that the current software
>>> just started supporting. In the Altera case that is the Max10 family.
>>> The lowest cost member is
>>> less than $4 in single piece quantity on Mouser. Yes it’s a BGA. The
>>> leaded parts are about $11 or so.
>>> Demo boards with various cool things on them are < $40.
>>> 
>>> Yes this sounds like an advertisement for Altera. It’s not really. All
>>> of the same basic issues apply equally
>>> to the other vendors. It’s a competitive world and they all do a
>>> pretty fast game of catch up. The only unique
>>> feature (AFIK) with Quartus is the inclusion of schematic entry. It
>>> lets you do a “no code” design if you are
>>> more familiar with logic schematics than with VHDL. If any of the
>>> “other guys” do this, it would be worth knowing
>>> about in the context of many of the people on the list being a bit
>>> code shy.
>> Xilinx used to have Futurenet as circuit entry and after massive begging
>> of the
>> community they also provided an interface from Orcad. But that was long
>> ago.
>> 
>> I think they still have something of their own, but I have converted to
>> pure VHDL
>> some 15 years ago and never looked back. Maybe over the fence to Verilog.
>> 
>> I have a Altium Designer license of my own and I think it can do circuit
>> diagrams to FPGA via VHDL, but never took the time to poke around in that
>> corner.
>> 
>> The 2C64 is so small that about any ISE version is ok for it. The VHDL
>> source
>> of my pps generator would compile for an Microsemi Igloo , Altera,
>> Spartan, Whatever.. without change.
>> 
>> That does not mean that I'm a Xilinx fan boy. Nothing could be more wrong.
>> I'm currently doing some ORIGINAL Virtex FPGAs, not Virtex II, 2E, 4, 5,
>> 7..
>> in the Aces space project (to get the link to TimeNuttery) and they were
>> agreed on in 2002.
>> 
>> Xilinx now nearly deny fatherhood and it is fun to write specialties like a
>> configuration memory scrubber when even a certain app note seems to be
>> removed from everywhere; maybe an ITAR thing.
>> 
>> The latest ISE version that supports original Virtex is 10.1, with a
>> nearly defunct project management. V7 to 9 were even worse.
>> 
> 
> 
> Even worse, there's a lot of "logiCores" for the older parts like a nice 
> simple DDC that don't compile any more.
> 
> We have a bunch of copies of ISE 10 to do software for the original Virtex 
> (in the Electra radio on Mars reconnaissance orbiter) and Virtex II (in 
> subsequent Electras, and the radio in the SCaN Testbed on ISS)
> 
> 
> 


… and that’s not a completely crazy thing to do for the older parts. Get a copy 
of the
stuff that worked with them and freeze it on a (possibly virtual) machine. 

Bob


> 
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Re: [time-nuts] MV89A / MTI-260 / HP10811 carrier board

[Magnus Danielson]

Gerhard,

On 02/27/2016 07:16 PM, Gerhard Hoffmann wrote:

Am 27.02.2016 um 16:15 schrieb Bob Camp:
Xilinx used to have Futurenet as circuit entry and after massive begging
of the
community they also provided an interface from Orcad. But that was long
ago.

I think they still have something of their own, but I have converted to
pure VHDL
some 15 years ago and never looked back. Maybe over the fence to Verilog.

I have a Altium Designer license of my own and I think it can do circuit
diagrams to FPGA via VHDL, but never took the time to poke around in that
corner.

The 2C64 is so small that about any ISE version is ok for it. The VHDL
source
of my pps generator would compile for an Microsemi Igloo , Altera,
Spartan, Whatever.. without change.

That does not mean that I'm a Xilinx fan boy. Nothing could be more wrong.
I'm currently doing some ORIGINAL Virtex FPGAs, not Virtex II, 2E, 4, 5,
7..
in the Aces space project (to get the link to TimeNuttery) and they were
agreed on in 2002.


In a box I have some of our test-boards using the Virtex, which we used 
to validate our ASIC design. We made the boards so ugly they could not 
easily be made into a product. :)


I did my first real VHDL design on those boards, in the end of the 
previous millennium and for the ASIC. I remember when we got the -6 
chips, it was some 4000 dollars a piece.


What was most annoying was that I had to finish my design before going 
the VHDL coarse. Let me say that as I got back from the coarse I improve 
test-benches and coding a lot. I did one mistake, which we could fix in 
the metallic layer change we got for free, but which never affected any 
of the products as we never used that feature in any of the products 
anyway. As the FPGAs got more powerful we didn't go back to the world of 
ASIC and once we got the FPGA FW upgradeable just like any other FW, we 
have not looked back, it is now released just as any SW.



Xilinx now nearly deny fatherhood and it is fun to write specialties like a
configuration memory scrubber when even a certain app note seems to be
removed from everywhere; maybe an ITAR thing.


CPLD is still a nice technology, it just that like PAL, only go that 
far. I remember when CPLD was like a more complex PAL/PLD and then 
looking at the XC3000 or even to the XC4000 sea of gates whoo...


Our first product was based on the XC4000 chips and ran for very long. I 
think there is still some networks out there running those boxes, as we 
just released an upgrade for it. It also has some CPLDs in them. One is 
however a particular hate-object for me, as we never could change it 
into a better design and solve some of its fundamental limits. Not 
because CPLD as such, but because we had one in the wrong place. Ah 
well, we learned from that experience.



The latest ISE version that supports original Virtex is 10.1, with a
nearly defunct project management. V7 to 9 were even worse.


Its not all good that they drop support as they go. Hobbyists often use 
old devices as well as new.



Now that Altera is in bed with Intel, that's a good perspective.


Not convinced.

Cheers,
Magnus
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Re: [time-nuts] MV89A / MTI-260 / HP10811 carrier board

[jimlux]

On 2/27/16 10:16 AM, Gerhard Hoffmann wrote:

Am 27.02.2016 um 16:15 schrieb Bob Camp:

Hi

You will run into the same problem on the Altera side. Their “super
suite” is called Quartus and
the latest free version only supports the newer parts. Once you get a
few generations back, you
need to download an older version. That’s not impossible to do or
crazy to work with. The newer
stuff is a bit better. The generation to generation transitions are
not insane, but they will take up
time working this and that out. Much better (if possible) to start
with a part that the current software
just started supporting. In the Altera case that is the Max10 family.
The lowest cost member is
less than $4 in single piece quantity on Mouser. Yes it’s a BGA. The
leaded parts are about $11 or so.
Demo boards with various cool things on them are < $40.

Yes this sounds like an advertisement for Altera. It’s not really. All
of the same basic issues apply equally
to the other vendors. It’s a competitive world and they all do a
pretty fast game of catch up. The only unique
feature (AFIK) with Quartus is the inclusion of schematic entry. It
lets you do a “no code” design if you are
more familiar with logic schematics than with VHDL. If any of the
“other guys” do this, it would be worth knowing
about in the context of many of the people on the list being a bit
code shy.

Xilinx used to have Futurenet as circuit entry and after massive begging
of the
community they also provided an interface from Orcad. But that was long
ago.

I think they still have something of their own, but I have converted to
pure VHDL
some 15 years ago and never looked back. Maybe over the fence to Verilog.

I have a Altium Designer license of my own and I think it can do circuit
diagrams to FPGA via VHDL, but never took the time to poke around in that
corner.

The 2C64 is so small that about any ISE version is ok for it. The VHDL
source
of my pps generator would compile for an Microsemi Igloo , Altera,
Spartan, Whatever.. without change.

That does not mean that I'm a Xilinx fan boy. Nothing could be more wrong.
I'm currently doing some ORIGINAL Virtex FPGAs, not Virtex II, 2E, 4, 5,
7..
in the Aces space project (to get the link to TimeNuttery) and they were
agreed on in 2002.

Xilinx now nearly deny fatherhood and it is fun to write specialties like a
configuration memory scrubber when even a certain app note seems to be
removed from everywhere; maybe an ITAR thing.

The latest ISE version that supports original Virtex is 10.1, with a
nearly defunct project management. V7 to 9 were even worse.




Even worse, there's a lot of "logiCores" for the older parts like a nice 
simple DDC that don't compile any more.


We have a bunch of copies of ISE 10 to do software for the original 
Virtex (in the Electra radio on Mars reconnaissance orbiter) and Virtex 
II (in subsequent Electras, and the radio in the SCaN Testbed on ISS)





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Re: [time-nuts] MV89A / MTI-260 / HP10811 carrier board

[Gerhard Hoffmann]

Am 27.02.2016 um 16:15 schrieb Bob Camp:

Hi

You will run into the same problem on the Altera side. Their “super suite” is 
called Quartus and
the latest free version only supports the newer parts. Once you get a few 
generations back, you
need to download an older version. That’s not impossible to do or crazy to work 
with. The newer
stuff is a bit better. The generation to generation transitions are not insane, 
but they will take up
time working this and that out. Much better (if possible) to start with a part 
that the current software
just started supporting. In the Altera case that is the Max10 family. The 
lowest cost member is
less than $4 in single piece quantity on Mouser. Yes it’s a BGA. The leaded 
parts are about $11 or so.
Demo boards with various cool things on them are < $40.

Yes this sounds like an advertisement for Altera. It’s not really. All of the 
same basic issues apply equally
to the other vendors. It’s a competitive world and they all do a pretty fast 
game of catch up. The only unique
feature (AFIK) with Quartus is the inclusion of schematic entry. It lets you do 
a “no code” design if you are
more familiar with logic schematics than with VHDL. If any of the “other guys” 
do this, it would be worth knowing
about in the context of many of the people on the list being a bit code shy.
Xilinx used to have Futurenet as circuit entry and after massive begging 
of the

community they also provided an interface from Orcad. But that was long ago.

I think they still have something of their own, but I have converted to 
pure VHDL

some 15 years ago and never looked back. Maybe over the fence to Verilog.

I have a Altium Designer license of my own and I think it can do circuit
diagrams to FPGA via VHDL, but never took the time to poke around in that
corner.

The 2C64 is so small that about any ISE version is ok for it. The VHDL 
source

of my pps generator would compile for an Microsemi Igloo , Altera,
Spartan, Whatever.. without change.

That does not mean that I'm a Xilinx fan boy. Nothing could be more wrong.
I'm currently doing some ORIGINAL Virtex FPGAs, not Virtex II, 2E, 4, 5, 
7..

in the Aces space project (to get the link to TimeNuttery) and they were
agreed on in 2002.

Xilinx now nearly deny fatherhood and it is fun to write specialties like a
configuration memory scrubber when even a certain app note seems to be
removed from everywhere; maybe an ITAR thing.

The latest ISE version that supports original Virtex is 10.1, with a
nearly defunct project management. V7 to 9 were even worse.

Now that Altera is in bed with Intel, that's a good perspective.

regards, Gerhard
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Re: [time-nuts] MV89A / MTI-260 / HP10811 carrier board

[Bob Camp]

Hi

You will run into the same problem on the Altera side. Their “super suite” is 
called Quartus and
the latest free version only supports the newer parts. Once you get a few 
generations back, you
need to download an older version. That’s not impossible to do or crazy to work 
with. The newer
stuff is a bit better. The generation to generation transitions are not insane, 
but they will take up
time working this and that out. Much better (if possible) to start with a part 
that the current software
just started supporting. In the Altera case that is the Max10 family. The 
lowest cost member is 
less than $4 in single piece quantity on Mouser. Yes it’s a BGA. The leaded 
parts are about $11 or so. 
Demo boards with various cool things on them are < $40. 

Yes this sounds like an advertisement for Altera. It’s not really. All of the 
same basic issues apply equally
to the other vendors. It’s a competitive world and they all do a pretty fast 
game of catch up. The only unique
feature (AFIK) with Quartus is the inclusion of schematic entry. It lets you do 
a “no code” design if you are 
more familiar with logic schematics than with VHDL. If any of the “other guys” 
do this, it would be worth knowing
about in the context of many of the people on the list being a bit code shy. 

Bob

> On Feb 27, 2016, at 3:03 AM, Bruce Griffiths <bruce.griffi...@xtra.co.nz> 
> wrote:
> 
> To program the chip one needs a USB to JTAG programming cable and development 
> software to produce the programming data file for the chip.
> The Xilinx Coolrunner II CPLDS are only supported by Xilinx's ISE software 
> which is obsolete. Vivado the current development software doesn't support 
> them.
> Bruce
> 
> 
>On Saturday, 27 February 2016 12:01 PM, Tom Van Baak <t...@leapsecond.com> 
> wrote:
> 
> 
> Gerhard Hoffmann wrote:
>> I have never used PICs and given their life cycle it's a bad time to jump on 
>> the train.
>> Not now when I'm just converting everything to ARM.
> 
> Hi Gerhard,
> 
> The 12F-series that I use for the PIC dividers is very solid. These are sold 
> by the billions. Not sure what train you're talking about. Don't confuse ARM 
> and x86 chips du jour with something like an 8-pin 8-bit PIC. For more info 
> on the PIC dividers see:
> http://leapsecond.com/pic/picdiv.htm
> http://leapsecond.com/pic/picdiv-list.htm
> 
> Thanks for posting the sample Xilinx code. That's intriguing. So if I started 
> from scratch, what does it take to turn your firmware source code into a 
> working chip? Are any of the chips as small or as cheap as a SMT or DIP PIC?
> 
> By contrast, the (pd10.asm) PIC code to generate a 10 ms wide 1PPS from 10 
> MHz is two macros and a loop:
> 
> DELAY_24996MACRO  ; delay 24996 instructions
> movlw  d'249'
> callDelayW100
> movlw  d'94'
> callDelayW1
> ENDM
> 
> DELAY_2474996  MACRO  ; delay 2474996 instructions
> movlw  d'247'
> callDelayW10k
> movlw  d'49'
> callDelayW100
> movlw  d'93'
> callDelayW1
> ENDM
> 
> ; Set output pins high for 10 ms = 25,000 Tcy at 10 MHz.
> rise:  movlw  0xFF
> movwf  GPIO
> DELAY_24996
> gotofall
> 
> ; Set output pins low for 990 ms = 2,475,000 Tcy at 10 MHz.
> fall:  movlw  0x00
> movwf  GPIO
> DELAY_2474996
>         goto    rise
> 
> /tvb
> 
> - Original Message - 
> From: "Gerhard Hoffmann" <dk...@arcor.de>
> To: <time-nuts@febo.com>
> Sent: Thursday, February 25, 2016 5:30 PM
> Subject: Re: [time-nuts] MV89A / MTI-260 / HP10811 carrier board
> 
> 
>> Am 25.02.2016 um 22:23 schrieb Magnus Danielson:
>>> Interesting. I would consider the PICDIV such as that of TADD-2, which 
>>> has the benefit of producing a range of frequencies, so that a 
>>> suitable can be selected as matching the needs. I've found it very 
>>> useful property of the TADD-2, where I have my TADD-2s wired up to 
>>> output one of each. I also wired them to output the buffered variant 
>>> of the clock, which gives better measures compared to running the sine 
>>> straight into the counters.
>> 
>> I have never used PICs and given their life cycle it's a bad time to 
>> jump on the train.
>> Not now when I'm just converting everything to ARM. OTOH I have used 
>> Xilinx since they exist
>> and this board is more or less a cleanup of things that are already there..
>> 
>> 
>> This here is all it takes for 10 and 100 MHz oscillators:
>> 
>> 

Re: [time-nuts] MV89A / MTI-260 / HP10811 carrier board

[Bruce Griffiths]

To program the chip one needs a USB to JTAG programming cable and development 
software to produce the programming data file for the chip.
The Xilinx Coolrunner II CPLDS are only supported by Xilinx's ISE software 
which is obsolete. Vivado the current development software doesn't support them.
Bruce
 

On Saturday, 27 February 2016 12:01 PM, Tom Van Baak <t...@leapsecond.com> 
wrote:
 

 Gerhard Hoffmann wrote:
> I have never used PICs and given their life cycle it's a bad time to jump on 
> the train.
> Not now when I'm just converting everything to ARM.

Hi Gerhard,

The 12F-series that I use for the PIC dividers is very solid. These are sold by 
the billions. Not sure what train you're talking about. Don't confuse ARM and 
x86 chips du jour with something like an 8-pin 8-bit PIC. For more info on the 
PIC dividers see:
http://leapsecond.com/pic/picdiv.htm
http://leapsecond.com/pic/picdiv-list.htm

Thanks for posting the sample Xilinx code. That's intriguing. So if I started 
from scratch, what does it take to turn your firmware source code into a 
working chip? Are any of the chips as small or as cheap as a SMT or DIP PIC?

By contrast, the (pd10.asm) PIC code to generate a 10 ms wide 1PPS from 10 MHz 
is two macros and a loop:

DELAY_24996    MACRO          ; delay 24996 instructions
        movlw  d'249'
        call    DelayW100
        movlw  d'94'
        call    DelayW1
        ENDM

DELAY_2474996  MACRO          ; delay 2474996 instructions
        movlw  d'247'
        call    DelayW10k
        movlw  d'49'
        call    DelayW100
        movlw  d'93'
        call    DelayW1
        ENDM

        ; Set output pins high for 10 ms = 25,000 Tcy at 10 MHz.
rise:  movlw  0xFF
        movwf  GPIO
        DELAY_24996
        goto    fall

        ; Set output pins low for 990 ms = 2,475,000 Tcy at 10 MHz.
fall:  movlw  0x00
        movwf  GPIO
        DELAY_2474996
        goto    rise

/tvb

- Original Message - 
From: "Gerhard Hoffmann" <dk...@arcor.de>
To: <time-nuts@febo.com>
Sent: Thursday, February 25, 2016 5:30 PM
Subject: Re: [time-nuts] MV89A / MTI-260 / HP10811 carrier board


> Am 25.02.2016 um 22:23 schrieb Magnus Danielson:
>> Interesting. I would consider the PICDIV such as that of TADD-2, which 
>> has the benefit of producing a range of frequencies, so that a 
>> suitable can be selected as matching the needs. I've found it very 
>> useful property of the TADD-2, where I have my TADD-2s wired up to 
>> output one of each. I also wired them to output the buffered variant 
>> of the clock, which gives better measures compared to running the sine 
>> straight into the counters.
> 
> I have never used PICs and given their life cycle it's a bad time to 
> jump on the train.
> Not now when I'm just converting everything to ARM. OTOH I have used 
> Xilinx since they exist
> and this board is more or less a cleanup of things that are already there..
> 
> 
> This here is all it takes for 10 and 100 MHz oscillators:
> 
> --
> -- Company:        Hoffmann RF & DSP
> -- Create Date:    09:09:37 08/08/2012
> -- Module Name:    pps1_generator - Behavioral
> -- Target Devices:  X2c64A-5VQ44
> -- Additional Comments:  Free firmware under BSD license
> --
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use ieee.numeric_std.all;
> 
> entity pps1_generator is
>    Port(
>        clk        : in  STD_LOGIC;
>        RunAt100MHz : in  STD_LOGIC;
>        pps1_out    : out STD_LOGIC;
>    );
> end pps1_generator;
> 
> architecture Behavioral of pps1_generator is
>    signal tctr      : integer range 0 to ;
>    signal pw_ctr    : integer range 0 to 19;
>    signal cycle_done : boolean;
>    signal pw_done    : boolean;
> 
>    function bool2sl(b : boolean) return std_logic is
>    begin
>        if b then return '1'; else return '0'; end if;
>    end function bool2sl;
> 
> begin
> 
>    u_div : process(clk) is
>    begin
>        if rising_edge(clk) then
>            cycle_done <= (tctr = 0); -- pipeline the comparator
> 
>            if cycle_done
>            then
>                if RunAt100MHz = '1' then
>                    tctr <= 1 - 2; -- divide by 100 Meg
>                else
>                    tctr <= 1000 - 2; -- divide by 10 Meg
>                end if;
> 
>            else
>                tctr <= tctr - 1;
>            end if;
> 
>        end if;                        -- rising_edge()
>    end process u_div;
> 
> 
> -- produce the standard 20 usec pulsewidth
>    u_pulsewidth : process(clk) is
>    beg

Re: [time-nuts] MV89A / MTI-260 / HP10811 carrier board

[CFO]

On 2016-02-26 23:57, Tom Van Baak wrote:
> Gerhard Hoffmann wrote:
>> I have never used PICs and given their life cycle it's a bad time to jump on 
>> the train.
>> Not now when I'm just converting everything to ARM.
> Hi Gerhard,
>
> The 12F-series that I use for the PIC dividers is very solid. These are sold 
> by the billions. Not sure what train you're talking about. Don't confuse ARM 
> and x86 chips du jour with something like an 8-pin 8-bit PIC. For more info 
> on the PIC dividers see:
> http://leapsecond.com/pic/picdiv.htm
> http://leapsecond.com/pic/picdiv-list.htm
>
> Thanks for posting the sample Xilinx code. That's intriguing. So if I started 
> from scratch, what does it take to turn your firmware source code into a 
> working chip? Are any of the chips as small or as cheap as a SMT or DIP PIC?

Hi Tom / Gerhard / Magnus et all.

I have been using Altera parts, primarily because the finished boards on
*bay are so cheap.
I'm still a beginner in VHDL , but can do a little 


I have both Xilinx ISE & Altera Quartus installed on my linux mint 17
(x64) , and both works ok.
With a few install quirks.


VHDL is quite the same for both , and only the timing constraint magic
is different.

Gerhard would'nt a 240 MC 7$ cpld board , or a small 14$ FPGA be a nice
base for some of your timing magic ?


240 MC CPLD
http://www.ebay.com/itm/1PCS-NEW-EPM240-Altera-MAX-II-CPLD-Development-Board-/272086159418

http://www.ebay.com/itm/Altera-MAX-II-EPM240-CPLD-Development-Board-Experiment-Board-Learning-Breadboard-/181436966398


Small fpga
http://www.ebay.com/itm/1PCS-Altera-CycloneII-EP2C5T144-FPGA-Mini-Development-Board-/272086171657



Altera usb programmer (Jtag)
http://www.ebay.com/itm/Altera-Mini-Usb-Blaster-Cable-For-CPLD-FPGA-NIOS-JTAG-Altera-Programmer-/272097471982


Rgds
CFO - Denmark

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Re: [time-nuts] MV89A / MTI-260 / HP10811 carrier board

[Tom Van Baak]

Gerhard Hoffmann wrote:
> I have never used PICs and given their life cycle it's a bad time to jump on 
> the train.
> Not now when I'm just converting everything to ARM.

Hi Gerhard,

The 12F-series that I use for the PIC dividers is very solid. These are sold by 
the billions. Not sure what train you're talking about. Don't confuse ARM and 
x86 chips du jour with something like an 8-pin 8-bit PIC. For more info on the 
PIC dividers see:
http://leapsecond.com/pic/picdiv.htm
http://leapsecond.com/pic/picdiv-list.htm

Thanks for posting the sample Xilinx code. That's intriguing. So if I started 
from scratch, what does it take to turn your firmware source code into a 
working chip? Are any of the chips as small or as cheap as a SMT or DIP PIC?

By contrast, the (pd10.asm) PIC code to generate a 10 ms wide 1PPS from 10 MHz 
is two macros and a loop:

DELAY_24996 MACRO   ; delay 24996 instructions
movlw   d'249'
callDelayW100
movlw   d'94'
callDelayW1
ENDM

DELAY_2474996   MACRO   ; delay 2474996 instructions
movlw   d'247'
callDelayW10k
movlw   d'49'
callDelayW100
movlw   d'93'
callDelayW1
ENDM

; Set output pins high for 10 ms = 25,000 Tcy at 10 MHz.
rise:   movlw   0xFF
movwf   GPIO
DELAY_24996
gotofall

; Set output pins low for 990 ms = 2,475,000 Tcy at 10 MHz.
fall:   movlw   0x00
movwf   GPIO
DELAY_2474996
gotorise

/tvb

- Original Message - 
From: "Gerhard Hoffmann" <dk...@arcor.de>
To: <time-nuts@febo.com>
Sent: Thursday, February 25, 2016 5:30 PM
Subject: Re: [time-nuts] MV89A / MTI-260 / HP10811 carrier board


> Am 25.02.2016 um 22:23 schrieb Magnus Danielson:
>> Interesting. I would consider the PICDIV such as that of TADD-2, which 
>> has the benefit of producing a range of frequencies, so that a 
>> suitable can be selected as matching the needs. I've found it very 
>> useful property of the TADD-2, where I have my TADD-2s wired up to 
>> output one of each. I also wired them to output the buffered variant 
>> of the clock, which gives better measures compared to running the sine 
>> straight into the counters.
> 
> I have never used PICs and given their life cycle it's a bad time to 
> jump on the train.
> Not now when I'm just converting everything to ARM. OTOH I have used 
> Xilinx since they exist
> and this board is more or less a cleanup of things that are already there.
> 
> 
> This here is all it takes for 10 and 100 MHz oscillators:
> 
> --
> -- Company: Hoffmann RF & DSP
> -- Create Date:09:09:37 08/08/2012
> -- Module Name:pps1_generator - Behavioral
> -- Target Devices:   X2c64A-5VQ44
> -- Additional Comments:   Free firmware under BSD license
> --
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use ieee.numeric_std.all;
> 
> entity pps1_generator is
> Port(
> clk : in  STD_LOGIC;
> RunAt100MHz : in  STD_LOGIC;
> pps1_out: out STD_LOGIC;
> );
> end pps1_generator;
> 
> architecture Behavioral of pps1_generator is
> signal tctr   : integer range 0 to ;
> signal pw_ctr : integer range 0 to 19;
> signal cycle_done : boolean;
> signal pw_done: boolean;
> 
> function bool2sl(b : boolean) return std_logic is
> begin
> if b then return '1'; else return '0'; end if;
> end function bool2sl;
> 
> begin
> 
> u_div : process(clk) is
> begin
> if rising_edge(clk) then
> cycle_done <= (tctr = 0); -- pipeline the comparator
> 
> if cycle_done
> then
> if RunAt100MHz = '1' then
> tctr <= 1 - 2; -- divide by 100 Meg
> else
> tctr <= 1000 - 2; -- divide by 10 Meg
> end if;
> 
> else
> tctr <= tctr - 1;
> end if;
> 
> end if; -- rising_edge()
> end process u_div;
> 
> 
> -- produce the standard 20 usec pulsewidth
> u_pulsewidth : process(clk) is
> begin
> if rising_edge(clk) then
> if cycle_done then
> if RunAt100MHz = '1' then
> pw_ctr <= 1;
> else
> pw_ctr <= 1999;
> end if;
> 
> elsif pw_ctr /= 0 then
> pw_ctr <= 

Re: [time-nuts] MV89A / MTI-260 / HP10811 carrier board

[Magnus Danielson]

Dear Gerhard,

I think you missed my point by reacting to the technology choice rather 
than the function I was proposing.


BTW, I write VHDL, assembler and C code as my daytime work, dealing with 
timing.


Cheers,
Magnus

On 02/26/2016 02:30 AM, Gerhard Hoffmann wrote:

Am 25.02.2016 um 22:23 schrieb Magnus Danielson:

Interesting. I would consider the PICDIV such as that of TADD-2, which
has the benefit of producing a range of frequencies, so that a
suitable can be selected as matching the needs. I've found it very
useful property of the TADD-2, where I have my TADD-2s wired up to
output one of each. I also wired them to output the buffered variant
of the clock, which gives better measures compared to running the sine
straight into the counters.


I have never used PICs and given their life cycle it's a bad time to
jump on the train.
Not now when I'm just converting everything to ARM. OTOH I have used
Xilinx since they exist
and this board is more or less a cleanup of things that are already there.


This here is all it takes for 10 and 100 MHz oscillators:

--

-- Company: Hoffmann RF & DSP
-- Create Date:09:09:37 08/08/2012
-- Module Name:pps1_generator - Behavioral
-- Target Devices:   X2c64A-5VQ44
-- Additional Comments:   Free firmware under BSD license
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity pps1_generator is
 Port(
 clk : in  STD_LOGIC;
 RunAt100MHz : in  STD_LOGIC;
 pps1_out: out STD_LOGIC;
 );
end pps1_generator;

architecture Behavioral of pps1_generator is
 signal tctr   : integer range 0 to ;
 signal pw_ctr : integer range 0 to 19;
 signal cycle_done : boolean;
 signal pw_done: boolean;

 function bool2sl(b : boolean) return std_logic is
 begin
 if b then return '1'; else return '0'; end if;
 end function bool2sl;

begin

 u_div : process(clk) is
 begin
 if rising_edge(clk) then
 cycle_done <= (tctr = 0); -- pipeline the comparator

 if cycle_done
 then
 if RunAt100MHz = '1' then
 tctr <= 1 - 2; -- divide by 100 Meg
 else
 tctr <= 1000 - 2; -- divide by 10 Meg
 end if;

 else
 tctr <= tctr - 1;
 end if;

 end if; -- rising_edge()
 end process u_div;


-- produce the standard 20 usec pulsewidth
 u_pulsewidth : process(clk) is
 begin
 if rising_edge(clk) then
 if cycle_done then
 if RunAt100MHz = '1' then
 pw_ctr <= 1;
 else
 pw_ctr <= 1999;
 end if;

 elsif pw_ctr /= 0 then
 pw_ctr <= pw_ctr - 1;
 end if;

 pps1_out <= bool2sl(pw_ctr /= 0);

 end if; -- rising_edge()
 end process u_pulsewidth;

end Behavioral;
-




I have also a version that fits into 2 chips, runs at Osc = 200 MHz and
produces a fixed 1/10/100/1000pps and another pps that can be shifted
against the first one in 5nsec steps over > 1 second.
It also provides control for a Micrel ECL chip that does the ps
interpolation
between the 5 ns steps.

It has a shift register interface that is controlled by a Beagle Bone Black
under Debian Linux, so network access is free.

Ideal for testing ranging systems and TICs / TDCs, but it still needs
some software.



The power-supply input didn't look all that clear. It would be handy
if a single input could be used.


It can run on  -5...-8V (for the opamps) and +12V for Morion and MTI;
the HP10811 needs 20V or so
for its heater. In this case the 12V is made from the 20V. I do not want
a switcher there.




I could probably have use for several of these boards.


Me too. I have recently decremented the number of available Lucent REF 0
plug-ins quite substantially.

(BTW: The Lucent REF 1 units with GPS are completely sold out for good,
I have asked.)

The idea is to lock 8 or 16   5 MHz MTI-260s to something long-time
stable and see
how far I get wrt phase noise when I combine the outputs.

Seems to be more promising than that promiscuous coupled resonator stuff
that was promoted recently. It is even somewhat tunable.

I like throwing repetitive hardware at problems when I get sth. in return.
Like my 220pv/sqrtHz preamp with 20 low noise opamps averaged.

regards, Gerhard, DK4XP


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Re: [time-nuts] MV89A / MTI-260 / HP10811 carrier board

[Gerhard Hoffmann]

Am 25.02.2016 um 22:23 schrieb Magnus Danielson:
Interesting. I would consider the PICDIV such as that of TADD-2, which 
has the benefit of producing a range of frequencies, so that a 
suitable can be selected as matching the needs. I've found it very 
useful property of the TADD-2, where I have my TADD-2s wired up to 
output one of each. I also wired them to output the buffered variant 
of the clock, which gives better measures compared to running the sine 
straight into the counters.


I have never used PICs and given their life cycle it's a bad time to 
jump on the train.
Not now when I'm just converting everything to ARM. OTOH I have used 
Xilinx since they exist

and this board is more or less a cleanup of things that are already there.


This here is all it takes for 10 and 100 MHz oscillators:

--
-- Company: Hoffmann RF & DSP
-- Create Date:09:09:37 08/08/2012
-- Module Name:pps1_generator - Behavioral
-- Target Devices:   X2c64A-5VQ44
-- Additional Comments:   Free firmware under BSD license
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity pps1_generator is
Port(
clk : in  STD_LOGIC;
RunAt100MHz : in  STD_LOGIC;
pps1_out: out STD_LOGIC;
);
end pps1_generator;

architecture Behavioral of pps1_generator is
signal tctr   : integer range 0 to ;
signal pw_ctr : integer range 0 to 19;
signal cycle_done : boolean;
signal pw_done: boolean;

function bool2sl(b : boolean) return std_logic is
begin
if b then return '1'; else return '0'; end if;
end function bool2sl;

begin

u_div : process(clk) is
begin
if rising_edge(clk) then
cycle_done <= (tctr = 0); -- pipeline the comparator

if cycle_done
then
if RunAt100MHz = '1' then
tctr <= 1 - 2; -- divide by 100 Meg
else
tctr <= 1000 - 2; -- divide by 10 Meg
end if;

else
tctr <= tctr - 1;
end if;

end if; -- rising_edge()
end process u_div;


-- produce the standard 20 usec pulsewidth
u_pulsewidth : process(clk) is
begin
if rising_edge(clk) then
if cycle_done then
if RunAt100MHz = '1' then
pw_ctr <= 1;
else
pw_ctr <= 1999;
end if;

elsif pw_ctr /= 0 then
pw_ctr <= pw_ctr - 1;
end if;

pps1_out <= bool2sl(pw_ctr /= 0);

end if; -- rising_edge()
end process u_pulsewidth;

end Behavioral;
-



I have also a version that fits into 2 chips, runs at Osc = 200 MHz and
produces a fixed 1/10/100/1000pps and another pps that can be shifted
against the first one in 5nsec steps over > 1 second.
It also provides control for a Micrel ECL chip that does the ps 
interpolation

between the 5 ns steps.

It has a shift register interface that is controlled by a Beagle Bone Black
under Debian Linux, so network access is free.

Ideal for testing ranging systems and TICs / TDCs, but it still needs
some software.



The power-supply input didn't look all that clear. It would be handy 
if a single input could be used.


It can run on  -5...-8V (for the opamps) and +12V for Morion and MTI; 
the HP10811 needs 20V or so
for its heater. In this case the 12V is made from the 20V. I do not want 
a switcher there.





I could probably have use for several of these boards.

Me too. I have recently decremented the number of available Lucent REF 0 
plug-ins quite substantially.


(BTW: The Lucent REF 1 units with GPS are completely sold out for good, 
I have asked.)


The idea is to lock 8 or 16   5 MHz MTI-260s to something long-time 
stable and see

how far I get wrt phase noise when I combine the outputs.

Seems to be more promising than that promiscuous coupled resonator stuff
that was promoted recently. It is even somewhat tunable.

I like throwing repetitive hardware at problems when I get sth. in return.
Like my 220pv/sqrtHz preamp with 20 low noise opamps averaged.

regards, Gerhard, DK4XP


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Re: [time-nuts] MV89A / MTI-260 / HP10811 carrier board

[Gerhard Hoffmann]

Am 25.02.2016 um 20:06 schrieb Anders Wallin:

Hi, looks quite useful!
What's the benefit of the Xilinx CPLD (2-3 dollars/euro) over a PICDIV (<1
dollar/euro) ?

My work would cost more than 1-2 €


Sync-input for the PPS-output would be useful. Also a PPS LED that blinks.
If the PPS-divider is directly under the OCXO it will get more or less warm
- could that be a problem?

It is only useful as long as the oscillator is disciplined by the 1pps.
If the osc and the 1pps drift against each other, that is really bad.

I have written a VHDL implementation of the AD9901 phase detector
that could fit into the CPLD ( 6 Macrocells IIRC). It is a 1:1 translation
of the circuit in the data sheet. Still untested, would work for 1pps.
Maybe in V2.0.  Getting sth. that works is more important now.

That the divider gets warm is unimportant. The resynchronisation
flipflop, 1pps driver and the squarers are what counts.

I'd like to have the blinkenlights offboard. I read about a Tektronix
sampling scope that had sampling jitter to the tune of a blinking LED.



What's the idea with the mixer/DIY-PLL? Did you look at PLL-chips instead?
It is much like the circuit used by Riley and I had good results with it 
and similar

ones also.


Would it make sense to have the time-constant for the PLL-loop adjustable
with jumpers or a pot? Lock-indicator LED?

Maybe a decoupled testpoint for the tuning voltage, so one can watch it on
a meter. Unless it's so bad that there are cycle slips it is hard to say
automatically if it is locked.

And I hate pots. I want thin film fixed resistors.



Could the board be 100mm wide with all the connections on one 100mm side,
to allow vertical rack-mounting ('plug-in' unit) in a 3U enclosure?

You will need some shielding, both electrically and against air movement.

regards, Gerhard  DK4XP
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Re: [time-nuts] MV89A / MTI-260 / HP10811 carrier board

[Magnus Danielson]

Hi Gerhard,

Interesting. I would consider the PICDIV such as that of TADD-2, which 
has the benefit of producing a range of frequencies, so that a suitable 
can be selected as matching the needs. I've found it very useful 
property of the TADD-2, where I have my TADD-2s wired up to output one 
of each. I also wired them to output the buffered variant of the clock, 
which gives better measures compared to running the sine straight into 
the counters.


The power-supply input didn't look all that clear. It would be handy if 
a single input could be used.


I could probably have use for several of these boards.

Cheers,
Magnus

On 02/25/2016 04:25 PM, Gerhard Hoffmann wrote:

HI,

I have made some progress on my crystal oven carrier board.

It will offer a home for one of these:

- MTI-260

- Morion MV89A

- HP 10811-611


It provides regulated voltages for either of them, and the needed
electronics.

It will be possible to lock the resident oscillator to an external
reference frequency,

tune it a few Hz using a 10-turn-pot or an external tuning voltage from
0 to 5 volts.

The 10811 oscillator does not have a stable tuning reference voltage
output, it will be

provided.

There is a Xilinx Coolrunner 2C64 CPLD that generates a 1pps output from
the

resident oscillator with the usual 20 us pulsewidth.

The squarer that feeds the CPLD is either a LT6759-4 or my
implementation of

C.Steinmetz's interpretation of C.Wenzel's version of the standard
differential limiter.

The 1PPS can drive 3V3 CMOS, terminated with 50 Ohms. The output of the
CPLD

is re-clocked in a 74LVC74 Flipflop directly from the limiting amplifier.

There is a 1 stage common base isolation amplifier between the output of
the oscillator

and the output of the board. It can be configured to work as a push-pull
active frequency
doubler without attenuation instead. There are 2 or 3 crystal notches to
remove the
closest (sub-)harmonics without affecting carrier phase stability.


Board size is abt. 100 * 110 square mm.

The design is modular from predefined macros. You can cut it into pieces
and get:


3 positive voltage regulators, LM317 style

1 negative voltage regulator, LM337 style

2 current feedback amplifiers using LMH6702 / AD8009 etc

1 ring mixer using a low 1/f noise Avago diode ring

1 PLL-regulator

1 isolation or frequency doubler amplifier

1 LT6759-4 limiter

1 Wenzel limiter

1 Xilinx 2C64 Coolrunner with pins on 100 mil grid

1 3V3-CMOS reclocked driver for 50 Ohm load.

1 input power meter


Connections to the modules are on a 100 mil grid, so one can

rearrange/recycle everything on Vector board or such.

This is open source hardware under BSD rules.
I do not intend to sell boards on a commercial base,

maybe there will be some samples to get things started.
All parts are available from Digikey/Mouser.

I'm currently doing the layout and will be trough with it in a week or so.
proposals, spotted errors, what to do with the empty space etc. are
welcome.
(but not on parts values, that will be taken care of later)

circuits can be found under

<
http://www.hoffmann-hochfrequenz.de/downloads/CrystalOvenCarrierBoard.pdf >

This is no product documentation but a quick snapshot as of this afternoon.
One thing that is missing is sync'ing on a 1PPs instead of the external
frequency reference.

regards, Gerhard, DK4XP




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Re: [time-nuts] MV89A / MTI-260 / HP10811 carrier board

[Anders Wallin]

Hi, looks quite useful!
What's the benefit of the Xilinx CPLD (2-3 dollars/euro) over a PICDIV (<1
dollar/euro) ?
Sync-input for the PPS-output would be useful. Also a PPS LED that blinks.
If the PPS-divider is directly under the OCXO it will get more or less warm
- could that be a problem?

What's the idea with the mixer/DIY-PLL? Did you look at PLL-chips instead?
Would it make sense to have the time-constant for the PLL-loop adjustable
with jumpers or a pot? Lock-indicator LED?

Could the board be 100mm wide with all the connections on one 100mm side,
to allow vertical rack-mounting ('plug-in' unit) in a 3U enclosure?

here's a link to a similar-ish board, for comparison/inspiration:
http://www.qsl.net/bi7lnq/distribution_amp/v1.5/10M_distributor.pdf

cheers,

Anders
PS. use Kicad for your next OSHW design! ;)


On Thu, Feb 25, 2016 at 5:25 PM, Gerhard Hoffmann  wrote:

> HI,
>
> I have made some progress on my crystal oven carrier board.
>
> It will offer a home for one of these:
>
> - MTI-260
>
> - Morion MV89A
>
> - HP 10811-611
>
>
> It provides regulated voltages for either of them, and the needed
> electronics.
>
> It will be possible to lock the resident oscillator to an external
> reference frequency,
>
> tune it a few Hz using a 10-turn-pot or an external tuning voltage from 0
> to 5 volts.
>
> The 10811 oscillator does not have a stable tuning reference voltage
> output, it will be
>
> provided.
>
> There is a Xilinx Coolrunner 2C64 CPLD that generates a 1pps output from
> the
>
> resident oscillator with the usual 20 us pulsewidth.
>
> The squarer that feeds the CPLD is either a LT6759-4 or my implementation
> of
>
> C.Steinmetz's interpretation of C.Wenzel's version of the standard
> differential limiter.
>
> The 1PPS can drive 3V3 CMOS, terminated with 50 Ohms. The output of the
> CPLD
>
> is re-clocked in a 74LVC74 Flipflop directly from the limiting amplifier.
>
> There is a 1 stage common base isolation amplifier between the output of
> the oscillator
>
> and the output of the board. It can be configured to work as a push-pull
> active frequency
> doubler without attenuation instead. There are 2 or 3 crystal notches to
> remove the
> closest (sub-)harmonics without affecting carrier phase stability.
>
>
> Board size is abt. 100 * 110 square mm.
>
> The design is modular from predefined macros. You can cut it into pieces
> and get:
>
>
> 3 positive voltage regulators, LM317 style
>
> 1 negative voltage regulator, LM337 style
>
> 2 current feedback amplifiers using LMH6702 / AD8009 etc
>
> 1 ring mixer using a low 1/f noise Avago diode ring
>
> 1 PLL-regulator
>
> 1 isolation or frequency doubler amplifier
>
> 1 LT6759-4 limiter
>
> 1 Wenzel limiter
>
> 1 Xilinx 2C64 Coolrunner with pins on 100 mil grid
>
> 1 3V3-CMOS reclocked driver for 50 Ohm load.
>
> 1 input power meter
>
>
> Connections to the modules are on a 100 mil grid, so one can
>
> rearrange/recycle everything on Vector board or such.
>
> This is open source hardware under BSD rules.
> I do not intend to sell boards on a commercial base,
>
> maybe there will be some samples to get things started.
> All parts are available from Digikey/Mouser.
>
> I'm currently doing the layout and will be trough with it in a week or so.
> proposals, spotted errors, what to do with the empty space etc. are
> welcome.
> (but not on parts values, that will be taken care of later)
>
> circuits can be found under
>
> <
> http://www.hoffmann-hochfrequenz.de/downloads/CrystalOvenCarrierBoard.pdf
> >
>
> This is no product documentation but a quick snapshot as of this afternoon.
> One thing that is missing is sync'ing on a 1PPs instead of the external
> frequency reference.
>
> regards, Gerhard, DK4XP
>
>
>
>
> ___
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to
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> and follow the instructions there.
>
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[time-nuts] MV89A / MTI-260 / HP10811 carrier board

[Gerhard Hoffmann]

HI,

I have made some progress on my crystal oven carrier board.

It will offer a home for one of these:

- MTI-260

- Morion MV89A

- HP 10811-611


It provides regulated voltages for either of them, and the needed 
electronics.


It will be possible to lock the resident oscillator to an external 
reference frequency,


tune it a few Hz using a 10-turn-pot or an external tuning voltage from 
0 to 5 volts.


The 10811 oscillator does not have a stable tuning reference voltage 
output, it will be


provided.

There is a Xilinx Coolrunner 2C64 CPLD that generates a 1pps output from 
the


resident oscillator with the usual 20 us pulsewidth.

The squarer that feeds the CPLD is either a LT6759-4 or my 
implementation of


C.Steinmetz's interpretation of C.Wenzel's version of the standard 
differential limiter.


The 1PPS can drive 3V3 CMOS, terminated with 50 Ohms. The output of the CPLD

is re-clocked in a 74LVC74 Flipflop directly from the limiting amplifier.

There is a 1 stage common base isolation amplifier between the output of 
the oscillator


and the output of the board. It can be configured to work as a push-pull 
active frequency
doubler without attenuation instead. There are 2 or 3 crystal notches to 
remove the

closest (sub-)harmonics without affecting carrier phase stability.


Board size is abt. 100 * 110 square mm.

The design is modular from predefined macros. You can cut it into pieces 
and get:



3 positive voltage regulators, LM317 style

1 negative voltage regulator, LM337 style

2 current feedback amplifiers using LMH6702 / AD8009 etc

1 ring mixer using a low 1/f noise Avago diode ring

1 PLL-regulator

1 isolation or frequency doubler amplifier

1 LT6759-4 limiter

1 Wenzel limiter

1 Xilinx 2C64 Coolrunner with pins on 100 mil grid

1 3V3-CMOS reclocked driver for 50 Ohm load.

1 input power meter


Connections to the modules are on a 100 mil grid, so one can

rearrange/recycle everything on Vector board or such.

This is open source hardware under BSD rules.
I do not intend to sell boards on a commercial base,

maybe there will be some samples to get things started.
All parts are available from Digikey/Mouser.

I'm currently doing the layout and will be trough with it in a week or so.
proposals, spotted errors, what to do with the empty space etc. are welcome.
(but not on parts values, that will be taken care of later)

circuits can be found under

< 
http://www.hoffmann-hochfrequenz.de/downloads/CrystalOvenCarrierBoard.pdf >


This is no product documentation but a quick snapshot as of this afternoon.
One thing that is missing is sync'ing on a 1PPs instead of the external 
frequency reference.


regards, Gerhard, DK4XP




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