Am 27.02.2016 um 16:15 schrieb Bob Camp:
Hi
You will run into the same problem on the Altera side. Their “super suite” is
called Quartus and
the latest free version only supports the newer parts. Once you get a few
generations back, you
need to download an older version. That’s not impossible to do or crazy to work
with. The newer
stuff is a bit better. The generation to generation transitions are not insane,
but they will take up
time working this and that out. Much better (if possible) to start with a part
that the current software
just started supporting. In the Altera case that is the Max10 family. The
lowest cost member is
less than $4 in single piece quantity on Mouser. Yes it’s a BGA. The leaded
parts are about $11 or so.
Demo boards with various cool things on them are < $40.
Yes this sounds like an advertisement for Altera. It’s not really. All of the
same basic issues apply equally
to the other vendors. It’s a competitive world and they all do a pretty fast
game of catch up. The only unique
feature (AFIK) with Quartus is the inclusion of schematic entry. It lets you do
a “no code” design if you are
more familiar with logic schematics than with VHDL. If any of the “other guys”
do this, it would be worth knowing
about in the context of many of the people on the list being a bit code shy.
Xilinx used to have Futurenet as circuit entry and after massive begging
of the
community they also provided an interface from Orcad. But that was long ago.
I think they still have something of their own, but I have converted to
pure VHDL
some 15 years ago and never looked back. Maybe over the fence to Verilog.
I have a Altium Designer license of my own and I think it can do circuit
diagrams to FPGA via VHDL, but never took the time to poke around in that
corner.
The 2C64 is so small that about any ISE version is ok for it. The VHDL
source
of my pps generator would compile for an Microsemi Igloo , Altera,
Spartan, Whatever.. without change.
That does not mean that I'm a Xilinx fan boy. Nothing could be more wrong.
I'm currently doing some ORIGINAL Virtex FPGAs, not Virtex II, 2E, 4, 5,
7..
in the Aces space project (to get the link to TimeNuttery) and they were
agreed on in 2002.
Xilinx now nearly deny fatherhood and it is fun to write specialties like a
configuration memory scrubber when even a certain app note seems to be
removed from everywhere; maybe an ITAR thing.
The latest ISE version that supports original Virtex is 10.1, with a
nearly defunct project management. V7 to 9 were even worse.
Now that Altera is in bed with Intel, that's a good perspective.
regards, Gerhard
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