Gerhard,
On 02/27/2016 07:16 PM, Gerhard Hoffmann wrote:
Am 27.02.2016 um 16:15 schrieb Bob Camp:
Xilinx used to have Futurenet as circuit entry and after massive begging
of the
community they also provided an interface from Orcad. But that was long
ago.
I think they still have something of their own, but I have converted to
pure VHDL
some 15 years ago and never looked back. Maybe over the fence to Verilog.
I have a Altium Designer license of my own and I think it can do circuit
diagrams to FPGA via VHDL, but never took the time to poke around in that
corner.
The 2C64 is so small that about any ISE version is ok for it. The VHDL
source
of my pps generator would compile for an Microsemi Igloo , Altera,
Spartan, Whatever.. without change.
That does not mean that I'm a Xilinx fan boy. Nothing could be more wrong.
I'm currently doing some ORIGINAL Virtex FPGAs, not Virtex II, 2E, 4, 5,
7..
in the Aces space project (to get the link to TimeNuttery) and they were
agreed on in 2002.
In a box I have some of our test-boards using the Virtex, which we used
to validate our ASIC design. We made the boards so ugly they could not
easily be made into a product. :)
I did my first real VHDL design on those boards, in the end of the
previous millennium and for the ASIC. I remember when we got the -6
chips, it was some 4000 dollars a piece.
What was most annoying was that I had to finish my design before going
the VHDL coarse. Let me say that as I got back from the coarse I improve
test-benches and coding a lot. I did one mistake, which we could fix in
the metallic layer change we got for free, but which never affected any
of the products as we never used that feature in any of the products
anyway. As the FPGAs got more powerful we didn't go back to the world of
ASIC and once we got the FPGA FW upgradeable just like any other FW, we
have not looked back, it is now released just as any SW.
Xilinx now nearly deny fatherhood and it is fun to write specialties like a
configuration memory scrubber when even a certain app note seems to be
removed from everywhere; maybe an ITAR thing.
CPLD is still a nice technology, it just that like PAL, only go that
far. I remember when CPLD was like a more complex PAL/PLD and then
looking at the XC3000 or even to the XC4000 sea of gates.... whoo...
Our first product was based on the XC4000 chips and ran for very long. I
think there is still some networks out there running those boxes, as we
just released an upgrade for it. It also has some CPLDs in them. One is
however a particular hate-object for me, as we never could change it
into a better design and solve some of its fundamental limits. Not
because CPLD as such, but because we had one in the wrong place. Ah
well, we learned from that experience.
The latest ISE version that supports original Virtex is 10.1, with a
nearly defunct project management. V7 to 9 were even worse.
Its not all good that they drop support as they go. Hobbyists often use
old devices as well as new.
Now that Altera is in bed with Intel, that's a good perspective.
Not convinced.
Cheers,
Magnus
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