[time-nuts] Re: Commercial solution - 122.88 MHz low noise source

[jeanmichel . friedt]

> First, does the installed TCXO have EFC capability, or not? Jeff apparently 
> says not, while Gerhard
> says yes. According to the datasheet, the ABLNO can be an XO only (no 
> suffix), or a VCXO ("V"
> suffix). Jeff should be able to tell which, by inspection.

The 16-bit Redpitaya I am looking at right now is "ABLNO 122.880 MHz F9X" so no 
"V" suffix.
The datasheet is e.g. at 
https://4donline.ihs.com/images/VipMasterIC/IC/ABRC/ABRC-S-A0009700443/ABRC-S-A0009775374-1.pdf?hkey=52A5661711E402568146F3353EA87419

Best, JM
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[time-nuts] Re: Commercial solution - 122.88 MHz low noise source

[ed breya]

I was curious and looked up this Red Pitaya SDR thing (which I had never 
heard of - I would have guessed a poisonous snake, without the 
internet), and the Abracom TCXO. It's getting a little confusing to keep 
up with what's going on.


First, does the installed TCXO have EFC capability, or not? Jeff 
apparently says not, while Gerhard says yes. According to the datasheet, 
the ABLNO can be an XO only (no suffix), or a VCXO ("V" suffix). Jeff 
should be able to tell which, by inspection.


It appears now that 125 MHz won't work, unless maybe the internal SW 
allows enough frequency offset to be set - TBD, I guess.


A current option seems to be putting the "same" kind of TCXO in a 
separate box to insulate it somewhat from ambient changes. After seeing 
what all the pieces look like, this makes sense, but why not be sure to 
get the ABLNO-V VCXO version, which would allow for PLLing if the 
thermal stuff is not satisfactory, or just because? You may decide to 
forget about the thermal stuff and just do a PLL anyway, with more 
confidence in the result.


If it turns out that the already installed TCXO is VC, then of course 
you could just leave it in, and (carefully) tap off some output for the 
PLL, and add an EFC line back. I think that was one of the possible 
scenarios mentioned in discussion. By the looks of it, it seems like 
trying to remove or replace the installed part, or doing any major mods, 
would be risky to the board.


Ed
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[time-nuts] Re: Commercial solution - 122.88 Mhz low noise source

[Jeff Blaine]

Unfortunately I don't have any control over the code being run. So it's 
got to be fed with the stock Fc.  Now that I think of it, there is an 
offset in the config file for the application.  The typical offsets are 
in the 1.xNNN tweaks.  But given that range, I'm wondering if I 
could pull the software offset off enough to let the homebrew 125 OCXO 
work for this application. Hmmm...


And on the replacement source, given the stock clock is of the "pretty 
clean" variety, and it's only a temp issue, I'm wondering now if another 
way to get to my end point simply is to address the environment instead 
of the frequency directly.  I could build a double insulated enclosure 
for a replacement clock using the same XO as it has now.  So the XO is 
in an insulated box.  And that sits in another (also insulated) box 
which has some small heating capacity for the space between the inner 
and outer box.  I think that if this resulted in a net temp change vs. 
time that's maybe 1/4 of the entire range, that would be "good enough" 
with respect to F accuracy.  And there would be no compromise on the 
clock's quality.


73/jeff/ac0c
alpha-charlie-zero-charlie
www.ac0c.com


On 4/4/22 12:56 PM, Philip Gladstone wrote:

I'm wondering if you could feed your stable 10MHz into the RP FPGA and then
change the FPGA code to use that as the master clock source and adjust the
PLL coefficients.

On Mon, Apr 4, 2022 at 1:45 PM Bob kb8tq  wrote:


Hi

That’s a massive step down from what’s in there now. How much
that impacts you depends a lot on what the end use is.  The plots
shown are in the vicinity of 10 MHz. If a straight multiply rule applies,
the performance at 122 MHz would be about 20 db worse. The chip
datasheet:


https://www.skyworksinc.com/-/media/SkyWorks/SL/documents/public/data-sheets/Si5328.pdf
<
https://www.skyworksinc.com/-/media/SkyWorks/SL/documents/public/data-sheets/Si5328.pdf
suggests that this is likely to be true for offsets < 100 KHz.


No, this isn’t in any way a knock on that GPSDO. It’s doing what it
was designed to do. I’m sure it works very well. It simply isn’t
targeted at the same sort of noise level as what’s on there now.

Bob


On Apr 4, 2022, at 11:35 AM, Jeff Blaine 

wrote:

I found a commercial programmable GPSDO that looks like it would do the

job.  Based on a Si chip.



http://leobodnar.com/files/Informal%20Evaluation%20of%20a%20Leo%20Bodnar%20GPS%20Frequency%20Reference.pdf

Performance is not in the "great" category but I am guessing it would be

in the "good enough" category.  And it does not require any design work or
project construction time.

73/jeff/ac0c
alpha-charlie-zero-charlie
www.ac0c.com


On 4/4/22 7:36 AM, Bob kb8tq wrote:

Hi

For a variety of reasons, you will have a loop bandwidth in the > 10 Hz
to < 200 Hz region. The VCXO isn’t great close in and the GPSDO (even
after multiplication) should be as good / better. Even with some work,
the VCXO still will wander around due to temperature. Unless you go
crazy, it also will wander a bit from supply. There’s also the chance of
vibration or shock.

As mentioned in another post, component values on an properly designed
analog loop running one of the typical chips get pretty crazy at very

low

loop bandwidths. You now get into questions about sensitivity of

components

if you go with certain ceramics, leakage if you run an electrolytic,

and with

size if you go with something else.

Bandwidth and damping ( or phase margin ) are two independent variables
when you design a PLL. You can have a narrowband bandwidth and a lot
of damping or the same bandwidth without much damping. It’s all in the
design equations ….

Bob


On Apr 3, 2022, at 11:22 PM, Jeff Blaine 

wrote:

It looks like the XO version is mounted on the PCB.  But there is a

VCXO version which would run about +/- 35 PPM/3.3V typical and that's
(amazingly) available.

Since this EFT is not an on-board capability, at the moment, I'm

thinking to mount the VCXO - and associated goodies to slave it to the 10
Mhz GPSDO feed - in a separate enclosure that could allow the VCXO to be
thermally insulated.  The temp swing vs. time will move very slowly and
that would allow a very damped PLL loop to apply corrections.

I've not done anything with a PLL before but I don't envision this as

being too complicated.  And it would be a pretty cool project.  Don't need
true "phase" lock, but rather "frequency control" without degrading the
noise characteristics of the VCXO.

73/jeff/ac0c
alpha-charlie-zero-charlie
www.ac0c.com


On 4/3/22 7:38 PM, Lux, Jim wrote:

On 4/3/22 5:09 PM, Bob kb8tq wrote:

Hi

Does the Abricon have an EFC input? If so, rigging up a PLL to lock
122.88 to 10 MHz is probably the best option.

Bob

And what about moving off the board - so you don't have to chase the

temperature swings.



On Apr 3, 2022, at 7:57 PM, Jeff Blaine 

wrote:

I've got a couple of Red Pitaya 122-16 SDR and want to discipline

them to an external low noise GPSDO source.  

[time-nuts] Re: Commercial solution - 122.88 Mhz low noise source

[Philip Gladstone]

I'm wondering if you could feed your stable 10MHz into the RP FPGA and then
change the FPGA code to use that as the master clock source and adjust the
PLL coefficients.

On Mon, Apr 4, 2022 at 1:45 PM Bob kb8tq  wrote:

> Hi
>
> That’s a massive step down from what’s in there now. How much
> that impacts you depends a lot on what the end use is.  The plots
> shown are in the vicinity of 10 MHz. If a straight multiply rule applies,
> the performance at 122 MHz would be about 20 db worse. The chip
> datasheet:
>
>
> https://www.skyworksinc.com/-/media/SkyWorks/SL/documents/public/data-sheets/Si5328.pdf
> <
> https://www.skyworksinc.com/-/media/SkyWorks/SL/documents/public/data-sheets/Si5328.pdf
> >
>
> suggests that this is likely to be true for offsets < 100 KHz.
>
>
> No, this isn’t in any way a knock on that GPSDO. It’s doing what it
> was designed to do. I’m sure it works very well. It simply isn’t
> targeted at the same sort of noise level as what’s on there now.
>
> Bob
>
> > On Apr 4, 2022, at 11:35 AM, Jeff Blaine 
> wrote:
> >
> > I found a commercial programmable GPSDO that looks like it would do the
> job.  Based on a Si chip.
> >
> >
> http://leobodnar.com/files/Informal%20Evaluation%20of%20a%20Leo%20Bodnar%20GPS%20Frequency%20Reference.pdf
> >
> > Performance is not in the "great" category but I am guessing it would be
> in the "good enough" category.  And it does not require any design work or
> project construction time.
> >
> > 73/jeff/ac0c
> > alpha-charlie-zero-charlie
> > www.ac0c.com
> >
> >
> > On 4/4/22 7:36 AM, Bob kb8tq wrote:
> >> Hi
> >>
> >> For a variety of reasons, you will have a loop bandwidth in the > 10 Hz
> >> to < 200 Hz region. The VCXO isn’t great close in and the GPSDO (even
> >> after multiplication) should be as good / better. Even with some work,
> >> the VCXO still will wander around due to temperature. Unless you go
> >> crazy, it also will wander a bit from supply. There’s also the chance of
> >> vibration or shock.
> >>
> >> As mentioned in another post, component values on an properly designed
> >> analog loop running one of the typical chips get pretty crazy at very
> low
> >> loop bandwidths. You now get into questions about sensitivity of
> components
> >> if you go with certain ceramics, leakage if you run an electrolytic,
> and with
> >> size if you go with something else.
> >>
> >> Bandwidth and damping ( or phase margin ) are two independent variables
> >> when you design a PLL. You can have a narrowband bandwidth and a lot
> >> of damping or the same bandwidth without much damping. It’s all in the
> >> design equations ….
> >>
> >> Bob
> >>
> >>> On Apr 3, 2022, at 11:22 PM, Jeff Blaine 
> wrote:
> >>>
> >>> It looks like the XO version is mounted on the PCB.  But there is a
> VCXO version which would run about +/- 35 PPM/3.3V typical and that's
> (amazingly) available.
> >>>
> >>> Since this EFT is not an on-board capability, at the moment, I'm
> thinking to mount the VCXO - and associated goodies to slave it to the 10
> Mhz GPSDO feed - in a separate enclosure that could allow the VCXO to be
> thermally insulated.  The temp swing vs. time will move very slowly and
> that would allow a very damped PLL loop to apply corrections.
> >>>
> >>> I've not done anything with a PLL before but I don't envision this as
> being too complicated.  And it would be a pretty cool project.  Don't need
> true "phase" lock, but rather "frequency control" without degrading the
> noise characteristics of the VCXO.
> >>>
> >>> 73/jeff/ac0c
> >>> alpha-charlie-zero-charlie
> >>> www.ac0c.com
> >>>
> >>>
> >>> On 4/3/22 7:38 PM, Lux, Jim wrote:
>  On 4/3/22 5:09 PM, Bob kb8tq wrote:
> > Hi
> >
> > Does the Abricon have an EFC input? If so, rigging up a PLL to lock
> > 122.88 to 10 MHz is probably the best option.
> >
> > Bob
> 
>  And what about moving off the board - so you don't have to chase the
> temperature swings.
> 
> 
> >> On Apr 3, 2022, at 7:57 PM, Jeff Blaine 
> wrote:
> >>
> >> I've got a couple of Red Pitaya 122-16 SDR and want to discipline
> them to an external low noise GPSDO source.  Wanted to see if there were
> some easy solutions that fell into this category.
> >>
> >> For the prior generation (QS1R), I had built a homebrew OCXO based
> on a custom low noise crystal from ICM and that worked great for the 125
> Mhz application.  Unfortunately this Pitaya is a bit removed in Fc and ICM
> has been out of biz for several years now.
> >>
> >> The RP's on-board oscillator is the respectable Abracon ABLNO
> 122.88 which runs about -115 dBc/hz at 100 Hz spacing and that's probably
> not a limitation for the unit.  Unfortunately the OSC is a bit too
> sensitive to external temp and wanders around quite a lot (+/- 5 PPM)
> compared to the homebrew OCXO - over the annual ambient temp range of
> (10-35C) (all datasheet referenced values). The Abracon unit is mounted on
> the board with the FPGA and 

[time-nuts] Re: Commercial solution - 122.88 Mhz low noise source

[Bob kb8tq]

Hi

That’s a massive step down from what’s in there now. How much 
that impacts you depends a lot on what the end use is.  The plots
shown are in the vicinity of 10 MHz. If a straight multiply rule applies,
the performance at 122 MHz would be about 20 db worse. The chip 
datasheet:

https://www.skyworksinc.com/-/media/SkyWorks/SL/documents/public/data-sheets/Si5328.pdf
 


suggests that this is likely to be true for offsets < 100 KHz.


No, this isn’t in any way a knock on that GPSDO. It’s doing what it
was designed to do. I’m sure it works very well. It simply isn’t 
targeted at the same sort of noise level as what’s on there now. 

Bob

> On Apr 4, 2022, at 11:35 AM, Jeff Blaine  wrote:
> 
> I found a commercial programmable GPSDO that looks like it would do the job.  
> Based on a Si chip.
> 
> http://leobodnar.com/files/Informal%20Evaluation%20of%20a%20Leo%20Bodnar%20GPS%20Frequency%20Reference.pdf
> 
> Performance is not in the "great" category but I am guessing it would be in 
> the "good enough" category.  And it does not require any design work or 
> project construction time.
> 
> 73/jeff/ac0c
> alpha-charlie-zero-charlie
> www.ac0c.com
> 
> 
> On 4/4/22 7:36 AM, Bob kb8tq wrote:
>> Hi
>> 
>> For a variety of reasons, you will have a loop bandwidth in the > 10 Hz
>> to < 200 Hz region. The VCXO isn’t great close in and the GPSDO (even
>> after multiplication) should be as good / better. Even with some work,
>> the VCXO still will wander around due to temperature. Unless you go
>> crazy, it also will wander a bit from supply. There’s also the chance of
>> vibration or shock.
>> 
>> As mentioned in another post, component values on an properly designed
>> analog loop running one of the typical chips get pretty crazy at very low
>> loop bandwidths. You now get into questions about sensitivity of components
>> if you go with certain ceramics, leakage if you run an electrolytic,  and 
>> with
>> size if you go with something else.
>> 
>> Bandwidth and damping ( or phase margin ) are two independent variables
>> when you design a PLL. You can have a narrowband bandwidth and a lot
>> of damping or the same bandwidth without much damping. It’s all in the
>> design equations ….
>> 
>> Bob
>> 
>>> On Apr 3, 2022, at 11:22 PM, Jeff Blaine  wrote:
>>> 
>>> It looks like the XO version is mounted on the PCB.  But there is a VCXO 
>>> version which would run about +/- 35 PPM/3.3V typical and that's 
>>> (amazingly) available.
>>> 
>>> Since this EFT is not an on-board capability, at the moment, I'm thinking 
>>> to mount the VCXO - and associated goodies to slave it to the 10 Mhz GPSDO 
>>> feed - in a separate enclosure that could allow the VCXO to be thermally 
>>> insulated.  The temp swing vs. time will move very slowly and that would 
>>> allow a very damped PLL loop to apply corrections.
>>> 
>>> I've not done anything with a PLL before but I don't envision this as being 
>>> too complicated.  And it would be a pretty cool project.  Don't need true 
>>> "phase" lock, but rather "frequency control" without degrading the noise 
>>> characteristics of the VCXO.
>>> 
>>> 73/jeff/ac0c
>>> alpha-charlie-zero-charlie
>>> www.ac0c.com
>>> 
>>> 
>>> On 4/3/22 7:38 PM, Lux, Jim wrote:
 On 4/3/22 5:09 PM, Bob kb8tq wrote:
> Hi
> 
> Does the Abricon have an EFC input? If so, rigging up a PLL to lock
> 122.88 to 10 MHz is probably the best option.
> 
> Bob
 
 And what about moving off the board - so you don't have to chase the 
 temperature swings.
 
 
>> On Apr 3, 2022, at 7:57 PM, Jeff Blaine  wrote:
>> 
>> I've got a couple of Red Pitaya 122-16 SDR and want to discipline them 
>> to an external low noise GPSDO source.  Wanted to see if there were some 
>> easy solutions that fell into this category.
>> 
>> For the prior generation (QS1R), I had built a homebrew OCXO based on a 
>> custom low noise crystal from ICM and that worked great for the 125 Mhz 
>> application.  Unfortunately this Pitaya is a bit removed in Fc and ICM 
>> has been out of biz for several years now.
>> 
>> The RP's on-board oscillator is the respectable Abracon ABLNO 122.88 
>> which runs about -115 dBc/hz at 100 Hz spacing and that's probably not a 
>> limitation for the unit.  Unfortunately the OSC is a bit too sensitive 
>> to external temp and wanders around quite a lot (+/- 5 PPM) compared to 
>> the homebrew OCXO - over the annual ambient temp range of (10-35C) (all 
>> datasheet referenced values). The Abracon unit is mounted on the board 
>> with the FPGA and sees additional temp range depending on other heat 
>> generation factors (FPGA loading).
>> 
>> I have a couple of commercial GPSDO on the bench now, so a pretty clean 
>> 10 Mhz GPSDO reference is available now.  And I've seen enough board 
>> 

[time-nuts] Re: Commercial solution - 122.88 Mhz low noise source

[Jeff Blaine]

I found a commercial programmable GPSDO that looks like it would do the 
job.  Based on a Si chip.


http://leobodnar.com/files/Informal%20Evaluation%20of%20a%20Leo%20Bodnar%20GPS%20Frequency%20Reference.pdf

Performance is not in the "great" category but I am guessing it would be 
in the "good enough" category.  And it does not require any design work 
or project construction time.


73/jeff/ac0c
alpha-charlie-zero-charlie
www.ac0c.com


On 4/4/22 7:36 AM, Bob kb8tq wrote:

Hi

For a variety of reasons, you will have a loop bandwidth in the > 10 Hz
to < 200 Hz region. The VCXO isn’t great close in and the GPSDO (even
after multiplication) should be as good / better. Even with some work,
the VCXO still will wander around due to temperature. Unless you go
crazy, it also will wander a bit from supply. There’s also the chance of
vibration or shock.

As mentioned in another post, component values on an properly designed
analog loop running one of the typical chips get pretty crazy at very low
loop bandwidths. You now get into questions about sensitivity of components
if you go with certain ceramics, leakage if you run an electrolytic,  and with
size if you go with something else.

Bandwidth and damping ( or phase margin ) are two independent variables
when you design a PLL. You can have a narrowband bandwidth and a lot
of damping or the same bandwidth without much damping. It’s all in the
design equations ….

Bob


On Apr 3, 2022, at 11:22 PM, Jeff Blaine  wrote:

It looks like the XO version is mounted on the PCB.  But there is a VCXO 
version which would run about +/- 35 PPM/3.3V typical and that's (amazingly) 
available.

Since this EFT is not an on-board capability, at the moment, I'm thinking to 
mount the VCXO - and associated goodies to slave it to the 10 Mhz GPSDO feed - 
in a separate enclosure that could allow the VCXO to be thermally insulated.  
The temp swing vs. time will move very slowly and that would allow a very 
damped PLL loop to apply corrections.

I've not done anything with a PLL before but I don't envision this as being too complicated.  And 
it would be a pretty cool project.  Don't need true "phase" lock, but rather 
"frequency control" without degrading the noise characteristics of the VCXO.

73/jeff/ac0c
alpha-charlie-zero-charlie
www.ac0c.com


On 4/3/22 7:38 PM, Lux, Jim wrote:

On 4/3/22 5:09 PM, Bob kb8tq wrote:

Hi

Does the Abricon have an EFC input? If so, rigging up a PLL to lock
122.88 to 10 MHz is probably the best option.

Bob


And what about moving off the board - so you don't have to chase the 
temperature swings.



On Apr 3, 2022, at 7:57 PM, Jeff Blaine  wrote:

I've got a couple of Red Pitaya 122-16 SDR and want to discipline them to an 
external low noise GPSDO source.  Wanted to see if there were some easy 
solutions that fell into this category.

For the prior generation (QS1R), I had built a homebrew OCXO based on a custom 
low noise crystal from ICM and that worked great for the 125 Mhz application.  
Unfortunately this Pitaya is a bit removed in Fc and ICM has been out of biz 
for several years now.

The RP's on-board oscillator is the respectable Abracon ABLNO 122.88 which runs 
about -115 dBc/hz at 100 Hz spacing and that's probably not a limitation for 
the unit.  Unfortunately the OSC is a bit too sensitive to external temp and 
wanders around quite a lot (+/- 5 PPM) compared to the homebrew OCXO - over the 
annual ambient temp range of (10-35C) (all datasheet referenced values). The 
Abracon unit is mounted on the board with the FPGA and sees additional temp 
range depending on other heat generation factors (FPGA loading).

I have a couple of commercial GPSDO on the bench now, so a pretty clean 10 Mhz GPSDO 
reference is available now.  And I've seen enough board discussion to know that a 
homebrew GPSDO solution is one of those "it's harder than it looks" things.  
Hence the desire just to buy whatever is the silver bullet, as long as it does not 
require too much silver.  ha ha

Appreciate any suggestions.  TKs!

73/jeff/ac0c
alpha-charlie-zero-charlie
www.ac0c.com

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[time-nuts] Re: Commercial solution - 122.88 Mhz low noise source

[Bob kb8tq]

Hi

For a variety of reasons, you will have a loop bandwidth in the > 10 Hz 
to < 200 Hz region. The VCXO isn’t great close in and the GPSDO (even
after multiplication) should be as good / better. Even with some work,
the VCXO still will wander around due to temperature. Unless you go 
crazy, it also will wander a bit from supply. There’s also the chance of
vibration or shock. 

As mentioned in another post, component values on an properly designed
analog loop running one of the typical chips get pretty crazy at very low
loop bandwidths. You now get into questions about sensitivity of components
if you go with certain ceramics, leakage if you run an electrolytic,  and with 
size if you go with something else.

Bandwidth and damping ( or phase margin ) are two independent variables
when you design a PLL. You can have a narrowband bandwidth and a lot
of damping or the same bandwidth without much damping. It’s all in the 
design equations …. 

Bob

> On Apr 3, 2022, at 11:22 PM, Jeff Blaine  wrote:
> 
> It looks like the XO version is mounted on the PCB.  But there is a VCXO 
> version which would run about +/- 35 PPM/3.3V typical and that's (amazingly) 
> available.
> 
> Since this EFT is not an on-board capability, at the moment, I'm thinking to 
> mount the VCXO - and associated goodies to slave it to the 10 Mhz GPSDO feed 
> - in a separate enclosure that could allow the VCXO to be thermally 
> insulated.  The temp swing vs. time will move very slowly and that would 
> allow a very damped PLL loop to apply corrections.
> 
> I've not done anything with a PLL before but I don't envision this as being 
> too complicated.  And it would be a pretty cool project.  Don't need true 
> "phase" lock, but rather "frequency control" without degrading the noise 
> characteristics of the VCXO.
> 
> 73/jeff/ac0c
> alpha-charlie-zero-charlie
> www.ac0c.com
> 
> 
> On 4/3/22 7:38 PM, Lux, Jim wrote:
>> On 4/3/22 5:09 PM, Bob kb8tq wrote:
>>> Hi
>>> 
>>> Does the Abricon have an EFC input? If so, rigging up a PLL to lock
>>> 122.88 to 10 MHz is probably the best option.
>>> 
>>> Bob
>> 
>> 
>> And what about moving off the board - so you don't have to chase the 
>> temperature swings.
>> 
>> 
>>> 
 On Apr 3, 2022, at 7:57 PM, Jeff Blaine  wrote:
 
 I've got a couple of Red Pitaya 122-16 SDR and want to discipline them to 
 an external low noise GPSDO source.  Wanted to see if there were some easy 
 solutions that fell into this category.
 
 For the prior generation (QS1R), I had built a homebrew OCXO based on a 
 custom low noise crystal from ICM and that worked great for the 125 Mhz 
 application.  Unfortunately this Pitaya is a bit removed in Fc and ICM has 
 been out of biz for several years now.
 
 The RP's on-board oscillator is the respectable Abracon ABLNO 122.88 which 
 runs about -115 dBc/hz at 100 Hz spacing and that's probably not a 
 limitation for the unit.  Unfortunately the OSC is a bit too sensitive to 
 external temp and wanders around quite a lot (+/- 5 PPM) compared to the 
 homebrew OCXO - over the annual ambient temp range of (10-35C) (all 
 datasheet referenced values). The Abracon unit is mounted on the board 
 with the FPGA and sees additional temp range depending on other heat 
 generation factors (FPGA loading).
 
 I have a couple of commercial GPSDO on the bench now, so a pretty clean 10 
 Mhz GPSDO reference is available now.  And I've seen enough board 
 discussion to know that a homebrew GPSDO solution is one of those "it's 
 harder than it looks" things.  Hence the desire just to buy whatever is 
 the silver bullet, as long as it does not require too much silver.  ha ha
 
 Appreciate any suggestions.  TKs!
 
 73/jeff/ac0c
 alpha-charlie-zero-charlie
 www.ac0c.com
 
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 time-nuts mailing list -- time-nuts@lists.febo.com -- To unsubscribe send 
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[time-nuts] Re: Commercial solution - 122.88 Mhz low noise source

[glen english LIST]

Jeff one thing to be careful of with slower (lower bandwidth) PLLs and 
low VCO gains, is that you end up with loop filter capacitor values  
that is microfarads.


This will require film, tantalum etc caps that are not microphonic 
sensitive. this needs a bit of space. Ceramic caps make good microphones 
! Same considerations  for (large) power supply bypasses .. if your pcb 
is in foam in a box, not say bolted to an aluminium chassis in a 
vehicle, you may have an easier time.


-glen

On 4/04/2022 1:22 pm, Jeff Blaine wrote:
It looks like the XO version is mounted on the PCB.  But there is a 
VCXO version which would run about +/- 35 PPM/3.3V typical and that's 
(amazingly) available.


Since this EFT is not an on-board capability, at the moment, I'm 
thinking to mount the VCXO - and associated goodies to slave it to the 
10 Mhz GPSDO feed - in a separate enclosure that could allow the VCXO 
to be thermally insulated.  The temp swing vs. time will move very 
slowly and that would allow a very damped PLL loop to apply corrections.


I've not done anything with a PLL before but I don't envision this as 
being too complicated.  And it would be a pretty cool project. Don't 
need true "phase" lock, but rather "frequency control" without 
degrading the noise characteristics of the VCXO.


73/jeff/ac0c
alpha-charlie-zero-charlie
www.ac0c.com


On 4/3/22 7:38 PM, Lux, Jim wrote:

On 4/3/22 5:09 PM, Bob kb8tq wrote:

Hi

Does the Abricon have an EFC input? If so, rigging up a PLL to lock
122.88 to 10 MHz is probably the best option.

Bob



And what about moving off the board - so you don't have to chase the 
temperature swings.





On Apr 3, 2022, at 7:57 PM, Jeff Blaine  
wrote:


I've got a couple of Red Pitaya 122-16 SDR and want to discipline 
them to an external low noise GPSDO source. Wanted to see if there 
were some easy solutions that fell into this category.


For the prior generation (QS1R), I had built a homebrew OCXO based 
on a custom low noise crystal from ICM and that worked great for 
the 125 Mhz application.  Unfortunately this Pitaya is a bit 
removed in Fc and ICM has been out of biz for several years now.


The RP's on-board oscillator is the respectable Abracon ABLNO 
122.88 which runs about -115 dBc/hz at 100 Hz spacing and that's 
probably not a limitation for the unit. Unfortunately the OSC is a 
bit too sensitive to external temp and wanders around quite a lot 
(+/- 5 PPM) compared to the homebrew OCXO - over the annual ambient 
temp range of (10-35C) (all datasheet referenced values). The 
Abracon unit is mounted on the board with the FPGA and sees 
additional temp range depending on other heat generation factors 
(FPGA loading).


I have a couple of commercial GPSDO on the bench now, so a pretty 
clean 10 Mhz GPSDO reference is available now.  And I've seen 
enough board discussion to know that a homebrew GPSDO solution is 
one of those "it's harder than it looks" things.  Hence the desire 
just to buy whatever is the silver bullet, as long as it does not 
require too much silver.  ha ha


Appreciate any suggestions.  TKs!

73/jeff/ac0c
alpha-charlie-zero-charlie
www.ac0c.com

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--
Glen English
RF Communications and Electronics Engineer

CORTEX RF

Pacific Media Technologies Pty Ltd trading as Cortex RF

ABN 40 075 532 008

PO Box 5231 Lyneham ACT 2602, Australia.
au mobile : +61 (0)418 975077
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[time-nuts] Re: Commercial solution - 122.88 Mhz low noise source

[Jeff Blaine]

It looks like the XO version is mounted on the PCB.  But there is a VCXO 
version which would run about +/- 35 PPM/3.3V typical and that's 
(amazingly) available.


Since this EFT is not an on-board capability, at the moment, I'm 
thinking to mount the VCXO - and associated goodies to slave it to the 
10 Mhz GPSDO feed - in a separate enclosure that could allow the VCXO to 
be thermally insulated.  The temp swing vs. time will move very slowly 
and that would allow a very damped PLL loop to apply corrections.


I've not done anything with a PLL before but I don't envision this as 
being too complicated.  And it would be a pretty cool project.  Don't 
need true "phase" lock, but rather "frequency control" without degrading 
the noise characteristics of the VCXO.


73/jeff/ac0c
alpha-charlie-zero-charlie
www.ac0c.com


On 4/3/22 7:38 PM, Lux, Jim wrote:

On 4/3/22 5:09 PM, Bob kb8tq wrote:

Hi

Does the Abricon have an EFC input? If so, rigging up a PLL to lock
122.88 to 10 MHz is probably the best option.

Bob



And what about moving off the board - so you don't have to chase the 
temperature swings.





On Apr 3, 2022, at 7:57 PM, Jeff Blaine  
wrote:


I've got a couple of Red Pitaya 122-16 SDR and want to discipline 
them to an external low noise GPSDO source.  Wanted to see if there 
were some easy solutions that fell into this category.


For the prior generation (QS1R), I had built a homebrew OCXO based 
on a custom low noise crystal from ICM and that worked great for the 
125 Mhz application.  Unfortunately this Pitaya is a bit removed in 
Fc and ICM has been out of biz for several years now.


The RP's on-board oscillator is the respectable Abracon ABLNO 122.88 
which runs about -115 dBc/hz at 100 Hz spacing and that's probably 
not a limitation for the unit.  Unfortunately the OSC is a bit too 
sensitive to external temp and wanders around quite a lot (+/- 5 
PPM) compared to the homebrew OCXO - over the annual ambient temp 
range of (10-35C) (all datasheet referenced values). The Abracon 
unit is mounted on the board with the FPGA and sees additional temp 
range depending on other heat generation factors (FPGA loading).


I have a couple of commercial GPSDO on the bench now, so a pretty 
clean 10 Mhz GPSDO reference is available now.  And I've seen enough 
board discussion to know that a homebrew GPSDO solution is one of 
those "it's harder than it looks" things.  Hence the desire just to 
buy whatever is the silver bullet, as long as it does not require 
too much silver.  ha ha


Appreciate any suggestions.  TKs!

73/jeff/ac0c
alpha-charlie-zero-charlie
www.ac0c.com

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[time-nuts] Re: Commercial solution - 122.88 Mhz low noise source

[glen english LIST]

Hi Jeff

I know the device well (Red pittaya 122-16. Great ADC) . Have you 
thought of tweaking the supply volts to the on board oscillator (which 
isnt too bad at all) to shift it ? that sometimes works.


Crystek have a 122.88 MHz CVHD-950 series VCXO which you can disclipine 
and it is VERY good. The only twist is that its about 20ppm/volt and 
that is alot of variation so you need to take care with noise injection.


I've changed my  new SDR designs to using a ADF4356 in integer mode,  
and a dielectric resonator (393 MHz) on the output to kill wideband 
spurs. I'd suggest running the '4356 at 122.88 (I'm using the common and 
some sort of resonator on the output to kill wideband spurs if they are 
a problem for you.


I've been using a common footprint Connor Win D75A part with that 
familiar footprint.  but you really want a 16.384 or 12.288 / 24.576 to 
run integerer.  Taiten TSEAALJANF-16.384000   which is easy to 
discipline, worth a look also.


VK1XX

On 4/04/2022 9:57 am, Jeff Blaine wrote:
I've got a couple of Red Pitaya 122-16 SDR and want to discipline them 
to an external low noise GPSDO source.  Wanted to see if there were 
some easy solutions that fell into this category.


For the prior generation (QS1R), I had built a homebrew OCXO based on 
a custom low noise crystal from ICM and that worked great for the 125 
Mhz application.  Unfortunately this Pitaya is a bit removed in Fc and 
ICM has been out of biz for several years now.


The RP's on-board oscillator is the respectable Abracon ABLNO 122.88 
which runs about -115 dBc/hz at 100 Hz spacing and that's probably not 
a limitation for the unit.  Unfortunately the OSC is a bit too 
sensitive to external temp and wanders around quite a lot (+/- 5 PPM) 
compared to the homebrew OCXO - over the annual ambient temp range of 
(10-35C) (all datasheet referenced values). The Abracon unit is 
mounted on the board with the FPGA and sees additional temp range 
depending on other heat generation factors (FPGA loading).


I have a couple of commercial GPSDO on the bench now, so a pretty 
clean 10 Mhz GPSDO reference is available now.  And I've seen enough 
board discussion to know that a homebrew GPSDO solution is one of 
those "it's harder than it looks" things.  Hence the desire just to 
buy whatever is the silver bullet, as long as it does not require too 
much silver.  ha ha


Appreciate any suggestions.  TKs!

73/jeff/ac0c
alpha-charlie-zero-charlie
www.ac0c.com

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--
Glen English
RF Communications and Electronics Engineer

CORTEX RF

Pacific Media Technologies Pty Ltd trading as Cortex RF

ABN 40 075 532 008

PO Box 5231 Lyneham ACT 2602, Australia.
au mobile : +61 (0)418 975077
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[time-nuts] Re: Commercial solution - 122.88 Mhz low noise source

[Lux, Jim]

On 4/3/22 5:09 PM, Bob kb8tq wrote:

Hi

Does the Abricon have an EFC input? If so, rigging up a PLL to lock
122.88 to 10 MHz is probably the best option.

Bob



And what about moving off the board - so you don't have to chase the 
temperature swings.






On Apr 3, 2022, at 7:57 PM, Jeff Blaine  wrote:

I've got a couple of Red Pitaya 122-16 SDR and want to discipline them to an 
external low noise GPSDO source.  Wanted to see if there were some easy 
solutions that fell into this category.

For the prior generation (QS1R), I had built a homebrew OCXO based on a custom 
low noise crystal from ICM and that worked great for the 125 Mhz application.  
Unfortunately this Pitaya is a bit removed in Fc and ICM has been out of biz 
for several years now.

The RP's on-board oscillator is the respectable Abracon ABLNO 122.88 which runs 
about -115 dBc/hz at 100 Hz spacing and that's probably not a limitation for 
the unit.  Unfortunately the OSC is a bit too sensitive to external temp and 
wanders around quite a lot (+/- 5 PPM) compared to the homebrew OCXO - over the 
annual ambient temp range of (10-35C) (all datasheet referenced values). The 
Abracon unit is mounted on the board with the FPGA and sees additional temp 
range depending on other heat generation factors (FPGA loading).

I have a couple of commercial GPSDO on the bench now, so a pretty clean 10 Mhz GPSDO 
reference is available now.  And I've seen enough board discussion to know that a 
homebrew GPSDO solution is one of those "it's harder than it looks" things.  
Hence the desire just to buy whatever is the silver bullet, as long as it does not 
require too much silver.  ha ha

Appreciate any suggestions.  TKs!

73/jeff/ac0c
alpha-charlie-zero-charlie
www.ac0c.com

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[time-nuts] Re: Commercial solution - 122.88 Mhz low noise source

[Bob kb8tq]

Hi

Does the Abricon have an EFC input? If so, rigging up a PLL to lock 
122.88 to 10 MHz is probably the best option.

Bob

> On Apr 3, 2022, at 7:57 PM, Jeff Blaine  wrote:
> 
> I've got a couple of Red Pitaya 122-16 SDR and want to discipline them to an 
> external low noise GPSDO source.  Wanted to see if there were some easy 
> solutions that fell into this category.
> 
> For the prior generation (QS1R), I had built a homebrew OCXO based on a 
> custom low noise crystal from ICM and that worked great for the 125 Mhz 
> application.  Unfortunately this Pitaya is a bit removed in Fc and ICM has 
> been out of biz for several years now.
> 
> The RP's on-board oscillator is the respectable Abracon ABLNO 122.88 which 
> runs about -115 dBc/hz at 100 Hz spacing and that's probably not a limitation 
> for the unit.  Unfortunately the OSC is a bit too sensitive to external temp 
> and wanders around quite a lot (+/- 5 PPM) compared to the homebrew OCXO - 
> over the annual ambient temp range of (10-35C) (all datasheet referenced 
> values). The Abracon unit is mounted on the board with the FPGA and sees 
> additional temp range depending on other heat generation factors (FPGA 
> loading).
> 
> I have a couple of commercial GPSDO on the bench now, so a pretty clean 10 
> Mhz GPSDO reference is available now.  And I've seen enough board discussion 
> to know that a homebrew GPSDO solution is one of those "it's harder than it 
> looks" things.  Hence the desire just to buy whatever is the silver bullet, 
> as long as it does not require too much silver.  ha ha
> 
> Appreciate any suggestions.  TKs!
> 
> 73/jeff/ac0c
> alpha-charlie-zero-charlie
> www.ac0c.com
> 
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