Re: [U-Boot] [PATCH 13/14] mkimage: Don't close the file if it wasn't opened

[Tom Rini]

On Wed, Mar 16, 2016 at 07:45:43AM -0600, Simon Glass wrote:

> The error path for fit_import_data() is incorrect if the second open() call
> fails.
> 
> Reported-by: Coverity (CID: 138489)
> Signed-off-by: Simon Glass 

Reviewed-by: Tom Rini 

-- 
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[U-Boot] [PATCH v2] mx6sabresd: Use VESA 1024x768 timings

[Fabio Estevam]

VESA 1024x768 results in much more accurate timings.

Based on the patch from Soeren Moch for the tbs2910 board.

Signed-off-by: Fabio Estevam 
---
Changes since v1:
- Fix Soeren's name

 board/freescale/mx6sabresd/mx6sabresd.c | 28 ++--
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c 
b/board/freescale/mx6sabresd/mx6sabresd.c
index e9d9664..727334a 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -386,13 +386,13 @@ struct display_info_t const displays[] = {{
.refresh= 60,
.xres   = 1024,
.yres   = 768,
-   .pixclock   = 15385,
-   .left_margin= 220,
-   .right_margin   = 40,
-   .upper_margin   = 21,
-   .lower_margin   = 7,
-   .hsync_len  = 60,
-   .vsync_len  = 10,
+   .pixclock   = 15384,
+   .left_margin= 160,
+   .right_margin   = 24,
+   .upper_margin   = 29,
+   .lower_margin   = 3,
+   .hsync_len  = 136,
+   .vsync_len  = 6,
.sync   = FB_SYNC_EXT,
.vmode  = FB_VMODE_NONINTERLACED
 } }, {
@@ -406,13 +406,13 @@ struct display_info_t const displays[] = {{
.refresh= 60,
.xres   = 1024,
.yres   = 768,
-   .pixclock   = 15385,
-   .left_margin= 220,
-   .right_margin   = 40,
-   .upper_margin   = 21,
-   .lower_margin   = 7,
-   .hsync_len  = 60,
-   .vsync_len  = 10,
+   .pixclock   = 15384,
+   .left_margin= 160,
+   .right_margin   = 24,
+   .upper_margin   = 29,
+   .lower_margin   = 3,
+   .hsync_len  = 136,
+   .vsync_len  = 6,
.sync   = FB_SYNC_EXT,
.vmode  = FB_VMODE_NONINTERLACED
 } }, {
-- 
1.9.1

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Re: [U-Boot] [PATCH 6/7] ARM: OMAP5/DRA7: Expose do_set_iodelay

[Tom Rini]

On Tue, Mar 15, 2016 at 06:09:16PM -0500, Nishanth Menon wrote:

> do_set_iodelay can now be used from board files based on needs of the
> platforms variation they have.
> 
> Signed-off-by: Nishanth Menon 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] [U-Boot, 09/10] keystone2: env: add env script for booting with an initramfs with firmware

[Tom Rini]

On Wed, Mar 09, 2016 at 03:39:38PM +0530, Lokesh Vutla wrote:

> From: Murali Karicheri 
> 
> This patch updates the env script to include a initramfs with firmware
> loaded and provided to kernel through second argument of bootz command
> during boot. Defined DEFAULT_FW_INITRAMFS_BOOT_ENV to have all of the
> required env variables and use it in evm specific config file.
> 
> The K2 linux drivers for PCIe and NetCP (1G, 10G) requires serdes
> firmwares. These requires firmware to be available early through the boot
> process in some cases to satisfy firmware requests from driver. Hence use
> a small initramfs to provide the same and update boot env to accommodate
> this in the boot flow. This method is used when rootfs is nfs and ubifs.
> This fs contains just lib/firmware folder with all required firmware.
> 
> When rootfs is on initramfs, then the filesystem has the firmware under
> lib/firmware and this early initramfs is not required and is not used.
> 
> Signed-off-by: Murali Karicheri 
> Signed-off-by: Lokesh Vutla 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [PATCH v8 1/9] mips: add base support for QCA/Atheros ath79 SOCs

[Marek Vasut]

On 03/17/2016 01:35 PM, Wills Wang wrote:
> 
> 
> On Thursday, March 17, 2016 08:20 PM, Marek Vasut wrote:
>> On 03/17/2016 05:02 AM, Wills Wang wrote:
>>>
>>> On Thursday, March 17, 2016 11:44 AM, Marek Vasut wrote:
 On 03/17/2016 04:39 AM, Wills Wang wrote:
> On Thursday, March 17, 2016 05:35 AM, Marek Vasut wrote:
>> On 03/16/2016 09:59 AM, Wills Wang wrote:
>>> This patch add some common code for QCA/Atheros ath79 SOCs such as
>>> DDR tuning, chip reset and CPU detection.
>>>
>>> Signed-off-by: Wills Wang 
>>> ---
>>>
>>> Changes in v8:
>>> - Use setbits_be32
>>> - Use lookup-table instead of big switch statement for CPU detection
>>>
>> Good stuff, minor nits below.
 [...]

>>> +phys_size_t initdram(int board_type)
>>> +{
>>> +ddr_tap_tuning();
>> Is the DDR tap tuning needed on all AR7xxx/AR9xxx systems ?
> Yes, it's for optimizing DDR timing according to hardware.
> Sometimes, the hard code value is not ideal.
 AR934x doesn't seem to need this.
>>> I seem the following code in u-boot from Atheros LSDK:
>>> #ifdef CONFIG_AP123
>>>  ath_ddr_tap_cal();
>> Where can I get the LSDK ? I'd like to take a look and add it into my
>> ar934x support patch.
> You can refer to u-boot from Atheros QSDK
> https://us.codeaurora.org/cgit/quic/qsdk/oss/boot/u-boot-1.1.4/
> It's almost same as u-boot from Atheros LSDK.
> The above snippet can be found in
> https://us.codeaurora.org/cgit/quic/qsdk/oss/boot/u-boot-1.1.4/tree/board/ar7240/ap123/ap123.c?h=1.1

Thank you!

>>> +return get_ram_size((void *)KSEG1, SZ_256M);
>>> +}
>>> diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
>>> b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
>>> new file mode 100644
>>> index 000..893dedc
>>> --- /dev/null
>>> +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
>>> @@ -0,0 +1,1184 @@
>>> +/*
>>> + * Atheros AR71XX/AR724X/AR913X SoC register definitions
>>> + *
>>> + * Copyright (C) 2015-2016 Wills Wang 
>>> + * Copyright (C) 2010-2011 Jaiganesh Narayanan
>>> 
>>> + * Copyright (C) 2008-2010 Gabor Juhos 
>>> + * Copyright (C) 2008 Imre Kaloz 
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0+
>>> + */
>>> +
>>> +#ifndef __ASM_MACH_AR71XX_REGS_H
>>> +#define __ASM_MACH_AR71XX_REGS_H
>>> +
>>> +#ifndef __ASSEMBLY__
>>> +#include 
>>> +#else
>>> +#ifndef BIT
>>> +#define BIT(nr) (1 << (nr))
>> This should really go into some common header.
> This header is also included by some assembly code,
> but the BIT macro in linux/bitops.h isn't compatiable with assembler.
 Because of the 1UL in it ?
>>> Yes, there are also a few other C keywords and syntax, such as in-line
>>> function.
>> Hm, it pains me to see such duplication, but I have no better idea
>> how to deal with it without introducing ifdefs.
>>
> 


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Re: [U-Boot] [U-Boot, 13/27] omap-common: clocks-common: Setup USB DPLL when MUSB is in use

[Tom Rini]

On Sat, Feb 27, 2016 at 07:19:01PM +0100, Paul Kocialkowski wrote:

> On (at least) OMAP4, the USB DPLL is required to be setup for the internal PHY
> to work properly. The internal PHY is used by default with the MUSB USB OTG
> controller.
> 
> Signed-off-by: Paul Kocialkowski 

Applied to u-boot/master, thanks!

-- 
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[U-Boot] [PATCH] sun7i: Add support for the Itead Core EVB

[codekipper]

From: Marcus Cooper 

---
 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/sun7i-a20-itead-core-evb.dts | 316 ++
 configs/Itead_Core_EVB_defconfig  |  22 +++
 3 files changed, 339 insertions(+)
 create mode 100644 arch/arm/dts/sun7i-a20-itead-core-evb.dts
 create mode 100644 configs/Itead_Core_EVB_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b574284..dae2bfc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -162,6 +162,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-cubietruck.dtb \
sun7i-a20-hummingbird.dtb \
sun7i-a20-i12-tvbox.dtb \
+   sun7i-a20-itead-core-evb.dtb \
sun7i-a20-lamobo-r1.dtb \
sun7i-a20-m3.dtb \
sun7i-a20-m5.dtb \
diff --git a/arch/arm/dts/sun7i-a20-itead-core-evb.dts 
b/arch/arm/dts/sun7i-a20-itead-core-evb.dts
new file mode 100644
index 000..140f0dd
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-itead-core-evb.dts
@@ -0,0 +1,316 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include 
+#include 
+#include 
+
+/ {
+   model = "Itead Core EVB";
+   compatible = "itead,core-evb", "allwinner,sun7i-a20";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_itead_core_evb>;
+
+   blue {
+   label = "itead_core_evb:blue:usr";
+   gpios = < 7 21 GPIO_ACTIVE_HIGH>;
+   };
+
+   orange {
+   label = "itead_core_evb:orange:usr";
+   gpios = < 7 20 GPIO_ACTIVE_HIGH>;
+   };
+
+   white {
+   label = "itead_core_evb:white:usr";
+   gpios = < 7 11 GPIO_ACTIVE_HIGH>;
+   };
+
+   green {
+   label = "itead_core_evb:green:usr";
+   gpios = < 7 7 GPIO_ACTIVE_HIGH>;
+   };
+   };
+
+   mmc3_pwrseq: mmc3_pwrseq {
+   compatible = "mmc-pwrseq-simple";
+   pinctrl-names = "default";
+   pinctrl-0 = <_pwrseq_pin_itead_core_evb>;
+   reset-gpios = < 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */
+   };
+};
+
+ {
+   target-supply = <_ahci_5v>;
+   status = "okay";
+};
+
+ {
+   cpu-supply = <_dcdc2>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_rgmii_a>;
+   phy = <>;
+   phy-mode = "rgmii";
+   status = "okay";
+
+   phy1: ethernet-phy@1 {
+   reg = <1>;
+   };
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+   status = "okay";
+
+   axp209: pmic@34 {
+

Re: [U-Boot] [PATCH] arm: socfpga: Enable DM_I2C

[Marek Vasut]

On 03/18/2016 01:16 PM, Stefan Roese wrote:
> On 18.03.2016 12:20, Marek Vasut wrote:
>> On 03/18/2016 08:55 AM, Stefan Roese wrote:
>>> The designware I2C driver now supports DM. So lets use it and enable
>>> DM_I2C for this platform per default.
>>>
>>> Signed-off-by: Stefan Roese 
>>> Cc: Marek Vasut 
>>> ---
>>>   arch/arm/Kconfig |  1 +
>>>   arch/arm/dts/socfpga.dtsi|  4 
>>>   include/configs/socfpga_common.h | 16 
>>>   3 files changed, 5 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>>> index e5f57ef..98c1f10 100644
>>> --- a/arch/arm/Kconfig
>>> +++ b/arch/arm/Kconfig
>>> @@ -516,6 +516,7 @@ config ARCH_SOCFPGA
>>>   select DM
>>>   select DM_SPI_FLASH
>>>   select DM_SPI
>>> +select DM_I2C
>>>
>>>   config TARGET_CM_T43
>>>   bool "Support cm_t43"
>>> diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
>>> index 8588221..fe55722 100644
>>> --- a/arch/arm/dts/socfpga.dtsi
>>> +++ b/arch/arm/dts/socfpga.dtsi
>>> @@ -23,6 +23,10 @@
>>>   spi0 = 
>>>   spi1 = 
>>>   spi2 = 
>>> +i2c0 = 
>>> +i2c1 = 
>>> +i2c2 = 
>>> +i2c3 = 
>>
>> Something tells me that you should be super-careful here, because some
>> socfpga boards actually do use i2c. But just adding the aliases here
>> without actually enabling the i2c via DT now will cause breakage.
> 
> Right. But if the boards are also used in Linux and the dts is synced
> with the Linux one, then the I2C DT node should be enabled, right?

In theory, yes. I hope practice is in-line with theory here.

>> One way to solve it is to enable all four buses in socfpga-cyclone5.dtsi
>> but that's not something I find very appealing.
> 
> I don't like it. In the Linux socpfga.dtsi the I2C DT nodes are also
> disabled per default. We should stay in sync here.

I agree with this.

>> The other is to keep the
>> patch this way and wait until someone complains his i2c is not working.
>>
>> What do you think ?
> 
> Or we could move the aliases into the board specific dts files? I
> could start with the SR1500 board.
> 
> What do you think?

The aliases are fine. It's the "status = "okay"" bit which I suspect
might be missing for some boards. But then, let's see if something
breaks, we should be able to find it before 2016.05 is out anyway.

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Re: [U-Boot] [PATCH v8 1/9] mips: add base support for QCA/Atheros ath79 SOCs

[Wills Wang]

On Thursday, March 17, 2016 11:44 AM, Marek Vasut wrote:

On 03/17/2016 04:39 AM, Wills Wang wrote:


On Thursday, March 17, 2016 05:35 AM, Marek Vasut wrote:

On 03/16/2016 09:59 AM, Wills Wang wrote:

This patch add some common code for QCA/Atheros ath79 SOCs such as
DDR tuning, chip reset and CPU detection.

Signed-off-by: Wills Wang 
---

Changes in v8:
- Use setbits_be32
- Use lookup-table instead of big switch statement for CPU detection


Good stuff, minor nits below.

[...]


+phys_size_t initdram(int board_type)
+{
+ddr_tap_tuning();

Is the DDR tap tuning needed on all AR7xxx/AR9xxx systems ?

Yes, it's for optimizing DDR timing according to hardware.
Sometimes, the hard code value is not ideal.

AR934x doesn't seem to need this.

I seem the following code in u-boot from Atheros LSDK:
#ifdef CONFIG_AP123
ath_ddr_tap_cal();


+return get_ram_size((void *)KSEG1, SZ_256M);
+}
diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
new file mode 100644
index 000..893dedc
--- /dev/null
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -0,0 +1,1184 @@
+/*
+ * Atheros AR71XX/AR724X/AR913X SoC register definitions
+ *
+ * Copyright (C) 2015-2016 Wills Wang 
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan 
+ * Copyright (C) 2008-2010 Gabor Juhos 
+ * Copyright (C) 2008 Imre Kaloz 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_AR71XX_REGS_H
+#define __ASM_MACH_AR71XX_REGS_H
+
+#ifndef __ASSEMBLY__
+#include 
+#else
+#ifndef BIT
+#define BIT(nr) (1 << (nr))

This should really go into some common header.

This header is also included by some assembly code,
but the BIT macro in linux/bitops.h isn't compatiable with assembler.

Because of the 1UL in it ?
Yes, there are also a few other C keywords and syntax, such as in-line 
function.


[...]



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[U-Boot] [PATCH] sunxi: Enable realtek phy support

[Hans de Goede]

Enable building of drivers/net/phy/realtek.c so that realtek phys
get properly initialized.

Signed-off-by: Hans de Goede 
---
 include/configs/sunxi-common.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 40850e5..7244c5a 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -314,6 +314,7 @@ extern int soft_i2c_gpio_scl;
 #define CONFIG_PHY_GIGE/* GMAC can use gigabit PHY 
*/
 #define CONFIG_PHY_ADDR1
 #define CONFIG_MII /* MII PHY management   */
+#define CONFIG_PHY_REALTEK
 #endif
 
 #ifdef CONFIG_USB_EHCI_HCD
-- 
2.7.2

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Re: [U-Boot] [PATCH 3/6] i2c: designware_i2c: Integrate set_speed() into dw_i2c_set_bus_speed()

[Marek Vasut]

On 03/18/2016 08:54 AM, Stefan Roese wrote:
> Integrating set_speed() into dw_i2c_set_bus_speed() will make the
> conversion to DM easier for this driver.
> 
> Signed-off-by: Stefan Roese 
> Cc: Simon Glass 
> Cc: Bin Meng 
> Cc: Marek Vasut 
> Cc: Heiko Schocher 

Acked-by: Marek Vasut 

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Re: [U-Boot] [PATCH v2] spl_mmc: allow to load raw image

[Tom Rini]

On Wed, Mar 16, 2016 at 12:10:00PM +0900, Masahiro Yamada wrote:

> The function spl_parse_image_header() falls back to a raw image
> if the U-Boot header is missing and CONFIG_SPL_PANIC_ON_RAW_IMAGE
> is undefined.  While, mmc_load_image_raw_sector() only accepts a
> U-Boot legacy image or an FIT image, preventing us from loading a
> raw image.
> 
> Signed-off-by: Masahiro Yamada 

Reviewed-by: Tom Rini 

-- 
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[U-Boot] [PATCH v2 2/2] mmc: Print send_cmd response only when return value is zero

[Bin Meng]

send_cmd response is valid only when no error happened. If an error
occured, let mmc_send_cmd() print the return value to aid debugging.

Signed-off-by: Bin Meng 

---

Changes in v2:
- change commit subject: it should be 'return value is zero'

 drivers/mmc/mmc.c | 80 +--
 1 file changed, 42 insertions(+), 38 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index a7f9843..d3c22ab 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -61,46 +61,50 @@ int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 
struct mmc_data *data)
printf("CMD_SEND:%d\n", cmd->cmdidx);
printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
-   switch (cmd->resp_type) {
-   case MMC_RSP_NONE:
-   printf("\t\tMMC_RSP_NONE\n");
-   break;
-   case MMC_RSP_R1:
-   printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
-   cmd->response[0]);
-   break;
-   case MMC_RSP_R1b:
-   printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
-   cmd->response[0]);
-   break;
-   case MMC_RSP_R2:
-   printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
-   cmd->response[0]);
-   printf("\t\t  \t\t 0x%08X \n",
-   cmd->response[1]);
-   printf("\t\t  \t\t 0x%08X \n",
-   cmd->response[2]);
-   printf("\t\t  \t\t 0x%08X \n",
-   cmd->response[3]);
-   printf("\n");
-   printf("\t\t\t\t\tDUMPING DATA\n");
-   for (i = 0; i < 4; i++) {
-   int j;
-   printf("\t\t\t\t\t%03d - ", i*4);
-   ptr = (u8 *)>response[i];
-   ptr += 3;
-   for (j = 0; j < 4; j++)
-   printf("%02X ", *ptr--);
+   if (ret) {
+   printf("\t\tRET\t\t\t %d\n", ret);
+   } else {
+   switch (cmd->resp_type) {
+   case MMC_RSP_NONE:
+   printf("\t\tMMC_RSP_NONE\n");
+   break;
+   case MMC_RSP_R1:
+   printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
+   cmd->response[0]);
+   break;
+   case MMC_RSP_R1b:
+   printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
+   cmd->response[0]);
+   break;
+   case MMC_RSP_R2:
+   printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
+   cmd->response[0]);
+   printf("\t\t  \t\t 0x%08X \n",
+   cmd->response[1]);
+   printf("\t\t  \t\t 0x%08X \n",
+   cmd->response[2]);
+   printf("\t\t  \t\t 0x%08X \n",
+   cmd->response[3]);
printf("\n");
+   printf("\t\t\t\t\tDUMPING DATA\n");
+   for (i = 0; i < 4; i++) {
+   int j;
+   printf("\t\t\t\t\t%03d - ", i*4);
+   ptr = (u8 *)>response[i];
+   ptr += 3;
+   for (j = 0; j < 4; j++)
+   printf("%02X ", *ptr--);
+   printf("\n");
+   }
+   break;
+   case MMC_RSP_R3:
+   printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
+   cmd->response[0]);
+   break;
+   default:
+   printf("\t\tERROR MMC rsp not supported\n");
+   break;
}
-   break;
-   case MMC_RSP_R3:
-   printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
-   cmd->response[0]);
-   break;
-   default:
-   printf("\t\tERROR MMC rsp not supported\n");
-   break;
}
 #else
ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
-- 
1.8.2.1

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[U-Boot] [PATCH] image-fit: Change FIT prefix for configurations

[Sáreník Ján]

Instead of `bootm ${loadaddr}#conf@1`
one uses   `bootm ${loadaddr}_conf@1`

This fixes the bug with using just `bootm #conf@2`
without $loadaddr where text starting with # is
interpreted as a comment.
---
 cmd/bootm.c  | 2 +-
 common/image-fit.c   | 2 +-
 doc/uImage.FIT/command_syntax_extensions.txt | 2 +-
 include/configs/baltos.h | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/cmd/bootm.c b/cmd/bootm.c
index 555ccbc..23740c5 100644
--- a/cmd/bootm.c
+++ b/cmd/bootm.c
@@ -124,7 +124,7 @@ int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
  *
  * Right now we assume the first arg should never be '-'
  */
-if ((*endp != 0) && (*endp != ':') && (*endp != '#'))
+if ((*endp != 0) && (*endp != ':') && (*endp != '_'))
 return do_bootm_subcommand(cmdtp, flag, argc, argv);
 }

diff --git a/common/image-fit.c b/common/image-fit.c
index 25f8a11..e23796f 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -75,7 +75,7 @@ static int fit_parse_spec(const char *spec, char sepc, ulong 
addr_curr,
 int fit_parse_conf(const char *spec, ulong addr_curr,
 ulong *addr, const char **conf_name)
 {
-return fit_parse_spec(spec, '#', addr_curr, addr, conf_name);
+return fit_parse_spec(spec, '_', addr_curr, addr, conf_name);
 }

 /**
diff --git a/doc/uImage.FIT/command_syntax_extensions.txt 
b/doc/uImage.FIT/command_syntax_extensions.txt
index 6c99b1c..ef4db80 100644
--- a/doc/uImage.FIT/command_syntax_extensions.txt
+++ b/doc/uImage.FIT/command_syntax_extensions.txt
@@ -36,7 +36,7 @@ Old uImage:
 New uImage:
 8.  bootm 
 9.  bootm []:
-10. bootm []#
+10. bootm []_
 11. bootm []: []:
 12. bootm []: []: []:
 13. bootm []: []: 
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index b8c915c..8a01fe8 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -80,7 +80,7 @@
 "ubifsmount ubi0:kernel; " \
 "ubifsload $loadaddr kernel-fit.itb;" \
 "ubifsumount; " \
-"bootm ${loadaddr}#conf${board_name}; " \
+"bootm ${loadaddr}_conf${board_name}; " \
 "if test $? -ne 0; then echo Using default FIT config; " \
 "bootm ${loadaddr}; fi;\0"
 #else
--
2.7.3



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Re: [U-Boot] [PATCH v4 01/14] armv8: ls2080: Add SFP Configs for LS2080/LS2085

[york sun]

On 02/08/2016 09:26 PM, Saksham Jain wrote:
> In LS2080/LS2085, SFP is LE and Ver is 3.4

Please spell out little endian and version. Use proper period sign at the end of
sentence.

> The base address is 0x01e80200

Same here.

York

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Re: [U-Boot] [PATCH v4 2/4] drivers: remove writes{b, w, l, q} and reads{b, w, l, q}.

[Scott Wood]

On 03/18/2016 08:52 AM, Purna Chandra Mandal wrote:
> Definition of writes{bwlq}, reads{bwlq} are now added into arch specific
> asm/io.h. So removing them from drivers to fix re-definition error
> 
> Signed-off-by: Purna Chandra Mandal 
> ---
> 
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> 
>  drivers/mtd/nand/pxa3xx_nand.c  | 8 
>  drivers/usb/musb-new/linux-compat.h | 7 ---
>  2 files changed, 15 deletions(-)

Acked-by: Scott Wood 

-Scott

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[U-Boot] [PATCH 12/13] ARM: uniphier: add System Control register macros for ARMv8 SoCs

[Masahiro Yamada]

The System Control block moved to a completely different register
map for ARMv8 SoCs, so it cannot be shared with the ARM 32-bit ones.
Define register macros in a new header file.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/sc64-regs.h | 44 ++
 1 file changed, 44 insertions(+)
 create mode 100644 arch/arm/mach-uniphier/sc64-regs.h

diff --git a/arch/arm/mach-uniphier/sc64-regs.h 
b/arch/arm/mach-uniphier/sc64-regs.h
new file mode 100644
index 000..ef02830
--- /dev/null
+++ b/arch/arm/mach-uniphier/sc64-regs.h
@@ -0,0 +1,44 @@
+/*
+ * UniPhier SC (System Control) block registers for ARMv8 SoCs
+ *
+ * Copyright (C) 2016 Masahiro Yamada 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef SC64_REGS_H
+#define SC64_REGS_H
+
+#define SC_BASE_ADDR   0x6184
+
+#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
+#define SC_RSTCTRL3(SC_BASE_ADDR | 0x2008)
+#define SC_RSTCTRL4(SC_BASE_ADDR | 0x200c)
+#define   SC_RSTCTRL4_ETHER(1 << 6)
+#define   SC_RSTCTRL4_NAND (1 << 0)
+#define SC_RSTCTRL5(SC_BASE_ADDR | 0x2010)
+#define SC_RSTCTRL6(SC_BASE_ADDR | 0x2014)
+#define SC_RSTCTRL7(SC_BASE_ADDR | 0x2018)
+#define   SC_RSTCTRL7_UMCSB(1 << 16)
+#define   SC_RSTCTRL7_UMCA2(1 << 10)
+#define   SC_RSTCTRL7_UMCA1(1 << 9)
+#define   SC_RSTCTRL7_UMCA0(1 << 8)
+#define   SC_RSTCTRL7_UMC32(1 << 2)
+#define   SC_RSTCTRL7_UMC31(1 << 1)
+#define   SC_RSTCTRL7_UMC30(1 << 0)
+
+#define SC_CLKCTRL (SC_BASE_ADDR | 0x2100)
+#define SC_CLKCTRL3(SC_BASE_ADDR | 0x2108)
+#define SC_CLKCTRL4(SC_BASE_ADDR | 0x210c)
+#define   SC_CLKCTRL4_PERI (1 << 7)
+#define   SC_CLKCTRL4_ETHER(1 << 6)
+#define   SC_CLKCTRL4_NAND (1 << 0)
+#define SC_CLKCTRL5(SC_BASE_ADDR | 0x2110)
+#define SC_CLKCTRL6(SC_BASE_ADDR | 0x2114)
+#define SC_CLKCTRL7(SC_BASE_ADDR | 0x2118)
+#define   SC_CLKCTRL7_UMCSB(1 << 16)
+#define   SC_CLKCTRL7_UMC32(1 << 2)
+#define   SC_CLKCTRL7_UMC31(1 << 1)
+#define   SC_CLKCTRL7_UMC30(1 << 0)
+
+#endif /* SC64_REGS_H */
-- 
1.9.1

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Re: [U-Boot] [PATCH] arm: socfpga: Enable DM_I2C

[Stefan Roese]

On 18.03.2016 12:20, Marek Vasut wrote:

On 03/18/2016 08:55 AM, Stefan Roese wrote:

The designware I2C driver now supports DM. So lets use it and enable
DM_I2C for this platform per default.

Signed-off-by: Stefan Roese 
Cc: Marek Vasut 
---
  arch/arm/Kconfig |  1 +
  arch/arm/dts/socfpga.dtsi|  4 
  include/configs/socfpga_common.h | 16 
  3 files changed, 5 insertions(+), 16 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e5f57ef..98c1f10 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -516,6 +516,7 @@ config ARCH_SOCFPGA
select DM
select DM_SPI_FLASH
select DM_SPI
+   select DM_I2C

  config TARGET_CM_T43
bool "Support cm_t43"
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 8588221..fe55722 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -23,6 +23,10 @@
spi0 = 
spi1 = 
spi2 = 
+   i2c0 = 
+   i2c1 = 
+   i2c2 = 
+   i2c3 = 


Something tells me that you should be super-careful here, because some
socfpga boards actually do use i2c. But just adding the aliases here
without actually enabling the i2c via DT now will cause breakage.


Right. But if the boards are also used in Linux and the dts is synced
with the Linux one, then the I2C DT node should be enabled, right?


One way to solve it is to enable all four buses in socfpga-cyclone5.dtsi
but that's not something I find very appealing.


I don't like it. In the Linux socpfga.dtsi the I2C DT nodes are also
disabled per default. We should stay in sync here.


The other is to keep the
patch this way and wait until someone complains his i2c is not working.

What do you think ?


Or we could move the aliases into the board specific dts files? I
could start with the SR1500 board.

What do you think?

Thanks,
Stefan
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Re: [U-Boot] [PATCH 1/7] ARM: DRA72x: Add support for detection of SR2.0

[Tom Rini]

On Tue, Mar 15, 2016 at 06:09:11PM -0500, Nishanth Menon wrote:

> From: Ravi Babu 
> 
> Add support for detection of SR2.0 version of DRA72x family of
> processors.
> 
> Signed-off-by: Ravi Babu 
> Signed-off-by: Nishanth Menon 

Reviewed-by: Tom Rini 

-- 
Tom


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Re: [U-Boot] [PATCH v3 3/4] drivers: musb-new: Add USB DRC driver for Microchip PIC32 OTG controller.

[Purna Chandra Mandal]

On 03/16/2016 09:18 PM, Marek Vasut wrote:

> On 03/16/2016 10:58 AM, Purna Chandra Mandal wrote:
>> On 03/15/2016 11:49 PM, Marek Vasut wrote:
>>
>>> On 03/15/2016 01:44 PM, Purna Chandra Mandal wrote:
 This driver adds support of PIC32 MUSB OTG controller as dual role device.
 It implements platform specific glue to reuse musb core.

 Signed-off-by: Cristian Birsan 
 Signed-off-by: Purna Chandra Mandal 
>>> [...]
>>>
 diff --git a/drivers/usb/musb-new/pic32.c b/drivers/usb/musb-new/pic32.c
 new file mode 100644
 index 000..980a971
 --- /dev/null
 +++ b/drivers/usb/musb-new/pic32.c
 @@ -0,0 +1,294 @@
 +/*
 + * Microchip PIC32 MUSB "glue layer"
 + *
 + * Copyright (C) 2015, Microchip Technology Inc.
 + *  Cristian Birsan 
 + *  Purna Chandra Mandal 
 + *
 + * SPDX-License-Identifier: GPL-2.0+
 + *
 + * Based on the dsps "glue layer" code.
 + */
 +
 +#include 
 +#include 
 +#include "linux-compat.h"
 +#include "musb_core.h"
 +#include "musb_uboot.h"
 +
 +DECLARE_GLOBAL_DATA_PTR;
 +
 +#define PIC32_TX_EP_MASK  0x0f/* EP0 + 7 Tx EPs */
 +#define PIC32_RX_EP_MASK  0x0e/* 7 Rx EPs */
 +
 +#define MUSB_SOFTRST  0x7f
 +#define  MUSB_SOFTRST_NRSTBIT(0)
 +#define  MUSB_SOFTRST_NRSTX   BIT(1)
 +
 +#define USBCRCON  0
 +#define  USBCRCON_USBWKUPEN   BIT(0)  /* Enable Wakeup Interrupt */
 +#define  USBCRCON_USBRIE  BIT(1)  /* Enable Remote resume Interrupt */
 +#define  USBCRCON_USBIE   BIT(2)  /* Enable USB General interrupt 
 */
 +#define  USBCRCON_SENDMONEN   BIT(3)  /* Enable Session End VBUS 
 monitoring */
 +#define  USBCRCON_BSVALMONEN  BIT(4)  /* Enable B-Device VBUS 
 monitoring */
 +#define  USBCRCON_ASVALMONEN  BIT(5)  /* Enable A-Device VBUS 
 monitoring */
 +#define  USBCRCON_VBUSMONEN   BIT(6)  /* Enable VBUS monitoring */
 +#define  USBCRCON_PHYIDEN BIT(7)  /* PHY ID monitoring enable */
 +#define  USBCRCON_USBIDVALBIT(8)  /* USB ID value */
 +#define  USBCRCON_USBIDOVEN   BIT(9)  /* USB ID override enable */
 +#define  USBCRCON_USBWK   BIT(24) /* USB Wakeup Status */
 +#define  USBCRCON_USBRF   BIT(25) /* USB Resume Status */
 +#define  USBCRCON_USBIF   BIT(26) /* USB General Interrupt Status 
 */
 +
 +static void __iomem *musb_glue;
>>> What would happen once you make a chip with two MUSB controllers ?
>> Currently PIC32 has only one MUSB controller and only one glue reg-space.
>> Don't know how the reg-map will be in future when PIC32 will have multiple
>> MUSB controllers. Assuming that glue address map will be separate for
>> each controller we can add logic to support multiple MUSB controller.
>>
>> IMO, better if we don't assume something of the future and bloat logic.
> If you switch this to driver model, you will need to weed out all the
> static global variables anyway. Better do it now.

Thanks. Will do.

 +/* pic32_musb_disable - disable HDRC */
 +static void pic32_musb_disable(struct musb *musb)
 +{
>>> Is there no way to shut down the MUSB on the PIC32 ?
>> There is no way to disable MUSB.
> Yet another broken chip design. Can't you put the controller into reset
> and gate the clock for it ?

USB clock can't be gated! USB controller clock is derived from peripheral bus
clock(PBCLK5) which is shared with other modules and USB Phy clock derived from
UPLL can;t be gated at all.

 +}
 +
 +/* pic32_musb_enable - enable HDRC */
 +static int pic32_musb_enable(struct musb *musb)
 +{
 +  /* soft reset by NRSTx */
 +  musb_writeb(musb->mregs, MUSB_SOFTRST, MUSB_SOFTRST_NRSTX);
 +  /* set mode */
 +  musb_platform_set_mode(musb, musb->board_mode);
 +
 +  return 0;
 +}
 +
 +static irqreturn_t pic32_interrupt(int irq, void *hci)
 +{
 +  struct musb  *musb = hci;
 +  irqreturn_t ret = IRQ_NONE;
 +  u32 epintr, usbintr;
 +
 +  /* Get usb core interrupts */
>>> You mean "get" or "ack" here ?
>> I meant read-and-ack. Will update comment.
> Thanks
>
 +  musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
 +  if (musb->int_usb)
 +  musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
 +
 +  /* Get endpoint interrupts */
>>> DTTO
>> I meant read-and-ack.
>>
 +  musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX) & PIC32_RX_EP_MASK;
 +  if (musb->int_rx)
 +  musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
>>> Same here
>> ack. Will update comment.
>>
 +  musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX) & PIC32_TX_EP_MASK;
 +  if (musb->int_tx)
 +  

Re: [U-Boot] mx6sabresd: Use VESA 1024x768 timings

[Fabio Estevam]

On Wed, Mar 16, 2016 at 12:52 PM, Soeren Moch  wrote:
>> VESA 1024x768 results in much more accurate timings.
>>
>> Based on the patch from Soeren Moech for the tbs2910 board.
>
> Soeren Moch

Sorry about that. Fixed in v2.
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[U-Boot] [PATCH v3 02/10] dhry: Correct dhrystone calculation for fast machines

[Simon Glass]

At present samus reports about 5600 DMIPS. With the default iteration count
this is OK, but if 10 million runs are performed it overflows. Fix it.

Signed-off-by: Simon Glass 
---

Changes in v3: None
Changes in v2: None

 lib/dhry/cmd_dhry.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/lib/dhry/cmd_dhry.c b/lib/dhry/cmd_dhry.c
index 5dc191e..d7e1e6a 100644
--- a/lib/dhry/cmd_dhry.c
+++ b/lib/dhry/cmd_dhry.c
@@ -6,11 +6,13 @@
 
 #include 
 #include 
+#include 
 #include "dhry.h"
 
 static int do_dhry(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-   ulong start, duration, dhry_per_sec, vax_mips;
+   ulong start, duration, vax_mips;
+   u64 dhry_per_sec;
int iterations = 100;
 
if (argc > 1)
@@ -19,10 +21,10 @@ static int do_dhry(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
start = get_timer(0);
dhry(iterations);
duration = get_timer(start);
-   dhry_per_sec = iterations * 1000 / duration;
+   dhry_per_sec = lldiv(iterations * 1000ULL, duration);
vax_mips = dhry_per_sec / 1757;
printf("%d iterations in %lu ms: %lu/s, %lu DMIPS\n", iterations,
-  duration, dhry_per_sec, vax_mips);
+  duration, (ulong)dhry_per_sec, vax_mips);
 
return 0;
 }
-- 
2.7.0.rc3.207.g0ac5344

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Re: [U-Boot] [PATCH v3 06/10] x86: dts: Drop memory SPD compatible string

[Bin Meng]

On Wed, Mar 16, 2016 at 9:44 PM, Simon Glass  wrote:
> This is not needed now that the memory controller driver has the SPD data
> in its own node.
>
> Signed-off-by: Simon Glass 
> Reviewed-by: Bin Meng 
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/dts/chromebook_link.dts | 1 -
>  include/fdtdec.h | 1 -
>  lib/fdtdec.c | 1 -
>  3 files changed, 3 deletions(-)
>

applied to u-boot-x86, thanks!
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[U-Boot] [PATCH 10/14] mkimage: Fix missing free() in fit_extract_data()

[Simon Glass]

The 'buf' variable is not freed. Fix it.

Reported-by: Coverity (CID: 138492)
Signed-off-by: Simon Glass 
---

 tools/fit_image.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tools/fit_image.c b/tools/fit_image.c
index bfb43b2..e628212 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -452,6 +452,8 @@ static int fit_extract_data(struct image_tool_params 
*params, const char *fname)
 err_munmap:
munmap(fdt, sbuf.st_size);
 err:
+   if (buf)
+   free(buf);
close(fd);
return ret;
 }
-- 
2.7.0.rc3.207.g0ac5344

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Re: [U-Boot] [PATCH 2/2] board: ti: am57xx: Set ethernet MAC addresses from EEPROM to env

[Tom Rini]

On Fri, Mar 18, 2016 at 01:18:12PM +0200, Roger Quadros wrote:

> The MAC addresses for the PRU Ethernet ports will be available in the
> board EEPROM as an address range. Populate those MAC addresses (if valid)
> into the u-boot environment so that they can be passed on to the
> device tree during fdt_fixup_ethernet().
> 
> Signed-off-by: Roger Quadros 

Reviewed-by: Tom Rini 

-- 
Tom


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[U-Boot] [PATCH v3 2/2] drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.

[Purna Chandra Mandal]

PIC32 internal flash devices are parallel NOR flash divided into
number of banks to allow erase-programming in one while fetch and
execution continues on other. As the flash banks are memory mapped
stored code can be executed directly from flash (XIP), also there
is additional hardware logic to prefetch and cache contents to
improve execution performance. These flash can also be used to
store user data (like environment).
Flash erase and programming are handled by on-chip NVM controller.

Driver implemented driver model but MTD is not really support.

Signed-off-by: Purna Chandra Mandal 

---

Changes in v3:
- add driver model support but MTD is not implemented

Changes in v2:
- kconfig: add CONFIG_FLASH_PIC32 dependent on MACH_PIC32
- fix single/multi-line comment style
- simplify byte-stream-to-word in little-endian format
- replace virt_to_phys() with CPHYSADDR()
- separate flash ID definition in different patch

 drivers/mtd/Kconfig   |   7 +
 drivers/mtd/Makefile  |   1 +
 drivers/mtd/pic32_flash.c | 444 ++
 3 files changed, 452 insertions(+)
 create mode 100644 drivers/mtd/pic32_flash.c

diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index c58841e..390e9e4 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -28,6 +28,13 @@ config ALTERA_QSPI
  NOR flash to parallel flash interface. Please find details on the
  "Embedded Peripherals IP User Guide" of Altera.
 
+config FLASH_PIC32
+   bool "Microchip PIC32 Flash driver"
+   depends on MACH_PIC32 && MTD
+   help
+ This enables access to Microchip PIC32 internal non-CFI flash
+ chips through PIC32 Non-Volatile-Memory Controller.
+
 endmenu
 
 source "drivers/mtd/nand/Kconfig"
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 7f018a4..9380085 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -19,4 +19,5 @@ obj-$(CONFIG_HAS_DATAFLASH) += dataflash.o
 obj-$(CONFIG_FTSMC020) += ftsmc020.o
 obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
 obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o
+obj-$(CONFIG_FLASH_PIC32) += pic32_flash.o
 obj-$(CONFIG_ST_SMI) += st_smi.o
diff --git a/drivers/mtd/pic32_flash.c b/drivers/mtd/pic32_flash.c
new file mode 100644
index 000..9166fcd
--- /dev/null
+++ b/drivers/mtd/pic32_flash.c
@@ -0,0 +1,444 @@
+/*
+ * Copyright (C) 2015
+ * Cristian Birsan 
+ * Purna Chandra Mandal 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* NVM Controller registers */
+struct pic32_reg_nvm {
+   struct pic32_reg_atomic ctrl;
+   struct pic32_reg_atomic key;
+   struct pic32_reg_atomic addr;
+   struct pic32_reg_atomic data;
+};
+
+/* NVM operations */
+#define NVMOP_NOP  0
+#define NVMOP_WORD_WRITE   1
+#define NVMOP_PAGE_ERASE   4
+
+/* NVM control bits */
+#define NVM_WR BIT(15)
+#define NVM_WREN   BIT(14)
+#define NVM_WRERR  BIT(13)
+#define NVM_LVDERR BIT(12)
+
+/* NVM programming unlock register */
+#define LOCK_KEY   0x0
+#define UNLOCK_KEY10xaa996655
+#define UNLOCK_KEY20x556699aa
+
+/*
+ * PIC32 flash banks consist of number of pages, each page
+ * into number of rows and rows into number of words.
+ * Here we will maintain page information instead of sector.
+ */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+static struct pic32_reg_nvm *nvm_regs_p;
+
+static inline void flash_initiate_operation(u32 nvmop)
+{
+   /* set operation */
+   writel(nvmop, _regs_p->ctrl.raw);
+
+   /* enable flash write */
+   writel(NVM_WREN, _regs_p->ctrl.set);
+
+   /* unlock sequence */
+   writel(LOCK_KEY, _regs_p->key.raw);
+   writel(UNLOCK_KEY1, _regs_p->key.raw);
+   writel(UNLOCK_KEY2, _regs_p->key.raw);
+
+   /* initiate operation */
+   writel(NVM_WR, _regs_p->ctrl.set);
+}
+
+static int flash_wait_till_busy(const char *func, ulong timeout)
+{
+   int ret = wait_for_bit(__func__, _regs_p->ctrl.raw,
+  NVM_WR, false, timeout, false);
+
+   return ret ? ERR_TIMOUT : ERR_OK;
+}
+
+static inline int flash_complete_operation(void)
+{
+   u32 tmp;
+
+   tmp = readl(_regs_p->ctrl.raw);
+   if (tmp & NVM_WRERR) {
+   printf("Error in Block Erase - Lock Bit may be set!\n");
+   flash_initiate_operation(NVMOP_NOP);
+   return ERR_PROTECTED;
+   }
+
+   if (tmp & NVM_LVDERR) {
+   printf("Error in Block Erase - low-vol detected!\n");
+   flash_initiate_operation(NVMOP_NOP);
+   return ERR_NOT_ERASED;
+   }
+
+   /* disable flash write or erase operation */
+   writel(NVM_WREN, _regs_p->ctrl.clr);
+
+   return ERR_OK;
+}
+
+/*
+ * 

Re: [U-Boot] [PATCH 3/3] ARM: keystone2: Convert BOOT_SET_BITFIELD into static inline function

[Tom Rini]

On Tue, Mar 15, 2016 at 10:25:53AM -0500, Nishanth Menon wrote:

> Fix up BOOT_SET_BITFIELD to be a static inline function to be readable
> with the same functionality.
> 
> Reported-by: Tom Rini 
> Signed-off-by: Nishanth Menon 

Reviewed-by: Tom Rini 

-- 
Tom


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Re: [U-Boot] [U-Boot,v5,17/30] efi_loader: Add runtime services

[Tom Rini]

On Fri, Mar 04, 2016 at 01:10:01AM +0100, Alexander Graf wrote:

> After booting has finished, EFI allows firmware to still interact with the OS
> using the "runtime services". These callbacks live in a separate address 
> space,
> since they are available long after U-Boot has been overwritten by the OS.
> 
> This patch adds enough framework for arbitrary code inside of U-Boot to become
> a runtime service with the right section attributes set. For now, we don't 
> make
> use of it yet though.
> 
> We could maybe in the future map U-boot environment variables to EFI variables
> here.
> 
> Signed-off-by: Alexander Graf 
> Reviewed-by: Simon Glass 
> Tested-by: Simon Glass 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [PATCH v8 1/9] mips: add base support for QCA/Atheros ath79 SOCs

[Marek Vasut]

On 03/17/2016 04:39 AM, Wills Wang wrote:
> 
> 
> On Thursday, March 17, 2016 05:35 AM, Marek Vasut wrote:
>> On 03/16/2016 09:59 AM, Wills Wang wrote:
>>> This patch add some common code for QCA/Atheros ath79 SOCs such as
>>> DDR tuning, chip reset and CPU detection.
>>>
>>> Signed-off-by: Wills Wang 
>>> ---
>>>
>>> Changes in v8:
>>> - Use setbits_be32
>>> - Use lookup-table instead of big switch statement for CPU detection
>>>
>> Good stuff, minor nits below.

[...]

>>> +phys_size_t initdram(int board_type)
>>> +{
>>> +ddr_tap_tuning();
>> Is the DDR tap tuning needed on all AR7xxx/AR9xxx systems ?
> Yes, it's for optimizing DDR timing according to hardware.
> Sometimes, the hard code value is not ideal.

AR934x doesn't seem to need this.

>>> +return get_ram_size((void *)KSEG1, SZ_256M);
>>> +}
>>> diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
>>> b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
>>> new file mode 100644
>>> index 000..893dedc
>>> --- /dev/null
>>> +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
>>> @@ -0,0 +1,1184 @@
>>> +/*
>>> + * Atheros AR71XX/AR724X/AR913X SoC register definitions
>>> + *
>>> + * Copyright (C) 2015-2016 Wills Wang 
>>> + * Copyright (C) 2010-2011 Jaiganesh Narayanan 
>>> + * Copyright (C) 2008-2010 Gabor Juhos 
>>> + * Copyright (C) 2008 Imre Kaloz 
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0+
>>> + */
>>> +
>>> +#ifndef __ASM_MACH_AR71XX_REGS_H
>>> +#define __ASM_MACH_AR71XX_REGS_H
>>> +
>>> +#ifndef __ASSEMBLY__
>>> +#include 
>>> +#else
>>> +#ifndef BIT
>>> +#define BIT(nr) (1 << (nr))
>> This should really go into some common header.
> This header is also included by some assembly code,
> but the BIT macro in linux/bitops.h isn't compatiable with assembler.

Because of the 1UL in it ?

[...]

-- 
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Marek Vasut
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[U-Boot] [PATCH] [v3] armv8: fsl-layerscape: Updating entries in Serdes Table

[Pratiyush Mohan Srivastava]

The serdes protocol entries in  Serdes table 1 for protocol
0x03, 0x33, 0x35 and in Serdes table 2 for protocols 0x45
and 0x47 are updated to reflect the entries in
current Reference Manual.

Signed-off-by: Pratiyush Mohan Srivastava 
Reported-by: Jose Rivera 
---
Changes for v3
Rebased to latest master Branch

 arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c 
b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
index ea3114c..eaa44a7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
@@ -14,7 +14,7 @@ struct serdes_config {
 
 static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
-   {0x03, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2 } },
+   {0x03, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
{0x05, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } },
{0x07, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
SGMII1 } },
@@ -31,9 +31,9 @@ static struct serdes_config serdes1_cfg_tbl[] = {
{0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
{0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1  } },
{0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1  } },
-   {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A,
-   QSGMII_B} },
-   {0x35, {QSGMII_C, QSGMII_D, QSGMII_A, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
+   {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B,
+   QSGMII_A} },
+   {0x35, {QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
{}
 };
 static struct serdes_config serdes2_cfg_tbl[] = {
@@ -56,10 +56,10 @@ static struct serdes_config serdes2_cfg_tbl[] = {
{0x42, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
{0x43, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
{0x44, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
-   {0x45, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15,
-   SGMII16 } },
-   {0x47, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4,
+   {0x45, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4,
PCIE4 } },
+   {0x47, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15,
+   SGMII16 } },
{0x49, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
SATA2 } },
{0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
-- 
1.9.1

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[U-Boot] [RFC PATCH 0/2] simple cache layer for block devices

[Eric Nelson]

Here's an example of a very simple cache for block devices that 
will prevent duplicate back-to-back reads from the same block
device.

By itself, this is sufficient to speed reads of certain files from
ext4 by 30x as described in this thread.

The areas I think could benefit most from some level of block cache
in U-Boot are:
- reads from partition tables
- directory searches

Having more than one cache entry is probably better for both of
those, but I'd like to get some feedback first.

The implementation explicitly prevents reads of more than
8 blocks to prevent slowing down the most speed-critical operations
(reading files) and I'm not sure this is the right choice of size.

The small size limit also prevents the overhead in the interface to
cache_block_fill() from being a problem. A more robust approach would
allow the cache to take over previously allocated blocks, but this
would also be more invasive, since some cacheable blocks are currently
allocated on the stack.

Eric Nelson (2):
  add block device cache
  mmc: add support for block device cache

 drivers/block/Makefile  |  1 +
 drivers/block/cache_block.c | 76 +
 drivers/mmc/mmc.c   | 10 +-
 drivers/mmc/mmc_write.c |  7 +
 include/part.h  | 65 ++
 5 files changed, 158 insertions(+), 1 deletion(-)
 create mode 100644 drivers/block/cache_block.c

-- 
2.6.2

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Re: [U-Boot] [PATCH v8 1/9] mips: add base support for QCA/Atheros ath79 SOCs

[Marek Vasut]

On 03/17/2016 05:02 AM, Wills Wang wrote:
> 
> 
> On Thursday, March 17, 2016 11:44 AM, Marek Vasut wrote:
>> On 03/17/2016 04:39 AM, Wills Wang wrote:
>>>
>>> On Thursday, March 17, 2016 05:35 AM, Marek Vasut wrote:
 On 03/16/2016 09:59 AM, Wills Wang wrote:
> This patch add some common code for QCA/Atheros ath79 SOCs such as
> DDR tuning, chip reset and CPU detection.
>
> Signed-off-by: Wills Wang 
> ---
>
> Changes in v8:
> - Use setbits_be32
> - Use lookup-table instead of big switch statement for CPU detection
>
 Good stuff, minor nits below.
>> [...]
>>
> +phys_size_t initdram(int board_type)
> +{
> +ddr_tap_tuning();
 Is the DDR tap tuning needed on all AR7xxx/AR9xxx systems ?
>>> Yes, it's for optimizing DDR timing according to hardware.
>>> Sometimes, the hard code value is not ideal.
>> AR934x doesn't seem to need this.
> I seem the following code in u-boot from Atheros LSDK:
> #ifdef CONFIG_AP123
> ath_ddr_tap_cal();

Where can I get the LSDK ? I'd like to take a look and add it into my
ar934x support patch.

> +return get_ram_size((void *)KSEG1, SZ_256M);
> +}
> diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
> b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
> new file mode 100644
> index 000..893dedc
> --- /dev/null
> +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
> @@ -0,0 +1,1184 @@
> +/*
> + * Atheros AR71XX/AR724X/AR913X SoC register definitions
> + *
> + * Copyright (C) 2015-2016 Wills Wang 
> + * Copyright (C) 2010-2011 Jaiganesh Narayanan
> 
> + * Copyright (C) 2008-2010 Gabor Juhos 
> + * Copyright (C) 2008 Imre Kaloz 
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __ASM_MACH_AR71XX_REGS_H
> +#define __ASM_MACH_AR71XX_REGS_H
> +
> +#ifndef __ASSEMBLY__
> +#include 
> +#else
> +#ifndef BIT
> +#define BIT(nr) (1 << (nr))
 This should really go into some common header.
>>> This header is also included by some assembly code,
>>> but the BIT macro in linux/bitops.h isn't compatiable with assembler.
>> Because of the 1UL in it ?
> Yes, there are also a few other C keywords and syntax, such as in-line
> function.

Hm, it pains me to see such duplication, but I have no better idea
how to deal with it without introducing ifdefs.

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v8 1/9] mips: add base support for QCA/Atheros ath79 SOCs

[Wills Wang]

On Thursday, March 17, 2016 08:20 PM, Marek Vasut wrote:

On 03/17/2016 05:02 AM, Wills Wang wrote:


On Thursday, March 17, 2016 11:44 AM, Marek Vasut wrote:

On 03/17/2016 04:39 AM, Wills Wang wrote:

On Thursday, March 17, 2016 05:35 AM, Marek Vasut wrote:

On 03/16/2016 09:59 AM, Wills Wang wrote:

This patch add some common code for QCA/Atheros ath79 SOCs such as
DDR tuning, chip reset and CPU detection.

Signed-off-by: Wills Wang 
---

Changes in v8:
- Use setbits_be32
- Use lookup-table instead of big switch statement for CPU detection


Good stuff, minor nits below.

[...]


+phys_size_t initdram(int board_type)
+{
+ddr_tap_tuning();

Is the DDR tap tuning needed on all AR7xxx/AR9xxx systems ?

Yes, it's for optimizing DDR timing according to hardware.
Sometimes, the hard code value is not ideal.

AR934x doesn't seem to need this.

I seem the following code in u-boot from Atheros LSDK:
#ifdef CONFIG_AP123
 ath_ddr_tap_cal();

Where can I get the LSDK ? I'd like to take a look and add it into my
ar934x support patch.

You can refer to u-boot from Atheros QSDK
https://us.codeaurora.org/cgit/quic/qsdk/oss/boot/u-boot-1.1.4/
It's almost same as u-boot from Atheros LSDK.
The above snippet can be found in
https://us.codeaurora.org/cgit/quic/qsdk/oss/boot/u-boot-1.1.4/tree/board/ar7240/ap123/ap123.c?h=1.1

+return get_ram_size((void *)KSEG1, SZ_256M);
+}
diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
new file mode 100644
index 000..893dedc
--- /dev/null
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -0,0 +1,1184 @@
+/*
+ * Atheros AR71XX/AR724X/AR913X SoC register definitions
+ *
+ * Copyright (C) 2015-2016 Wills Wang 
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan

+ * Copyright (C) 2008-2010 Gabor Juhos 
+ * Copyright (C) 2008 Imre Kaloz 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_AR71XX_REGS_H
+#define __ASM_MACH_AR71XX_REGS_H
+
+#ifndef __ASSEMBLY__
+#include 
+#else
+#ifndef BIT
+#define BIT(nr) (1 << (nr))

This should really go into some common header.

This header is also included by some assembly code,
but the BIT macro in linux/bitops.h isn't compatiable with assembler.

Because of the 1UL in it ?

Yes, there are also a few other C keywords and syntax, such as in-line
function.

Hm, it pains me to see such duplication, but I have no better idea
how to deal with it without introducing ifdefs.



--
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Wills

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Re: [U-Boot] [U-Boot, 05/27] omap4: Export elpidia sdram device details

[Tom Rini]

On Sat, Feb 27, 2016 at 07:18:53PM +0100, Paul Kocialkowski wrote:

> Individual boards might provide their own emif_get_device_details function and
> use elpidia device details in their own way, hence those have to be exported.
> 
> This also wraps existing definitions with the proper ifdef logic.
> 
> Signed-off-by: Paul Kocialkowski 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] sunxi: Support SID e-fuses on A83T and H3

[Hans de Goede]

Hi,

On 27-01-16 09:34, Chen-Yu Tsai wrote:

On the A83T and H3, the SID block is at a different address.
Furthurmore, the e-fuses are at an offset of 0x200 within the
hardware's address space.

Signed-off-by: Chen-Yu Tsai 


Thanks, applied to my tree and this will go out with the
next pull-req.

Regards,

Hans



---
  arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 7 +++
  1 file changed, 7 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h 
b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 0cdefdc..f797649 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -74,7 +74,14 @@
  #define SUNXI_AD_DA_BASE  0x01c22c00
  #define SUNXI_KEYPAD_BASE 0x01c23000
  #define SUNXI_TZPC_BASE   0x01c23400
+
+#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN8I_H3)
+/* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */
+#define SUNXI_SID_BASE 0x01c14200
+#else
  #define SUNXI_SID_BASE0x01c23800
+#endif
+
  #define SUNXI_SJTAG_BASE  0x01c23c00

  #define SUNXI_TP_BASE 0x01c25000


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Re: [U-Boot] [PATCH v3 05/10] x86: ivybridge: Convert to use the common SDRAM code

[Bin Meng]

On Wed, Mar 16, 2016 at 9:44 PM, Simon Glass  wrote:
> Adjust the existing implementation to use the new common SDRAM init code.
>
> Signed-off-by: Simon Glass 
> Reviewed-by: Bin Meng 
> ---
>
> Changes in v3: None
> Changes in v2:
> - Rename sdram to mrc
>
>  arch/x86/cpu/ivybridge/sdram.c | 394 
> +
>  1 file changed, 83 insertions(+), 311 deletions(-)
>

applied to u-boot-x86, thanks!
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[U-Boot] [PATCH] Fix typo in chosen parameter in vf610-twr.dts.

[Alexander Merkle]

Signed-off-by: Alexander Merkle 
---

 arch/arm/dts/vf610-twr.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/vf610-twr.dts b/arch/arm/dts/vf610-twr.dts
index a4ccbcb..237aa8d 100644
--- a/arch/arm/dts/vf610-twr.dts
+++ b/arch/arm/dts/vf610-twr.dts
@@ -11,7 +11,7 @@
model = "VF610 Tower Board";
compatible = "fsl,vf610-twr", "fsl,vf610";
 
-   choosen {
+   chosen {
stdout-path = 
};
 
-- 
2.7.0

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Re: [U-Boot] [PATCH v2 2/2] mmc: Print send_cmd response only when return value is zero

[Tom Rini]

On Thu, Mar 17, 2016 at 09:53:14PM -0700, Bin Meng wrote:

> send_cmd response is valid only when no error happened. If an error
> occured, let mmc_send_cmd() print the return value to aid debugging.
> 
> Signed-off-by: Bin Meng 
> 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] [PATCH v8 2/9] mips: ath79: add support for AR933x SOCs

[Marek Vasut]

On 03/16/2016 09:59 AM, Wills Wang wrote:
> This patch enable work for ar933x SOC.
> 
> Signed-off-by: Wills Wang 
> ---
> 
> Changes in v8:
> - Fix multi-line comment for ar933x
> 
> Changes in v7:
> - Use CKSEGxADDR instead of KSEGxADDR for ar933x
> 
> Changes in v6:
> - Remove board.c
> - Define magic value in ddr.c
> 
> Changes in v5:
> - Add ddr.c for ar933x
> 
> Changes in v4:
> - Add clk.c for ar933x
> 
> Changes in v3: None
> Changes in v2: None

[...]

> +#define DDR_REFRESH_EN  (1 << 14)
> +#define DDR_REFRESH_M   0x3ff
> +#define DDR_REFRESH(x)  ((x) & 0x3ff)
> +#define DDR_REFRESH_VAL_25M (DDR_REFRESH_EN | DDR_REFRESH(390))
> +#define DDR_REFRESH_VAL_40M (DDR_REFRESH_EN | DDR_REFRESH(624))
> +
> +#define DDR_TRAS_S  0
> +#define DDR_TRAS_M  0x1f
> +#define DDR_TRAS(x) ((x) << DDR_TRAS_S)
> +#define DDR_TRCD_M  0xf
> +#define DDR_TRCD_S  5
> +#define DDR_TRCD(x) ((x) << DDR_TRCD_S)
> +#define DDR_TRP_M   0xf
> +#define DDR_TRP_S   9
> +#define DDR_TRP(x)  ((x) << DDR_TRP_S)
> +#define DDR_TRRD_M  0xf
> +#define DDR_TRRD_S  13
> +#define DDR_TRRD(x) ((x) << DDR_TRRD_S)
> +#define DDR_TRFC_M  0x7f
> +#define DDR_TRFC_S  17
> +#define DDR_TRFC(x) ((x) << DDR_TRFC_S)
> +#define DDR_TMRD_M  0xf
> +#define DDR_TMRD_S  23
> +#define DDR_TMRD(x) ((x) << DDR_TMRD_S)
> +#define DDR_CAS_L_M 0x17
> +#define DDR_CAS_L_S 27
> +#define DDR_CAS_L(x)(((x) & DDR_CAS_L_M) << DDR_CAS_L_S)
> +#define DDR_OPEN(1 << 30)

Use the BIT() macro consistently ;-)

> +#define DDR_CONF_REG_VAL(DDR_TRAS(16) | DDR_TRCD(6) | \
> +  DDR_TRP(6) | DDR_TRRD(4) | \
> +  DDR_TRFC(30) | DDR_TMRD(15) | \
> +  DDR_CAS_L(7) | DDR_OPEN)
> +

[...]

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Re: [U-Boot] [U-Boot,24/27] power: twl6030: Power off support

[Tom Rini]

On Sat, Feb 27, 2016 at 07:19:12PM +0100, Paul Kocialkowski wrote:

> This adds support for powering off (the omap SoC) from the twl6030.
> 
> Signed-off-by: Paul Kocialkowski 

Applied to u-boot/master, thanks!

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[U-Boot] [PATCH 13/13] ARM: uniphier: support Debug UART

[Masahiro Yamada]

For ARM32 architecture, CONFIG_DEBUG_LL is available for early
low-level debugging (and actually UniPhier 32bit SoCs use it), but
ARM64 architecture does not support it.  Instead, CONFIG_DEBUG_UART
is available as an architecture-independent debug facility.

This commit supports it on all the UniPhier SoCs (including the new
ARMv8 SoCs), which is very useful for new SoC bringups.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/Makefile|  1 +
 arch/arm/mach-uniphier/debug-uart/Makefile | 17 +
 .../arm/mach-uniphier/debug-uart/debug-uart-ld20.c | 35 +
 arch/arm/mach-uniphier/debug-uart/debug-uart-ld4.c | 21 ++
 .../arm/mach-uniphier/debug-uart/debug-uart-ld6b.c | 31 
 .../arm/mach-uniphier/debug-uart/debug-uart-pro4.c | 31 
 .../arm/mach-uniphier/debug-uart/debug-uart-pro5.c | 34 +
 .../arm/mach-uniphier/debug-uart/debug-uart-pxs2.c | 32 
 .../arm/mach-uniphier/debug-uart/debug-uart-sld3.c | 31 
 .../arm/mach-uniphier/debug-uart/debug-uart-sld8.c | 21 ++
 arch/arm/mach-uniphier/debug-uart/debug-uart.c | 85 ++
 arch/arm/mach-uniphier/debug-uart/debug-uart.h | 20 +
 arch/arm/mach-uniphier/init/init.c |  8 ++
 drivers/serial/Kconfig |  9 +++
 14 files changed, 376 insertions(+)
 create mode 100644 arch/arm/mach-uniphier/debug-uart/Makefile
 create mode 100644 arch/arm/mach-uniphier/debug-uart/debug-uart-ld20.c
 create mode 100644 arch/arm/mach-uniphier/debug-uart/debug-uart-ld4.c
 create mode 100644 arch/arm/mach-uniphier/debug-uart/debug-uart-ld6b.c
 create mode 100644 arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c
 create mode 100644 arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c
 create mode 100644 arch/arm/mach-uniphier/debug-uart/debug-uart-pxs2.c
 create mode 100644 arch/arm/mach-uniphier/debug-uart/debug-uart-sld3.c
 create mode 100644 arch/arm/mach-uniphier/debug-uart/debug-uart-sld8.c
 create mode 100644 arch/arm/mach-uniphier/debug-uart/debug-uart.c
 create mode 100644 arch/arm/mach-uniphier/debug-uart/debug-uart.h

diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index 1a8c649..35edca1 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -28,5 +28,6 @@ obj-y += boot-mode/
 obj-y += dram/
 
 obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
+obj-$(CONFIG_DEBUG_UART_UNIPHIER) += debug-uart/
 
 obj-$(CONFIG_CPU_V7) += arm32/
diff --git a/arch/arm/mach-uniphier/debug-uart/Makefile 
b/arch/arm/mach-uniphier/debug-uart/Makefile
new file mode 100644
index 000..0bad718
--- /dev/null
+++ b/arch/arm/mach-uniphier/debug-uart/Makefile
@@ -0,0 +1,17 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3)   += debug-uart-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4)+= debug-uart-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4)   += debug-uart-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8)   += debug-uart-sld8.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO5)   += debug-uart-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS2)   += debug-uart-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD6B)   += debug-uart-ld6b.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)   += debug-uart-ld20.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)   += debug-uart-ld20.o
+endif
+
+obj-y  += debug-uart.o
diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-ld20.c 
b/arch/arm/mach-uniphier/debug-uart/debug-uart-ld20.c
new file mode 100644
index 000..2dc2bf8
--- /dev/null
+++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-ld20.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+#include "../sc64-regs.h"
+#include "../sg-regs.h"
+#include "debug-uart.h"
+
+#define UNIPHIER_LD20_UART_CLK 5882
+
+unsigned int uniphier_ld20_debug_uart_init(void)
+{
+   u32 tmp;
+
+   sg_set_iectrl(54);  /* TXD0 */
+   sg_set_iectrl(58);  /* TXD1 */
+   sg_set_iectrl(90);  /* TXD2 */
+   sg_set_iectrl(94);  /* TXD3 */
+   sg_set_pinsel(54, 0, 8, 4); /* TXD0 -> TXD0 */
+   sg_set_pinsel(58, 1, 8, 4); /* SPITXD1 -> TXD1 */
+   sg_set_pinsel(90, 1, 8, 4); /* PC0WE -> TXD2 */
+   sg_set_pinsel(94, 1, 8, 4); /* PCD00 -> TXD3 */
+
+   tmp = readl(SC_CLKCTRL4);
+   tmp |= SC_CLKCTRL4_PERI;
+   writel(tmp, SC_CLKCTRL4);
+
+   return DIV_ROUND_CLOSEST(UNIPHIER_LD20_UART_CLK, 16 * CONFIG_BAUDRATE);
+}
diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-ld4.c 
b/arch/arm/mach-uniphier/debug-uart/debug-uart-ld4.c
new file mode 100644
index 000..d5f1234
--- /dev/null
+++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-ld4.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 

Re: [U-Boot] [PATCH v8 3/9] mips: ath79: add support for QCA953x SOCs

[Marek Vasut]

On 03/17/2016 04:14 AM, Wills Wang wrote:
> 
> 
> On Thursday, March 17, 2016 05:39 AM, Marek Vasut wrote:
>> On 03/16/2016 09:59 AM, Wills Wang wrote:
>>> This patch enable work for qca953x SOC.
>>>
>>> Signed-off-by: Wills Wang 
>>> ---
>>>
>>> Changes in v8:
>>> - Fix multi-line comment for qca953x
>>>
>>> Changes in v7:
>>> - Use CKSEGxADDR instead of KSEGxADDR for qca953x
>>>
>>> Changes in v6:
>>> - Initial support for qca953x
>> Same comment about the BIT() macro as ar933x support. Did you ever test
>> the QCA953x ?
> Yes, i have a qca9531 board that is compatible with AP143.

Cool, thanks for confirming :-)

-- 
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Re: [U-Boot] [U-Boot,21/27] kc1: OMAP4 reboot mode support

[Tom Rini]

On Sat, Feb 27, 2016 at 07:19:09PM +0100, Paul Kocialkowski wrote:

> This adds support for the omap4 reboot mode mechanism and exports the reboot
> mode via an environment variable, that is used in the boot command to make it
> possible to boot from the recovery partition or fastboot.
> 
> Signed-off-by: Paul Kocialkowski 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] sunxi: chip: enable composite video out

[Hans de Goede]

Hi,

On 07-03-16 13:50, Maxime Ripard wrote:

From: Alex Kaplan 

The CHIP has a composite video output in the mini-Jack connector, alongside
with the 2 audio channels. Enable this output in U-Boot.

Signed-off-by: Alex Kaplan 
Signed-off-by: Maxime Ripard 


Thanks,

Merged.

Regards,

Hans



---
  configs/CHIP_defconfig | 1 +
  1 file changed, 1 insertion(+)

diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index 3135d1c88e79..4f99d1efdf9e 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -4,6 +4,7 @@ CONFIG_MACH_SUN5I=y
  CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
  # CONFIG_MMC is not set
  CONFIG_USB0_VBUS_PIN="PB10"
+CONFIG_VIDEO_COMPOSITE=y
  CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
  CONFIG_SPL=y
  CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"


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Re: [U-Boot] [PATCH 2/6] i2c: designware_i2c: Add dw_i2c_enable() helper function

[Marek Vasut]

On 03/18/2016 01:04 PM, Stefan Roese wrote:
> On 18.03.2016 12:12, Marek Vasut wrote:
>> On 03/18/2016 08:54 AM, Stefan Roese wrote:
>>> dw_i2c_enable() is used to dis-/en-able the I2C controller. It makes
>>> sense to add such a function, as the controller is dis-/en-abled
>>> multiple times in the code. Additionally, this function now checks,
>>> if the controller is really dis-/en-abled. This code is copied
>>> from the Linux I2C driver version.
>>>
>>> Signed-off-by: Stefan Roese 
>>> Cc: Simon Glass 
>>> Cc: Bin Meng 
>>> Cc: Marek Vasut 
>>> Cc: Heiko Schocher 
>>> ---
>>>   drivers/i2c/designware_i2c.c | 46
>>> +---
>>>   1 file changed, 26 insertions(+), 20 deletions(-)
>>>
>>> diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
>>> index e768cde..c8ea520 100644
>>> --- a/drivers/i2c/designware_i2c.c
>>> +++ b/drivers/i2c/designware_i2c.c
>>> @@ -34,6 +34,26 @@ static struct i2c_regs *i2c_get_base(struct
>>> i2c_adapter *adap)
>>>   return NULL;
>>>   }
>>>
>>> +static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
>>> +{
>>> +int timeout = 100;
>>> +
>>> +do {
>>> +writel(enable, _base->ic_enable);
>>
>> This should at least use IC_ENABLE_0B and not the boot enable.
>>
>>> +if ((readl(_base->ic_enable_status) & 1) == enable)
>>> +return;
>>> +
>>> +/*
>>> + * Wait 10 times the signaling period of the highest I2C
>>> + * transfer supported by the driver (for 400KHz this is
>>> + * 25us) as described in the DesignWare I2C databook.
>>> + */
>>> +udelay(25);
>>> +} while (timeout--);
>>> +
>>> +printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
>>> +}
>>> +
>>>   /*
>>>* set_speed - Set the i2c speed mode (standard, high, fast)
>>>* @i2c_spd:required i2c speed mode
>>> @@ -45,12 +65,9 @@ static void set_speed(struct i2c_adapter *adap,
>>> int i2c_spd)
>>>   struct i2c_regs *i2c_base = i2c_get_base(adap);
>>>   unsigned int cntl;
>>>   unsigned int hcnt, lcnt;
>>> -unsigned int enbl;
>>>
>>>   /* to set speed cltr must be disabled */
>>> -enbl = readl(_base->ic_enable);
>>> -enbl &= ~IC_ENABLE_0B;
>>> -writel(enbl, _base->ic_enable);
>>> +dw_i2c_enable(i2c_base, 0);
>>
>> This and all the other places which you changed actually change the
>> logic of the code, right ? Is that a problem ?
> 
> It is a functional change, yes. With a now added check, if the
> controller is actually getting enabled or disabled. The code is
> taken from the Linux kernel, as noted in the commit text. And
> I've tested this code on SoCFPGA without any issues so far.
> 
> Additional testing would be very welcome though. ;)

I will have a board ready for mainlining that uses i2c, so if something
breaks, I will cry ;-)

-- 
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[U-Boot] Please pull u-boot-dm

[Simon Glass]

Hi Tom,

Here is the rest of the block device stuff as well as a few buildman
improvements and a few other things.

The following changes since commit f23baa572f96e1e13d7f1a3c8addb61b5d0dbd29:

  cmd_dhry.c: Use lldiv for vax_mips calculation as well (2016-03-17
10:14:25 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-dm.git

for you to fetch changes up to e4fb863f6dec0002069d57422ebe3ce3af69a273:

  dm: blk: Add tests for block devices (2016-03-17 21:27:39 -0600)


Michal Simek (1):
  dm: ns16550: Add support for reg-offset property

Przemyslaw Marczak (2):
  dts:exynos:update pinctrl size-cells and fix child regs
  Revert "fdt: fix address cell count checking in fdt_translate_address()"

Simon Glass (8):
  gpio: Report errors when GPIOs cannot be read
  buildman: Allow branch names which conflict with directories
  buildman: Add a way to specific a full toolchain prefix
  buildman: Clarify the use of -V
  dm: usb: Unbind old block devices when shutting down USB
  dm: sandbox: Switch over to use DM for block devices
  dm: sandbox: Drop the pre-DM host implementation
  dm: blk: Add tests for block devices

 arch/arm/dts/exynos4210-pinctrl-uboot.dtsi |   8 +-
 arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi |  18 +--
 arch/arm/dts/exynos5250-pinctrl-uboot.dtsi |  16 +--
 arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi |  12 +-
 arch/arm/dts/s5pc110-pinctrl.dtsi  |   4 +-
 cmd/gpio.c |  34 --
 common/fdt_support.c   |   7 +-
 configs/sandbox_defconfig  |   1 +
 drivers/block/sandbox.c|  90 --
 drivers/serial/ns16550.c   |   6 +-
 drivers/usb/host/usb-uclass.c  |   6 +-
 include/ns16550.h  |   1 +
 test/dm/Makefile   |   1 +
 test/dm/blk.c  |  96 +++
 tools/buildman/README  | 299
-
 tools/buildman/cmdline.py  |   2 +-
 tools/buildman/func_test.py|   2 +
 tools/buildman/toolchain.py|  40 +-
 tools/patman/gitutil.py|   5 +
 19 files changed, 404 insertions(+), 244 deletions(-)
 create mode 100644 test/dm/blk.c

Regards,
Simon
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Re: [U-Boot] [PATCH] sandbox: Enable many more commands

[Tom Rini]

On Sat, Mar 19, 2016 at 06:25:48PM -0600, Simon Glass wrote:
> Hi Tom,
> 
> On 15 March 2016 at 21:32, Simon Glass  wrote:
> >
> > On 15 March 2016 at 11:20, Tom Rini  wrote:
> > >   good enough.
> > > - Make  include  like other arches do
> > > - Enable many many more drivers in sandbox_defconfig so that we can get
> > >   more build-time testing on this platform.
> > >
> > > Cc: Simon Glass 
> > > Signed-off-by: Tom Rini 
> > > ---
> > >  arch/sandbox/include/asm/cache.h |1 +
> > >  arch/sandbox/include/asm/io.h|1 +
> > >  configs/sandbox_defconfig|   56 
> > > --
> > >  3 files changed, 56 insertions(+), 2 deletions(-)
> >
> > Great!
> >
> > Reviewed-by: Simon Glass 
> 
> I am seeing errors with this patch building for sandbox:
> 
> tools/bin2header.c: In function ‘main’:
> tools/bin2header.c:26:3: warning: implicit declaration of function
> ‘read’ [-Wimplicit-function-declaration]
>nread = read(0, buf, sizeof(buf));
>^
> cmd/license.c:15:21: fatal error: license.h: No such file or directory
>  #include 
>  ^
> compilation terminated.
> make[2]: *** [cmd/license.o] Error 1
> make[2]: *** Waiting for unfinished jobs
> make[1]: *** [cmd] Error 2
> make[1]: *** Waiting for unfinished jobs
> make: *** [sub-make] Error 2
> 
> 
> Can you take a look? If it matters I am doing an out-of-tree build.

Yeah, sorry, this relies on the cmd: license patch I posted in order to
work as nothing uses the license command today and it's pretty badly
broken, but easily fixed.  I was hoping Masahiro would chime in on the
kbuild fun that the patch does, but if you wanna pull it in that's fine,
I'll probably grab it soon otherwise myself.

-- 
Tom


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Re: [U-Boot] [PATCH v3 4/4] dm: blk: Add tests for block devices

[Simon Glass]

On 13 March 2016 at 08:22, Simon Glass  wrote:
> Add some tests to check that block devices work as expected.
>
> Signed-off-by: Simon Glass 
> Tested-by: Stephen Warren 
> ---
>
> Changes in v3:
> - Drop patches already applied
>
> Changes in v2:
> - Rename to blk_get_device_by_str()
>
>  test/dm/Makefile |  1 +
>  test/dm/blk.c| 96 
> 
>  2 files changed, 97 insertions(+)
>  create mode 100644 test/dm/blk.c

Applied to u-boot-dm.
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Re: [U-Boot] [PATCH v3 2/4] dm: sandbox: Switch over to use DM for block devices

[Simon Glass]

On 13 March 2016 at 08:22, Simon Glass  wrote:
> Now that the drivers used by sandbox support CONFIG_BLK, we can switch
> sandbox over to use driver model for block devices.
>
> Signed-off-by: Simon Glass 
> Tested-by: Stephen Warren 
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  configs/sandbox_defconfig | 1 +
>  1 file changed, 1 insertion(+)

Applied to u-boot-dm.
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Re: [U-Boot] [PATCH v2 3/3] buildman: Clarify the use of -V

[Simon Glass]

On 14 March 2016 at 10:56, Stephen Warren  wrote:
> On 03/12/2016 06:50 PM, Simon Glass wrote:
>>
>> This option outputs to the log file, not to the terminal. Clarify that in
>> the help, and add a mention of it in the README.
>
>
> Reviewed-by: Stephen Warren 

Applied to u-boot-dm.
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Re: [U-Boot] [PATCH v3 3/4] dm: sandbox: Drop the pre-DM host implementation

[Simon Glass]

On 13 March 2016 at 08:22, Simon Glass  wrote:
> Driver model is used for host device block devices now, so we don't need the
> old code. Remove it.
>
> Signed-off-by: Simon Glass 
> Tested-by: Stephen Warren 
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  drivers/block/sandbox.c | 90 
> -
>  1 file changed, 90 deletions(-)

Applied to u-boot-dm.
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Re: [U-Boot] [PATCH v3 1/4] dm: usb: Unbind old block devices when shutting down USB

[Simon Glass]

On 13 March 2016 at 08:22, Simon Glass  wrote:
> When 'usb start' is used, block devices are created for any USB flash sticks
> and disks, etc. When 'usb stop' is used, these block devices are currently
> not removed.
>
> We don't want old block devices hanging around since they can still be
> visible to U-Boot. Therefore, when USB is shut down, remove and unbind all
> the block devices created by the USB subsystem.
>
> Possibly we should unbind all devices which don't cause problems by being
> unbound. Most likely we can remove everything except USB controllers, hubs
> and emulators. We can consider that later.
>
> Signed-off-by: Simon Glass 
> Tested-by: Stephen Warren 
> ---
>
> Changes in v3:
> - Expand the commit message
>
> Changes in v2: None
>
>  drivers/usb/host/usb-uclass.c | 6 +-
>  1 file changed, 5 insertions(+), 1 deletion(-)

Applied to u-boot-dm.
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Re: [U-Boot] [PATCH v2 1/3] buildman: Allow branch names which conflict with directories

[Simon Glass]

On 12 March 2016 at 18:50, Simon Glass  wrote:
>
> At present if you try to use buildman with the branch 'test' it will
> complain that it is unsure whether you mean the branch or the directory.
> This is a feature of the 'git log' command that buildman uses. Fix it
> by resolving the ambiguity.
>
> Signed-off-by: Simon Glass 
> Reviewed-by: Joe Hershberger 
> ---
>
> Changes in v2:
> - Fix test breakage
>
>  tools/buildman/func_test.py | 2 ++
>  tools/patman/gitutil.py | 5 +
>  2 files changed, 7 insertions(+)

Applied to u-boot-dm.
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Re: [U-Boot] [PATCH v2 2/3] buildman: Add a way to specific a full toolchain prefix

[Simon Glass]

Hi Stephen,

On 14 March 2016 at 10:56, Stephen Warren  wrote:
> On 03/12/2016 06:50 PM, Simon Glass wrote:
>>
>> At present buildman allows you to specify the directory containing the
>> toolchain, but not the actual toolchain prefix. If there are multiple
>> toolchains in a single directory, this can be inconvenient.
>>
>> Add a new 'toolchain-prefix' setting to the settings file, which allows
>> the full prefix (or path to the C compiler) to be specified.
>>
>> Update the documentation to match.
>
>
> Excellent, now the buildman config file does exactly what I want:-)
>
> Tested-by: Stephen Warren 
> I tested the version already applied in u-boot-dm/buildman, which I assume
> is the same as this:-)

Yes it is. Thanks for testing it.

Applied to u-boot-dm.

Regards,
Simon
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Re: [U-Boot] [PATCH] sandbox: Enable many more commands

[Simon Glass]

Hi Tom,

On 15 March 2016 at 21:32, Simon Glass  wrote:
>
> On 15 March 2016 at 11:20, Tom Rini  wrote:
> >   good enough.
> > - Make  include  like other arches do
> > - Enable many many more drivers in sandbox_defconfig so that we can get
> >   more build-time testing on this platform.
> >
> > Cc: Simon Glass 
> > Signed-off-by: Tom Rini 
> > ---
> >  arch/sandbox/include/asm/cache.h |1 +
> >  arch/sandbox/include/asm/io.h|1 +
> >  configs/sandbox_defconfig|   56 
> > --
> >  3 files changed, 56 insertions(+), 2 deletions(-)
>
> Great!
>
> Reviewed-by: Simon Glass 

I am seeing errors with this patch building for sandbox:

tools/bin2header.c: In function ‘main’:
tools/bin2header.c:26:3: warning: implicit declaration of function
‘read’ [-Wimplicit-function-declaration]
   nread = read(0, buf, sizeof(buf));
   ^
cmd/license.c:15:21: fatal error: license.h: No such file or directory
 #include 
 ^
compilation terminated.
make[2]: *** [cmd/license.o] Error 1
make[2]: *** Waiting for unfinished jobs
make[1]: *** [cmd] Error 2
make[1]: *** Waiting for unfinished jobs
make: *** [sub-make] Error 2


Can you take a look? If it matters I am doing an out-of-tree build.

Regards,
Simon
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Re: [U-Boot] [PATCH 00/18] sf: fix support of QSPI memories and controllers

[Cyrille Pitchen]

Le 16/03/2016 15:14, Jagan Teki a écrit :
> On Wednesday 16 March 2016 07:00 PM, Cyrille Pitchen wrote:
>> Le 15/03/2016 19:21, Jagan Teki a écrit :
>>> On Tuesday 15 March 2016 11:42 PM, Cyrille Pitchen wrote:
 Hi all,

 This series of patches fixes and extend the support of QSPI memories
 in the SPI flash framework. The updates are split into many parts to
 make it easier to understand and review but they should be considered
 as a whole.

 This was tested on a Atmel sama5d2 xplained board with a Micron n25q128a
 memory.

 Best regards,

 Cyrille

 Cyrille Pitchen (18):
 Revert "sf: Fix quad bit set for micron devices"
 sf: call spi_claim_bus() and spi_release_bus() only once per read,
   write or erase
 sf: replace spi_flash_read_common() calls by spi_flash_cmd_read()
 sf: remove spi_flash_write_common()
 sf: export spi_flash_wait_ready() function
 sf: share erase generic algorithm
 sf: share write generic algorithm
 sf: share read generic algorithm
 sf: add hooks to handle register read and write operations
 sf: move support of SST flash into generic spi_flash_write_alg()
 sf: fix selection of supported READ commands for QSPI memories
 sf: fix detection of QSPI memories when they boot in Quad or Dual mode
 sf: add helper function to set the number of dummy bytes
 sf: add 4byte address opcodes
 sf: prepare next fixes to support of QSPI memories by manufacturer
 sf: fix support of Micron memories
 ARM: at91: clock: add function to get QSPI clocks
 sf: add driver for Atmel QSPI controller
>>>
>>> Appreciate for the work, we're working on spi-nor framework[1] planning to 
>>> push in couple of weeks. Will let you know once it merged so that you can 
>>> add your changes on top of that.
>>>
>>> [1] 
>>> http://git.denx.de/?p=u-boot/u-boot-spi.git;a=shortlog;h=refs/heads/spi-nor-next
>>>
>>
>> Hi Jagan,
>>
>> I've started to have a look on your branch. I hope it's not to late for few
>> comments:
>>
>> Globally I see the new code attend to match the spi-nor framework from Linux.
>> OK that's fine but please note the current spi-nor framework in Linux has
>> incomplete and sometime not working support of QSPI memories.
>>
>> First, after a discussion with Brian and Bean on linux-mtd [1], Bean's commit
>> to add support to Micron QSPI memories was reverted since it didn't work 
>> alone.
>> In his reply, Brian agreed the code was not tested and should not have been
>> merged.
>>
>> This highlights a more general issue: currently, there is no mean for the
>> spi-nor framework to notify the SPI controller driver about a SPI protocol
>> change at the QSPI memory side. This applies to Micron memories when they 
>> enter
>> their Quad I/O mode. If so, ALL commands, even JEDEC Read ID, Read Status
>> Register, ..., MUST use the SPI 4-4-4 protocol. Commands sent using SPI 1-x-y
>> protocols are no longer decoded properly.
>> This also applies to Macronix and Winbond memories if they enter their QPI
>> mode, which is the equivalent of Micron Quad I/O mode.
>> This is why I've suggested to add 4 new fields in the struct spi_nor:
>> - .reg_proto: the SPI protocol to be used by .read_reg() and .write_reg()
>>hooks.
>> - .read_proto: the SPI protocol to be used by the .read() hooks, maybe by the
>>.read_mmap() also.
>> - .write_proto: the SPI protocol to be used by the .write() hooks
>> - .erase_proto: the SPI protocol to be used by the .erase() hooks.
>>
>> (Q)SPI controller drivers cannot guess the protocol to be used from the 
>> command
>> op code. Indeed, taking the Micron case as un example, the very same 0xeb op
>> code may be used with the SPI 1-4-4 protocol (Micron Extended SPI mode) or
>> with the SPI 4-4-4 protocol (Micron Quad I/O mode).
>>
>>
>> Also just some words about the naming of SPI x-y-z protocols:
>> - x refers to the number of I/O lines used to send the op code byte
>> - y is the number of I/O lines used to send the address, mode/dummy cycles
>>(if these cycles exist for the command op code)
>> - z is the number of I/O lines used to send/receive data (if needed)
>>
>> So the SNOR_OP_READ_1_1_2_IO macro for the Fast Read Dual I/O command (as
>> opposed to the macro SNOR_OP_READ_1_1_2 macro for the Fast Read Dual Output
>> command) doesn't make sense: it should be named SNOR_OP_READ_1_2_2.
>>
>>
>> Then about the value used for the dummy cycles, it's not always true that we
>> don't care about initializing them. Depending on the configuration of the
>> memory, some special dummy cycles, sometime called mode cycles, are used to
>> during Fast Read operations to make the memory enter/leaver its Continuous 
>> Read
>> mode. Once is Continuous Read mode, the op code byte is no longer sent, it is
>> implicit and the command actually starts from the address cycles. This mode
>> is 

Re: [U-Boot] [PATCH v2 0/5] Enable caches for the RPi2

[Alexander Graf]

On 17.03.16 05:26, Stephen Warren wrote:
> On 03/16/2016 08:41 AM, Alexander Graf wrote:
>> This patch set converts the Raspberry Pi 2 system to properly make use of
>> the caches available in it.
>>
>> Because we're running in HYP mode, we first need to teach U-Boot how to
>> make use of HYP registers and the LPAE page layout which is mandated by
>> hardware when running in HYP mode.
>>
>> Then while we're at it, also mark the frame buffer cached to speed up
>> screen updates.
>>
>> With this patch set, my Raspberry Pi 3 running in AArch32 mode is a *lot*
>> faster than without.
>>
>> Please verify that the code works on a RPi2 as well and doesn't break the
>> original Pi. In theory it should work, but I only have a 3 to test on
>> available here.
> 
> This series mostly works OK. I found the following results, with my
> rpi_dev branch on github if you want to test the exact same commits:
> 
> RPi B+ (running rpi_1 build):
> - Very minor transient corruption when running "ls mmc 0:2 /etc"
> 
> RPi 2 (running rpi_2 build):
> RPi 3 (booting in 32-bit mode and running rpi_2 build):
> RPi 3 (booting in 32-bit mode and running rpi_3_32b build):
> - Obvious transient corruption when running "ls mmc 0:2 /etc"
> 
> RPi 3 (booting in 64-bit mode and running rpi_3 build):
> - No issues
> 
> I suspect the transient corruptions that I saw were missing cache flush
> operations; during the large "memcpy" while scrolling the LCD, I would
> see corruption in the copied data. This would soon disappear; presumably
> as new data is written to the bottom lines of the frame-buffer flushes
> out old cache lines while doing a write-allocate?
> 
> Still, I'm not 100% sure this is an issue with these patches since the
> RPi B+ has a similar (although much less obvious) issue. Perhaps U-Boot
> is using the wrong VC/GPU cache alias (top 2 bits of 32-bit physical
> address) for the frame-buffer, i.e. the issue is in the GPU cache, not
> in the ARM cache?
> 
> As far as I can tell, USB worked fine in all cases (at least, the
> on-board hub/Ethernet device seemed to be enumerated without issue
> according to "usb tree" and "usb info".)
> 
> As such, I'm tempted to just ack the patches, but it'd be nice if you
> could take a look and see if something obvious is wrong.

Ugh. It helps when you get the parameters for ALIGN() correctly.

Please just squash the patch below into the last patch, then things
should work fine. If you like I can resend a v3, but I guess the change
is small enough?


Alex

diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c
index fe49f2e..40fc418 100644
--- a/drivers/video/bcm2835.c
+++ b/drivers/video/bcm2835.c
@@ -109,7 +109,7 @@ void lcd_ctrl_init(void *lcdbase)

/* Enable dcache for the frame buffer */
 mmu_set_region_dcache_behaviour(gd->fb_base,
-   ALIGN(PAGE_SIZE,
msg_setup->allocate_buffer.body.resp.fb_size),
+   ALIGN(msg_setup->allocate_buffer.body.resp.fb_size,
PAGE_SIZE),
DCACHE_WRITEBACK);
lcd_set_flush_dcache(1);
 }
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Re: [U-Boot] [PATCH v8 3/9] mips: ath79: add support for QCA953x SOCs

[Wills Wang]

On Thursday, March 17, 2016 05:39 AM, Marek Vasut wrote:

On 03/16/2016 09:59 AM, Wills Wang wrote:

This patch enable work for qca953x SOC.

Signed-off-by: Wills Wang 
---

Changes in v8:
- Fix multi-line comment for qca953x

Changes in v7:
- Use CKSEGxADDR instead of KSEGxADDR for qca953x

Changes in v6:
- Initial support for qca953x

Same comment about the BIT() macro as ar933x support. Did you ever test
the QCA953x ?

Yes, i have a qca9531 board that is compatible with AP143.

Best regards,
Marek Vasut


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Wills

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Re: [U-Boot] [PATCH] fdt: Try to read #address-cells/size-cells from parent

[Michal Simek]

On 16.3.2016 23:47, David Gibson wrote:
> On Wed, Mar 16, 2016 at 05:18:25PM +0100, Michal Simek wrote:
>> Hi David,
>>
>> On 15.3.2016 01:27, David Gibson wrote:
>>> On Mon, Mar 14, 2016 at 10:10:58PM +0100, Michal Simek wrote:
 On 13.3.2016 02:54, Simon Glass wrote:
> Hi Michal,
>
> On 16 February 2016 at 09:10, Michal Simek  
> wrote:
>> Hi Simon,
>>
>> On 16.2.2016 17:00, Simon Glass wrote:
>>> Hi Michal,
>>>
>>> On 15 February 2016 at 02:58, Michal Simek  
>>> wrote:
 Hi Simon,

 On 10.2.2016 13:04, Michal Simek wrote:
> Read #address-cells and #size-cells from parent if they are not 
> present in
> current node.
>
> Signed-off-by: Michal Simek 
> ---
>
> I have code which read information about memory for zynqmp but memory
> node most of the time doesn't contain #address/size-cells which are
> present in parent node.
> That's why let's try to read it from parent.
>
> Also I think that we shouldn't return 2 if property is not found 
> because
> it has side effect on 32bit systems with #address/size-cells = <1>;
>
> ---
>  lib/libfdt/fdt_addresses.c | 18 ++
>  1 file changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/lib/libfdt/fdt_addresses.c b/lib/libfdt/fdt_addresses.c
> index 76054d98e5fd..b164d0988079 100644
> --- a/lib/libfdt/fdt_addresses.c
> +++ b/lib/libfdt/fdt_addresses.c
> @@ -19,10 +19,15 @@ int fdt_address_cells(const void *fdt, int 
> nodeoffset)
>   const fdt32_t *ac;
>   int val;
>   int len;
> + int parent;
>
>   ac = fdt_getprop(fdt, nodeoffset, "#address-cells", );
> - if (!ac)
> - return 2;
> + if (!ac) {
> + parent = fdt_parent_offset(fdt, nodeoffset);
> + ac = fdt_getprop(fdt, parent, "#address-cells", );
> + if (!ac)
> + return 2;
> + }
>
>   if (len != sizeof(*ac))
>   return -FDT_ERR_BADNCELLS;
> @@ -39,10 +44,15 @@ int fdt_size_cells(const void *fdt, int 
> nodeoffset)
>   const fdt32_t *sc;
>   int val;
>   int len;
> + int parent;
>
>   sc = fdt_getprop(fdt, nodeoffset, "#size-cells", );
> - if (!sc)
> - return 2;
> + if (!sc) {
> + parent = fdt_parent_offset(fdt, nodeoffset);
> + sc = fdt_getprop(fdt, parent, "#size-cells", );
> + if (!sc)
> + return 2;
> + }
>
>   if (len != sizeof(*sc))
>   return -FDT_ERR_BADNCELLS;
>

 Simon: Any comment?
>>>
>>> It seems risky to change the behaviour here. Also fdt_parent_offset() 
>>> is slow.
>>>
>>> Can you point me to the binding / example DT that you are trying to 
>>> parse?
>>
>> Look at dram_init(), etc.
>> https://github.com/Xilinx/u-boot-xlnx/blob/master/board/xilinx/zynqmp/zynqmp.c
>>
>> fdt_get_reg() is calling fdt_size_cells()
>>
>>
>> And this is DTS fragment.
>> #address-cells = <2>;
>> #size-cells = <1>;
>>
>> memory {
>> device_type = "memory";
>> reg = <0x0 0x0 0x8000>, <0x8 0x 0x8000>;
>> };
>>
>> Code is in memory node I need to work with and asking for size-cells.
>> Current code returns 2 instead of error and the rest of code just works
>> with size = 2 which is incorrect for this setup.
>>
>> I have already changed size-cells = 2 in our repo because I need to
>> support for more than 4GB memory anyway but this should point to the
>> problem in that generic functions.
>
> I think this should go in a higher-level function. I very much doubt
> that this patch would be accepted upstream.
>
> Can you find the caller and make it call this function again (for the
> parent) when no nothing is found on the first call? Hopefully this
> caller will have access to the parent node and will not need to call
> fdt_parent_offset().

 The funny part is that nothing is found means return 2. If this returns
 something <0 then there is not a problem to try it with parents.
>>>
>>> I don't have the full context of this thread, so it's a bit hard to be
>>> sure, but this doesn't look right from what I can see.  Two things to
>>> remember here:
>>>
>>>   * #address-cells and #size-cells 

Re: [U-Boot] [U-Boot, 15/27] power: twl6030: Configure VUSB voltage on USB device setup

[Tom Rini]

On Sat, Feb 27, 2016 at 07:19:03PM +0100, Paul Kocialkowski wrote:

> This explicitly sets VUSB voltage to 3.3V when enabling USB.
> 
> Signed-off-by: Paul Kocialkowski 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] spl_mmc: allow to load raw image

[Tom Rini]

On Fri, Mar 18, 2016 at 01:07:47AM +0900, Masahiro Yamada wrote:
> Hi Tom,
> 
> 2016-03-17 11:04 GMT+09:00 Tom Rini :
> > On Mon, Feb 29, 2016 at 08:31:57PM +0900, Masahiro Yamada wrote:
> >
> >> The function spl_parse_image_header() falls back to a raw image
> >> if the U-Boot header is missing and CONFIG_SPL_PANIC_ON_RAW_IMAGE
> >> is undefined.  While, the bad magic checking here makes the
> >> spl_parse_image_header() unreachable in case of the missing header.
> >>
> >> Signed-off-by: Masahiro Yamada 
> >> Reviewed-by: Tom Rini 
> >
> > Applied to u-boot/master, thanks!
> 
> I guess this is false.
> 
> This is v1 that you said does not work as is.

Yup, oops, forgot to delete it from my local bundle.

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[U-Boot] [PATCH v2 3/5] lcd: Fix compile warning in 64bit mode

[Alexander Graf]

When compiling the code for 64bit, the lcd code emits warnings because it
tries to cast pointers to 32bit values. Fix it by casting them to longs
instead, actually properly aligning with the function prototype.

Signed-off-by: Alexander Graf 
---
 common/lcd.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/lcd.c b/common/lcd.c
index 51705ad..783626e 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -66,8 +66,8 @@ void lcd_sync(void)
int line_length;
 
if (lcd_flush_dcache)
-   flush_dcache_range((u32)lcd_base,
-   (u32)(lcd_base + lcd_get_size(_length)));
+   flush_dcache_range((ulong)lcd_base,
+   (ulong)(lcd_base + lcd_get_size(_length)));
 #endif
 }
 
-- 
1.8.5.6

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Re: [U-Boot] [U-Boot, 2/4] omap3: Use a define for reboot reason offset

[Tom Rini]

On Sat, Feb 27, 2016 at 07:26:42PM +0100, Paul Kocialkowski wrote:

> This introduces a define for the offset to the reboot reason, rather than
> hardcoding it.
> 
> Signed-off-by: Paul Kocialkowski 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [linux-sunxi] [PATCH v2 1/2] sun7i: Add support for the Itead Ibox

[Hans de Goede]

Hi,

On 15-03-16 18:47, codekip...@gmail.com wrote:

From: Marcus Cooper 

Add dts and defconfig for the multi board device based on the
Allwinner A20 SoC. It contains the A20 Itead Core module and a
base board for the external interfaces.

The core module comes with 4GB NAND and 1GB DDR RAM. As this is
a generic design which has also been used on a A10 board then a
common core dtsi file is included.

The base board to which the core board is connected provides
3 USB 2.0 Host ports, 1 USB 2.0 OTG, 1 uSD slot, 10/100 Ethernet
port, HDMI, IR receiver,  SPDIF and a 32-pin GPIO header. This
header expands the features of core board by exposing the VGA pins,
audio In/Out pins, SATA, SPI, I2C, UARTS, USB-OTG and power..

Signed-off-by: Marcus Cooper 


Thanks, since my sunxi-wip branch already contains a commit syncing
all the sunxi u-boot dts files with the upstream kernel, the dts
file bits are not needed.

I've merged this patch without the dts file bits. This also means
that your second patch is not needed.

Regards,

Hans



---
  arch/arm/dts/Makefile |   1 +
  arch/arm/dts/sun7i-a20-itead-ibox.dts | 121 ++
  arch/arm/dts/sunxi-itead-core-common.dtsi | 136 ++
  board/sunxi/MAINTAINERS   |   5 ++
  configs/Itead_Ibox_A20_defconfig  |  16 
  5 files changed, 279 insertions(+)
  create mode 100644 arch/arm/dts/sun7i-a20-itead-ibox.dts
  create mode 100644 arch/arm/dts/sunxi-itead-core-common.dtsi
  create mode 100644 configs/Itead_Ibox_A20_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b574284..466f961 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -162,6 +162,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-cubietruck.dtb \
sun7i-a20-hummingbird.dtb \
sun7i-a20-i12-tvbox.dtb \
+   sun7i-a20-itead-ibox.dtb \
sun7i-a20-lamobo-r1.dtb \
sun7i-a20-m3.dtb \
sun7i-a20-m5.dtb \
diff --git a/arch/arm/dts/sun7i-a20-itead-ibox.dts 
b/arch/arm/dts/sun7i-a20-itead-ibox.dts
new file mode 100644
index 000..c6fcd36
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-itead-ibox.dts
@@ -0,0 +1,121 @@
+/*
+ * Copyright 2015 - Marcus Cooper 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-itead-core-common.dtsi"
+
+/ {
+   model = "Itead Ibox A20";
+   compatible = "itead,itead-ibox-a20", "allwinner,sun7i-a20";
+
+   leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_itead_core>;
+
+   green {
+   label = "itead_core:green:usr";
+   gpios = < 7 20 GPIO_ACTIVE_HIGH>;
+   default-state = "on";
+   };
+
+   blue {
+   label = "itead_core:blue:usr";
+   gpios = < 7 21 GPIO_ACTIVE_HIGH>;
+   

[U-Boot] [PATCH 3/6] ARM: keystone2: Only link cmd_ddr3.o on non-SPL builds

[Tom Rini]

When we switch to including all linker lists in U-Boot it is important
to not include commands as that may lead to link errors due to other
things we have already discarded.  In this case simply move cmd_ddr3.o
over to the list with the rest.

Cc: Vitaly Andrianov 
Cc: Nishanth Menon 
Cc: Lokesh Vutla 
Signed-off-by: Tom Rini 
---
 arch/arm/mach-keystone/Makefile |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile
index 8829e7f..b2ffe5b 100644
--- a/arch/arm/mach-keystone/Makefile
+++ b/arch/arm/mach-keystone/Makefile
@@ -13,9 +13,10 @@ ifndef CONFIG_SPL_BUILD
 obj-y  += cmd_clock.o
 obj-y  += cmd_mon.o
 obj-y  += cmd_poweroff.o
+obj-y  += cmd_ddr3.o
 endif
 obj-y  += msmc.o
-obj-y  += ddr3.o cmd_ddr3.o
+obj-y  += ddr3.o
 obj-y  += keystone.o
 obj-$(CONFIG_K2E_EVM) += ddr3_spd.o
 obj-$(CONFIG_K2HK_EVM) += ddr3_spd.o
-- 
1.7.9.5

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[U-Boot] [PATCH] arm: socfpga: Nuke useless include

[Marek Vasut]

The dwmmc.h include was forgotten during the migration of dwmmc
probing to DM. Since the shiny DM is in place now, remove this
relic of the past.

Signed-off-by: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
---
 arch/arm/mach-socfpga/misc.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index ce3ff0a..ebaa736 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -16,7 +16,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
-- 
2.7.0

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Re: [U-Boot] [PATCH v4 14/14] SECURE BOOT: Change fsl_secboot_validate function to output image addr

[york sun]

On 02/08/2016 09:27 PM, Saksham Jain wrote:
> Currently, fsl_secboot_validate function used to set env variable "img_addr"
> to contain address of image being validated.
> 
> The function has been changed to output image addr via argument
> img_addr_ptr. The command esbc_validate sets the env variable
> "img_addr".
> 
> This change helps when fsl_secboot_validate function is called from within
> UBOOT (because now instead of calling function "getenv("img_addr")"
> we can directly get the image address.)
> 

Please keep line wrap under 72 characters and consistent.

York

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Re: [U-Boot] [PATCH] sunxi: Add support for Cubietruck Plus

[Dennis Gilmore]

On Saturday, March 19, 2016 5:43:52 PM CDT Dennis Gilmore wrote:
> Hans,
> 
> What is the status of this patch?
> 
> Dennis

With the patch applied building for Cubietruck_plus fails with 

  ld.bfd   -pie  --gc-sections -Bstatic -Ttext 0x4a00 -o u-boot -T u-
boot.lds arch/arm/cpu/armv7/start.o --start-group  arch/arm/cpu/built-in.o  
arch/arm/cpu/armv7/built-in.o  arch/arm/lib/built-in.o  board/sunxi/built-in.o  
cmd/built-in.o  common/built-in.o  disk/built-in.o  drivers/built-in.o  
drivers/dma/built-in.o  drivers/gpio/built-in.o  drivers/i2c/built-in.o  
drivers/mmc/built-in.o  drivers/mtd/built-in.o  drivers/mtd/onenand/built-in.o  
drivers/mtd/spi/built-in.o  drivers/net/built-in.o  drivers/net/phy/built-in.o  
drivers/pci/built-in.o  drivers/power/built-in.o  drivers/power/battery/built-
in.o  drivers/power/fuel_gauge/built-in.o  drivers/power/mfd/built-in.o  
drivers/power/pmic/built-in.o  drivers/power/regulator/built-in.o  drivers/
serial/built-in.o  drivers/spi/built-in.o  drivers/usb/dwc3/built-in.o  
drivers/usb/emul/built-in.o  drivers/usb/eth/built-in.o  drivers/usb/gadget/
built-in.o  drivers/usb/gadget/udc/built-in.o  drivers/usb/host/built-in.o  
drivers/usb/musb-new/built-in.o  drivers/usb/musb/built-in.o  drivers/usb/phy/
built-in.o  drivers/usb/ulpi/built-in.o  fs/built-in.o  lib/built-in.o  net/
built-in.o  test/built-in.o  test/dm/built-in.o --end-group arch/arm/lib/
eabi_compat.o  -L /usr/lib/gcc/armv7hl-redhat-linux-gnueabi/6.0.0 -lgcc -Map 
u-boot.map
board/sunxi/built-in.o: In function `i2c_init_board':
/builddir/build/BUILD/u-boot-2016.03/board/sunxi/board.c:363: undefined 
reference to `clock_twi_onoff'
ld.bfd: BFD version 2.26.20160125 assertion fail elf32-arm.c:8434
ld.bfd: error: required section '.rel.plt' not found in the linker script
ld.bfd: final link failed: Invalid operation


> On Wednesday, January 27, 2016 4:34:44 PM CDT Chen-Yu Tsai wrote:
> > Cubietruck Plus is a A83T/H8 based development board. The board has
> > standard DDR3 SDRAM, AXP818 PMIC/codec, SD/MMC, eMMC, USB 2.0 host
> > via HSIC USB Hub, USB OTG, SATA via USB bridge, gigabit ethernet,
> > WiFi, headphone out / mic in, and various GPIO headers.
> > 
> > The board also has an EEPROM on i2c0 which holds the MAC address.
> > 
> > DLDO3 and DLDO4 provide power to the EMAC pins and PHY. Pin PA20
> > is connected to the reset control of the PHY. EMAC is not actually
> > supported yet.
> > 
> > The DTS is the same as the one already in the kernel.
> > 
> > Signed-off-by: Chen-Yu Tsai 
> > ---
> > 
> >  arch/arm/dts/Makefile   |  1 +
> >  arch/arm/dts/sun8i-a83t-cubietruck-plus.dts | 65
> > 
> > + configs/Cubietruck_plus_defconfig  
> > |
> > 18 
> > 
> >  3 files changed, 84 insertions(+)
> >  create mode 100644 arch/arm/dts/sun8i-a83t-cubietruck-plus.dts
> >  create mode 100644 configs/Cubietruck_plus_defconfig
> > 
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index 1c7d359..e338db5 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -184,6 +184,7 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \
> > 
> > sun8i-a33-sinlinx-sina33.dtb
> >  
> >  dtb-$(CONFIG_MACH_SUN8I_A83T) += \
> >  
> > sun8i-a83t-allwinner-h8homlet-v2.dtb \
> > 
> > +   sun8i-a83t-cubietruck-plus.dtb \
> > 
> > sun8i-a83t-sinovoip-bpi-m3.dtb
> >  
> >  dtb-$(CONFIG_MACH_SUN8I_H3) += \
> >  
> > sun8i-h3-orangepi-pc.dtb \
> > 
> > diff --git a/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts
> > b/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts new file mode 100644
> > index 000..88b1e09
> > --- /dev/null
> > +++ b/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts
> > @@ -0,0 +1,65 @@
> > +/*
> > + * Copyright 2015 Chen-Yu Tsai
> > + *
> > + * Chen-Yu Tsai 
> > + *
> > + * This file is dual-licensed: you can use it either under the terms
> > + * of the GPL or the X11 license, at your option. Note that this dual
> > + * licensing only applies to this file, and not this project as a
> > + * whole.
> > + *
> > + *  a) This file is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of the
> > + * License, or (at your option) any later version.
> > + *
> > + * This file is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * Or, alternatively,
> > + *
> > + *  b) Permission is hereby granted, free of charge, to any person
> > + * obtaining a copy of this software and associated documentation
> > + * files (the "Software"), to deal in the Software without
> > + * restriction, including without limitation the rights to use,
> > + * 

Re: [U-Boot] [U-Boot, 03/10] ti_armv7_keystone2: env: Remove securedb.key.bin load

[Tom Rini]

On Wed, Mar 09, 2016 at 03:39:32PM +0530, Lokesh Vutla wrote:

> From: Carlos Hernandez 
> 
> securedb.key.bin is not supported so it should not be loaded by
> default init_ubi command.
> 
> Signed-off-by: Carlos Hernandez 
> Signed-off-by: Lokesh Vutla 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH 2/2] armv8/ls1043aqds: use configuarable clock for non-QSPI boot

[york sun]

On 03/14/2016 03:06 AM, Gong Qianyu wrote:
> For QSPI boot and SD boot with QSPI, we could only read from FPGA
> through I2C to get the system clock and DDR clock info. However in
> U-Boot booting flow, I2C is not initialized when get_clocks() is
> called and thus it couldn't get correct value of the clocks.
> So the configuarable clock is only supported by non-QSPI boot.
> 
> Signed-off-by: Gong Qianyu 
> ---
>  include/configs/ls1043aqds.h | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
> index 158cf02..93671f0 100644
> --- a/include/configs/ls1043aqds.h
> +++ b/include/configs/ls1043aqds.h
> @@ -29,8 +29,13 @@ unsigned long get_board_sys_clk(void);
>  unsigned long get_board_ddr_clk(void);
>  #endif
>  
> +#if defined(CONFIG_QSPI_BOOT) || (CONFIG_SD_BOOT_QSPI)
>  #define CONFIG_SYS_CLK_FREQ  1
>  #define CONFIG_DDR_CLK_FREQ  1
> +#else
> +#define CONFIG_SYS_CLK_FREQ  get_board_sys_clk()
> +#define CONFIG_DDR_CLK_FREQ  get_board_ddr_clk()
> +#endif
>  
>  #define CONFIG_SKIP_LOWLEVEL_INIT
>  
> 
Qianyu,

Please work with Yuan Yao on qixis access. We may have a solution to get the
clocks on QSPI boot.

York
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Re: [U-Boot] [PATCH v4 04/14] SECURE BOOT: Add Secure Boot support on ls2080aqds/rdb

[york sun]

Please squash your patch "[PATCH] MAINTAINERS : Add entry for ls2080/5 SECURE
BOOT defconfigs" withi this one.

On 02/08/2016 09:27 PM, Saksham Jain wrote:
> Following changes have been made to enable secure boot:
> 1) Sec_init has been called in starting to initialize SEC Block (CAAM)
> which will be used for Secure Boot validation later for both ls2080a qds
> and rdb
> 2) 64Bit address in ESBC Header has been enabled as this SoC is based on
> armv8
> 3) Secure Boot defconfigs created for boards (NOR Boot).

Suggest to rewrite this commit message. You don't have to itemize the changes.
Keeping it in simply paragraph looks better.

York

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Re: [U-Boot] [PATCH] sunxi: Fix gmac not working due to cpu_eth_init no longer being called

[Hans de Goede]

Hi,

On 17-03-16 14:21, Ian Campbell wrote:

On Thu, 2016-03-17 at 14:02 +0100, Hans de Goede wrote:

cpu_eth_init is no longer called for dm enabled eth drivers, this
was causing the sunxi gmac eth controller to no longer work in u-
boot.

This commit fixes this by moving the gpio setup to gpio_init() and by
calling the clock, reset and pinmux setup function from s_init().

Note that the mdelay is dropped as the phy gets enabled much earlier
now, so it is no longer needed.


Everything is DM_ETH based now, right? Which is why this final hunk is
OK?


Correct, we only do DM for eth in sunxi now, we try to do only DM everywhere.

But we still have a bunch of things we need to convert, like i2c which
has dm support in the core now I believe, patches welcome :)

Regards,

Hans





[...]
@@ -79,16 +79,4 @@ int sunxi_gmac_initialize(bd_t *bis)
for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
  #endif
-
-#ifdef CONFIG_DM_ETH
-   return 0;
-#else
-# ifdef CONFIG_RGMII
-   return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
-# elif defined CONFIG_GMII
-   return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII);
-# else
-   return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
-# endif
-#endif
  }

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[U-Boot] [PATCH 09/14] mkimage: Fix error path in fit_extract_data()

[Simon Glass]

The 'fdt' variable is not unmapped in all error cases. Fix this.

Reported-by: Coverity (CID: 138493)

Signed-off-by: Simon Glass 
---

 tools/fit_image.c | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/tools/fit_image.c b/tools/fit_image.c
index 8d58370..bfb43b2 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -385,7 +385,7 @@ static int fit_extract_data(struct image_tool_params 
*params, const char *fname)
buf = malloc(fit_size);
if (!buf) {
ret = -ENOMEM;
-   goto err;
+   goto err_munmap;
}
buf_ptr = 0;
 
@@ -393,7 +393,7 @@ static int fit_extract_data(struct image_tool_params 
*params, const char *fname)
if (images < 0) {
debug("%s: Cannot find /images node: %d\n", __func__, images);
ret = -EINVAL;
-   goto err;
+   goto err_munmap;
}
 
for (node = fdt_first_subnode(fdt, images);
@@ -411,7 +411,7 @@ static int fit_extract_data(struct image_tool_params 
*params, const char *fname)
ret = fdt_delprop(fdt, node, "data");
if (ret) {
ret = -EPERM;
-   goto err;
+   goto err_munmap;
}
fdt_setprop_u32(fdt, node, "data-offset", buf_ptr);
fdt_setprop_u32(fdt, node, "data-size", len);
@@ -446,8 +446,11 @@ static int fit_extract_data(struct image_tool_params 
*params, const char *fname)
ret = -EIO;
goto err;
}
-   ret = 0;
+   close(fd);
+   return 0;
 
+err_munmap:
+   munmap(fdt, sbuf.st_size);
 err:
close(fd);
return ret;
-- 
2.7.0.rc3.207.g0ac5344

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Re: [U-Boot] [PATCH] sunxi: Add support for Cubietruck Plus

[Dennis Gilmore]

Hans,

What is the status of this patch?

Dennis

On Wednesday, January 27, 2016 4:34:44 PM CDT Chen-Yu Tsai wrote:
> Cubietruck Plus is a A83T/H8 based development board. The board has
> standard DDR3 SDRAM, AXP818 PMIC/codec, SD/MMC, eMMC, USB 2.0 host
> via HSIC USB Hub, USB OTG, SATA via USB bridge, gigabit ethernet,
> WiFi, headphone out / mic in, and various GPIO headers.
> 
> The board also has an EEPROM on i2c0 which holds the MAC address.
> 
> DLDO3 and DLDO4 provide power to the EMAC pins and PHY. Pin PA20
> is connected to the reset control of the PHY. EMAC is not actually
> supported yet.
> 
> The DTS is the same as the one already in the kernel.
> 
> Signed-off-by: Chen-Yu Tsai 
> ---
>  arch/arm/dts/Makefile   |  1 +
>  arch/arm/dts/sun8i-a83t-cubietruck-plus.dts | 65
> + configs/Cubietruck_plus_defconfig   |
> 18 
>  3 files changed, 84 insertions(+)
>  create mode 100644 arch/arm/dts/sun8i-a83t-cubietruck-plus.dts
>  create mode 100644 configs/Cubietruck_plus_defconfig
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 1c7d359..e338db5 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -184,6 +184,7 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \
>   sun8i-a33-sinlinx-sina33.dtb
>  dtb-$(CONFIG_MACH_SUN8I_A83T) += \
>   sun8i-a83t-allwinner-h8homlet-v2.dtb \
> + sun8i-a83t-cubietruck-plus.dtb \
>   sun8i-a83t-sinovoip-bpi-m3.dtb
>  dtb-$(CONFIG_MACH_SUN8I_H3) += \
>   sun8i-h3-orangepi-pc.dtb \
> diff --git a/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts
> b/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts new file mode 100644
> index 000..88b1e09
> --- /dev/null
> +++ b/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts
> @@ -0,0 +1,65 @@
> +/*
> + * Copyright 2015 Chen-Yu Tsai
> + *
> + * Chen-Yu Tsai 
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "sun8i-a83t.dtsi"
> +
> +/ {
> + model = "Cubietech Cubietruck Plus";
> + compatible = "cubietech,cubietruck-plus", "allwinner,sun8i-a83t";
> +
> + aliases {
> + serial0 = 
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins_b>;
> + status = "okay";
> +};
> diff --git a/configs/Cubietruck_plus_defconfig
> b/configs/Cubietruck_plus_defconfig new file mode 100644
> index 000..bb0b336
> --- /dev/null
> +++ b/configs/Cubietruck_plus_defconfig
> @@ -0,0 +1,18 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_SUNXI=y
> +CONFIG_MACH_SUN8I_A83T=y
> +CONFIG_DRAM_CLK=672
> +CONFIG_DRAM_ZQ=15355
> +CONFIG_DRAM_ODT_EN=y
> +CONFIG_MMC0_CD_PIN="PF6"
> +CONFIG_I2C0_ENABLE=y
> +CONFIG_AXP_GPIO=y
> +CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus"
> +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> +CONFIG_SPL=y
> +CONFIG_SYS_EXTRA_OPTIONS="RGMII,MACPWR=SUNXI_GPD(20)"
> +# CONFIG_CMD_IMLS is not 

[U-Boot] [PATCH 1/3] Fix typo in chosen parameter in vf610-twr.dts

[Alexander Merkle]

Fix typo "choosen" instead of "chosen" in vf610-twr.dts.
Fixes boot process and terminal output for Vybrid series.

Signed-off-by: Alexander Merkle 
---

 arch/arm/dts/vf610-twr.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/vf610-twr.dts b/arch/arm/dts/vf610-twr.dts
index a4ccbcb..237aa8d 100644
--- a/arch/arm/dts/vf610-twr.dts
+++ b/arch/arm/dts/vf610-twr.dts
@@ -11,7 +11,7 @@
model = "VF610 Tower Board";
compatible = "fsl,vf610-twr", "fsl,vf610";
 
-   choosen {
+   chosen {
stdout-path = 
};
 
-- 
2.7.0

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Re: [U-Boot] [PATCH 4/7] board: ti: DRA72: revC evm: Update sdram timing configuration for SR2.0

[Tom Rini]

On Tue, Mar 15, 2016 at 06:09:14PM -0500, Nishanth Menon wrote:

> From: Ravi Babu 
> 
> DDR configuration has changes from SR1.1 based Rev-A/B version of evm
> to the SR2.0 based Rev C of the EVM. Rev C evm now uses the higher
> density MT41K512M8RH-125-AAT:E (IT) which is of size 2GB.
> 
> Update the DDR configuration based on data from EMIF configuration
> tool 1.1.1. NOTE: we use eeprom information (ram_size) to update the
> configuration.
> 
> Tested-by: Vishal Mahaveer 
> Signed-off-by: Ravi Babu 
> Signed-off-by: Nishanth Menon 

Reviewed-by: Tom Rini 

-- 
Tom


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[U-Boot] [PATCH 6/6] i2c: designware_i2c: Add support for PCI(e) based I2C cores (x86)

[Stefan Roese]

This patch adds support for the PCI(e) based I2C cores. Which can be
found for example on the Intel Bay Trail SoC. It has 7 I2C controllers
implemented as PCI devices.

This patch also adds the fixed values for the timing registers for
BayTrail which are taken from the Linux designware I2C driver.

Signed-off-by: Stefan Roese 
Cc: Simon Glass 
Cc: Bin Meng 
Cc: Marek Vasut 
Cc: Heiko Schocher 
---
 drivers/i2c/designware_i2c.c | 111 +++
 1 file changed, 101 insertions(+), 10 deletions(-)

diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index 4e5340d..f7f2eba 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -8,11 +8,32 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include "designware_i2c.h"
 
+struct dw_scl_sda_cfg {
+   u32 ss_hcnt;
+   u32 fs_hcnt;
+   u32 ss_lcnt;
+   u32 fs_lcnt;
+   u32 sda_hold;
+};
+
+#ifdef CONFIG_X86
+/* BayTrail HCNT/LCNT/SDA hold time */
+static struct dw_scl_sda_cfg byt_config = {
+   .ss_hcnt = 0x200,
+   .fs_hcnt = 0x55,
+   .ss_lcnt = 0x200,
+   .fs_lcnt = 0x99,
+   .sda_hold = 0x6,
+};
+#endif
+
 struct dw_i2c {
struct i2c_regs *regs;
+   struct dw_scl_sda_cfg *scl_sda_cfg;
 };
 
 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
@@ -42,6 +63,7 @@ static void dw_i2c_enable(struct i2c_regs *i2c_base, bool 
enable)
  * Set the i2c speed.
  */
 static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
+  struct dw_scl_sda_cfg *scl_sda_cfg,
   unsigned int speed)
 {
unsigned int cntl;
@@ -61,34 +83,55 @@ static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs 
*i2c_base,
cntl = (readl(_base->ic_con) & (~IC_CON_SPD_MSK));
 
switch (i2c_spd) {
+#ifndef CONFIG_X86 /* No High-speed for BayTrail yet */
case IC_SPEED_MODE_MAX:
-   cntl |= IC_CON_SPD_HS;
-   hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
+   cntl |= IC_CON_SPD_SS;
+   if (scl_sda_cfg) {
+   hcnt = scl_sda_cfg->fs_hcnt;
+   lcnt = scl_sda_cfg->fs_lcnt;
+   } else {
+   hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
+   lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
+   }
writel(hcnt, _base->ic_hs_scl_hcnt);
-   lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
writel(lcnt, _base->ic_hs_scl_lcnt);
break;
+#endif
 
case IC_SPEED_MODE_STANDARD:
cntl |= IC_CON_SPD_SS;
-   hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
+   if (scl_sda_cfg) {
+   hcnt = scl_sda_cfg->ss_hcnt;
+   lcnt = scl_sda_cfg->ss_lcnt;
+   } else {
+   hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
+   lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
+   }
writel(hcnt, _base->ic_ss_scl_hcnt);
-   lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
writel(lcnt, _base->ic_ss_scl_lcnt);
break;
 
case IC_SPEED_MODE_FAST:
default:
cntl |= IC_CON_SPD_FS;
-   hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
+   if (scl_sda_cfg) {
+   hcnt = scl_sda_cfg->fs_hcnt;
+   lcnt = scl_sda_cfg->fs_lcnt;
+   } else {
+   hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
+   lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
+   }
writel(hcnt, _base->ic_fs_scl_hcnt);
-   lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
writel(lcnt, _base->ic_fs_scl_lcnt);
break;
}
 
writel(cntl, _base->ic_con);
 
+   /* Configure SDA Hold Time if required */
+   if (scl_sda_cfg)
+   writel(scl_sda_cfg->sda_hold, _base->ic_sda_hold);
+
/* Enable back i2c now speed set */
dw_i2c_enable(i2c_base, 1);
 
@@ -315,7 +358,7 @@ static void __dw_i2c_init(struct i2c_regs *i2c_base, int 
speed, int slaveaddr)
writel(IC_TX_TL, _base->ic_tx_tl);
writel(IC_STOP_DET, _base->ic_intr_mask);
 #ifndef CONFIG_DM_I2C
-   __dw_i2c_set_bus_speed(i2c_base, speed);
+   __dw_i2c_set_bus_speed(i2c_base, NULL, speed);
writel(slaveaddr, _base->ic_sar);
 #endif
 
@@ -356,7 +399,7 @@ static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter 
*adap,
 unsigned int speed)
 {
adap->speed = speed;
-   return 

[U-Boot] [PATCH] dm: gpio: pca953x: introduce driver model support for pca953x

[Peng Fan]

Introduce a new driver that supports driver model for pca953x.
The pca953x chips are used as I2C I/O expanders.
This driver is designed to support the following chips:
"
4 bits: pca9536, pca9537
8 bits: max7310, max7315, pca6107, pca9534, pca9538, pca9554,
pca9556, pca9557, pca9574, tca6408, xra1202
16 bits: max7312, max7313, pca9535, pca9539, pca9555, pca9575,
 tca6416
24 bits: tca6424
40 bits: pca9505, pca9698
"
But for now this driver only supports max 24 bits and pca953x compatible
chips. pca957x compatible chips are not supported now.
These can be addressed when we need to add such support for the different
chips.
This driver has been tested on i.MX6 SoloX Sabreauto board with max7310
i2c expander using gpio command as following:

=>gpio status -a
Bank gpio@48:
gpio@480: input: 1 [ ]
=> gpio clear gpio@480
gpio: pin gpio@480 (gpio 224) value is 0
=> gpio status -a
Bank gpio@48:
gpio@480: output: 0 [ ]

=> dm tree:
 i2c [   ]|   |   `-- i2c@021a8000
 gpio[   ]|   |   |-- gpio@30
 gpio[   ]|   |   `-- gpio@32

Signed-off-by: Peng Fan 
Cc: Simon Glass 
Cc: Masahiro Yamada 
Cc: Wenyou Yang 
Cc: Daniel Schwierzeck 
Cc: Purna Chandra Mandal 
Cc: Thomas Chou 
Cc: Bhuvanchandra DV 
Cc: Andrea Scian 
Cc: Michal Simek 
Cc: Stefano Babic 
Cc: Fabio Estevam 
---
 drivers/gpio/Kconfig|  23 +++
 drivers/gpio/Makefile   |   2 +
 drivers/gpio/pca953x_gpio.c | 349 
 3 files changed, 374 insertions(+)
 create mode 100644 drivers/gpio/pca953x_gpio.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 94fabb9..51658f1 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -96,4 +96,27 @@ config PIC32_GPIO
help
  Say yes here to support Microchip PIC32 GPIOs.
 
+config DM_PCA953X
+   bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports"
+   depends on DM_GPIO
+   help
+ Say yes here to provide access to several register-oriented
+ SMBus I/O expanders, made mostly by NXP or TI.  Compatible
+ models include:
+
+ 4 bits:   pca9536, pca9537
+
+ 8 bits:   max7310, max7315, pca6107, pca9534, pca9538, pca9554,
+   pca9556, pca9557, pca9574, tca6408, xra1202
+
+ 16 bits:  max7312, max7313, pca9535, pca9539, pca9555, pca9575,
+   tca6416
+
+ 24 bits:  tca6424
+
+ 40 bits:  pca9505, pca9698
+
+ Now, max 24 bits chips and PCA953X compatible chips are
+ supported
+
 endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ca8c487..bfc67d2 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -11,6 +11,8 @@ obj-$(CONFIG_AXP_GPIO)+= axp_gpio.o
 endif
 obj-$(CONFIG_DM_GPIO)  += gpio-uclass.o
 
+obj-$(CONFIG_DM_PCA953X)   += pca953x_gpio.o
+
 obj-$(CONFIG_AT91_GPIO)+= at91_gpio.o
 obj-$(CONFIG_ATMEL_PIO4)   += atmel_pio4.o
 obj-$(CONFIG_INTEL_ICH6_GPIO)  += intel_ich6_gpio.o
diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
new file mode 100644
index 000..6b67b07
--- /dev/null
+++ b/drivers/gpio/pca953x_gpio.c
@@ -0,0 +1,349 @@
+/*
+ * Take linux kernel driver drivers/gpio/gpio-pca953x.c for reference.
+ *
+ * Copyright (C) 2016 Peng Fan 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+
+/*
+ * Note:
+ * The driver's compatible table is borrowed from Linux Kernel,
+ * but now max supported gpio pins is 24 and only PCA953X_TYPE
+ * is supported. PCA957X_TYPE is not supported now.
+ * Also the Polarity Inversion feature is not supported now.
+ *
+ * TODO:
+ * 1. Support PCA957X_TYPE
+ * 2. Support max 40 gpio pins
+ * 3. Support Plolarity Inversion
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PCA953X_INPUT   0
+#define PCA953X_OUTPUT  1
+#define PCA953X_INVERT  2
+#define PCA953X_DIRECTION   3
+
+#define PCA_GPIO_MASK   0x00FF
+#define PCA_INT 0x0100
+#define PCA953X_TYPE0x1000
+#define PCA957X_TYPE0x2000
+#define PCA_TYPE_MASK   0xF000
+#define PCA_CHIP_TYPE(x)((x) & PCA_TYPE_MASK)
+
+enum {
+   PCA953X_DIRECTION_IN,
+   PCA953X_DIRECTION_OUT,
+};
+
+#define MAX_BANK 3
+#define BANK_SZ 8
+
+/*
+ * struct pca953x_info - Data for pca953x
+ *
+ * @dev: udevice structure for the device
+ * @addr: i2c slave address
+ * @invert: Polarity inversion or not
+ * @gpio_count: the number of gpio pins that the device supports
+ * @chip_type: indicate the chip 

[U-Boot] [PATCH v3 09/10] x86: Add missing pci.h header in me_common.h

[Simon Glass]

This uses PCI so should include the header.

Signed-off-by: Simon Glass 
---

Changes in v3:
- Add new patch top include missing pci.h header in me_common.c

Changes in v2: None

 arch/x86/include/asm/me_common.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/me_common.h b/arch/x86/include/asm/me_common.h
index 7089117..2e2251c 100644
--- a/arch/x86/include/asm/me_common.h
+++ b/arch/x86/include/asm/me_common.h
@@ -15,6 +15,7 @@
 
 #include 
 #include 
+#include 
 
 #define MCHBAR_PEI_VERSION 0x5034
 
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH 1/4] rework board config files

[Cyrille Pitchen]

---
 board/atmel/sama5d2_xplained/Kconfig| 14 ++
 board/atmel/sama5d2_xplained/sama5d2_xplained.c | 14 +-
 drivers/mmc/Kconfig |  6 ++
 include/configs/at91-sama5_common.h | 10 ++
 include/configs/sama5d2_xplained.h  | 15 ++-
 5 files changed, 41 insertions(+), 18 deletions(-)

diff --git a/board/atmel/sama5d2_xplained/Kconfig 
b/board/atmel/sama5d2_xplained/Kconfig
index 55712e97454b..d4106b90f599 100644
--- a/board/atmel/sama5d2_xplained/Kconfig
+++ b/board/atmel/sama5d2_xplained/Kconfig
@@ -12,4 +12,18 @@ config SYS_SOC
 config SYS_CONFIG_NAME
default "sama5d2_xplained"
 
+config ATMEL_SPI0
+   bool "SPI0"
+   default y
+
+config ATMEL_SDHCI0
+   bool "SDHCI0"
+   select ATMEL_SDHCI
+   default y
+
+config ATMEL_SDHCI1
+   bool "SDHCI1"
+   select ATMEL_SDHCI
+   default y
+
 endif
diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c 
b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
index 10edf28a9bd6..4dd83e5e991f 100644
--- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c
+++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
@@ -25,6 +25,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifndef CONFIG_DM_SPI
 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 {
return bus == 0 && cs == 0;
@@ -39,7 +40,9 @@ void spi_cs_deactivate(struct spi_slave *slave)
 {
atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
 }
+#endif
 
+#ifdef CONFIG_ATMEL_SPI0
 static void board_spi0_hw_init(void)
 {
atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0);
@@ -50,6 +53,7 @@ static void board_spi0_hw_init(void)
 
at91_periph_clk_enable(ATMEL_ID_SPI0);
 }
+#endif
 
 static void board_usb_hw_init(void)
 {
@@ -157,6 +161,7 @@ static void board_gmac_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_GMAC);
 }
 
+#ifdef CONFIG_ATMEL_SDHCI0
 static void board_sdhci0_hw_init(void)
 {
atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0);  /* SDMMC0_CK */
@@ -176,7 +181,9 @@ static void board_sdhci0_hw_init(void)
at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0,
 GCK_CSS_PLLA_CLK, 1);
 }
+#endif
 
+#ifdef CONFIG_ATMEL_SDHCI1
 static void board_sdhci1_hw_init(void)
 {
atmel_pio4_set_e_periph(AT91_PIO_PORTA, 18, 0); /* SDMMC1_DAT0 */
@@ -192,6 +199,7 @@ static void board_sdhci1_hw_init(void)
at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1,
 GCK_CSS_PLLA_CLK, 1);
 }
+#endif
 
 int board_mmc_init(bd_t *bis)
 {
@@ -230,17 +238,15 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-#ifdef CONFIG_ATMEL_SPI
+#ifdef CONFIG_ATMEL_SPI0
board_spi0_hw_init();
 #endif
-#ifdef CONFIG_ATMEL_SDHCI
 #ifdef CONFIG_ATMEL_SDHCI0
board_sdhci0_hw_init();
 #endif
 #ifdef CONFIG_ATMEL_SDHCI1
board_sdhci1_hw_init();
 #endif
-#endif
 #ifdef CONFIG_MACB
board_gmac_hw_init();
 #endif
@@ -289,14 +295,12 @@ void spl_board_init(void)
 #ifdef CONFIG_SYS_USE_SERIALFLASH
board_spi0_hw_init();
 #endif
-#ifdef CONFIG_ATMEL_SDHCI
 #ifdef CONFIG_ATMEL_SDHCI0
board_sdhci0_hw_init();
 #endif
 #ifdef CONFIG_ATMEL_SDHCI1
board_sdhci1_hw_init();
 #endif
-#endif
 }
 
 static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index dc8532fe9373..b3d085119ac8 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -49,4 +49,10 @@ config MMC_UNIPHIER
help
  This selects support for the SD/MMC Host Controller on UniPhier SoCs.
 
+config ATMEL_SDHCI
+   bool "Atmel SD Host Controller Interface"
+   depends on ARCH_AT91
+   help
+ This enables support for the Atmel SD/eMMC controller
+
 endmenu
diff --git a/include/configs/at91-sama5_common.h 
b/include/configs/at91-sama5_common.h
index 6525b5c3701e..0297fd781dc6 100644
--- a/include/configs/at91-sama5_common.h
+++ b/include/configs/at91-sama5_common.h
@@ -104,6 +104,16 @@
"sf read 0x2100 0x6 0xc000; "   
\
"sf read 0x2200 0x6c000 0x394000; " 
\
"bootz 0x2200 - 0x2100"
+#elif CONFIG_SYS_USE_QSPIFLASH
+/* u-boot env in QSPI flash, by default is bus 0 and cs 0  */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET  0x1
+#define CONFIG_ENV_SIZE0x1
+#define CONFIG_ENV_SECT_SIZE   0x1
+#define CONFIG_BOOTCOMMAND "sf probe 0; "  
\
+   "sf read 0x2100 0x6 0x1; "  
\
+   "sf read 0x2200 0x7 0x50; " 
\
+   "bootz 0x2200 - 0x2100"
 #endif
 
 #endif
diff 

[U-Boot] [PATCH 3/6] i2c: designware_i2c: Integrate set_speed() into dw_i2c_set_bus_speed()

[Stefan Roese]

Integrating set_speed() into dw_i2c_set_bus_speed() will make the
conversion to DM easier for this driver.

Signed-off-by: Stefan Roese 
Cc: Simon Glass 
Cc: Bin Meng 
Cc: Marek Vasut 
Cc: Heiko Schocher 
---
 drivers/i2c/designware_i2c.c | 37 +
 1 file changed, 13 insertions(+), 24 deletions(-)

diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index c8ea520..508dac9 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -55,16 +55,25 @@ static void dw_i2c_enable(struct i2c_regs *i2c_base, bool 
enable)
 }
 
 /*
- * set_speed - Set the i2c speed mode (standard, high, fast)
- * @i2c_spd:   required i2c speed mode
+ * i2c_set_bus_speed - Set the i2c speed
+ * @speed: required i2c speed
  *
- * Set the i2c speed mode (standard, high, fast)
+ * Set the i2c speed.
  */
-static void set_speed(struct i2c_adapter *adap, int i2c_spd)
+static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
+unsigned int speed)
 {
struct i2c_regs *i2c_base = i2c_get_base(adap);
unsigned int cntl;
unsigned int hcnt, lcnt;
+   int i2c_spd;
+
+   if (speed >= I2C_MAX_SPEED)
+   i2c_spd = IC_SPEED_MODE_MAX;
+   else if (speed >= I2C_FAST_SPEED)
+   i2c_spd = IC_SPEED_MODE_FAST;
+   else
+   i2c_spd = IC_SPEED_MODE_STANDARD;
 
/* to set speed cltr must be disabled */
dw_i2c_enable(i2c_base, 0);
@@ -102,27 +111,7 @@ static void set_speed(struct i2c_adapter *adap, int 
i2c_spd)
 
/* Enable back i2c now speed set */
dw_i2c_enable(i2c_base, 1);
-}
-
-/*
- * i2c_set_bus_speed - Set the i2c speed
- * @speed: required i2c speed
- *
- * Set the i2c speed.
- */
-static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
-unsigned int speed)
-{
-   int i2c_spd;
-
-   if (speed >= I2C_MAX_SPEED)
-   i2c_spd = IC_SPEED_MODE_MAX;
-   else if (speed >= I2C_FAST_SPEED)
-   i2c_spd = IC_SPEED_MODE_FAST;
-   else
-   i2c_spd = IC_SPEED_MODE_STANDARD;
 
-   set_speed(adap, i2c_spd);
adap->speed = speed;
 
return 0;
-- 
2.7.3

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Re: [U-Boot] spl_nor: fix warning when compiled for 64bit target

[Tom Rini]

On Mon, Feb 29, 2016 at 08:50:34PM +0900, Masahiro Yamada wrote:

> Fix "warning: cast to pointer from integer of different size".
> 
> Signed-off-by: Masahiro Yamada 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [U-Boot, 10/10] keystone2: env: Set mmc as default boot for k2g-evm

[Tom Rini]

On Wed, Mar 09, 2016 at 03:39:39PM +0530, Lokesh Vutla wrote:

> From: Yan Liu 
> 
> For k2l, k2e and k2hk, ubi is set to default boot in uboot
> environment settings; while for k2g, mmc should be the
> default boot. This patch is to set mmc as default for k2g-evm
> 
> Signed-off-by: Yan Liu 
> Signed-off-by: Lokesh Vutla 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH v4 3/4] drivers:usb:common:fsl-dt-fixup: Add device-tree fixup support for xhci controller

[Sriram Dash]

>-Original Message-
>From: Marek Vasut [mailto:ma...@denx.de]
>Sent: Friday, March 11, 2016 10:14 PM
>To: Sriram Dash ; u-boot@lists.denx.de
>Cc: york sun ; Ramneek Mehresh
>; Rajesh Bhagat 
>Subject: Re: [PATCH v4 3/4] drivers:usb:common:fsl-dt-fixup: Add device-tree 
>fixup
>support for xhci controller
>
>On 03/11/2016 07:26 AM, Sriram Dash wrote:
>> Enables usb device-tree fixup code to incorporate xhci controller
>>
>> Signed-off-by: Ramneek Mehresh 
>> Signed-off-by: Sriram Dash 
>> ---
>> Changes in v4:
>>   - Use a terminating entry in the array for getting node type for
>> controller Changes in v3:
>>   - Modify the Makefile to remove comparison
>>   - Put the supported controllers in array and checking from array
>> Changes in v2:
>>   - Remove the #defines from the patch and adding controller support
>>
>>  drivers/usb/common/Makefile   |  1 +
>>  drivers/usb/common/fsl-dt-fixup.c | 44 
>> +++
>>  include/fdt_support.h |  4 ++--
>>  3 files changed, 25 insertions(+), 24 deletions(-)
>>
>> diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile
>> index a38ee4a..2f3d43d 100644
>> --- a/drivers/usb/common/Makefile
>> +++ b/drivers/usb/common/Makefile
>> @@ -4,3 +4,4 @@
>>  #
>>
>>  obj-$(CONFIG_USB_EHCI_FSL) += fsl-dt-fixup.o
>> +obj-$(CONFIG_USB_XHCI_FSL) += fsl-dt-fixup.o
>> diff --git a/drivers/usb/common/fsl-dt-fixup.c
>> b/drivers/usb/common/fsl-dt-fixup.c
>> index 64e20d8..b574127 100644
>> --- a/drivers/usb/common/fsl-dt-fixup.c
>> +++ b/drivers/usb/common/fsl-dt-fixup.c
>> @@ -19,15 +19,21 @@
>>  #define CONFIG_USB_MAX_CONTROLLER_COUNT 1  #endif
>>
>> -static const char *fdt_usb_get_node_type(void *blob, int
>> start_offset,
>> +static char *fdt_usb_get_node_type(void *blob, int start_offset,
>>   int *node_offset);
>>
>> +char compat_usb_fsl[] = {
>
>static const
>

Will take care in v5.

>> +"fsl-usb2-mph" "\0"
>> +"fsl-usb2-dr" "\0"
>> +"snps,dwc3" "\0"
>> +};
>> +
>>  static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
>> const char *phy_type, int start_offset)  
>> {
>>  const char *prop_mode = "dr_mode";
>>  const char *prop_type = "phy_type";
>> -const char *node_type = NULL;
>> +char *node_type = NULL;
>>  int node_offset;
>>  int err;
>>
>> @@ -54,29 +60,23 @@ static int fdt_fixup_usb_mode_phy_type(void *blob,
>const char *mode,
>>  return node_offset;
>>  }
>[...]
>
>
>--
>Best regards,
>Marek Vasut
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Re: [U-Boot] [PATCH 1/6] ARM: keystone2: Split monitor code / command code

[Albert ARIBAUD]

Hello Tom,

On Wed, 16 Mar 2016 11:03:03 -0400, Tom Rini  wrote:
> When we switch to including all linker lists in U-Boot it is important
> to not include commands as that may lead to link errors due to other
> things we have already discarded.  In this case, we split the code for
> supporting the monitor out from the code for loading it.

Not sure I'm understanding this commit message. Can you clarify?

Amicalement,
-- 
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[U-Boot] [PATCH 02/13] ARM: uniphier: remove commented out define

[Masahiro Yamada]

This TODO is no longer useful.  CONFIG_SYS_NS16550_SERIAL is just
ignored on DM serial.

If one wants to use the 16550A UART device on the UniPhier Micro
Support Card, it can be enabled by CONFIG_SYS_NS16550 via Kconfig.
Please notice CONFIG_SPL_OF_TRANSLATE must be enabled as well and
the device tree must be treaked in order to use the NS16550 serial
on SPL.

Signed-off-by: Masahiro Yamada 
---

 include/configs/uniphier.h | 5 -
 1 file changed, 5 deletions(-)

diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 1a74489..9c9e3b8 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -18,11 +18,6 @@
 #define CONFIG_SYS_NS16550_REG_SIZE-2
 #endif
 
-/* TODO: move to Kconfig and device tree */
-#if 0
-#define CONFIG_SYS_NS16550_SERIAL
-#endif
-
 #define CONFIG_SMC911X
 
 /* dummy: referenced by examples/standalone/smc911x_eeprom.c */
-- 
1.9.1

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Re: [U-Boot] [PATCH] Add CONFIG_GMAC_TX_DELAY=4 for OlinuXino Lime2

[Michael Haas]

Hello all,


After the board locked up, I am now working exclusively from within
u-boot. Occasionally, gbit will work well. At other times, it will
appear to work well but the kernel won't boot. And sometimes,
downloading a  kernel will just time-out.

A reset is often enough to get a behavior change. In my earlier post, I
noted that it's hard for me now to get broken gbit: I've since then also
had spurs where five resets in a row did not work.

On 03/17/2016 11:52 AM, Hans de Goede wrote:
> There are 3 things which would be interesting to save and compare
> with a boot which does have the problem:
>

> ./mmio-dump 0x1c20164
>
>

I have used the u-boot 'md' command here. Between a completely broken
(timeouts) and working (at least a finished download), there is no change:

Working:

=> md 0x1c20164
01c20164: 0c06   


Broken:

 md 0x1c20164
01c20164: 0c06   


>
> 2) The pmic settings for various ldo-s, etc. as root run:
>
> i2cdump -f -y 0 0x34
>
>

I used the i2c md command here to get several dumps:

Working 1:
=> i2c md 0x34 0 0xff
: c1 10 00 41 00 00 00 00 00 00 00 00 00 00 00 00...A
0010: 01 00 17 00 00 00 00 00 00 00 00 00 00 00 00 00
0020: 00 00 00 1c 00 00 00 16 cf 54 00 00 00 00 00 00.T..
0030: 60 03 42 c9 45 22 9d 08 a5 1f 68 5f fc 16 00 00`.B.E"h_
0040: 00 00 00 00 00 00 00 00 40 40 00 00 00 00 00 00@@..
0050: 09 0a 00 00 00 00 00 00 00 00 00 00 00 00 6d 0f..m.
0060: db 07 3e 08 00 00 00 00 00 00 00 00 00 00 00 00..>.
0070: 00 00 00 00 00 00 00 00 1a 03 00 00 00 00 db 08
0080: e0 fd 83 80 32 00 ff 00 00 00 00 00 00 00 00 212..!
0090: 07 a5 07 07 00 02 00 00 00 00 00 00 00 00 00 00
00a0: 00 00 00 00 00 00 00 00 08 00 00 00 00 00 db 06
00b0: 00 00 00 00 00 00 00 00 00 7f 00 ba 00 00 00 00
00c0: 01 01 02 04 07 0d 10 1a 24 2e 35 3d 49 54 5c 63$.5=IT\c
00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00f0: 41 00 80 03 00 00 00 00 00 00 00 00 00 00 00A..


Working 2:

=> i2c md 0x34 0 0xff
: c1 10 00 41 00 00 00 00 00 00 00 00 00 00 00 00...A
0010: 01 00 17 00 00 00 00 00 00 00 00 00 00 00 00 00
0020: 00 00 00 1c 00 00 00 16 cf 54 00 00 00 00 00 00.T..
0030: 60 03 42 c9 45 22 9d 08 a5 1f 68 5f fc 16 00 00`.B.E"h_
0040: 00 00 00 00 00 00 00 00 40 40 00 00 00 00 00 00@@..
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6d 0f..m.
0060: db 0c 3e 08 00 00 00 00 00 00 00 00 00 00 00 00..>.
0070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 db 08
0080: e0 fd 83 80 32 00 ff 00 00 00 00 00 00 00 00 212..!
0090: 07 a5 07 07 00 02 00 00 00 00 00 00 00 00 00 00
00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 dc 00
00b0: 00 00 00 00 00 00 00 00 00 7f 00 ba 00 00 00 00
00c0: 01 01 02 04 07 0d 10 1a 24 2e 35 3d 49 54 5c 63$.5=IT\c
00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00f0: 41 00 80 03 00 00 00 00 00 00 00 00 00 00 00A..


Broken 1:

=> i2c md 0x34 0 0xff
: c1 10 00 41 00 00 00 00 00 00 00 00 00 00 00 00...A
0010: 01 00 17 00 00 00 00 00 00 00 00 00 00 00 00 00
0020: 00 00 00 1c 00 00 00 16 cf 54 00 00 00 00 00 00.T..
0030: 60 03 42 c9 45 22 9d 08 a5 1f 68 5f fc 16 00 00`.B.E"h_
0040: 00 00 00 00 00 00 00 00 40 40 00 00 00 00 00 00@@..
0050: 22 06 00 00 00 00 00 00 00 00 00 00 00 00 6e 04".n.
0060: db 0a 3e 08 00 00 00 00 00 00 00 00 00 00 00 00..>.
0070: 00 00 00 00 00 00 00 00 03 08 00 00 00 00 db 08
0080: e0 fd 83 80 32 00 ff 00 00 00 00 00 00 00 00 212..!
0090: 07 a5 07 07 00 02 00 00 00 00 00 00 00 00 00 00
00a0: 00 00 00 00 00 00 00 00 20 08 00 00 00 00 db 09 ...
00b0: 00 00 00 00 00 00 00 00 00 7f 00 ba 00 00 00 00
00c0: 01 01 02 04 07 0d 10 1a 24 2e 35 3d 49 54 5c 63$.5=IT\c
00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00f0: 41 00 80 03 00 00 00 00 00 00 00 00 00 00 00A..

Broken 2:

=> i2c md 0x34 0 0xff
: c1 10 00 41 00 00 00 00 00 00 00 00 00 00 00 00...A
0010: 01 00 17 00 00 00 00 00 00 00 00 00 00 00 00 00
0020: 00 00 00 1c 00 00 00 16 cf 54 00 00 00 00 00 00

Re: [U-Boot] [U-Boot,07/27] omap4: Export jedec sdram timings

[Tom Rini]

On Sat, Feb 27, 2016 at 07:18:55PM +0100, Paul Kocialkowski wrote:

> Individual boards might provide their own emif_get_device_timings function and
> use the jedec timings in their own way, hence those have to be exported.
> 
> Signed-off-by: Paul Kocialkowski 

Applied to u-boot/master, thanks!

-- 
Tom


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[U-Boot] [PATCH 6/6] arm: omap-common: Guard some parts of the code with CONFIG_OMAP44XX/OMAP54XX

[Tom Rini]

On OMAP4 platforms that also need to calculate their DDR settings we are
now getting very close to the linker limit size.  Since OMAP44XX is only
seen with LPDDR2, remove some run time tests for LPDDR2 or DDR3 as we
will know that we don't have it for OMAP44XX.

Cc: Nishanth Menon 
Signed-off-by: Tom Rini 
---
 arch/arm/cpu/armv7/omap-common/emif-common.c |8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c 
b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 697d6e0..9a9c764 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -195,6 +195,7 @@ void emif_update_timings(u32 base, const struct emif_regs 
*regs)
}
 }
 
+#ifndef CONFIG_OMAP44XX
 static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
 {
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@@ -405,6 +406,7 @@ static void ddr3_init(u32 base, const struct emif_regs 
*regs)
else
dra7_ddr3_init(base, regs);
 }
+#endif
 
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
@@ -1178,7 +1180,7 @@ static void do_sdram_init(u32 base)
 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 
/*
-* Initializing the LPDDR2 device can not happen from SDRAM.
+* Initializing the DDR device can not happen from SDRAM.
 * Changing the timing registers in EMIF can happen(going from one
 * OPP to another)
 */
@@ -1186,15 +1188,19 @@ static void do_sdram_init(u32 base)
if (emif_sdram_type(regs->sdram_config) ==
EMIF_SDRAM_TYPE_LPDDR2)
lpddr2_init(base, regs);
+#ifndef CONFIG_OMAP44XX
else
ddr3_init(base, regs);
+#endif
}
+#ifdef CONFIG_OMAP54X
if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
set_lpmode_selfrefresh(base);
emif_reset_phy(base);
omap5_ddr3_leveling(base, regs);
}
+#endif
 
/* Write to the shadow registers */
emif_update_timings(base, regs);
-- 
1.7.9.5

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Re: [U-Boot] [U-Boot, 05/10] am43xx: configs: Enable USB commands for non usb boot also

[Tom Rini]

On Wed, Mar 09, 2016 at 03:39:34PM +0530, Lokesh Vutla wrote:

> From: Mugunthan V N 
> 
> With commit aee119bd70b8 ('am43xx_evm: add usb host boot support') usb
> commands is removed from U-boot second stage and enbaled only on USB
> boot config. Fixing this by enable USB commands for both USB boot and
> in second stage u-boot.
> 
> Signed-off-by: Mugunthan V N 
> Signed-off-by: Lokesh Vutla 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [PATCH 2/2] Fix spelling of "supported/unsupported".

[Peter Griffin]

On Tue, 15 Mar 2016, Vagrant Cascadian wrote:

> Signed-off-by: Vagrant Cascadian 
> ---
> 
>  board/hisilicon/hikey/hikey.c | 2 +-
>  fs/fat/fat_write.c| 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Peter Griffin 
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Re: [U-Boot] [PATCH v8 0/9] add support for atheros ath79 based SOCs

[Marek Vasut]

On 03/16/2016 09:59 AM, Wills Wang wrote:
> These series of patch add support for atheros ath79 based SOCs in u-boot,
> at the present moment it's just available for ar933x and qca953x chip.
> 
> Changes in v8:
> - Use setbits_be32
> - Use lookup-table instead of big switch statement for CPU detection
> - Fix multi-line comment for ar933x
> - Fix multi-line comment for qca953x
> - Remove ath79_serial_write/read
> - Use pinctrl for serial
> - Add Kconfig dependence for serial option
> - Remove ath79_spi_write/read
> - Use pinctrl for spi
> - Add Kconfig dependence for spi option
> - Use dev_get_parent
> - Move board/ath79/ap121 into board/qca/ap121
> - Move SYS_VENDOR into board-level for ap121
> - Move board/ath79/ap143 into board/qca/ap143
> - Move SYS_VENDOR into board-level for ap143

I was almost worried I'll never see a new series, good to have you back
:-) I have been working on getting ar934x board (TP-Link WNDR4300)
working. It's much nicer chip than the ar933x. Expect patches later ;-)

-- 
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Re: [U-Boot] [PATCH] sunxi: Fix gmac not working due to cpu_eth_init no longer being called

[Ian Campbell]

On Thu, 2016-03-17 at 15:38 +0100, Hans de Goede wrote:
> Hi,
> 
> On 17-03-16 14:21, Ian Campbell wrote:
> > 
> > On Thu, 2016-03-17 at 14:02 +0100, Hans de Goede wrote:
> > > 
> > > cpu_eth_init is no longer called for dm enabled eth drivers, this
> > > was causing the sunxi gmac eth controller to no longer work in u-
> > > boot.
> > > 
> > > This commit fixes this by moving the gpio setup to gpio_init()
> > > and by
> > > calling the clock, reset and pinmux setup function from s_init().
> > > 
> > > Note that the mdelay is dropped as the phy gets enabled much
> > > earlier
> > > now, so it is no longer needed.
> > Everything is DM_ETH based now, right? Which is why this final hunk is
> > OK?
> Correct, we only do DM for eth in sunxi now,

Super. Acked-by: Ian Campbell 

Ian.
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Re: [U-Boot] [PATCH v3 4/4] board: pic32mzda: enable USB-host, USB-storage support.

[Marek Vasut]

On 03/16/2016 10:12 AM, Daniel Schwierzeck wrote:
> 
> 
> Am 15.03.2016 um 13:44 schrieb Purna Chandra Mandal:
>> Enable MUSB host and USB storage support for Microchip
>> PIC32MZ[DA] Starter Kit.
>>
>> Signed-off-by: Purna Chandra Mandal 
>>
>> ---
>>
>> Changes in v3:
>> - add arch specific reads{bwlq}, writes{bwlq} in respective arch io.h
>> - remove reads{bwlq}, writes{bwlq} in musb-new driver
>>
>> Changes in v2:
>> - compilation fix in drivers/usb/musb-new/linux-compat.h seperated
>> - compilation fix in drivers/gadget/f_mass_storage.c seperated
>>
>>  arch/mips/dts/pic32mzda.dtsi   | 10 ++
>>  arch/mips/dts/pic32mzda_sk.dts |  4 
>>  configs/pic32mzdask_defconfig  |  6 +-
>>  include/configs/pic32mzdask.h  |  7 +++
>>  4 files changed, 26 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
>> index 7d180d9..57e4500 100644
>> --- a/arch/mips/dts/pic32mzda.dtsi
>> +++ b/arch/mips/dts/pic32mzda.dtsi
>> @@ -171,4 +171,14 @@
>>  #address-cells = <1>;
>>  #size-cells = <0>;
>>  };
>> +
>> +usb: musb@1f8e3000 {
>> +compatible = "microchip,pic32mzda-usb";
>> +reg = <0x1f8e3000 0x1000>,
>> +  <0x1f884000 0x1000>;
>> +reg-names = "mc", "control";
>> +interrupts = <132 IRQ_TYPE_EDGE_RISING>,
>> + <133 IRQ_TYPE_LEVEL_HIGH>;
>> +status = "disabled";
>> +};
>>  };
>> diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
>> index e5ce0bd..0a7847e 100644
>> --- a/arch/mips/dts/pic32mzda_sk.dts
>> +++ b/arch/mips/dts/pic32mzda_sk.dts
>> @@ -52,4 +52,8 @@
>>  ethernet_phy: lan8740_phy@0 {
>>  reg = <0>;
>>  };
>> +};
>> +
>> + {
>> +status = "okay";
>>  };
>> \ No newline at end of file
>> diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
>> index 1dbe1b5..544112f 100644
>> --- a/configs/pic32mzdask_defconfig
>> +++ b/configs/pic32mzdask_defconfig
>> @@ -12,6 +12,7 @@ CONFIG_SYS_PROMPT="dask # "
>>  CONFIG_LOOPW=y
>>  CONFIG_CMD_MEMTEST=y
>>  CONFIG_CMD_MEMINFO=y
>> +CONFIG_CMD_USB=y
>>  # CONFIG_CMD_FPGA is not set
>>  CONFIG_CMD_GPIO=y
>>  CONFIG_CMD_RARP=y
>> @@ -28,6 +29,9 @@ CONFIG_DM_ETH=y
>>  CONFIG_PIC32_ETH=y
>>  CONFIG_PINCTRL=y
>>  # CONFIG_PINCTRL_FULL is not set
>> -CONFIG_SYS_VSNPRINTF=y
>> +CONFIG_USB=y
>> +CONFIG_DM_USB=y
>> +CONFIG_USB_MUSB_HOST=y
>> +CONFIG_USB_STORAGE=y
>>  CONFIG_USE_TINY_PRINTF=y
>>  CONFIG_CMD_DHRYSTONE=y
>> diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
>> index 2d35a0b..1d5be2b 100644
>> --- a/include/configs/pic32mzdask.h
>> +++ b/include/configs/pic32mzdask.h
>> @@ -117,6 +117,12 @@
>>  #define CONFIG_GENERIC_MMC
>>  #define CONFIG_CMD_MMC
>>  
>> +/*--
>> + * USB Configuration
>> + */
>> +#define CONFIG_USB_MUSB_PIO_ONLY
>> +#define CONFIG_SYS_CACHELINE_SIZE   16
> 
> I see CONFIG_SYS_CACHELINE_SIZE is used in drivers/usb/ in various memalign() 
> calls. Actually we have ARCH_DMA_MINALIGN for this case. At least for MIPS I 
> want to get rid of CONFIG_SYS_CACHELINE_SIZE in the future becasue we have 
> auto-detection for that. 
> 
> If possible I'd like to see a patch which replaces CONFIG_SYS_CACHELINE_SIZE 
> with ARCH_DMA_MINALIGN in drivers/user/. Marek what do you think?

I think that makes sense.

>> +
>>  /*---
>>   * File System Configuration
>>   */
>> @@ -167,6 +173,7 @@
>>  
>>  #define BOOT_TARGET_DEVICES(func)   \
>>  func(MMC, mmc, 0)   \
>> +func(USB, usb, 0)   \
>>  func(DHCP, dhcp, na)
>>  
>>  #include 
>>
> 


-- 
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Marek Vasut
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Re: [U-Boot] Newbie SPL question for socfpga_sockit

[George Broz]

On 16 March 2016 at 18:35, Marek Vasut  wrote:
> On 03/16/2016 05:17 PM, George Broz wrote:
>> On 15 March 2016 at 18:29, George Broz  wrote:
>>
>>>
>>> Hello again -
>>>
>>> So under the assumption my SoCKit h/w was broken, I bought a new board.
>>> They are back ordered on SoCKit boards, so I got a DE0-Nano-SoC instead.
>>>
>>> I build the v2016.03 (release) version of u-boot-with-spl.sfp.
>>>
>>> I power-up the (brand new) board and get:
>>>
>>> U-Boot SPL 2016.03 (Mar 15 2016 - 14:52:42)
>>> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
>>> drivers/ddr/altera/sequencer.c: CALIBRATION FAILED
>>> drivers/ddr/altera/sequencer.c: Calibration complete
>>> SDRAM calibration failed.
>>> ### ERROR ### Please RESET the board ###
>>>
>>> U-Boot SPL 2016.03 (Mar 15 2016 - 14:52:42)
>>> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
>>> drivers/ddr/altera/sequencer.c: CALIBRATION FAILED
>>> drivers/ddr/altera/sequencer.c: Calibration complete
>>> SDRAM calibration failed.
>>> ### ERROR ### Please RESET the board ###
>>>
>>> U-Boot SPL 2016.03 (Mar 15 2016 - 14:52:42)
>>> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
>>> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
>>> drivers/ddr/altera/sequencer.c: Calibration complete
>>> Trying to boot from MMC
>>>
>>> U-Boot 2016.03 (Mar 15 2016 - 14:52:42 -0700)
>>>
>>> CPU:   Altera SoCFPGA Platform
>>> FPGA:  Altera Cyclone V, SE/A4 or SX/C4, version 0x0
>>> BOOT:  SD/MMC Internal Transceiver (3.0V)
>>>Watchdog enabled
>>> I2C:   ready
>>> DRAM:  1 GiB
>>> MMC:   dwmmc0@ff704000: 0
>>> In:serial
>>> Out:   serial
>>> Err:   serial
>>> Model: Terasic DE0-Nano(Atlas)
>>> Net:
>>> Error: ethernet@ff702000 address not set.
>>> No ethernet found.
>>> Hit any key to stop autoboot:  0
>>> =>
>>>
>>> And this is a good case... usually it doesn't succeed after the fourth try
>>> and I have to cycle power 4 or 5 times before I get lucky.
>>>
>>> If I do get lucky and then try to see a USB storage device, then I get:
>>>
>>> =>
>>> => usb start
>>> starting USB...
>>> USB0:   Core Release: 2.93a
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> scanning bus 0 for devices... 1 USB Device(s) found
>>> =>
>>>
>>> (Every time)
>>>
>>> The version of u-boot SPL that ships with the board:
>>> U-Boot SPL 2013.01.01 (Dec 29 2014 - 15:29:15)
>>>
>>> boots every time and has limited USB capability as
>>> it can see some USB sticks, but not others.
>>>
>>>
>>> Anyway - brand new board - same old symptoms.
>>>
>>> Is it perhaps a toolchain problem?? I'm using:
>>>
>>> Thread model: posix
>>> gcc version 4.9.3 20141031 (prerelease) (Linaro GCC 4.9-2014.11)
>>>
>>> COLLECT_GCC=arm-poky-linux-gnueabi-gcc
>>> COLLECT_LTO_WRAPPER=/opt/poky/1.7.1/sysroots/x86_64-pokysdk-linux/usr/libexec/arm-poky-linux-gnueabi/gcc/arm-poky-linux-gnueabi/4.9.3/lto-wrapper
>>> < snip >
>>>
>>> Any advice greatly appreciated.
>>>
>>>
>>> Regards,
>>> --George Broz
>>
>> Rebuilt using the Altera EDS15.0 toolchain:
>>
>>   arm-altera-eabi-gcc --version
>>   arm-altera-eabi-gcc (Sourcery CodeBench Lite 2014.11-13) 4.9.1
>>   Copyright (C) 2014 Free Software Foundation, Inc.
>>   This is free software; see the source for copying conditions.  There is NO
>>   warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
>>
>>
>> Get same result ... mostly failing calibration, non-working USB
>>
>> U-Boot SPL 2016.03 (Mar 16 2016 - 08:27:20)
>> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
>> drivers/ddr/altera/sequencer.c: CALIBRATION FAILED
>> drivers/ddr/altera/sequencer.c: Calibration complete
>> SDRAM calibration failed.
>> ### ERROR ### Please RESET the board ###
>>
>> U-Boot SPL 2016.03 (Mar 16 2016 - 08:27:20)
>> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
>> drivers/ddr/altera/sequencer.c: CALIBRATION FAILED
>> drivers/ddr/altera/sequencer.c: Calibration complete
>> SDRAM calibration failed.
>> ### ERROR ### Please RESET the board ###
>>
>> U-Boot SPL 2016.03 (Mar 16 2016 - 08:27:20)
>> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
>> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
>> drivers/ddr/altera/sequencer.c: Calibration complete
>> Trying to boot from MMC
>>
>>
>> U-Boot 2016.03 (Mar 16 2016 - 08:27:20 -0700)
>>
>> Does this work for anybody else?
>> Is it in anyone's experience that these 

Re: [U-Boot] [U-Boot,v5,18/30] efi_loader: Add disk interfaces

[Tom Rini]

On Fri, Mar 04, 2016 at 01:10:02AM +0100, Alexander Graf wrote:

> A EFI applications usually want to access storage devices to load data from.
> 
> This patch adds support for EFI disk interfaces. It loops through all block
> storage interfaces known to U-Boot and creates an EFI object for each existing
> one. EFI applications can then through these objects call U-Boot's read and
> write functions.
> 
> Signed-off-by: Alexander Graf 
> Reviewed-by: Simon Glass 
> Tested-by: Simon Glass 

Applied to u-boot/master, thanks!

-- 
Tom


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[U-Boot] [PATCH 07/13] ARM: uniphier: add work-around to support Micro Support Card v3.6.10

[Masahiro Yamada]

Due to some hardware guy's awful work, this version is not compatible
with v3.6: the logic of BIT(0) of the reset logic is inverted! (and
v3.6.10 is horribly wrong in multiple ways), but this is what we have
to solve now.

The v3.6 expects 0x set to the register for reset de-assertion,
while v3.6 does 0x0001.

This commit (ab)uses another bug of v3.6.10 to work around the issue.
The UniPhier System Bus is a 16-bit bus, which this support card is
connected to.  A 32-bit write to the bus (writel() function call) is
divided into two 16-bit write transactions, with LSB the first.  What
is amazing for v3.6.10 is that access to address 4N + 2 goes to 4N
(Jesus Christ!).

For clarification, things are like this:

writel(0x0001, MICRO_SUPPORT_CARD_RESET);

is done with two bus transactions as follows

[1] write 0x to address MICRO_SUPPORT_CARD
[2] write 0x0001 to address MICRO_SUPPORT_CARD + 2

For v3.6, [1] is written to the register and [2] is correctly ignored
because there is nothing at the address MICRO_SUPPORT_CARD + 2.  This
is what we expect.

For v3.6.10, [1] is written to the reset register and then [2] is
over-written to the same register due to the bus access bug.

For the latter, it produces a glitch signal to the BIT[0], so the
device state is lost due to the reset pulse.  This solution only
works for the start-up code.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/micro-support-card.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-uniphier/micro-support-card.c 
b/arch/arm/mach-uniphier/micro-support-card.c
index f7a37e3..eeb515a 100644
--- a/arch/arm/mach-uniphier/micro-support-card.c
+++ b/arch/arm/mach-uniphier/micro-support-card.c
@@ -25,12 +25,12 @@
  */
 void support_card_reset_deassert(void)
 {
-   writel(0, MICRO_SUPPORT_CARD_RESET);
+   writel(0x0001, MICRO_SUPPORT_CARD_RESET);
 }
 
 void support_card_reset(void)
 {
-   writel(3, MICRO_SUPPORT_CARD_RESET);
+   writel(0x00020003, MICRO_SUPPORT_CARD_RESET);
 }
 
 static int support_card_show_revision(void)
-- 
1.9.1

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[U-Boot] [PATCH v4 4/4] board: pic32mzda: enable USB-host, USB-storage support.

[Purna Chandra Mandal]

Enable MUSB host and USB storage support for Microchip
PIC32MZ[DA] Starter Kit.

Signed-off-by: Purna Chandra Mandal 
---

Changes in v4:
- dts: add USB clock to musb node
- add missing CONFIG_PIC32_USB in defconfig

Changes in v3:
- add arch specific reads{bwlq}, writes{bwlq} in respective arch io.h
- remove reads{bwlq}, writes{bwlq} in musb-new driver

Changes in v2:
- compilation fix in drivers/usb/musb-new/linux-compat.h seperated
- compilation fix in drivers/gadget/f_mass_storage.c seperated

 arch/mips/dts/pic32mzda.dtsi   | 12 
 arch/mips/dts/pic32mzda_sk.dts |  4 
 configs/pic32mzdask_defconfig  |  7 ++-
 include/configs/pic32mzdask.h  |  7 +++
 4 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
index 5d8bc4b..8865154 100644
--- a/arch/mips/dts/pic32mzda.dtsi
+++ b/arch/mips/dts/pic32mzda.dtsi
@@ -179,4 +179,16 @@
  <0x1d10 0x10>;
reg-names = "nvm", "bank1","bank2";
};
+
+   usb: musb@1f8e3000 {
+   compatible = "microchip,pic32mzda-usb";
+   reg = <0x1f8e3000 0x1000>,
+ <0x1f884000 0x1000>;
+   reg-names = "mc", "control";
+   interrupts = <132 IRQ_TYPE_EDGE_RISING>,
+<133 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < PB5CLK>;
+   clock-names = "usb_clk";
+   status = "disabled";
+   };
 };
diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
index e5ce0bd..0a7847e 100644
--- a/arch/mips/dts/pic32mzda_sk.dts
+++ b/arch/mips/dts/pic32mzda_sk.dts
@@ -52,4 +52,8 @@
ethernet_phy: lan8740_phy@0 {
reg = <0>;
};
+};
+
+ {
+   status = "okay";
 };
\ No newline at end of file
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 2f3d463..33af04e 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -12,6 +12,7 @@ CONFIG_SYS_PROMPT="dask # "
 CONFIG_LOOPW=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_RARP=y
@@ -29,6 +30,10 @@ CONFIG_DM_ETH=y
 CONFIG_PIC32_ETH=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_FULL is not set
-CONFIG_SYS_VSNPRINTF=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_PIC32=y
+CONFIG_USB_STORAGE=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 92314e5..9296d26 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -110,6 +110,12 @@
 #define CONFIG_GENERIC_MMC
 #define CONFIG_CMD_MMC
 
+/*--
+ * USB Configuration
+ */
+#define CONFIG_USB_MUSB_PIO_ONLY
+#define CONFIG_SYS_CACHELINE_SIZE  16
+
 /*---
  * File System Configuration
  */
@@ -160,6 +166,7 @@
 
 #define BOOT_TARGET_DEVICES(func)  \
func(MMC, mmc, 0)   \
+   func(USB, usb, 0)   \
func(DHCP, dhcp, na)
 
 #include 
-- 
1.8.3.1

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Re: [U-Boot] [RFC PATCH 1/2] add block device cache

[Eric Nelson]

Thanks for the review(s) Stephen.

On 03/17/2016 02:16 PM, Stephen Warren wrote:
> On 03/16/2016 03:40 PM, Eric Nelson wrote:
>> Signed-off-by: Eric Nelson 
> 
> A patch description would be useful here; the cover letter wouldn't be
> checked in.
> 

Yeah. Please hote the RFC.

I was really hoping for some broader feedback about whether this
is a better approach than the more specialized ext4 extent cache.

If I can get an ack on the approach, I think a minimal block
device cache would support at least 2 or 4 entries, and I'd
need to be able to answer the questions from your other
response:

> Do you have any stats on how many operations this saves for typical FS 
> operations such as:
> 
> - Partition table type identification (with various types such as MBR/DOS, 
> GPT, ...)
> - Partition enumeration
> - Filesystem identification (with various filesystems such as FAT, ext, ...)
> - File reads 

Should I interpret this as support of a small(ish) block device cache?

Regards,


Eric
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[U-Boot] [PATCH v2 4/5] RPi: Enable caches for rpi2

[Alexander Graf]

Now that we have support for running with caches enabled in HYP mode,
opt in to that on the Raspberry Pi 2. This brings a significant performance
boost.

Signed-off-by: Alexander Graf 

---

v1 -> v2:

  - Move to KConfig
  - Adapt to new define name
---
 arch/arm/mach-bcm283x/Kconfig | 1 +
 arch/arm/mach-bcm283x/init.c  | 7 +++
 include/configs/rpi_2.h   | 1 -
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index 2315a13..1a7baf6 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -12,6 +12,7 @@ config TARGET_RPI
 config TARGET_RPI_2
bool "Raspberry Pi 2"
select CPU_V7
+   select ARMV7_LPAE
 
 endchoice
 
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index d2d366b..4fa94db 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -15,3 +15,10 @@ int arch_cpu_init(void)
 
return 0;
 }
+
+#ifdef CONFIG_ARMV7_LPAE
+void enable_caches(void)
+{
+   dcache_enable();
+}
+#endif
diff --git a/include/configs/rpi_2.h b/include/configs/rpi_2.h
index bea4ebd..13dc8de 100644
--- a/include/configs/rpi_2.h
+++ b/include/configs/rpi_2.h
@@ -10,7 +10,6 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BCM2836
 #define CONFIG_SYS_CACHELINE_SIZE  64
-#define CONFIG_SYS_DCACHE_OFF
 
 #include "rpi-common.h"
 
-- 
1.8.5.6

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