Re: [U-Boot] [PATCH 1/2] drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl

[Shengzhou Liu]

> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Wednesday, June 01, 2016 12:04 AM
> To: Shengzhou Liu ; u-boot@lists.denx.de
> Shengzhou,
> 
> If you have to use an odd number for clk_adj, we can go ahead to merge
> these patches. In my experience, clk_adj is very forgivable. If you have only
> one value works, there is probably something wrong.
> 
> York
> 
York, 
The odd clk_adj = 9  is the optimal with timing centralization, maybe it work  
if set it to 8, but not the optimal.
Theoretically we should have the actual value instead of dividing 2 to avoid 
confusion for customers.
Shengzhou
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Re: [U-Boot] [RFC] tools/env: Support UBI devices

[Heiko Schocher]

Hello Kevin,

Sorry for the late reply

Am 17.05.2016 um 00:07 schrieb Kevin Smith:

Instead of requiring gluebi to update u-boot environments from
Linux, directly support writing to an UBI device.  The
fw_env.config file will look something like this:

Device  Offset  Envsize LEB SizeCount
/dev/ubi0_0 0   0x1 0x1f000 1

It is important to use LEB size instead of PEB size when using
UBI.

Signed-off-by: Kevin Smith 
Cc: Michael Heimpold 
Cc: Joe Hershberger 
---
  tools/env/fw_env.c | 71 --
  1 file changed, 48 insertions(+), 23 deletions(-)


Did you looked at the patches from Marcin. He also did such an
approach here:

[U-Boot,1/2] tools: env: Fix format warnings in debug
http://patchwork.ozlabs.org/patch/619306/

[U-Boot,2/2] tools: env: Add support for direct read/write UBI volumes
http://patchwork.ozlabs.org/patch/619305/

I like his approach more, as with it we can also use UBI Volumes
by name and the config file looks cleaner to me ...

bye,
Heiko
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[U-Boot] [PATCH] spl: fit: Fix load address of fit header

[Lokesh Vutla]

When loading fit header, it should be loaded to a previous address
aligned to ARCH_DMA_MINALIGN and not 8. Fixing the same.

Signed-off-by: Lokesh Vutla 
---
 common/spl/spl_fit.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index a828f72..c9eb020 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -156,8 +156,8 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong 
sector, void *fit)
 * In fact the FIT has its own load address, but we assume it cannot
 * be before CONFIG_SYS_TEXT_BASE.
 */
-   fit = (void *)(CONFIG_SYS_TEXT_BASE - size - info->bl_len);
-   fit = (void *)ALIGN((ulong)fit, 8);
+   fit = (void *)((CONFIG_SYS_TEXT_BASE - size - info->bl_len -
+   align_len) & ~align_len);
sectors = get_aligned_image_size(info, size, 0);
count = info->read(info, sector, sectors, fit);
debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu\n",
-- 
2.8.2

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Re: [U-Boot] u-boot-x86 sf probe fail

[Bin Meng]

Hi,

On Tue, May 31, 2016 at 6:14 PM, Hilbert Tu(杜睿哲_Pegatron)
 wrote:
> Hi,
>
> I use Coreboot with u-boot-x86 as payload to bring-up my Intel Atom C2000 
> platform, but I cannot make my SPI flash(w25q128fv) to work.
> Actually the SPI was detected under coreboot with correct ID, but in u-boot 
> “sf probe” command, it just always failed.
> After tracing and code dump, I found it was failed due to SPIS_FCERR in 
> spi/ich.c spi_xfer function.
> I totally have no idea why this happened and how to proceed my bring-up.
> My u-boot-x86 is up-to-date version and the SPI use intel,ich9-spi compatible 
> in my dts file.
>

Can you double check Atom C2000 SPI controller that it is ICH9
compatible? Or maybe ICH7 compatible? Did you check its register can
be accessed correctly?

> Following is my dm tree and there is spi-flash device
>
> => dm tree
> Class   Probed   Name
> 
> root[ + ]root_driver
> serial  [ + ]|-- serial
> keyboard[ + ]|-- keyboard
> rtc [   ]|-- rtc
> timer   [ + ]|-- tsc-timer
> pci [ + ]`-- pci
> pch [ + ]|-- pch@1f,0
> irq [ + ]|   |-- irq-router
> spi [   ]|   `-- spi
> spi_flash   [   ]|   `-- spi-flash@0
> pci_generic [   ]|-- pci_0:0.0
> pci [ + ]|-- pci_0:1.0
> pci_generic [   ]|   `-- pci_1:0.0
> pci [ + ]|-- pci_0:3.0
> pci_generic [   ]|-- pci_0:e.0
> pci_generic [   ]|-- pci_0:f.0
> pci_generic [   ]|-- pci_0:13.0
> usb [   ]|-- ehci_pci
> pci_generic [   ]|-- pci_0:17.0
> pci_generic [   ]|-- pci_0:18.0
> pci_generic [   ]`-- pci_0:1f.3
> =>
> Could you please give me some hint or tell me where I can reference? Thanks.
>

Regards,
Bin
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[U-Boot] [PATCH v2] serial: atmel_usart: Add device tree support

[Wenyou Yang]

Add device tree support.

Signed-off-by: Wenyou Yang 
---

Changes in v2:
 - Add conditional for device tree support.

 drivers/serial/atmel_usart.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
index 4fe992b..e450135 100644
--- a/drivers/serial/atmel_usart.c
+++ b/drivers/serial/atmel_usart.c
@@ -191,16 +191,35 @@ static int atmel_serial_probe(struct udevice *dev)
 {
struct atmel_serial_platdata *plat = dev->platdata;
struct atmel_serial_priv *priv = dev_get_priv(dev);
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+   fdt_addr_t addr_base;
 
+   addr_base = dev_get_addr(dev);
+   if (addr_base == FDT_ADDR_T_NONE)
+   return -ENODEV;
+
+   plat->base_addr = (uint32_t)addr_base;
+#endif
priv->usart = (atmel_usart3_t *)plat->base_addr;
atmel_serial_init_internal(priv->usart);
 
return 0;
 }
 
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct udevice_id atmel_serial_ids[] = {
+   { .compatible = "atmel,at91sam9260-usart" },
+   { }
+};
+#endif
+
 U_BOOT_DRIVER(serial_atmel) = {
.name   = "serial_atmel",
.id = UCLASS_SERIAL,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+   .of_match = atmel_serial_ids,
+   .platdata_auto_alloc_size = sizeof(struct atmel_serial_platdata),
+#endif
.probe = atmel_serial_probe,
.ops= _serial_ops,
.flags = DM_FLAG_PRE_RELOC,
-- 
2.7.4

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[U-Boot] [PATCH] arm: Select CONFIG_ARM64 for Cavium ThunderX

[Marek Vasut]

Select the config option, since this board is ARM64.

Signed-off-by: Marek Vasut 
Cc: Simon Glass 
Cc: Tom Rini 
---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f82f5a8..77eab66 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -780,6 +780,7 @@ config ARCH_ROCKCHIP
 
 config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
+   select ARM64
select OF_CONTROL
 
 endchoice
-- 
2.7.0

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Re: [U-Boot] [PATCH v4] arm/arm64: implement a boot header capability

[Tom Rini]

On Tue, May 31, 2016 at 10:45:06AM -0700, Steve Rae wrote:

> From: Andre Przywara 
> 
> Some SPL loaders (like Allwinner's boot0, and Broadcom's boot0)
> require a header before the actual U-Boot binary to both check its
> validity and to find other data to load. Sometimes this header may
> only be a few bytes of information, and sometimes this might simply
> be space that needs to be reserved for a post-processing tool.
> 
> Introduce a config option to allow assembler preprocessor commands
> to be inserted into the code at the appropriate location; typical
> assembler preprocessor commands might be:
>   .space 1000
>   .word 0x12345678
> 
> Signed-off-by: Andre Przywara 
> Signed-off-by: Steve Rae 
> Commit Notes:
> Please note that the current code:
>   start.S (arm64) and
>   vectors.S (arm)
> already jumps over some portion of data already, so this option basically
> just increases the size of this region (and the resulting binary).
> 
> For use with Allwinner's boot0 blob there is a tool called boot0img[1],
> which fills the header to allow booting A64 based boards.
> For the Pine64 we need a 1536 byte header (including the branch
> instruction) at the moment, so we add this to the defconfig.
> 
> [1] https://github.com/apritzel/pine64/tree/master/tools
> END
> 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH] mips: wdr4300: Move the CONFIG_USE_PRIVATE_LIBGCC to Kconfig

[Tom Rini]

On Wed, Jun 01, 2016 at 12:00:02AM +0200, Marek Vasut wrote:

> This fixes the last remaining libgcc warning, where the symbol was
> defined twice.
> 
> Signed-off-by: Marek Vasut 
> Cc: Simon Glass 
> Cc: Tom Rini 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH 2/2] ARM: omap: Enable tiny printf on omap3_logic

[Tom Rini]

On Tue, May 31, 2016 at 11:12:47PM +0200, Marek Vasut wrote:

> Enable support for tiny printf on the omap3_logic board to trim down
> the SPL size. This makes the SPL actually build again and fit into
> the SRAM.
> 
> Signed-off-by: Marek Vasut 
> Cc: Simon Glass 
> Cc: Tom Rini 
> Cc: le...@alse-fr.com

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH 1/2] tiny-printf: Support sprintf()

[Tom Rini]

On Tue, May 31, 2016 at 11:12:46PM +0200, Marek Vasut wrote:

> Add a simple version of this function for SPL. It does not check the buffer
> size as this would add to the code size.
> 
> Signed-off-by: Marek Vasut 
> Cc: Simon Glass 
> Cc: Stefan Roese 
> Cc: Tom Rini 
> Cc: le...@alse-fr.com

Reviewed-by: Tom Rini 

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[U-Boot] [PATCH] mips: wdr4300: Move the CONFIG_USE_PRIVATE_LIBGCC to Kconfig

[Marek Vasut]

This fixes the last remaining libgcc warning, where the symbol was
defined twice.

Signed-off-by: Marek Vasut 
Cc: Simon Glass 
Cc: Tom Rini 
---
 configs/tplink_wdr4300_defconfig | 1 +
 include/configs/tplink_wdr4300.h | 2 --
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig
index b1af2f6..3eec4c2 100644
--- a/configs/tplink_wdr4300_defconfig
+++ b/configs/tplink_wdr4300_defconfig
@@ -1,6 +1,7 @@
 CONFIG_MIPS=y
 CONFIG_ARCH_ATH79=y
 CONFIG_BOARD_TPLINK_WDR4300=y
+CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SERIAL=y
diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
index 6273711..abe1da2 100644
--- a/include/configs/tplink_wdr4300.h
+++ b/include/configs/tplink_wdr4300.h
@@ -78,8 +78,6 @@
 #define CONFIG_SYS_MEMTEST_END 0x83f0
 #define CONFIG_CMD_MEMTEST
 
-#define CONFIG_USE_PRIVATE_LIBGCC
-
 #define CONFIG_CMD_MII
 #define CONFIG_PHY_GIGE
 
-- 
2.7.0

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Re: [U-Boot] [PATCH 2/2] arm: socfpga: Enable tiny printf and simple malloc in SPL

[Marek Vasut]

On 05/31/2016 02:34 AM, Chin Liang See wrote:
> On Mon, 2016-05-30 at 18:39 +0200, Stefan Roese wrote:
>> On 30.05.2016 17:22, Marek Vasut wrote:
>>> Enable both features to reduce the SPL size by 6 kiB.
>>>
>>> Signed-off-by: Marek Vasut 
>>> Cc: Chin Liang See 
>>> Cc: Dinh Nguyen 
>>> Cc: Pavel Machek 
>>> Cc: Stefan Roese 
>>
>> Reviewed-by: Stefan Roese 
>>
> 
> Acked-by: Chin Liang See 

Applied both to u-boot-socfpga/master

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[U-Boot] [PATCH 2/2] ARM: omap: Enable tiny printf on omap3_logic

[Marek Vasut]

Enable support for tiny printf on the omap3_logic board to trim down
the SPL size. This makes the SPL actually build again and fit into
the SRAM.

Signed-off-by: Marek Vasut 
Cc: Simon Glass 
Cc: Tom Rini 
Cc: le...@alse-fr.com
---
 configs/omap3_logic_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index 3226247..e7bf385 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_LOGIC=y
+CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
-- 
2.7.0

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[U-Boot] [PATCH 1/2] tiny-printf: Support sprintf()

[Marek Vasut]

Add a simple version of this function for SPL. It does not check the buffer
size as this would add to the code size.

Signed-off-by: Marek Vasut 
Cc: Simon Glass 
Cc: Stefan Roese 
Cc: Tom Rini 
Cc: le...@alse-fr.com
---
 lib/tiny-printf.c | 16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index 4b70263..5ea2555 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -147,8 +147,7 @@ static void putc_outstr(char ch)
*outstr++ = ch;
 }
 
-/* Note that size is ignored */
-int snprintf(char *buf, size_t size, const char *fmt, ...)
+int sprintf(char *buf, const char *fmt, ...)
 {
va_list va;
int ret;
@@ -161,3 +160,16 @@ int snprintf(char *buf, size_t size, const char *fmt, ...)
 
return ret;
 }
+
+/* Note that size is ignored */
+int snprintf(char *buf, size_t size, const char *fmt, ...)
+{
+   va_list va;
+   int ret;
+
+   va_start(va, fmt);
+   ret = sprintf(buf, fmt, va);
+   va_end(va);
+
+   return ret;
+}
-- 
2.7.0

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[U-Boot] [PATCH] dm: gpio: MPC85XX GPIO platform data support

[Hamish Martin]

Define a platform data structure for the MPC85XX GPIO driver to allow
use of the driver without device tree. Users should define the GPIO
blocks for their platform like this:
  struct mpc85xx_gpio_plat gpio_blocks[] = {
 {
 .addr = 0x13,
 .ngpios = 32,
 },
 {
 .addr = 0x131000,
 .ngpios = 32,
 },
  };

  U_BOOT_DEVICES(my_platform_gpios) = {
 { "gpio_mpc85xx", _blocks[0] },
 { "gpio_mpc85xx", _blocks[1] },
  };

This is intended to build upon the recent submission of the base
MPC85XX driver from Mario Six. We need to use that new driver
without dts support and this patch gives us that flexibility.
This has been tested on a Freescale T2080 CPU, although only the first
GPIO block.

Signed-off-by: Hamish Martin 
Reviewed-by: Mario Six 
Tested-by: Mario Six 
---
 arch/powerpc/include/asm/arch-mpc85xx/gpio.h |  6 +
 drivers/gpio/mpc85xx_gpio.c  | 37 ++--
 2 files changed, 36 insertions(+), 7 deletions(-)

diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h 
b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
index 41b6677bba38..76faa22c8b43 100644
--- a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
@@ -18,4 +18,10 @@
 #include 
 #endif
 
+struct mpc85xx_gpio_plat {
+   ulong addr;
+   unsigned long size;
+   uint ngpios;
+};
+
 #endif
diff --git a/drivers/gpio/mpc85xx_gpio.c b/drivers/gpio/mpc85xx_gpio.c
index 04773e2b31c3..3754a8215c36 100644
--- a/drivers/gpio/mpc85xx_gpio.c
+++ b/drivers/gpio/mpc85xx_gpio.c
@@ -163,23 +163,41 @@ static int mpc85xx_gpio_get_function(struct udevice *dev, 
unsigned gpio)
return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
 }
 
+#if CONFIG_IS_ENABLED(OF_CONTROL)
 static int mpc85xx_gpio_ofdata_to_platdata(struct udevice *dev) {
-   struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+   struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev);
fdt_addr_t addr;
fdt_size_t size;
 
addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev->of_offset,
  "reg", 0, );
 
-   data->addr = addr;
-   data->base = map_sysmem(CONFIG_SYS_IMMR + addr, size);
+   plat->addr = addr;
+   plat->size = size;
+   plat->ngpios = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "ngpios", 32);
 
-   if (!data->base)
+   return 0;
+}
+#endif
+
+static int mpc85xx_gpio_platdata_to_priv(struct udevice *dev)
+{
+   struct mpc85xx_gpio_data *priv = dev_get_priv(dev);
+   struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev);
+   unsigned long size = plat->size;
+
+   if (size == 0)
+   size = 0x100;
+
+   priv->addr = plat->addr;
+   priv->base = map_sysmem(CONFIG_SYS_IMMR + plat->addr, size);
+
+   if (!priv->base)
return -ENOMEM;
 
-   data->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
- "ngpios", 32);
-   data->dat_shadow = 0;
+   priv->gpio_count = plat->ngpios;
+   priv->dat_shadow = 0;
 
return 0;
 }
@@ -190,6 +208,8 @@ static int mpc85xx_gpio_probe(struct udevice *dev)
struct mpc85xx_gpio_data *data = dev_get_priv(dev);
char name[32], *str;
 
+   mpc85xx_gpio_platdata_to_priv(dev);
+
snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
str = strdup(name);
 
@@ -221,8 +241,11 @@ U_BOOT_DRIVER(gpio_mpc85xx) = {
.name   = "gpio_mpc85xx",
.id = UCLASS_GPIO,
.ops= _mpc85xx_ops,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
.ofdata_to_platdata = mpc85xx_gpio_ofdata_to_platdata,
+   .platdata_auto_alloc_size = sizeof(struct mpc85xx_gpio_plat),
.of_match = mpc85xx_gpio_ids,
+#endif
.probe  = mpc85xx_gpio_probe,
.priv_auto_alloc_size = sizeof(struct mpc85xx_gpio_data),
 };
-- 
2.8.3

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Re: [U-Boot] [PATCH 1/2] spl: Remove bogus GD_FLG_SPL_INIT check

[Pavel Machek]

On Mon 2016-05-30 17:22:33, Marek Vasut wrote:
> Remove the check for GD_FLG_SPL_INIT in spl_relocate_stack_gd().
> The check will always fail. This is because spl_relocate_stack_gd()
> is called from ARM's crt0.S and it is called before board_init_r().
> The board_init_r() calls spl_init(), which sets the GD_FLG_SPL_INIT
> flag.
> 
> Note that reserving the malloc area in RAM is not a problem even
> if the GD_FLG_SPL_INIT flag is not set.
> 
> Signed-off-by: Marek Vasut 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Hans de Goede 
> Cc: Pavel Machek 
> Cc: Stefan Roese 
> Cc: Stephen Warren 

Acked-by: Pavel Machek 

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Re: [U-Boot] [PATCH 2/2] arm: socfpga: Enable tiny printf and simple malloc in SPL

[Pavel Machek]

On Mon 2016-05-30 17:22:34, Marek Vasut wrote:
> Enable both features to reduce the SPL size by 6 kiB.
> 
> Signed-off-by: Marek Vasut 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 

Acked-by: Pavel Machek 
Tested-by: Pavel Machek 

Thanks!
Pavel
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Re: [U-Boot] [PATCH 2/2] nand: extend nand torture

[Benoît Thébaudeau]

Dear Max Krummenacher,

On Mon, May 30, 2016 at 4:28 PM, Max Krummenacher  wrote:
> nand torture currently works on exactly one nand block which is specified
> by giving the byteoffset to the beginning of the block.
>
> Extend this by allowing for a second parameter specifying the byte offset
> to the last block to be tested.
>

End offsets are always ambiguous because users can hesitate between
the offset of the first byte of the last block, the offset of the last
byte of the last block, and the offset of the first byte of the block
following the last one (if any). A byte size would probably be better
here, and it would also be more consistent with the other nand
commands.

> e.g.
> ==> nand torture 100
>
> NAND torture: device 0 offset 0x100 size 0x2
> passed 1, failed 0
>
> ==> nand torture 100 104
>
> NAND torture: device 0 offset 0x100 size 0x2
> passed 2, failed 0
>

With more than one block to test, the printed size becomes ambiguous
here. It would be better to indicate that it is the erase size of the
block. The total test size could also be printed, either instead of
the erase size, or besides it.

> Signed-off-by: Max Krummenacher 
> ---
>
>  cmd/nand.c | 25 +
>  1 file changed, 21 insertions(+), 4 deletions(-)
>
> diff --git a/cmd/nand.c b/cmd/nand.c
> index a6b67e2..615dbd5 100644
> --- a/cmd/nand.c
> +++ b/cmd/nand.c
> @@ -646,6 +646,8 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, 
> char * const argv[])
>
>  #ifdef CONFIG_CMD_NAND_TORTURE
> if (strcmp(cmd, "torture") == 0) {
> +   loff_t endoff;
> +   unsigned failed = 0, passed = 0;
> if (argc < 3)
> goto usage;
>
> @@ -653,13 +655,27 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int 
> argc, char * const argv[])
> puts("Offset is not a valid number\n");
> return 1;
> }
> -
> +   endoff = off + nand->erasesize;
> +   if (argc > 3)
> +   if (!str2off(argv[3], )) {
> +   puts("End is not a valid number\n");
> +   return 1;
> +   }
> printf("\nNAND torture: device %d offset 0x%llx size 0x%x\n",
> dev, off, nand->erasesize);
> -   ret = nand_torture(nand, off);
> -   printf(" %s\n", ret ? "Failed" : "Passed");
> +   while (off < endoff) {
>
> -   return ret == 0 ? 0 : 1;
> +   ret = nand_torture(nand, off);
> +   if (ret) {
> +   failed++;
> +   printf(" off 0x%llx %s\n", off, "Failed");
> +   } else {
> +   passed++;
> +   }
> +   off += nand->erasesize;
> +   }
> +   printf("passed %u, failed %u\n", passed, failed);
> +   return failed == 0 ? 0 : 1;
> }
>  #endif

A size parameter could probably be added to nand_torture() instead of
handling the range in the command, so that the direct usages of
nand_torture() (in or out of tree) can also benefit from this
enhancement.

>
> @@ -775,6 +791,7 @@ static char nand_help_text[] =
> "nand dump[.oob] off - dump page\n"
>  #ifdef CONFIG_CMD_NAND_TORTURE
> "nand torture off - torture block at offset\n"
> +   "nand torture start end - torture blocks from start to end offset\n"
>  #endif
> "nand scrub [-y] off size | scrub.part partition | scrub.chip\n"
> "really clean NAND erasing bad blocks (UNSAFE)\n"

doc/README.nand should also be updated accordingly.

> --
> 2.5.5

Best regards,
Benoît
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Re: [U-Boot] [PATCH 1/2] [RFC] lib: Implement support for tiny sprintf()

[Simon Glass]

Hi Marek,

On 1 June 2016 at 07:36, Marek Vasut  wrote:
> On 05/31/2016 08:19 PM, Simon Glass wrote:
>> Hi,
>>
>> On 31 May 2016 at 05:55, Tom Rini  wrote:
>>> On Thu, May 26, 2016 at 06:00:24PM +0200, Marek Vasut wrote:
>>>
 Tweak the tiny printf code to also provide similarly tiny sprintf()
 implementation. This is not comformant with POSIX for sure, but it
 keeps the size down while still behaving rather reasonably.

 Signed-off-by: Marek Vasut 
 Cc: Simon Glass 
 Cc: Tom Rini 
>>>
>>> Reviewed-by: Tom Rini 
>>
>> Also please see this one:
>>
>> http://patchwork.ozlabs.org/patch/622267/
>>
>> It uses a function passed in.
>
> Oh, I knew I saw some s*printf() stuff from you. Works for me :)

OK good. It works for me too but I'm sure it can be improved (code
size, use of division, etc.), so see how you go.

Regards,
Simon
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Re: [U-Boot] [PATCH 2/2] arm: socfpga: Enable tiny printf and simple malloc in SPL

[Marek Vasut]

On 05/31/2016 07:43 PM, Sylvain Lesne wrote:
> On 05/31/2016 05:42 PM, Marek Vasut wrote:
>> On 05/31/2016 04:58 PM, Sylvain Lesne wrote:
>>> Hi,
>>
>> Hi,
>>
>>> On 05/30/2016 05:22 PM, Marek Vasut wrote:
 Enable both features to reduce the SPL size by 6 kiB.

 Signed-off-by: Marek Vasut 
 Cc: Chin Liang See 
 Cc: Dinh Nguyen 
 Cc: Pavel Machek 
 Cc: Stefan Roese 
>>>
>>> I tried to use the raw MMC boot (on the sockit, with current master
>>> + your patches), so I changed the following:
>>>
>>> --- a/include/configs/socfpga_common.h
>>> +++ b/include/configs/socfpga_common.h
>>> @@ -349,9 +349,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>>> #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
>>> #define CONFIG_SPL_LIBDISK_SUPPORT
>>> #else
>>> -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3
>>> -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560
>>> sect (1M+256k) */
>>> -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
>>> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 3
>>> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 /* offset 512
>>> sect (256k) */
>>> +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 1000 /* 512 KB */
>>
>> This should be 0x800 (was probably a typo in the original).
>> Otherwise this should not break anything, yeah.
>>
> 
> I might be missing something obvious, but it actually seems that this
> define isn't used outside of the include/configs/ folder...

Oh heh, good catch. If you want to nuke that one in include/configs/, be
my guest. The mmc spl is now parsing the uImage header to load the
right amount of data.

>>> +#define CONFIG_SPL_LIBDISK_SUPPORT
>>> #endif
>>> #endif
>>>
>>> AFAIK, there were two mistakes:
>>> 1) FS_BOOT_PARTITION instead of RAW_MODE_U_BOOT
>>> 2) CONFIG_SPL_LIBDISK_SUPPORT was missing
>>
>> In fact, LIBDISK support was not used before you added the
>> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION into the board config.
>> The libdisk functions are needed for determining the start of the
>> partition. Looking through the SPL MMC, the code originally loaded the
>> u-boot image from a fixed offset on the card (2560 sectors), which is
>> indeed not optimal.
>>
> 
> I agree, but I thought that the CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
> option was a bit confusing in this context! And I did not realise
> the behaviour would be to load from a fixed offset.
> 
> As soon as the tiny printf "issue" is solved, I'll send this patch
> (as I don't want to break the build).

I think I will just pick these patches here, you can apply them and send
whatever you have.

>> So yes, please send the above patch, it'd be a nice improvement.
>>
>>> (I edited the offset to be able to use u-boot-with-spl.sfp directly)
>>>
>>> With these settings, I think we run into the size problem reported
>>> previously in the ML.
>>>
>>> So, enabling tiny printf could help, but we now get:
>>>
>>> disk/built-in.o: In function `part_get_info_extended':
>>> ...u-boot/disk/part_dos.c:236: undefined reference to `sprintf'
>>>
>>> So I think we can just put "info->name[0] = 0;" instead of
>>> the snprintf() calls, when using tiny printf.
>>
>> There is more of that stuff in disk/ , at least part_efi.c and
>> part_iso.c suffer from the exact same problem. I am not sure if
>> setting the name to '\0' wouldn't break anything, CCing Simon
>> as he was recently digging in those areas.
>>
>> Also, take a look at this patch:
>> https://patchwork.ozlabs.org/patch/626760/
> 
> Ah yes, I naively only looked at the part_dos.c file. Actually
> a tiny snprintf implementation by Simon was already merged!
> 
> http://git.denx.de/?p=u-boot.git;a=commit;h=5c411d88be8df5f6a8a1ea0c961f7c35ba82c064
> 
> If I implement a naive sprintf() using this as a basis, I can boot
> from MMC without tweaking anything else, but it adds ~730 bytes
> to tiny-printf.o.

I suppose the naive implementation would be calling snprintf() with size
= ~0 ? Go for it.

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 1/2] [RFC] lib: Implement support for tiny sprintf()

[Marek Vasut]

On 05/31/2016 08:19 PM, Simon Glass wrote:
> Hi,
> 
> On 31 May 2016 at 05:55, Tom Rini  wrote:
>> On Thu, May 26, 2016 at 06:00:24PM +0200, Marek Vasut wrote:
>>
>>> Tweak the tiny printf code to also provide similarly tiny sprintf()
>>> implementation. This is not comformant with POSIX for sure, but it
>>> keeps the size down while still behaving rather reasonably.
>>>
>>> Signed-off-by: Marek Vasut 
>>> Cc: Simon Glass 
>>> Cc: Tom Rini 
>>
>> Reviewed-by: Tom Rini 
> 
> Also please see this one:
> 
> http://patchwork.ozlabs.org/patch/622267/
> 
> It uses a function passed in.

Oh, I knew I saw some s*printf() stuff from you. Works for me :)

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 1/2] [RFC] lib: Implement support for tiny sprintf()

[Simon Glass]

Hi,

On 31 May 2016 at 05:55, Tom Rini  wrote:
> On Thu, May 26, 2016 at 06:00:24PM +0200, Marek Vasut wrote:
>
>> Tweak the tiny printf code to also provide similarly tiny sprintf()
>> implementation. This is not comformant with POSIX for sure, but it
>> keeps the size down while still behaving rather reasonably.
>>
>> Signed-off-by: Marek Vasut 
>> Cc: Simon Glass 
>> Cc: Tom Rini 
>
> Reviewed-by: Tom Rini 

Also please see this one:

http://patchwork.ozlabs.org/patch/622267/

It uses a function passed in.

Regards,
Simon
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Re: [U-Boot] [PATCH 0/5] Update fastboot sparse image handling

[Steve Rae]

On Fri, May 20, 2016 at 6:05 PM, Steve Rae  wrote:
> While retaining the storage abstraction feature implemented in U-Boot,
> this series updates the fastboot sparse image handling by
> (1) fixing broken code,
> (2) resync'ing with the upstream code, and
> (3) improving performance when writing CHUNK_TYPE_FILL
>
>
> Steve Rae (5):
>   fastboot: sparse: remove session-id logic
>   fastboot: sparse: resync common/image-sparse.c (part 1)
>   fastboot: sparse: resync common/image-sparse.c (part 2)
>   fastboot: sparse: implement reserve()
>   fastboot: sparse: improve CHUNK_TYPE_FILL write performance
>
>  common/fb_mmc.c |  79 +++
>  common/fb_nand.c| 100 +
>  common/image-sparse.c   | 478 
> +++-
>  drivers/usb/gadget/f_fastboot.c |  47 ++--
>  include/fastboot.h  |   4 +-
>  include/fb_mmc.h|   7 +-
>  include/fb_nand.h   |   7 +-
>  include/image-sparse.h  |  29 ++-
>  8 files changed, 309 insertions(+), 442 deletions(-)
>
> --
> 1.8.5
>

Tom,
please pull this series.
Thanks, Steve
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Re: [U-Boot] [PATCH 2/2] arm: socfpga: Enable tiny printf and simple malloc in SPL

[Sylvain Lesne]

On 05/31/2016 05:42 PM, Marek Vasut wrote:
> On 05/31/2016 04:58 PM, Sylvain Lesne wrote:
>> Hi,
> 
> Hi,
> 
>> On 05/30/2016 05:22 PM, Marek Vasut wrote:
>>> Enable both features to reduce the SPL size by 6 kiB.
>>>
>>> Signed-off-by: Marek Vasut 
>>> Cc: Chin Liang See 
>>> Cc: Dinh Nguyen 
>>> Cc: Pavel Machek 
>>> Cc: Stefan Roese 
>>
>> I tried to use the raw MMC boot (on the sockit, with current master
>> + your patches), so I changed the following:
>>
>> --- a/include/configs/socfpga_common.h
>> +++ b/include/configs/socfpga_common.h
>> @@ -349,9 +349,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>> #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
>> #define CONFIG_SPL_LIBDISK_SUPPORT
>> #else
>> -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3
>> -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560
>> sect (1M+256k) */
>> -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
>> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 3
>> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 /* offset 512
>> sect (256k) */
>> +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 1000 /* 512 KB */
> 
> This should be 0x800 (was probably a typo in the original).
> Otherwise this should not break anything, yeah.
> 

I might be missing something obvious, but it actually seems that this
define isn't used outside of the include/configs/ folder...

>> +#define CONFIG_SPL_LIBDISK_SUPPORT
>> #endif
>> #endif
>>
>> AFAIK, there were two mistakes:
>> 1) FS_BOOT_PARTITION instead of RAW_MODE_U_BOOT
>> 2) CONFIG_SPL_LIBDISK_SUPPORT was missing
> 
> In fact, LIBDISK support was not used before you added the
> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION into the board config.
> The libdisk functions are needed for determining the start of the
> partition. Looking through the SPL MMC, the code originally loaded the
> u-boot image from a fixed offset on the card (2560 sectors), which is
> indeed not optimal.
> 

I agree, but I thought that the CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
option was a bit confusing in this context! And I did not realise
the behaviour would be to load from a fixed offset.

As soon as the tiny printf "issue" is solved, I'll send this patch
(as I don't want to break the build).

> So yes, please send the above patch, it'd be a nice improvement.
> 
>> (I edited the offset to be able to use u-boot-with-spl.sfp directly)
>>
>> With these settings, I think we run into the size problem reported
>> previously in the ML.
>>
>> So, enabling tiny printf could help, but we now get:
>>
>> disk/built-in.o: In function `part_get_info_extended':
>> ...u-boot/disk/part_dos.c:236: undefined reference to `sprintf'
>>
>> So I think we can just put "info->name[0] = 0;" instead of
>> the snprintf() calls, when using tiny printf.
> 
> There is more of that stuff in disk/ , at least part_efi.c and
> part_iso.c suffer from the exact same problem. I am not sure if
> setting the name to '\0' wouldn't break anything, CCing Simon
> as he was recently digging in those areas.
> 
> Also, take a look at this patch:
> https://patchwork.ozlabs.org/patch/626760/

Ah yes, I naively only looked at the part_dos.c file. Actually
a tiny snprintf implementation by Simon was already merged!

http://git.denx.de/?p=u-boot.git;a=commit;h=5c411d88be8df5f6a8a1ea0c961f7c35ba82c064

If I implement a naive sprintf() using this as a basis, I can boot
from MMC without tweaking anything else, but it adds ~730 bytes
to tiny-printf.o.

Thanks!
Sylvain

> 
>> I can submit those changes as two patches if it makes sense.
> 
> Please do.
> 
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[U-Boot] [PATCH v4] arm/arm64: implement a boot header capability

[Steve Rae]

From: Andre Przywara 

Some SPL loaders (like Allwinner's boot0, and Broadcom's boot0)
require a header before the actual U-Boot binary to both check its
validity and to find other data to load. Sometimes this header may
only be a few bytes of information, and sometimes this might simply
be space that needs to be reserved for a post-processing tool.

Introduce a config option to allow assembler preprocessor commands
to be inserted into the code at the appropriate location; typical
assembler preprocessor commands might be:
  .space 1000
  .word 0x12345678

Signed-off-by: Andre Przywara 
Signed-off-by: Steve Rae 
Commit Notes:
Please note that the current code:
  start.S (arm64) and
  vectors.S (arm)
already jumps over some portion of data already, so this option basically
just increases the size of this region (and the resulting binary).

For use with Allwinner's boot0 blob there is a tool called boot0img[1],
which fills the header to allow booting A64 based boards.
For the Pine64 we need a 1536 byte header (including the branch
instruction) at the moment, so we add this to the defconfig.

[1] https://github.com/apritzel/pine64/tree/master/tools
END

---

Changes in v4:
as per Tom Rini :
- move definitions out of the "include/configs/*" files
- rename definitions
and moved some of the commit message into commit notes.

Changes in v3:
( v3 submitted by: Steve Rae 
at the request of: Andre Przywara  )
- changed from just reserving space (with the .space command) to
executing the assembler preprocessor commands
( also updated the subject and the original commit messaage )

Changes in v2:
( by: Andre Przywara  )

Changes in v1:
( by: Andre Przywara  )

 arch/arm/Kconfig   |  8 
 arch/arm/cpu/armv8/start.S | 10 ++
 arch/arm/include/asm/arch-bcm281xx/boot0.h | 15 +++
 arch/arm/include/asm/arch-sunxi/boot0.h| 14 ++
 arch/arm/lib/vectors.S | 10 ++
 configs/bcm28155_ap_defconfig  |  1 +
 configs/bcm28155_w1d_defconfig |  1 +
 configs/pine64_plus_defconfig  |  1 +
 8 files changed, 60 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-bcm281xx/boot0.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/boot0.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5fd20b9..ddd49b1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -77,6 +77,14 @@ config SYS_L2CACHE_OFF
  If SoC does not support L2CACHE or one do not want to enable
  L2CACHE, choose this option.
 
+config ENABLE_ARM_SOC_BOOT0_HOOK
+   bool "prepare BOOT0 header"
+   help
+ If the SoC's BOOT0 requires a header area filled with (magic)
+ values, then choose this option, and create a define called
+ ARM_SOC_BOOT0_HOOK which contains the required assembler
+ preprocessor code.
+
 choice
prompt "Target select"
default TARGET_HIKEY
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index e933021..c1a2f45 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -21,6 +21,16 @@
 _start:
b   reset
 
+#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
+/*
+ * Various SoCs need something special and SoC-specific up front in
+ * order to boot, allow them to set that in their boot0.h file and then
+ * use it here.
+ */
+#include 
+ARM_SOC_BOOT0_HOOK
+#endif
+
.align 3
 
 .globl _TEXT_BASE
diff --git a/arch/arm/include/asm/arch-bcm281xx/boot0.h 
b/arch/arm/include/asm/arch-bcm281xx/boot0.h
new file mode 100644
index 000..7e72882
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm281xx/boot0.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2016 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __BOOT0_H
+#define __BOOT0_H
+
+/* BOOT0 header information */
+#define ARM_SOC_BOOT0_HOOK \
+   .word   0xbabeface; \
+   .word   _end - _start
+
+#endif /* __BOOT0_H */
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h 
b/arch/arm/include/asm/arch-sunxi/boot0.h
new file mode 100644
index 000..ea5675e
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -0,0 +1,14 @@
+/*
+ * Configuration settings for the Allwinner A64 (sun50i) CPU
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __BOOT0_H
+#define __BOOT0_H
+
+/* reserve space for BOOT0 header information */
+#define ARM_SOC_BOOT0_HOOK \
+   .space  1532
+
+#endif /* __BOOT0_H */
diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S
index 49238ed..5cc132b 100644
--- a/arch/arm/lib/vectors.S
+++ b/arch/arm/lib/vectors.S
@@ -60,6 +60,16 @@ _start:
ldr pc, _irq
ldr pc, _fiq
 
+#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
+/*
+ * Various SoCs need something special and 

[U-Boot] [RESEND RFC PATCH] zynq: add support for on-board shared reset gpio

[Andrea Merello]

I'm adding support [1] for another zynq-based board (MYIR Zturn [2]).

This board has one peculiarity that I have to deal with: it has a shared reset
signal that hits both the USB PHY and the Ethernet PHY, and this is routed to
a GPIO that must be shaken down and up before using those two pheripherals
(especially USB) in order to make things working.

This must be done before the two ethernet and USB drivers probes, so I couldn't
delegate this to any of the twos..

Right now I added a top-level node "board" to my DT containing the GPIO property
and I handle this in the board initialization code.

board {
phys-reset-gpio = < 51 GPIO_ACTIVE_LOW>;
};

RFC: is this a good/clean way to handle this thing? Ideally I would like to
put this mechanism out of the Zynq-specific board file, so that it could be
available for any kind of board..

(once a clean way to handle this thing have been agreed I'll rebase and I'll
post a patch serie for adding support for that board).

[1] https://github.com/andreamerello/u-boot-zynq
[2] http://www.myirtech.com/list.asp?id=502

Signed-off-by: Andrea Merello 
Cc: Michal Simek 

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 183f642..f72b219 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 

 DECLARE_GLOBAL_DATA_PTR;

@@ -70,8 +71,43 @@ int board_init(void)
return 0;
 }

+int phys_reset(void)
+{
+   struct gpio_desc reset_gpio;
+   int nodeoffset;
+   const void *blob = gd->fdt_blob;
+
+   nodeoffset = fdt_path_offset(blob, "/board");
+   if (nodeoffset == -FDT_ERR_NOTFOUND)
+   return 0;
+   if (nodeoffset < 0)
+   return nodeoffset;
+
+   gpio_request_by_name_nodev(blob, nodeoffset, "phys-reset-gpio", 0,
+  _gpio, 0);
+
+   if (dm_gpio_is_valid(_gpio)) {
+   /* reset PHYs (ethernet and USB) before any driver comes up */
+   dm_gpio_set_dir_flags(_gpio, reset_gpio.flags |
+   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+   mdelay(100);
+   dm_gpio_set_dir_flags(_gpio, (reset_gpio.flags |
+   GPIOD_IS_OUT) & ~GPIOD_IS_OUT_ACTIVE);
+
+   /* wait for PHYs to come up before going on */
+   mdelay(100);
+
+   printf("PHYs reset OK\n");
+   }
+
+   return 0;
+}
+
 int board_late_init(void)
 {
+   phys_reset();
+
switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
case ZYNQ_BM_NOR:
setenv("modeboot", "norboot");
--
2.1.4
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Re: [U-Boot] [PATCH 1/3] MIPS: Move cache sizes to Kconfig

[Zubair Lutfullah Kakakhel]

Marek Vasut  denx.de> writes:

...

> 
> Off-topic: Is malta that mipsfpga or is that something else ?
> Can I synthesise that mipsfpga into some altera FPGA ? If so, which one
> is a good pick ?

Hi Marek

Malta is a generic MIPS evaluation platform.
https://www.linux-mips.org/wiki/MIPS_Malta

MIPSfpga is currently for universities/academics.

A microAptiv core (including verilog source code) is given
to academics to play with. The whole pack includes teaching
resources, exercises, guides etc.

If you do come under the definition of a University/Academic,
do check it out https://community.imgtec.com/university/

Reference designs to run bare metal code runs on both Xilinx/Altera FPGAs.

However, reference designs to run the Linux Kernel are Xilinx specific.

Some more detail here.

https://kernel.org/doc/Documentation/devicetree/bindings/mips/img/xilfpga.txt

Hope that helps.

Thanks
ZubairLK

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Re: [U-Boot] [PATCH 1/2] drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl

[York Sun]

On 05/30/2016 08:18 PM, Shengzhou Liu wrote:
> 
>> -Original Message-
>> From: York Sun [mailto:york@nxp.com]
>> Sent: Tuesday, May 17, 2016 12:55 AM
>> To: Shengzhou Liu ; u-boot@lists.denx.de
>> Subject: Re: [PATCH 1/2] drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl
> 
>>
>> Shengzhou,
>>
>> Your understanding is correct. However, we have done analysis that the
>> additional bit is not used for finer adjustment. So unless you have a case
>> requiring values in the middle, I suggest to keep current code.
>>
>> York
> 
> York
> 
> On LS1046RDB, the clk_adj is 9, an odd instead of even data, so we have to 
> update it, and there will be more new boards in future with possibly odd 
> clk_adj.
> 

Shengzhou,

If you have to use an odd number for clk_adj, we can go ahead to merge these
patches. In my experience, clk_adj is very forgivable. If you have only one
value works, there is probably something wrong.

York


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Re: [U-Boot] [PATCH v2 1/8] board: ge: bx50v3: move detect_baseboard() out of CONFIG_VIDEO_IPUV3

[Andrew Shadura]

On 31/05/16 17:35, Stefano Babic wrote:
> But this generates a warning:
> 
> w+board/ge/bx50v3/bx50v3.c:324:12: warning: 'detect_baseboard' defined
> but not used [-Wunused-function]
> 
> Why do you export it if you do not need it ? It is used only in the hdmi
> detection, that means just if IPU is set.

Strange, it wouldn't compile here unless I did this. Apparently it *was*
used from somewhere else, but maybe it's no longer. Let me double check.

-- 
Cheers,
  Andrew



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Re: [U-Boot] [PATCH v3] arm64: arm: implement a boot header capability

[Tom Rini]

On Mon, May 30, 2016 at 11:37:47AM -0700, Steve Rae wrote:
> Hi Tom,
> 
> On Mon, May 30, 2016 at 11:14 AM, Tom Rini  wrote:
> >
> > On Mon, May 30, 2016 at 09:51:22AM -0700, Steve Rae wrote:
> >
> > > From: Andre Przywara 
> > >
> > > Some SPL loaders (like Allwinner's boot0, and Broadcom's boot0)
> > > require a header before the actual U-Boot binary to both check its
> > > validity and to find other data to load. Sometimes this header may
> > > only be a few bytes of information, and sometimes this might simply
> > > be space that needs to be reserved for a post-processing tool.
> > >
> > > Introduce a config option to allow assembler preprocessor commands
> > > to be inserted into the code at the appropriate location; typical
> > > preprocessor commands might be:
> > >   .space 1000
> > >   .word 0x12345678
> > > etc.
> > > Please note that the current code:
> > >   start.S (arm64) and
> > >   vectors.S (arm)
> > > already jumps over some portion of data already, so this option basically
> > > just increases the size of this region (and the resulting binary).
> > >
> > > For use with Allwinner's boot0 blob there is a tool called boot0img[1],
> > > which fills the header to allow booting A64 based boards.
> > > For the Pine64 we need a 1536 byte header (including the branch
> > > instruction) at the moment, so we add this to the defconfig.
> > >
> > > Signed-off-by: Andre Przywara 
> > > Signed-off-by: Steve Rae 
> >
> > I think this is a step in the right direction.
> Thanks
> 
> >
> > [snip]
> > > diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
> > > index e933021..9202889 100644
> > > --- a/arch/arm/cpu/armv8/start.S
> > > +++ b/arch/arm/cpu/armv8/start.S
> > > @@ -21,6 +21,10 @@
> > >  _start:
> > >   b   reset
> > >
> > > +#ifdef CONFIG_BOOT0_CODE
> > > +CONFIG_BOOT0_CODE
> > > +#endif
> > > +
> > >   .align 3
> >
> > I don't like adding things to the CONFIG name space that we can't
> > control the contents of via Kconfig.  So I think we need to change the
> > BOOT0_CODE portion to something like ARMV8_SOC_BOOT0_HOOK.  And if
> > there's some part of the ARMv8 docs we can reference that explains why
> > it's boot0 and at least 2 different SoCs have done this, we can use a
> > better name here.
> >
> OK, I follow your logic -- but this is not ARMV8 specific...
> In this commit:
> - Allwinner is arm64, but
> - Broadcom is arm (armv7l)
> so maybe just:
> SOC_BOOT0_HOOK ?
> And I don't know where the "BOOT0" terminology started - maybe it is
> in ARM/ARMV8 documentation; I just don't know

OK.  Yes, lets call it ARM_SOC_BOOT0_HOOK until/unless someone chimes in
with a better still name.

> > Then..
> > > diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
> > > index c1ae6f5..d2678c9 100644
> > > --- a/board/sunxi/Kconfig
> > > +++ b/board/sunxi/Kconfig
> > > @@ -15,6 +15,13 @@ config SUNXI_GEN_SUN6I
> > >   separate ahb reset control registers, custom pmic bus, new style
> > >   watchdog, etc.
> > >
> > > +config SUNXI_BOOT0
> > > + bool "prepare for boot0 header"
> > > + ---help---
> > > + If U-Boot is loaded from the Allwinner provided boot0 blob, it
> > > + expects a header area filled with magic values.
> > > + This option will add some space at the beginning of the image to
> > > + let a tool later on fill in this header with sensible data.
> >
> > This becomes something like ENABLE_ARMV8_SOC_BOOT0_HOOK and generic the
> > text a bit more here and mention the Allwinner and Broadcom examples.
> OK for the Allwinner...
> But I don't think the Broadcom boards are going to define SUNXI_BOOT0 ?!?!?!

Right.  But it should become ENABLE_ARM_SOC_BOOT0_HOOK and both
platforms (and other future ones probably) would enable it.

> > > diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h
> > > index 889e5db..515552b 100644
> > > --- a/include/configs/bcm28155_ap.h
> > > +++ b/include/configs/bcm28155_ap.h
> > > @@ -137,4 +137,8 @@
> > >  #define CONFIG_USB_GADGET_BCM_UDC_OTG_PHY
> > >  #define CONFIG_USBID_ADDR0x34052c46
> > >
> > > +#define CONFIG_BOOT0_CODE\
> > > + .word   0xbabeface; \
> > > + .word   _end - _start
> > > +
> >
> > Then this goes into arch/arm/include/asm/arch-bcm281xx/boot0.h or
> > similar?
> OK - I get that it shouldn't be in the (deprecated) include/configs 
> file(s)
> However, I didn't really want to add more #include lines to:
> arch/arm/cpu/armv8/start.S  or
> arch/arm/lib/vectors.S
> So, if I add your suggested filename, will it get "picked up" through
> the existing
> #include 
> ?

No, you would need to make both S files include  but I
think that's a logical thing to do.  I would be:
#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
#include 

/*
 * Various SoCs need something special and SoC-specific up front in
 * order to boot, allow them to set that in their boot0.h 

Re: [U-Boot] [RFC PATCH 1/5] spl: dfu: add dfu support in SPL

[Lukasz Majewski]

Hi Ravi,

> Hi Lukasz
> 
> >> without fat/ext4, mmc support. But all device support may increase 
> >> size.
> 
> > Ok.
> 
> > However, adding fat/ext4/mmc (and other) support should be on
> > demand (and enabled by proper Kconfig options). This would allow
> > others to add only what is really needed.
> 
> True, we provide incremental build option on need basis.  

+1

> 
> >> 
> >> >If yes, then even BBB's SPL can support DFU without any problems 
> >> >(105KiB < 128 KiB).
> >> 
> >> You mean BBB must have 128KB ? Can you confirm.
> 
> >I didn't find any _hard_ rule about the size.
> 
> >In the am335x_evm.h file the spice reserved for SPL (on raw eMMC) is
> >128 KiB.
> 
> Are you referring to eMMC raw boot option ?

Yes, this is LBA address of eMMC memory.

> 
> >> If BBB is support SPI boot, flashing MLO/U-boot to SPI-flash
> >> through SPL-DFU/SF would be sufficient right ?
> 
> >I don't know the exact use cases, but yes, BBB can boot from SPI
> >flash.
> 
> >I'm just wondering - the use case for your board is to use USB to
> >flash your device in u-boot SPL. If I might ask, why cannot you wait
> >for the U-Boot to use fully-fledged DFU for flashing?
> 
> Full-fledged DFU already supported in u-boot. 

This is a good news.

> The problem here is, how to flash the images first time to fresh
> boards to QSPI or eMMC device, where there is no MMC/SD boot
> option available. The solution to this problem is use peripheral USB
> boot mode (configuring sysboot switches), where the ROM loads the
> intial SPL(+DFU builtin for spi/eMMC) to IRAM, then run dfu/sf or
> dfu/eMMC to flash the binaries from PC using USB interface. Refer to
> SPL-DFU support based on 2014.07 u-boot
> http://www.ti.com/lit/an/sprac33/sprac33.pdf. 

I know about similar bootstrap (on TI board), which uses serial instead
of USB.

In this approach MLO was loaded by serial, then it loaded u-boot, which
was responsible for factory setting of the device (flashing rootfs,
boot and other partitions).

One question:

Would it be possible to develop SPL (MLO) for your platform, which does
following things:

1. Loads the full-fledge u-boot to SDRAM
2. Starts the u-boot and
3. u-boot flash all the needed stuff


By using such approach we could restrict our dfu support in SPL u-boot
only to receiving data and uploading it to SDRAM (i.e. we wouldn't
need to add write support for ext, fat and eMMC).



> 
> The SPL-DFU definitely helpful in production/development, where just
> connect EVM to PC through USB cable, and flash the MLO/U-BOOT,
> binaries to selected device (QSPI/eMMC).
> 
> I think based on discussion we had, some conclusion we could arrive, 
> 1) SPL size is constraint based on IRAM size, that all platform
> cannot be supported by default. 2) Kconfig option to compile only
> required device (eMMC, SPI) 3) Kconfig option for fat/ext4 support.
> 4) Try using common/spl/spl_fat{ext}.. to reduce footprint.
> 
> Regards
> Ravi 
> 



-- 
Best regards,

Lukasz Majewski

Samsung R Institute Poland (SRPOL) | Linux Platform Group
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Re: [U-Boot] [PATCH 06/11][v4] armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC

[York Sun]

On 05/31/2016 08:17 AM, Prabhakar Kushwaha wrote:
> The QorIQ LS1012A processor, optimized for battery-backed or
> USB-powered, integrates a single ARM Cortex-A53 core with a hardware
> packet forwarding engine and high-speed interfaces to deliver
> line-rate networking performance.
> 
> This patch add support of LS1012A SoC along with
>  - Update platform & DDR clock read logic as per SVR
>  - Define MMDC controller register set.
>  - Update LUT base address for PCIe
>  - Avoid L3 platform cache compilation
>  - Update USB address, errata
>  - SerDes table
>  - Added CSU IDs for SDHC2, SAI-1 to SAI-4
> 
> Signed-off-by: Calvin Johnson 
> Signed-off-by: Makarand Pawagi 
> Signed-off-by: Prabhakar Kushwaha 
> ---
> Changes for v2: Sending as it is
> Changes for v3: Incorporated York's comments
>   - Placed SoC overview in README.soc
> Changes for v4
>   - Incorporated Edward L Swarthout's comments
>   - Updated DDR speed
>   - Added defines for MMDC controller



> diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
> new file mode 100644
> index 000..31411f7
> --- /dev/null
> +++ b/include/fsl_mmdc.h
> @@ -0,0 +1,164 @@
> +/*
> + * Copyright 2016 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#ifndef FSL_MMDC_H
> +#define FSL_MMDC_H
> +
> +#define CONFIG_SYS_MMDC_CORE_ODT_TIMING  0x12554000
> +#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_00xbabf7954
> +#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_10xff328f64
> +#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_20x01ff00db
> +
> +#define CONFIG_SYS_MMDC_CORE_MISC0x0680
> +#define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT 0x0800
> +#define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY  0x2000
> +#define CONFIG_SYS_MMDC_PHY_ODT_CTRL 0x022a
> +
> +#define CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY  0x00bf1023
> +
> +#define CONFIG_SYS_MMDC_CORE_ADDR_PARTITION  0x007f
> +
> +#define CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL   0xa1390003
> +
> +#define  FORCE_ZQ_AUTO_CALIBRATION   (0x1 << 16)
> +
> +/* PHY Write Leveling Configuration and Error Status (MPWLGCR) */
> +#define WR_LVL_HW_EN 0x0001
> +
> +/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
> +#define MPR_COMPARE_EN   0x0001
> +
> +#define CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG 0x40404040
> +
> +/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
> +#define AUTO_RD_DQS_GATING_CALIBRATION_EN0x1000
> +
> +/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
> +#define AUTO_RD_CALIBRATION_EN   0x0010
> +
> +#define CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL   0x00030035
> +
> +#define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT   0x1067
> +
> +#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x103e8000
> +
> +#define START_REFRESH0x0001

Are these values board-specific?

York
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Re: [U-Boot] [PATCH 2/2] arm: socfpga: Enable tiny printf and simple malloc in SPL

[Marek Vasut]

On 05/31/2016 04:58 PM, Sylvain Lesne wrote:
> Hi,

Hi,

> On 05/30/2016 05:22 PM, Marek Vasut wrote:
>> Enable both features to reduce the SPL size by 6 kiB.
>>
>> Signed-off-by: Marek Vasut 
>> Cc: Chin Liang See 
>> Cc: Dinh Nguyen 
>> Cc: Pavel Machek 
>> Cc: Stefan Roese 
> 
> I tried to use the raw MMC boot (on the sockit, with current master
> + your patches), so I changed the following:
> 
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -349,9 +349,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
> #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
> #define CONFIG_SPL_LIBDISK_SUPPORT
> #else
> -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3
> -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560
> sect (1M+256k) */
> -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 3
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 /* offset 512
> sect (256k) */
> +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 1000 /* 512 KB */

This should be 0x800 (was probably a typo in the original).
Otherwise this should not break anything, yeah.

> +#define CONFIG_SPL_LIBDISK_SUPPORT
> #endif
> #endif
> 
> AFAIK, there were two mistakes:
> 1) FS_BOOT_PARTITION instead of RAW_MODE_U_BOOT
> 2) CONFIG_SPL_LIBDISK_SUPPORT was missing

In fact, LIBDISK support was not used before you added the
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION into the board config.
The libdisk functions are needed for determining the start of the
partition. Looking through the SPL MMC, the code originally loaded the
u-boot image from a fixed offset on the card (2560 sectors), which is
indeed not optimal.

So yes, please send the above patch, it'd be a nice improvement.

> (I edited the offset to be able to use u-boot-with-spl.sfp directly)
> 
> With these settings, I think we run into the size problem reported
> previously in the ML.
> 
> So, enabling tiny printf could help, but we now get:
> 
> disk/built-in.o: In function `part_get_info_extended':
> ...u-boot/disk/part_dos.c:236: undefined reference to `sprintf'
>
> So I think we can just put "info->name[0] = 0;" instead of
> the snprintf() calls, when using tiny printf.

There is more of that stuff in disk/ , at least part_efi.c and
part_iso.c suffer from the exact same problem. I am not sure if
setting the name to '\0' wouldn't break anything, CCing Simon
as he was recently digging in those areas.

Also, take a look at this patch:
https://patchwork.ozlabs.org/patch/626760/

> I can submit those changes as two patches if it makes sense.

Please do.

> Thanks,
> Sylvain
> 


-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2 1/8] board: ge: bx50v3: move detect_baseboard() out of CONFIG_VIDEO_IPUV3

[Stefano Babic]

Hi Andrew,

On 30/05/2016 13:37, Andrew Shadura wrote:
> detect_baseboard() function doesn't depend on CONFIG_VIDEO_IPUV3.
> Make sure it's available when CONFIG_VIDEO_IPUV3 is off.
> 
> Signed-off-by: Andrew Shadura 
> ---
>  board/ge/bx50v3/bx50v3.c | 18 +-
>  1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
> index ff8f4d7..e167cd5 100644
> --- a/board/ge/bx50v3/bx50v3.c
> +++ b/board/ge/bx50v3/bx50v3.c
> @@ -321,6 +321,15 @@ int board_phy_config(struct phy_device *phydev)
>   return 0;
>  }
>  
> +static int detect_baseboard(struct display_info_t const *dev)
> +{
> + if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) ||
> + IS_ENABLED(CONFIG_TARGET_GE_B650V3))
> + return 1;
> +
> + return 0;
> +}
> +
>  #if defined(CONFIG_VIDEO_IPUV3)
>  static iomux_v3_cfg_t const backlight_pads[] = {
>   /* Power for LVDS Display */
> @@ -345,15 +354,6 @@ int board_cfb_skip(void)
>   return 0;
>  }
>  
> -static int detect_baseboard(struct display_info_t const *dev)
> -{
> - if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) ||
> - IS_ENABLED(CONFIG_TARGET_GE_B650V3))
> - return 1;
> -
> - return 0;
> -}
> -
>  struct display_info_t const displays[] = {{
>   .bus= -1,
>   .addr   = -1,
> 

But this generates a warning:

w+board/ge/bx50v3/bx50v3.c:324:12: warning: 'detect_baseboard' defined
but not used [-Wunused-function]

Why do you export it if you do not need it ? It is used only in the hdmi
detection, that means just if IPU is set.

Best regards,
Stefano Babic

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[U-Boot] [PATCH 07/11][v4] board: freescale: common: Conditionally compile IFC QXIS func

[Prabhakar Kushwaha]

From: Abhimanyu Saini 

Check if qixis supports memory-mapped read/write
before compiling IFC based qixis read/write functions.

Signed-off-by: Calvin Johnson 
Signed-off-by: Abhimanyu Saini 
Signed-off-by: Prabhakar Kushwaha 
---
Chages for v2: New patch in this patch-set
Chages for v3: Sending as it is
Chages for v4: Sending as it is

 board/freescale/common/qixis.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 113295f..2e35d41 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -27,6 +27,7 @@ void qixis_write_i2c(unsigned int reg, u8 value)
 }
 #endif
 
+#ifdef QIXIS_BASE
 u8 qixis_read(unsigned int reg)
 {
void *p = (void *)QIXIS_BASE;
@@ -40,6 +41,7 @@ void qixis_write(unsigned int reg, u8 value)
 
out_8(p + reg, value);
 }
+#endif
 
 u16 qixis_read_minor(void)
 {
-- 
1.9.1


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[U-Boot] [PATCH 10/11][v4] armv8: ls1012a: Add support of ls1012ardb board

[Prabhakar Kushwaha]

QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

Signed-off-by: Calvin Johnson 
Signed-off-by: Pratiyush Mohan Srivastava 
Signed-off-by: Prabhakar Kushwaha 
---
Changes for v2: Sending as it is
Changes for v3: Incorporated York's comments
Changes for v4: Incorporated Alex and York's comments
- removed ddr init magic numbers
- updated file license
- define pcie, sata, sdhc define in rdb.h
- use arch_fixup_fdt

 arch/arm/Kconfig|  10 ++
 arch/arm/dts/Makefile   |   3 +-
 arch/arm/dts/fsl-ls1012a-rdb.dts|  16 +++
 arch/arm/dts/fsl-ls1012a-rdb.dtsi   |  39 ++
 board/freescale/ls1012ardb/Kconfig  |  15 +++
 board/freescale/ls1012ardb/MAINTAINERS  |   6 +
 board/freescale/ls1012ardb/Makefile |   7 +
 board/freescale/ls1012ardb/README   |  54 
 board/freescale/ls1012ardb/ls1012ardb.c | 223 
 configs/ls1012ardb_qspi_defconfig   |  32 +
 include/configs/ls1012ardb.h| 107 +++
 11 files changed, 511 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dts
 create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dtsi
 create mode 100644 board/freescale/ls1012ardb/Kconfig
 create mode 100644 board/freescale/ls1012ardb/MAINTAINERS
 create mode 100644 board/freescale/ls1012ardb/Makefile
 create mode 100644 board/freescale/ls1012ardb/README
 create mode 100644 board/freescale/ls1012ardb/ls1012ardb.c
 create mode 100644 configs/ls1012ardb_qspi_defconfig
 create mode 100644 include/configs/ls1012ardb.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 30fc32a..9be8c2b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -705,6 +705,15 @@ config TARGET_LS1012AQDS
  development platform that supports the QorIQ LS1012A
  Layerscape Architecture processor.
 
+config TARGET_LS1012ARDB
+   bool "Support ls1012ardb"
+   select ARM64
+   help
+ Support for Freescale LS1012ARDB platform.
+ The LS1012A Reference design board (RDB) is a high-performance
+ development platform that supports the QorIQ LS1012A
+ Layerscape Architecture processor.
+
 config TARGET_LS1021AQDS
bool "Support ls1021aqds"
select CPU_V7
@@ -862,6 +871,7 @@ source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
+source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 47ec7a2..f021699 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -121,7 +121,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
-   fsl-ls1012a-qds.dtb
+   fsl-ls1012a-qds.dtb \
+   fsl-ls1012a-rdb.dtb
 
 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
 
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dts b/arch/arm/dts/fsl-ls1012a-rdb.dts
new file mode 100644
index 000..f683812
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-rdb.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-rdb.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi 
b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
new file mode 100644
index 000..bf407ae
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
@@ -0,0 +1,39 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+   model = "LS1012A RDB Board";
+   aliases {
+   spi0 = 
+   };
+};
+
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fl128s@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
diff --git 

Re: [U-Boot] [PATCH 2/2] arm: socfpga: Enable tiny printf and simple malloc in SPL

[Sylvain Lesne]

Hi,

On 05/30/2016 05:22 PM, Marek Vasut wrote:
> Enable both features to reduce the SPL size by 6 kiB.
>
> Signed-off-by: Marek Vasut 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Pavel Machek 
> Cc: Stefan Roese 

I tried to use the raw MMC boot (on the sockit, with current master
+ your patches), so I changed the following:

--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -349,9 +349,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
#define CONFIG_SPL_LIBDISK_SUPPORT
#else
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560
sect (1M+256k) */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 3
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 /* offset 512
sect (256k) */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 1000 /* 512 KB */
+#define CONFIG_SPL_LIBDISK_SUPPORT
#endif
#endif

AFAIK, there were two mistakes:
1) FS_BOOT_PARTITION instead of RAW_MODE_U_BOOT
2) CONFIG_SPL_LIBDISK_SUPPORT was missing

(I edited the offset to be able to use u-boot-with-spl.sfp directly)

With these settings, I think we run into the size problem reported
previously in the ML.

So, enabling tiny printf could help, but we now get:

disk/built-in.o: In function `part_get_info_extended':
...u-boot/disk/part_dos.c:236: undefined reference to `sprintf'

So I think we can just put "info->name[0] = 0;" instead of
the snprintf() calls, when using tiny printf.

I can submit those changes as two patches if it makes sense.

Thanks,
Sylvain
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[U-Boot] [PATCH 08/11][v4] board: freescale: common: Add flag for LBMAP brdcfg reg offset

[Prabhakar Kushwaha]

From: Abhimanyu Saini 

Add QIXIS_LBMAP_BRDCFG_REG to the save offset of LBMAP
configuration register instead of hardcoding it in
set_lbmap() function.

Signed-off-by: Calvin Johnson 
Signed-off-by: Abhimanyu Saini 
Signed-off-by: Prabhakar Kushwaha 
---
Chages for v2: New patch in this patch-set
Chages for v3: Sending as it is
Chages for v4: Sending as it is

 board/freescale/common/qixis.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 2e35d41..0db0ed6 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -14,6 +14,13 @@
 #include 
 #include "qixis.h"
 
+#ifndef QIXIS_LBMAP_BRDCFG_REG
+/*
+ * For consistency with existing platforms
+ */
+#define QIXIS_LBMAP_BRDCFG_REG 0x00
+#endif
+
 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
 u8 qixis_read_i2c(unsigned int reg)
 {
@@ -144,9 +151,9 @@ static void __maybe_unused set_lbmap(int lbmap)
 {
u8 reg;
 
-   reg = QIXIS_READ(brdcfg[0]);
+   reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
-   QIXIS_WRITE(brdcfg[0], reg);
+   QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg);
 }
 
 static void __maybe_unused set_rcw_src(int rcw_src)
-- 
1.9.1


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[U-Boot] [PATCH 11/11][v4] armv8: ls1012a: Add support of ls1012afrdm board

[Prabhakar Kushwaha]

QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance
development platform, with a complete debugging environment.
The LS1012AFRDM board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

Signed-off-by: Shengzhou Liu 
Signed-off-by: Calvin Johnson 
Signed-off-by: Pratiyush Mohan Srivastava 
Signed-off-by: Prabhakar Kushwaha 
---
Changes for v4: New patch in this patch-set

 arch/arm/Kconfig  |  10 ++
 arch/arm/dts/Makefile |   3 +-
 arch/arm/dts/fsl-ls1012a-frdm.dts |  16 +++
 arch/arm/dts/fsl-ls1012a-frdm.dtsi|  37 ++
 board/freescale/ls1012afrdm/Kconfig   |  15 +++
 board/freescale/ls1012afrdm/MAINTAINERS   |   6 +
 board/freescale/ls1012afrdm/Makefile  |   7 ++
 board/freescale/ls1012afrdm/README|  58 +
 board/freescale/ls1012afrdm/ls1012afrdm.c | 191 ++
 configs/ls1012afrdm_qspi_defconfig|  29 +
 include/configs/ls1012afrdm.h |  44 +++
 11 files changed, 415 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dts
 create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dtsi
 create mode 100644 board/freescale/ls1012afrdm/Kconfig
 create mode 100644 board/freescale/ls1012afrdm/MAINTAINERS
 create mode 100644 board/freescale/ls1012afrdm/Makefile
 create mode 100644 board/freescale/ls1012afrdm/README
 create mode 100644 board/freescale/ls1012afrdm/ls1012afrdm.c
 create mode 100644 configs/ls1012afrdm_qspi_defconfig
 create mode 100644 include/configs/ls1012afrdm.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9be8c2b..71169b2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -714,6 +714,15 @@ config TARGET_LS1012ARDB
  development platform that supports the QorIQ LS1012A
  Layerscape Architecture processor.
 
+config TARGET_LS1012AFRDM
+   bool "Support ls1012afrdm"
+   select ARM64
+   help
+ Support for Freescale LS1012AFRDM platform.
+ The LS1012A Freedom  board (FRDM) is a high-performance
+ development platform that supports the QorIQ LS1012A
+ Layerscape Architecture processor.
+
 config TARGET_LS1021AQDS
bool "Support ls1021aqds"
select CPU_V7
@@ -872,6 +881,7 @@ source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
+source "board/freescale/ls1012afrdm/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f021699..e8ad6c6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -122,7 +122,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
fsl-ls1012a-qds.dtb \
-   fsl-ls1012a-rdb.dtb
+   fsl-ls1012a-rdb.dtb \
+   fsl-ls1012a-frdm.dtb
 
 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
 
diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dts 
b/arch/arm/dts/fsl-ls1012a-frdm.dts
new file mode 100644
index 000..983e599
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-frdm.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-frdm.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dtsi 
b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
new file mode 100644
index 000..25dcdd2
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
@@ -0,0 +1,37 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+   model = "LS1012A FREEDOM Board";
+   aliases {
+   spi0 = 
+   };
+};
+
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fl128s@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
diff --git a/board/freescale/ls1012afrdm/Kconfig 
b/board/freescale/ls1012afrdm/Kconfig
new file mode 100644
index 000..a34521c
--- /dev/null
+++ b/board/freescale/ls1012afrdm/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1012AFRDM
+
+config SYS_BOARD
+   default "ls1012afrdm"
+
+config SYS_VENDOR
+   default "freescale"
+
+config SYS_SOC
+   default 

[U-Boot] [PATCH 09/11][v4] armv8: ls1012a: Add support of ls1012aqds board

[Prabhakar Kushwaha]

QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
development platform, with a complete debugging environment.
The LS1012AQDS board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

Signed-off-by: Calvin Johnson 
Signed-off-by: Pratiyush Mohan Srivastava 
Signed-off-by: Abhimanyu Saini 
Signed-off-by: Prabhakar Kushwaha 
---
Changes for v2: 
  - Added support of qixis over i2c
  - print fpga, board info using qixis
Changes for v3: Incorporated York's comments
Changes for v4: Incorporated Alex and York's comments
- Removed ddr magic number
- updated license
- move PCie, SATA, SDHC define from common to qds.h
- use arch_fixup_fdt

 arch/arm/Kconfig  |  10 ++
 arch/arm/dts/Makefile |   3 +-
 arch/arm/dts/fsl-ls1012a-qds.dts  |  14 ++
 arch/arm/dts/fsl-ls1012a-qds.dtsi | 123 ++
 arch/arm/dts/fsl-ls1012a.dtsi | 119 +
 board/freescale/ls1012aqds/Kconfig|  15 ++
 board/freescale/ls1012aqds/MAINTAINERS|   6 +
 board/freescale/ls1012aqds/Makefile   |   7 +
 board/freescale/ls1012aqds/README |  59 +++
 board/freescale/ls1012aqds/ls1012aqds.c   | 233 ++
 board/freescale/ls1012aqds/ls1012aqds_qixis.h |  35 
 configs/ls1012aqds_qspi_defconfig |  32 
 include/configs/ls1012a_common.h  | 145 
 include/configs/ls1012aqds.h  | 191 +
 14 files changed, 991 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dts
 create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dtsi
 create mode 100644 arch/arm/dts/fsl-ls1012a.dtsi
 create mode 100644 board/freescale/ls1012aqds/Kconfig
 create mode 100644 board/freescale/ls1012aqds/MAINTAINERS
 create mode 100644 board/freescale/ls1012aqds/Makefile
 create mode 100644 board/freescale/ls1012aqds/README
 create mode 100644 board/freescale/ls1012aqds/ls1012aqds.c
 create mode 100644 board/freescale/ls1012aqds/ls1012aqds_qixis.h
 create mode 100644 configs/ls1012aqds_qspi_defconfig
 create mode 100644 include/configs/ls1012a_common.h
 create mode 100644 include/configs/ls1012aqds.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7a77b6a..30fc32a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -696,6 +696,15 @@ config TARGET_HIKEY
  Support for HiKey 96boards platform. It features a HI6220
  SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
 
+config TARGET_LS1012AQDS
+   bool "Support ls1012aqds"
+   select ARM64
+   help
+ Support for Freescale LS1012AQDS platform.
+ The LS1012A Development System (QDS) is a high-performance
+ development platform that supports the QorIQ LS1012A
+ Layerscape Architecture processor.
+
 config TARGET_LS1021AQDS
bool "Support ls1021aqds"
select CPU_V7
@@ -852,6 +861,7 @@ source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
+source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 92c7545..47ec7a2 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -120,7 +120,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
-   fsl-ls1043a-rdb.dtb
+   fsl-ls1043a-rdb.dtb \
+   fsl-ls1012a-qds.dtb
 
 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
 
diff --git a/arch/arm/dts/fsl-ls1012a-qds.dts b/arch/arm/dts/fsl-ls1012a-qds.dts
new file mode 100644
index 000..76db36c
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-qds.dts
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-qds.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi 
b/arch/arm/dts/fsl-ls1012a-qds.dtsi
new file mode 100644
index 000..dde7134
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+   model = "LS1012A QDS Board";
+   aliases {
+   spi0 = 
+   spi1 = 
+   };
+};
+
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   dflash0: n25q128a {
+   #address-cells = 

[U-Boot] [PATCH 05/11][v4] armv8: fsl-layerscape: Organize SoC overview at common location

[Prabhakar Kushwaha]

SoC overviews are getting repeated across board folders.
So, Organize SoC overview at common location i.e. fsl-layerscape/doc

Also move README.lsch2 and README.lsch3 in same folder.

Signed-off-by: Prabhakar Kushwaha 
---
Changes for v3: New patch in the list
Changes for v4: Sending as it  is

 .../armv8/fsl-layerscape/{ => doc}/README.lsch2|  0
 .../armv8/fsl-layerscape/{ => doc}/README.lsch3|  0
 arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc   | 86 ++
 board/freescale/ls1043aqds/README  | 37 +-
 board/freescale/ls1043ardb/README  | 37 +-
 board/freescale/ls2080aqds/README  | 45 +--
 board/freescale/ls2080ardb/README  | 45 +--
 7 files changed, 96 insertions(+), 154 deletions(-)
 rename arch/arm/cpu/armv8/fsl-layerscape/{ => doc}/README.lsch2 (100%)
 rename arch/arm/cpu/armv8/fsl-layerscape/{ => doc}/README.lsch3 (100%)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 
b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
similarity index 100%
rename from arch/arm/cpu/armv8/fsl-layerscape/README.lsch2
rename to arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 
b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
similarity index 100%
rename from arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
rename to arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc 
b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
new file mode 100644
index 000..a4130ce
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -0,0 +1,86 @@
+SoC overview
+
+   1. LS1043A
+   2. LS2080A
+
+LS1043A
+-
+The LS1043A integrated multicore processor combines four ARM Cortex-A53
+processor cores with datapath acceleration optimized for L2/3 packet
+processing, single pass security offload and robust traffic management
+and quality of service.
+
+The LS1043A SoC includes the following function and features:
+ - Four 64-bit ARM Cortex-A53 CPUs
+ - 1 MB unified L2 Cache
+ - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
+   support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
+   the following functions:
+   - Packet parsing, classification, and distribution (FMan)
+   - Queue management for scheduling, packet sequencing, and congestion
+ management (QMan)
+   - Hardware buffer management for buffer allocation and de-allocation (BMan)
+   - Cryptography acceleration (SEC)
+ - Ethernet interfaces by FMan
+   - Up to 1 x XFI supporting 10G interface
+   - Up to 1 x QSGMII
+   - Up to 4 x SGMII supporting 1000Mbps
+   - Up to 2 x SGMII supporting 2500Mbps
+   - Up to 2 x RGMII supporting 1000Mbps
+ - High-speed peripheral interfaces
+   - Three PCIe 2.0 controllers, one supporting x4 operation
+   - One serial ATA (SATA 3.0) controllers
+ - Additional peripheral interfaces
+   - Three high-speed USB 3.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (eSDXC/eMMC)
+   - Quad Serial Peripheral Interface (QSPI) Controller
+   - Serial peripheral interface (SPI) controller
+   - Four I2C controllers
+   - Two DUARTs
+   - Integrated flash controller supporting NAND and NOR flash
+ - QorIQ platform's trust architecture 2.1
+
+LS2080A
+
+The LS2080A integrated multicore processor combines eight ARM Cortex-A57
+processor cores with high-performance data path acceleration logic and network
+and peripheral bus interfaces required for networking, telecom/datacom,
+wireless infrastructure, and mil/aerospace applications.
+
+The LS2080A SoC includes the following function and features:
+
+ - Eight 64-bit ARM Cortex-A57 CPUs
+ - 1 MB platform cache with ECC
+ - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
+ - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
+  the AIOP
+ - Data path acceleration architecture (DPAA2) incorporating acceleration for
+ the following functions:
+   - Packet parsing, classification, and distribution (WRIOP)
+   - Queue and Hardware buffer management for scheduling, packet sequencing, 
and
+ congestion management, buffer allocation and de-allocation (QBMan)
+   - Cryptography acceleration (SEC) at up to 10 Gbps
+   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
+   - Decompression/compression acceleration (DCE) at up to 20 Gbps
+   - Accelerated I/O processing (AIOP) at up to 20 Gbps
+   - QDMA engine
+ - 16 SerDes lanes at up to 10.3125 GHz
+ - Ethernet interfaces
+   - Up to eight 10 Gbps Ethernet MACs
+   - Up to eight 1 / 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+   - Four PCIe 3.0 controllers, one supporting SR-IOV
+ - Additional peripheral interfaces
+   

[U-Boot] [PATCH 06/11][v4] armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC

[Prabhakar Kushwaha]

The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.

This patch add support of LS1012A SoC along with
 - Update platform & DDR clock read logic as per SVR
 - Define MMDC controller register set.
 - Update LUT base address for PCIe
 - Avoid L3 platform cache compilation
 - Update USB address, errata
 - SerDes table
 - Added CSU IDs for SDHC2, SAI-1 to SAI-4

Signed-off-by: Calvin Johnson 
Signed-off-by: Makarand Pawagi 
Signed-off-by: Prabhakar Kushwaha 
---
Changes for v2: Sending as it is
Changes for v3: Incorporated York's comments
- Placed SoC overview in README.soc
Changes for v4
- Incorporated Edward L Swarthout's comments
- Updated DDR speed
- Added defines for MMDC controller

 arch/arm/cpu/armv8/fsl-layerscape/Makefile |   4 +
 arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc   |  43 ++
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c |  11 ++
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   |   2 +
 arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c |  74 ++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c|   2 +
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  29 
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |   1 +
 .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |   1 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |   4 +
 .../include/asm/arch-fsl-layerscape/ns_access.h|  10 ++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |   1 +
 include/fsl_mmdc.h | 164 +
 include/linux/usb/xhci-fsl.h   |   6 +-
 14 files changed, 351 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
 create mode 100644 include/fsl_mmdc.h

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile 
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 5f86ef9..eb2cbc3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -28,3 +28,7 @@ endif
 ifneq ($(CONFIG_LS1043A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
 endif
+
+ifneq ($(CONFIG_LS1012A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
+endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc 
b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
index a4130ce..8eee016 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -2,6 +2,7 @@ SoC overview
 
1. LS1043A
2. LS2080A
+   3. LS1012A
 
 LS1043A
 -
@@ -84,3 +85,45 @@ The LS2080A SoC includes the following function and features:
  - QorIQ platform's trust architecture 3.0
  - Service processor (SP) provides pre-boot initialization and secure-boot
   capabilities
+
+LS1012A
+
+The LS1012A features an advanced 64-bit ARM v8 Cortex-
+A53 processor, with 32 KB of parity protected L1-I cache,
+32 KB of ECC protected L1-D cache, as well as 256 KB of
+ECC protected L2 cache.
+
+The LS1012A SoC includes the following function and features:
+ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
+ - ARM v8 cryptography extensions
+ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
+16-/8-bit operation (no ECC support)
+ - ARM core-link CCI-400 cache coherent interconnect
+ - Packet Forwarding Engine (PFE)
+ - Cryptography acceleration (SEC)
+ - Ethernet interfaces supported by PFE:
+ - One Configurable x3 SerDes:
+Two Serdes PLLs supported for usage by any SerDes data lane
+Support for up to 6 GBaud operation
+ - High-speed peripheral interfaces:
+ - One PCI Express Gen2 controller, supporting x1 operation
+ - One serial ATA (SATA Gen 3.0) controller
+ - One USB 3.0/2.0 controller with integrated PHY
+ - One USB 2.0 controller with ULPI interface. .
+ - Additional peripheral interfaces:
+- One quad serial peripheral interface (QuadSPI) controller
+- One serial peripheral interface (SPI) controller
+- Two enhanced secure digital host controllers
+- Two I2C controllers
+- One 16550 compliant DUART (two UART interfaces)
+- Two general purpose IOs (GPIO)
+- Two FlexTimers
+- Five synchronous audio interfaces (SAI)
+- Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
+- Single-source clocking solution enabling generation of core, platform,
+DDR, SerDes, and USB clocks from a single external crystal and internal
+crystaloscillator
+- Thermal monitor unit (TMU) with +/- 3C accuracy
+- Two WatchDog timers
+- ARM generic timer
+ - QorIQ platform's trust architecture 2.1
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c 

[U-Boot] [PATCH 03/11][v4] driver: mtd: spi: Adding support for QSPI flash

[Prabhakar Kushwaha]

Serial number, vendor id and page size are added for QSPI flash
common on both LS1012AQDS and LS1012ARDB i.e. S25FS512SDSMFI011.

Signed-off-by: Pratiyush Mohan Srivastava 
Signed-off-by: Calvin Johnson 
Signed-off-by: Mingkai Hu 
Signed-off-by: Prabhakar Kushwaha 
---
Changes for v2: Sending as it is
Changes for v3: Sending as it is
Changes for v4: Sending as it is

 drivers/mtd/spi/sf_params.c | 1 +
 drivers/mtd/spi/spi_flash.c | 5 +++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 4f37e33..c577d9e 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -67,6 +67,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
{"S25FL128S_64K",  0x012018, 0x4d01,64 * 1024,   256, RD_FULL,  
 WR_QPP},
{"S25FL256S_256K", 0x010219, 0x4d00,   256 * 1024,   128, RD_FULL,  
 WR_QPP},
{"S25FL256S_64K",  0x010219, 0x4d01,64 * 1024,   512, RD_FULL,  
 WR_QPP},
+   {"S25FS512S",  0x010220, 0x4D00,   128 * 1024,   512, RD_FULL,  
 WR_QPP},
{"S25FL512S_256K", 0x010220, 0x4d00,   256 * 1024,   256, RD_FULL,  
 WR_QPP},
{"S25FL512S_64K",  0x010220, 0x4d01,64 * 1024,  1024, RD_FULL,  
 WR_QPP},
{"S25FL512S_512K", 0x010220, 0x4f00,   256 * 1024,   256, RD_FULL,  
 WR_QPP},
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index fa0e799..64d4e0f 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1072,7 +1072,8 @@ int spi_flash_scan(struct spi_flash *flash)
 * sector that is not overlaid by the parameter sectors.
 * The uniform sector erase command has no effect on parameter sectors.
 */
-   if (jedec == 0x0219 && (ext_jedec & 0xff00) == 0x4d00) {
+   if ((jedec == 0x0219 || (jedec == 0x0220)) &&
+   (ext_jedec & 0xff00) == 0x4d00) {
int ret;
u8 id[6];
 
@@ -1146,7 +1147,7 @@ int spi_flash_scan(struct spi_flash *flash)
 * have 256b pages.
 */
if (ext_jedec == 0x4d00) {
-   if ((jedec == 0x0215) || (jedec == 0x216))
+   if ((jedec == 0x0215) || (jedec == 0x216) || (jedec == 0x220))
flash->page_size = 256;
else
flash->page_size = 512;
-- 
1.9.1


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[U-Boot] [PATCH 04/11][v4] armv8: fsl-layerscape: fix compile warning "rcw_tmp"

[Prabhakar Kushwaha]

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c: In function
‘get_sys_info’:
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c:29:6: warning:
unused variable ‘rcw_tmp’ [-Wunused-variable]
  u32 rcw_tmp;

Signed-off-by: Prabhakar Kushwaha 
---
Changes for v2: Sending as it is
Changes for v3: Sending as it is
Changes for v4: Sending as it is

 arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 453a93d..4fc3186 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -25,7 +25,10 @@ void get_sys_info(struct sys_info *sys_info)
struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
u32 ccr;
 #endif
-#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN)
+#if (defined(CONFIG_FSL_ESDHC) &&\
+   defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
+   defined(CONFIG_SYS_DPAA_FMAN)
+
u32 rcw_tmp;
 #endif
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
-- 
1.9.1


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[U-Boot] [PATCH 01/11][v4] armv8: fsl-layerscape: Put SMMU config code in SMMU_BASE

[Prabhakar Kushwaha]

It is not mandatory for Layerscape SoCs to have SMMU. SoCs like
LS1012A are layerscape SoC without SMMU IP.

So put SMMU configuration code under SMMU_BASE.

Signed-off-by: Prabhakar Kushwaha 
---
Changes for v2: Sending as it is
Changes for v3: Sending as it is
Changes for v4: Sending as it is

 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 04831ca..d743ffe 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -94,11 +94,13 @@ ENTRY(lowlevel_init)
bl  ccn504_set_qos
 #endif
 
+#ifdef SMMU_BASE
/* Set the SMMU page size in the sACR register */
ldr x1, =SMMU_BASE
ldr w0, [x1, #0x10]
orr w0, w0, #1 << 16  /* set sACR.pagesize to indicate 64K page */
str w0, [x1, #0x10]
+#endif
 
/* Initialize GIC Secure Bank Status */
 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
-- 
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[U-Boot] [PATCH 00/11] [v4] armv8: fsl-layerscape: Add support of LS1012A SoC and platform

[Prabhakar Kushwaha]

The QorIQ LS1012A processor is a new Freescale' SoC optimized for 
battery-backed or USB-powered, integrates a single ARM Cortex-A53
core with a hardware packet forwarding engine and high-speed 
interfaces to deliver line-rate networking performance.

LS1012AQDS, LS1012ARDB and LS1012AFRDM are a high-performance
development platform using LS1012A SoC.

Changes for v2: Add support of board, fpga info and qixis_reset for QDS
Changes for v3: Incorporated York's comments
Changes for v4:
- Incorporated york's comments
- updated file license
- Incorporated review comments from Edward L Swarthou, Alex
- Removed DDR init magic numbers

Abhimanyu Saini (2):
  board: freescale: common: Conditionally compile IFC QXIS func
  board: freescale: common: Add flag for LBMAP brdcfg reg offset

Prabhakar Kushwaha (9):
  armv8: fsl-layerscape: Put SMMU config code in SMMU_BASE
  armv8: fsl-layerscape: Avoid LS1043A specifc defines
  driver: mtd: spi: Adding support for QSPI flash
  armv8: fsl-layerscape: fix compile warning "rcw_tmp"
  armv8: fsl-layerscape: Organize SoC overview at common location
  armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC
  armv8: ls1012a: Add support of ls1012aqds board
  armv8: ls1012a: Add support of ls1012ardb board
  armv8: ls1012a: Add support of ls1012afrdm board

 arch/arm/Kconfig   |  30 +++
 arch/arm/cpu/armv8/fsl-layerscape/Makefile |   4 +
 .../armv8/fsl-layerscape/{ => doc}/README.lsch2|   0
 .../armv8/fsl-layerscape/{ => doc}/README.lsch3|   0
 arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc   | 129 
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c |  16 +-
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   |   4 +
 arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c |  74 +++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c|   4 +-
 arch/arm/dts/Makefile  |   5 +-
 arch/arm/dts/fsl-ls1012a-frdm.dts  |  16 ++
 arch/arm/dts/fsl-ls1012a-frdm.dtsi |  37 
 arch/arm/dts/fsl-ls1012a-qds.dts   |  14 ++
 arch/arm/dts/fsl-ls1012a-qds.dtsi  | 123 +++
 arch/arm/dts/fsl-ls1012a-rdb.dts   |  16 ++
 arch/arm/dts/fsl-ls1012a-rdb.dtsi  |  39 
 arch/arm/dts/fsl-ls1012a.dtsi  | 119 +++
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  29 +++
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |   1 +
 .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |   3 +-
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |   4 +
 .../include/asm/arch-fsl-layerscape/ns_access.h|  10 +
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |   1 +
 board/freescale/common/qixis.c |  13 +-
 board/freescale/ls1012afrdm/Kconfig|  15 ++
 board/freescale/ls1012afrdm/MAINTAINERS|   6 +
 board/freescale/ls1012afrdm/Makefile   |   7 +
 board/freescale/ls1012afrdm/README |  58 +
 board/freescale/ls1012afrdm/ls1012afrdm.c  | 191 +
 board/freescale/ls1012aqds/Kconfig |  15 ++
 board/freescale/ls1012aqds/MAINTAINERS |   6 +
 board/freescale/ls1012aqds/Makefile|   7 +
 board/freescale/ls1012aqds/README  |  59 ++
 board/freescale/ls1012aqds/ls1012aqds.c| 233 +
 board/freescale/ls1012aqds/ls1012aqds_qixis.h  |  35 
 board/freescale/ls1012ardb/Kconfig |  15 ++
 board/freescale/ls1012ardb/MAINTAINERS |   6 +
 board/freescale/ls1012ardb/Makefile|   7 +
 board/freescale/ls1012ardb/README  |  54 +
 board/freescale/ls1012ardb/ls1012ardb.c| 223 
 board/freescale/ls1043aqds/README  |  37 +---
 board/freescale/ls1043ardb/README  |  37 +---
 board/freescale/ls2080aqds/README  |  45 +---
 board/freescale/ls2080ardb/README  |  45 +---
 configs/ls1012afrdm_qspi_defconfig |  29 +++
 configs/ls1012aqds_qspi_defconfig  |  32 +++
 configs/ls1012ardb_qspi_defconfig  |  32 +++
 drivers/mtd/spi/sf_params.c|   1 +
 drivers/mtd/spi/spi_flash.c|   5 +-
 include/configs/ls1012a_common.h   | 145 +
 include/configs/ls1012afrdm.h  |  44 
 include/configs/ls1012aqds.h   | 191 +
 include/configs/ls1012ardb.h   | 107 ++
 include/fsl_mmdc.h | 164 +++
 include/linux/usb/xhci-fsl.h   |   6 +-
 55 files changed, 2385 insertions(+), 163 deletions(-)
 rename arch/arm/cpu/armv8/fsl-layerscape/{ => doc}/README.lsch2 (100%)
 rename 

[U-Boot] [PATCH 02/11][v4] armv8: fsl-layerscape: Avoid LS1043A specifc defines

[Prabhakar Kushwaha]

Other than LS1043A, LS1012A also Chassis Gen2 Architecture compliant.

So Avoid LS1043A specific defines in arch/arm

Signed-off-by: Prabhakar Kushwaha 
---
Changes for v2: Sending as it is
Changes for v3: Sending as it is
Changes for v4: Sending as it is

 arch/arm/cpu/armv8/fsl-layerscape/soc.c   | 2 +-
 arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 0fb5c7f..0ae61d6 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -224,7 +224,7 @@ int sata_init(void)
 }
 #endif
 
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_FSL_LSCH2)
 #ifdef CONFIG_SCSI_AHCI_PLAT
 int sata_init(void)
 {
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h 
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index f71c2c1..c4fb7c9 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -55,7 +55,7 @@ enum srds {
FSL_SRDS_1  = 0,
FSL_SRDS_2  = 1,
 };
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_FSL_LSCH2)
 enum srds_prtcl {
NONE = 0,
PCIE1,
-- 
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[U-Boot] [PATCH v2] imx: mx6var_som: Add support for Variscite mx6 boards

[Eran Matityahu]

Add support for Variscite VAR-SOM-MX6 / VAR-SOM-SOLO/DUAL / DART-MX6 boards 
with features:
PMIC, NAND flash, SD/MMC, USB, Ethernet, I2C, LVDS, HDMI.

Signed-off-by: Eran Matityahu 
Cc: Stefano Babic 
---
Note:
This patch depends on two other patches I've submitted that were not yet 
reviewed:
  https://patchwork.ozlabs.org/patch/614924/  or 
  http://lists.denx.de/pipermail/u-boot/2016-April/252840.html

  https://patchwork.ozlabs.org/patch/627880/  or
  http://lists.denx.de/pipermail/u-boot/2016-May/256341.html

Changes for v2:
- Many changes, code reorganization & cleanups and minor bug fixes
- On DART board mmc0 is now always SD and mmc1 is eMMC,
  regardless of the current boot device
- Move all previous automatic env settings from the code to
  env scripts, and also add some new ones, with options to
  enable/disable each one individually from the env
- Add audiocodec_reset to SPL to fix a bug in "L" SOM variants (Low 
power)
- Change kernel device tree file names for Variscite's 4.1.15 kernel
- Change mmcblk device numbers for Variscite's 4.1.15 kernel
- Changed a lot of things following Stefano's comments:
  Some things were fixed and some were made more clear.

Some explanations:
- This single U-Boot supports 3 different carrier boards:
  VAR-MX6CustomBoard, VAR-SOLOCustomBoard and VAR-DT6CustomBoard,
  and 3 different SOM types: VAR-SOM-MX6, VAR-SOM-SOLO/DUAL and DART-MX6
  (DART-MX6 goes with VAR-DT6CustomBoard, and the others can be mixed).
  Each SOM type can come in various configurations (can be with
  different CPU types and frequencies, can be with or without eMMC,
  can be with different types and capacities of NAND, RAM, etc.)
- About the EEPROM code:
  Since each SOM can come with a different RAM type and capacity, we use
  an EPPROM to keep the configuration of the specific RAM on the SOM.
  This code is based on an old U-Boot Variscite was managing internally
  before my time in the company.
  I've changed and simplified a lot of the code, but I cannot change
  the data on the EEPROM completely, since these SOMs are already in
  the market for a few years now.

 arch/arm/cpu/armv7/mx6/Kconfig|7 +
 board/variscite/mx6var_som/Kconfig|   12 +
 board/variscite/mx6var_som/MAINTAINERS|7 +
 board/variscite/mx6var_som/Makefile   |9 +
 board/variscite/mx6var_som/addresses.inc  |   38 +
 board/variscite/mx6var_som/mx6var_eeprom.h|   16 +
 board/variscite/mx6var_som/mx6var_eeprom_v1.c |  244 +
 board/variscite/mx6var_som/mx6var_eeprom_v1.h |   66 ++
 board/variscite/mx6var_som/mx6var_eeprom_v2.c |  238 
 board/variscite/mx6var_som/mx6var_eeprom_v2.h |   57 +
 board/variscite/mx6var_som/mx6var_som.c   | 1444 +
 board/variscite/mx6var_som/values.inc |   39 +
 configs/mx6var_som_nand_defconfig |   31 +
 configs/mx6var_som_sd_defconfig   |   31 +
 include/configs/mx6var_som.h  |  429 
 tools/logos/variscite.bmp |  Bin 0 -> 15414 bytes
 16 files changed, 2668 insertions(+)
 create mode 100644 board/variscite/mx6var_som/Kconfig
 create mode 100644 board/variscite/mx6var_som/MAINTAINERS
 create mode 100644 board/variscite/mx6var_som/Makefile
 create mode 100644 board/variscite/mx6var_som/addresses.inc
 create mode 100644 board/variscite/mx6var_som/mx6var_eeprom.h
 create mode 100644 board/variscite/mx6var_som/mx6var_eeprom_v1.c
 create mode 100644 board/variscite/mx6var_som/mx6var_eeprom_v1.h
 create mode 100644 board/variscite/mx6var_som/mx6var_eeprom_v2.c
 create mode 100644 board/variscite/mx6var_som/mx6var_eeprom_v2.h
 create mode 100644 board/variscite/mx6var_som/mx6var_som.c
 create mode 100644 board/variscite/mx6var_som/values.inc
 create mode 100644 configs/mx6var_som_nand_defconfig
 create mode 100644 configs/mx6var_som_sd_defconfig
 create mode 100644 include/configs/mx6var_som.h
 create mode 100644 tools/logos/variscite.bmp

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 663f970..738c2ea 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -129,6 +129,12 @@ config TARGET_MX6UL_14X14_EVK
select DM_THERMAL
select SUPPORT_SPL
 
+config TARGET_MX6VAR_SOM
+   bool "mx6var_som"
+   select SUPPORT_SPL
+   select DM
+   select DM_THERMAL
+
 config TARGET_NITROGEN6X
bool "nitrogen6x"
 
@@ -208,6 +214,7 @@ source "board/technexion/pico-imx6ul/Kconfig"
 source "board/tbs/tbs2910/Kconfig"
 source "board/tqc/tqma6/Kconfig"
 source "board/udoo/Kconfig"
+source "board/variscite/mx6var_som/Kconfig"
 source "board/wandboard/Kconfig"
 source "board/warp/Kconfig"
 
diff --git 

Re: [U-Boot] [PATCH 2/3] armv8/fsl-layerscape: add dwc3 gadget driver support

[Lukasz Majewski]

Hi Rajat,

> From: Rajesh Bhagat 
> 
> Implements the dwc3 gadget driver support for LS1043
> platform, and performs below operations:
> 1. Enables snooping support for DWC3 controller.
> 2. Enables cache coherency in LS1043 platform.
> 
> Signed-off-by: Rajat Srivastava 
> Signed-off-by: Rajesh Bhagat 
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/soc.c| 87
> +- .../include/asm/arch-fsl-layerscape/immap_lsch2.h
> |  6 ++ .../include/asm/arch-fsl-layerscape/sys_proto.h| 11 +++
>  drivers/usb/dwc3/core.c| 12 +++
>  4 files changed, 114 insertions(+), 2 deletions(-)
>  create mode 100644
> arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 0fb5c7f..84b973d
> 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> @@ -17,6 +17,10 @@
>  #ifdef CONFIG_CHAIN_OF_TRUST
>  #include 
>  #endif
> +#include 
> +#include 
> +#include 
> +
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -318,9 +322,12 @@ void fsl_lsch2_early_init_f(void)
>  #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
>   out_be32(>qspi_cfg, SCFG_QSPI_CLKSEL);
>  #endif
> - /* Make SEC reads and writes snoopable */
> + /* Make SEC and USB reads and writes snoopable */
>   setbits_be32(>snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
> -  SCFG_SNPCNFGCR_SECWRSNP);
> +  SCFG_SNPCNFGCR_SECWRSNP |
> SCFG_SNPCNFGCR_USB1RDSNP |
> +  SCFG_SNPCNFGCR_USB1WRSNP |
> SCFG_SNPCNFGCR_USB2RDSNP |
> +  SCFG_SNPCNFGCR_USB2WRSNP |
> SCFG_SNPCNFGCR_USB3RDSNP |
> +  SCFG_SNPCNFGCR_USB3WRSNP);
>  
>   /*
>* Enable snoop requests and DVM message requests for
> @@ -336,6 +343,82 @@ void fsl_lsch2_early_init_f(void)
>  }
>  #endif
>  
> +#ifdef CONFIG_USB_DWC3
> +
> +#if defined(CONFIG_LS1043A)
> +static struct dwc3_device dwc3_device_data0 = {
> + .maximum_speed = USB_SPEED_HIGH,
> + .base = CONFIG_SYS_FSL_XHCI_USB1_ADDR,
> + .dr_mode = USB_DR_MODE_PERIPHERAL,
> + .index = 0,
> +};
> +
> +static struct dwc3_device dwc3_device_data1 = {
> + .maximum_speed = USB_SPEED_HIGH,
> + .base = CONFIG_SYS_FSL_XHCI_USB2_ADDR,
> + .dr_mode = USB_DR_MODE_PERIPHERAL,
> + .index = 1,
> +};
> +
> +static struct dwc3_device dwc3_device_data2 = {
> + .maximum_speed = USB_SPEED_HIGH,
> + .base = CONFIG_SYS_FSL_XHCI_USB3_ADDR,
> + .dr_mode = USB_DR_MODE_PERIPHERAL,
> + .index = 2,
> +};
> +
> +int usb_gadget_handle_interrupts(int index)
> +{
> + dwc3_uboot_handle_interrupt(index);
> + return 0;
> +}
> +#endif
> +
> +int board_usb_init(int index, enum usb_init_type init)
> +{
> + switch (init) {
> + case USB_INIT_DEVICE:
> + switch (index) {
> +#if defined(CONFIG_LS1043A)
> + case 0:
> + dwc3_uboot_init(_device_data0);
> + break;
> +
> + case 1:
> + dwc3_uboot_init(_device_data1);
> + break;
> + case 2:
> + dwc3_uboot_init(_device_data2);
> + break;
> +#endif
> + default:
> + printf("Invalid Controller Index\n");
> + return -1;
> + }
> + break;
> + default:
> + break;
> + }
> + return 0;
> +}
> +
> +int board_usb_cleanup(int index, enum usb_init_type init)
> +{
> + switch (init) {
> + case USB_INIT_DEVICE:
> +#if defined(CONFIG_LS1043A)
> + dwc3_uboot_exit(index);
> +#endif
> + break;
> + default:
> + break;
> + }
> + return 0;
> +}
> +#endif
> +
> +
> +
>  #ifdef CONFIG_BOARD_LATE_INIT
>  int board_late_init(void)
>  {
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index
> 57b99d4..13ba1a6 100644 ---
> a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -328,6
> +328,12 @@ struct ccsr_gur { 
>  #define SCFG_SNPCNFGCR_SECRDSNP  0x8000
>  #define SCFG_SNPCNFGCR_SECWRSNP  0x4000
> +#define SCFG_SNPCNFGCR_USB1RDSNP 0x0020
> +#define SCFG_SNPCNFGCR_USB1WRSNP 0x0010
> +#define SCFG_SNPCNFGCR_USB2RDSNP 0x8000
> +#define SCFG_SNPCNFGCR_USB2WRSNP 0x0001
> +#define SCFG_SNPCNFGCR_USB3RDSNP 0x2000
> +#define SCFG_SNPCNFGCR_USB3WRSNP 0x4000
>  
>  /* Supplemental Configuration Unit */
>  struct ccsr_scfg {
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
> b/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h new file mode
> 100644 index 000..252c676
> --- /dev/null
> +++ 

Re: [U-Boot] [PATCH 1/3] usb: ums: support multiple controllers using controller_index

[Lukasz Majewski]

Hi Rajat,

> From: Rajesh Bhagat 
> 
> Adds a new field in fsg_common namely controller_index to support
> multiple controllers usb gadget support.
> 
> Signed-off-by: Rajat Srivastava 
> Signed-off-by: Rajesh Bhagat 
> ---
>  cmd/usb_mass_storage.c  |  2 +-
>  drivers/usb/gadget/f_mass_storage.c | 10 +-
>  2 files changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
> index b05913a..1c955f8 100644
> --- a/cmd/usb_mass_storage.c
> +++ b/cmd/usb_mass_storage.c
> @@ -214,7 +214,7 @@ int do_usb_mass_storage(cmd_tbl_t *cmdtp, int
> flag, while (1) {
>   usb_gadget_handle_interrupts(controller_index);
>  
> - rc = fsg_main_thread(NULL);
> + rc = fsg_main_thread(_index);

controller_index is defined as unsigned int.

However, fsg_main_thread(void *common_) accepts void * as its parameter.

Could you adjust it to accept unsigned int index parameter?

>   if (rc) {
>   /* Check I/O error */
>   if (rc == -EIO)
> diff --git a/drivers/usb/gadget/f_mass_storage.c
> b/drivers/usb/gadget/f_mass_storage.c index 1ecb92a..cc3e4af 100644
> --- a/drivers/usb/gadget/f_mass_storage.c
> +++ b/drivers/usb/gadget/f_mass_storage.c
> @@ -362,6 +362,7 @@ struct fsg_common {
>   char inquiry_string[8 + 16 + 4 + 1];
>  
>   struct kref ref;
> + unsigned int controller_index;
>  };
>  
>  struct fsg_config {
> @@ -691,7 +692,7 @@ static int sleep_thread(struct fsg_common *common)
>   k = 0;
>   }
>  
> - usb_gadget_handle_interrupts(0);
> +
> usb_gadget_handle_interrupts(common->controller_index); }
>   common->thread_wakeup_needed = 0;
>   return rc;
> @@ -2406,6 +2407,11 @@ int fsg_main_thread(void *common_)
>  {
>   int ret;
>   struct fsg_common   *common = the_fsg_common;
> +
> + /* update the controller_index */
> + if (common_)

Replace common_ with unsigned int index 

> + common->controller_index = *(unsigned int *)common_;
> +
>   /* The main loop */
>   do {
>   if (exception_in_progress(common)) {
> @@ -2476,6 +2482,7 @@ static struct fsg_common
> *fsg_common_init(struct fsg_common *common, 
>   common->ops = NULL;
>   common->private_data = NULL;
> + common->controller_index = 0;
>  
>   common->gadget = gadget;
>   common->ep0 = gadget->ep0;
> @@ -2770,6 +2777,7 @@ int fsg_add(struct usb_configuration *c)
>  
>   fsg_common->ops = NULL;
>   fsg_common->private_data = NULL;
> + fsg_common->controller_index = 0;
>  
>   the_fsg_common = fsg_common;
>  



-- 
Best regards,

Lukasz Majewski

Samsung R Institute Poland (SRPOL) | Linux Platform Group
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Re: [U-Boot] Please pull u-boot-marvell/master

[Tom Rini]

On Tue, May 31, 2016 at 08:08:44AM +0200, Stefan Roese wrote:

> Hi Tom,
> 
> please pull the following patches from the Marvell git repository.
> I've included 2 SPEAr patches there since we don't have a SPEAr
> git repository. I hope this okay.
> 
> Thanks,
> Stefan
> 
> The following changes since commit e4a94ce4ac77396b181663c0493c50bc2d5b9143:
> 
>   Merge git://git.denx.de/u-boot-dm (2016-05-27 20:34:12 -0400)
> 
> are available in the git repository at:
> 
>   git://www.denx.de/git/u-boot-marvell.git 
> 
> for you to fetch changes up to e084fd922f7483d591c623823452fff7879c9d71:
> 
>   arm: spear: x600: Remove EFI support to reduce image size (2016-05-31 
> 07:48:40 +0200)
> 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [GIT PULL] u-boot-mips/master

[Tom Rini]

On Tue, May 31, 2016 at 11:36:46AM +0200, Daniel Schwierzeck wrote:

> Hi Tom,
> 
> please pull the last batch of MIPS updates, thanks.
> 
> The following changes since commit e4a94ce4ac77396b181663c0493c50bc2d5b9143:
> 
>   Merge git://git.denx.de/u-boot-dm (2016-05-27 20:34:12 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-mips.git master
> 
> for you to fetch changes up to f1b65c98b0a134ce92c38141b917fd3a210ee535:
> 
>   mips: ath79: ap143: Reset ethernet on boot (2016-05-31 10:17:54 +0200)
> 

Applied to u-boot/master, thanks!




-- 
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Re: [U-Boot] [PATCH] Revert "image.h: Tighten up content using handy CONFIG_IS_ENABLED() macro."

[Tom Rini]

On Tue, May 31, 2016 at 08:41:54PM +0900, Masahiro Yamada wrote:

> This reverts commit 56adbb38727320375b2f695bd04600d766d8a1b3.
> 
> Since commit 56adbb387273 ("image.h: Tighten up content using handy
> CONFIG_IS_ENABLED() macro."), I found my boards fail to boot Linux
> because the commit changed the logic of macros it touched.  Now,
> IMAGE_ENABLE_RAMDISK_HIGH and IMAGE_BOOT_GET_CMDLINE are 0 for all
> the boards.
> 
> As you can see in include/linux/kconfig.h, CONFIG_IS_ENABLE() (and
> IS_ENABLED() as well) can only take a macro that is either defined
> as 1 or undefined.  This is met for boolean options defined in
> Kconfig.  On the other hand, CONFIG_SYS_BOOT_RAMDISK_HIGH and
> CONFIG_SYS_BOOT_GET_CMDLINE are defined without any value in
> arch/*/include/asm/config.h .  This kind of clean-up is welcome,
> but the options should be moved to Kconfig beforehand.
> 
> Moreover, CONFIG_IS_ENABLED(SPL_CRC32_SUPPORT) looks weird.
> It should be either CONFIG_IS_ENABLED(CRC32_SUPPORT) or
> IS_ENABLED(CONFIG_SPL_CRC32_SUPPORT).  But, I see no define for
> CONFIG_SPL_CRC32_SUPPORT anywhere.  Likewise for the other three.
> 
> The logic of IMAGE_OF_BOARD_SETUP and IMAGE_OF_SYSTEM_SETUP were
> also changed for SPL.  This can be a problem for boards defining
> CONFIG_SPL_OF_LIBFDT.  I guess it should have been changed to
> IS_ENABLED(CONFIG_OF_BOARD_SETUP).
> 
> In the first place, if we replace the references in C code,
> the macros IMAGE_* will go away.
> 
>   if (IS_ENABLED(CONFIG_OF_BOARD_SETUP) {
>   ...
>   }
> 
> Signed-off-by: Masahiro Yamada 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH] tools/env: allow to pass NULL for environment options

[Tom Rini]

On Tue, May 31, 2016 at 09:21:56AM +0200, Andreas Fenkart wrote:

> If users of the library are happy with the default, e.g. config file
> name. They can pass NULL as the opts pointer. This simplifies the
> transition of existing library users.
> FIXES a compile error. since common_args has been removed by
> a previous patch
> 
> Signed-off-by: Andreas Fenkart 

Applied to u-boot/master, thanks!

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Re: [U-Boot] Please pull u-boot-x86

[Tom Rini]

On Mon, May 30, 2016 at 10:45:35AM +0800, Bin Meng wrote:

> Hi Tom,
> 
> The following changes since commit 6523dbf7cce8d8c903346f756e0e41e46ce6d6b9:
> 
>   Merge branch 'master' of git://git.denx.de/u-boot-mips (2016-05-25
> 20:22:48 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-x86.git master
> 
> for you to fetch changes up to d3d664725b4a05cf32d905ff806b44bb01fa61c0:
> 
>   x86: baytrail: acpi: Fix I/O APIC ID in the MADT table (2016-05-30
> 10:21:12 +0800)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] image.h: Tighten up content using handy CONFIG_IS_ENABLED() macro: Causing Linux boot crash

[Tom Rini]

On Tue, May 31, 2016 at 02:32:06PM +, Prabhakar Kushwaha wrote:

> Hi Robert,
> 
> I was trying Linux boot on LS2080ARDB platform(ls2080ardb_defconfig) with top 
> commit i.e. "e4a94ce4ac77396b181663c0493c50bc2d5b9143 ".
> 
> I am seeing below crash while trying to mount root file system. 
> 
> [2.844331] NET: Registered protocol family 17
> [2.848787] NET: Registered protocol family 15
> [2.853251] 8021q: 802.1Q VLAN Support v1.8
> [2.857455] 9pnet: Installing 9P2000 support
> [2.861753] Key type dns_resolver registered
> [2.866274] registered taskstats version 1
> [2.870575] fsl_generic: FSL DPAA Generic Ethernet driver
> [2.877144] rtc-ds3232 2-0068: setting system clock to 2016-02-08 05:34:04 
> UTC (1454909644)
> [2.886344] List of all partitions:
> [2.889831] 010033554432 ram0  (driver?)
> [2.894450] 010133554432 ram1  (driver?)
> [2.899077] 010233554432 ram2  (driver?)
> [2.903695] 010333554432 ram3  (driver?)
> [2.908318] 010433554432 ram4  (driver?)
> [2.912935] 010533554432 ram5  (driver?)
> [2.917557] 010633554432 ram6  (driver?)
> [2.922175] 010733554432 ram7  (driver?)
> [2.926800] 010833554432 ram8  (driver?)
> [2.931417] 010933554432 ram9  (driver?)
> [2.936035] 010a33554432 ram10  (driver?)
> [2.940743] 010b33554432 ram11  (driver?)
> [2.945447] 010c33554432 ram12  (driver?)
> [2.950153] 010d33554432 ram13  (driver?)
> [2.954857] 010e33554432 ram14  (driver?)
> [2.959565] 010f33554432 ram15  (driver?)
> [2.964272] 1f00  131072 mtdblock0  (driver?)
> [2.969329] 1f01 2097152 mtdblock1  (driver?)
> [2.974378] No filesystem could mount root, tried:  ext3 ext2 ext4 vfat 
> fuseblk
> [2.981713] Kernel panic - not syncing: VFS: Unable to mount root fs on 
> unknown-block(1,0)
> [2.989979] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.1.8+ #1
> [2.995896] Hardware name: Freescale Layerscape 2080a RDB Board (DT)
> [3.002247] Call trace:
> [3.004692] [] dump_backtrace+0x0/0x12c
> [3.010089] [] show_stack+0x10/0x1c
> [3.015139] [] dump_stack+0x8c/0xdc
> [3.020189] [] panic+0xe4/0x220
> [3.024890] [] mount_block_root+0x248/0x270
> [3.030635] [] mount_root+0x114/0x134
> [3.035857] [] prepare_namespace+0x174/0x1c0
> [3.041688] [] kernel_init_freeable+0x1c0/0x1e8
> [3.047779] [] kernel_init+0xc/0xdc
> [3.052829] CPU7: stopping
> [3.055534] CPU: 7 PID: 0 Comm: swapper/7 Not tainted 4.1.8+ #1
> [3.061450] Hardware name: Freescale Layerscape 2080a RDB Board (DT)
> 
> 
> I did git bisect and figure out commit 
> "56adbb38727320375b2f695bd04600d766d8a1b3" i.e.  "image.h: Tighten up content 
> using handy CONFIG_IS_ENABLED() macro" causing this crash. 
> If I revert this patch, every things work perfectly. 
> 
> Any suggestion.. Am I missing something!!

No, just my fault here, sorry, pushing a fix shortly.

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Re: [U-Boot] [PATCH v2 6/7] dfu, nand, ubi: fix erasing after write finish

[Lukasz Majewski]

Hi Heiko,

> + off = dfu->offset;
> + if ((off & (mtd->erasesize - 1)) != 0) {
> + /*
> +  * last write ended with unaligned length
> +  * sector is erased, jump to next
> +  */
> + off = off & ~((mtd->erasesize - 1));
> + off += mtd->erasesize;
> + }
> + opts.offset = dfu->data.nand.start + off +

Acked-by: Lukasz Majewski 

-- 
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Lukasz Majewski

Samsung R Institute Poland (SRPOL) | Linux Platform Group
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[U-Boot] image.h: Tighten up content using handy CONFIG_IS_ENABLED() macro: Causing Linux boot crash

[Prabhakar Kushwaha]

Hi Robert,

I was trying Linux boot on LS2080ARDB platform(ls2080ardb_defconfig) with top 
commit i.e. "e4a94ce4ac77396b181663c0493c50bc2d5b9143 ".

I am seeing below crash while trying to mount root file system. 

[2.844331] NET: Registered protocol family 17
[2.848787] NET: Registered protocol family 15
[2.853251] 8021q: 802.1Q VLAN Support v1.8
[2.857455] 9pnet: Installing 9P2000 support
[2.861753] Key type dns_resolver registered
[2.866274] registered taskstats version 1
[2.870575] fsl_generic: FSL DPAA Generic Ethernet driver
[2.877144] rtc-ds3232 2-0068: setting system clock to 2016-02-08 05:34:04 
UTC (1454909644)
[2.886344] List of all partitions:
[2.889831] 010033554432 ram0  (driver?)
[2.894450] 010133554432 ram1  (driver?)
[2.899077] 010233554432 ram2  (driver?)
[2.903695] 010333554432 ram3  (driver?)
[2.908318] 010433554432 ram4  (driver?)
[2.912935] 010533554432 ram5  (driver?)
[2.917557] 010633554432 ram6  (driver?)
[2.922175] 010733554432 ram7  (driver?)
[2.926800] 010833554432 ram8  (driver?)
[2.931417] 010933554432 ram9  (driver?)
[2.936035] 010a33554432 ram10  (driver?)
[2.940743] 010b33554432 ram11  (driver?)
[2.945447] 010c33554432 ram12  (driver?)
[2.950153] 010d33554432 ram13  (driver?)
[2.954857] 010e33554432 ram14  (driver?)
[2.959565] 010f33554432 ram15  (driver?)
[2.964272] 1f00  131072 mtdblock0  (driver?)
[2.969329] 1f01 2097152 mtdblock1  (driver?)
[2.974378] No filesystem could mount root, tried:  ext3 ext2 ext4 vfat 
fuseblk
[2.981713] Kernel panic - not syncing: VFS: Unable to mount root fs on 
unknown-block(1,0)
[2.989979] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.1.8+ #1
[2.995896] Hardware name: Freescale Layerscape 2080a RDB Board (DT)
[3.002247] Call trace:
[3.004692] [] dump_backtrace+0x0/0x12c
[3.010089] [] show_stack+0x10/0x1c
[3.015139] [] dump_stack+0x8c/0xdc
[3.020189] [] panic+0xe4/0x220
[3.024890] [] mount_block_root+0x248/0x270
[3.030635] [] mount_root+0x114/0x134
[3.035857] [] prepare_namespace+0x174/0x1c0
[3.041688] [] kernel_init_freeable+0x1c0/0x1e8
[3.047779] [] kernel_init+0xc/0xdc
[3.052829] CPU7: stopping
[3.055534] CPU: 7 PID: 0 Comm: swapper/7 Not tainted 4.1.8+ #1
[3.061450] Hardware name: Freescale Layerscape 2080a RDB Board (DT)


I did git bisect and figure out commit 
"56adbb38727320375b2f695bd04600d766d8a1b3" i.e.  "image.h: Tighten up content 
using handy CONFIG_IS_ENABLED() macro" causing this crash. 
If I revert this patch, every things work perfectly. 

Any suggestion.. Am I missing something!!

--prabhakar

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Re: [U-Boot] [PATCH 4/6] mips: ath79: Add support for ungating USB and ethernet on qca953x

[Wills Wang]

On 05/31/2016 04:50 PM, Piotr Dymacz wrote:

Hello,

2016-05-31 2:51 GMT+02:00 Marek Vasut :

On 05/31/2016 02:35 AM, Wills Wang wrote:

[snip]


   +static int usb_reset_qca953x(void __iomem *reset_regs)
+{
+void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+  MAP_NOCACHE);
+
+clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
+0xf00, 0x200);

Do you know what these magic numbers mean ?

I can help here.

This register is common for (almost) all modern QC/A WiSOCs, with
similar structure, at least for AR934x, QCA953x, QCA955x and QCA956x
(please take a look at [1]).
I have seen it (SDK, datasheets) under two different names:
SWITCH_CLOCK_SPARE and SWITCH_CLOCK_CONTROL, on different addresses
(offset +/- 1), depending on the SOC.

The bit field [8:11] is "USB_REFCLK_FREQ_SEL" and it's the same for
all above SOCs. Value (dec) 2 is for 25 MHz, value 5 for 40 MHz.

You are right, i found the same description in ar9341 data sheet.

I'm going to provide some patches for ath79 in future, which will make
code more universal for all QC/A WiSOCs.

You are always welcome.

--
Regards,
Piotr Dymacz

[1] http://postimg.org/image/tyrkhkw57/full/


+mdelay(10);
+
+/* Ungate the USB block */
+setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+ QCA953X_RESET_USBSUS_OVERRIDE);
+mdelay(1);
+clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+ QCA953X_RESET_USB_PHY);
+mdelay(1);
+clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+ QCA953X_RESET_USB_PHY_ANALOG);
+mdelay(1);
+clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+ QCA953X_RESET_USB_HOST);
+mdelay(1);
+clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+ QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
+mdelay(1);
+
+return 0;
+}
+
   int ath79_usb_reset(void)
   {
   void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
@@ -204,6 +252,8 @@ int ath79_usb_reset(void)
   return usb_reset_ar933x(reset_regs);
   if (soc_is_ar934x())
   return usb_reset_ar934x(reset_regs);
+if (soc_is_qca953x())
+return usb_reset_qca953x(reset_regs);
 return -EINVAL;
   }



--
Best regards,
Marek Vasut
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--
Best Regards
Wills

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Re: [U-Boot] [U-Boot, RFC] SPL: FIT: Align loading address for header

[Tom Rini]

On Tue, May 31, 2016 at 07:42:42PM +0530, Lokesh Vutla wrote:
> 
> 
> On Tuesday 31 May 2016 07:39 PM, Tom Rini wrote:
> > On Tue, May 31, 2016 at 09:59:47AM +0530, Lokesh Vutla wrote:
> >>
> >>
> >> On Monday 30 May 2016 11:26 PM, Tom Rini wrote:
> >>> On Thu, Apr 28, 2016 at 10:36:11AM +0200, Michal Simek wrote:
> >>>
>  If bl_len is not aligned it can caused a problem because another code
>  expects that start is aligned.
> 
>  Signed-off-by: Michal Simek 
>  Reviewed-by: Simon Glass 
> >>>
> >>> Applied to u-boot/master, thanks!
> >>
> >> This patch is not required and should not be applied.
> > 
> > Did you both agree on "spl: Allow to load a FIT containing U-Boot from
> > FS" instead then?  And thus what's in the tree needs a little re-work
> > since I made the above apply on top of this one instead?  Sorry/thanks!
> 
> Yes, Michal as well agreed that this is not required[1]. This patch
> might work but it can fail in corner cases.
> 
> If you want I can send a fix patch on top of latest.

Yes please, thanks!

-- 
Tom


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Re: [U-Boot] [U-Boot, RFC] SPL: FIT: Align loading address for header

[Lokesh Vutla]

On Tuesday 31 May 2016 07:39 PM, Tom Rini wrote:
> On Tue, May 31, 2016 at 09:59:47AM +0530, Lokesh Vutla wrote:
>>
>>
>> On Monday 30 May 2016 11:26 PM, Tom Rini wrote:
>>> On Thu, Apr 28, 2016 at 10:36:11AM +0200, Michal Simek wrote:
>>>
 If bl_len is not aligned it can caused a problem because another code
 expects that start is aligned.

 Signed-off-by: Michal Simek 
 Reviewed-by: Simon Glass 
>>>
>>> Applied to u-boot/master, thanks!
>>
>> This patch is not required and should not be applied.
> 
> Did you both agree on "spl: Allow to load a FIT containing U-Boot from
> FS" instead then?  And thus what's in the tree needs a little re-work
> since I made the above apply on top of this one instead?  Sorry/thanks!

Yes, Michal as well agreed that this is not required[1]. This patch
might work but it can fail in corner cases.

If you want I can send a fix patch on top of latest.

[1] http://patchwork.ozlabs.org/patch/616065/

Thanks and regards,
Lokesh

> 
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Re: [U-Boot] [U-Boot, RFC] SPL: FIT: Align loading address for header

[Tom Rini]

On Tue, May 31, 2016 at 09:59:47AM +0530, Lokesh Vutla wrote:
> 
> 
> On Monday 30 May 2016 11:26 PM, Tom Rini wrote:
> > On Thu, Apr 28, 2016 at 10:36:11AM +0200, Michal Simek wrote:
> > 
> >> If bl_len is not aligned it can caused a problem because another code
> >> expects that start is aligned.
> >>
> >> Signed-off-by: Michal Simek 
> >> Reviewed-by: Simon Glass 
> > 
> > Applied to u-boot/master, thanks!
> 
> This patch is not required and should not be applied.

Did you both agree on "spl: Allow to load a FIT containing U-Boot from
FS" instead then?  And thus what's in the tree needs a little re-work
since I made the above apply on top of this one instead?  Sorry/thanks!

-- 
Tom


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Re: [U-Boot] [RFC PATCH 1/5] spl: dfu: add dfu support in SPL

[B, Ravi]

Hi Lukasz

>> without fat/ext4, mmc support. But all device support may increase 
>> size.

> Ok.

> However, adding fat/ext4/mmc (and other) support should be on demand (and 
> enabled by proper Kconfig options).
> This would allow others to add only what is really needed.

True, we provide incremental build option on need basis.  

>> 
>> >If yes, then even BBB's SPL can support DFU without any problems 
>> >(105KiB < 128 KiB).
>> 
>> You mean BBB must have 128KB ? Can you confirm.

>I didn't find any _hard_ rule about the size.

>In the am335x_evm.h file the spice reserved for SPL (on raw eMMC) is 128 KiB.

Are you referring to eMMC raw boot option ?

>> If BBB is support SPI boot, flashing MLO/U-boot to SPI-flash through 
>> SPL-DFU/SF would be sufficient right ?

>I don't know the exact use cases, but yes, BBB can boot from SPI flash.

>I'm just wondering - the use case for your board is to use USB to flash your 
>device in u-boot SPL. 
>If I might ask, why cannot you wait for the U-Boot to use fully-fledged DFU 
>for flashing?

Full-fledged DFU already supported in u-boot. 
The problem here is, how to flash the images first time to fresh boards to  
QSPI or eMMC device, where there is no MMC/SD boot option available. 
The solution to this problem is use peripheral USB boot mode (configuring 
sysboot switches), where the ROM loads the intial SPL(+DFU builtin for 
spi/eMMC) to IRAM, then run dfu/sf or dfu/eMMC to flash the binaries from PC 
using USB interface.
Refer to SPL-DFU support based on 2014.07 u-boot 
http://www.ti.com/lit/an/sprac33/sprac33.pdf. 

The SPL-DFU definitely helpful in production/development, where just connect 
EVM to PC through USB cable, and flash the MLO/U-BOOT, binaries to selected 
device (QSPI/eMMC).

I think based on discussion we had, some conclusion we could arrive, 
1) SPL size is constraint based on IRAM size, that all platform cannot be 
supported by default.
2) Kconfig option to compile only required device (eMMC, SPI)
3) Kconfig option for fat/ext4 support.
4) Try using common/spl/spl_fat{ext}.. to reduce footprint.

Regards
Ravi 
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Re: [U-Boot] [PATCH 2/3] armv8/fsl-layerscape: add dwc3 gadget driver support

[Felipe Balbi]

Hi,

Marek Vasut  writes:
>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>> index 85cc96a..5eeb71d 100644
>> --- a/drivers/usb/dwc3/core.c
>> +++ b/drivers/usb/dwc3/core.c
>> @@ -690,6 +690,18 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
>>  return -ENOMEM;
>>  }
>>  
>> +#if defined(CONFIG_LS1043A)
>
> How was this added in Linux ? I doubt such horrid ifdef was allowed.
> I presume it went through either DT or struct dwc3_device, right ?
> So fix this here the same way.

dwc3 doesn't have any of that. I wouldn't take it :-p

-- 
balbi


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[U-Boot] [PATCH] dm: gpio: MPC85XX GPIO platform data support

[Hamish Martin]

Define a platform data structure for the MPC85XX GPIO driver to allow
use of the driver without device tree. Users should define the GPIO
blocks for their platform like this:
  struct mpc85xx_gpio_plat gpio_blocks[] = {
 {
 .addr = 0x13,
 .ngpios = 32,
 },
 {
 .addr = 0x131000,
 .ngpios = 32,
 },
  };

  U_BOOT_DEVICES(my_platform_gpios) = {
 { "gpio_mpc85xx", _blocks[0] },
 { "gpio_mpc85xx", _blocks[1] },
  };

This is intended to build upon the recent submission of the base
MPC85XX driver from Mario Six. We need to use that new driver
without dts support and this patch gives us that flexibility.
This has been tested on a Freescale T2080 CPU, although only the first
GPIO block.

Signed-off-by: Hamish Martin 
Reviewed-by: Mario Six 
Tested-by: Mario Six 
---
 arch/powerpc/include/asm/arch-mpc85xx/gpio.h |  6 +
 drivers/gpio/mpc85xx_gpio.c  | 36 ++--
 2 files changed, 35 insertions(+), 7 deletions(-)

diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h 
b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
index 41b6677bba38..76faa22c8b43 100644
--- a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
@@ -18,4 +18,10 @@
 #include 
 #endif
 
+struct mpc85xx_gpio_plat {
+   ulong addr;
+   unsigned long size;
+   uint ngpios;
+};
+
 #endif
diff --git a/drivers/gpio/mpc85xx_gpio.c b/drivers/gpio/mpc85xx_gpio.c
index 04773e2b31c3..c4563bee4d84 100644
--- a/drivers/gpio/mpc85xx_gpio.c
+++ b/drivers/gpio/mpc85xx_gpio.c
@@ -163,23 +163,41 @@ static int mpc85xx_gpio_get_function(struct udevice *dev, 
unsigned gpio)
return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
 }
 
+#if CONFIG_IS_ENABLED(OF_CONTROL)
 static int mpc85xx_gpio_ofdata_to_platdata(struct udevice *dev) {
-   struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+   struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev)
fdt_addr_t addr;
fdt_size_t size;
 
addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev->of_offset,
  "reg", 0, );
 
-   data->addr = addr;
-   data->base = map_sysmem(CONFIG_SYS_IMMR + addr, size);
+   plat->addr = addr;
+   plat->size = size;
+   plat->ngpios = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "ngpios", 32);
 
-   if (!data->base)
+   return 0;
+}
+#endif
+
+static int mpc85xx_gpio_platdata_to_priv(struct udevice *dev)
+{
+   struct mpc85xx_gpio_data *priv = dev_get_priv(dev);
+   struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev);
+   unsigned long size = plat->size;
+
+   if (size == 0)
+   size = 0x100;
+
+   priv->addr = plat->addr;
+   priv->base = map_sysmem(CONFIG_SYS_IMMR + plat->addr, size);
+
+   if (!priv->base)
return -ENOMEM;
 
-   data->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
- "ngpios", 32);
-   data->dat_shadow = 0;
+   priv->gpio_count = plat->ngpios;
+   priv->dat_shadow = 0;
 
return 0;
 }
@@ -190,6 +208,8 @@ static int mpc85xx_gpio_probe(struct udevice *dev)
struct mpc85xx_gpio_data *data = dev_get_priv(dev);
char name[32], *str;
 
+   mpc85xx_gpio_platdata_to_priv(dev);
+
snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
str = strdup(name);
 
@@ -221,8 +241,10 @@ U_BOOT_DRIVER(gpio_mpc85xx) = {
.name   = "gpio_mpc85xx",
.id = UCLASS_GPIO,
.ops= _mpc85xx_ops,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
.ofdata_to_platdata = mpc85xx_gpio_ofdata_to_platdata,
.of_match = mpc85xx_gpio_ids,
+#endif
.probe  = mpc85xx_gpio_probe,
.priv_auto_alloc_size = sizeof(struct mpc85xx_gpio_data),
 };
-- 
2.8.3

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Re: [U-Boot] [PATCH 4/6] mips: ath79: Add support for ungating USB and ethernet on qca953x

[Piotr Dymacz]

Hello,

2016-05-31 2:51 GMT+02:00 Marek Vasut :
> On 05/31/2016 02:35 AM, Wills Wang wrote:

[snip]

   +static int usb_reset_qca953x(void __iomem *reset_regs)
 +{
 +void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
 +  MAP_NOCACHE);
 +
 +clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
 +0xf00, 0x200);
>
> Do you know what these magic numbers mean ?

I can help here.

This register is common for (almost) all modern QC/A WiSOCs, with
similar structure, at least for AR934x, QCA953x, QCA955x and QCA956x
(please take a look at [1]).
I have seen it (SDK, datasheets) under two different names:
SWITCH_CLOCK_SPARE and SWITCH_CLOCK_CONTROL, on different addresses
(offset +/- 1), depending on the SOC.

The bit field [8:11] is "USB_REFCLK_FREQ_SEL" and it's the same for
all above SOCs. Value (dec) 2 is for 25 MHz, value 5 for 40 MHz.

I'm going to provide some patches for ath79 in future, which will make
code more universal for all QC/A WiSOCs.

--
Regards,
Piotr Dymacz

[1] http://postimg.org/image/tyrkhkw57/full/

 +mdelay(10);
 +
 +/* Ungate the USB block */
 +setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
 + QCA953X_RESET_USBSUS_OVERRIDE);
 +mdelay(1);
 +clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
 + QCA953X_RESET_USB_PHY);
 +mdelay(1);
 +clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
 + QCA953X_RESET_USB_PHY_ANALOG);
 +mdelay(1);
 +clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
 + QCA953X_RESET_USB_HOST);
 +mdelay(1);
 +clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
 + QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
 +mdelay(1);
 +
 +return 0;
 +}
 +
   int ath79_usb_reset(void)
   {
   void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
 @@ -204,6 +252,8 @@ int ath79_usb_reset(void)
   return usb_reset_ar933x(reset_regs);
   if (soc_is_ar934x())
   return usb_reset_ar934x(reset_regs);
 +if (soc_is_qca953x())
 +return usb_reset_qca953x(reset_regs);
 return -EINVAL;
   }

>>>
>>
>
>
> --
> Best regards,
> Marek Vasut
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Re: [U-Boot] [PATCH 1/2] common: usb_storage : Implement logic to calculate optimal usb maximum trasfer blocks

[Rajesh Bhagat]

> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Tuesday, May 31, 2016 5:12 AM
> To: Rajesh Bhagat ; u-boot@lists.denx.de
> Cc: s...@chromium.org; york sun ; Sriram Dash
> 
> Subject: Re: [PATCH 1/2] common: usb_storage : Implement logic to calculate
> optimal usb maximum trasfer blocks
> 
> On 05/30/2016 01:23 PM, Rajesh Bhagat wrote:
> > Implements the logic to calculate the optimal usb maximum trasfer
> > blocks instead of sending USB_MAX_XFER_BLK blocks which is 65535 and
> > 20 in case of EHCI and other USB protocols respectively.
> >
> > It adds an array of trasfer blocks that should be checked for success
> > starting from minimum to maximum, and rest of the read/write are
> > performed with that optimal value. It tries to increase/decrease the
> > blocks in follwing scenarios:
> >
> > 1.decrease blocks: when read/write for a particular number of blocks
> > fails.
> > 2. increase blocks: when read/write for a particular number of blocks
> > pass and amount left to trasfer is greater than current number of
> > blocks.
> >
> > Currently changes are done for EHCI where min = 4096 andmax = 65535 is
> > taken. And for other cases code is left unchanged by keeping min = max
> > = 20.
> >
> > Signed-off-by: Sriram Dash 
> > Signed-off-by: Rajesh Bhagat 
> > ---
> >  common/usb_storage.c |   54
> --
> >  1 file changed, 43 insertions(+), 11 deletions(-)
> >
> > diff --git a/common/usb_storage.c b/common/usb_storage.c index
> > 7e6e52d..7b5ad07 100644
> > --- a/common/usb_storage.c
> > +++ b/common/usb_storage.c
> > @@ -101,16 +101,15 @@ struct us_data {  };
> >
> >  #ifdef CONFIG_USB_EHCI
> > -/*
> > - * The U-Boot EHCI driver can handle any transfer length as long as
> > there is
> > - * enough free heap space left, but the SCSI READ(10) and WRITE(10)
> > commands are
> > - * limited to 65535 blocks.
> > - */
> > -#define USB_MAX_XFER_BLK   65535
> > +#define USB_XFER_BLK_TBL_SZ5
> > +static unsigned short usb_xfer_blk_tbl[5] = {4096, 8192, 16384,
> > +32768, 65535};
> 
> You should stick to using one block less than the power of two, the 
> controllers react to
> that a bit better. 

Hello Marek,

I agree to above point, Will change the logic to use one block less than power 
of two
i.e. 4095, 8191... 65535

> Each value in this table can then be calculated really trivially, it's:
> 
> (1 << (12 + n)) - 1
> 

Prior to current implementation, I created USB_MIN_XFER_BLK=4096 and 
USB_MAX_XFER_BLK=65535 macros. And started the logic to multiple and divide 
by two to reach USB_MAX_XFER_BLK. Then thought, calculation would be costlier 
than indexing an array. 

Please comment. 

> You also don't need such static data.
> 

Let me share the background for keeping this variable, It is taken to store the 
last optimal value for next read/write operation. And these value is reset to 
minimum
when another USB device is connected.

Refer below log: 

1st time (Iterated over all the possible size)
=> mw 8100  400; mw a000  400; usb write 
a000 0 8; usb read 8100 0 8; cmp.b a000 8100 1000;

USB write: device 0 block # 0, count 524288 ... usb_read: retry #2, xfer_blk 
4096, smallblks 4096
usb_read: retry #2, xfer_blk 8192, smallblks 8192
usb_read: retry #2, xfer_blk 16384, smallblks 16384
usb_read: retry #2, xfer_blk 32768, smallblks 32768
usb_read: retry #2, xfer_blk 65535, smallblks 65535
usb_read: retry #2, xfer_blk 65535, smallblks 65535
usb_read: retry #2, xfer_blk 65535, smallblks 65535
usb_read: retry #2, xfer_blk 65535, smallblks 65535
usb_read: retry #2, xfer_blk 65535, smallblks 65535
usb_read: retry #2, xfer_blk 65535, smallblks 65535
usb_read: retry #2, xfer_blk 65535, smallblks 65535
usb_read: retry #2, xfer_blk 65535, smallblks 4103
524288 blocks write: OK

2nd time (It started form 65535 blocks as it is last optimal value)
=> mw 8100  400; mw a000  400; usb write 
a000 0 8; usb read 8100 0 8; cmp.b a000 8100 1000;

USB write: device 0 block # 0, count 524288 ... usb_read: retry #2, xfer_blk 
65535, smallblks 65535
usb_read: retry #2, xfer_blk 65535, smallblks 65535
usb_read: retry #2, xfer_blk 65535, smallblks 65535
usb_read: retry #2, xfer_blk 65535, smallblks 65535
usb_read: retry #2, xfer_blk 65535, smallblks 65535
usb_read: retry #2, xfer_blk 65535, smallblks 65535
usb_read: retry #2, xfer_blk 65535, smallblks 65535
usb_read: retry #2, xfer_blk 65535, smallblks 65535
usb_read: retry #2, xfer_blk 65535, smallblks 8
524288 blocks write: OK

And I observed this value is different for read/write, Hence second patch is 
sent for handle 
that situation. 

Best Regards,
Rajesh Bhagat 

> >  #else
> > -#define USB_MAX_XFER_BLK   20
> > +#define USB_XFER_BLK_TBL_SZ1
> > 

[U-Boot] u-boot-x86 sf probe fail

[杜睿哲_Pegatron]

Hi,

I use Coreboot with u-boot-x86 as payload to bring-up my Intel Atom C2000 
platform, but I cannot make my SPI flash(w25q128fv) to work.
Actually the SPI was detected under coreboot with correct ID, but in u-boot “sf 
probe” command, it just always failed.
After tracing and code dump, I found it was failed due to SPIS_FCERR in 
spi/ich.c spi_xfer function.
I totally have no idea why this happened and how to proceed my bring-up.
My u-boot-x86 is up-to-date version and the SPI use intel,ich9-spi compatible 
in my dts file.

Following is my dm tree and there is spi-flash device

=> dm tree
Class   Probed   Name

root[ + ]root_driver
serial  [ + ]|-- serial
keyboard[ + ]|-- keyboard
rtc [   ]|-- rtc
timer   [ + ]|-- tsc-timer
pci [ + ]`-- pci
pch [ + ]|-- pch@1f,0
irq [ + ]|   |-- irq-router
spi [   ]|   `-- spi
spi_flash   [   ]|   `-- spi-flash@0
pci_generic [   ]|-- pci_0:0.0
pci [ + ]|-- pci_0:1.0
pci_generic [   ]|   `-- pci_1:0.0
pci [ + ]|-- pci_0:3.0
pci_generic [   ]|-- pci_0:e.0
pci_generic [   ]|-- pci_0:f.0
pci_generic [   ]|-- pci_0:13.0
usb [   ]|-- ehci_pci
pci_generic [   ]|-- pci_0:17.0
pci_generic [   ]|-- pci_0:18.0
pci_generic [   ]`-- pci_0:1f.3
=>
Could you please give me some hint or tell me where I can reference? Thanks.

Regards,
Hilbert
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Re: [U-Boot] tools/env: check that redundant environments have equal size

[Andreas Fenkart]

Hi Tom

I thought there was something wrong with my april patches, so I
started reworking them. This patch is part of the rework. I broke it
out of the series to make it stand out of the other patches since it
might break behaviour. You can ignore it, it's part of the v2 series.
I will rebase my cleaned up patches when I have time. One problem
though is that the env-tools on master now have a compile error. I
will fix that and send out a patch soon...

Andreas

2016-05-30 20:01 GMT+02:00 Tom Rini :
> On Mon, May 30, 2016 at 01:59:51PM -0400, Tom Rini wrote:
>> On Thu, May 19, 2016 at 12:43:51PM +0200, Andreas Fenkart wrote:
>>
>> > For double buffering to work, the target buffer must always be big
>> > enough to hold all data. This can only be ensured if buffers are of
>> > equal size, otherwise one must be smaller and we risk data loss
>> > when copying from the bigger to the smaller.
>> >
>> > Signed-off-by: Andreas Fenkart 
>>
>> Applied to u-boot/master, thanks!
>
> Actually, wait, no, this one isn't, with your other series now applied,
> this doesn't apply cleanly, thanks!
>
> --
> Tom
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[U-Boot] [PATCH 1/2] nand: fix nand torture to use changed mtd api

[Max Krummenacher]

The mtd subsystem deprecated and renamed the direct use of the mtd_info
struct's functionpointers. Instead the corresponding mtd_xxx function
should be used.

See also:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=3c3c10bba1e4ccb75b41442e45c1a072f6cded19

Signed-off-by: Max Krummenacher 
---

 drivers/mtd/nand/nand_util.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index 71285b6..c957c69 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -847,7 +847,7 @@ int nand_torture(nand_info_t *nand, loff_t offset)
}
 
for (i = 0; i < patt_count; i++) {
-   err = nand->erase(nand, );
+   err = mtd_erase(nand, );
if (err) {
printf("%s: erase() failed for block at 0x%llx: %d\n",
nand->name, instr.addr, err);
@@ -855,7 +855,7 @@ int nand_torture(nand_info_t *nand, loff_t offset)
}
 
/* Make sure the block contains only 0xff bytes */
-   err = nand->read(nand, offset, nand->erasesize, , buf);
+   err = mtd_read(nand, offset, nand->erasesize, , buf);
if ((err && err != -EUCLEAN) || retlen != nand->erasesize) {
printf("%s: read() failed for block at 0x%llx: %d\n",
nand->name, instr.addr, err);
@@ -872,14 +872,14 @@ int nand_torture(nand_info_t *nand, loff_t offset)
 
/* Write a pattern and check it */
memset(buf, patterns[i], nand->erasesize);
-   err = nand->write(nand, offset, nand->erasesize, , buf);
+   err = mtd_write(nand, offset, nand->erasesize, , buf);
if (err || retlen != nand->erasesize) {
printf("%s: write() failed for block at 0x%llx: %d\n",
nand->name, instr.addr, err);
goto out;
}
 
-   err = nand->read(nand, offset, nand->erasesize, , buf);
+   err = mtd_read(nand, offset, nand->erasesize, , buf);
if ((err && err != -EUCLEAN) || retlen != nand->erasesize) {
printf("%s: read() failed for block at 0x%llx: %d\n",
nand->name, instr.addr, err);
-- 
2.5.5

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[U-Boot] [PATCH 2/2] nand: extend nand torture

[Max Krummenacher]

nand torture currently works on exactly one nand block which is specified
by giving the byteoffset to the beginning of the block.

Extend this by allowing for a second parameter specifying the byte offset
to the last block to be tested.

e.g.
==> nand torture 100

NAND torture: device 0 offset 0x100 size 0x2
passed 1, failed 0

==> nand torture 100 104

NAND torture: device 0 offset 0x100 size 0x2
passed 2, failed 0

Signed-off-by: Max Krummenacher 
---

 cmd/nand.c | 25 +
 1 file changed, 21 insertions(+), 4 deletions(-)

diff --git a/cmd/nand.c b/cmd/nand.c
index a6b67e2..615dbd5 100644
--- a/cmd/nand.c
+++ b/cmd/nand.c
@@ -646,6 +646,8 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 
 #ifdef CONFIG_CMD_NAND_TORTURE
if (strcmp(cmd, "torture") == 0) {
+   loff_t endoff;
+   unsigned failed = 0, passed = 0;
if (argc < 3)
goto usage;
 
@@ -653,13 +655,27 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
puts("Offset is not a valid number\n");
return 1;
}
-
+   endoff = off + nand->erasesize;
+   if (argc > 3)
+   if (!str2off(argv[3], )) {
+   puts("End is not a valid number\n");
+   return 1;
+   }
printf("\nNAND torture: device %d offset 0x%llx size 0x%x\n",
dev, off, nand->erasesize);
-   ret = nand_torture(nand, off);
-   printf(" %s\n", ret ? "Failed" : "Passed");
+   while (off < endoff) {
 
-   return ret == 0 ? 0 : 1;
+   ret = nand_torture(nand, off);
+   if (ret) {
+   failed++;
+   printf(" off 0x%llx %s\n", off, "Failed");
+   } else {
+   passed++;
+   }
+   off += nand->erasesize;
+   }
+   printf("passed %u, failed %u\n", passed, failed);
+   return failed == 0 ? 0 : 1;
}
 #endif
 
@@ -775,6 +791,7 @@ static char nand_help_text[] =
"nand dump[.oob] off - dump page\n"
 #ifdef CONFIG_CMD_NAND_TORTURE
"nand torture off - torture block at offset\n"
+   "nand torture start end - torture blocks from start to end offset\n"
 #endif
"nand scrub [-y] off size | scrub.part partition | scrub.chip\n"
"really clean NAND erasing bad blocks (UNSAFE)\n"
-- 
2.5.5

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[U-Boot] [PATCH] ARM: uniphier: do not overwrite fdt_file environment

[Masahiro Yamada]

This code auto-detects the best-match FDT file name, but it should
respect the user's choice if "fdt_file" environment is found in
a non-volatile device.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/board_late_init.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-uniphier/board_late_init.c 
b/arch/arm/mach-uniphier/board_late_init.c
index 845f047..eabf2b5 100644
--- a/arch/arm/mach-uniphier/board_late_init.c
+++ b/arch/arm/mach-uniphier/board_late_init.c
@@ -39,6 +39,9 @@ static int uniphier_set_fdt_file(void)
int buf_len = 256;
int ret;
 
+   if (getenv("fdt_file"))
+   return 0;   /* do nothing if it is already set */
+
ret = fdt_get_string(gd->fdt_blob, 0, "compatible", );
if (ret)
return -EINVAL;
-- 
1.9.1

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Re: [U-Boot] [PATCH] Revert "image.h: Tighten up content using handy CONFIG_IS_ENABLED() macro."

[Masahiro Yamada]

Hi.

2016-05-31 21:05 GMT+09:00 Robert P. J. Day :
> On Tue, 31 May 2016, Masahiro Yamada wrote:
>
>> This reverts commit 56adbb38727320375b2f695bd04600d766d8a1b3.
>>
>> Since commit 56adbb387273 ("image.h: Tighten up content using handy
>> CONFIG_IS_ENABLED() macro."), I found my boards fail to boot Linux
>> because the commit changed the logic of macros it touched.  Now,
>> IMAGE_ENABLE_RAMDISK_HIGH and IMAGE_BOOT_GET_CMDLINE are 0 for all
>> the boards.
>>
>> As you can see in include/linux/kconfig.h, CONFIG_IS_ENABLE() (and
>> IS_ENABLED() as well) can only take a macro that is either defined
>> as 1 or undefined.  This is met for boolean options defined in
>> Kconfig.  On the other hand, CONFIG_SYS_BOOT_RAMDISK_HIGH and
>> CONFIG_SYS_BOOT_GET_CMDLINE are defined without any value in
>> arch/*/include/asm/config.h .  This kind of clean-up is welcome,
>> but the options should be moved to Kconfig beforehand.
>
> ... snip ...
>
>   whoops, that would be my fault, i never considered that possibility,
> i thought this was a fairly straightforward (and mostly aesthetic)
> change.
>
>   it seems that there is a fair amount of inconsistent usage of CONFIG
> settings, as in, if one wants to test only if a setting is defined:
>
>   #ifdef CONFIG_FOO
>
> then it's sufficient to manually set:
>
>   #define CONFIG_FOO
>
> however, in the above, it doesn't hurt to also write:
>
>   #define CONFIG_FOO 1
>
> but the instant you do that, you can *also* then test:
>
>   #if CONFIG_FOO
>
> and i'm wondering how much there is of mixing both tests; that is,
> once you write this:
>
>   #define CONFIG_FOO 1
>
> you have a tendency to start using both tests:
>
>   #ifdef CONFIG_FOO
>   #if CONFIG_FOO
>
> which is definitely messy. anyway, my fault for not looking at the
> above carefully enough before submitting.
>


IS_ENABLED() (and include/linux/kernel.h) came from Linux Kernel.

So, you should understand things in Linux side.

Is Linux, all CONFIG options are defined in Kconfig.
(there is only one exception, CONFIG_SHELL, though.)

As you see in include/generated/autoconf.h,
all the boolean options are either defined as 1
or not defined at all.

So,
>   #define CONFIG_FOO
this case (definition without any value) never happens in Linux Kernel.


#if CONFIG_FOO
is error when CONFIG_FOO is not defined.
(notice, boolean CONFIG options are defined as 1 or undefined.
no case for defined as 0.)


I know two benefits of IS_ENABLED().

[1]
If CONFIG_FOO=y in Kconfig,
CONFIG_FOO is defined in include/generated/autoconf.h

If CONFIG_FOO=m in Kconfig,
CONFIG_FOO_MODULE is defined in include/generated/autoconf.h

So, before IS_ENABLED() was invented, we used to write like follows

#if defined(CONFIG_FOO) || defined(CONFIG_FOO_MODULE)
  ...
#end


Now, we can use it as a shorthand

#if IS_ENABLED(CONFIG_FOO)
  ...
#end


[2]
IS_ENABLED() can be used in C context.

if (CONFIG_FOO) {
 printk("CONFIG_FOO is defined\n");
}

causes build error if CONFIG_FOO is not defined at all.
(again, no possibilit for  #define CONFIG_FOO   0)

if (IS_ENABLED(CONFIG_FOO)) {
 printk("CONFIG_FOO is defined\n");
}

works as expected because IS_ENABLED(CONFIG_FOO) is evaluated to 0
when CONFIG_FOO is not defined.



In U-Boot, things are much more complicated.
Historically, all CONFIGs were defined in C headers
(and still many are defined there)

For those, both style
#define CONFIG_FOO
#define CONFIG_FOO  1
exist because it did not matter at all.

Since Kconfig was introduced to U-Boot,
we have moved many options to Kconfig, but the migration is still under way.


#define CONFIG_FOO  1
is only used in Kconfig.


What is more complex about U-Boot is
it supports multiple image generation from one config.


It is too painful to write

#if  (!defined(CONFIG_SPL_BUILD) && defined(CONFIG_FOO)) ||
  (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FOO))

so, a shorthand

#if CONFIG_IS_ENABLED(CONFIG_FOO)

was added.


They are handy, but we have to take care of their correct usage.


-- 
Best Regards
Masahiro Yamada
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Re: [U-Boot] [RFC PATCH 1/5] spl: dfu: add dfu support in SPL

[Lukasz Majewski]

Hi Ravi,

> Hi Lukasz
> 
> >> >> Since DFU is tighly coupled to u-boot infrastructure , the size 
> >> >> will increase due to multiple dependencies to compile u-boot
> >> >> DFU source in SPL. Let me re-think on possibility and come back.
> >> 
> >> >If you would need any assistance, please let me know (I don't
> >> >have dra7x, but I do have Beagle Bone Black).
> >> 
> >> The current implementation of dfu (drivers/dfu/dfu.c) relies on 
> >> environment modules (getenv,setenv), and hash algo methods. The 
> >> mandatory modules for DFU includes USB(dwc3/musb), gadget, 
> >> drivers/dfu, hash, environ modules. Added to this mmc/sf support,
> >> with filesystem fat/ext4 would definitely increase the size.
> >> 
> 
> >I've double checked BBB SPL setup:
> 
> >- SPL is the MLO (./common/spl/)
> >- Its size shall be less than 128 KiB
> >- It can reside on eMMC (fat partition, raw LBA offset), NAND or be
> >sent
>  > via serial port.
> 
> >I've build the am335x_boneblack_defconfig and MLO size is 75 KiB.
> 
> >Please correct me, but it seems that the SPL-DFU support adds around
> >30 KiB to SPL binary size.
> 
> 30KB+ is just approx size optimitzed for DFU-SF (qspi) support only,

So the 30KiB+ is for the DFU-SF support only.

> without fat/ext4, mmc support. But all device support may increase
> size.

Ok.

However, adding fat/ext4/mmc (and other) support should be on demand
(and enabled by proper Kconfig options).

This would allow others to add only what is really needed.

> 
> >If yes, then even BBB's SPL can support DFU without any problems
> >(105KiB < 128 KiB).
> 
> You mean BBB must have 128KB ? Can you confirm.

I didn't find any _hard_ rule about the size.

In the am335x_evm.h file the spice reserved for SPL (on raw eMMC) is 128
KiB.

> If BBB is support SPI boot, flashing MLO/U-boot to SPI-flash through
> SPL-DFU/SF would be sufficient right ?

I don't know the exact use cases, but yes, BBB can boot from SPI flash.


I'm just wondering - the use case for your board is to use USB to flash
your device in u-boot SPL. 
If I might ask, why cannot you wait for the U-Boot to use fully-fledged
DFU for flashing?


> Further dfu support for
> mmc/sd, ram available from u-boot.
> 
> >>I'm also wondering if we could even shrink the code more with
> >>reusing or extending the code at ./common/spl/spl_{ext|fat|mmc|sf,
> >>etc}.c (in this way we avoid adding the whole fat, ext, sf
> >>"commands").
> 
> Yes we must see this option. I will check on this.
> 
> >>For more aggressive size reduction we could for example disable
> >>hash algo checking and add ./common/spl/spl_dfu.c file with
> >>ordinary functions and rid of the need to add the whole dfu command.
> 
> >> I have tried minimal subset adding DFU-SF serial flash support
> >> alone in SPL, this itself increases SPL size to 30K+ (SPL size
> >> approx. 107KB for dra7x). 
> >> 
> >> But beagle bone IRAM would be around 64KB right? Definetly this
> >> will not fit.
> >> 
> >> Can we enable this feature for platform with minimum SRAM size of 
> >> 160KB. So SPL-DFU cannot be supported for platform less than 160KB 
> >> (like am335x).
> 
> >I will ask on ML if there is any other interested party in SPL-DFU
> >support (and what are their limitations of SPL code size).
> 
> OK.
> 
> Regards
> Ravi 
> 



-- 
Best regards,

Lukasz Majewski

Samsung R Institute Poland (SRPOL) | Linux Platform Group
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Re: [U-Boot] [PATCH] Revert "image.h: Tighten up content using handy CONFIG_IS_ENABLED() macro."

[Robert P. J. Day]

On Tue, 31 May 2016, Masahiro Yamada wrote:

> This reverts commit 56adbb38727320375b2f695bd04600d766d8a1b3.
>
> Since commit 56adbb387273 ("image.h: Tighten up content using handy
> CONFIG_IS_ENABLED() macro."), I found my boards fail to boot Linux
> because the commit changed the logic of macros it touched.  Now,
> IMAGE_ENABLE_RAMDISK_HIGH and IMAGE_BOOT_GET_CMDLINE are 0 for all
> the boards.
>
> As you can see in include/linux/kconfig.h, CONFIG_IS_ENABLE() (and
> IS_ENABLED() as well) can only take a macro that is either defined
> as 1 or undefined.  This is met for boolean options defined in
> Kconfig.  On the other hand, CONFIG_SYS_BOOT_RAMDISK_HIGH and
> CONFIG_SYS_BOOT_GET_CMDLINE are defined without any value in
> arch/*/include/asm/config.h .  This kind of clean-up is welcome,
> but the options should be moved to Kconfig beforehand.

... snip ...

  whoops, that would be my fault, i never considered that possibility,
i thought this was a fairly straightforward (and mostly aesthetic)
change.

  it seems that there is a fair amount of inconsistent usage of CONFIG
settings, as in, if one wants to test only if a setting is defined:

  #ifdef CONFIG_FOO

then it's sufficient to manually set:

  #define CONFIG_FOO

however, in the above, it doesn't hurt to also write:

  #define CONFIG_FOO 1

but the instant you do that, you can *also* then test:

  #if CONFIG_FOO

and i'm wondering how much there is of mixing both tests; that is,
once you write this:

  #define CONFIG_FOO 1

you have a tendency to start using both tests:

  #ifdef CONFIG_FOO
  #if CONFIG_FOO

which is definitely messy. anyway, my fault for not looking at the
above carefully enough before submitting.

rday

-- 


Robert P. J. Day Ottawa, Ontario, CANADA
http://crashcourse.ca

Twitter:   http://twitter.com/rpjday
LinkedIn:   http://ca.linkedin.com/in/rpjday


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Re: [U-Boot] [PATCH 1/2] common: usb_storage : Implement logic to calculate optimal usb maximum trasfer blocks

[Marek Vasut]

On 05/31/2016 05:23 AM, Rajesh Bhagat wrote:
> 
> 
>> -Original Message-
>> From: Marek Vasut [mailto:ma...@denx.de]
>> Sent: Tuesday, May 31, 2016 5:12 AM
>> To: Rajesh Bhagat ; u-boot@lists.denx.de
>> Cc: s...@chromium.org; york sun ; Sriram Dash
>> 
>> Subject: Re: [PATCH 1/2] common: usb_storage : Implement logic to calculate
>> optimal usb maximum trasfer blocks
>>
>> On 05/30/2016 01:23 PM, Rajesh Bhagat wrote:
>>> Implements the logic to calculate the optimal usb maximum trasfer
>>> blocks instead of sending USB_MAX_XFER_BLK blocks which is 65535 and
>>> 20 in case of EHCI and other USB protocols respectively.
>>>
>>> It adds an array of trasfer blocks that should be checked for success
>>> starting from minimum to maximum, and rest of the read/write are
>>> performed with that optimal value. It tries to increase/decrease the
>>> blocks in follwing scenarios:
>>>
>>> 1.decrease blocks: when read/write for a particular number of blocks
>>> fails.
>>> 2. increase blocks: when read/write for a particular number of blocks
>>> pass and amount left to trasfer is greater than current number of
>>> blocks.
>>>
>>> Currently changes are done for EHCI where min = 4096 andmax = 65535 is
>>> taken. And for other cases code is left unchanged by keeping min = max
>>> = 20.
>>>
>>> Signed-off-by: Sriram Dash 
>>> Signed-off-by: Rajesh Bhagat 
>>> ---
>>>  common/usb_storage.c |   54
>> --
>>>  1 file changed, 43 insertions(+), 11 deletions(-)
>>>
>>> diff --git a/common/usb_storage.c b/common/usb_storage.c index
>>> 7e6e52d..7b5ad07 100644
>>> --- a/common/usb_storage.c
>>> +++ b/common/usb_storage.c
>>> @@ -101,16 +101,15 @@ struct us_data {  };
>>>
>>>  #ifdef CONFIG_USB_EHCI
>>> -/*
>>> - * The U-Boot EHCI driver can handle any transfer length as long as
>>> there is
>>> - * enough free heap space left, but the SCSI READ(10) and WRITE(10)
>>> commands are
>>> - * limited to 65535 blocks.
>>> - */
>>> -#define USB_MAX_XFER_BLK   65535
>>> +#define USB_XFER_BLK_TBL_SZ5
>>> +static unsigned short usb_xfer_blk_tbl[5] = {4096, 8192, 16384,
>>> +32768, 65535};
>>
>> You should stick to using one block less than the power of two, the 
>> controllers react to
>> that a bit better. 
> 
> Hello Marek,
> 
> I agree to above point, Will change the logic to use one block less than 
> power of two
> i.e. 4095, 8191... 65535
> 
>> Each value in this table can then be calculated really trivially, it's:
>>
>> (1 << (12 + n)) - 1
>>
> 
> Prior to current implementation, I created USB_MIN_XFER_BLK=4096 and 
> USB_MAX_XFER_BLK=65535 macros. And started the logic to multiple and divide 
> by two to reach USB_MAX_XFER_BLK. Then thought, calculation would be costlier 
> than indexing an array. 

Since the numbers are 16bit tops, they will most likely end up being
optimized to mov rN, #imm16 or mov rN, imm16 + sub rN, #1 . That's two
local instructions tops, which will always be at least as fast as any
memory fetch.

> Please comment. 
> 
>> You also don't need such static data.
>>
> 
> Let me share the background for keeping this variable, It is taken to store 
> the 
> last optimal value for next read/write operation. And these value is reset to 
> minimum
> when another USB device is connected.

Consider the scenario where you have two sticks plugged in and mix
reading from both. Your approach with static variable will fail miserably.

> Refer below log: 
> 
> 1st time (Iterated over all the possible size)
> => mw 8100  400; mw a000  400; usb write 
> a000 0 8; usb read 8100 0 8; cmp.b a000 8100 1000;
> 
> USB write: device 0 block # 0, count 524288 ... usb_read: retry #2, xfer_blk 
> 4096, smallblks 4096
> usb_read: retry #2, xfer_blk 8192, smallblks 8192
> usb_read: retry #2, xfer_blk 16384, smallblks 16384
> usb_read: retry #2, xfer_blk 32768, smallblks 32768
> usb_read: retry #2, xfer_blk 65535, smallblks 65535
> usb_read: retry #2, xfer_blk 65535, smallblks 65535
> usb_read: retry #2, xfer_blk 65535, smallblks 65535
> usb_read: retry #2, xfer_blk 65535, smallblks 65535
> usb_read: retry #2, xfer_blk 65535, smallblks 65535
> usb_read: retry #2, xfer_blk 65535, smallblks 65535
> usb_read: retry #2, xfer_blk 65535, smallblks 65535
> usb_read: retry #2, xfer_blk 65535, smallblks 4103
> 524288 blocks write: OK
> 
> 2nd time (It started form 65535 blocks as it is last optimal value)
> => mw 8100  400; mw a000  400; usb write 
> a000 0 8; usb read 8100 0 8; cmp.b a000 8100 1000;
> 
> USB write: device 0 block # 0, count 524288 ... usb_read: retry #2, xfer_blk 
> 65535, smallblks 65535
> usb_read: retry #2, xfer_blk 65535, smallblks 65535
> usb_read: retry #2, xfer_blk 65535, smallblks 65535
> usb_read: retry #2, xfer_blk 65535, smallblks 

[U-Boot] [PATCH v2 6/7] dfu, nand, ubi: fix erasing after write finish

[Heiko Schocher]

writting to ubi nand partitions need after write ends an erase
of the remaining sectors. This fail, if dfu write size was not
a multiple of erasesize, example log:

Failure erase: -1

Fix this error.

Signed-off-by: Heiko Schocher 

---

Changes in v2:
- rebase to current mainline commit id:
  e4a94ce4ac77396b181663c0493c50bc2d5b9143
  and the "mtd: nand Sync with Linux v4.6" patches:
  [U-Boot,1/7] mtd: nand: Remove jz4740 driver
  http://patchwork.ozlabs.org/patch/627922/
  [U-Boot,2/7] mtd: nand: Remove docg4 driver and palmtreo680 flashing tool
  http://patchwork.ozlabs.org/patch/627924/
  [U-Boot,3/7] mtd: nand: Remove nand_info_t typedef
  http://patchwork.ozlabs.org/patch/627923/
  [U-Boot,4/7] nand: Embed mtd_info in struct nand_chip
  http://patchwork.ozlabs.org/patch/627925/
  [U-Boot,5/7] mtd: nand: Add+use mtd_to/from_nand and 
nand_get/set_controller_data
  http://patchwork.ozlabs.org/patch/627926/
  [U-Boot,6/7] mtd: nand: Add page argument to write_page() etc.
  http://patchwork.ozlabs.org/patch/627927/
  [U-Boot,7/7] mtd: nand: Sync with Linux v4.6
  http://patchwork.ozlabs.org/patch/627928/

 drivers/dfu/dfu_nand.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c
index 5906057..1ca10d4 100644
--- a/drivers/dfu/dfu_nand.c
+++ b/drivers/dfu/dfu_nand.c
@@ -143,6 +143,7 @@ static int dfu_read_medium_nand(struct dfu_entity *dfu, u64 
offset, void *buf,
 static int dfu_flush_medium_nand(struct dfu_entity *dfu)
 {
int ret = 0;
+   u64 off;
 
/* in case of ubi partition, erase rest of the partition */
if (dfu->data.nand.ubi) {
@@ -159,7 +160,16 @@ static int dfu_flush_medium_nand(struct dfu_entity *dfu)
mtd = nand_info[nand_curr_device];
 
memset(, 0, sizeof(opts));
-   opts.offset = dfu->data.nand.start + dfu->offset +
+   off = dfu->offset;
+   if ((off & (mtd->erasesize - 1)) != 0) {
+   /*
+* last write ended with unaligned length
+* sector is erased, jump to next
+*/
+   off = off & ~((mtd->erasesize - 1));
+   off += mtd->erasesize;
+   }
+   opts.offset = dfu->data.nand.start + off +
dfu->bad_skip;
opts.length = dfu->data.nand.start +
dfu->data.nand.size - opts.offset;
-- 
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[U-Boot] [PATCH v2 7/7] siemens,am33x: add draco etamin board

[Heiko Schocher]

In the draco CPU board family, etamin is a new variant
with bigger flash and more RAM. Due to new flash that
uses larger pages (4K) some changes are necessary because
it impacts the MTD partition layout and the ubi mount
parameters.

Signed-off-by: Samuel Egli 
Signed-off-by: Heiko Schocher 
---

Changes in v2: None

 arch/arm/Kconfig   |   5 +
 board/siemens/common/board.c   |   4 +
 board/siemens/draco/Kconfig|  16 ++
 board/siemens/draco/MAINTAINERS|   1 +
 board/siemens/draco/board.c|  39 -
 board/siemens/draco/mux.c  |   2 +-
 configs/etamin_defconfig   |  17 +++
 include/configs/draco.h|   1 +
 include/configs/etamin.h   | 261 +
 include/configs/pxm2.h |   1 +
 include/configs/rastaban.h |   1 +
 include/configs/rut.h  |   1 +
 include/configs/siemens-am33x-common.h |   5 +-
 include/configs/thuban.h   |   1 +
 14 files changed, 351 insertions(+), 4 deletions(-)
 create mode 100644 configs/etamin_defconfig
 create mode 100644 include/configs/etamin.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7a77b6a..d79ec3d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -339,6 +339,11 @@ config TARGET_RASTABAN
select CPU_V7
select SUPPORT_SPL
 
+config TARGET_ETAMIN
+bool "Support etamin"
+select CPU_V7
+select SUPPORT_SPL
+
 config TARGET_PXM2
bool "Support pxm2"
select CPU_V7
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index c127f6c..9cafcea 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@@ -83,8 +83,12 @@ int board_init(void)
 #ifdef CONFIG_FACTORYSET
factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR);
 #endif
+
gpmc_init();
 
+#ifdef CONFIG_NAND_CS_INIT
+   board_nand_cs_init();
+#endif
 #ifdef CONFIG_VIDEO
board_video_init();
 #endif
diff --git a/board/siemens/draco/Kconfig b/board/siemens/draco/Kconfig
index 819d187..a699c7d 100644
--- a/board/siemens/draco/Kconfig
+++ b/board/siemens/draco/Kconfig
@@ -45,3 +45,19 @@ config SYS_CONFIG_NAME
default "rastaban"
 
 endif
+
+if TARGET_ETAMIN
+
+config SYS_BOARD
+default "draco"
+
+config SYS_VENDOR
+default "siemens"
+
+config SYS_SOC
+default "am33xx"
+
+config SYS_CONFIG_NAME
+default "etamin"
+
+endif
diff --git a/board/siemens/draco/MAINTAINERS b/board/siemens/draco/MAINTAINERS
index 484dd73..e9107f0 100644
--- a/board/siemens/draco/MAINTAINERS
+++ b/board/siemens/draco/MAINTAINERS
@@ -4,6 +4,7 @@ S:  Maintained
 F: board/siemens/draco/
 F: include/configs/draco.h
 F: configs/draco_defconfig
+F: configs/etamin_defconfig
 F: include/configs/thuban.h
 F: configs/thuban_defconfig
 F: include/configs/rastaban.h
diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c
index 41bdef0..d8869a0 100644
--- a/board/siemens/draco/board.c
+++ b/board/siemens/draco/board.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -33,6 +34,7 @@
 #include 
 #include "board.h"
 #include "../common/factoryset.h"
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -40,6 +42,7 @@ DECLARE_GLOBAL_DATA_PTR;
 static struct draco_baseboard_id __attribute__((section(".data"))) settings;
 
 #if DDR_PLL_FREQ == 303
+#if !defined(CONFIG_TARGET_ETAMIN)
 /* Default@303MHz-i0 */
 const struct ddr3_data ddr3_default = {
0x3352, 0x56312e35, 0x0080, 0x, 0x003A, 0x003F, 0x009F,
@@ -48,6 +51,16 @@ const struct ddr3_data ddr3_default = {
"default name @303MHz   \0",
"default marking\0",
 };
+#else
+/* etamin board */
+const struct ddr3_data ddr3_default = {
+   0x3352, 0x56312e36, 0x0080, 0x, 0x003A, 0x0010, 0x009F,
+   0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2,
+   0x093B, 0x018A,
+   "test-etamin\0",
+   "generic-8Gbit  \0",
+};
+#endif
 #elif DDR_PLL_FREQ == 400
 /* Default@400MHz-i0 */
 const struct ddr3_data ddr3_default = {
@@ -210,6 +223,7 @@ struct ctrl_ioregs draco_ddr3_ioregs = {
draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
settings.ddr3.emif_ddr_phy_ctlr_1;
draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
+   draco_ddr3_emif_reg_data.sdram_config2 = 0x0800;
draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
 
draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
@@ -251,6 +265,10 @@ int board_late_init(void)
 
nand_curr_device = 0;
omap_nand_switch_ecc(1, ecc_type);
+#ifdef CONFIG_TARGET_ETAMIN
+   nand_curr_device = 1;
+   omap_nand_switch_ecc(1, ecc_type);
+#endif
 #ifdef CONFIG_FACTORYSET
/* 

[U-Boot] [PATCH v2 5/7] am335x, dxr2: get ECC sType from I2C eeprom

[Heiko Schocher]

read the ECC Type field from the i2c eeprom, instead
configuring it static in the U-Boot binary.

see RM:
Table 26-17. NAND Geometry Information on I2C EEPROM

Signed-off-by: Heiko Schocher 

---

Changes in v2:
- rebase to current mainline commit id:
  e4a94ce4ac77396b181663c0493c50bc2d5b9143

 board/siemens/draco/board.c | 45 -
 1 file changed, 44 insertions(+), 1 deletion(-)

diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c
index 988c12a..41bdef0 100644
--- a/board/siemens/draco/board.c
+++ b/board/siemens/draco/board.c
@@ -105,6 +105,40 @@ static void print_chip_data(void)
 }
 #endif /* CONFIG_SPL_BUILD */
 
+#define AM335X_NAND_ECC_MASK 0x0f
+#define AM335X_NAND_ECC_TYPE_16 0x02
+
+static int ecc_type;
+
+struct am335x_nand_geometry {
+   u32 magic;
+   u8 nand_geo_addr;
+   u8 nand_geo_page;
+   u8 nand_bus;
+};
+
+static int draco_read_nand_geometry(void)
+{
+   struct am335x_nand_geometry geo;
+
+   /* Read NAND geometry */
+   if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2,
+(uchar *), sizeof(struct am335x_nand_geometry))) {
+   printf("Could not read the NAND geomtery; something 
fundamentally wrong on the I2C bus.\n");
+   return -EIO;
+   }
+   if (geo.magic != 0xa657b310) {
+   printf("%s: bad magic: %x\n", __func__, geo.magic);
+   return -EFAULT;
+   }
+   if ((geo.nand_bus & AM335X_NAND_ECC_MASK) == AM335X_NAND_ECC_TYPE_16)
+   ecc_type = 16;
+   else
+   ecc_type = 8;
+
+   return 0;
+}
+
 /*
  * Read header information from EEPROM into global structure.
  */
@@ -147,6 +181,8 @@ static int read_eeprom(void)
printf("Warning: No chip data in eeprom\n");
 
print_ddr3_timings();
+
+   return draco_read_nand_geometry();
 #endif
return 0;
 }
@@ -207,7 +243,14 @@ static void spl_siemens_board_init(void)
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
-   omap_nand_switch_ecc(1, 8);
+   int ret;
+
+   ret = draco_read_nand_geometry();
+   if (ret != 0)
+   return ret;
+
+   nand_curr_device = 0;
+   omap_nand_switch_ecc(1, ecc_type);
 #ifdef CONFIG_FACTORYSET
/* Set ASN in environment*/
if (factory_dat.asn[0] != 0) {
-- 
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[U-Boot] [PATCH v2 4/7] mtd: nand: omap: allow to switch to BCH16

[Heiko Schocher]

support in omap_nand_switch_ecc() also an eccstrength
from 16.

Signed-off-by: Heiko Schocher 
---

Changes in v2:
- rebase to current mainline commit id:
  e4a94ce4ac77396b181663c0493c50bc2d5b9143

 arch/arm/cpu/armv7/omap3/board.c | 6 --
 drivers/mtd/nand/omap_gpmc.c | 4 
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 0c44ea5..5f55977 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -280,6 +280,8 @@ static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int 
argc, char * const arg
omap_nand_switch_ecc(1, 1);
else if (strncmp(argv[2], "bch8", 4) == 0)
omap_nand_switch_ecc(1, 8);
+   else if (strncmp(argv[2], "bch16", 5) == 0)
+   omap_nand_switch_ecc(1, 16);
else
goto usage;
}
@@ -308,8 +310,8 @@ usage:
 U_BOOT_CMD(
nandecc, 3, 1,  do_switch_ecc,
"switch OMAP3 NAND ECC calculation algorithm",
-   "hw [hamming|bch8] - Switch between NAND hardware 1-bit hamming and"
-   " 8-bit BCH\n"
+   "hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming"
+   " and 8-bit/16-bit BCH\n"
"   ecc calculation (second parameter may"
" be omitted).\n"
"nandecc sw   - Switch to NAND software ecc algorithm."
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index 37c4341..67f293d 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -917,6 +917,10 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, 
uint32_t eccstrength)
err = omap_select_ecc_scheme(nand,
OMAP_ECC_BCH8_CODE_HW,
mtd->writesize, mtd->oobsize);
+   } else if (eccstrength == 16) {
+   err = omap_select_ecc_scheme(nand,
+   OMAP_ECC_BCH16_CODE_HW,
+   mtd->writesize, mtd->oobsize);
} else {
printf("nand: error: unsupported ECC scheme\n");
return -EINVAL;
-- 
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[U-Boot] [PATCH v2 2/7] ubi: add new ubi command "ubi detach"

[Heiko Schocher]

simple detachs ubi from the mtd partition.

Signed-off-by: Heiko Schocher 

---

Changes in v2:
- add comments from Scott Wood:
  - correct spelling error "dettach" -> "detach"
  - use "o...@buserror.net" as email address for Scott
- rebase to current mainline commit id:
  e4a94ce4ac77396b181663c0493c50bc2d5b9143

 cmd/ubi.c | 38 +++---
 1 file changed, 27 insertions(+), 11 deletions(-)

diff --git a/cmd/ubi.c b/cmd/ubi.c
index 753a4db..4a92d84 100644
--- a/cmd/ubi.c
+++ b/cmd/ubi.c
@@ -443,14 +443,8 @@ static int ubi_dev_scan(struct mtd_info *info, char 
*ubidev,
return 0;
 }
 
-int ubi_part(char *part_name, const char *vid_header_offset)
+int ubi_detach(void)
 {
-   int err = 0;
-   char mtd_dev[16];
-   struct mtd_device *dev;
-   struct part_info *part;
-   u8 pnum;
-
if (mtdparts_init() != 0) {
printf("Error initializing mtdparts!\n");
return 1;
@@ -466,17 +460,28 @@ int ubi_part(char *part_name, const char 
*vid_header_offset)
cmd_ubifs_umount();
 #endif
 
-   /* todo: get dev number for NAND... */
-   ubi_dev.nr = 0;
-
/*
 * Call ubi_exit() before re-initializing the UBI subsystem
 */
if (ubi_initialized) {
ubi_exit();
del_mtd_partitions(ubi_dev.mtd_info);
+   ubi_initialized = 0;
}
 
+   ubi_dev.selected = 0;
+   return 0;
+}
+
+int ubi_part(char *part_name, const char *vid_header_offset)
+{
+   int err = 0;
+   char mtd_dev[16];
+   struct mtd_device *dev;
+   struct part_info *part;
+   u8 pnum;
+
+   ubi_detach();
/*
 * Search the mtd device number where this partition
 * is located
@@ -517,6 +522,15 @@ static int do_ubi(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
if (argc < 2)
return CMD_RET_USAGE;
 
+
+   if (strcmp(argv[1], "detach") == 0) {
+   if (argc < 2)
+   return CMD_RET_USAGE;
+
+   return ubi_detach();
+   }
+
+
if (strcmp(argv[1], "part") == 0) {
const char *vid_header_offset = NULL;
 
@@ -661,7 +675,9 @@ static int do_ubi(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 U_BOOT_CMD(
ubi, 6, 1, do_ubi,
"ubi commands",
-   "part [part] [offset]\n"
+   "detach"
+   " - detach ubi from a mtd partition\n"
+   "ubi part [part] [offset]\n"
" - Show or set current partition (with optional VID"
" header offset)\n"
"ubi info [l[ayout]]"
-- 
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[U-Boot] [PATCH v2 3/7] nand: add nand mtd concat support

[Heiko Schocher]

add for nand devices mtd concat support. Generic MTD concat
support is already ported to mainline, and used in the cfi_mtd
driver. This patch adds it similiar for nand devices.

Signed-off-by: Heiko Schocher 

---

Changes in v2:
- add comments from Scott Wood:
  - move c_mtd_name from file scope to local
  - use nand_info instead mtd_nand_list
  - use o...@buserror.net as email address for Scott
- rebase to current mainline commit id:
  e4a94ce4ac77396b181663c0493c50bc2d5b9143
  and the "mtd: nand Sync with Linux v4.6" patches:
  [U-Boot,1/7] mtd: nand: Remove jz4740 driver
  http://patchwork.ozlabs.org/patch/627922/
  [U-Boot,2/7] mtd: nand: Remove docg4 driver and palmtreo680 flashing tool
  http://patchwork.ozlabs.org/patch/627924/
  [U-Boot,3/7] mtd: nand: Remove nand_info_t typedef
  http://patchwork.ozlabs.org/patch/627923/
  [U-Boot,4/7] nand: Embed mtd_info in struct nand_chip
  http://patchwork.ozlabs.org/patch/627925/
  [U-Boot,5/7] mtd: nand: Add+use mtd_to/from_nand and 
nand_get/set_controller_data
  http://patchwork.ozlabs.org/patch/627926/
  [U-Boot,6/7] mtd: nand: Add page argument to write_page() etc.
  http://patchwork.ozlabs.org/patch/627927/
  [U-Boot,7/7] mtd: nand: Sync with Linux v4.6
  http://patchwork.ozlabs.org/patch/627928/

 drivers/mtd/nand/nand.c | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index f449316..95ee37b 100644
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #ifndef CONFIG_SYS_NAND_BASE_LIST
 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
@@ -30,6 +31,10 @@ static char dev_name[CONFIG_SYS_MAX_NAND_DEVICE][8];
 
 static unsigned long total_nand_size; /* in kiB */
 
+#ifdef CONFIG_MTD_CONCAT
+static int nand_devices_found;
+#endif
+
 int nand_mtd_to_devnum(struct mtd_info *mtd)
 {
int i;
@@ -59,6 +64,9 @@ int nand_register(int devnum, struct mtd_info *mtd)
 * via the mtdcore infrastructure (e.g. ubi).
 */
add_mtd_device(mtd);
+#ifdef CONFIG_MTD_CONCAT
+   nand_devices_found++;
+#endif
 #endif
 
total_nand_size += mtd->size / 1024;
@@ -112,4 +120,23 @@ void nand_init(void)
board_nand_select_device(mtd_to_nand(nand_info[nand_curr_device]),
 nand_curr_device);
 #endif
+
+#ifdef CONFIG_MTD_CONCAT
+   if (nand_devices_found > 1) {
+   struct mtd_info *mtd;
+   char c_mtd_name[16];
+
+   /*
+* We detected multiple devices. Concatenate them together.
+*/
+   sprintf(c_mtd_name, "nand%d", nand_devices_found);
+   mtd = mtd_concat_create(nand_info, nand_devices_found,
+   c_mtd_name);
+
+   if (mtd == NULL)
+   return;
+
+   nand_register(nand_devices_found, mtd);
+   }
+#endif /* CONFIG_MTD_CONCAT */
 }
-- 
2.5.5

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[U-Boot] [PATCH v2 0/7] add support for the etamin draco board variant.

[Heiko Schocher]

In the draco CPU board family, etamin is a new variant
with bigger flash and more RAM. Due to new flash that
uses larger pages (4K) some changes are necessary because
it impacts the MTD partition layout and the ubi mount
parameters.

special here is:
- adding MTD concat support for nand flashs
- add UBI Fastmap support for the siemens boards
- fix a bug in dfu/nand when erasing remaining blocks on
  ubi partitions.
- nand on etamin uses eccstrength bch16, so support
  switch to bch16 also.
- read the ecc type from the config in i2c eeprom, so
  no need to use a define.

$ ./tools/buildman/buildman arm -se
boards.cfg is up to date. Nothing to do.
Summary of current source for 561 boards (8 threads, 1 job per thread)
   arm:  +   Cubietruck omap3_logic omap3_overo gwventana
+arm-linux-gnueabi-ld.bfd: u-boot-spl section `.data' will not fit in region 
`.sram'
+arm-linux-gnueabi-ld.bfd: region `.sram' overflowed by 236 bytes
+make[2]: *** [spl/u-boot-spl] Error 1
+make[1]: *** [spl/u-boot-spl] Error 2
+make: *** [sub-make] Error 2
+arm-linux-gnueabi-ld.bfd: region `.sram' overflowed by 944 bytes
+arm-linux-gnueabi-ld.bfd: region `.sram' overflowed by 620 bytes
+common/spl/spl_ext.c: In function 'spl_load_image_ext_os':
+common/spl/spl_ext.c:125:20: error: 'CONFIG_SPL_FS_LOAD_ARGS_NAME' undeclared 
(first use in this function)
+common/spl/spl_ext.c:125:20: note: each undeclared identifier is reported only 
once for each function it appears in
+common/spl/spl_ext.c:139:4: error: 'CONFIG_SPL_FS_LOAD_KERNEL_NAME' undeclared 
(first use in this function)
+make[3]: *** [spl/common/spl/spl_ext.o] Error 1
+make[2]: *** [spl/common/spl] Error 2
w+common/spl/spl_ext.c:140:1: warning: control reaches end of non-void function 
[-Wreturn-type]
$

No new errors/warnings

- news for the v2 version:
  as Scott Wood posted a "mtd, nand sync with Linux v4.6"
  patchserie, I rebased this patchset to his series, so my
  patches are based on the patches:

  [U-Boot,1/7] mtd: nand: Remove jz4740 driver
  http://patchwork.ozlabs.org/patch/627922/
  [U-Boot,2/7] mtd: nand: Remove docg4 driver and palmtreo680 flashing tool
  http://patchwork.ozlabs.org/patch/627924/
  [U-Boot,3/7] mtd: nand: Remove nand_info_t typedef
  http://patchwork.ozlabs.org/patch/627923/
  [U-Boot,4/7] nand: Embed mtd_info in struct nand_chip
  http://patchwork.ozlabs.org/patch/627925/
  [U-Boot,5/7] mtd: nand: Add+use mtd_to/from_nand and 
nand_get/set_controller_data
  http://patchwork.ozlabs.org/patch/627926/
  [U-Boot,6/7] mtd: nand: Add page argument to write_page() etc.
  http://patchwork.ozlabs.org/patch/627927/
  [U-Boot,7/7] mtd: nand: Sync with Linux v4.6
  http://patchwork.ozlabs.org/patch/627928/

Last but not least, tbot results for the etamin module
(UBI/UBIFS and a lot of DFU tests)

xeidos.ddns.net/tests/test_db_auslesen.php#42
http://xeidos.ddns.net/tbot/id_42/html_log.html


Changes in v2:
- rebase to current mainline commit id:
  e4a94ce4ac77396b181663c0493c50bc2d5b9143
- add comments from Scott Wood:
  - correct spelling error "dettach" -> "detach"
  - use "o...@buserror.net" as email address for Scott
- rebase to current mainline commit id:
  e4a94ce4ac77396b181663c0493c50bc2d5b9143
- add comments from Scott Wood:
  - move c_mtd_name from file scope to local
  - use nand_info instead mtd_nand_list
  - use o...@buserror.net as email address for Scott
- rebase to current mainline commit id:
  e4a94ce4ac77396b181663c0493c50bc2d5b9143
  and the "mtd: nand Sync with Linux v4.6" patches:
  [U-Boot,1/7] mtd: nand: Remove jz4740 driver
  http://patchwork.ozlabs.org/patch/627922/
  [U-Boot,2/7] mtd: nand: Remove docg4 driver and palmtreo680 flashing tool
  http://patchwork.ozlabs.org/patch/627924/
  [U-Boot,3/7] mtd: nand: Remove nand_info_t typedef
  http://patchwork.ozlabs.org/patch/627923/
  [U-Boot,4/7] nand: Embed mtd_info in struct nand_chip
  http://patchwork.ozlabs.org/patch/627925/
  [U-Boot,5/7] mtd: nand: Add+use mtd_to/from_nand and 
nand_get/set_controller_data
  http://patchwork.ozlabs.org/patch/627926/
  [U-Boot,6/7] mtd: nand: Add page argument to write_page() etc.
  http://patchwork.ozlabs.org/patch/627927/
  [U-Boot,7/7] mtd: nand: Sync with Linux v4.6
  http://patchwork.ozlabs.org/patch/627928/
- rebase to current mainline commit id:
  e4a94ce4ac77396b181663c0493c50bc2d5b9143
- rebase to current mainline commit id:
  e4a94ce4ac77396b181663c0493c50bc2d5b9143
- rebase to current mainline commit id:
  e4a94ce4ac77396b181663c0493c50bc2d5b9143
  and the "mtd: nand Sync with Linux v4.6" patches:
  [U-Boot,1/7] mtd: nand: Remove jz4740 driver
  http://patchwork.ozlabs.org/patch/627922/
  [U-Boot,2/7] mtd: nand: Remove docg4 driver and palmtreo680 flashing tool
  http://patchwork.ozlabs.org/patch/627924/
  [U-Boot,3/7] mtd: nand: Remove nand_info_t typedef
  http://patchwork.ozlabs.org/patch/627923/
  [U-Boot,4/7] nand: Embed mtd_info in struct nand_chip
  http://patchwork.ozlabs.org/patch/627925/
  [U-Boot,5/7] mtd: nand: Add+use 

[U-Boot] [PATCH v2 1/7] siemens,am33x: add ubi fastmap support

[Heiko Schocher]

From: Samuel Egli 

From: Samuel Egli 

Signed-off-by: Heiko Schocher 

---

Changes in v2:
- rebase to current mainline commit id:
  e4a94ce4ac77396b181663c0493c50bc2d5b9143

 include/configs/siemens-am33x-common.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/siemens-am33x-common.h 
b/include/configs/siemens-am33x-common.h
index dfc928d..ae26dad 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -288,6 +288,8 @@
 #define CONFIG_LZO
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
+#define CONFIG_MTD_UBI_FASTMAP
+#define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT  1
 #endif
 
 /* Commen environment */
-- 
2.5.5

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[U-Boot] [PATCH 1/3] usb: ums: support multiple controllers using controller_index

[Rajat Srivastava]

From: Rajesh Bhagat 

Adds a new field in fsg_common namely controller_index to support
multiple controllers usb gadget support.

Signed-off-by: Rajat Srivastava 
Signed-off-by: Rajesh Bhagat 
---
 cmd/usb_mass_storage.c  |  2 +-
 drivers/usb/gadget/f_mass_storage.c | 10 +-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
index b05913a..1c955f8 100644
--- a/cmd/usb_mass_storage.c
+++ b/cmd/usb_mass_storage.c
@@ -214,7 +214,7 @@ int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag,
while (1) {
usb_gadget_handle_interrupts(controller_index);
 
-   rc = fsg_main_thread(NULL);
+   rc = fsg_main_thread(_index);
if (rc) {
/* Check I/O error */
if (rc == -EIO)
diff --git a/drivers/usb/gadget/f_mass_storage.c 
b/drivers/usb/gadget/f_mass_storage.c
index 1ecb92a..cc3e4af 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -362,6 +362,7 @@ struct fsg_common {
char inquiry_string[8 + 16 + 4 + 1];
 
struct kref ref;
+   unsigned int controller_index;
 };
 
 struct fsg_config {
@@ -691,7 +692,7 @@ static int sleep_thread(struct fsg_common *common)
k = 0;
}
 
-   usb_gadget_handle_interrupts(0);
+   usb_gadget_handle_interrupts(common->controller_index);
}
common->thread_wakeup_needed = 0;
return rc;
@@ -2406,6 +2407,11 @@ int fsg_main_thread(void *common_)
 {
int ret;
struct fsg_common   *common = the_fsg_common;
+
+   /* update the controller_index */
+   if (common_)
+   common->controller_index = *(unsigned int *)common_;
+
/* The main loop */
do {
if (exception_in_progress(common)) {
@@ -2476,6 +2482,7 @@ static struct fsg_common *fsg_common_init(struct 
fsg_common *common,
 
common->ops = NULL;
common->private_data = NULL;
+   common->controller_index = 0;
 
common->gadget = gadget;
common->ep0 = gadget->ep0;
@@ -2770,6 +2777,7 @@ int fsg_add(struct usb_configuration *c)
 
fsg_common->ops = NULL;
fsg_common->private_data = NULL;
+   fsg_common->controller_index = 0;
 
the_fsg_common = fsg_common;
 
-- 
1.9.1

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Re: [U-Boot] [PATCH 2/3] armv8/fsl-layerscape: add dwc3 gadget driver support

[Marek Vasut]

On 05/31/2016 01:32 PM, Rajat Srivastava wrote:
> From: Rajesh Bhagat 
> 
> Implements the dwc3 gadget driver support for LS1043
> platform, and performs below operations:
> 1. Enables snooping support for DWC3 controller.
> 2. Enables cache coherency in LS1043 platform.
> 
> Signed-off-by: Rajat Srivastava 
> Signed-off-by: Rajesh Bhagat 
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/soc.c| 87 
> +-
>  .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  6 ++
>  .../include/asm/arch-fsl-layerscape/sys_proto.h| 11 +++
>  drivers/usb/dwc3/core.c| 12 +++
>  4 files changed, 114 insertions(+), 2 deletions(-)
>  create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c

Don't mix platform code with driver code, split this patch.

> index 0fb5c7f..84b973d 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> @@ -17,6 +17,10 @@
>  #ifdef CONFIG_CHAIN_OF_TRUST
>  #include 
>  #endif
> +#include 
> +#include 
> +#include 
> +
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -318,9 +322,12 @@ void fsl_lsch2_early_init_f(void)
>  #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
>   out_be32(>qspi_cfg, SCFG_QSPI_CLKSEL);
>  #endif
> - /* Make SEC reads and writes snoopable */
> + /* Make SEC and USB reads and writes snoopable */
>   setbits_be32(>snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
> -  SCFG_SNPCNFGCR_SECWRSNP);
> +  SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
> +  SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
> +  SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
> +  SCFG_SNPCNFGCR_USB3WRSNP);
>  
>   /*
>* Enable snoop requests and DVM message requests for
> @@ -336,6 +343,82 @@ void fsl_lsch2_early_init_f(void)
>  }
>  #endif
>  
> +#ifdef CONFIG_USB_DWC3
> +
> +#if defined(CONFIG_LS1043A)
> +static struct dwc3_device dwc3_device_data0 = {
> + .maximum_speed = USB_SPEED_HIGH,
> + .base = CONFIG_SYS_FSL_XHCI_USB1_ADDR,
> + .dr_mode = USB_DR_MODE_PERIPHERAL,
> + .index = 0,
> +};
> +
> +static struct dwc3_device dwc3_device_data1 = {
> + .maximum_speed = USB_SPEED_HIGH,
> + .base = CONFIG_SYS_FSL_XHCI_USB2_ADDR,
> + .dr_mode = USB_DR_MODE_PERIPHERAL,
> + .index = 1,
> +};
> +
> +static struct dwc3_device dwc3_device_data2 = {
> + .maximum_speed = USB_SPEED_HIGH,
> + .base = CONFIG_SYS_FSL_XHCI_USB3_ADDR,
> + .dr_mode = USB_DR_MODE_PERIPHERAL,
> + .index = 2,
> +};
> +
> +int usb_gadget_handle_interrupts(int index)
> +{
> + dwc3_uboot_handle_interrupt(index);
> + return 0;
> +}
> +#endif
> +
> +int board_usb_init(int index, enum usb_init_type init)
> +{
> + switch (init) {
> + case USB_INIT_DEVICE:
> + switch (index) {
> +#if defined(CONFIG_LS1043A)
> + case 0:
> + dwc3_uboot_init(_device_data0);
> + break;
> +
> + case 1:
> + dwc3_uboot_init(_device_data1);
> + break;
> + case 2:
> + dwc3_uboot_init(_device_data2);
> + break;
> +#endif
> + default:
> + printf("Invalid Controller Index\n");
> + return -1;
> + }
> + break;
> + default:
> + break;
> + }
> + return 0;
> +}
> +
> +int board_usb_cleanup(int index, enum usb_init_type init)
> +{
> + switch (init) {
> + case USB_INIT_DEVICE:
> +#if defined(CONFIG_LS1043A)
> + dwc3_uboot_exit(index);
> +#endif
> + break;
> + default:
> + break;
> + }
> + return 0;
> +}
> +#endif
> +
> +
> +
>  #ifdef CONFIG_BOARD_LATE_INIT
>  int board_late_init(void)
>  {
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> index 57b99d4..13ba1a6 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> @@ -328,6 +328,12 @@ struct ccsr_gur {
>  
>  #define SCFG_SNPCNFGCR_SECRDSNP  0x8000
>  #define SCFG_SNPCNFGCR_SECWRSNP  0x4000
> +#define SCFG_SNPCNFGCR_USB1RDSNP 0x0020
> +#define SCFG_SNPCNFGCR_USB1WRSNP 0x0010
> +#define SCFG_SNPCNFGCR_USB2RDSNP 0x8000
> +#define SCFG_SNPCNFGCR_USB2WRSNP 0x0001
> +#define SCFG_SNPCNFGCR_USB3RDSNP 0x2000
> +#define SCFG_SNPCNFGCR_USB3WRSNP 0x4000
>  
>  /* Supplemental Configuration Unit */
>  struct ccsr_scfg {
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h 
> 

Re: [U-Boot] [PATCH 4/6] mips: ath79: Add support for ungating USB and ethernet on qca953x

[Marek Vasut]

On 05/31/2016 10:50 AM, Piotr Dymacz wrote:
> Hello,
> 
> 2016-05-31 2:51 GMT+02:00 Marek Vasut :
>> On 05/31/2016 02:35 AM, Wills Wang wrote:
> 
> [snip]
> 
>   +static int usb_reset_qca953x(void __iomem *reset_regs)
> +{
> +void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
> +  MAP_NOCACHE);
> +
> +clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
> +0xf00, 0x200);
>>
>> Do you know what these magic numbers mean ?
> 
> I can help here.
> 
> This register is common for (almost) all modern QC/A WiSOCs, with
> similar structure, at least for AR934x, QCA953x, QCA955x and QCA956x
> (please take a look at [1]).
> I have seen it (SDK, datasheets) under two different names:
> SWITCH_CLOCK_SPARE and SWITCH_CLOCK_CONTROL, on different addresses
> (offset +/- 1), depending on the SOC.
> 
> The bit field [8:11] is "USB_REFCLK_FREQ_SEL" and it's the same for
> all above SOCs. Value (dec) 2 is for 25 MHz, value 5 for 40 MHz.
> 
> I'm going to provide some patches for ath79 in future, which will make
> code more universal for all QC/A WiSOCs.

Oh, very cool, thanks!

-- 
Best regards,
Marek Vasut
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[U-Boot] [PATCH 2/3] armv8/fsl-layerscape: add dwc3 gadget driver support

[Rajat Srivastava]

From: Rajesh Bhagat 

Implements the dwc3 gadget driver support for LS1043
platform, and performs below operations:
1. Enables snooping support for DWC3 controller.
2. Enables cache coherency in LS1043 platform.

Signed-off-by: Rajat Srivastava 
Signed-off-by: Rajesh Bhagat 
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 87 +-
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  6 ++
 .../include/asm/arch-fsl-layerscape/sys_proto.h| 11 +++
 drivers/usb/dwc3/core.c| 12 +++
 4 files changed, 114 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 0fb5c7f..84b973d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -17,6 +17,10 @@
 #ifdef CONFIG_CHAIN_OF_TRUST
 #include 
 #endif
+#include 
+#include 
+#include 
+
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -318,9 +322,12 @@ void fsl_lsch2_early_init_f(void)
 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
out_be32(>qspi_cfg, SCFG_QSPI_CLKSEL);
 #endif
-   /* Make SEC reads and writes snoopable */
+   /* Make SEC and USB reads and writes snoopable */
setbits_be32(>snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
-SCFG_SNPCNFGCR_SECWRSNP);
+SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
+SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
+SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
+SCFG_SNPCNFGCR_USB3WRSNP);
 
/*
 * Enable snoop requests and DVM message requests for
@@ -336,6 +343,82 @@ void fsl_lsch2_early_init_f(void)
 }
 #endif
 
+#ifdef CONFIG_USB_DWC3
+
+#if defined(CONFIG_LS1043A)
+static struct dwc3_device dwc3_device_data0 = {
+   .maximum_speed = USB_SPEED_HIGH,
+   .base = CONFIG_SYS_FSL_XHCI_USB1_ADDR,
+   .dr_mode = USB_DR_MODE_PERIPHERAL,
+   .index = 0,
+};
+
+static struct dwc3_device dwc3_device_data1 = {
+   .maximum_speed = USB_SPEED_HIGH,
+   .base = CONFIG_SYS_FSL_XHCI_USB2_ADDR,
+   .dr_mode = USB_DR_MODE_PERIPHERAL,
+   .index = 1,
+};
+
+static struct dwc3_device dwc3_device_data2 = {
+   .maximum_speed = USB_SPEED_HIGH,
+   .base = CONFIG_SYS_FSL_XHCI_USB3_ADDR,
+   .dr_mode = USB_DR_MODE_PERIPHERAL,
+   .index = 2,
+};
+
+int usb_gadget_handle_interrupts(int index)
+{
+   dwc3_uboot_handle_interrupt(index);
+   return 0;
+}
+#endif
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+   switch (init) {
+   case USB_INIT_DEVICE:
+   switch (index) {
+#if defined(CONFIG_LS1043A)
+   case 0:
+   dwc3_uboot_init(_device_data0);
+   break;
+
+   case 1:
+   dwc3_uboot_init(_device_data1);
+   break;
+   case 2:
+   dwc3_uboot_init(_device_data2);
+   break;
+#endif
+   default:
+   printf("Invalid Controller Index\n");
+   return -1;
+   }
+   break;
+   default:
+   break;
+   }
+   return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+   switch (init) {
+   case USB_INIT_DEVICE:
+#if defined(CONFIG_LS1043A)
+   dwc3_uboot_exit(index);
+#endif
+   break;
+   default:
+   break;
+   }
+   return 0;
+}
+#endif
+
+
+
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 57b99d4..13ba1a6 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -328,6 +328,12 @@ struct ccsr_gur {
 
 #define SCFG_SNPCNFGCR_SECRDSNP0x8000
 #define SCFG_SNPCNFGCR_SECWRSNP0x4000
+#define SCFG_SNPCNFGCR_USB1RDSNP   0x0020
+#define SCFG_SNPCNFGCR_USB1WRSNP   0x0010
+#define SCFG_SNPCNFGCR_USB2RDSNP   0x8000
+#define SCFG_SNPCNFGCR_USB2WRSNP   0x0001
+#define SCFG_SNPCNFGCR_USB3RDSNP   0x2000
+#define SCFG_SNPCNFGCR_USB3WRSNP   0x4000
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h 
b/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
new file mode 100644
index 000..252c676
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef 

[U-Boot] [PATCH 0/3] armv8/fsl-layerscape: add dwc3 gadget driver support

[Rajat Srivastava]

Adds support for dwc3 gadget driver for ARM v8 platform of layerscape
series. Currently this patch has been tested for LS1043A. 

Rajat Srivastava (3):
  usb: ums: support multiple controllers using controller_index
  armv8/fsl-layerscape: add dwc3 gadget driver support
  armv8/fsl-layerscape: enable dwc3 gadget driver support

 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 87 +-
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  6 ++
 .../include/asm/arch-fsl-layerscape/sys_proto.h| 11 +++
 cmd/usb_mass_storage.c |  2 +-
 drivers/usb/dwc3/core.c| 12 +++
 drivers/usb/gadget/f_mass_storage.c| 10 ++-
 include/configs/ls1043aqds.h   | 15 
 7 files changed, 139 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h

-- 
1.9.1

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[U-Boot] [PATCH] Revert "image.h: Tighten up content using handy CONFIG_IS_ENABLED() macro."

[Masahiro Yamada]

This reverts commit 56adbb38727320375b2f695bd04600d766d8a1b3.

Since commit 56adbb387273 ("image.h: Tighten up content using handy
CONFIG_IS_ENABLED() macro."), I found my boards fail to boot Linux
because the commit changed the logic of macros it touched.  Now,
IMAGE_ENABLE_RAMDISK_HIGH and IMAGE_BOOT_GET_CMDLINE are 0 for all
the boards.

As you can see in include/linux/kconfig.h, CONFIG_IS_ENABLE() (and
IS_ENABLED() as well) can only take a macro that is either defined
as 1 or undefined.  This is met for boolean options defined in
Kconfig.  On the other hand, CONFIG_SYS_BOOT_RAMDISK_HIGH and
CONFIG_SYS_BOOT_GET_CMDLINE are defined without any value in
arch/*/include/asm/config.h .  This kind of clean-up is welcome,
but the options should be moved to Kconfig beforehand.

Moreover, CONFIG_IS_ENABLED(SPL_CRC32_SUPPORT) looks weird.
It should be either CONFIG_IS_ENABLED(CRC32_SUPPORT) or
IS_ENABLED(CONFIG_SPL_CRC32_SUPPORT).  But, I see no define for
CONFIG_SPL_CRC32_SUPPORT anywhere.  Likewise for the other three.

The logic of IMAGE_OF_BOARD_SETUP and IMAGE_OF_SYSTEM_SETUP were
also changed for SPL.  This can be a problem for boards defining
CONFIG_SPL_OF_LIBFDT.  I guess it should have been changed to
IS_ENABLED(CONFIG_OF_BOARD_SETUP).

In the first place, if we replace the references in C code,
the macros IMAGE_* will go away.

  if (IS_ENABLED(CONFIG_OF_BOARD_SETUP) {
  ...
  }

Signed-off-by: Masahiro Yamada 
---

 include/image.h | 69 +++--
 1 file changed, 57 insertions(+), 12 deletions(-)

diff --git a/include/image.h b/include/image.h
index 80a4454..a8f6bd1 100644
--- a/include/image.h
+++ b/include/image.h
@@ -52,15 +52,19 @@ struct lmb;
 #include 
 #include 
 #include 
-# ifdef CONFIG_FIT_DISABLE_SHA256
-#  undef CONFIG_SHA256
-#  undef IMAGE_ENABLE_SHA256
-# endif
 # ifdef CONFIG_SPL_BUILD
-#  define IMAGE_ENABLE_CRC32   CONFIG_IS_ENABLED(SPL_CRC32_SUPPORT)
-#  define IMAGE_ENABLE_MD5 CONFIG_IS_ENABLED(SPL_MD5_SUPPORT)
-#  define IMAGE_ENABLE_SHA1CONFIG_IS_ENABLED(SPL_SHA1_SUPPORT)
-#  define IMAGE_ENABLE_SHA256  CONFIG_IS_ENABLED(SPL_SHA256_SUPPORT)
+#  ifdef CONFIG_SPL_CRC32_SUPPORT
+#   define IMAGE_ENABLE_CRC32  1
+#  endif
+#  ifdef CONFIG_SPL_MD5_SUPPORT
+#   define IMAGE_ENABLE_MD51
+#  endif
+#  ifdef CONFIG_SPL_SHA1_SUPPORT
+#   define IMAGE_ENABLE_SHA1   1
+#  endif
+#  ifdef CONFIG_SPL_SHA256_SUPPORT
+#   define IMAGE_ENABLE_SHA256 1
+#  endif
 # else
 #  define CONFIG_CRC32 /* FIT images need CRC32 support */
 #  define CONFIG_MD5   /* and MD5 */
@@ -71,12 +75,53 @@ struct lmb;
 #  define IMAGE_ENABLE_SHA11
 #  define IMAGE_ENABLE_SHA256  1
 # endif
+
+#ifdef CONFIG_FIT_DISABLE_SHA256
+#undef CONFIG_SHA256
+#undef IMAGE_ENABLE_SHA256
+#endif
+
+#ifndef IMAGE_ENABLE_CRC32
+#define IMAGE_ENABLE_CRC32 0
+#endif
+
+#ifndef IMAGE_ENABLE_MD5
+#define IMAGE_ENABLE_MD5   0
+#endif
+
+#ifndef IMAGE_ENABLE_SHA1
+#define IMAGE_ENABLE_SHA1  0
+#endif
+
+#ifndef IMAGE_ENABLE_SHA256
+#define IMAGE_ENABLE_SHA2560
+#endif
+
 #endif /* IMAGE_ENABLE_FIT */
 
-#define IMAGE_ENABLE_RAMDISK_HIGH  CONFIG_IS_ENABLED(SYS_BOOT_RAMDISK_HIGH)
-#define IMAGE_BOOT_GET_CMDLINE CONFIG_IS_ENABLED(SYS_BOOT_GET_CMDLINE)
-#define IMAGE_OF_BOARD_SETUP   CONFIG_IS_ENABLED(OF_BOARD_SETUP)
-#define IMAGE_OF_SYSTEM_SETUP  CONFIG_IS_ENABLED(OF_SYSTEM_SETUP)
+#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
+# define IMAGE_ENABLE_RAMDISK_HIGH 1
+#else
+# define IMAGE_ENABLE_RAMDISK_HIGH 0
+#endif
+
+#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
+# define IMAGE_BOOT_GET_CMDLINE1
+#else
+# define IMAGE_BOOT_GET_CMDLINE0
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+# define IMAGE_OF_BOARD_SETUP  1
+#else
+# define IMAGE_OF_BOARD_SETUP  0
+#endif
+
+#ifdef CONFIG_OF_SYSTEM_SETUP
+# define IMAGE_OF_SYSTEM_SETUP 1
+#else
+# define IMAGE_OF_SYSTEM_SETUP 0
+#endif
 
 /*
  * Operating System Codes
-- 
1.9.1

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[U-Boot] [PATCH 3/3] armv8/fsl-layerscape: enable dwc3 gadget driver support

[Rajat Srivastava]

From: Rajesh Bhagat 

Enables dwc3 gadget driver support on LS1043QDS platform.

Signed-off-by: Rajat Srivastava 
Signed-off-by: Rajesh Bhagat 
---
 include/configs/ls1043aqds.h | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index af1f73d..8c99641 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -394,6 +394,21 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_USB_MAX_CONTROLLER_COUNT3
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
 #define CONFIG_USB_STORAGE
+
+#define CONFIG_USB_DWC3
+#define CONFIG_USB_DWC3_GADGET
+
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
+#define CONFIG_G_DNL_VENDOR_NUM 0x0471
+#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
+#define CONFIG_USB_GADGET_DUALSPEED
+
+/* USB Gadget ums command */
+#define CONFIG_CMD_USB_MASS_STORAGE
 #endif
 
 /*
-- 
1.9.1

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Re: [U-Boot] [RFC PATCH 1/5] spl: dfu: add dfu support in SPL

[B, Ravi]

Hi Lukasz

>> >> Since DFU is tighly coupled to u-boot infrastructure , the size 
>> >> will increase due to multiple dependencies to compile u-boot DFU 
>> >> source in SPL. Let me re-think on possibility and come back.
>> 
>> >If you would need any assistance, please let me know (I don't have 
>> >dra7x, but I do have Beagle Bone Black).
>> 
>> The current implementation of dfu (drivers/dfu/dfu.c) relies on 
>> environment modules (getenv,setenv), and hash algo methods. The 
>> mandatory modules for DFU includes USB(dwc3/musb), gadget, 
>> drivers/dfu, hash, environ modules. Added to this mmc/sf support, with 
>> filesystem fat/ext4 would definitely increase the size.
>> 

>I've double checked BBB SPL setup:

>- SPL is the MLO (./common/spl/)
>- Its size shall be less than 128 KiB
>- It can reside on eMMC (fat partition, raw LBA offset), NAND or be sent
 > via serial port.

>I've build the am335x_boneblack_defconfig and MLO size is 75 KiB.

>Please correct me, but it seems that the SPL-DFU support adds around
>30 KiB to SPL binary size.

30KB+ is just approx size optimitzed for DFU-SF (qspi) support only, without 
fat/ext4, mmc support. 
But all device support may increase size.

>If yes, then even BBB's SPL can support DFU without any problems (105KiB < 128 
>KiB).

You mean BBB must have 128KB ? Can you confirm.
If BBB is support SPI boot, flashing MLO/U-boot to SPI-flash through SPL-DFU/SF 
would be sufficient right ?
Further dfu support for mmc/sd, ram available from u-boot.

>>I'm also wondering if we could even shrink the code more with reusing or 
>>extending the code at ./common/spl/spl_{ext|fat|mmc|sf, etc}.c (in this way 
>>we avoid adding the whole fat, ext, sf "commands").

Yes we must see this option. I will check on this.

>>For more aggressive size reduction we could for example disable hash algo 
>>checking and add ./common/spl/spl_dfu.c file with ordinary functions and rid 
>>of the need to add the whole dfu command.

>> I have tried minimal subset adding DFU-SF serial flash support alone 
>> in SPL, this itself increases SPL size to 30K+ (SPL size approx.
>> 107KB for dra7x). 
>> 
>> But beagle bone IRAM would be around 64KB right? Definetly this will 
>> not fit.
>> 
>> Can we enable this feature for platform with minimum SRAM size of 
>> 160KB. So SPL-DFU cannot be supported for platform less than 160KB 
>> (like am335x).

>I will ask on ML if there is any other interested party in SPL-DFU support 
>(and what are their limitations of SPL code size).

OK.

Regards
Ravi 
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Re: [U-Boot] [PATCH] malloc: Remove control-L in malloc.h

[Måns Rullgård]

Marek Vasut  writes:

> On 05/30/2016 10:37 PM, Marek Vasut wrote:
>> On 05/30/2016 10:15 PM, Wolfgang Denk wrote:
>>> Dear Marek,
>>>
>>> In message <1464621732-7617-1-git-send-email-ma...@denx.de> you wrote:
 Remove what must've been a typo.

 Signed-off-by: Marek Vasut 
 Cc: Tom Rini 
 Cc: Simon Glass 
 ---
  include/malloc.h | 1 -
  1 file changed, 1 deletion(-)

 diff --git a/include/malloc.h b/include/malloc.h
 index 8175c75..e065473 100644
 --- a/include/malloc.h
 +++ b/include/malloc.h
 @@ -215,7 +215,6 @@
  
  */
  
 -
  #ifndef __MALLOC_H__
  #define __MALLOC_H__
>>>
>>> This is most likely NOT a typo, but an intentional page break (yes,
>>> there was a time when people used to _print_ source code on dead
>>> wood).  And I bet if comes from the original imported dlmalloc code,
>>> so please check twice befoire introducing an unneeded difference.
>> 
>> Urgh, ok, feel free to drop this patch, I don't really care.
>
> ...about this patch
>
> I didn't expect to meet control-L in any files, that's new (old).

Kids these days...

-- 
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Re: [U-Boot] [RFC PATCH 1/5] spl: dfu: add dfu support in SPL

[Lukasz Majewski]

Hi Ravi,

> Hi Lucasz
> 
> Thanks for active support.
> 
> >> >> > 
> >> >> > - Would it be hard to add SPL-DFU support also to BeagleBone
> >> >> >  Black(am335x) (BBB) board? I'm asking since BBB is far more 
> >> >> > pervasive than dra7x (and I might be able to cover SPL-DFU
> >> >> > easily with our new ptest (DFU) test suite).
> >> >> >   
> >> >> 
> >> >> It's possible to extend this for other platform, but SPL size
> >> >> would be 152k.
> >> 
> >> >That was my point to reduce the size as much as possible and only 
> >> >provide minimal functionality to fit the bill.
> >> 
> >> Since DFU is tighly coupled to u-boot infrastructure , the size
> >> will increase due to multiple dependencies to compile u-boot DFU
> >> source in SPL. Let me re-think on possibility and come back.
> 
> >If you would need any assistance, please let me know (I don't have
> >dra7x, but I do have Beagle Bone Black).
> 
> The current implementation of dfu (drivers/dfu/dfu.c) relies on
> environment modules (getenv,setenv), and hash algo methods. The
> mandatory modules for DFU includes USB(dwc3/musb), gadget,
> drivers/dfu, hash, environ modules. Added to this mmc/sf support,
> with filesystem fat/ext4 would definitely increase the size.
> 

I've double checked BBB SPL setup:

- SPL is the MLO (./common/spl/)
- Its size shall be less than 128 KiB
- It can reside on eMMC (fat partition, raw LBA offset), NAND or be sent
  via serial port.

I've build the am335x_boneblack_defconfig and MLO size is 75 KiB.

Please correct me, but it seems that the SPL-DFU support adds around
30 KiB to SPL binary size.

If yes, then even BBB's SPL can support DFU without any problems (105KiB
< 128 KiB).

I'm also wondering if we could even shrink the code more with
reusing or extending the code at ./common/spl/spl_{ext|fat|mmc|sf,
etc}.c (in this way we avoid adding the whole fat, ext, sf "commands").

For more aggressive size reduction we could for example disable hash
algo checking and add ./common/spl/spl_dfu.c file with ordinary
functions and rid of the need to add the whole dfu command.


> I have tried minimal subset adding DFU-SF serial flash support alone
> in SPL, this itself increases SPL size to 30K+ (SPL size approx.
> 107KB for dra7x). 
> 
> But beagle bone IRAM would be around 64KB right? Definetly this will
> not fit.
> 
> Can we enable this feature for platform with minimum SRAM size of
> 160KB. So SPL-DFU cannot be supported for platform less than 160KB
> (like am335x).

I will ask on ML if there is any other interested party in SPL-DFU
support (and what are their limitations of SPL code size).

> 
> Any suggestion ?
> 
> Regards
> Ravi 
> 



-- 
Best regards,

Lukasz Majewski

Samsung R Institute Poland (SRPOL) | Linux Platform Group
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Re: [U-Boot] [PATCH 6/6] mips: ath79: ap143: Reset ethernet on boot

[Daniel Schwierzeck]

Am 30.05.2016 um 16:54 schrieb Wills Wang:
> This patch reset the ethernet controller for ap143 board
> 
> Signed-off-by: Wills Wang 
> ---
> 
>  board/qca/ap143/ap143.c | 2 ++
>  1 file changed, 2 insertions(+)
> 

applied to u-boot-mips, thanks!

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Re: [U-Boot] [PATCH 4/6] mips: ath79: Add support for ungating USB and ethernet on qca953x

[Daniel Schwierzeck]

Am 30.05.2016 um 16:54 schrieb Wills Wang:
> Add code to ungate USB and ethernet controller on qca953x
> 
> Signed-off-by: Wills Wang 
> ---
> 
>  arch/mips/mach-ath79/reset.c | 50 
> 
>  1 file changed, 50 insertions(+)

applied to u-boot-mips, thanks!

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Re: [U-Boot] [PATCH 5/6] mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro define

[Daniel Schwierzeck]

Am 30.05.2016 um 16:54 schrieb Wills Wang:
> Add AR933X_PLL_SWITCH_CLOCK_CONTROL_REG define for ar933x chip.
> 
> Signed-off-by: Wills Wang 
> ---
> 
>  arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1 +
>  arch/mips/mach-ath79/reset.c| 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 

applied to u-boot-mips, thanks!

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Re: [U-Boot] [PATCH 3/6] mips: ath79: Use 8MB flash profile for mtd partition by default

[Daniel Schwierzeck]

Am 30.05.2016 um 16:54 schrieb Wills Wang:
> Change bootm flash address and mtd partition table for 8MB flash profile.
> 
> Signed-off-by: Wills Wang 
> ---
> 
>  include/configs/ap121.h | 4 ++--
>  include/configs/ap143.h | 6 +++---
>  2 files changed, 5 insertions(+), 5 deletions(-)
> 

applied to u-boot-mips, thanks!

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Re: [U-Boot] [PATCH 2/6] mips: ath79: ap121: Enable ethernet

[Daniel Schwierzeck]

Am 30.05.2016 um 16:54 schrieb Wills Wang:
> This patch enable network function for ap121 board.
> 
> Signed-off-by: Wills Wang 
> Acked-by: Marek Vasut 
> ---
> 
>  arch/mips/dts/ap121.dts   | 5 +
>  arch/mips/dts/ar933x.dtsi | 4 ++--
>  board/qca/ap121/ap121.c   | 2 ++
>  configs/ap121_defconfig   | 9 +++--
>  4 files changed, 16 insertions(+), 4 deletions(-)

applied to u-boot-mips, thanks!

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Re: [U-Boot] [PATCH 1/6] mips: ath79: Rename get_bootstrap into ath79_get_bootstrap

[Daniel Schwierzeck]

Am 30.05.2016 um 16:54 schrieb Wills Wang:
> Add a platform prefix for function name in order to make more readable,
> and move it into ath79.h
> 
> Signed-off-by: Wills Wang 
> Acked-by: Marek Vasut 
> ---
> 
>  arch/mips/mach-ath79/ar933x/clk.c |  4 ++--
>  arch/mips/mach-ath79/ar933x/ddr.c |  4 ++--
>  arch/mips/mach-ath79/ar934x/clk.c |  6 +++---
>  arch/mips/mach-ath79/ar934x/ddr.c |  4 ++--
>  arch/mips/mach-ath79/include/mach/ath79.h |  1 +
>  arch/mips/mach-ath79/include/mach/reset.h | 14 --
>  arch/mips/mach-ath79/qca953x/clk.c|  4 ++--
>  arch/mips/mach-ath79/qca953x/ddr.c|  4 ++--
>  arch/mips/mach-ath79/reset.c  |  2 +-
>  9 files changed, 15 insertions(+), 28 deletions(-)
>  delete mode 100644 arch/mips/mach-ath79/include/mach/reset.h
> 

applied to u-boot-mips, thanks!

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