[U-Boot] [PATCH 23/97] powerpc: MPC8569: Remove macro CONFIG_MPC8569

[York Sun]

Replace CONFIG_MPC8569 with ARCH_MPC8569 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun 
---

 arch/powerpc/cpu/mpc85xx/Kconfig  | 4 
 arch/powerpc/cpu/mpc85xx/Makefile | 2 +-
 arch/powerpc/cpu/mpc85xx/speed.c  | 2 +-
 arch/powerpc/cpu/mpc85xx/start.S  | 4 ++--
 arch/powerpc/include/asm/config_mpc85xx.h | 2 +-
 arch/powerpc/include/asm/immap_85xx.h | 4 ++--
 include/configs/MPC8569MDS.h  | 1 -
 scripts/config_whitelist.txt  | 1 -
 8 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 9545793..b58ccee 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -88,6 +88,7 @@ config TARGET_MPC8568MDS
 
 config TARGET_MPC8569MDS
bool "Support MPC8569MDS"
+   select ARCH_MPC8569
 
 config TARGET_MPC8572DS
bool "Support MPC8572DS"
@@ -219,6 +220,9 @@ config ARCH_MPC8560
 config ARCH_MPC8568
bool
 
+config ARCH_MPC8569
+   bool
+
 source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile 
b/arch/powerpc/cpu/mpc85xx/Makefile
index 390eede..9df1434 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -70,7 +70,7 @@ obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o
 obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
 obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
 obj-$(CONFIG_ARCH_MPC8568) += mpc8568_serdes.o
-obj-$(CONFIG_MPC8569) += mpc8569_serdes.o
+obj-$(CONFIG_ARCH_MPC8569) += mpc8569_serdes.o
 obj-$(CONFIG_MPC8572) += mpc8572_serdes.o
 obj-$(CONFIG_P1010)+= p1010_serdes.o
 obj-$(CONFIG_P1011)+= p1021_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index a7f43b6..3ac3580 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -707,7 +707,7 @@ int get_clocks (void)
 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
gd->arch.sdhc_clk = sys_info.freq_sdhc / 2;
 #else
-#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
+#if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_P1010) ||\
defined(CONFIG_P1014)
gd->arch.sdhc_clk = gd->bus_clk;
 #else
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index c3e1234..5f8881d 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -345,7 +345,7 @@ l2_disabled:
mtspr   DBCR0,r0
 #endif
 
-#ifdef CONFIG_MPC8569
+#ifdef CONFIG_ARCH_MPC8569
 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
 
@@ -376,7 +376,7 @@ l2_disabled:
tlbivax 0,r4
isync
 
-#endif /* CONFIG_MPC8569 */
+#endif /* CONFIG_ARCH_MPC8569 */
 
 /*
  * Search for the TLB that covers the code we're executing, and shrink it
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index c38d983..c162c9d 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -113,7 +113,7 @@
 #define CONFIG_SYS_FSL_RMU
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM   2
 
-#elif defined(CONFIG_MPC8569)
+#elif defined(CONFIG_ARCH_MPC8569)
 #define CONFIG_MAX_CPUS1
 #define CONFIG_SYS_FSL_NUM_LAWS10
 #define CONFIG_SYS_FSL_SEC_COMPAT  2
diff --git a/arch/powerpc/include/asm/immap_85xx.h 
b/arch/powerpc/include/asm/immap_85xx.h
index ec4c837..123dcad 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2210,7 +2210,7 @@ typedef struct ccsr_gur {
u32 gpiocr; /* GPIO control */
 #endif
u8  res3[12];
-#if defined(CONFIG_MPC8569)
+#if defined(CONFIG_ARCH_MPC8569)
u32 plppar1;/* Platform port pin assignment 1 */
u32 plppar2;/* Platform port pin assignment 2 */
u32 plpdir1;/* Platform port pin direction 1 */
@@ -2484,7 +2484,7 @@ typedef struct ccsr_gur {
u32 svr;/* System version */
u8  res10[8];
u32 rstcr;  /* Reset control */
-#if defined(CONFIG_ARCH_MPC8568) || defined(CONFIG_MPC8569)
+#if defined(CONFIG_ARCH_MPC8568) || defined(CONFIG_ARCH_MPC8569)
u8  res11a[76];
par_io_t qe_par_io[7];
u8  res11b[1600];
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index a2ec52b..2da630c 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -13,7 +13,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE   1   /* BOOKE */
 #define CONFIG_E5001   /* BOOKE e500 family */
-#define CONFIG_MPC8569 1   /* MPC8569 specific */
 #define CONFIG_MPC8569MDS  

[U-Boot] [PATCH 28/97] powerpc: P1010: Remove macro CONFIG_P1010

[York Sun]

Replace CONFIG_P1010 with ARCH_P1010 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun 
---

 arch/powerpc/cpu/mpc85xx/Kconfig  | 4 
 arch/powerpc/cpu/mpc85xx/Makefile | 2 +-
 arch/powerpc/cpu/mpc85xx/speed.c  | 2 +-
 arch/powerpc/include/asm/config_mpc85xx.h | 2 +-
 arch/powerpc/include/asm/immap_85xx.h | 8 
 include/configs/P1010RDB.h| 1 -
 scripts/config_whitelist.txt  | 1 -
 7 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index f4d9f9d..9b6dd34 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -96,6 +96,7 @@ config TARGET_MPC8572DS
 
 config TARGET_P1010RDB
bool "Support P1010RDB"
+   select ARCH_P1010
select SUPPORT_SPL
select SUPPORT_TPL
 
@@ -228,6 +229,9 @@ config ARCH_MPC8569
 config ARCH_MPC8572
bool
 
+config ARCH_P1010
+   bool
+
 source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile 
b/arch/powerpc/cpu/mpc85xx/Makefile
index e3f7dc8..de42b65 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -72,7 +72,7 @@ obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
 obj-$(CONFIG_ARCH_MPC8568) += mpc8568_serdes.o
 obj-$(CONFIG_ARCH_MPC8569) += mpc8569_serdes.o
 obj-$(CONFIG_ARCH_MPC8572) += mpc8572_serdes.o
-obj-$(CONFIG_P1010)+= p1010_serdes.o
+obj-$(CONFIG_ARCH_P1010)   += p1010_serdes.o
 obj-$(CONFIG_P1011)+= p1021_serdes.o
 obj-$(CONFIG_P1012)+= p1021_serdes.o
 obj-$(CONFIG_P1013)+= p1022_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 3ac3580..c20bc9d 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -707,7 +707,7 @@ int get_clocks (void)
 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
gd->arch.sdhc_clk = sys_info.freq_sdhc / 2;
 #else
-#if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_P1010) ||\
+#if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010) ||\
defined(CONFIG_P1014)
gd->arch.sdhc_clk = gd->bus_clk;
 #else
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 7d81dfc..adad3d3 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -140,7 +140,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
-#elif defined(CONFIG_P1010)
+#elif defined(CONFIG_ARCH_P1010)
 #define CONFIG_MAX_CPUS1
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_SYS_FSL_NUM_LAWS12
diff --git a/arch/powerpc/include/asm/immap_85xx.h 
b/arch/powerpc/include/asm/immap_85xx.h
index 4aeccbf..0cd90d1 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2169,7 +2169,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR_IO_SEL0x0060
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT  21
 #else
-#if defined(CONFIG_P1010)
+#if defined(CONFIG_ARCH_P1010)
 #define MPC85xx_PORDEVSR_IO_SEL0x0060
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT  21
 #elif defined(CONFIG_ARCH_BSC9132)
@@ -2181,7 +2181,7 @@ typedef struct ccsr_gur {
 #else
 #define MPC85xx_PORDEVSR_IO_SEL0x0078
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT  19
-#endif /* if defined(CONFIG_P1010) */
+#endif /* if defined(CONFIG_ARCH_P1010) */
 #endif
 #define MPC85xx_PORDEVSR_PCI2_ARB  0x0004
 #define MPC85xx_PORDEVSR_PCI1_ARB  0x0002
@@ -,7 +,7 @@ typedef struct ccsr_gur {
u32 gpindr; /* General-purpose input data */
u8  res5[12];
u32 pmuxcr; /* Alt. function signal multiplex control */
-#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
+#if defined(CONFIG_ARCH_P1010) || defined(CONFIG_P1014)
 #define MPC85xx_PMUXCR_TSEC1_0_15880x4000
 #define MPC85xx_PMUXCR_TSEC1_0_RES 0xC000
 #define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG   0x1000
@@ -2350,7 +2350,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR_SPI_GPIO0x0100
 #endif
u32 pmuxcr2;/* Alt. function signal multiplex control 2 */
-#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
+#if defined(CONFIG_ARCH_P1010) || defined(CONFIG_P1014)
 #define MPC85xx_PMUXCR2_UART_GPIO  0x4000
 #define MPC85xx_PMUXCR2_UART_TDM   0x8000
 #define MPC85xx_PMUXCR2_UART_RES   0xC000
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index c45b091..e17de90 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -11,7 +11,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_P1010
 #define 

[U-Boot] [PATCH 27/97] powerpc: xpedite: Remove macro CONFIG_XPEDITE5370

[York Sun]

This macro is no longer used.

Signed-off-by: York Sun 
---

 include/configs/xpedite537x.h | 1 -
 scripts/config_whitelist.txt  | 1 -
 2 files changed, 2 deletions(-)

diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index 61ee576..a6bdffc 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -16,7 +16,6 @@
  */
 #define CONFIG_BOOKE   1   /* BOOKE */
 #define CONFIG_E5001   /* BOOKE e500 family */
-#define CONFIG_XPEDITE5370 1
 #define CONFIG_SYS_BOARD_NAME  "XPedite5370"
 #define CONFIG_SYS_FORM_3U_VPX 1
 #define CONFIG_BOARD_EARLY_INIT_R  /* Call board_pre_init */
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index db34894..0dd5a7b 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -8292,7 +8292,6 @@ CONFIG_XILINX_TB_WATCHDOG
 CONFIG_XPEDITE1000
 CONFIG_XPEDITE5140
 CONFIG_XPEDITE5200
-CONFIG_XPEDITE5370
 CONFIG_XPEDITE550X
 CONFIG_XR16L2751
 CONFIG_XSENGINE
-- 
2.7.4

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[U-Boot] [PATCH 24/97] powerpc: MPC8569MDS: Remove macro CONFIG_MPC8569MDS

[York Sun]

Use CONFIG_TARGET_MPC8569MDS instead.

Signed-off-by: York Sun 
---

 board/freescale/common/pq-mds-pib.c | 2 +-
 include/configs/MPC8569MDS.h| 1 -
 scripts/config_whitelist.txt| 1 -
 3 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/board/freescale/common/pq-mds-pib.c 
b/board/freescale/common/pq-mds-pib.c
index 1eb3786..d152a78 100644
--- a/board/freescale/common/pq-mds-pib.c
+++ b/board/freescale/common/pq-mds-pib.c
@@ -63,7 +63,7 @@ int pib_init(void)
 #endif
 
 #if defined(CONFIG_PQ_MDS_PIB_ATM)
-#if defined(CONFIG_MPC8569MDS)
+#if defined(CONFIG_TARGET_MPC8569MDS)
val8 = 0;
i2c_write(0x20, 0x6, 1, , 1);
i2c_write(0x20, 0x7, 1, , 1);
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 2da630c..91f0104 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -13,7 +13,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE   1   /* BOOKE */
 #define CONFIG_E5001   /* BOOKE e500 family */
-#define CONFIG_MPC8569MDS  1   /* MPC8569MDS board specific */
 
 #define CONFIG_FSL_ELBC1   /* Has Enhance localbus 
controller */
 
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index fdd9ce2..ab26d67 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -3141,7 +3141,6 @@ CONFIG_MPC83XX_GPIO_1_INIT_VALUE
 CONFIG_MPC83XX_PCI2
 CONFIG_MPC850
 CONFIG_MPC855
-CONFIG_MPC8569MDS
 CONFIG_MPC857
 CONFIG_MPC8572
 CONFIG_MPC8572DS
-- 
2.7.4

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[U-Boot] [PATCH 17/97] powerpc: MPC8555: Remove macro CONFIG_MPC8555

[York Sun]

Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun 
---

 arch/powerpc/cpu/mpc85xx/Kconfig  | 4 
 arch/powerpc/cpu/mpc85xx/cpu.c| 2 +-
 arch/powerpc/cpu/mpc85xx/speed.c  | 4 ++--
 arch/powerpc/include/asm/config_mpc85xx.h | 2 +-
 arch/powerpc/include/asm/cpm_85xx.h   | 2 +-
 arch/powerpc/include/asm/fsl_lbc.h| 2 +-
 arch/powerpc/include/asm/immap_85xx.h | 2 +-
 drivers/ddr/fsl/ctrl_regs.c   | 2 +-
 drivers/ddr/fsl/mpc85xx_ddr_gen1.c| 2 +-
 drivers/input/keyboard.c  | 2 +-
 include/configs/MPC8555CDS.h  | 1 -
 include/keyboard.h| 2 +-
 scripts/config_whitelist.txt  | 1 -
 13 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 8b08ee2..c58f76f 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -76,6 +76,7 @@ config TARGET_MPC8548CDS
 
 config TARGET_MPC8555CDS
bool "Support MPC8555CDS"
+   select ARCH_MPC8555
 
 config TARGET_MPC8560ADS
bool "Support MPC8560ADS"
@@ -207,6 +208,9 @@ config ARCH_MPC8544
 config ARCH_MPC8548
bool
 
+config ARCH_MPC8555
+   bool
+
 source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index c563744..3e6f8f3 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -294,7 +294,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
 {
 /* Everything after the first generation of PQ3 parts has RSTCR */
 #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
-defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
+   defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_MPC8560)
unsigned long val, msr;
 
/*
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index bd810d7..93c7193 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -626,7 +626,7 @@ void get_sys_info(sys_info_t *sys_info)
 */
lcrr_div *= 4;
 #elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \
-!defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
+   !defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_MPC8560)
/*
 * Yes, the entire PQ38 family use the same
 * bit-representation for twice the clock divider values.
@@ -682,7 +682,7 @@ int get_clocks (void)
 * AN2919.
 */
 #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
-   defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
+   defined(CONFIG_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \
defined(CONFIG_P1022)
gd->arch.i2c1_clk = sys_info.freq_systembus;
 #elif defined(CONFIG_ARCH_MPC8544)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index f16e32e..4e38d23 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -85,7 +85,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
 
-#elif defined(CONFIG_MPC8555)
+#elif defined(CONFIG_ARCH_MPC8555)
 #define CONFIG_MAX_CPUS1
 #define CONFIG_SYS_FSL_NUM_LAWS8
 #define CONFIG_SYS_FSL_DDRC_GEN1
diff --git a/arch/powerpc/include/asm/cpm_85xx.h 
b/arch/powerpc/include/asm/cpm_85xx.h
index e89e2f0..b46e20e 100644
--- a/arch/powerpc/include/asm/cpm_85xx.h
+++ b/arch/powerpc/include/asm/cpm_85xx.h
@@ -77,7 +77,7 @@
  */
 #define CPM_DATAONLY_BASE  ((uint)128)
 #define CPM_DP_NOSPACE ((uint)0x7FFF)
-#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_MPC8555)
+#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
 #define CPM_FCC_SPECIAL_BASE   ((uint)0x9000)
 #define CPM_DATAONLY_SIZE  ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
 #else  /* MPC8540, MPC8560 */
diff --git a/arch/powerpc/include/asm/fsl_lbc.h 
b/arch/powerpc/include/asm/fsl_lbc.h
index c7805e9..ff9b2d9 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -326,7 +326,7 @@ void lbc_sdram_init(void);
 #define LCRR_CLKDIV0x001F
 #define LCRR_CLKDIV_SHIFT  0
 #if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \
-   defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_MPC8555) || \
+   defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) || \
defined(CONFIG_MPC8560)
 #define LCRR_CLKDIV_2  0x0002
 #define LCRR_CLKDIV_4  0x0004
diff --git a/arch/powerpc/include/asm/immap_85xx.h 

[U-Boot] [PATCH 18/97] powerpc: MPC8555CDS: Remove macro CONFIG_MPC8555CDS

[York Sun]

Use CONFIG_TARGET_MPC8555CDS instead.

Signed-off-by: York Sun 
---

 arch/powerpc/cpu/mpc85xx/pci.c  | 2 +-
 board/freescale/common/Makefile | 2 +-
 include/configs/MPC8555CDS.h| 1 -
 scripts/config_whitelist.txt| 1 -
 4 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/pci.c b/arch/powerpc/cpu/mpc85xx/pci.c
index bf003a7..538729f 100644
--- a/arch/powerpc/cpu/mpc85xx/pci.c
+++ b/arch/powerpc/cpu/mpc85xx/pci.c
@@ -120,7 +120,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
 
pci_register_hose(hose);
 
-#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_TARGET_MPC8541CDS)
+#if defined(CONFIG_TARGET_MPC8555CDS) || defined(CONFIG_TARGET_MPC8541CDS)
/*
 * This is a SW workaround for an apparent HW problem
 * in the PCI controller on the MPC8/41 CDS boards.
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index e01df42..06ce311 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -47,7 +47,7 @@ obj-$(CONFIG_FSL_DCU_SII9022A)+= dcu_sii9022a.o
 
 obj-$(CONFIG_TARGET_MPC8541CDS)+= cds_pci_ft.o
 obj-$(CONFIG_TARGET_MPC8548CDS)+= cds_pci_ft.o
-obj-$(CONFIG_MPC8555CDS)   += cds_pci_ft.o
+obj-$(CONFIG_TARGET_MPC8555CDS)+= cds_pci_ft.o
 
 obj-$(CONFIG_TARGET_MPC8536DS) += ics307_clk.o
 obj-$(CONFIG_MPC8572DS)+= ics307_clk.o
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index d0498c6..3cf8d97 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -17,7 +17,6 @@
 #define CONFIG_BOOKE   1   /* BOOKE */
 #define CONFIG_E5001   /* BOOKE e500 family */
 #define CONFIG_CPM21   /* has CPM2 */
-#define CONFIG_MPC8555CDS  1   /* MPC8555CDS board specific */
 
 #defineCONFIG_SYS_TEXT_BASE0xfff8
 
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index aa7dcc8..39507d3 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -3141,7 +3141,6 @@ CONFIG_MPC83XX_GPIO_1_INIT_VALUE
 CONFIG_MPC83XX_PCI2
 CONFIG_MPC850
 CONFIG_MPC855
-CONFIG_MPC8555CDS
 CONFIG_MPC8560
 CONFIG_MPC8560ADS
 CONFIG_MPC8568
-- 
2.7.4

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[U-Boot] [PATCH 21/97] powerpc: MPC8568: Remove macro CONFIG_MPC8568

[York Sun]

Replace CONFIG_MPC8568 with ARCH_MPC8568 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun 
---

 arch/powerpc/cpu/mpc85xx/Kconfig  | 4 
 arch/powerpc/cpu/mpc85xx/Makefile | 2 +-
 arch/powerpc/include/asm/config_mpc85xx.h | 2 +-
 arch/powerpc/include/asm/immap_85xx.h | 2 +-
 include/configs/MPC8568MDS.h  | 1 -
 scripts/config_whitelist.txt  | 1 -
 6 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 98f98af..9545793 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -84,6 +84,7 @@ config TARGET_MPC8560ADS
 
 config TARGET_MPC8568MDS
bool "Support MPC8568MDS"
+   select ARCH_MPC8568
 
 config TARGET_MPC8569MDS
bool "Support MPC8569MDS"
@@ -215,6 +216,9 @@ config ARCH_MPC8555
 config ARCH_MPC8560
bool
 
+config ARCH_MPC8568
+   bool
+
 source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile 
b/arch/powerpc/cpu/mpc85xx/Makefile
index 4733bfd..390eede 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -69,7 +69,7 @@ obj-$(CONFIG_ARCH_C29X)   += c29x_serdes.o
 obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o
 obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
 obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
-obj-$(CONFIG_MPC8568) += mpc8568_serdes.o
+obj-$(CONFIG_ARCH_MPC8568) += mpc8568_serdes.o
 obj-$(CONFIG_MPC8569) += mpc8569_serdes.o
 obj-$(CONFIG_MPC8572) += mpc8572_serdes.o
 obj-$(CONFIG_P1010)+= p1010_serdes.o
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index ef591b9..c38d983 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -98,7 +98,7 @@
 #define CONFIG_SYS_FSL_DDRC_GEN1
 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
 
-#elif defined(CONFIG_MPC8568)
+#elif defined(CONFIG_ARCH_MPC8568)
 #define CONFIG_MAX_CPUS1
 #define CONFIG_SYS_FSL_NUM_LAWS10
 #define CONFIG_SYS_FSL_DDRC_GEN2
diff --git a/arch/powerpc/include/asm/immap_85xx.h 
b/arch/powerpc/include/asm/immap_85xx.h
index d6e7f62..ec4c837 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2484,7 +2484,7 @@ typedef struct ccsr_gur {
u32 svr;/* System version */
u8  res10[8];
u32 rstcr;  /* Reset control */
-#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
+#if defined(CONFIG_ARCH_MPC8568) || defined(CONFIG_MPC8569)
u8  res11a[76];
par_io_t qe_par_io[7];
u8  res11b[1600];
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 62f06db..18adc6f 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -13,7 +13,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE   1   /* BOOKE */
 #define CONFIG_E5001   /* BOOKE e500 family */
-#define CONFIG_MPC8568 1   /* MPC8568 specific */
 #define CONFIG_MPC8568MDS  1   /* MPC8568MDS board specific */
 
 #defineCONFIG_SYS_TEXT_BASE0xfff8
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 722fb66..c6f12d0 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -3141,7 +3141,6 @@ CONFIG_MPC83XX_GPIO_1_INIT_VALUE
 CONFIG_MPC83XX_PCI2
 CONFIG_MPC850
 CONFIG_MPC855
-CONFIG_MPC8568
 CONFIG_MPC8568MDS
 CONFIG_MPC8569
 CONFIG_MPC8569MDS
-- 
2.7.4

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[U-Boot] [PATCH 11/97] powerpc: MPC8536: Move CONFIG_MPC8536 to Kconfig option

[York Sun]

Replace CONFIG_MPC8536 with ARCH_MPC8536 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun 
---

 arch/powerpc/cpu/mpc85xx/Kconfig  | 4 
 arch/powerpc/cpu/mpc85xx/Makefile | 2 +-
 arch/powerpc/include/asm/config_mpc85xx.h | 2 +-
 arch/powerpc/include/asm/immap_85xx.h | 4 ++--
 arch/powerpc/include/asm/processor.h  | 2 +-
 include/configs/MPC8536DS.h   | 1 -
 scripts/config_whitelist.txt  | 1 -
 7 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 640c846..682d4e7 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -56,6 +56,7 @@ config TARGET_P5040DS
 
 config TARGET_MPC8536DS
bool "Support MPC8536DS"
+   select ARCH_MPC8536
 
 config TARGET_MPC8540ADS
bool "Support MPC8540ADS"
@@ -189,6 +190,9 @@ config ARCH_BSC9132
 config ARCH_C29X
bool
 
+config ARCH_MPC8536
+   bool
+
 config ARCH_MPC8544
bool
 
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile 
b/arch/powerpc/cpu/mpc85xx/Makefile
index bfff58e..4733bfd 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -66,7 +66,7 @@ obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
 
 # SoC specific SERDES support
 obj-$(CONFIG_ARCH_C29X)+= c29x_serdes.o
-obj-$(CONFIG_MPC8536) += mpc8536_serdes.o
+obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o
 obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
 obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
 obj-$(CONFIG_MPC8568) += mpc8568_serdes.o
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 77e3f83..be1ab4a 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -35,7 +35,7 @@
 #define CONFIG_SYS_NUM_TLBCAMS 16
 #endif
 
-#if defined(CONFIG_MPC8536)
+#if defined(CONFIG_ARCH_MPC8536)
 #define CONFIG_MAX_CPUS1
 #define CONFIG_SYS_FSL_NUM_LAWS12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB  1
diff --git a/arch/powerpc/include/asm/immap_85xx.h 
b/arch/powerpc/include/asm/immap_85xx.h
index cef9da0..1ae5af1 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2120,7 +2120,7 @@ typedef struct ccsr_rcpm {
 #else
 typedef struct ccsr_gur {
u32 porpllsr;   /* POR PLL ratio status */
-#ifdef CONFIG_MPC8536
+#ifdef CONFIG_ARCH_MPC8536
 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e00
 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT   25
 #elif defined(CONFIG_ARCH_C29X)
@@ -2203,7 +2203,7 @@ typedef struct ccsr_gur {
u8  res1[8];
u32 gpporcr;/* General-purpose POR configuration */
u8  res2[12];
-#if defined(CONFIG_MPC8536)
+#if defined(CONFIG_ARCH_MPC8536)
u32 gencfgr;/* General Configuration Register */
 #define MPC85xx_GENCFGR_SDHC_WP_INV0x2000
 #else
diff --git a/arch/powerpc/include/asm/processor.h 
b/arch/powerpc/include/asm/processor.h
index fdfca90..fbf72bb 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1048,7 +1048,7 @@
 #define SVR_FAM(svr)   (((svr) >> 20) & 0xFFF) /* Family field */
 #define SVR_MEM(svr)   (((svr) >> 16) & 0xF)   /* Member field */
 
-#ifdef CONFIG_MPC8536
+#ifdef CONFIG_ARCH_MPC8536
 #define SVR_MAJ(svr)   (((svr) >>  4) & 0x7)   /* Major revision field*/
 #else
 #define SVR_MAJ(svr)   (((svr) >>  4) & 0xF)   /* Major revision field*/
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 0f29863..d6ef67f 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -40,7 +40,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE   1   /* BOOKE */
 #define CONFIG_E5001   /* BOOKE e500 family */
-#define CONFIG_MPC8536 1
 #define CONFIG_MPC8536DS   1
 
 #define CONFIG_FSL_ELBC1   /* Has Enhanced localbus 
controller */
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 20ac99d..2dcbb04 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -3140,7 +3140,6 @@ CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN
 CONFIG_MPC83XX_GPIO_1_INIT_VALUE
 CONFIG_MPC83XX_PCI2
 CONFIG_MPC850
-CONFIG_MPC8536
 CONFIG_MPC8536DS
 CONFIG_MPC8540
 CONFIG_MPC8540ADS
-- 
2.7.4

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[U-Boot] [PATCH 09/97] powerpc: C29X: Move CONFIG_PPC_C29X to Kconfig option

[York Sun]

Replace CONFIG_PPC_C29X with ARCH_C29X in Kconfig and clean up existing
macros.

Signed-off-by: York Sun 
---

 arch/powerpc/cpu/mpc85xx/Kconfig  |  4 
 arch/powerpc/cpu/mpc85xx/Makefile |  2 +-
 arch/powerpc/cpu/mpc85xx/cpu_init.c   |  2 +-
 arch/powerpc/include/asm/config_mpc85xx.h |  4 ++--
 arch/powerpc/include/asm/immap_85xx.h | 10 +-
 drivers/crypto/fsl/jr.c   |  2 +-
 include/configs/C29XPCIE.h|  4 
 include/fsl_sec.h |  2 +-
 scripts/config_whitelist.txt  |  1 -
 9 files changed, 15 insertions(+), 16 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 4fd2ea6..640c846 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -33,6 +33,7 @@ config TARGET_BSC9132QDS
 
 config TARGET_C29XPCIE
bool "Support C29XPCIE"
+   select ARCH_C29X
select SUPPORT_SPL
select SUPPORT_TPL
select PHYS_64BIT
@@ -185,6 +186,9 @@ config ARCH_BSC9131
 config ARCH_BSC9132
bool
 
+config ARCH_C29X
+   bool
+
 config ARCH_MPC8544
bool
 
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile 
b/arch/powerpc/cpu/mpc85xx/Makefile
index e545112..bfff58e 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -65,7 +65,7 @@ obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
 obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
 
 # SoC specific SERDES support
-obj-$(CONFIG_PPC_C29X) += c29x_serdes.o
+obj-$(CONFIG_ARCH_C29X)+= c29x_serdes.o
 obj-$(CONFIG_MPC8536) += mpc8536_serdes.o
 obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
 obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index dfea750..c2402a8 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -959,7 +959,7 @@ int cpu_init_r(void)
 #ifdef CONFIG_FSL_CAAM
sec_init();
 
-#if defined(CONFIG_PPC_C29X)
+#if defined(CONFIG_ARCH_C29X)
if ((SVR_SOC_VER(svr) == SVR_C292) ||
(SVR_SOC_VER(svr) == SVR_C293))
sec_init_idx(1);
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 80b3b74..77e3f83 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -914,7 +914,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 
 
-#elif defined(CONFIG_PPC_C29X)
+#elif defined(CONFIG_ARCH_C29X)
 #define CONFIG_MAX_CPUS1
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_SYS_FSL_NUM_LAWS12
@@ -955,7 +955,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_DDRC_GEN3
 #endif
 
-#if !defined(CONFIG_PPC_C29X)
+#if !defined(CONFIG_ARCH_C29X)
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 #endif
 
diff --git a/arch/powerpc/include/asm/immap_85xx.h 
b/arch/powerpc/include/asm/immap_85xx.h
index 74c2959..cef9da0 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2123,7 +2123,7 @@ typedef struct ccsr_gur {
 #ifdef CONFIG_MPC8536
 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e00
 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT   25
-#elif defined(CONFIG_PPC_C29X)
+#elif defined(CONFIG_ARCH_C29X)
 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3f00
 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT   (9 - ((gur->pordevsr2 \
& MPC85xx_PORDEVSR2_DDR_SPD_0) \
@@ -2175,7 +2175,7 @@ typedef struct ccsr_gur {
 #elif defined(CONFIG_ARCH_BSC9132)
 #define MPC85xx_PORDEVSR_IO_SEL0x00FE
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT  17
-#elif defined(CONFIG_PPC_C29X)
+#elif defined(CONFIG_ARCH_C29X)
 #define MPC85xx_PORDEVSR_IO_SEL0x00e0
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT  21
 #else
@@ -2193,7 +2193,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR_RIO_DEV_ID0x0007
u32 pordbgmsr;  /* POR debug mode status */
u32 pordevsr2;  /* POR I/O device status 2 */
-#if defined(CONFIG_PPC_C29X)
+#if defined(CONFIG_ARCH_C29X)
 #define MPC85xx_PORDEVSR2_DDR_SPD_00x0008
 #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT  3
 #endif
@@ -2344,7 +2344,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR0_SIM_SEL_MASK   0x0003b000
 #define MPC85xx_PMUXCR0_SIM_SEL0x00014000
 #endif
-#if defined(CONFIG_PPC_C29X)
+#if defined(CONFIG_ARCH_C29X)
 #define MPC85xx_PMUXCR_SPI_MASK0x0300
 #define MPC85xx_PMUXCR_SPI 0x
 #define MPC85xx_PMUXCR_SPI_GPIO0x0100
@@ -2964,7 +2964,7 @@ struct ccsr_pman {
 #endif
 #define CONFIG_SYS_MDIO1_OFFSET0x24000
 #define 

[U-Boot] [PATCH 07/97] powerpc: BSC9131RDB: Remove CONFIG_BSC9131RDB macro

[York Sun]

This macro CONFIG_BSC9131RDB is no longer needed.

Signed-off-by: York Sun 
---

 configs/BSC9131RDB_NAND_SYSCLK100_defconfig | 2 +-
 configs/BSC9131RDB_NAND_defconfig   | 2 +-
 configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig | 2 +-
 configs/BSC9131RDB_SPIFLASH_defconfig   | 2 +-
 scripts/config_whitelist.txt| 1 -
 5 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig 
b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
index 484baf8..e88e234 100644
--- a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
@@ -7,7 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND,SYS_CLK_100"
+CONFIG_SYS_EXTRA_OPTIONS="NAND,SYS_CLK_100"
 CONFIG_BOOTDELAY=10
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SPL=y
diff --git a/configs/BSC9131RDB_NAND_defconfig 
b/configs/BSC9131RDB_NAND_defconfig
index ad24afa..5c4d45d 100644
--- a/configs/BSC9131RDB_NAND_defconfig
+++ b/configs/BSC9131RDB_NAND_defconfig
@@ -7,7 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_BOOTDELAY=10
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SPL=y
diff --git a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig 
b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
index 4904da4..23a74c3 100644
--- a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
@@ -5,7 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH,SYS_CLK_100"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100"
 CONFIG_BOOTDELAY=10
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/BSC9131RDB_SPIFLASH_defconfig 
b/configs/BSC9131RDB_SPIFLASH_defconfig
index 47b4486..2c5d637 100644
--- a/configs/BSC9131RDB_SPIFLASH_defconfig
+++ b/configs/BSC9131RDB_SPIFLASH_defconfig
@@ -5,7 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
 CONFIG_BOOTDELAY=10
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_HUSH_PARSER=y
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 8008a00..fa7fb7a 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -451,7 +451,6 @@ CONFIG_BOOT_RETRY_MIN
 CONFIG_BOOT_RETRY_TIME
 CONFIG_BOUNCE_BUFFER
 CONFIG_BPTR_VIRT_ADDR
-CONFIG_BSC9131RDB
 CONFIG_BSC9132QDS
 CONFIG_BSEIP
 CONFIG_BS_ADDR_DEVICE
-- 
2.7.4

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[U-Boot] [PATCH 03/97] powerpc: MPC8548CDS: Remove macro CONFIG_MPC8548CDS

[York Sun]

Use CONFIG_TARGET_MPC8548CDS instead.

Signed-off-by: York Sun 
---

 board/freescale/common/Makefile | 2 +-
 include/configs/MPC8548CDS.h| 1 -
 scripts/config_whitelist.txt| 1 -
 3 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index be114ce..c131ed9 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -46,7 +46,7 @@ endif
 obj-$(CONFIG_FSL_DCU_SII9022A)+= dcu_sii9022a.o
 
 obj-$(CONFIG_MPC8541CDS)   += cds_pci_ft.o
-obj-$(CONFIG_MPC8548CDS)   += cds_pci_ft.o
+obj-$(CONFIG_TARGET_MPC8548CDS)+= cds_pci_ft.o
 obj-$(CONFIG_MPC8555CDS)   += cds_pci_ft.o
 
 obj-$(CONFIG_MPC8536DS)+= ics307_clk.o
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 40922ee..310c070 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -16,7 +16,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE   1   /* BOOKE */
 #define CONFIG_E5001   /* BOOKE e500 family */
-#define CONFIG_MPC8548CDS  1   /* MPC8548CDS board specific */
 
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE   0xfff8
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index d5a6c98..68cca99 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -3153,7 +3153,6 @@ CONFIG_MPC8541
 CONFIG_MPC8541CDS
 CONFIG_MPC8544
 CONFIG_MPC8544DS
-CONFIG_MPC8548CDS
 CONFIG_MPC855
 CONFIG_MPC8555
 CONFIG_MPC8555CDS
-- 
2.7.4

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[U-Boot] [PATCH 06/97] powerpc: BSC9131/2: Move CONFIG_BSC9131/2 to Kconfig options

[York Sun]

Replace CONFIG_BSC9131, CONFIG_BSC9132 with ARCH_BSC9131, ARCH_BSC9132
Kconfig options.

Also drop #ifdef in BSC9131RDB.h since it is redundant.

Signed-off-by: York Sun 
---

 arch/powerpc/cpu/mpc85xx/Kconfig  |  8 
 arch/powerpc/cpu/mpc85xx/Makefile |  2 +-
 arch/powerpc/include/asm/config_mpc85xx.h |  4 ++--
 arch/powerpc/include/asm/fsl_law.h|  4 ++--
 arch/powerpc/include/asm/immap_85xx.h | 20 ++--
 include/configs/BSC9131RDB.h  |  3 ---
 include/configs/BSC9132QDS.h  |  4 
 scripts/config_whitelist.txt  |  2 --
 8 files changed, 23 insertions(+), 24 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 5ea02b5..4fd2ea6 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -23,10 +23,12 @@ config TARGET_B4860QDS
 
 config TARGET_BSC9131RDB
bool "Support BSC9131RDB"
+   select ARCH_BSC9131
select SUPPORT_SPL
 
 config TARGET_BSC9132QDS
bool "Support BSC9132QDS"
+   select ARCH_BSC9132
select SUPPORT_SPL
 
 config TARGET_C29XPCIE
@@ -177,6 +179,12 @@ config TARGET_CYRUS
 
 endchoice
 
+config ARCH_BSC9131
+   bool
+
+config ARCH_BSC9132
+   bool
+
 config ARCH_MPC8544
bool
 
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile 
b/arch/powerpc/cpu/mpc85xx/Makefile
index 744c781..e545112 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -96,7 +96,7 @@ obj-$(CONFIG_PPC_T4160) += t4240_serdes.o
 obj-$(CONFIG_PPC_T4080) += t4240_serdes.o
 obj-$(CONFIG_PPC_B4420) += b4860_serdes.o
 obj-$(CONFIG_PPC_B4860) += b4860_serdes.o
-obj-$(CONFIG_BSC9132) += bsc9132_serdes.o
+obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o
 obj-$(CONFIG_PPC_T1040) += t1040_serdes.o
 obj-$(CONFIG_PPC_T1042)+= t1040_serdes.o
 obj-$(CONFIG_PPC_T1020)+= t1040_serdes.o
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 5c97e69..80b3b74 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -579,7 +579,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000
 #define CONFIG_SYS_FSL_ERRATUM_A005812
 
-#elif defined(CONFIG_BSC9131)
+#elif defined(CONFIG_ARCH_BSC9131)
 #define CONFIG_MAX_CPUS1
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_SYS_FSL_NUM_LAWS12
@@ -598,7 +598,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004477
 #define CONFIG_ESDHC_HC_BLK_ADDR
 
-#elif defined(CONFIG_BSC9132)
+#elif defined(CONFIG_ARCH_BSC9132)
 #define CONFIG_MAX_CPUS2
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB  3
 #define CONFIG_FSL_SDHC_V2_3
diff --git a/arch/powerpc/include/asm/fsl_law.h 
b/arch/powerpc/include/asm/fsl_law.h
index 2a759c8..85278b3 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -82,7 +82,7 @@ enum law_trgt_if {
 #ifndef CONFIG_MPC8641
LAW_TRGT_IF_PCIE_1 = 0x02,
 #endif
-#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
+#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
LAW_TRGT_IF_OCN_DSP = 0x03,
 #else
 #if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
@@ -95,7 +95,7 @@ enum law_trgt_if {
LAW_TRGT_IF_PLATFORM_SRAM = 0x0a,
LAW_TRGT_IF_DDR_INTRLV = 0x0b,
LAW_TRGT_IF_RIO = 0x0c,
-#if defined(CONFIG_BSC9132)
+#if defined(CONFIG_ARCH_BSC9132)
LAW_TRGT_IF_CLASS_DSP = 0x0d,
 #else
LAW_TRGT_IF_RIO_2 = 0x0d,
diff --git a/arch/powerpc/include/asm/immap_85xx.h 
b/arch/powerpc/include/asm/immap_85xx.h
index 64c4435..74c2959 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2129,7 +2129,7 @@ typedef struct ccsr_gur {
& MPC85xx_PORDEVSR2_DDR_SPD_0) \
>> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
 #else
-#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
+#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3f00
 #else
 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e00
@@ -2172,7 +2172,7 @@ typedef struct ccsr_gur {
 #if defined(CONFIG_P1010)
 #define MPC85xx_PORDEVSR_IO_SEL0x0060
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT  21
-#elif defined(CONFIG_BSC9132)
+#elif defined(CONFIG_ARCH_BSC9132)
 #define MPC85xx_PORDEVSR_IO_SEL0x00FE
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT  17
 #elif defined(CONFIG_PPC_C29X)
@@ -2296,7 +2296,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR_SPI_MASK0x0060
 #define MPC85xx_PMUXCR_SPI 0x
 #endif
-#if defined(CONFIG_BSC9131)
+#if defined(CONFIG_ARCH_BSC9131)
 #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ  0x4000
 #define MPC85xx_PMUXCR_TSEC2_USB   0xC000
 #define 

[U-Boot] [PATCH 02/97] powerpc: MPC8548: Move CONFIG_MPC8548 to Kconfig option

[York Sun]

Replace CONFIG_MPC8548 with ARCH_MPC8548 in Kconfig.

Signed-off-by: York Sun 
---

 arch/powerpc/cpu/mpc85xx/Kconfig  | 6 ++
 arch/powerpc/cpu/mpc85xx/Makefile | 2 +-
 arch/powerpc/cpu/mpc85xx/cpu_init.c   | 2 +-
 arch/powerpc/include/asm/config_mpc85xx.h | 2 +-
 arch/powerpc/include/asm/immap_85xx.h | 8 
 board/xes/common/fsl_8xxx_pci.c   | 2 +-
 include/configs/MPC8548CDS.h  | 1 -
 include/configs/sbc8548.h | 1 -
 include/configs/xpedite520x.h | 1 -
 scripts/config_whitelist.txt  | 1 -
 10 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 9bcbda0..530c232 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -10,6 +10,7 @@ choice
 
 config TARGET_SBC8548
bool "Support sbc8548"
+   select ARCH_MPC8548
 
 config TARGET_SOCRATES
bool "Support socrates"
@@ -63,6 +64,7 @@ config TARGET_MPC8544DS
 
 config TARGET_MPC8548CDS
bool "Support MPC8548CDS"
+   select ARCH_MPC8548
 
 config TARGET_MPC8555CDS
bool "Support MPC8555CDS"
@@ -156,6 +158,7 @@ config TARGET_KMP204X
 
 config TARGET_XPEDITE520X
bool "Support xpedite520x"
+   select ARCH_MPC8548
 
 config TARGET_XPEDITE537X
bool "Support xpedite537x"
@@ -172,6 +175,9 @@ config TARGET_CYRUS
 
 endchoice
 
+config ARCH_MPC8548
+   bool
+
 source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile 
b/arch/powerpc/cpu/mpc85xx/Makefile
index f4c4fe2..1383454 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -68,7 +68,7 @@ obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
 obj-$(CONFIG_PPC_C29X) += c29x_serdes.o
 obj-$(CONFIG_MPC8536) += mpc8536_serdes.o
 obj-$(CONFIG_MPC8544) += mpc8544_serdes.o
-obj-$(CONFIG_MPC8548) += mpc8548_serdes.o
+obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
 obj-$(CONFIG_MPC8568) += mpc8568_serdes.o
 obj-$(CONFIG_MPC8569) += mpc8569_serdes.o
 obj-$(CONFIG_MPC8572) += mpc8572_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 53b3729..dfea750 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -442,7 +442,7 @@ ulong cpu_init_f(void)
 #if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT)
struct law_entry law;
 #endif
-#ifdef CONFIG_MPC8548
+#ifdef CONFIG_ARCH_MPC8548
ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
uint svr = get_svr();
 
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 6d845e8..1b4844f 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -66,7 +66,7 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
-#elif defined(CONFIG_MPC8548)
+#elif defined(CONFIG_ARCH_MPC8548)
 #define CONFIG_MAX_CPUS1
 #define CONFIG_SYS_FSL_NUM_LAWS10
 #define CONFIG_SYS_FSL_DDRC_GEN2
diff --git a/arch/powerpc/include/asm/immap_85xx.h 
b/arch/powerpc/include/asm/immap_85xx.h
index 76ea00b..64c4435 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -124,10 +124,10 @@ typedef struct ccsr_i2c {
u8  res[4096 - 1 * sizeof(struct fsl_i2c_base)];
 } ccsr_i2c_t;
 
-#if defined(CONFIG_MPC8540) \
-   || defined(CONFIG_MPC8541) \
-   || defined(CONFIG_MPC8548) \
-   || defined(CONFIG_MPC8555)
+#if defined(CONFIG_MPC8540) || \
+   defined(CONFIG_MPC8541) || \
+   defined(CONFIG_ARCH_MPC8548) || \
+   defined(CONFIG_MPC8555)
 /* DUART Registers */
 typedef struct ccsr_duart {
u8  res1[1280];
diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c
index 510f638..6237571 100644
--- a/board/xes/common/fsl_8xxx_pci.c
+++ b/board/xes/common/fsl_8xxx_pci.c
@@ -55,7 +55,7 @@ void pci_init_board(void)
} else {
printf("PCI1: disabled\n");
}
-#elif defined CONFIG_MPC8548
+#elif defined CONFIG_ARCH_MPC8548
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* PCI1 not present on MPC8572 */
setbits_be32(>devdisr, MPC85xx_DEVDISR_PCI1);
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index fa114b3..40922ee 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -16,7 +16,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE   1   /* BOOKE */
 #define CONFIG_E5001   /* BOOKE e500 family */
-#define CONFIG_MPC8548 1   /* MPC8548 specific */
 #define CONFIG_MPC8548CDS  1   /* MPC8548CDS 

[U-Boot] [PATCH 04/97] powerpc: MPC8544: Move CONFIG_MPC8544 to Kconfig option

[York Sun]

Replace CONFIG_MPC8544 with ARCH_MPC8544 in Kconfig.

Signed-off-by: York Sun 
---

 arch/powerpc/cpu/mpc85xx/Kconfig  | 5 +
 arch/powerpc/cpu/mpc85xx/Makefile | 2 +-
 arch/powerpc/cpu/mpc85xx/speed.c  | 4 ++--
 arch/powerpc/include/asm/config_mpc85xx.h | 2 +-
 include/configs/MPC8544DS.h   | 1 -
 include/configs/socrates.h| 1 -
 scripts/config_whitelist.txt  | 1 -
 7 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 530c232..5ea02b5 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -14,6 +14,7 @@ config TARGET_SBC8548
 
 config TARGET_SOCRATES
bool "Support socrates"
+   select ARCH_MPC8544
 
 config TARGET_B4860QDS
bool "Support B4860QDS"
@@ -61,6 +62,7 @@ config TARGET_MPC8541CDS
 
 config TARGET_MPC8544DS
bool "Support MPC8544DS"
+   select ARCH_MPC8544
 
 config TARGET_MPC8548CDS
bool "Support MPC8548CDS"
@@ -175,6 +177,9 @@ config TARGET_CYRUS
 
 endchoice
 
+config ARCH_MPC8544
+   bool
+
 config ARCH_MPC8548
bool
 
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile 
b/arch/powerpc/cpu/mpc85xx/Makefile
index 1383454..744c781 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -67,7 +67,7 @@ obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
 # SoC specific SERDES support
 obj-$(CONFIG_PPC_C29X) += c29x_serdes.o
 obj-$(CONFIG_MPC8536) += mpc8536_serdes.o
-obj-$(CONFIG_MPC8544) += mpc8544_serdes.o
+obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
 obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
 obj-$(CONFIG_MPC8568) += mpc8568_serdes.o
 obj-$(CONFIG_MPC8569) += mpc8569_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index e732969..be03e01 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -652,7 +652,7 @@ void get_sys_info(sys_info_t *sys_info)
 int get_clocks (void)
 {
sys_info_t sys_info;
-#ifdef CONFIG_MPC8544
+#ifdef CONFIG_ARCH_MPC8544
volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
 #endif
 #if defined(CONFIG_CPM2)
@@ -685,7 +685,7 @@ int get_clocks (void)
defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
defined(CONFIG_P1022)
gd->arch.i2c1_clk = sys_info.freq_systembus;
-#elif defined(CONFIG_MPC8544)
+#elif defined(CONFIG_ARCH_MPC8544)
/*
 * On the 8544, the I2C clock is the same as the SEC clock.  This can be
 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 1b4844f..5c97e69 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -57,7 +57,7 @@
 #define CONFIG_SYS_FSL_SEC_COMPAT  2
 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
 
-#elif defined(CONFIG_MPC8544)
+#elif defined(CONFIG_ARCH_MPC8544)
 #define CONFIG_MAX_CPUS1
 #define CONFIG_SYS_FSL_NUM_LAWS10
 #define CONFIG_SYS_FSL_DDRC_GEN2
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index d868ce2..fb5309a 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -14,7 +14,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE   1   /* BOOKE */
 #define CONFIG_E5001   /* BOOKE e500 family */
-#define CONFIG_MPC8544 1
 #define CONFIG_MPC8544DS   1
 
 #ifndef CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 753ccfb..c697f63 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -20,7 +20,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE   1   /* BOOKE*/
 #define CONFIG_E5001   /* BOOKE e500 family*/
-#define CONFIG_MPC8544 1
 #define CONFIG_SOCRATES1
 
 #defineCONFIG_SYS_TEXT_BASE0xfff8
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 68cca99..9a1bc54 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -3151,7 +3151,6 @@ CONFIG_MPC8540
 CONFIG_MPC8540ADS
 CONFIG_MPC8541
 CONFIG_MPC8541CDS
-CONFIG_MPC8544
 CONFIG_MPC8544DS
 CONFIG_MPC855
 CONFIG_MPC8555
-- 
2.7.4

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[U-Boot] [PATCH 01/97] tools/env: Correct include kconfig

[York Sun]

While we move some config macros to Kconfig, kconfig header is needed
to avoid compiling error if not already included.

Signed-off-by: York Sun 
---

 common/env_embedded.c | 2 ++
 tools/envcrc.c| 2 ++
 2 files changed, 4 insertions(+)

diff --git a/common/env_embedded.c b/common/env_embedded.c
index 56a13cb..b368fda 100644
--- a/common/env_embedded.c
+++ b/common/env_embedded.c
@@ -5,6 +5,8 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
+#include 
+
 #ifndef __ASSEMBLY__
 #define__ASSEMBLY__/* Dirty trick to get only 
#defines */
 #endif
diff --git a/tools/envcrc.c b/tools/envcrc.c
index a9d9b48..e9fd088 100644
--- a/tools/envcrc.c
+++ b/tools/envcrc.c
@@ -12,6 +12,8 @@
 #include 
 #include 
 
+#include 
+
 #ifndef __ASSEMBLY__
 #define__ASSEMBLY__/* Dirty trick to get only 
#defines */
 #endif
-- 
2.7.4

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[U-Boot] [PATCH v2 4/4] dts: popmetal: add usb host power supply node

[Kever Yang]

The popmetal board using a HOST_VBUS_DRV gpio signal to control the
USB host port 5V power, add a fix regulator and pinctrl for it, and
enable the USB host1 controller with the vbus-supply.

Signed-off-by: Kever Yang 
---

Changes in v2: None

 arch/arm/dts/rk3288-popmetal.dtsi | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm/dts/rk3288-popmetal.dtsi 
b/arch/arm/dts/rk3288-popmetal.dtsi
index f3bd468..e5be4cb 100644
--- a/arch/arm/dts/rk3288-popmetal.dtsi
+++ b/arch/arm/dts/rk3288-popmetal.dtsi
@@ -145,6 +145,18 @@
regulator-always-on;
vin-supply = <_io>;
};
+
+   vcc5v0_host: usb-host-regulator {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = < 14 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_vbus_drv>;
+   regulator-name = "vcc5v0_host";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   };
 };
 
  {
@@ -471,6 +483,12 @@
rockchip,pins = <7 11 RK_FUNC_GPIO _pull_none>;
};
};
+
+   usb_host {
+   host_vbus_drv: host-vbus-drv {
+   rockchip,pins = <0 14 RK_FUNC_GPIO _pull_none>;
+   };
+   };
 };
 
  {
@@ -515,6 +533,11 @@
status = "okay";
 };
 
+_host1 {
+   vbus-supply = <_host>;
+   status = "okay";
+};
+
  {
status = "okay";
 };
-- 
1.9.1

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[U-Boot] [PATCH v2 3/4] config: popmetal: enable the USB host controller and function

[Kever Yang]

RK3288 using the dwc2 USB host controller, enable it and other usb host
funtion like storage and ether.

Signed-off-by: Kever Yang 
Acked-by: Simon Glass 
---

Changes in v2: None

 configs/popmetal-rk3288_defconfig | 3 +++
 include/configs/rk3288_common.h   | 7 +++
 2 files changed, 10 insertions(+)

diff --git a/configs/popmetal-rk3288_defconfig 
b/configs/popmetal-rk3288_defconfig
index 1e70ae0..a2d1d65 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -63,3 +63,6 @@ CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
 CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 0868612..8006aac 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -90,6 +90,13 @@
 #define CONFIG_G_DNL_VENDOR_NUM0x2207
 #define CONFIG_G_DNL_PRODUCT_NUM   0x320a
 
+/* usb host support */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_ASIX
+#endif
 #define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x\0" \
"pxefile_addr_r=0x0010\0" \
-- 
1.9.1

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[U-Boot] [PATCH v2 1/4] usb: dwc2: add support for external vbus supply

[Kever Yang]

Some board do not use the dwc2 internal VBUS_DRV signal, but
use a gpio pin to enable the 5.0V VBUS power, add interface to
enable the power in dwc2 driver.

Signed-off-by: Kever Yang 
---

Changes in v2: None

 drivers/usb/host/dwc2.c | 29 +
 1 file changed, 29 insertions(+)

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index d08879d..8292aa8 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "dwc2.h"
 
@@ -55,6 +56,8 @@ DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, 
DWC2_STATUS_BUF_SIZE,
 static struct dwc2_priv local;
 #endif
 
+static struct udevice *g_dwc2_udev;
+
 /*
  * DWC2 IP interface
  */
@@ -159,6 +162,29 @@ static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
mdelay(100);
 }
 
+static int dwc_vbus_supply_init(void)
+{
+#if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR) && \
+   !defined(CONFIG_SPL_BUILD)
+   struct udevice *vbus_supply;
+   int ret;
+
+   ret = device_get_supply_regulator(g_dwc2_udev, "vbus-supply",
+ _supply);
+   if (ret) {
+   debug("%s: No vbus supply\n", g_dwc2_udev->name);
+   return 0;
+   }
+
+   ret = regulator_set_enable(vbus_supply, true);
+   if (ret) {
+   error("Error enabling vbus supply\n");
+   return ret;
+   }
+#endif
+   return 0;
+}
+
 /*
  * This function initializes the DWC_otg controller registers for
  * host mode.
@@ -248,6 +274,8 @@ static void dwc_otg_core_host_init(struct dwc2_core_regs 
*regs)
writel(hprt0, >hprt0);
}
}
+
+   dwc_vbus_supply_init();
 }
 
 /*
@@ -1194,6 +1222,7 @@ static int dwc2_usb_ofdata_to_platdata(struct udevice 
*dev)
const void *prop;
fdt_addr_t addr;
 
+   g_dwc2_udev = dev;
addr = dev_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
-- 
1.9.1

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[U-Boot] [PATCH v2 2/4] board: popmetal: de-assert the host rst pin in board init

[Kever Yang]

The PopMetal board have a on board FE1.1 usb 2.0 hub which connect to
the usb host port, we need to de-assert its reset pin to enable it.

Signed-off-by: Kever Yang 
---

Changes in v2:
- move the vbus power enable into dwc2 driver

 board/chipspark/popmetal_rk3288/popmetal-rk3288.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c 
b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
index aad74ef..ed82b2b 100644
--- a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
+++ b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
@@ -6,6 +6,7 @@
 
 #include 
 #include 
+#include 
 
 void board_boot_order(u32 *spl_boot_list)
 {
@@ -13,3 +14,19 @@ void board_boot_order(u32 *spl_boot_list)
spl_boot_list[0] = BOOT_DEVICE_MMC2;
spl_boot_list[1] = BOOT_DEVICE_MMC1;
 }
+
+#define GPIO7A3_HUB_RST227
+
+int rk_board_late_init(void)
+{
+   int ret;
+
+   ret = gpio_request(GPIO7A3_HUB_RST, "hub_rst");
+   if (ret)
+   return ret;
+   ret = gpio_direction_output(GPIO7A3_HUB_RST, 1);
+   if (ret)
+   return ret;
+
+   return 0;
+}
-- 
1.9.1

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[U-Boot] [PATCH v2 0/4] Enable the host controller and hub on PopMetal board

[Kever Yang]

The PopMetal board based on rk3288 SoC have 3 USB 2.0 host ports from
a usb 2.0 hub which connect to the rk3288 usb host1.

This patch set enable those ports by enable the rk3288 usb host controller
driver and usb host function like storage and ether, enable the port
power and de-assert the hub reset signal.

Test with U-disk on Popmetal board.
=> usb start
starting USB...
USB0:   Core Release: 3.10a
scanning bus 0 for devices... ** First descriptor is NOT a primary desc
on 0:1 **
3 USB Device(s) found
   scanning usb for ethernet devices... 0 Ethernet Device(s) found
=> usb tree
USB device tree:
  1  Hub (480 Mb/s, 0mA)
  |   U-Boot Root Hub
  |
  +-2  Hub (480 Mb/s, 100mA)
|   USB 2.0 Hub
|
+-3  Mass Storage (480 Mb/s, 300mA)
 Kingston DataTraveler G2 001D92AD7612B91113680066


Changes in v2:
- move the vbus power enable into dwc2 driver

Kever Yang (4):
  usb: dwc2: add support for external vbus supply
  board: popmetal: de-assert the host rst pin in board init
  config: popmetal: enable the USB host controller and function
  dts: popmetal: add usb host power supply node

 arch/arm/dts/rk3288-popmetal.dtsi | 23 ++
 board/chipspark/popmetal_rk3288/popmetal-rk3288.c | 17 +
 configs/popmetal-rk3288_defconfig |  3 +++
 drivers/usb/host/dwc2.c   | 29 +++
 include/configs/rk3288_common.h   |  7 ++
 5 files changed, 79 insertions(+)

-- 
1.9.1

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[U-Boot] [PATCH 10/19] imx: mx6sll: add clock support

[Peng Fan]

Add clock support for i.MX6SLL.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/cpu/armv7/mx6/clock.c | 28 +---
 1 file changed, 21 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 0f68218..fe5c349 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -171,6 +171,8 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
reg &= ~mask;
__raw_writel(reg, _ccm->CCGR2);
} else {
+   if (is_mx6sll())
+   return -EINVAL;
if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
mask = MXC_CCM_CCGR6_I2C4_MASK;
addr = _ccm->CCGR6;
@@ -382,7 +384,7 @@ static u32 get_ipg_per_clk(void)
u32 reg, perclk_podf;
 
reg = __raw_readl(_ccm->cscmr1);
-   if (is_mx6sl() || is_mx6sx() ||
+   if (is_mx6sll() || is_mx6sl() || is_mx6sx() ||
is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
return MXC_HCLK; /* OSC 24Mhz */
@@ -400,7 +402,7 @@ static u32 get_uart_clk(void)
reg = __raw_readl(_ccm->cscdr1);
 
if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
-   is_mx6ull()) {
+   is_mx6sll() || is_mx6ull()) {
if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
freq = MXC_HCLK;
}
@@ -420,7 +422,7 @@ static u32 get_cspi_clk(void)
 MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 
if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
-   is_mx6ull()) {
+   is_mx6sll() || is_mx6ull()) {
if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
return MXC_HCLK / (cspi_podf + 1);
}
@@ -482,7 +484,8 @@ static u32 get_mmdc_ch0_clk(void)
 
u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
 
-   if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) {
+   if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() ||
+   is_mx6sll()) {
podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
@@ -625,7 +628,8 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 
debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
 
-   if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) {
+   if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() &&
+   !is_mx6sll()) {
debug("This chip not support lcd!\n");
return;
}
@@ -783,7 +787,7 @@ int enable_lcdif_clock(u32 base_addr, bool enable)
 MXC_CCM_CCGR3_DISP_AXI_MASK) :
(MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
 MXC_CCM_CCGR3_DISP_AXI_MASK);
-   } else if (is_mx6ul() || is_mx6ull()) {
+   } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
if (base_addr != LCDIF1_BASE_ADDR) {
puts("Wrong LCD interface!\n");
return -EINVAL;
@@ -976,6 +980,16 @@ static u32 get_usdhc_clk(u32 port)
u32 cscmr1 = __raw_readl(_ccm->cscmr1);
u32 cscdr1 = __raw_readl(_ccm->cscdr1);
 
+   if (is_mx6ul() || is_mx6ull()) {
+   if (port > 1)
+   return 0;
+   }
+
+   if (is_mx6sll()) {
+   if (port > 2)
+   return 0;
+   }
+
switch (port) {
case 0:
usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
@@ -1139,7 +1153,7 @@ void hab_caam_clock_enable(unsigned char enable)
 {
u32 reg;
 
-   if (is_mx6ull()) {
+   if (is_mx6ull() || is_mx6sll()) {
/* CG5, DCP clock */
reg = __raw_readl(_ccm->CCGR0);
if (enable)
-- 
2.6.2

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[U-Boot] [PATCH 16/19] pinctrl: imx6: support i.MX6SLL

[Peng Fan]

There two iomuxc for i.MX6SLL. One is normal IOMUXC, the other
is for IOMUXC_SNVS.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Simon Glass 
---
 drivers/pinctrl/nxp/pinctrl-imx6.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c 
b/drivers/pinctrl/nxp/pinctrl-imx6.c
index 32b4754..4488b16 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx6.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx6.c
@@ -28,6 +28,8 @@ static const struct udevice_id imx6_pinctrl_match[] = {
{ .compatible = "fsl,imx6q-iomuxc", .data = 
(ulong)_pinctrl_soc_info },
{ .compatible = "fsl,imx6dl-iomuxc", .data = 
(ulong)_pinctrl_soc_info },
{ .compatible = "fsl,imx6sl-iomuxc", .data = 
(ulong)_pinctrl_soc_info },
+   { .compatible = "fsl,imx6sll-iomuxc-snvs", .data = 
(ulong)_snvs_pinctrl_soc_info },
+   { .compatible = "fsl,imx6sll-iomuxc", .data = 
(ulong)_pinctrl_soc_info },
{ .compatible = "fsl,imx6sx-iomuxc", .data = 
(ulong)_pinctrl_soc_info },
{ .compatible = "fsl,imx6ul-iomuxc", .data = 
(ulong)_pinctrl_soc_info },
{ .compatible = "fsl,imx6ull-iomuxc-snvs", .data = 
(ulong)_snvs_pinctrl_soc_info },
-- 
2.6.2

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[U-Boot] [PATCH 18/19] arm: imx: add i.MX6SLL EVK board support

[Peng Fan]

Add i.MX6SLL EVK board support.
1. Add imx6sll-evk device tree.
2. Enable SDHC/I2C/UART.
3. Enable REGULATOR/PMIC/I2C/GPIO/SDHC/PINCTRL driver.

Boot Log:
U-Boot 2016.11-00127-gc635871-dirty (Nov 24 2016 - 13:28:19 +0800)

CPU:   Freescale i.MX6SLL rev1.0 at 792MHz
CPU:   Commercial temperature grade (0C to 95C)Reset cause: POR
Model: Freescale i.MX6SLL EVK Board
Board: MX6SLL EVK
DRAM:  2 GiB
i2c bus 0 at 35258368, no gpio pinctrl state.
PMIC: PFUZE100! DEV_ID=0x10 REV_ID=0x21
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
In:serial
Out:   serial
Err:   serial
Net:   CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/cpu/armv7/mx6/Kconfig |   7 +
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/imx6sll-evk.dts   | 801 +
 board/freescale/mx6sllevk/Kconfig  |  12 +
 board/freescale/mx6sllevk/Makefile |   6 +
 board/freescale/mx6sllevk/imximage.cfg | 121 +
 board/freescale/mx6sllevk/mx6sllevk.c  | 131 ++
 configs/mx6sllevk_defconfig|  36 ++
 include/configs/mx6sllevk.h| 152 +++
 9 files changed, 1267 insertions(+)
 create mode 100644 arch/arm/dts/imx6sll-evk.dts
 create mode 100644 board/freescale/mx6sllevk/Kconfig
 create mode 100644 board/freescale/mx6sllevk/Makefile
 create mode 100644 board/freescale/mx6sllevk/imximage.cfg
 create mode 100644 board/freescale/mx6sllevk/mx6sllevk.c
 create mode 100644 configs/mx6sllevk_defconfig
 create mode 100644 include/configs/mx6sllevk.h

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 72bc083..c5674c5 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -124,6 +124,12 @@ config TARGET_MX6SLEVK
bool "mx6slevk"
select SUPPORT_SPL
 
+config TARGET_MX6SLLEVK
+bool "mx6sll evk"
+select MX6SLL
+select DM
+select DM_THERMAL
+
 config TARGET_MX6SXSABRESD
bool "mx6sxsabresd"
select MX6SX
@@ -244,6 +250,7 @@ source "board/freescale/mx6qarm2/Kconfig"
 source "board/freescale/mx6qsabreauto/Kconfig"
 source "board/freescale/mx6sabresd/Kconfig"
 source "board/freescale/mx6slevk/Kconfig"
+source "board/freescale/mx6sllevk/Kconfig"
 source "board/freescale/mx6sxsabresd/Kconfig"
 source "board/freescale/mx6sxsabreauto/Kconfig"
 source "board/freescale/mx6ul_14x14_evk/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2c5b2f2..4b4356b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -285,6 +285,7 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
bk4r1.dtb
 
 dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
+   imx6sll-evk.dtb \
imx6dl-icore.dtb \
imx6q-icore.dtb
 
diff --git a/arch/arm/dts/imx6sll-evk.dts b/arch/arm/dts/imx6sll-evk.dts
new file mode 100644
index 000..b4af007
--- /dev/null
+++ b/arch/arm/dts/imx6sll-evk.dts
@@ -0,0 +1,801 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include 
+#include 
+#include "imx6sll.dtsi"
+
+/ {
+   model = "Freescale i.MX6SLL EVK Board";
+   compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
+
+   memory {
+   reg = <0x8000 0x8000>;
+   };
+
+   backlight {
+   compatible = "pwm-backlight";
+   pwms = < 0 500>;
+   brightness-levels = <0 4 8 16 32 64 128 255>;
+   default-brightness-level = <6>;
+   status = "okay";
+   };
+
+   battery: max8903@0 {
+   compatible = "fsl,max8903-charger";
+   pinctrl-names = "default";
+   dok_input = < 13 1>;
+   uok_input = < 13 1>;
+   chg_input = < 15 1>;
+   flt_input = < 14 1>;
+   fsl,dcm_always_high;
+   fsl,dc_valid;
+   fsl,adc_disable;
+   status = "okay";
+   };
+
+   pxp_v4l2_out {
+   compatible = "fsl,imx6sl-pxp-v4l2";
+   status = "okay";
+   };
+
+   regulators {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   reg_usb_otg1_vbus: regulator@0 {
+   compatible = "regulator-fixed";
+   reg = <0>;
+   regulator-name = "usb_otg1_vbus";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   gpio = < 0 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
+
+   reg_usb_otg2_vbus: regulator@1 {
+   

[U-Boot] [PATCH 11/19] imx-common: cache: configure L2 Cache for i.MX6SLL

[Peng Fan]

If L2 cache configured as OCRAM, reset it.
Switch to use runtime check.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/imx-common/cache.c | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c
index b775488..1c4a9a2 100644
--- a/arch/arm/imx-common/cache.c
+++ b/arch/arm/imx-common/cache.c
@@ -8,6 +8,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
@@ -39,6 +40,7 @@ void enable_caches(void)
 void v7_outer_cache_enable(void)
 {
struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+   struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
unsigned int val;
 
 
@@ -55,15 +57,14 @@ void v7_outer_cache_enable(void)
 */
setbits_le32(>pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
 
-#if defined CONFIG_MX6SL
-   struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-   val = readl(>gpr[11]);
-   if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
-   /* L2 cache configured as OCRAM, reset it */
-   val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
-   writel(val, >gpr[11]);
+   if (is_mx6sl() || is_mx6sll()) {
+   val = readl(>gpr[11]);
+   if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
+   /* L2 cache configured as OCRAM, reset it */
+   val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
+   writel(val, >gpr[11]);
+   }
}
-#endif
 
writel(0x132, >pl310_tag_latency_ctrl);
writel(0x132, >pl310_data_latency_ctrl);
-- 
2.6.2

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[U-Boot] [PATCH 04/19] imx-common: timer: add i.MX6SLL support

[Peng Fan]

Add i.MX6 SLL GPT timer support.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/imx-common/timer.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index 1f7c671..ee6eff2 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -45,7 +45,7 @@ static inline int gpt_has_clk_source_osc(void)
 #if defined(CONFIG_MX6)
if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
-   is_mx6ull())
+   is_mx6ull() || is_mx6sll())
return 1;
 
return 0;
@@ -84,8 +84,12 @@ int timer_init(void)
if (gpt_has_clk_source_osc()) {
i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
 
-   /* For DL/S, SX, UL, ULL set 24Mhz OSC Enable bit and prescaler 
*/
-   if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull()) {
+   /*
+* For DL/S, SX, UL, ULL, SLL set 24Mhz OSC
+* Enable bit and prescaler
+*/
+   if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
+   is_mx6sll()) {
i |= GPTCR_24MEN;
 
/* Produce 3Mhz clock */
-- 
2.6.2

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[U-Boot] [PATCH 15/19] imx-common: lcdif: update lcdif regs for i.MX6SL/SLL

[Peng Fan]

Update lcdif regs for i.MX6SL/SLL

Signed-off-by: Ye.Li 
Signed-off-by: Peng Fan 
---
 arch/arm/include/asm/imx-common/regs-lcdif.h | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/imx-common/regs-lcdif.h 
b/arch/arm/include/asm/imx-common/regs-lcdif.h
index 5a4f61f..ab147b5 100644
--- a/arch/arm/include/asm/imx-common/regs-lcdif.h
+++ b/arch/arm/include/asm/imx-common/regs-lcdif.h
@@ -20,7 +20,7 @@ struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_ctrl)   /* 0x00 */
mxs_reg_32(hw_lcdif_ctrl1)  /* 0x10 */
 #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
-   defined(CONFIG_MX7)
+   defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
mxs_reg_32(hw_lcdif_ctrl2)  /* 0x20 */
 #endif
mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
@@ -56,7 +56,7 @@ struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_data)   /* 0x1b0/0x180 */
mxs_reg_32(hw_lcdif_bm_error_stat)  /* 0x1c0/0x190 */
 #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
-   defined(CONFIG_MX7)
+   defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
mxs_reg_32(hw_lcdif_crc_stat)   /* 0x1a0 */
 #endif
mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
@@ -64,7 +64,8 @@ struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */
mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */
mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */
-#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7)
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7) || \
+   defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
mxs_reg_32(hw_lcdif_thres)
mxs_reg_32(hw_lcdif_as_ctrl)
mxs_reg_32(hw_lcdif_as_buf)
-- 
2.6.2

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[U-Boot] [PATCH 12/19] imx: mx6sll: add Kconfig entry for i.MX6SLL

[Peng Fan]

add Kconfig entry for i.MX6SLL

Signed-off-by: Peng Fan 
---
 arch/arm/cpu/armv7/mx6/Kconfig | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 762a581..72bc083 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -26,6 +26,10 @@ config MX6SX
select ROM_UNIFIED_SECTIONS
bool
 
+config MX6SLL
+   select ROM_UNIFIED_SECTIONS
+   bool
+
 config MX6UL
select SYS_L2CACHE_OFF
select ROM_UNIFIED_SECTIONS
-- 
2.6.2

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[U-Boot] [PATCH 09/19] imx: clock: gate clk before changing pix clk mux

[Peng Fan]

The LCDIF Pixel clock mux is not glitchless, so need
to gate before changing mux.

Also change enable_lcdif_clock prototype with a new input
parameter to indicate disable or enable.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/cpu/armv7/mx6/clock.c| 50 ++-
 arch/arm/include/asm/arch-mx6/clock.h |  2 +-
 board/freescale/mx6sxsabresd/mx6sxsabresd.c   |  2 +-
 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c |  2 +-
 4 files changed, 33 insertions(+), 23 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index e307b28..0f68218 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -707,6 +707,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
return;
 
+   enable_lcdif_clock(base_addr, 0);
if (!is_mx6sl()) {
/* Select pre-lcd clock to PLL5 and set pre divider */
clrsetbits_le32(_ccm->cscdr2,
@@ -736,11 +737,14 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
(((postd - 1)^0x6) <<
 MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET));
}
+
+   enable_lcdif_clock(base_addr, 1);
} else if (is_mx6sx()) {
/* Setting LCDIF2 for i.MX6SX */
if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
return;
 
+   enable_lcdif_clock(base_addr, 0);
/* Select pre-lcd clock to PLL5 and set pre divider */
clrsetbits_le32(_ccm->cscdr2,
MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
@@ -754,10 +758,12 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
((postd - 1) <<
 MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
+
+   enable_lcdif_clock(base_addr, 1);
}
 }
 
-int enable_lcdif_clock(u32 base_addr)
+int enable_lcdif_clock(u32 base_addr, bool enable)
 {
u32 reg = 0;
u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
@@ -796,15 +802,17 @@ int enable_lcdif_clock(u32 base_addr)
 MXC_CCM_CCGR3_LCDIF_PIX_MASK);
writel(reg, _ccm->CCGR3);
 
-   reg = readl(_ccm->cscdr3);
-   reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK;
-   reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET;
-   writel(reg, _ccm->cscdr3);
+   if (enable) {
+   reg = readl(_ccm->cscdr3);
+   reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK;
+   reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET;
+   writel(reg, _ccm->cscdr3);
 
-   reg = readl(_ccm->CCGR3);
-   reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK |
-   MXC_CCM_CCGR3_LCDIF_PIX_MASK;
-   writel(reg, _ccm->CCGR3);
+   reg = readl(_ccm->CCGR3);
+   reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK |
+   MXC_CCM_CCGR3_LCDIF_PIX_MASK;
+   writel(reg, _ccm->CCGR3);
+   }
 
return 0;
} else {
@@ -820,19 +828,21 @@ int enable_lcdif_clock(u32 base_addr)
reg &= ~MXC_CCM_CCGR2_LCD_MASK;
writel(reg, _ccm->CCGR2);
 
-   /* Select pre-mux */
-   reg = readl(_ccm->cscdr2);
-   reg &= ~lcdif_clk_sel_mask;
-   writel(reg, _ccm->cscdr2);
+   if (enable) {
+   /* Select pre-mux */
+   reg = readl(_ccm->cscdr2);
+   reg &= ~lcdif_clk_sel_mask;
+   writel(reg, _ccm->cscdr2);
 
-   /* Enable the LCDIF pix clock */
-   reg = readl(_ccm->CCGR3);
-   reg |= lcdif_ccgr3_mask;
-   writel(reg, _ccm->CCGR3);
+   /* Enable the LCDIF pix clock */
+   reg = readl(_ccm->CCGR3);
+   reg |= lcdif_ccgr3_mask;
+   writel(reg, _ccm->CCGR3);
 
-   reg = readl(_ccm->CCGR2);
-   reg |= MXC_CCM_CCGR2_LCD_MASK;
-   writel(reg, _ccm->CCGR2);
+   reg = readl(_ccm->CCGR2);
+   reg |= MXC_CCM_CCGR2_LCD_MASK;
+   writel(reg, _ccm->CCGR2);
+   }
 
return 0;
 }
diff --git a/arch/arm/include/asm/arch-mx6/clock.h 
b/arch/arm/include/asm/arch-mx6/clock.h
index 82f9f92..0cbf699 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -74,7 +74,7 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num);
 void enable_ipu_clock(void);
 int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
 void enable_enet_clk(unsigned char enable);
-int enable_lcdif_clock(u32 base_addr);

[U-Boot] [PATCH 08/19] imx: mx6sl: add lcdif clock support

[Peng Fan]

Add lcdif clock support for i.MX6SL.

Signed-off-by: Peng Fan 
---
 arch/arm/cpu/armv7/mx6/clock.c   | 78 
 arch/arm/include/asm/arch-mx6/crm_regs.h | 21 +
 2 files changed, 80 insertions(+), 19 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 644b9d7..e307b28 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -625,16 +625,18 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 
debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
 
-   if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull()) {
+   if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) {
debug("This chip not support lcd!\n");
return;
}
 
-   if (base_addr == LCDIF1_BASE_ADDR) {
-   reg = readl(_ccm->cscdr2);
-   /* Can't change clocks when clock not from pre-mux */
-   if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
-   return;
+   if (!is_mx6sl()) {
+   if (base_addr == LCDIF1_BASE_ADDR) {
+   reg = readl(_ccm->cscdr2);
+   /* Can't change clocks when clock not from pre-mux */
+   if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
+   return;
+   }
}
 
if (is_mx6sx()) {
@@ -705,19 +707,35 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
return;
 
-   /* Select pre-lcd clock to PLL5 and set pre divider */
-   clrsetbits_le32(_ccm->cscdr2,
-   MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
-   MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
-   (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
-   ((pred - 1) <<
-MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
-
-   /* Set the post divider */
-   clrsetbits_le32(_ccm->cbcmr,
-   MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
-   ((postd - 1) <<
-MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
+   if (!is_mx6sl()) {
+   /* Select pre-lcd clock to PLL5 and set pre divider */
+   clrsetbits_le32(_ccm->cscdr2,
+   MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
+   MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
+   (0x2 << 
MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
+   ((pred - 1) <<
+MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
+
+   /* Set the post divider */
+   clrsetbits_le32(_ccm->cbcmr,
+   MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
+   ((postd - 1) <<
+   MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
+   } else {
+   /* Select pre-lcd clock to PLL5 and set pre divider */
+   clrsetbits_le32(_ccm->cscdr2,
+   MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK |
+   MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK,
+   (0x2 << 
MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET) |
+   ((pred - 1) <<
+
MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET));
+
+   /* Set the post divider */
+   clrsetbits_le32(_ccm->cscmr1,
+   MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK,
+   (((postd - 1)^0x6) <<
+MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET));
+   }
} else if (is_mx6sx()) {
/* Setting LCDIF2 for i.MX6SX */
if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
@@ -767,6 +785,28 @@ int enable_lcdif_clock(u32 base_addr)
/* Set to pre-mux clock at default */
lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
lcdif_ccgr3_mask =  MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
+   } else if (is_mx6sl()) {
+   if (base_addr != LCDIF1_BASE_ADDR) {
+   puts("Wrong LCD interface!\n");
+   return -EINVAL;
+   }
+
+   reg = readl(_ccm->CCGR3);
+   reg &= ~(MXC_CCM_CCGR3_LCDIF_AXI_MASK |
+MXC_CCM_CCGR3_LCDIF_PIX_MASK);
+   writel(reg, _ccm->CCGR3);
+
+   reg = readl(_ccm->cscdr3);
+   reg &= 

[U-Boot] [PATCH 14/19] OCOTP: Update OCOTP driver to support i.MX6SLL

[Peng Fan]

Add the i.MX6SLL support to OCOTP driver.

The i.MX6SLL reuses the i.MX6ULL fuse, bank 7 and bank8 have 4 words
each, and there is a hole between bank 5 and bank 6.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/misc/mxc_ocotp.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index 8a100c1..0b1c050 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -62,7 +62,7 @@
 #define FUSE_BANK_SIZE 0x80
 #ifdef CONFIG_MX6SL
 #define FUSE_BANKS 8
-#elif defined(CONFIG_MX6ULL)
+#elif defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL)
 #define FUSE_BANKS 9
 #else
 #define FUSE_BANKS 16
@@ -79,7 +79,7 @@
 /*
  * There is a hole in shadow registers address map of size 0x100
  * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX,
- * iMX6UL and i.MX6ULL.
+ * iMX6UL, i.MX6ULL and i.MX6SLL.
  * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
  * we should account for this hole in address space.
  *
@@ -100,8 +100,8 @@ u32 fuse_bank_physical(int index)
 
if (is_mx6sl()) {
phy_index = index;
-   } else if (is_mx6ul() || is_mx6ull()) {
-   if (is_mx6ull() && index == 8)
+   } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
+   if ((is_mx6ull() || is_mx6sll()) && index == 8)
index = 7;
 
if (index >= 6)
@@ -121,7 +121,7 @@ u32 fuse_bank_physical(int index)
 
 u32 fuse_word_physical(u32 bank, u32 word_index)
 {
-   if (is_mx6ull()) {
+   if (is_mx6ull() || is_mx6sll()) {
if (bank == 8)
word_index = word_index + 4;
}
@@ -164,10 +164,10 @@ static int prepare_access(struct ocotp_regs **regs, u32 
bank, u32 word,
return -EINVAL;
}
 
-   if (is_mx6ull()) {
+   if (is_mx6ull() || is_mx6sll()) {
if ((bank == 7 || bank == 8) &&
word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) {
-   printf("mxc_ocotp %s(): Invalid argument on 6ULL\n", 
caller);
+   printf("mxc_ocotp %s(): Invalid argument\n", caller);
return -EINVAL;
}
}
@@ -271,7 +271,7 @@ static void setup_direct_access(struct ocotp_regs *regs, 
u32 bank, u32 word,
 #else
u32 addr;
/* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */
-   if ((is_mx6ull()) && (bank > 7)) {
+   if ((is_mx6ull() || is_mx6sll()) && (bank > 7)) {
bank = bank - 1;
word += 4;
}
-- 
2.6.2

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[U-Boot] [PATCH 07/19] imx: mx6: lcdif: gate clock before changing mux

[Peng Fan]

The mux for the lcd clock is not glitchless,
so need to first gate the clock before changing the mux.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/cpu/armv7/mx6/clock.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 8ab07b6..644b9d7 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -771,6 +771,16 @@ int enable_lcdif_clock(u32 base_addr)
return 0;
}
 
+   /* Gate LCDIF clock first */
+   reg = readl(_ccm->CCGR3);
+   reg &= ~lcdif_ccgr3_mask;
+   writel(reg, _ccm->CCGR3);
+
+   reg = readl(_ccm->CCGR2);
+   reg &= ~MXC_CCM_CCGR2_LCD_MASK;
+   writel(reg, _ccm->CCGR2);
+
+   /* Select pre-mux */
reg = readl(_ccm->cscdr2);
reg &= ~lcdif_clk_sel_mask;
writel(reg, _ccm->cscdr2);
-- 
2.6.2

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[U-Boot] [PATCH 03/19] imx: mx6sll: update register address

[Peng Fan]

Update register address for i.MX6 SLL

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/include/asm/arch-mx6/imx-regs.h | 76 
 1 file changed, 49 insertions(+), 27 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 8bb36eb..53e499c 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -26,7 +26,7 @@
 #define APBH_DMA_ARB_END_ADDR   0x0180BFFF
 #define M4_BOOTROM_BASE_ADDR   0x007F8000
 
-#else
+#elif !defined(CONFIG_MX6SLL)
 #define CAAM_ARB_BASE_ADDR  0x0010
 #define CAAM_ARB_END_ADDR   0x00103FFF
 #define APBH_DMA_ARB_BASE_ADDR  0x0011
@@ -46,13 +46,9 @@
 #define MXS_BCH_BASE   (APBH_DMA_ARB_BASE_ADDR + 0x04000)
 
 /* GPV - PL301 configuration ports */
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+ defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL))
 #define GPV2_BASE_ADDR  0x00D0
-#else
-#define GPV2_BASE_ADDR 0x0020
-#endif
-
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
 #define GPV3_BASE_ADDR 0x00E0
 #define GPV4_BASE_ADDR 0x00F0
 #define GPV5_BASE_ADDR 0x0100
@@ -61,6 +57,7 @@
 #define PCIE_ARB_END_ADDR   0x08FF
 
 #else
+#define GPV2_BASE_ADDR 0x0020
 #define GPV3_BASE_ADDR 0x0030
 #define GPV4_BASE_ADDR 0x0080
 #define PCIE_ARB_BASE_ADDR  0x0100
@@ -96,7 +93,7 @@
 #define WEIM_ARB_END_ADDR   0x57FF
 #define QSPI0_AMBA_BASE 0x6000
 #define QSPI0_AMBA_END  0x6FFF
-#else
+#elif !defined(CONFIG_MX6SLL)
 #define SATA_ARB_BASE_ADDR  0x0220
 #define SATA_ARB_END_ADDR   0x02203FFF
 #define OPENVG_ARB_BASE_ADDR0x02204000
@@ -111,7 +108,8 @@
 #define WEIM_ARB_END_ADDR   0x0FFF
 #endif
 
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+#if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
+ defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
 #define MMDC0_ARB_BASE_ADDR 0x8000
 #define MMDC0_ARB_END_ADDR  0x
 #define MMDC1_ARB_BASE_ADDR 0xC000
@@ -141,19 +139,21 @@
 #define ECSPI2_BASE_ADDR(ATZ1_BASE_ADDR + 0x0C000)
 #define ECSPI3_BASE_ADDR(ATZ1_BASE_ADDR + 0x1)
 #define ECSPI4_BASE_ADDR(ATZ1_BASE_ADDR + 0x14000)
-#ifdef CONFIG_MX6SL
-#define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
-#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2)
-#define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
-#define SSI1_IPS_BASE_ADDR  (ATZ1_BASE_ADDR + 0x28000)
-#define SSI2_IPS_BASE_ADDR  (ATZ1_BASE_ADDR + 0x2C000)
-#define SSI3_IPS_BASE_ADDR  (ATZ1_BASE_ADDR + 0x3)
-#define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
-#define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
-#else
+
+#define MX6SL_UART5_BASE_ADDR   (ATZ1_BASE_ADDR + 0x18000)
+#define MX6SLL_UART4_BASE_ADDR  (ATZ1_BASE_ADDR + 0x18000)
+#define MX6UL_UART7_BASE_ADDR   (ATZ1_BASE_ADDR + 0x18000)
+#define MX6SL_UART2_BASE_ADDR   (ATZ1_BASE_ADDR + 0x24000)
+#define MX6SLL_UART2_BASE_ADDR  (ATZ1_BASE_ADDR + 0x24000)
+#define MX6UL_UART8_BASE_ADDR   (ATZ1_BASE_ADDR + 0x24000)
+#define MX6SL_UART3_BASE_ADDR   (ATZ1_BASE_ADDR + 0x34000)
+#define MX6SLL_UART3_BASE_ADDR  (ATZ1_BASE_ADDR + 0x34000)
+#define MX6SL_UART4_BASE_ADDR   (ATZ1_BASE_ADDR + 0x38000)
+
 #ifndef CONFIG_MX6SX
 #define ECSPI5_BASE_ADDR(ATZ1_BASE_ADDR + 0x18000)
 #endif
+#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2)
 #define UART1_BASE  (ATZ1_BASE_ADDR + 0x2)
 #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
 #define UART8_BASE  (ATZ1_BASE_ADDR + 0x24000)
@@ -161,7 +161,6 @@
 #define SSI2_BASE_ADDR  (ATZ1_BASE_ADDR + 0x2C000)
 #define SSI3_BASE_ADDR  (ATZ1_BASE_ADDR + 0x3)
 #define ASRC_BASE_ADDR  (ATZ1_BASE_ADDR + 0x34000)
-#endif
 
 #ifndef CONFIG_MX6SX
 #define SPBA_BASE_ADDR  (ATZ1_BASE_ADDR + 0x3C000)
@@ -176,6 +175,8 @@
 #define PWM4_BASE_ADDR  (AIPS1_OFF_BASE_ADDR + 0xC000)
 #define CAN1_BASE_ADDR  (AIPS1_OFF_BASE_ADDR + 0x1)
 #define CAN2_BASE_ADDR  (AIPS1_OFF_BASE_ADDR + 0x14000)
+/* QOSC on i.MX6SLL */
+#define QOSC_BASE_ADDR  (AIPS1_OFF_BASE_ADDR + 0x14000)
 #define GPT1_BASE_ADDR  (AIPS1_OFF_BASE_ADDR + 0x18000)
 #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
 #define 

[U-Boot] [PATCH 00/19] imx: add i.MX6SLL support

[Peng Fan]

This patch set is to add i.MX6SLL support.
1. There are also a few patches to fix bugs in this patchset.
2. Default add device tree support.
3. Add two defconfigs, one for DCD, the other for plugin.

Peng Fan (19):
  imx: add i.MX 6SLL CPU type
  imx: mx6sll: add pinmux header files
  imx: mx6sll: update register address
  imx-common: timer: add i.MX6SLL support
  imx: mx6sll: add iomux settings
  imx: mx6: fix mmdc ch0 clk for 6SL
  imx: mx6: lcdif: gate clock before changing mux
  imx: mx6sl: add lcdif clock support
  imx: clock: gate clk before changing pix clk mux
  imx: mx6sll: add clock support
  imx-common: cache: configure L2 Cache for i.MX6SLL
  imx: mx6sll: add Kconfig entry for i.MX6SLL
  mx6_common: correct loadaddr and text base for i.MX6SLL
  OCOTP: Update OCOTP driver to support i.MX6SLL
  imx-common: lcdif: update lcdif regs for i.MX6SL/SLL
  pinctrl: imx6: support i.MX6SLL
  arm: dts: add i.MX6SLL device tree
  arm: imx: add i.MX6SLL EVK board support
  imx: mx6sllevk: add plugin support

 arch/arm/cpu/armv7/mx6/Kconfig|   11 +
 arch/arm/cpu/armv7/mx6/clock.c|  143 ++-
 arch/arm/dts/Makefile |1 +
 arch/arm/dts/imx6sll-evk.dts  |  801 
 arch/arm/dts/imx6sll-pinfunc.h|  882 ++
 arch/arm/dts/imx6sll.dtsi |  859 +
 arch/arm/imx-common/cache.c   |   17 +-
 arch/arm/imx-common/cpu.c |2 +
 arch/arm/imx-common/iomux-v3.c|   10 +-
 arch/arm/imx-common/timer.c   |   10 +-
 arch/arm/include/asm/arch-imx/cpu.h   |3 +-
 arch/arm/include/asm/arch-mx6/clock.h |2 +-
 arch/arm/include/asm/arch-mx6/crm_regs.h  |   21 +
 arch/arm/include/asm/arch-mx6/imx-regs.h  |   76 +-
 arch/arm/include/asm/arch-mx6/mx6-pins.h  |2 +
 arch/arm/include/asm/arch-mx6/mx6sll_pins.h   | 1019 +
 arch/arm/include/asm/imx-common/iomux-v3.h|6 +-
 arch/arm/include/asm/imx-common/regs-lcdif.h  |7 +-
 arch/arm/include/asm/imx-common/sys_proto.h   |1 +
 board/freescale/mx6sllevk/Kconfig |   12 +
 board/freescale/mx6sllevk/Makefile|6 +
 board/freescale/mx6sllevk/imximage.cfg|  127 +++
 board/freescale/mx6sllevk/mx6sllevk.c |  131 +++
 board/freescale/mx6sllevk/plugin.S|  155 
 board/freescale/mx6sxsabresd/mx6sxsabresd.c   |2 +-
 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c |2 +-
 configs/mx6sllevk_defconfig   |   36 +
 configs/mx6sllevk_plugin_defconfig|   37 +
 drivers/misc/mxc_ocotp.c  |   16 +-
 drivers/pinctrl/nxp/pinctrl-imx6.c|2 +
 include/configs/mx6_common.h  |3 +-
 include/configs/mx6sllevk.h   |  152 +++
 include/dt-bindings/clock/imx6sll-clock.h |  204 +
 33 files changed, 4667 insertions(+), 91 deletions(-)
 create mode 100644 arch/arm/dts/imx6sll-evk.dts
 create mode 100644 arch/arm/dts/imx6sll-pinfunc.h
 create mode 100644 arch/arm/dts/imx6sll.dtsi
 create mode 100644 arch/arm/include/asm/arch-mx6/mx6sll_pins.h
 create mode 100644 board/freescale/mx6sllevk/Kconfig
 create mode 100644 board/freescale/mx6sllevk/Makefile
 create mode 100644 board/freescale/mx6sllevk/imximage.cfg
 create mode 100644 board/freescale/mx6sllevk/mx6sllevk.c
 create mode 100644 board/freescale/mx6sllevk/plugin.S
 create mode 100644 configs/mx6sllevk_defconfig
 create mode 100644 configs/mx6sllevk_plugin_defconfig
 create mode 100644 include/configs/mx6sllevk.h
 create mode 100644 include/dt-bindings/clock/imx6sll-clock.h

-- 
2.6.2

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[U-Boot] [PATCH 2/2] armv8: ls2080aqds: Add support for SD boot

[Priyanka Jain]

Signed-off-by: Priyanka Jain 
Signed-off-by: Abhimanyu 
---
Depends on 
For correct type of image creation: 
https://patchwork.ozlabs.org/patch/671466/
For proper functonality on reverting below patch
ARM: Rework and correct barrier definitions

 configs/ls2080aqds_sdcard_defconfig |   49 +++
 include/configs/ls2080a_common.h|3 ++
 include/configs/ls2080aqds.h|7 +
 3 files changed, 59 insertions(+), 0 deletions(-)
 create mode 100644 configs/ls2080aqds_sdcard_defconfig

diff --git a/configs/ls2080aqds_sdcard_defconfig 
b/configs/ls2080aqds_sdcard_defconfig
new file mode 100644
index 000..985364c
--- /dev/null
+++ b/configs/ls2080aqds_sdcard_defconfig
@@ -0,0 +1,49 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080AQDS=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_FSL_DDR4=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 3828058..2d19357 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -263,6 +263,9 @@ unsigned long long get_qixis_addr(void);
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_SYS_NAND_U_BOOT_DST 0x8040
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_NAND_U_BOOT_DST
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR0x8b0
 #endif
 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0010
 #define CONFIG_SYS_SPL_MALLOC_START0x8020
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index a87d13a..1d69481 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -170,12 +170,14 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_LBMAP_DFLTBANK   0x00
 #define QIXIS_LBMAP_ALTBANK0x04
 #define QIXIS_LBMAP_NAND   0x09
+#define QIXIS_LBMAP_SD 0x00
 #define QIXIS_LBMAP_QSPI   0x0f
 #define QIXIS_RST_CTL_RESET0x31
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE   0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START  0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE  0x08
 #define QIXIS_RCW_SRC_NAND 0x107
+#define QIXIS_RCW_SRC_SD   0x40
 #define QIXIS_RCW_SRC_QSPI 0x62
 #defineQIXIS_RST_FORCE_MEM 0x01
 
@@ -239,6 +241,11 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SPL_PAD_TO  0x2
 #define CONFIG_SYS_NAND_U_BOOT_OFFS(256 * 1024)
 #define CONFIG_SYS_NAND_U_BOOT_SIZE(640 * 1024)
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET  0x20
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE0x2
 #endif
 #else
 #define CONFIG_SYS_CSPR0_EXT   CONFIG_SYS_NOR0_CSPR_EXT
-- 
1.7.4.1

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[U-Boot] [PATCH 19/19] imx: mx6sllevk: add plugin support

[Peng Fan]

Add plugin support for mx6sllevk board.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 board/freescale/mx6sllevk/imximage.cfg |   6 ++
 board/freescale/mx6sllevk/plugin.S | 155 +
 configs/mx6sllevk_plugin_defconfig |  37 
 3 files changed, 198 insertions(+)
 create mode 100644 board/freescale/mx6sllevk/plugin.S
 create mode 100644 configs/mx6sllevk_plugin_defconfig

diff --git a/board/freescale/mx6sllevk/imximage.cfg 
b/board/freescale/mx6sllevk/imximage.cfg
index 53fb74f..7d8b323 100644
--- a/board/freescale/mx6sllevk/imximage.cfg
+++ b/board/freescale/mx6sllevk/imximage.cfg
@@ -23,6 +23,11 @@ IMAGE_VERSION 2
 
 BOOT_FROM  sd
 
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGINplugin-binary-fileIRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx6sllevk/plugin.bin 0x00907000
+#else
+
 #ifdef CONFIG_SECURE_BOOT
 CSF CONFIG_CSF_SIZE
 #endif
@@ -119,3 +124,4 @@ DATA 4 0x021B0800 0xA1390003
 DATA 4 0x021B0004 0x00020052
 DATA 4 0x021B0404 0x00011006
 DATA 4 0x021B001C 0x
+#endif
diff --git a/board/freescale/mx6sllevk/plugin.S 
b/board/freescale/mx6sllevk/plugin.S
new file mode 100644
index 000..f9ef35a
--- /dev/null
+++ b/board/freescale/mx6sllevk/plugin.S
@@ -0,0 +1,155 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+
+/* DDR script */
+.macro imx6sll_evk_ddr_setting
+   ldr r0, =IOMUXC_BASE_ADDR
+   ldr r1, =0x0008
+   str r1, [r0, #0x550]
+   ldr r1, =0x
+   str r1, [r0, #0x534]
+   ldr r1, =0x0030
+   str r1, [r0, #0x2AC]
+   str r1, [r0, #0x548]
+   str r1, [r0, #0x52C]
+   ldr r1, =0x0002
+   str r1, [r0, #0x530]
+   ldr r1, =0x3030
+   str r1, [r0, #0x2B0]
+   str r1, [r0, #0x2B4]
+   str r1, [r0, #0x2B8]
+   str r1, [r0, #0x2BC]
+
+   ldr r1, =0x0002
+   str r1, [r0, #0x540]
+   ldr r1, =0x0030
+   str r1, [r0, #0x544]
+   str r1, [r0, #0x54C]
+   str r1, [r0, #0x554]
+   str r1, [r0, #0x558]
+   str r1, [r0, #0x294]
+   str r1, [r0, #0x298]
+   str r1, [r0, #0x29C]
+   str r1, [r0, #0x2A0]
+
+   ldr r1, =0x00082030
+   str r1, [r0, #0x2C0]
+
+   ldr r0, =MMDC_P0_BASE_ADDR
+   ldr r1, =0x8000
+   str r1, [r0, #0x1C]
+   ldr r1, =0xA1390003
+   str r1, [r0, #0x800]
+   ldr r1, =0x084700C7
+   str r1, [r0, #0x85C]
+   ldr r1, =0x0040
+   str r1, [r0, #0x890]
+
+   ldr r1, =0x3F393B3C
+   str r1, [r0, #0x848]
+   ldr r1, =0x262C3826
+   str r1, [r0, #0x850]
+
+   ldr r1, =0x
+   str r1, [r0, #0x81C]
+   str r1, [r0, #0x820]
+   str r1, [r0, #0x824]
+   str r1, [r0, #0x828]
+
+   ldr r1, =0xf333
+   str r1, [r0, #0x82C]
+   str r1, [r0, #0x830]
+   str r1, [r0, #0x834]
+   str r1, [r0, #0x838]
+
+   ldr r1, =0x24922492
+   str r1, [r0, #0x8C0]
+   ldr r1, =0x0800
+   str r1, [r0, #0x8B8]
+
+   ldr r1, =0x00020052
+   str r1, [r0, #0x004]
+   ldr r1, =0x53574333
+   str r1, [r0, #0x00C]
+   ldr r1, =0x00100B22
+   str r1, [r0, #0x010]
+   ldr r1, =0x00170778
+   str r1, [r0, #0x038]
+   ldr r1, =0x00C700DB
+   str r1, [r0, #0x014]
+   ldr r1, =0x00201718
+   str r1, [r0, #0x018]
+   ldr r1, =0x0F9F26D2
+   str r1, [r0, #0x02C]
+   ldr r1, =0x009F0E10
+   str r1, [r0, #0x030]
+   ldr r1, =0x005F
+   str r1, [r0, #0x040]
+   ldr r1, =0xC419
+   str r1, [r0, #0x000]
+   ldr r1, =0x2000
+   str r1, [r0, #0x83C]
+
+   ldr r1, =0x8050
+   str r1, [r0, #0x01C]
+   ldr r1, =0x8058
+   str r1, [r0, #0x01C]
+   ldr r1, =0x003F8030
+   str r1, [r0, #0x01C]
+   ldr r1, =0x003F8038
+   str r1, [r0, #0x01C]
+   ldr r1, =0xFF0A8030
+   str r1, [r0, #0x01C]
+   ldr r1, =0xFF0A8038
+   str r1, [r0, #0x01C]
+   ldr r1, =0x04028030
+   str r1, [r0, #0x01C]
+   ldr r1, =0x04028038
+   str r1, [r0, #0x01C]
+   ldr r1, =0x83018030
+   str r1, [r0, #0x01C]
+   ldr r1, =0x83018038
+   str r1, [r0, #0x01C]
+   ldr r1, =0x01038030
+   str r1, [r0, #0x01C]
+   ldr r1, =0x01038038
+   str r1, [r0, #0x01C]
+
+   ldr r1, =0x1800
+   str r1, [r0, #0x020]
+   ldr r1, =0xA1390003
+   str r1, [r0, #0x800]
+   ldr r1, =0x00020052
+   str r1, [r0, #0x004]
+   ldr r1, =0x00011006
+   str r1, [r0, #0x404]
+   ldr r1, =0x
+   str r1, [r0, #0x01C]
+.endm
+
+.macro imx6_clock_gating
+   ldr r0, =CCM_BASE_ADDR
+   ldr r1, =0x
+   str r1, [r0, #0x068]
+   str r1, [r0, #0x06c]
+   str r1, [r0, #0x070]
+   str r1, [r0, #0x074]
+   str r1, [r0, #0x078]
+   str r1, [r0, #0x07c]
+   str r1, [r0, #0x080]
+.endm
+

[U-Boot] [PATCH 1/2][RESEND] armv8:ls2080a: Reorganise NAND_BOOT code in config flag

[Priyanka Jain]

Add CONFIG_NAND_BOOT config flag to organise
NAND_BOOT specific code in config flag like
-nand-boot specfic errata errata_rcw_src()
-CONFIG_SYS_NAND_U_BOOT_DST,etc

Signed-off-by: Priyanka Jain 
Signed-off-by: Abhimanyu Saini 
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c |2 +-
 configs/ls2080aqds_nand_defconfig   |2 +-
 configs/ls2080ardb_nand_defconfig   |2 +-
 include/configs/ls2080a_common.h|4 
 include/configs/ls2080aqds.h|4 +++-
 5 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index d43361f..73a751d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -134,7 +134,7 @@ void erratum_a009635(void)
 
 static void erratum_rcw_src(void)
 {
-#if defined(CONFIG_SPL)
+#if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
u32 val;
diff --git a/configs/ls2080aqds_nand_defconfig 
b/configs/ls2080aqds_nand_defconfig
index 2161815..5e7bea5 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -12,7 +12,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, NAND_BOOT, LS2080A"
 CONFIG_BOOTDELAY=10
 CONFIG_SPL=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/ls2080ardb_nand_defconfig 
b/configs/ls2080ardb_nand_defconfig
index e40152e..d6633c3 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -12,7 +12,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, NAND_BOOT, LS2080A"
 CONFIG_BOOTDELAY=10
 CONFIG_SPL=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 2cae966..3828058 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -250,6 +250,7 @@ unsigned long long get_qixis_addr(void);
 
 #define CONFIG_PANIC_HANG  /* do not reset board on panic */
 
+#ifdef CONFIG_SPL
 #define CONFIG_SPL_BSS_START_ADDR  0x8010
 #define CONFIG_SPL_BSS_MAX_SIZE0x0010
 #define CONFIG_SPL_FRAMEWORK
@@ -259,11 +260,14 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SPL_TARGET  "u-boot-with-spl.bin"
 #define CONFIG_SPL_TEXT_BASE   0x1800a000
 
+#ifdef CONFIG_NAND_BOOT
 #define CONFIG_SYS_NAND_U_BOOT_DST 0x8040
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_NAND_U_BOOT_DST
+#endif
 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0010
 #define CONFIG_SYS_SPL_MALLOC_START0x8020
 #define CONFIG_SYS_MONITOR_LEN (640 * 1024)
+#endif
 
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)  /* Increase max gunzip size */
 
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 838568f..a87d13a 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -202,7 +202,8 @@ unsigned long get_board_ddr_clk(void);
FTIM2_GPCM_TWP(0x3E))
 #define CONFIG_SYS_CS3_FTIM3   0x0
 
-#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
+#if defined(CONFIG_SPL)
+#if defined(CONFIG_NAND_BOOT)
 #define CONFIG_SYS_CSPR1_EXT   CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR1   CONFIG_SYS_NOR0_CSPR_EARLY
 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
@@ -238,6 +239,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SPL_PAD_TO  0x2
 #define CONFIG_SYS_NAND_U_BOOT_OFFS(256 * 1024)
 #define CONFIG_SYS_NAND_U_BOOT_SIZE(640 * 1024)
+#endif
 #else
 #define CONFIG_SYS_CSPR0_EXT   CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0   CONFIG_SYS_NOR0_CSPR_EARLY
-- 
1.7.4.1

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[U-Boot] [PATCH 2/2][RESEND] armv8: ls2080aqds: Add support for SD boot

[Priyanka Jain]

Signed-off-by: Priyanka Jain 
Signed-off-by: Abhimanyu Saini 
---
Depends on 
For correct type of image creation: 
https://patchwork.ozlabs.org/patch/671466/
For proper functonality on reverting below patch
ARM: Rework and correct barrier definitions

 configs/ls2080aqds_sdcard_defconfig |   49 +++
 include/configs/ls2080a_common.h|3 ++
 include/configs/ls2080aqds.h|7 +
 3 files changed, 59 insertions(+), 0 deletions(-)
 create mode 100644 configs/ls2080aqds_sdcard_defconfig

diff --git a/configs/ls2080aqds_sdcard_defconfig 
b/configs/ls2080aqds_sdcard_defconfig
new file mode 100644
index 000..985364c
--- /dev/null
+++ b/configs/ls2080aqds_sdcard_defconfig
@@ -0,0 +1,49 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080AQDS=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_FSL_DDR4=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 3828058..2d19357 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -263,6 +263,9 @@ unsigned long long get_qixis_addr(void);
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_SYS_NAND_U_BOOT_DST 0x8040
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_NAND_U_BOOT_DST
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR0x8b0
 #endif
 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0010
 #define CONFIG_SYS_SPL_MALLOC_START0x8020
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index a87d13a..1d69481 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -170,12 +170,14 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_LBMAP_DFLTBANK   0x00
 #define QIXIS_LBMAP_ALTBANK0x04
 #define QIXIS_LBMAP_NAND   0x09
+#define QIXIS_LBMAP_SD 0x00
 #define QIXIS_LBMAP_QSPI   0x0f
 #define QIXIS_RST_CTL_RESET0x31
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE   0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START  0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE  0x08
 #define QIXIS_RCW_SRC_NAND 0x107
+#define QIXIS_RCW_SRC_SD   0x40
 #define QIXIS_RCW_SRC_QSPI 0x62
 #defineQIXIS_RST_FORCE_MEM 0x01
 
@@ -239,6 +241,11 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SPL_PAD_TO  0x2
 #define CONFIG_SYS_NAND_U_BOOT_OFFS(256 * 1024)
 #define CONFIG_SYS_NAND_U_BOOT_SIZE(640 * 1024)
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET  0x20
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE0x2
 #endif
 #else
 #define CONFIG_SYS_CSPR0_EXT   CONFIG_SYS_NOR0_CSPR_EXT
-- 
1.7.4.1

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[U-Boot] [PATCH 1/2] armv8:ls2080a: Reorganise NAND_BOOT code in config flag

[Priyanka Jain]

Add CONFIG_NAND_BOOT config flag to organise
NAND_BOOT specific code in config flag like
-nand-boot specfic errata errata_rcw_src()
-CONFIG_SYS_NAND_U_BOOT_DST,etc

Signed-off-by: Priyanka Jain 
Signed-off-by: Abhimanyu 
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c |2 +-
 configs/ls2080aqds_nand_defconfig   |2 +-
 configs/ls2080ardb_nand_defconfig   |2 +-
 include/configs/ls2080a_common.h|4 
 include/configs/ls2080aqds.h|4 +++-
 5 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index d43361f..73a751d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -134,7 +134,7 @@ void erratum_a009635(void)
 
 static void erratum_rcw_src(void)
 {
-#if defined(CONFIG_SPL)
+#if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
u32 val;
diff --git a/configs/ls2080aqds_nand_defconfig 
b/configs/ls2080aqds_nand_defconfig
index 2161815..5e7bea5 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -12,7 +12,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, NAND_BOOT, LS2080A"
 CONFIG_BOOTDELAY=10
 CONFIG_SPL=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/ls2080ardb_nand_defconfig 
b/configs/ls2080ardb_nand_defconfig
index e40152e..d6633c3 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -12,7 +12,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, NAND_BOOT, LS2080A"
 CONFIG_BOOTDELAY=10
 CONFIG_SPL=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 2cae966..3828058 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -250,6 +250,7 @@ unsigned long long get_qixis_addr(void);
 
 #define CONFIG_PANIC_HANG  /* do not reset board on panic */
 
+#ifdef CONFIG_SPL
 #define CONFIG_SPL_BSS_START_ADDR  0x8010
 #define CONFIG_SPL_BSS_MAX_SIZE0x0010
 #define CONFIG_SPL_FRAMEWORK
@@ -259,11 +260,14 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SPL_TARGET  "u-boot-with-spl.bin"
 #define CONFIG_SPL_TEXT_BASE   0x1800a000
 
+#ifdef CONFIG_NAND_BOOT
 #define CONFIG_SYS_NAND_U_BOOT_DST 0x8040
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_NAND_U_BOOT_DST
+#endif
 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0010
 #define CONFIG_SYS_SPL_MALLOC_START0x8020
 #define CONFIG_SYS_MONITOR_LEN (640 * 1024)
+#endif
 
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)  /* Increase max gunzip size */
 
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 838568f..a87d13a 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -202,7 +202,8 @@ unsigned long get_board_ddr_clk(void);
FTIM2_GPCM_TWP(0x3E))
 #define CONFIG_SYS_CS3_FTIM3   0x0
 
-#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
+#if defined(CONFIG_SPL)
+#if defined(CONFIG_NAND_BOOT)
 #define CONFIG_SYS_CSPR1_EXT   CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR1   CONFIG_SYS_NOR0_CSPR_EARLY
 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
@@ -238,6 +239,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SPL_PAD_TO  0x2
 #define CONFIG_SYS_NAND_U_BOOT_OFFS(256 * 1024)
 #define CONFIG_SYS_NAND_U_BOOT_SIZE(640 * 1024)
+#endif
 #else
 #define CONFIG_SYS_CSPR0_EXT   CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0   CONFIG_SYS_NOR0_CSPR_EARLY
-- 
1.7.4.1

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Re: [U-Boot] [PATCH] mmc: s5p_sdhci: fix to check proper pinmux id

[Jaehoon Chung]

Hi,

On 11/24/2016 11:29 AM, Seung-Woo Kim wrote:
> At sdhci_get_config(), there was wrong condition to check pimux
> id, so this patch fixes to check proper pinmux id.

I can't see this patch on patchwork.

Best Regards,
Jaehoon Chung

> 
> Signed-off-by: Seung-Woo Kim 
> ---
>  drivers/mmc/s5p_sdhci.c |2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c
> index b329bef..ac737e0 100644
> --- a/drivers/mmc/s5p_sdhci.c
> +++ b/drivers/mmc/s5p_sdhci.c
> @@ -152,7 +152,7 @@ static int sdhci_get_config(const void *blob, int node, 
> struct sdhci_host *host)
>  
>   /* Get device id */
>   dev_id = pinmux_decode_periph_id(blob, node);
> - if (dev_id < PERIPH_ID_SDMMC0 && dev_id > PERIPH_ID_SDMMC3) {
> + if (dev_id < PERIPH_ID_SDMMC0 || dev_id > PERIPH_ID_SDMMC3) {
>   debug("MMC: Can't get device id\n");
>   return -EINVAL;
>   }
> 

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[U-Boot] [PATCH v2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

[Vignesh R]

According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
data interface writes until the last word of an indirect transfer
otherwise indirect writes is known to fails sometimes. So, make sure
that QSPI indirect writes are 32 bit sized except for the last write. If
the txbuf is unaligned then use bounce buffer to avoid data aborts.

So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER
for all boards that use Cadence QSPI driver.

[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf

Signed-off-by: Vignesh R 
---

v2:
 - Use bounce buffer
 - Link to v1: https://patchwork.ozlabs.org/patch/693069/

 drivers/spi/cadence_qspi_apb.c   | 26 --
 include/configs/k2g_evm.h|  1 +
 include/configs/socfpga_common.h |  1 +
 include/configs/stv0991.h|  1 +
 4 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index e285d3c1e761..6ce98acf747d 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -30,6 +30,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "cadence_qspi.h"
 
 #define CQSPI_REG_POLL_US  (1) /* 1us */
@@ -741,6 +742,17 @@ int cadence_qspi_apb_indirect_write_execute(struct 
cadence_spi_platdata *plat,
unsigned int remaining = n_tx;
unsigned int write_bytes;
int ret;
+   struct bounce_buffer bb;
+   u8 *bb_txbuf;
+
+   /*
+* Handle non-4-byte aligned accesses via bounce buffer to
+* avoid data abort.
+*/
+   ret = bounce_buffer_start(, (void *)txbuf, n_tx, GEN_BB_READ);
+   if (ret)
+   return ret;
+   bb_txbuf = bb.bounce_buffer;
 
/* Configure the indirect read transfer bytes */
writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
@@ -751,11 +763,11 @@ int cadence_qspi_apb_indirect_write_execute(struct 
cadence_spi_platdata *plat,
 
while (remaining > 0) {
write_bytes = remaining > page_size ? page_size : remaining;
-   /* Handle non-4-byte aligned access to avoid data abort. */
-   if (((uintptr_t)txbuf % 4) || (write_bytes % 4))
-   writesb(plat->ahbbase, txbuf, write_bytes);
-   else
-   writesl(plat->ahbbase, txbuf, write_bytes >> 2);
+   writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
+   if (write_bytes % 4)
+   writesb(plat->ahbbase,
+   bb_txbuf + rounddown(write_bytes, 4),
+   write_bytes % 4);
 
ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL,
   CQSPI_REG_SDRAMLEVEL_WR_MASK <<
@@ -765,7 +777,7 @@ int cadence_qspi_apb_indirect_write_execute(struct 
cadence_spi_platdata *plat,
goto failwr;
}
 
-   txbuf += write_bytes;
+   bb_txbuf += write_bytes;
remaining -= write_bytes;
}
 
@@ -776,6 +788,7 @@ int cadence_qspi_apb_indirect_write_execute(struct 
cadence_spi_platdata *plat,
printf("Indirect write completion error (%i)\n", ret);
goto failwr;
}
+   bounce_buffer_stop();
 
/* Clear indirect completion status */
writel(CQSPI_REG_INDIRECTWR_DONE_MASK,
@@ -786,6 +799,7 @@ failwr:
/* Cancel the indirect write */
writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
   plat->regbase + CQSPI_REG_INDIRECTWR);
+   bounce_buffer_stop();
return ret;
 }
 
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index a14544526c71..1d603e0c002f 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -79,6 +79,7 @@
 #define CONFIG_CADENCE_QSPI
 #define CONFIG_CQSPI_REF_CLK 38400
 #define CONFIG_CQSPI_DECODER 0x0
+#define CONFIG_BOUNCE_BUFFER
 #endif
 
 #endif /* __CONFIG_K2G_EVM_H */
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index d37e5958b586..2de57b063334 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -208,6 +208,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_CQSPI_REF_CLK   cm_get_qspi_controller_clk_hz()
 #endif
 #define CONFIG_CQSPI_DECODER   0
+#define CONFIG_BOUNCE_BUFFER
 
 /*
  * Designware SPI support
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index bfd1bd719285..09a3064bd6d6 100644
--- a/include/configs/stv0991.h
+++ b/include/configs/stv0991.h
@@ -74,6 +74,7 @@
 #ifdef CONFIG_OF_CONTROL   /* QSPI is controlled via DT */
 #define CONFIG_CQSPI_DECODER   0
 #define CONFIG_CQSPI_REF_CLK   ((30/4)/2)*1000*1000
+#define CONFIG_BOUNCE_BUFFER
 
 #endif
 
-- 
2.10.2

Re: [U-Boot] [PATCH u-boot 0/5] Aspeed I2C driver, using Driver Model.

[Heiko Schocher]

Hello Maxim,

Am 23.11.2016 um 17:40 schrieb Maxim Sloyko:

Sorry, this was by mistake, please ignore.


no problem at all!

bye,
Heiko



On Wed, Nov 23, 2016 at 4:28 AM, Heiko Schocher > wrote:

Hello Maxim,

Am 23.11.2016 um 00:56 schrieb max...@google.com :

From: Maxim Sloyko >

This series of patches is only meant for openbmc/u-boot tree.


If this series is not for U-Boot mainline, why do you post this patches
on the U-Boot Mailinglist?

bye,
Heiko

It adds basic support for aspeed i2c. Only single master
mode is supported with synchronous transfer.

The style is inconsistent with U-Boot style guide in few places,
but follows local style in those files.

Maxim Sloyko (5):
aspeed/g5: Device Tree for ast2500, copied from openbmc/linux 
(include
  file), plus minimal device tree configuration for ast2500 eval
  board.
aspeed: Fixed incosistency in some SCU registers naming.
aspeed: Added function to calculate APB Clock frequency.
aspeed: Added function to configure pins for I2C devices.
aspeed: I2C driver.

   arch/arm/dts/Makefile   |2 +
   arch/arm/dts/aspeed-g5-evb.dts  |   28 +
   arch/arm/dts/aspeed-g5.dtsi | 1278 
+++
   arch/arm/include/asm/arch-aspeed/ast_scu.h  |6 +
   arch/arm/include/asm/arch-aspeed/regs-scu.h |   73 +-
   arch/arm/mach-aspeed/ast-scu.c  |   41 +-
   drivers/i2c/Kconfig |7 +
   drivers/i2c/Makefile|1 +
   drivers/i2c/ast_i2c.c   |  305 +++
   drivers/i2c/ast_i2c.h   |  143 +++
   10 files changed, 1851 insertions(+), 33 deletions(-)
   create mode 100644 arch/arm/dts/aspeed-g5-evb.dts
   create mode 100644 arch/arm/dts/aspeed-g5.dtsi
   create mode 100644 drivers/i2c/ast_i2c.c
   create mode 100644 drivers/i2c/ast_i2c.h

--
2.8.0.rc3.226.g39d4020

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany




--
*M*axim *S*loyko


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Re: [U-Boot] [PATCH] common: image: Remove FIT header update from image post-processing

[Lokesh Vutla]

On Tuesday 22 November 2016 02:07 AM, Andrew F. Davis wrote:
> After an image is selected out of a FIT blob for further processing we
> run an optional, platform specific, post-processing function on this
> component. This post-processing may modify the position and size of the
> image, so after post-processing we update the location and size for this
> image in the FIT header. This can cause problems as the position of
> subsequent components in the FIT blob are only referenced by relative
> position to the end of the last component. When we resize or move a
> component the following components position will be calculated
> incorrectly. To fix this, we do not update the FIT header but instead
> only update our local understanding of the image data. This also allows
> us to re-run post-processing steps if needed.
> 
> Signed-off-by: Andrew F. Davis 
> Tested-by: Carlos Hernandez 

Reviewed-by: Lokesh Vutla 

Thanks and regards,
Lokesh

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Re: [U-Boot] [PATCH] image-fit: Fix compiling error caused by autoconf.h

[Alison Wang]

> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Thursday, November 24, 2016 3:09 AM
> To: u-boot@lists.denx.de
> Cc: york sun ; Alison Wang 
> Subject: [PATCH] image-fit: Fix compiling error caused by autoconf.h
> 
> Commit ec6617c3 includes autoconf.h in image-fit.c, causing conflict
> for board odroid-xu3 which overwrites CONFIG_SYS_BOARD in header
> file. Move the include higher and use linux/kconfig.h instead of
> generated/autoconf.h.
> 
> Signed-off-by: York Sun 
> CC: Alison Wang 
> ---
>  common/image-fit.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/common/image-fit.c b/common/image-fit.c
> index ea56d5b..9468e51 100644
> --- a/common/image-fit.c
> +++ b/common/image-fit.c
> @@ -14,6 +14,7 @@
>  #include 
>  #else
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -27,7 +28,6 @@ DECLARE_GLOBAL_DATA_PTR;
>  #include 
>  #include 
>  #include 
> -#include 
> 
> 
> /**
> ***/
>  /* New uImage format routines */

Reviewed-by: Alison Wang 

Thanks.

Best Regards,
Alison Wang
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Re: [U-Boot] [PATCH 05/24] SPL: tiny-printf: add "l" modifier

[Siarhei Siamashka]

On Sun, 20 Nov 2016 14:56:59 +
Andre Przywara  wrote:

> tiny-printf does not know about the "l" modifier so far, which breaks
> the crash dump on AArch64, because it uses %lx to print the registers.
> Add an easy way of handling longs correctly.

I can't help but notice that the changes of this kind are in a way
defeating the original purpose of tiny-printf. And it is surely not
the first patch adding features to tiny-printf. I guess, in the end
we may end up with a large and bloated printf implementation again :-)

A possible solution might be just a strict check when parsing format
modifiers and abort with an error message (yeah, this will introduce
some size increase, but hopefully the last one). This way we
acknowledge the fact that tiny-printf is a reduced incomplete
implementation, and that the callers need to take this into account.

As for the "l" modifier. How much does it add to the code size? IMHO
this information should be mentioned in the commit message. Can the
AArch64 crash dump code be modified to avoid using it? Or can we have
the "l" modifier supported on 64-bit platforms only?

> Signed-off-by: Andre Przywara 
> ---
>  lib/tiny-printf.c | 43 +--
>  1 file changed, 33 insertions(+), 10 deletions(-)
> 
> diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
> index 30ac759..b01099d 100644
> --- a/lib/tiny-printf.c
> +++ b/lib/tiny-printf.c
> @@ -38,8 +38,8 @@ static void out_dgt(struct printf_info *info, char dgt)
>   info->zs = 1;
>  }
>  
> -static void div_out(struct printf_info *info, unsigned int *num,
> - unsigned int div)
> +static void div_out(struct printf_info *info, unsigned long *num,
> + unsigned long div)
>  {
>   unsigned char dgt = 0;
>  
> @@ -56,9 +56,9 @@ int _vprintf(struct printf_info *info, const char *fmt, 
> va_list va)
>  {
>   char ch;
>   char *p;
> - unsigned int num;
> + unsigned long num;
>   char buf[12];
> - unsigned int div;
> + unsigned long div;
>  
>   while ((ch = *(fmt++))) {
>   if (ch != '%') {
> @@ -66,8 +66,12 @@ int _vprintf(struct printf_info *info, const char *fmt, 
> va_list va)
>   } else {
>   bool lz = false;
>   int width = 0;
> + bool islong = false;
>  
>   ch = *(fmt++);
> + if (ch == '-')
> + ch = *(fmt++);
> +
>   if (ch == '0') {
>   ch = *(fmt++);
>   lz = 1;
> @@ -80,6 +84,11 @@ int _vprintf(struct printf_info *info, const char *fmt, 
> va_list va)
>   ch = *fmt++;
>   }
>   }
> + if (ch == 'l') {
> + ch = *(fmt++);
> + islong = true;
> + }
> +
>   info->bf = buf;
>   p = info->bf;
>   info->zs = 0;
> @@ -89,24 +98,38 @@ int _vprintf(struct printf_info *info, const char *fmt, 
> va_list va)
>   goto abort;
>   case 'u':
>   case 'd':
> - num = va_arg(va, unsigned int);
> - if (ch == 'd' && (int)num < 0) {
> - num = -(int)num;
> + div = 10;
> + if (islong) {
> + num = va_arg(va, unsigned long);
> + if (sizeof(long) > 4)
> + div *= div * 10;
> + } else {
> + num = va_arg(va, unsigned int);
> + }
> +
> + if (ch == 'd' && (long)num < 0) {
> + num = -(long)num;
>   out(info, '-');
>   }
>   if (!num) {
>   out_dgt(info, 0);
>   } else {
> - for (div = 10; div; div /= 10)
> + for (; div; div /= 10)
>   div_out(info, , div);
>   }
>   break;
>   case 'x':
> - num = va_arg(va, unsigned int);
> + if (islong) {
> + num = va_arg(va, unsigned long);
> + div = 1UL << (sizeof(long) * 8 - 4);
> + } else {
> + 

Re: [U-Boot] [PATCH 02/24] sun6i: Restrict some register initialization to Allwinner A31 SoC

[Siarhei Siamashka]

On Sun, 20 Nov 2016 14:56:56 +
Andre Przywara  wrote:

> These days many Allwinner SoCs use clock_sun6i.c, although out of them
> only the (original sun6i) A31 has a second MBUS clock register.
> Also setting up the PRCM PLL_CTLR1 register to provide the proper voltage
> seems to be an A31-only feature as well.
> So restrict the initialization to this SoC only to avoid writing bogus
> values to (undefined) registers in other chips.
> 
> Signed-off-by: Andre Przywara 
> Reviewed-by: Alexander Graf 
> Reviewed-by: Chen-Yu Tsai 
> ---
>  arch/arm/mach-sunxi/clock_sun6i.c | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm/mach-sunxi/clock_sun6i.c 
> b/arch/arm/mach-sunxi/clock_sun6i.c
> index ed8cd9b..382fa94 100644
> --- a/arch/arm/mach-sunxi/clock_sun6i.c
> +++ b/arch/arm/mach-sunxi/clock_sun6i.c
> @@ -21,6 +21,8 @@ void clock_init_safe(void)
>  {
>   struct sunxi_ccm_reg * const ccm =
>   (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> +
> +#ifdef CONFIG_MACH_SUN6I
>   struct sunxi_prcm_reg * const prcm =
>   (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
>  
> @@ -31,6 +33,7 @@ void clock_init_safe(void)
>   PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
>   PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
>   clrbits_le32(>pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
> +#endif

PRCM is generally poorly documented, with its description sometimes
entirely missing from the Allwinner manuals (while it exists in the
hardware). But many SoC variants are sharing the same features and need
the same code. I can confirm that this code chunk is needed on my A31s
tablet (otherwise the system does not boot), so it was not entirely
useless.

What about the other SoC variants? For example, I can see that the
A23 manual documents this register in a roughly the same way as A31
(the PLLVDD voltage settings, etc.). But I don't have any A23 hardware
to test. Basically, are we sure that we will not break A23 support
with this commit?

If I understand it correctly, you primarily wanted to disable this
code on A64. But disabling it everywhere other than A31 may be a
bit too broad.

>  
>   clock_set_pll1(40800);
>  
> @@ -41,7 +44,9 @@ void clock_init_safe(void)
>   writel(AHB1_ABP1_DIV_DEFAULT, >ahb1_apb1_div);
>  
>   writel(MBUS_CLK_DEFAULT, >mbus0_clk_cfg);
> +#ifdef CONFIG_MACH_SUN6I
>   writel(MBUS_CLK_DEFAULT, >mbus1_clk_cfg);
> +#endif

We can change this to:

   if (IS_ENABLED(CONFIG_MACH_SUN6I))
   writel(MBUS_CLK_DEFAULT, >mbus1_clk_cfg);

This saves one line of code and also looks a bit less ugly.

-- 
Best regards,
Siarhei Siamashka
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Re: [U-Boot] [PATCH v3 1/6] drivers: usb: gadget: ether: adopt to usb driver model

[Simon Glass]

Hi Mugunthan,

On 20 November 2016 at 22:38, Mugunthan V N  wrote:
> Hi Simon,
>
> On Saturday 19 November 2016 01:04 AM, Simon Glass wrote:
>> Hi Mugunthan,
>>
>> On 17 November 2016 at 01:09, Mugunthan V N  wrote:
>>> Convert usb ether gadget to adopt usb driver model
>>>
>>> Signed-off-by: Mugunthan V N 
>>> Reviewed-by: Simon Glass 
>>
>> Sorry, but I'd like to 'un-review' this.
>>
>>> ---
>>>  drivers/usb/gadget/ether.c | 36 
>>>  1 file changed, 36 insertions(+)
>>>
>>> diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
>>> index 497b981129..9bc61186cf 100644
>>> --- a/drivers/usb/gadget/ether.c
>>> +++ b/drivers/usb/gadget/ether.c
>>> @@ -24,6 +24,10 @@
>>>  #include "gadget_chips.h"
>>>  #include "rndis.h"
>>>
>>> +#include 
>>> +#include 
>>> +#include 
>>> +
>>>  #define USB_NET_NAME "usb_ether"
>>>
>>>  #define atomic_read
>>> @@ -101,6 +105,9 @@ struct eth_dev {
>>> struct usb_gadget   *gadget;
>>> struct usb_request  *req;   /* for control responses */
>>> struct usb_request  *stat_req;  /* for cdc & rndis status */
>>> +#ifdef CONFIG_DM_USB
>>> +   struct udevice  *usb_udev;
>>> +#endif
>>>
>>> u8  config;
>>> struct usb_ep   *in_ep, *out_ep, *status_ep;
>>> @@ -2303,6 +2310,24 @@ fail:
>>>
>>>  
>>> /*-*/
>>>
>>> +#ifdef CONFIG_DM_USB
>>> +int dm_usb_init(struct eth_dev *e_dev)
>>> +{
>>> +   struct udevice *dev = NULL;
>>> +   int ret;
>>> +
>>> +   ret = uclass_first_device(UCLASS_USB_DEV_GENERIC, );
>>> +   if (!dev || ret) {
>>> +   error("No USB device found\n");
>>> +   return -ENODEV;
>>> +   }
>>> +
>>> +   e_dev->usb_udev = dev;
>>> +
>>> +   return ret;
>>> +}
>>> +#endif
>>> +
>>>  static int usb_eth_init(struct eth_device *netdev, bd_t *bd)
>>>  {
>>> struct eth_dev *dev = _ethdev;
>>> @@ -2315,7 +2340,14 @@ static int usb_eth_init(struct eth_device *netdev, 
>>> bd_t *bd)
>>> goto fail;
>>> }
>>>
>>> +#ifdef CONFIG_DM_USB
>>> +   if (dm_usb_init(dev)) {
>>> +   error("USB ether not found\n");
>>> +   return -ENODEV;
>>> +   }
>>> +#else
>>> board_usb_init(0, USB_INIT_DEVICE);
>>> +#endif
>>>
>>> /* Configure default mac-addresses for the USB ethernet device */
>>>  #ifdef CONFIG_USBNET_DEV_ADDR
>>> @@ -2497,7 +2529,11 @@ void usb_eth_halt(struct eth_device *netdev)
>>> }
>>>
>>> usb_gadget_unregister_driver(_driver);
>>> +#ifdef CONFIG_DM_USB
>>> +   device_remove(dev->usb_udev);
>>> +#else
>>> board_usb_cleanup(0, USB_INIT_DEVICE);
>>> +#endif
>>
>> This doesn't look right to me. If your board is to be an Ethernet
>> device then it should do:
>>
>> uclass_first_device(UCLASS_ETH, )
>>
>> to get the device. That could be in the device tree under the USB
>> node, or perhaps you want to have a setup function which manualy binds
>> the device, a bit like usb_find_and_bind_driver().
>>
>
> This patch is to get usb device for the ether gadget. It uses the same
> api with UCLASS_USB_DEV_GENERIC to get usb device. The patch hadn't done
> for eth driver model adoption.

So can you do that one first, or is it coming soon?

Regards,
Simon
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Re: [U-Boot] [PATCH v2 1/1] cmd: pci: add option to parse and display BAR information

[Simon Glass]

Hi,

On 22 November 2016 at 03:49, Yehuda Yitschak  wrote:
> Hi Simon
>
>> -Original Message-
>> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
>> Sent: Friday, November 11, 2016 18:17
>> To: Yehuda Yitschak
>> Cc: Bin Meng; Heiko Schocher; Przemyslaw Marczak; Stefan Roese; Stephen
>> Warren; U-Boot Mailing List
>> Subject: Re: [PATCH v2 1/1] cmd: pci: add option to parse and display BAR
>> information
>>
>> Hi,
>>
>> On 6 November 2016 at 07:31,   wrote:
>> > From: Yehuda Yitschak 
>> >
>> > Currently the PCI command only allows to see the BAR register values
>> > but not the size and actual base address.
>> > This little extension parses the BAR registers and displays the base,
>> > size and type of each BAR.
>> >
>> > Signed-off-by: Yehuda Yitschak 
>> > ---
>> >  cmd/pci.c | 95
>> >
>> ++
>> +
>> >  1 file changed, 95 insertions(+)
>>
>> Reviewed-by: Simon Glass 
[...]

>>
>> > +  bar_id, base, size, is_64 ? 64 : 32,
>> > +  is_io ? "I/O" : "MEM",
>> > +  prefetchable ? "Prefetchable" : "");
>>
>> Check with sandbox, this gives a warning:
>>
>> cmd/pci.c: In function ‘pci_bar_show’:
>> cmd/pci.c:175:11: warning: format ‘%llx’ expects argument of type ‘long long
>> unsigned int’, but argument 3 has type ‘u64’ [-Wformat=]
>>prefetchable ? "Prefetchable" : "");
>>^
>
> Strange, I can't see that.
> What compiler are you using when you get the warning ?
> I am using gcc-4.8 for armv8, maybe that's why I don't see the warnings
> I might come down to the built-in definition of __UINT64_TYPE__ which the 
> sandbox arch uses

This is sandbox, perhaps this:

gcc version 4.8.4 (Ubuntu 4.8.4-2ubuntu1~14.04.3)
[...]

Regards,
Simon
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Re: [U-Boot] [RFC PATCH 1/2] dm: Add support for scsi/sata based devices

[Simon Glass]

Hi Michal,

On 21 November 2016 at 12:36, Michal Simek  wrote:
> On 24.9.2016 19:26, Simon Glass wrote:
>> Hi Michal,
>>
>> On 8 September 2016 at 07:57, Michal Simek  wrote:
>>> All sata based drivers are bind and corresponding block
>>> device is created. Based on this find_scsi_device() is able
>>> to get back block device based on scsi_curr_dev pointer.
>>>
>>> intr_scsi() is commented now but it can be replaced by calling
>>> find_scsi_device() and scsi_scan().
>>>
>>> scsi_dev_desc[] is commented out but common/scsi.c heavily depends on
>>> it. That's why CONFIG_SYS_SCSI_MAX_DEVICE is hardcoded to 1 and symbol
>>> is reassigned to a block description allocated by uclass.
>>> There is only one block description by device now but it doesn't need to
>>> be correct when more devices are present.
>>>
>>> scsi_bind() ensures corresponding block device creation.
>>> uclass post_probe (scsi_post_probe()) is doing low level init.
>>>
>>> SCSI/SATA DM based drivers requires to have 64bit base address as
>>> the first entry in platform data structure to setup mmio_base.
>>>
>>> Signed-off-by: Michal Simek 
>>> ---
>>>
>>>  cmd/scsi.c  | 38 ++
>>>  common/board_r.c|  4 ++--
>>>  common/scsi.c   | 17 -
>>>  drivers/block/ahci-uclass.c | 38 ++
>>>  drivers/block/ahci.c| 30 ++
>>>  include/ahci.h  |  2 +-
>>>  include/sata.h  |  3 +++
>>>  include/scsi.h  | 15 ++-
>>>  8 files changed, 134 insertions(+), 13 deletions(-)
>>
>> Thanks for looking at this. I've taken a look and have a few comments.
>>
>> It's confusing that you are changing both scsi and sata. Do you need
>> to add a DM_SCSI also? As far as I can see, they are separate
>> subsystems.
>>
>> I think you need a uclass which implements the scsi_scan() function.
>> The existing code could be refactored so that the common parts are
>> called from both scsi.c and your scsi-uclass.c. It should look for
>> devices, and then create a block device for each. Since you don't know
>> how many block devices to create, I don't think you can avoid creating
>> them 'on the fly' in scsi_scan(). For an example, see
>> usb_stor_probe_device().
>
> Just a question about this. I have played with this and I haven't looked
> at usb (because I have usb ports gone on my development platform) but
> based on my understanding of our controller (ceva-sata) we support 2
> ports where each of them can have 2 different IDs and I am not quite
> sure about LUN but hardcoding it to 1 should be fine for now.
>
> But all this depends on controller setup. Number of ports should be
> possible to detect from every controller (0x0 offset - cap register 4:0
> number of ports NP).
>
> I have this code. What do you think about it?
> (There is missing loop over number of ports which I will add but
> unfortunately I don't have a HW with this setup here.

I think this is reasonable. Ideally you could avoid creating the block
device until you know it is OK, but failing that, make sure to unbind
it.

>
>  void scsi_scan(int mode)
>  {
> unsigned char i, lun;
> struct uclass *uc;
>  struct udevice *dev; /* SCSI controller */
> int ret;
>
> if (mode == 1)
> printf("scanning bus for devices...\n");
>
>  ret = uclass_get(UCLASS_SCSI, );
>  if (ret)
>  return;
>
>  uclass_foreach_dev(dev, uc) {
> struct scsi_platdata *plat; /* scsi controller platdata */
> struct blk_desc *bdesc; /* block device description */
> struct udevice *bdev; /* block device */
> struct udevice **devp;
> int dev_num = 0;
> int last_dev_num = -1;
>
> /* probe SCSI controller driver */
> ret = uclass_get_device_tail(dev, 0, devp);
> if (ret)
> return;
>
> /* Get controller platdata */
> plat = dev_get_platdata(dev);
>
> for (i = 0; i < plat->max_id; i++) {
> for (lun = 0; lun < plat->max_lun; lun++) {
> /*
>  * Create only one block device and do 
> detection
>  * to make sure that there won't be a lot of
>  * block devices created
>  */
> if (last_dev_num != dev_num) {
> char str[10];
> snprintf(str, sizeof(str), "lun%d", 
> lun);
> ret = blk_create_devicef(dev, 
> "scsi_blk", str, IF_TYPE_SCSI, -1, 512,
>  

Re: [U-Boot] New UCLASS_PINCTRL driver - probe is not called for all nodes

[Simon Glass]

Hi Konstantin,

On 20 November 2016 at 04:33, Konstantin Porotchkin  wrote:
> Hi, Simon,
>
> Thank you for your reply.
> In order to activate pin control function using "pinctrl-0" property, the
> device driver itself has to be aware of the pin control existence, right?
> So if I put such property under SPI controller, the SPI controller driver
> has to handle call to the pin control driver methods, right?

No, this happens automatically in device_probe().

>
> However my current target is to trigger setup for all existent pin
> controllers regardless of the connected device entries.
> Unfortunately not all drivers are aware of the pin controller properties.
> For instance current SPI and I2C drivers does not trigger the pin controller
> "probe" method regardless of the "pinctrl-0" property presence in FDT.

Provided they have the correct properties in the DT, this should work
without effort.

>
> Regards
> Konstantin
>
> On Fri, Nov 18, 2016 at 3:14 AM, Simon Glass  wrote:
>>
>> Hi Konstantin,
>>
>> On 15 November 2016 at 06:56, Konstantin Porotchkin 
>> wrote:
>> > Hi, All,
>> >
>> > I am currently porting the Marvell (mvebu) pin control driver for
>> > Armada-8K
>> > family  to the current u-boot sources.
>> > The Armada 8K SoC is a hybrid chip that contains several interconnected
>> > dies in a single package.
>> > Each such device (AP, CP0, CP1) has an independent pin controller with
>> > different memory mapping.
>> > The DTS for such configuration looks like the following:
>> > / {
>> > ap806 {
>> > config-space {
>> > pinctl: pinctl@6F4000 {
>> > ...
>> > };
>> > };
>> > };
>> > cp110-master {
>> > config-space {
>> > cpm_pinctl: pinctl@44000 {
>> > ...
>> > };
>> > };
>> > };
>> > cp110-slave {
>> > config-space {
>> > cps_pinctl: pinctl@44000 {
>> > ...
>> > };
>> > };
>> > };
>> > };
>> >
>> > I expect that my driver "probe" method will be called 3 times - one for
>> > every controller.
>> > However, according to my test, only the first controller is probed
>> > (pinctl@6F4000).
>> > Two others are listed in the DM tree, but are not active (not probed).
>> >
>> > I can do a trick and sequentially call uclass_get_device() function for
>> > the UCLASS_PINCTRL type, causing all 3 controller to be probed and
>> > activated.
>> > However I think this is not the way it should work.
>> > Is my assumption wrong and such hybrid devices should use the above
>> > trick
>> > for bringing up all controllers in the package?
>>
>> They should be activated automatically by devices that use them. This
>> is the pinctrl-0 property in the device. Can you take a look at why
>> that is not working?
>>
>> Specifically, see pinctrl_select_state() in device_probe().

Regards,
Simon
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Re: [U-Boot] [PATCH v2 10/22] spi: Add error checking for invalid bus widths

[Simon Glass]

Hi Jagan,

On 21 November 2016 at 10:57, Jagan Teki  wrote:
> On Sun, Nov 20, 2016 at 2:19 AM, Fabio Estevam  wrote:
>> On Sat, Nov 19, 2016 at 6:04 PM, Simon Glass  wrote:
>>
 EPROTONOSUPPORT means: /* Protocol not supported */, which does not
 seem to be very appropriate here.
>>>
>>> This is a protocol as far as I can see - you can either use one pin or
>>> four pins.
>>
>> Actually they are SPI modes: one, two or four pins.
>>
 Why not return -EINVAL instead?
>>>
>>> The value is valid but is not supported. If we just return -EINVAL for
>>> anything we don't like, it makes it harder to root-cause the error. In
>>> particular we use -EINVAL when decoding the device tree. But
>>> EPROTONOSUPPORT is not widely used.
>>
>> I think the current behaviour of not returning an error code on an
>> invalid mode is correct and it matches what the kernel does in
>> drivers/spi/spi.c.
>>
>> If an invalid mode is passed we just ignore it and operate in single
>> mode instead.
>>
>> Maybe we can make this clearer by printing a message like this:
>>
>> --- a/drivers/spi/spi-uclass.c
>> +++ b/drivers/spi/spi-uclass.c
>> @@ -408,7 +408,7 @@ int spi_slave_ofdata_to_platdata(const void *blob, int 
>> node,
>> mode |= SPI_TX_QUAD;
>> break;
>> default:
>> -   error("spi-tx-bus-width %d not supported\n", value);
>> +   printf("spi-tx-bus-width %d not supported, operating
>> in single mode\n", value);
>> break;
>> }
>>
>> @@ -423,7 +423,7 @@ int spi_slave_ofdata_to_platdata(const void *blob, int 
>> node,
>> mode |= SPI_RX_QUAD;
>> break;
>> default:
>> -   error("spi-rx-bus-width %d not supported\n", value);
>> +   printf("spi-rx-bus-width %d not supported, operating
>> in single mode\n", value);
>> break;
>
> Yes, this is what I am commenting about.
>
> -EINVAL not needed, we can print "%d is not supporting and operating
> in normal/single mode and move on", So-that the dts will fix if
> something went wrong.

Well if you add printf() values you will bloat the code for little
benefit. If the device tree is invalid it really should be fixed.

Regards,
Simon
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Re: [U-Boot] [RFC PATCH v2 7/7] env: Automatically mark dynamic configuration info as "do not export"

[Simon Glass]

Hi Bernhard,

On 22 November 2016 at 15:30, Bernhard Nortmann
 wrote:
> Hi Simon!
>
>
> Am 19.11.2016 um 14:47 schrieb Simon Glass:
>>
>> Hi Bernhard,
>>
>> On 16 November 2016 at 03:30, Bernhard Nortmann
>>  wrote:
>>>
>>> This is an attempt to prevent such information from ending up
>>> in exported environment data, especially when doing "saveenv".
>>> (http://lists.denx.de/pipermail/u-boot/2015-September/227611.html)
>>>
>>> The patch makes use of the new setenv_transient() helper for
>>> environment variables that get updated via network configuration:
>>> BOOTP/DHCP (netboot_update_env), CDP (cdp_update_env) and
>>> link-local protocol (do_link_local).
>>>
>>> Signed-off-by: Bernhard Nortmann 
>>> ---
>>>
>>> Changes in v2: None
>>>
>>>   cmd/net.c | 34 +-
>>>   1 file changed, 17 insertions(+), 17 deletions(-)
>>
>> Reviewed-by: Simon Glass 
>>
>> How would you make these variables non-transient? Does the transient
>> nature show up in 'printenv'?
>>
>> Regards,
>> Simon
>
>
> I think it's best to consider a practical example. I'm firing up my
> sunxi-based
> device with these patches applied on top of U-Boot v2016.11, and interrupt
> the
> autoboot.
>
> The standard way to examine variables that have non-default flags is the
> "env
> flags" command. In my case this outputs (discarding the explanations near
> the
> top):
>
> Static flags:
> Variable NameVariable TypeVariable Access
> -----
> eth\d?addr   MAC address  write-once
> ipaddr   IP address   any
> gatewayipIP address   any
> netmask  IP address   any
> serverip IP address   any
> nvlandecimal  any
> vlan decimal  any
> dnsipIP address   any
> serial#  string   write-once
> fel_booted   boolean  system
> fel_scriptaddr   hexadecimal  system
>
> Active flags:
> Variable NameVariable TypeVariable Access
> -----
> serial#  string   write-once
> ethaddr  MAC address  write-once
> fel_booted   boolean  system
>
> As you can see, patch 5/7 has sneaked in two new "system" flags and since
> I've
> booted using the FEL mechanism, the "fel_booted" one is in effect
> ("active").
>
> Okay, now I use the command "setenv autoload no; dhcp" to auto-configure
> networking. Let's check "env flags" again. The "Static flags" section is
> unchanged, but at the bottom there's now:
>
> Active flags:
> Variable NameVariable TypeVariable Access
> -----
> ipaddr   IP address   transient
> serial#  string   write-once
> hostname string   transient
> ethaddr  MAC address  write-once
> netmask  IP address   transient
> serverip IP address   transient
> fel_booted   boolean  system
> dnsipIP address   transient
> gatewayipIP address   transient
>
>>Does the transient nature show up in 'printenv'?
>
> No, it doesn't. "printenv" will give output that looks as usual / perfectly
> normal. You're also not restricted in modifying "transient" variables, for
> example I can do "ipaddr 10.11.12.13" with no problems.
>
> But: The differences will become apparent when trying to export the
> environment
> with something like "saveenv" or "env export":
> => env export 0x4000
> ## Don't export "ipaddr"
> ## Don't export "hostname"
> ## Don't export "netmask"
> ## Don't export "serverip"
> ## Don't export "fel_booted"
> ## Don't export "dnsip"
> ## Don't export "gatewayip"
>
> U-Boot refuses to store the 'volatile' information for those variables that
> have been flagged accordingly, and informs the user about it. This is
> checked
> individually per variable, i.e. the other ones will get exported normally.
>
> At this point I decide that I want to set up a *static* IP configuration and
> make it persistent with "saveenv". Houston, we have a problem!
>
>>How would you make these variables non-transient?
>
> Well, again there's a standard U-Boot mechanism for this. The README
> mentions
> it in the description of CONFIG_ENV_FLAGS_LIST_STATIC: "To override a
> setting
> in the static list, simply add an entry for the same variable name to the
> 

Re: [U-Boot] [RFC PATCH v1 3/3] sandbox: GPT over MTD test

[Simon Glass]

On 22 November 2016 at 02:46, Patrick Delaunay
 wrote:
> From: Patrick Delaunay 
>
> activate needed feature in sandbox to allow test GPT over MTD
> - EFI_PARTITION_MTD
> - SPI_FLASH_MTD
> - CMD_MTDPARTS
> - MTD_PARTITIONS
> - MTD_DEVICE
>
> activate 2 features useful for test
> - RANDOM_UUID
> - PARTITION_TYPE_GUID
>
> Signed-off-by: Patrick Delaunay 
> Signed-off-by: Patrick Delaunay 
> ---
>
>  configs/sandbox_defconfig | 2 ++
>  include/configs/sandbox.h | 7 +++
>  2 files changed, 9 insertions(+)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH RESEND 7/9] video: Allow board hook before video init

[Simon Glass]

Hi Maxime,

On 22 November 2016 at 05:41, Maxime Ripard
 wrote:
> Hi Simon,
>
> On Mon, Nov 14, 2016 at 01:44:45PM -0700, Simon Glass wrote:
>> Hi Maxime,
>>
>> On 14 November 2016 at 13:24, Maxime Ripard
>>  wrote:
>> > Hi Simon,
>> >
>> > On Fri, Nov 11, 2016 at 09:17:28AM -0700, Simon Glass wrote:
>> >> Hi Maxime,
>> >>
>> >> On 8 November 2016 at 03:19, Maxime Ripard
>> >>  wrote:
>> >> > Some boards might need to some additional setup right before 
>> >> > initialising
>> >> > the video console.
>> >> >
>> >> > Add some hook to allow that.
>> >>
>> >> Instead of this, can you use driver model (UCLASS_VIDEO)?
>> >
>> > I don't really know the device model that well, hence 'm not really
>> > sure how would that help. Can a board register a hook to be called
>> > before a driver is probed?
>>
>> My suggest would be that the driver can do whatever is required. What
>> is the board-specific code actually wanting to do?
>
> We need to adjust the video-mode environment variable that is going to
> be used in the driver's initialisation. We're doing that by
> identifying which daughter board is attached, and then setting that
> value according to the display output we want to use.
>
> So we need some hook that would run between the environment
> initialisation and the video driver's init.

As an example of how you might pass platform data to the video driver,
see board_init() in gurnard.c.

Regards,
Simon
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Re: [U-Boot] [Resend RFC PATCH v1 1/3] add support of GPT partitioning over MTD

[Simon Glass]

Hi Patrick,

On 22 November 2016 at 06:24, Patrick Delaunay
 wrote:
> From: Patrick Delaunay 
>
> Signed-off-by: Patrick Delaunay 
> Signed-off-by: Patrick Delaunay 
> ---
>
>  Kconfig|  12 ++
>  cmd/gpt.c  |  98 --
>  cmd/mtdparts.c | 103 ++-
>  cmd/part.c |  48 -
>  disk/part_efi.c| 526 
> -
>  doc/README.gpt.mtd | 189 +++
>  include/part.h |  13 +-
>  include/uuid.h |   1 +
>  lib/uuid.c |  33 
>  9 files changed, 944 insertions(+), 79 deletions(-)
>  create mode 100644 doc/README.gpt.mtd

General comments:

- use 'U-Boot' consistently rather than variations
- can you split your large function up a bit?
- can you make a precursor patch to refactor things, so reducing the
size of this one?
- nice README!

>
> diff --git a/Kconfig b/Kconfig
> index 1263d0b..c2388e1 100644
> --- a/Kconfig
> +++ b/Kconfig
> @@ -335,6 +335,18 @@ config ARCH_FIXUP_FDT
>
>  endmenu# Boot images
>
> +config EFI_PARTITION_MTD
> +   bool "Support GPT over MTD"
> +   help
> + The GPT partition is normally defined only for block device with
> + built-in controller which manage flash translation layer
> + This option activate the GPT partition support over RAW device
> + using the MTD framework
> + - manage partition over MTD devices (as flash: NOR and NAND)
> + - extract MTD information
> + - update command gpt, mtdparts and part
> + NB: depends on EFI_PARTITION

So do you want 'depends on EFI_PARTITION'?

Regards,
Simon
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Re: [U-Boot] [PATCH] common: image: Remove FIT header update from image post-processing

[Simon Glass]

On 21 November 2016 at 13:37, Andrew F. Davis  wrote:
> After an image is selected out of a FIT blob for further processing we
> run an optional, platform specific, post-processing function on this
> component. This post-processing may modify the position and size of the
> image, so after post-processing we update the location and size for this
> image in the FIT header. This can cause problems as the position of
> subsequent components in the FIT blob are only referenced by relative
> position to the end of the last component. When we resize or move a
> component the following components position will be calculated
> incorrectly. To fix this, we do not update the FIT header but instead
> only update our local understanding of the image data. This also allows
> us to re-run post-processing steps if needed.
>
> Signed-off-by: Andrew F. Davis 
> Tested-by: Carlos Hernandez 
> ---
>  common/image-fit.c | 29 ++---
>  1 file changed, 6 insertions(+), 23 deletions(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 2/3] image: Add Trusted Execution Environment image type

[Simon Glass]

On 21 November 2016 at 13:14, Andrew F. Davis  wrote:
> Add a new image type representing Trusted Execution Environment (TEE)
> image types. For example, an OP-TEE OS binary image.
>
> Signed-off-by: Andrew F. Davis 
> ---
>  common/image.c  | 1 +
>  include/image.h | 1 +
>  2 files changed, 2 insertions(+)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 3/3] RFC: board: ti: dra7xx: add FIT image TEE processing

[Simon Glass]

On 21 November 2016 at 13:14, Andrew F. Davis  wrote:
> Populate the corresponding TEE image processing call to be
> performed during FIT loadable processing.
>
> Signed-off-by: Andrew F. Davis 
> ---
>  board/ti/dra7xx/evm.c | 7 +++
>  1 file changed, 7 insertions(+)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCHv3 09/15] pci: layerscape: add pci driver based on DM

[Simon Glass]

Hi,

On 22 November 2016 at 02:25, Z.Q. Hou  wrote:
> Hi Simon,
>
> Sorry for my delay respond due to out of the office several days, and thanks 
> a lot for your comments!
>
>> -Original Message-
>> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
>> Sent: 2016年11月18日 9:15
>> To: Z.Q. Hou 
>> Cc: U-Boot Mailing List ; Albert ARIBAUD
>> ; Prabhakar Kushwaha
>> ; Huan Wang-B18965
>> ; Sumit Garg ; Ruchika
>> Gupta ; Saksham Jain
>> ; york sun ; M.H. Lian
>> ; Bin Meng ; Mingkai Hu
>> 
>> Subject: Re: [PATCHv3 09/15] pci: layerscape: add pci driver based on DM
>>
>> Hi,
>>
>> On 16 November 2016 at 02:48, Zhiqiang Hou 
>> wrote:
>> > From: Minghuan Lian 
>> >
>> > There are more than five kinds of Layerscape SoCs. unfortunately, PCIe
>> > controller of each SoC is a little bit different. In order to avoid
>> > too many macro definitions, the patch addes a new implementation of
>> > PCIe driver based on DM. PCIe dts node is used to describe the
>> > difference.
>> >
>> > Signed-off-by: Minghuan Lian 
>> > Signed-off-by: Hou Zhiqiang 
>> > ---
>> > V3:
>> >  - No change
>> >
>> >  drivers/pci/Kconfig   |   8 +
>> >  drivers/pci/pcie_layerscape.c | 761
>> > ++
>> >  2 files changed, 769 insertions(+)
>> >

>> > +#ifdef CONFIG_FSL_LSCH3
>>
>> Can this be a run-time check?
>
> No, it is for Linux DT fixup and these functions is needed only by FSL_LSCH3 
> SoCs.

I mean that you cannot have an #ifdef in a driver - it should be done
at run-time by looking at the compatible strings.

>
>>
>> > +/*
>> > + * Return next available LUT index.
>> > + */
>> > +static int ls_pcie_next_lut_index(struct ls_pcie *pcie) {
>> > +   if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
>> > +   return pcie->next_lut_index++;
>> > +   else
>> > +   return -1;  /* LUT is full */
>>
>> -ENOSPC?
>
> Yes, ENOSPC is more reasonable.
>
>>
>> > +}
>> > +
>> > +/*
>> > + * Program a single LUT entry
>> > + */
>> > +static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32
>> devid,
>> > +   u32 streamid) {
>> > +   /* leave mask as all zeroes, want to match all bits */
>> > +   lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
>> > +   lut_writel(pcie, streamid | PCIE_LUT_ENABLE,
>> > +PCIE_LUT_LDR(index)); }
>> > +
>> > +/* returns the next available streamid */ static u32
>> > +ls_pcie_next_streamid(void) {
>> > +   static int next_stream_id = FSL_PEX_STREAM_ID_START;
>> > +
>> > +   if (next_stream_id > FSL_PEX_STREAM_ID_END)
>> > +   return 0x;
>>
>> Is FSL_PEX_STREAM_ID_END the maximum value, or the number of values?
>
> The maximum value for PCIe.
>
>> > +
>> > +   return next_stream_id++;
>> > +}
>> > +
>> > +/*
>> > + * An msi-map is a property to be added to the pci controller
>> > + * node.  It is a table, where each entry consists of 4 fields
>> > + * e.g.:
>> > + *
>> > + *  msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
>> > + * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
>> > + */
>> > +static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
>> > +  u32 devid, u32 streamid) {
>> > +   u32 *prop;
>> > +   u32 phandle;
>> > +   int nodeoffset;
>> > +
>> > +   /* find pci controller node */
>> > +   nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
>> > +
>> > + pcie->dbi_res.start);
>>
>> At this point I'm a bit lost, but if this is using driver model, you can use
>> dev->of_offset
>
> This function is used to fixup Linux Kernel DT instead of u-boot DT.

They should use the same DT.

>
>>
>> > +   if (nodeoffset < 0) {
>> > +   #ifdef FSL_PCIE_COMPAT /* Compatible with older version of dts
>> > + node */
>>
>> Eek! Can't you detect this at run-time?
>>
>
> No, it's Kernel DT fixup, we plan to refactor Layerscape PCIe Linux driver 
> using the compatible "fsl,ls-pcie",
> but for now the macro FSL_PCIE_COMPAT must be defined to fixup Linux DT.

I'm still confused by this. I don't see it defined anywhere and it is
not a CONFIG. Can you not detect at run-time when you need to do the
fix-up?

>
>> > +   nodeoffset = fdt_node_offset_by_compat_reg(blob,
>> > +
>> FSL_PCIE_COMPAT,
>> > +
>> pcie->dbi_res.start);
>> > +   if (nodeoffset < 0)
>> > +   return;
>> > +   #else
>> > +   return;
>> > +   #endif
>> > +   }
>> > +
>> > +   /* get phandle 

Re: [U-Boot] [PATCH 1/3] image: Add FIT image loadable section custom processing

[Simon Glass]

Hi Andrew,

On 21 November 2016 at 13:14, Andrew F. Davis  wrote:
> To help automate the loading of custom image types we add the ability
> to define custom handlers for the loadable section types. When we find
> a compatible type while loading a "loadable" image from a FIT image we
> run its associated handlers to perform any additional steps needed for
> loading this image.
>
> Signed-off-by: Andrew F. Davis 
> ---
>  common/image.c  | 33 +
>  include/image.h | 11 +++
>  2 files changed, 44 insertions(+)

Reviewed-by: Simon Glass 

But please comment U_BOOT_FIT_LOADABLE_HANDLER and its associated struct.

Also can you add some documentation somewhere? Perhaps to
source_file_format.txt?

Regards,
Simon
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Re: [U-Boot] [PATCH] sata: fix sata command can not being executed bug

[Simon Glass]

On 20 November 2016 at 19:24,   wrote:
> From: Tang Yuantian 
>
> Commit d97dc8a0 separated the non-command code into its own file
> which caused variable sata_curr_device can not be set to a correct
> value.
>
> Before commit d97dc8a0, variable sata_curr_device can be set
> correctly in sata_initialize().
> After commit d97dc8a0, sata_initialize() is moved out to its own file.
> Accordingly, variable sata_curr_device is removed from sata_initialize()
> too. This caused sata_curr_device never gets a chance to be set properly
> which prevent other commands from being executed.
>
> This patch sets variable sata_curr_device properly.
>
> Fixes: d97dc8a0 (dm: sata: Separate the non-command code into its
>  own file)
>
> Signed-off-by: Tang Yuantian 
> ---
> v3:
>   - refine the commit message
> v2:
>   - refined this patch and updated the commit title and message
>
>  cmd/sata.c| 9 ++---
>  common/sata.c | 8 +---
>  2 files changed, 11 insertions(+), 6 deletions(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH] splash: add support for loading splash from a FIT image

[Simon Glass]

Hi Tomas,

On 21 November 2016 at 01:27, Tomas Melin  wrote:
> Enable support for loading a splash image from within a FIT image.
> The image is assumed to be generated with mkimage -E flag to hold
> the data external to the FIT.
>
> Signed-off-by: Tomas Melin 
> ---
>  common/splash_source.c | 73 
> ++
>  include/splash.h   |  1 +
>  2 files changed, 74 insertions(+)
>
> diff --git a/common/splash_source.c b/common/splash_source.c
> index 72df2c1..d72aee1 100644
> --- a/common/splash_source.c
> +++ b/common/splash_source.c
> @@ -16,6 +16,7 @@
>  #include 
>  #include 
>  #include 
> +#include 

Can you please add a new patch to sort the includes?

http://www.denx.de/wiki/U-Boot/CodingStyle

>
>  DECLARE_GLOBAL_DATA_PTR;
>
> @@ -295,6 +296,74 @@ static struct splash_location *select_splash_location(
> return NULL;
>  }
>
> +#ifdef CONFIG_FIT
> +static int splash_load_fit(struct splash_location *location, u32 
> bmp_load_addr)

Is it possible to use fit_image_load() here instead of writing a new
function? I suppose not, since you need to load the data from an
external source. Can we at least put the code to read the details into
image.c, in a new function? Then this file can call it - it can return
a struct with the info, or a few parameters, perhaps.

Also please see spl_load_simple_fit() where you might find some common code.

> +{
> +   int res;
> +   int node_offset;
> +   int splash_offset;
> +   int splash_size;
> +   const fdt32_t *val;
> +   struct image_header *img_header;
> +   const u32 *fit_header;
> +   u32 fit_size;
> +   const size_t header_size = sizeof(struct image_header);
> +
> +   /* Read in image header */
> +   res = splash_storage_read_raw(location, bmp_load_addr, header_size);
> +   if (res < 0)
> +   return res;
> +
> +   img_header = (struct image_header*)bmp_load_addr;
> +   fit_size = fdt_totalsize(img_header);
> +
> +   fit_header = (const u32*)(bmp_load_addr + header_size);
> +   /* Read in entire FIT */
> +   res = splash_storage_read_raw(location, (u32)fit_header, fit_size);
> +   if (res < 0)
> +   return res;
> +
> +   res = fit_check_format(fit_header);
> +   if (!res) {
> +   printf("Could not find valid FIT-image\n");
> +   return -EINVAL;
> +   }
> +
> +   node_offset = fit_image_get_node(fit_header, location->name);
> +   if (node_offset < 0) {
> +   printf("Could not find splash image '%s' in FIT\n",
> +  location->name);
> +   return -ENOENT;
> +   }
> +
> +   val = fdt_getprop(fit_header, node_offset, "data-offset", NULL);
> +   if (!val) {
> +   printf("Could not find 'data-offset' property in FIT\n");
> +   return -ENOENT;
> +   }
> +   splash_offset = fdt32_to_cpu(*val);
> +
> +   val = fdt_getprop(fit_header, node_offset, "data-size", NULL);
> +   if (!val) {
> +   printf("Could not find 'data-size' property in FIT\n");
> +   return -ENOENT;
> +   }
> +   splash_size = fdt32_to_cpu(*val);
> +
> +   /* Align data offset to 4-byte boundrary */
> +   fit_size = fdt_totalsize(fit_header);
> +   fit_size = (fit_size + 3) & ~3;
> +
> +   /* Read in the splash data */
> +   location->offset = (location->offset + fit_size + splash_offset);
> +   res = splash_storage_read_raw(location, bmp_load_addr , splash_size);
> +   if (res < 0)
> +   return res;
> +
> +   return 0;
> +}
> +#endif /* CONFIG_FIT */
> +
>  /**
>   * splash_source_load - load splash image from a supported location.
>   *
> @@ -331,5 +400,9 @@ int splash_source_load(struct splash_location *locations, 
> uint size)
> return splash_load_raw(splash_location, bmp_load_addr);
> else if (splash_location->flags == SPLASH_STORAGE_FS)
> return splash_load_fs(splash_location, bmp_load_addr);
> +#ifdef CONFIG_FIT
> +   else if (splash_location->flags == SPLASH_STORAGE_FIT)
> +   return splash_load_fit(splash_location, bmp_load_addr);
> +#endif
> return -EINVAL;
>  }
> diff --git a/include/splash.h b/include/splash.h
> index 136eac7..af4e61f 100644
> --- a/include/splash.h
> +++ b/include/splash.h
> @@ -35,6 +35,7 @@ enum splash_storage {
>  enum splash_flags {
> SPLASH_STORAGE_RAW,
> SPLASH_STORAGE_FS,
> +   SPLASH_STORAGE_FIT,
>  };

Can you comment that enum please?

>
>  struct splash_location {
> --
> 2.1.4
>

Regards,
Simon
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Re: [U-Boot] [PATCH 3/6] arm64: mvebu: pinctrl: Add pin control driver for A8K family

[Simon Glass]

Hi,

On 20 November 2016 at 08:38,   wrote:
> From: Konstantin Porotchkin 
>
> Add a port of Marvell pin control driver.
> The A8K SoC family contains several silicone dies interconnected
> in a single package. Every die is normally equuipped with its own
> pin controller unit.
> Since the UCLASS_PINCTRL device only calls the probe method for
> the first detected pin controller, a trick similar to used with
> comphy driver is required.
> In order to bring up all pin controllers available in A8K SoC,
> the arch_early_init_r() function sequentially calls the
> uclass_get_device() function for each UCLASS_PINCTRL device.
>
> Change-Id: Iff143827e8f1558a554d77173562c4b52ce179d7
> Signed-off-by: Konstantin Porotchkin 
> Cc: Simon Glass 
> Cc: Stefan Roese 
> Cc: Nadav Haklai 
> Cc: Neta Zur Hershkovits 
> Cc: Omri Itach 
> Cc: Igal Liberman 
> Cc: Haim Boot 
> Cc: Hanna Hawa 
> ---
>  arch/arm/include/asm/arch-armada8k/soc-info.h  |  45 +
>  arch/arm/mach-mvebu/arm64-common.c |   1 -
>  .../pinctrl/marvell,mvebu-pinctrl.txt  | 113 
>  drivers/pinctrl/Kconfig|   1 +
>  drivers/pinctrl/Makefile   |   1 +
>  drivers/pinctrl/mvebu/Kconfig  |   7 +
>  drivers/pinctrl/mvebu/Makefile |  17 ++
>  drivers/pinctrl/mvebu/pinctrl-mvebu.c  | 195 
> +
>  drivers/pinctrl/mvebu/pinctrl-mvebu.h  |  44 +
>  9 files changed, 423 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/include/asm/arch-armada8k/soc-info.h
>  create mode 100644 doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt
>  create mode 100644 drivers/pinctrl/mvebu/Kconfig
>  create mode 100644 drivers/pinctrl/mvebu/Makefile
>  create mode 100644 drivers/pinctrl/mvebu/pinctrl-mvebu.c
>  create mode 100644 drivers/pinctrl/mvebu/pinctrl-mvebu.h
>

Generally looks good but I have a load of nits sorry.

> diff --git a/arch/arm/include/asm/arch-armada8k/soc-info.h 
> b/arch/arm/include/asm/arch-armada8k/soc-info.h
> new file mode 100644
> index 000..4640deb
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-armada8k/soc-info.h
> @@ -0,0 +1,45 @@
> +/*
> + * 
> ***
> + * Copyright (C) 2015 Marvell International Ltd.
> + * 
> ***
> + * This program is free software: you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the Free
> + * Software Foundation, either version 2 of the License, or any later 
> version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see .
> + * 
> ***

Can you please use SPDX?

> + */
> +
> +#ifndef _SOC_INFO_H_
> +#define _SOC_INFO_H_
> +
> +/* General MPP definitions */
> +#define MAX_MPP_OPTS   7
> +#define MAX_MPP_ID 15
> +
> +#define MPP_BIT_CNT4
> +#define MPP_FIELD_MASK 0x7
> +#define MPP_FIELD_BITS 3
> +#define MPP_VAL_MASK   0xF
> +
> +#define MPPS_PER_REG   (32 / MPP_BIT_CNT)
> +#define MAX_MPP_REGS   ((MAX_MPP_ID + MPPS_PER_REG) / MPPS_PER_REG)
> +
> +/* MPP pins and functions correcsponding to UART RX connections
> +   This information is used for detection of recovery boot mode (boot from 
> UART) */

/*
 * MPP pins
 * ...
 * /

> +#define MPP_UART_RX_PINS   { 3, 5 }
> +#define MPP_UART_RX_FUNCTIONS  { 1, 2 }
> +
> +/* Pin Ctrl driver definitions */
> +#define BITS_PER_PIN   4
> +#define PIN_FUNC_MASK  ((1 << BITS_PER_PIN) - 1)
> +#define PIN_REG_SHIFT  3
> +#define PIN_FIELD_MASK ((1 << PIN_REG_SHIFT) - 1)
> +
> +#endif /* _SOC_INFO_H_ */
> diff --git a/arch/arm/mach-mvebu/arm64-common.c 
> b/arch/arm/mach-mvebu/arm64-common.c
> index 1fc2ff2..78fe7a7 100644
> --- a/arch/arm/mach-mvebu/arm64-common.c
> +++ b/arch/arm/mach-mvebu/arm64-common.c
> @@ -124,7 +124,6 @@ int arch_early_init_r(void)
> if (ret)
> break;
> }
> -

Unrelated change?

> /* Cause the SATA device to do its early init */
> uclass_first_device(UCLASS_AHCI, );
>
> diff --git a/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt 
> 

Re: [U-Boot] [PATCH v4 1/3] spl: add RAM boot device only if it is actually defined

[Simon Glass]

Hi Stefan,

On 21 November 2016 at 11:58, Stefan Agner  wrote:
> From: Stefan Agner 
>
> Some devices (e.g. dra7xx) support loading to RAM using DFU without
> having direct boot from RAM support. Make sure the linker list
> does not contain BOOT_DEVICE_RAM if CONFIG_SPL_RAM_DEVICE is not
> enabled.
>
> Fixes: 98136b2f26fa ("spl: Convert spl_ram_load_image() to use linker list")
>
> Signed-off-by: Stefan Agner 
> Acked-by: Lukasz Majewski 
> ---
>
> Changes in v4:
> - Use correct config CONFIG_SPL_RAM_DEVICE to descide whether to add
>   BOOT_DEVICE_RAM to linker list.
>
> Changes in v3: None
> Changes in v2:
> - Use CONFIG_SPL_RAM_SUPPORT to descide whether to compile the
>   function in first place.
>
>  common/spl/spl.c | 2 ++
>  1 file changed, 2 insertions(+)

Can you put this into a separate spl_ram.c file?

- Simon
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Re: [U-Boot] [PATCH 22/24] ARM: SPL/FIT: differentiate between arm and arm64 arch properties

[Simon Glass]

On 20 November 2016 at 07:57, Andre Przywara  wrote:
> Since the SPL FIT loader can now differentiate between different
> architectures, teach it how to tell arm and arm64 apart when a FIT
> image is used.
> We just support those two for now, as these are so far the only sensible
> alternatives.
>
> Signed-off-by: Andre Przywara 
> ---
>  arch/arm/lib/spl.c | 15 +++
>  1 file changed, 15 insertions(+)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 20/24] SPL: read and store arch property from U-Boot image

[Simon Glass]

On 20 November 2016 at 07:57, Andre Przywara  wrote:
> Read the specified "arch" value from a legacy or FIT U-Boot image and
> store it in our SPL data structure.
> This allows loaders to take the target architecture in account for
> custom loading procedures.
> Having the complete string -> arch mapping for FIT based images in the
> SPL would be too big, so we leave it up to architectures (or boards) to
> overwrite the weak function that does the actual translation, possibly
> covering only the required subset there.
> Document struct spl_image_info on the way.
>
> Signed-off-by: Andre Przywara 
>
> add a struct comment for spl_image_info
> ---
>  common/spl/spl.c |  1 +
>  common/spl/spl_fit.c |  8 
>  include/spl.h| 15 ++-
>  3 files changed, 23 insertions(+), 1 deletion(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] mmc: add bkops-enable command

[Jaehoon Chung]

Hi Tomas,

On 11/23/2016 09:50 PM, Tomas Melin wrote:
> Hi Jaehoon,
> 
> On 11/23/2016 11:53 AM, Jaehoon Chung wrote:
>> On 11/21/2016 04:52 PM, Tomas Melin wrote:
>>> Is your meaning by this that you think that the kernel driver 
>>> implementation is insufficient, and that you therefore do not recommmend 
>>> using bkops functionality for eMMC at all (ever)?
>>
>> No...If user really want to use this, they can use the mmc-utils..
> 
> Actually, I have also been using mmc-utils for this purpose, and even 
> provided patches upstream for the tool. It seems that all settings are not 
> really working properly. E.g. setting both hwpartition and write reliability 
> failes in some cases with our devices, the write reliability bit setting is 
> for some reason lost after the power cycle. The same problems have not be 
> noticed doing the same configurations from U-Boot.
> So doing the emmc setting seems more reliable in U-Boot.
> 
> Below v2 of the original patch that instead puts the command into a separate 
> CONFIG_CMD_BKOPS_ENABLE that must be enabled explicitly by
> the user if he or she wishes to use the command.
> I understand your standpoint and arguments for not providing the command in 
> U-Boot with default setting, but please still consider
> accepting it as a configurable command that can be pulled in by those users 
> who need it. Either way, we will
> keep it as a out-of-tree patch. But frankly, I think this command might be of 
> use to many others as well.

I understood what your purpose..Could you send the patch again?
After sending the patch V2 again, i will check again for satisfying both you 
and me. :)

> 
> BR, 
> Tomas
> 
> 
>>From 7387943be48e7ccc2bf6aa1d30d35ef279c98f2d Mon Sep 17 00:00:00 2001
> From: Tomas Melin 
> Date: Wed, 16 Nov 2016 09:10:02 +0200
> Subject: [PATCH] mmc: add bkops-enable command
> 
> Add new command that provides possibility to enable the
> background operations handshake functionality
> (BKOPS_EN, EXT_CSD byte [163]) on eMMC devices.
> 
> This is an optional feature of eMMCs, the setting is write-once.
> The command must be explicitly taken into use with
> CONFIG_CMD_BKOPS_ENABLE.
> 
> Signed-off-by: Tomas Melin 
> ---
>  cmd/Kconfig   |  7 +++
>  cmd/mmc.c | 32 
>  drivers/mmc/mmc.c | 32 
>  include/mmc.h |  6 ++
>  4 files changed, 77 insertions(+)
> 
> diff --git a/cmd/Kconfig b/cmd/Kconfig
> index e339d86..8286d15 100644
> --- a/cmd/Kconfig
> +++ b/cmd/Kconfig
> @@ -550,6 +550,13 @@ config SYS_AMBAPP_PRINT_ON_STARTUP
>   help
> Show AMBA Plug-n-Play information on startup.
>  
> +config CMD_BKOPS_ENABLE
> + bool "mmc bkops enable"
> + depends on CMD_MMC
> + default n
> + help
> +   Enable background operations handshake on device.
> +
>  config CMD_BLOCK_CACHE
>   bool "blkcache - control and stats for block cache"
>   depends on BLOCK_CACHE
> diff --git a/cmd/mmc.c b/cmd/mmc.c
> index b2761e9..b8dcc26 100644
> --- a/cmd/mmc.c
> +++ b/cmd/mmc.c
> @@ -729,6 +729,31 @@ static int do_mmc_setdsr(cmd_tbl_t *cmdtp, int flag,
>   return ret;
>  }
>  
> +#ifdef CONFIG_CMD_BKOPS_ENABLE
> +static int do_mmc_bkops_enable(cmd_tbl_t *cmdtp, int flag,
> +int argc, char * const argv[])
> +{
> + int dev;
> + struct mmc *mmc;
> +
> + if (argc != 2)
> + return CMD_RET_USAGE;
> +
> + dev = simple_strtoul(argv[1], NULL, 10);
> +
> + mmc = init_mmc_device(dev, false);
> + if (!mmc)
> + return CMD_RET_FAILURE;
> +
> + if (IS_SD(mmc)) {
> + puts("BKOPS_EN only exists on eMMC\n");
> + return CMD_RET_FAILURE;
> + }
> +
> + return mmc_set_bkops_enable(mmc);
> +}
> +#endif
> +
>  static cmd_tbl_t cmd_mmc[] = {
>   U_BOOT_CMD_MKENT(info, 1, 0, do_mmcinfo, "", ""),
>   U_BOOT_CMD_MKENT(read, 4, 1, do_mmc_read, "", ""),
> @@ -749,6 +774,9 @@ static cmd_tbl_t cmd_mmc[] = {
>   U_BOOT_CMD_MKENT(rpmb, CONFIG_SYS_MAXARGS, 1, do_mmcrpmb, "", ""),
>  #endif
>   U_BOOT_CMD_MKENT(setdsr, 2, 0, do_mmc_setdsr, "", ""),
> +#ifdef CONFIG_CMD_BKOPS_ENABLE
> + U_BOOT_CMD_MKENT(bkops-enable, 2, 0, do_mmc_bkops_enable, "", ""),
> +#endif
>  };
>  
>  static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const 
> argv[])
> @@ -813,6 +841,10 @@ U_BOOT_CMD(
>   "mmc rpmb counter - read the value of the write counter\n"
>  #endif
>   "mmc setdsr  - set DSR register value\n"
> +#ifdef CONFIG_CMD_BKOPS_ENABLE
> + "mmc bkops-enable  - enable background operations handshake on 
> device\n"
> + "   WARNING: This is a write-once setting.\n"

"Write-once setting" -> "Onetime programmable"

> +#endif
>   );
>  
>  /* Old command kept for compatibility. Same as 'mmc info' */
> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
> index 0cec02c..d40d13f 100644
> --- 

Re: [U-Boot] [PATCH v2 5/7] ARM: stm32: enable support for smsc phy on stm32f746-disco board

[Vikas MANOCHA]

Hi,

> -Original Message-
> From: Michael Kurz [mailto:michi.k...@gmail.com]
> Sent: Friday, November 04, 2016 12:21 PM
> To: u-boot@lists.denx.de
> Cc: Michael Kurz ; Albert Aribaud 
> ; Vikas MANOCHA 
> Subject: [PATCH v2 5/7] ARM: stm32: enable support for smsc phy on 
> stm32f746-disco board
> 
> This patch enables support for the smsc phy on the stm32f746-disco board.
> 
> Signed-off-by: Michael Kurz 
> ---
> 
> Changes in v2: None
> 
>  include/configs/stm32f746-disco.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/include/configs/stm32f746-disco.h 
> b/include/configs/stm32f746-disco.h
> index 4088064..246cc2e 100644
> --- a/include/configs/stm32f746-disco.h
> +++ b/include/configs/stm32f746-disco.h
> @@ -46,6 +46,7 @@
>  #define CONFIG_DW_GMAC_DEFAULT_DMA_PBL   (8)
>  #define CONFIG_DW_ALTDESCRIPTOR
>  #define CONFIG_MII
> +#define CONFIG_PHY_SMSC
> 
>  #define CONFIG_STM32_HSE_HZ  2500
>  #define CONFIG_SYS_CLK_FREQ  2 /* 200 MHz */
> --
> 2.1.4

Acked-by: Vikas MANOCHA 

Cheers,
Vikas

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Re: [U-Boot] [RFC PATCH 1/1] Read mmc device memory capacity from EXT_CSD if memory is addressed by sector

[Jaehoon Chung]

Hi Tomas,

On 11/23/2016 10:04 PM, Tomas Melin wrote:
> Hi,
> 
> We have successfully been using this patch to fix the problem mentioned in the
> original message. Could this be picked up upstream?

Sorry. I didn't see this patch..Could you again send the patch without RFC?
Then it's helpful to me for checking this.

Best Regards,
Jaehoon Chung

> 
> BR,
> Tomas
> 
> On Wed Feb 5 21:00:42 CET 2014, Frank Bormann wrote:
>> Hello Everyone,
>>
>> I believe, there is a bug in the mmc driver code pertaining to how u-boot 
>> detects memory size of an mmc device. However, I am not 100% sure, my 
>> solution 
>> conforms to the JEDEC standard. So I am putting it up for discussion.
>>
>> Previously, sector count indicated by mmc devices in the EXT_CSD
>> would only be used in u-boot if the size indicated is greater than
>> 2 GB. This seems to be incorrect. I am working with a 4 GB Micron
>> eMMC device that after partition configuration and setting the
>> user data area to enhanced mode has a remaining capacity of less
>> than 2 GB for the user data area. JESD84-B50 explicitly states in
>> 6.2.4 that for these devices SEC_CNT from the EXT_CSD is still
>> valid even if the memory size for that device has dropped below
>> 2 GB by the partition configuration applied. The access mode bits
>>from the OCR register seem to provide a better way to decide
>> whether to use the CSD-based C_SIZE & C_MULT or the EXT_CSD-based
>> SEC_CNT information when determining the device's capacity.
>>
>> In particular, this fixes a bug where u-boot SPL would assign 0 to
>> mmc->block_dev.lba later on in the mmc_startup() function and
>> subsequently fail to load u-boot from that mmc due to the original
>> C_SIZE & C_MULT code assigning a 4 TB size to mmc->capacity, that
>> incorrect capacity never being overwritten by the SEC_CNT capacity
>> calculation (due to its size being less than 2 GB) and then finally
>> lldiv(mmc->capacity, mmc->read_bl_len) exceeding the 32-bit result
>> data type of mmc->block_dev.lba.
>>
>> Signed-off-by: Frank Bormann 
>> ---
>>  drivers/mmc/mmc.c |   10 +-
>>  include/mmc.h |1 +
>>  2 files changed, 6 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
>> index c6a1c23..c5d1efc 100644
>> --- a/drivers/mmc/mmc.c
>> +++ b/drivers/mmc/mmc.c
>> @@ -935,19 +935,19 @@ static int mmc_startup(struct mmc *mmc)
>> if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
>> /* check  ext_csd version and capacity */
>> err = mmc_send_ext_csd(mmc, ext_csd);
>> -   if (!err && (ext_csd[EXT_CSD_REV] >= 2)) {
>> +   if (!err && (ext_csd[EXT_CSD_REV] >= 2) &&
>> +   (mmc->ocr & OCR_ACCESS_MODE) == 
>> OCR_ACCESS_BY_SECTOR) {
>> /*
>>  * According to the JEDEC Standard, the value of
>> -* ext_csd's capacity is valid if the value is more
>> -* than 2GB
>> +* ext_csd's capacity is valid if the device 
>> addresses
>> +* its memory by sector
>>  */
>> capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
>> | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
>> | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
>> | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
>> capacity *= MMC_MAX_BLOCK_LEN;
>> -   if ((capacity >> 20) > 2 * 1024)
>> -   mmc->capacity_user = capacity;
>> +   mmc->capacity_user = capacity;
>> }
>>
>> switch (ext_csd[EXT_CSD_REV]) {
>> diff --git a/include/mmc.h b/include/mmc.h
>> index e1060b9..816b580 100644
>> --- a/include/mmc.h
>> +++ b/include/mmc.h
>> @@ -104,6 +104,7 @@
>>  #define OCR_HCS0x4000
>>  #define OCR_VOLTAGE_MASK   0x007FFF80
>>  #define OCR_ACCESS_MODE0x6000
>> +#define OCR_ACCESS_BY_SECTOR   (1 << 30)
>>
>>  #define SECURE_ERASE   0x8000
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> 
> 

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Re: [U-Boot] [PATCH 09/27] sh: Use asm-generic/io.h

[Vladimir Zapolskiy]

On 10/01/2016 05:19 PM, Paul Burton wrote:

Convert the sh architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As the generic implementations are
suitable for sh this is primarily a matter of moving code.


I'll try to find time and test this change on top of my fixes
during the weekend.


Feedback from architecture maintainers is welcome.


The unmodified U-boot from the last two releases can not run
on any SH board, you can consider that SH arch is unmaintained.


Signed-off-by: Paul Burton 
Cc: Nobuhiro Iwamatsu 
---


--
Best wishes,
Vladimir
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Re: [U-Boot] [PATCH v2 1/7] ARM: DTS: stm32: add stm32f746-disco device tree files

[Vikas MANOCHA]

Hi Michael,

> -Original Message-
> From: Michael Kurz [mailto:michi.k...@gmail.com]
> Sent: Friday, November 04, 2016 12:21 PM
> To: u-boot@lists.denx.de
> Cc: Michael Kurz ; Heiko Schocher ; Simon 
> Glass ; Masahiro Yamada
> ; York Sun ; Lokesh Vutla 
> ; Ian Campbell
> ; Hans de Goede ; Albert Aribaud 
> ; Vikas MANOCHA
> ; Stefan Roese ; Prabhakar Kushwaha 
> 
> Subject: [PATCH v2 1/7] ARM: DTS: stm32: add stm32f746-disco device tree files
> 
> This patch adds the DTS source files needed for stm32f746-disco board
> based on the stm32f429/469 files from current linux kernel.
> 
> Signed-off-by: Michael Kurz 
> ---
> 
> Changes in v2: None
> 
>  arch/arm/dts/Makefile   |2 +
>  arch/arm/dts/armv7-m.dtsi   |   24 +
>  arch/arm/dts/stm32f746-disco.dts|  154 +++
>  arch/arm/dts/stm32f746.dtsi |  397 +++
>  configs/stm32f746-disco_defconfig   |1 +
>  include/dt-bindings/pinctrl/stm32f746-pinfunc.h | 1324 
> +++
>  6 files changed, 1902 insertions(+)
>  create mode 100644 arch/arm/dts/armv7-m.dtsi
>  create mode 100644 arch/arm/dts/stm32f746-disco.dts
>  create mode 100644 arch/arm/dts/stm32f746.dtsi
>  create mode 100644 include/dt-bindings/pinctrl/stm32f746-pinfunc.h
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 836a8c4..0cb0d07 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -155,6 +155,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \

[...]

> +CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco"
>  CONFIG_BOOTDELAY=3
>  # CONFIG_DISPLAY_CPUINFO is not set
>  # CONFIG_DISPLAY_BOARDINFO is not set
> diff --git a/include/dt-bindings/pinctrl/stm32f746-pinfunc.h 
> b/include/dt-bindings/pinctrl/stm32f746-pinfunc.h
> new file mode 100644
> index 000..6348c6a
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/stm32f746-pinfunc.h
> @@ -0,0 +1,1324 @@

Split pin control in separate patch.

Otherwise,
Acked-by: Vikas MANOCHA 

> +#ifndef _DT_BINDINGS_STM32F746_PINFUNC_H
> +#define _DT_BINDINGS_STM32F746_PINFUNC_H
> +
> +#define STM32F746_PA0_FUNC_GPIO 0x0
> +#define STM32F746_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2

[...]

Cheers,
Vikas
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Re: [U-Boot] [PATCH v2 2/7] ARM: stm32: cleanup stm32f7 files

[Vikas MANOCHA]

Hi Michael,

> -Original Message-
> From: Michael Kurz [mailto:michi.k...@gmail.com]
> Sent: Friday, November 04, 2016 12:21 PM
> To: u-boot@lists.denx.de
> Cc: Michael Kurz ; Kamil Lulko ; 
> Toshifumi NISHINAGA
> ; Vadzim Dambrouski ; Albert 
> Aribaud ; Vikas
> MANOCHA ; Simon Glass 
> Subject: [PATCH v2 2/7] ARM: stm32: cleanup stm32f7 files
> 
> Cleanup stm32f7 files:
> - use BIT macro
> - use GENMASK macro
> - prefix all constants with STM32_

Adding no value to add this prefix.

> - remove double constants
> 
> Signed-off-by: Michael Kurz 
> 
> ---
> 
> Changes in v2:
> - add cleanup patch
> 
>  arch/arm/include/asm/arch-stm32f4/stm32.h|   2 +-
>  arch/arm/include/asm/arch-stm32f7/fmc.h  |   7 +-
>  arch/arm/include/asm/arch-stm32f7/gpt.h  |   9 +-
>  arch/arm/include/asm/arch-stm32f7/rcc.h  |  64 ---
>  arch/arm/include/asm/arch-stm32f7/stm32.h| 119 +---
>  arch/arm/include/asm/arch-stm32f7/stm32_periph.h |   3 +
>  arch/arm/mach-stm32/stm32f7/clock.c  | 227 
> ++-
>  arch/arm/mach-stm32/stm32f7/timer.c  |   4 +-
>  board/st/stm32f746-disco/stm32f746-disco.c   |  10 +-
>  drivers/mtd/stm32_flash.c|   2 +-
>  drivers/serial/serial_stm32x7.c  |   4 +-
>  11 files changed, 203 insertions(+), 248 deletions(-)  delete mode 100644 
> arch/arm/include/asm/arch-stm32f7/rcc.h
> 
> diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h 
> b/arch/arm/include/asm/arch-stm32f4/stm32.h
> index 6cc1966..b77345a 100644
> --- a/arch/arm/include/asm/arch-stm32f4/stm32.h
> +++ b/arch/arm/include/asm/arch-stm32f4/stm32.h
> @@ -102,7 +102,7 @@ struct stm32_pwr_regs {
>  #define STM32_USART3_BASE(STM32_APB1PERIPH_BASE + 0x4800)
>  #define STM32_USART6_BASE(STM32_APB2PERIPH_BASE + 0x1400)
> 
> -#define FLASH_CNTL_BASE  (STM32_AHB1PERIPH_BASE + 0x3C00)
> +#define STM32_FLASH_CNTL_BASE(STM32_AHB1PERIPH_BASE + 0x3C00)
> 
>  static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
>   [0 ... 3] = 16 * 1024,

[...]

> -#define RCC_ENR_GPIO_J_EN(1 << 9)
> -#define RCC_ENR_GPIO_K_EN(1 << 10)
> -
> -#endif

Not a good design to delete the reset and clock related stuff contained in one 
header and moving it to source file/stm32.c

> diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h 
> b/arch/arm/include/asm/arch-stm32f7/stm32.h
> index de55ae5..efc4fd7 100644
> --- a/arch/arm/include/asm/arch-stm32f7/stm32.h
> +++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
> @@ -9,46 +9,47 @@
>  #define _ASM_ARCH_HARDWARE_H
> 
>  /* STM32F746 */
> -#define ITCM_FLASH_BASE  0x0020UL
> -#define AXIM_FLASH_BASE  0x0800UL
> +#define STM32_ITCM_FLASH_BASE0x0020UL
> +#define STM32_AXIM_FLASH_BASE0x0800UL
> +
> +#define STM32_ITCM_SRAM_BASE 0xUL
> +#define STM32_DTCM_SRAM_BASE 0x2000UL
> +#define STM32_SRAM1_BASE 0x2001UL
> +#define STM32_SRAM2_BASE 0x2004C000UL
> +
> +#define STM32_PERIPH_BASE0x4000UL
> +
> +#define STM32_APB1_PERIPH_BASE   (STM32_PERIPH_BASE + 0x)
> +#define STM32_APB2_PERIPH_BASE   (STM32_PERIPH_BASE + 0x0001)
> +#define STM32_AHB1_PERIPH_BASE   (STM32_PERIPH_BASE + 0x0002)
> +#define STM32_AHB2_PERIPH_BASE   (STM32_PERIPH_BASE + 0x1000)
> +#define STM32_AHB3_PERIPH_BASE   (STM32_PERIPH_BASE + 0x2000)
> +
> +#define STM32_TIM2_BASE  (STM32_APB1_PERIPH_BASE + 0x)
> +#define STM32_USART2_BASE(STM32_APB1_PERIPH_BASE + 0x4400)
> +#define STM32_USART3_BASE(STM32_APB1_PERIPH_BASE + 0x4800)
> +#define STM32_PWR_BASE   (STM32_APB1_PERIPH_BASE + 0x7000)
> +
> +#define STM32_USART1_BASE(STM32_APB2_PERIPH_BASE + 0x1000)
> +#define STM32_USART6_BASE(STM32_APB2_PERIPH_BASE + 0x1400)
> +#define STM32_SYSCFG_BASE(STM32_APB2_PERIPH_BASE + 0x3800)
> +
> +#define STM32_GPIOA_BASE (STM32_AHB1_PERIPH_BASE + 0x)
> +#define STM32_GPIOB_BASE (STM32_AHB1_PERIPH_BASE + 0x0400)
> +#define STM32_GPIOC_BASE (STM32_AHB1_PERIPH_BASE + 0x0800)
> +#define STM32_GPIOD_BASE (STM32_AHB1_PERIPH_BASE + 0x0C00)
> +#define STM32_GPIOE_BASE (STM32_AHB1_PERIPH_BASE + 0x1000)
> +#define STM32_GPIOF_BASE (STM32_AHB1_PERIPH_BASE + 0x1400)
> +#define STM32_GPIOG_BASE (STM32_AHB1_PERIPH_BASE + 0x1800)
> +#define STM32_GPIOH_BASE (STM32_AHB1_PERIPH_BASE + 0x1C00)
> +#define STM32_GPIOI_BASE (STM32_AHB1_PERIPH_BASE + 0x2000)
> +#define STM32_GPIOJ_BASE (STM32_AHB1_PERIPH_BASE + 0x2400)
> +#define STM32_GPIOK_BASE (STM32_AHB1_PERIPH_BASE + 0x2800)
> +#define STM32_RCC_BASE   (STM32_AHB1_PERIPH_BASE + 0x3800)
> +#define STM32_FLASH_CNTL_BASE

Re: [U-Boot] [PATCH 08/24] armv8: add simple sdelay implementation

[Siarhei Siamashka]

On Mon, 21 Nov 2016 16:52:47 +0100
Alexander Graf  wrote:

> On 20/11/2016 15:57, Andre Przywara wrote:
> > The sunxi DRAM setup code needs an sdelay() implementation, which
> > wasn't defined for armv8 so far.
> > Shamelessly copy the armv7 version and adjust it to work in AArch64.
> >
> > Signed-off-by: Andre Przywara   
> 
> I don't think it hurts to write this in C - and I also doubt that 
> inlining has any negative effect.
> 
> Something along the lines of
> 
> static inline void sdelay(...) {
>for (; loops; loops--)
>  asm volatile("");
> }
> 
> inside a header should do the trick as well and is much more readable.

Unfortunately the performance of the generated C code is very
unpredictable. Depending on the optimization settings, it may
place the counter variable in a register, or keep it on stack.

It would be much nicer to have more predictable timings for
these delays. So I like the assembly version a lot better.
Naturally, when it is implemented correctly.

> 
> 
> Alex
> 
> > ---
> >  arch/arm/cpu/armv8/cpu.c | 13 +
> >  1 file changed, 13 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
> > index e06c3cc..e82e9cf 100644
> > --- a/arch/arm/cpu/armv8/cpu.c
> > +++ b/arch/arm/cpu/armv8/cpu.c
> > @@ -16,6 +16,19 @@
> >  #include 
> >  #include 
> >
> > +/
> > + * sdelay() - simple spin loop.  Will be constant time as
> > + *  its generally used in bypass conditions only.  This
> > + *  is necessary until timers are accessible.
> > + *
> > + *  not inline to increase chances its in cache when called
> > + */
> > +void sdelay(unsigned long loops)
> > +{
> > +   __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
> > + "b.ne 1b":"=r" (loops):"0"(loops));
> > +}
> > +
> >  int cleanup_before_linux(void)
> >  {
> > /*
> >  



-- 
Best regards,
Siarhei Siamashka
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Re: [U-Boot] [PATCH 08/24] armv8: add simple sdelay implementation

[André Przywara]

On 24/11/16 01:25, Siarhei Siamashka wrote:

Hi Siarhei,

> On Sun, 20 Nov 2016 14:57:02 +
> Andre Przywara  wrote:
> 
>> The sunxi DRAM setup code needs an sdelay() implementation, which
>> wasn't defined for armv8 so far.
>> Shamelessly copy the armv7 version and adjust it to work in AArch64.
>>
>> Signed-off-by: Andre Przywara 
>> ---
>>  arch/arm/cpu/armv8/cpu.c | 13 +
>>  1 file changed, 13 insertions(+)
>>
>> diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
>> index e06c3cc..e82e9cf 100644
>> --- a/arch/arm/cpu/armv8/cpu.c
>> +++ b/arch/arm/cpu/armv8/cpu.c
>> @@ -16,6 +16,19 @@
>>  #include 
>>  #include 
>>  
>> +/
>> + * sdelay() - simple spin loop.  Will be constant time as
>> + *  its generally used in bypass conditions only.  This
>> + *  is necessary until timers are accessible.
>> + *
>> + *  not inline to increase chances its in cache when called
>> + */
>> +void sdelay(unsigned long loops)
>> +{
>> +__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
>> +  "b.ne 1b":"=r" (loops):"0"(loops));
> 
> This inline assembly needs "cc" in the clobber list. Also don't we
> want to just use a single register for the counter ("subs %0, %0, #1")
> rather than trying to construct something excessively complicated
> and possibly fragile?

Please don't shoot the messenger, this is the version copied from ARMv7.
I noticed the redundant register as well, but didn't dare to touch it
(assuming some higher wisdom behind it).
And good catch for the cc clobber!

Cheers,
Andre.

> The https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html page provides
> some information.
> 
>> +}
>> +
>>  int cleanup_before_linux(void)
>>  {
>>  /*
> 
> 

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Re: [U-Boot] [PATCH 08/24] armv8: add simple sdelay implementation

[Siarhei Siamashka]

On Sun, 20 Nov 2016 14:57:02 +
Andre Przywara  wrote:

> The sunxi DRAM setup code needs an sdelay() implementation, which
> wasn't defined for armv8 so far.
> Shamelessly copy the armv7 version and adjust it to work in AArch64.
> 
> Signed-off-by: Andre Przywara 
> ---
>  arch/arm/cpu/armv8/cpu.c | 13 +
>  1 file changed, 13 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
> index e06c3cc..e82e9cf 100644
> --- a/arch/arm/cpu/armv8/cpu.c
> +++ b/arch/arm/cpu/armv8/cpu.c
> @@ -16,6 +16,19 @@
>  #include 
>  #include 
>  
> +/
> + * sdelay() - simple spin loop.  Will be constant time as
> + *  its generally used in bypass conditions only.  This
> + *  is necessary until timers are accessible.
> + *
> + *  not inline to increase chances its in cache when called
> + */
> +void sdelay(unsigned long loops)
> +{
> + __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
> +   "b.ne 1b":"=r" (loops):"0"(loops));

This inline assembly needs "cc" in the clobber list. Also don't we
want to just use a single register for the counter ("subs %0, %0, #1")
rather than trying to construct something excessively complicated
and possibly fragile?

The https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html page provides
some information.

> +}
> +
>  int cleanup_before_linux(void)
>  {
>   /*


-- 
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Siarhei Siamashka
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[U-Boot] Please pull u-boot-fsl-qoriq master

[york sun]

Tom,

Let's try again.

The following changes since commit 693d4c9f1dc40fcf24ced459bc4d1b46db33298a:

   spl: Remove CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (2016-11-18 21:20:59 
-0500)

are available in the git repository at:

   git://git.denx.de/u-boot-fsl-qoriq.git

for you to fetch changes up to 020198b0c7d251cf6bde76024ecf0ee711860534:

   image-fit: Fix compiling error caused by autoconf.h (2016-11-23 
10:40:08 -0800)


Alison Wang (3):
   armv8: Support loading 32-bit OS in AArch32 execution state
   armv8: fsl-layerscape: SMP support for loading 32-bit OS
   armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled

Feng Li (1):
   armv7: Add support of ls1021a-iot board

Hou Zhiqiang (1):
   fsl: serdes: fix a deadloop issue for P4080

Pratiyush Srivastava (1):
   armv8:ls1012a: Update bootargs for fast-boot

Priyanka Jain (8):
   armv8: ls2080a: Update serdes protocol support
   driver: net: ldpaa_eth: Fix missing bracket issue
   armv8: lsch3: Add generic get_svr() in assembly
   armv8: lsch3: Use SVR based timer base address detection
   armv8: fsl-layerscape: Update TZASC registers type
   armv8: fsl-layerscape : Check SVR for initializing TZASC
   armv8: fsl-layerscape: Add NXP LS2088A SoC support
   armv8/fsl-lsch3: Update code to release secondary cores

Shaohui Xie (3):
   lpuart: add a get_lpuart_clk function
   armv8: ls1046aqds: add lpuart support
   armv8: ls2080aqds: fix SGMII repeater settings

Shengzhou Liu (1):
   armv8/fsl-layerscape: Update CONFIG_LS2080A to CONFIG_FSL_LSCH3

Sriram Dash (1):
   powerpc: mpc512x: Add support for get_svr() for mpc512x devices

Thomas Abraham (1):
   arm: exynos7420: remove custome low level init function

York Sun (2):
   armv7: ls1021aiot: Fixing SPL compiling issues
   image-fit: Fix compiling error caused by autoconf.h

Yuan Yao (3):
   configs: ls2080ardb: Enable DSPI flash support
   arm: ls1021a: improve the core frequency to 1.2GHZ
   armv8: fsl-layerscape: Add README for deploying QSPI image

  arch/arm/Kconfig   |  21 ++
  arch/arm/cpu/armv8/fsl-layerscape/cpu.c|  13 +-
  arch/arm/cpu/armv8/fsl-layerscape/cpu.h|   1 +
  arch/arm/cpu/armv8/fsl-layerscape/doc/README.qspi  |  42 +++
  arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc   |  58 
  arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   | 111 +--
  arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c |   6 +
  arch/arm/cpu/armv8/fsl-layerscape/mp.c |  78 -
  arch/arm/cpu/armv8/fsl-layerscape/soc.c|  13 +-
  arch/arm/cpu/armv8/sec_firmware_asm.S  |  23 ++
  arch/arm/cpu/armv8/start.S |   8 +
  arch/arm/cpu/armv8/transition.S|  35 +-
  arch/arm/dts/Makefile  |   4 +-
  arch/arm/dts/fsl-ls1046a-qds-lpuart.dts|  16 +
  arch/arm/dts/fsl-ls1046a-qds.dtsi  |   4 +
  arch/arm/dts/fsl-ls1046a.dtsi  |  54 +++
  arch/arm/dts/ls1021a-iot-duart.dts |  16 +
  arch/arm/dts/ls1021a-iot.dtsi  | 103 ++
  arch/arm/include/asm/arch-fsl-layerscape/config.h  |   1 +
  arch/arm/include/asm/arch-fsl-layerscape/cpu.h |   4 +
  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |   9 +-
  arch/arm/include/asm/arch-fsl-layerscape/mp.h  |   6 +
  arch/arm/include/asm/arch-fsl-layerscape/soc.h |  12 +-
  arch/arm/include/asm/macro.h   | 176 +++---
  arch/arm/include/asm/system.h  | 121 ++-
  arch/arm/lib/bootm.c   |  45 ++-
  arch/arm/mach-exynos/Kconfig   |   1 +
  arch/arm/mach-exynos/soc.c |  18 +-
  arch/arm/mach-rmobile/lowlevel_init_gen3.S |   9 +-
  arch/powerpc/cpu/mpc512x/start.S   |   5 +
  arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c  |   6 +-
  board/freescale/ls1021aiot/Kconfig |  15 +
  board/freescale/ls1021aiot/MAINTAINERS |   7 +
  board/freescale/ls1021aiot/Makefile|   9 +
  board/freescale/ls1021aiot/README  |  58 
  board/freescale/ls1021aiot/dcu.c   |  47 +++
  board/freescale/ls1021aiot/ls1021aiot.c| 259 +++
  board/freescale/ls1021aiot/ls102xa_pbi.cfg |  14 +
  board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg  |  27 ++
  board/freescale/ls1021aiot/psci.S  |  28 ++
  board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg|   2 +-
  board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg  |   4 +-
  board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg |   4 +-
  board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg  |   2 +-
  board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg |   2 +-
  

Re: [U-Boot] [PATCH v4] mx6sx: Add initial support for Samtec VIN|ING 2000 board

[Marek Vasut]

On 11/23/2016 11:26 PM, Christoph Fritz wrote:
> This patch adds initial support for Samtec VIN|ING 2000 board.
> 
> Signed-off-by: Christoph Fritz 
> ---
> Changes since v1:
>  - add more comments (enet phy init)
>  - fix layout style e.g. multi-line-comments
>  - use pinmux macros
>  - use helper funcs clrsetbits_le32() and wait_for_bit()
>  - make some functions static
>  - drop board_ehci_hcd_init() and board_phy_config()
>  - simplify environment
> Changes since v2:
>  - adapt error handling in board_eth_init() and read_adc()
>  - purge unused macros
>  - use config_distro_bootcmd as environment
>  - fix CONFIG_PWM_IMX undef handling
> Changes since v3:
>  - fix comment spelling
>  - use u32
>  - rearrange if condition

[...]

> diff --git a/board/samtec/vining_2000/Kconfig 
> b/board/samtec/vining_2000/Kconfig
> new file mode 100644
> index 000..f40b3b4
> --- /dev/null
> +++ b/board/samtec/vining_2000/Kconfig
> @@ -0,0 +1,12 @@
> +if TARGET_VINING_2000

Darn, minor nit, should be TARGET_SAMTEC_VINING_2000 (for consistency
with VINING_FPGA).

> +config SYS_BOARD
> + default "vining_2000"
> +
> +config SYS_VENDOR
> + default "samtec"
> +
> +config SYS_CONFIG_NAME
> + default "vining_2000"
> +
> +endif

[...]

> +#ifdef CONFIG_PWM_IMX
> +static int set_pwm_leds(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
> +  ARRAY_SIZE(pwm_led_pads));
> + /* enable backlight PWM 2, green LED */
> + if (pwm_init(1, 0, 0))
> + goto error;

Looking at this, doesn't pwm_init() / pwm_config() return a valid error
code ? If so, propagate it out of this function instead of always
returning -EINVAL .

> + /* duty cycle 200ns, period: 8000ns */
> + if (pwm_config(1, 200, 8000))
> + goto error;
> + if (pwm_enable(1))
> + goto error;
> +
> + /* enable backlight PWM 1, blue LED */
> + if (pwm_init(0, 0, 0))
> + goto error;
> + /* duty cycle 200ns, period: 8000ns */
> + if (pwm_config(0, 200, 8000))
> + goto error;
> + if (pwm_enable(0))
> + goto error;
> +
> + /* enable backlight PWM 6, red LED */
> + if (pwm_init(5, 0, 0))
> + goto error;
> + /* duty cycle 200ns, period: 8000ns */
> + if (pwm_config(5, 200, 8000))
> + goto error;
> + if (pwm_enable(5))
> + goto error;
> +
> + return 0;
> +error:
> + return -EINVAL;
> +}
> +#else
> +static int set_pwm_leds(void)
> +{
> + return 0;
> +}
> +#endif

[...]

Looks great otherwise, thanks.

-- 
Best regards,
Marek Vasut
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[U-Boot] [PATCH v4] mx6sx: Add initial support for Samtec VIN|ING 2000 board

[Christoph Fritz]

This patch adds initial support for Samtec VIN|ING 2000 board.

Signed-off-by: Christoph Fritz 
---
Changes since v1:
 - add more comments (enet phy init)
 - fix layout style e.g. multi-line-comments
 - use pinmux macros
 - use helper funcs clrsetbits_le32() and wait_for_bit()
 - make some functions static
 - drop board_ehci_hcd_init() and board_phy_config()
 - simplify environment
Changes since v2:
 - adapt error handling in board_eth_init() and read_adc()
 - purge unused macros
 - use config_distro_bootcmd as environment
 - fix CONFIG_PWM_IMX undef handling
Changes since v3:
 - fix comment spelling
 - use u32
 - rearrange if condition

 arch/arm/cpu/armv7/mx6/Kconfig |   7 +
 board/samtec/vining_2000/Kconfig   |  12 +
 board/samtec/vining_2000/MAINTAINERS   |   6 +
 board/samtec/vining_2000/Makefile  |   6 +
 board/samtec/vining_2000/imximage.cfg  | 132 +
 board/samtec/vining_2000/vining_2000.c | 512 +
 configs/vining_2000_defconfig  |  31 ++
 include/configs/vining_2000.h  | 123 
 8 files changed, 829 insertions(+)
 create mode 100644 board/samtec/vining_2000/Kconfig
 create mode 100644 board/samtec/vining_2000/MAINTAINERS
 create mode 100644 board/samtec/vining_2000/Makefile
 create mode 100644 board/samtec/vining_2000/imximage.cfg
 create mode 100644 board/samtec/vining_2000/vining_2000.c
 create mode 100644 configs/vining_2000_defconfig
 create mode 100644 include/configs/vining_2000.h

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 762a581..57e02d5 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -192,6 +192,12 @@ config TARGET_UDOO
bool "udoo"
select SUPPORT_SPL
 
+config TARGET_VINING_2000
+   bool "samtec VIN|ING 2000"
+   select MX6SX
+   select DM
+   select DM_THERMAL
+
 config TARGET_WANDBOARD
bool "wandboard"
select SUPPORT_SPL
@@ -247,6 +253,7 @@ source "board/freescale/mx6ullevk/Kconfig"
 source "board/phytec/pcm058/Kconfig"
 source "board/gateworks/gw_ventana/Kconfig"
 source "board/kosagi/novena/Kconfig"
+source "board/samtec/vining_2000/Kconfig"
 source "board/seco/Kconfig"
 source "board/solidrun/mx6cuboxi/Kconfig"
 source "board/technexion/pico-imx6ul/Kconfig"
diff --git a/board/samtec/vining_2000/Kconfig b/board/samtec/vining_2000/Kconfig
new file mode 100644
index 000..f40b3b4
--- /dev/null
+++ b/board/samtec/vining_2000/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_VINING_2000
+
+config SYS_BOARD
+   default "vining_2000"
+
+config SYS_VENDOR
+   default "samtec"
+
+config SYS_CONFIG_NAME
+   default "vining_2000"
+
+endif
diff --git a/board/samtec/vining_2000/MAINTAINERS 
b/board/samtec/vining_2000/MAINTAINERS
new file mode 100644
index 000..027e527
--- /dev/null
+++ b/board/samtec/vining_2000/MAINTAINERS
@@ -0,0 +1,6 @@
+VINING_2000 BOARD
+M: Ingo Schroeck 
+S: Maintained
+F: board/samtec/vining_2000/
+F: include/configs/vining_2000.h
+F: configs/vining_2000_defconfig
diff --git a/board/samtec/vining_2000/Makefile 
b/board/samtec/vining_2000/Makefile
new file mode 100644
index 000..1b32f66
--- /dev/null
+++ b/board/samtec/vining_2000/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 samtec automotive software & electronics gmbh
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := vining_2000.o
diff --git a/board/samtec/vining_2000/imximage.cfg 
b/board/samtec/vining_2000/imximage.cfg
new file mode 100644
index 000..4133dda
--- /dev/null
+++ b/board/samtec/vining_2000/imximage.cfg
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2016 samtec automotive software & electronics gmbh
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#define __ASSEMBLY__
+#include 
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM  sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type   AddressValue
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address   absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0x
+DATA 4 0x020c406c 0x
+DATA 4 0x020c4070 0x
+DATA 4 0x020c4074 0x
+DATA 4 0x020c4078 0x
+DATA 4 0x020c407c 0x
+DATA 4 0x020c4080 0x
+DATA 4 0x020c4084 0x
+
+/* IOMUX - DDR IO Type */
+DATA 4 0x020e0618 0x000c
+DATA 4 0x020e05fc 0x
+
+/* Clock */
+DATA 4 0x020e032c 0x0030
+
+/* Address */
+DATA 4 0x020e0300 0x0028
+DATA 4 0x020e02fc 0x0028
+DATA 4 0x020e05f4 0x0028
+
+/* Control */
+DATA 4 0x020e0340 0x0028
+
+DATA 4 0x020e0320 0x
+DATA 4 0x020e0310 0x0028
+DATA 4 0x020e0314 0x0028
+DATA 4 0x020e0614 0x0028
+
+/* Data Strobe */
+DATA 4 0x020e05f8 0x0002

Re: [U-Boot] [U-Boot,v2] MAINTAINERS: SUNXI: Update maintainership

[Maxime Ripard]

Hi Tom,

On Tue, Nov 22, 2016 at 12:21:07PM -0500, Tom Rini wrote:
> On Tue, Nov 22, 2016 at 05:14:06PM +0530, Jagan Teki wrote:
> 
> > Add Jagan and Maxime as Maintainers for SUNXI
> > 
> > Signed-off-by: Jagan Teki 
> > Acked-by: Maxime Ripard 
> 
> Applied to u-boot/master, thanks!

I guess we should also take over the git repo, how does that work?
Should we send you our SSH keys?

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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[U-Boot] [PATCH] armv7: ls1021aiot: Fixing SPL compiling issues

[York Sun]

To align with SPL change 38fed8ab and 693d4c9f, add Kconfig option
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to defconfig, and remove
CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS.

Signed-off-by: York Sun 
CC: Feng Li 
---
 configs/ls1021aiot_sdcard_defconfig | 2 ++
 include/configs/ls1021aiot.h| 1 -
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/configs/ls1021aiot_sdcard_defconfig 
b/configs/ls1021aiot_sdcard_defconfig
index 4b082ab..a5a391d 100644
--- a/configs/ls1021aiot_sdcard_defconfig
+++ b/configs/ls1021aiot_sdcard_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AIOT=y
 CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
 CONFIG_DM_SPI=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
index 182a003..7af4bc4 100644
--- a/include/configs/ls1021aiot.h
+++ b/include/configs/ls1021aiot.h
@@ -96,7 +96,6 @@
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR0xe8
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
 
 #define CONFIG_SPL_TEXT_BASE   0x1000
 #define CONFIG_SPL_MAX_SIZE0x1a000
-- 
2.7.4

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Re: [U-Boot] [PATCH v3] mx6sx: Add initial support for Samtec VIN|ING 2000 board

[Marek Vasut]

On 11/23/2016 07:39 PM, Christoph Fritz wrote:
> This patch adds initial support for Samtec VIN|ING 2000 board.
> 
> Signed-off-by: Christoph Fritz 
> ---
> Changes since v1:
>  - add more comments (enet phy init)
>  - fix layout style e.g. multi-line-comments
>  - use pinmux macros
>  - use helper funcs clrsetbits_le32() and wait_for_bit()
>  - make some functions static
>  - drop board_ehci_hcd_init() and board_phy_config()
>  - simplify environment
> Changes since v2:
>  - adapt error handling in board_eth_init() and read_adc()
>  - purge unused macros
>  - use config_distro_bootcmd as environment
>  - fix CONFIG_PWM_IMX undef handling

[...]

> +int board_eth_init(bd_t *bis)
> +{
> + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
> + int ret;
> + unsigned char eth1addr[6];
> +
> + /* just to get secound mac address */
> + imx_get_mac_from_fuse(1, eth1addr);
> + if (!getenv("eth1addr") && is_valid_ethaddr(eth1addr))
> + eth_setenv_enetaddr("eth1addr", eth1addr);
> +
> + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
> +
> + /*
> +  * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
> +  * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
> +  * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
> +  */
> + clrsetbits_le32(_regs->gpr[1],
> + IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
> + IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
> + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
> + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
> +
> + ret = enable_fec_anatop_clock(0, ENET_50MHZ);
> +
> + if (ret) {

You can drop the newline above.

> + printf("FEC anatop MXC: %s:failed (%0x)\n",  __func__, ret);
> + goto eth_fail;
> + }

[...]

> +static int read_adc(unsigned int *val)

s/unsigned int/u32/

> +{
> + int ret;
> + void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
> +
> + /* use software mode */
> + writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
> +
> + /* start auto calibration */
> + setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
> + ret = wait_for_bit("ADC", b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
> + if (ret)
> + goto adc_exit;
> +
> + /* start conversation */

"conversion"

> + writel(0, b + ADCx_HC0);
> +
> + /* wait for conversation */

DTTO

> + ret = wait_for_bit("ADC", b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
> + if (ret)
> + goto adc_exit;
> +
> + /* read result */
> + *val = readl(b + ADCx_R0);
> +
> +adc_exit:
> + if (ret)
> + printf("ADC failure (ret=%i)\n", ret);
> + unmap_physmem(b, MAP_NOCACHE);
> + return ret;
> +}
> +
> +#define VAL_UPPER2498
> +#define VAL_LOWER1550
> +
> +static int set_pin_state(void)
> +{
> + unsigned int val;
> + int ret;
> +
> + ret = read_adc();
> + if (ret)
> + return ret;
> +
> + if (val >= VAL_UPPER)
> + setenv("pin_state", "connected");
> + else if (val < VAL_UPPER && val >= VAL_LOWER)
> + setenv("pin_state", "open");
> + else if (val < VAL_LOWER)

Isn't this just catch-all statement ? You can drop the condition.

> + setenv("pin_state", "button");
> +
> + return ret;
> +}

[...]

-- 
Best regards,
Marek Vasut
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[U-Boot] [PATCH] image-fit: Fix compiling error caused by autoconf.h

[York Sun]

Commit ec6617c3 includes autoconf.h in image-fit.c, causing conflict
for board odroid-xu3 which overwrites CONFIG_SYS_BOARD in header
file. Move the include higher and use linux/kconfig.h instead of
generated/autoconf.h.

Signed-off-by: York Sun 
CC: Alison Wang 
---
 common/image-fit.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/image-fit.c b/common/image-fit.c
index ea56d5b..9468e51 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -14,6 +14,7 @@
 #include 
 #else
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -27,7 +28,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #include 
 #include 
 #include 
-#include 
 
 /*/
 /* New uImage format routines */
-- 
2.7.4

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[U-Boot] [PATCH v3] mx6sx: Add initial support for Samtec VIN|ING 2000 board

[Christoph Fritz]

This patch adds initial support for Samtec VIN|ING 2000 board.

Signed-off-by: Christoph Fritz 
---
Changes since v1:
 - add more comments (enet phy init)
 - fix layout style e.g. multi-line-comments
 - use pinmux macros
 - use helper funcs clrsetbits_le32() and wait_for_bit()
 - make some functions static
 - drop board_ehci_hcd_init() and board_phy_config()
 - simplify environment
Changes since v2:
 - adapt error handling in board_eth_init() and read_adc()
 - purge unused macros
 - use config_distro_bootcmd as environment
 - fix CONFIG_PWM_IMX undef handling

 arch/arm/cpu/armv7/mx6/Kconfig |   7 +
 board/samtec/vining_2000/Kconfig   |  12 +
 board/samtec/vining_2000/MAINTAINERS   |   6 +
 board/samtec/vining_2000/Makefile  |   6 +
 board/samtec/vining_2000/imximage.cfg  | 132 +
 board/samtec/vining_2000/vining_2000.c | 513 +
 configs/vining_2000_defconfig  |  31 ++
 include/configs/vining_2000.h  | 123 
 8 files changed, 830 insertions(+)
 create mode 100644 board/samtec/vining_2000/Kconfig
 create mode 100644 board/samtec/vining_2000/MAINTAINERS
 create mode 100644 board/samtec/vining_2000/Makefile
 create mode 100644 board/samtec/vining_2000/imximage.cfg
 create mode 100644 board/samtec/vining_2000/vining_2000.c
 create mode 100644 configs/vining_2000_defconfig
 create mode 100644 include/configs/vining_2000.h

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 762a581..57e02d5 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -192,6 +192,12 @@ config TARGET_UDOO
bool "udoo"
select SUPPORT_SPL
 
+config TARGET_VINING_2000
+   bool "samtec VIN|ING 2000"
+   select MX6SX
+   select DM
+   select DM_THERMAL
+
 config TARGET_WANDBOARD
bool "wandboard"
select SUPPORT_SPL
@@ -247,6 +253,7 @@ source "board/freescale/mx6ullevk/Kconfig"
 source "board/phytec/pcm058/Kconfig"
 source "board/gateworks/gw_ventana/Kconfig"
 source "board/kosagi/novena/Kconfig"
+source "board/samtec/vining_2000/Kconfig"
 source "board/seco/Kconfig"
 source "board/solidrun/mx6cuboxi/Kconfig"
 source "board/technexion/pico-imx6ul/Kconfig"
diff --git a/board/samtec/vining_2000/Kconfig b/board/samtec/vining_2000/Kconfig
new file mode 100644
index 000..f40b3b4
--- /dev/null
+++ b/board/samtec/vining_2000/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_VINING_2000
+
+config SYS_BOARD
+   default "vining_2000"
+
+config SYS_VENDOR
+   default "samtec"
+
+config SYS_CONFIG_NAME
+   default "vining_2000"
+
+endif
diff --git a/board/samtec/vining_2000/MAINTAINERS 
b/board/samtec/vining_2000/MAINTAINERS
new file mode 100644
index 000..027e527
--- /dev/null
+++ b/board/samtec/vining_2000/MAINTAINERS
@@ -0,0 +1,6 @@
+VINING_2000 BOARD
+M: Ingo Schroeck 
+S: Maintained
+F: board/samtec/vining_2000/
+F: include/configs/vining_2000.h
+F: configs/vining_2000_defconfig
diff --git a/board/samtec/vining_2000/Makefile 
b/board/samtec/vining_2000/Makefile
new file mode 100644
index 000..1b32f66
--- /dev/null
+++ b/board/samtec/vining_2000/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 samtec automotive software & electronics gmbh
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := vining_2000.o
diff --git a/board/samtec/vining_2000/imximage.cfg 
b/board/samtec/vining_2000/imximage.cfg
new file mode 100644
index 000..4133dda
--- /dev/null
+++ b/board/samtec/vining_2000/imximage.cfg
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2016 samtec automotive software & electronics gmbh
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#define __ASSEMBLY__
+#include 
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM  sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type   AddressValue
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address   absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0x
+DATA 4 0x020c406c 0x
+DATA 4 0x020c4070 0x
+DATA 4 0x020c4074 0x
+DATA 4 0x020c4078 0x
+DATA 4 0x020c407c 0x
+DATA 4 0x020c4080 0x
+DATA 4 0x020c4084 0x
+
+/* IOMUX - DDR IO Type */
+DATA 4 0x020e0618 0x000c
+DATA 4 0x020e05fc 0x
+
+/* Clock */
+DATA 4 0x020e032c 0x0030
+
+/* Address */
+DATA 4 0x020e0300 0x0028
+DATA 4 0x020e02fc 0x0028
+DATA 4 0x020e05f4 0x0028
+
+/* Control */
+DATA 4 0x020e0340 0x0028
+
+DATA 4 0x020e0320 0x
+DATA 4 0x020e0310 0x0028
+DATA 4 0x020e0314 0x0028
+DATA 4 0x020e0614 0x0028
+
+/* Data Strobe */
+DATA 4 0x020e05f8 0x0002
+DATA 4 0x020e0330 0x0028
+DATA 4 0x020e0334 0x0028
+DATA 4 0x020e0338 

[U-Boot] [PATCH] sunxi: move CONFIG_SATAPWR to Kconfig option

[Jelle van der Waa]

Introduce a new CONFIG_SATAPWR Kconfig option to replace the
option in CONFIG_SYS_EXTRA_OPTIONS.

Signed-off-by: Jelle van der Waa 
---
 board/sunxi/Kconfig|  7 +++
 board/sunxi/board.c| 11 ++-
 configs/A10-OLinuXino-Lime_defconfig   |  3 ++-
 configs/A20-OLinuXino-Lime2_defconfig  |  3 ++-
 configs/A20-OLinuXino-Lime_defconfig   |  3 ++-
 configs/A20-OLinuXino_MICRO_defconfig  |  3 ++-
 configs/A20-Olimex-SOM-EVB_defconfig   |  3 ++-
 configs/Cubieboard2_defconfig  |  3 ++-
 configs/Cubieboard_defconfig   |  3 ++-
 configs/Cubietruck_defconfig   |  3 ++-
 configs/Itead_Ibox_A20_defconfig   |  3 ++-
 configs/Lamobo_R1_defconfig|  3 ++-
 configs/Linksprite_pcDuino3_Nano_defconfig |  3 ++-
 configs/Linksprite_pcDuino3_defconfig  |  3 ++-
 configs/Sinovoip_BPI_M3_defconfig  |  2 +-
 configs/orangepi_plus_defconfig|  3 ++-
 16 files changed, 40 insertions(+), 19 deletions(-)

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index ae2fba1..fe2f7b4 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -667,6 +667,13 @@ config GMAC_TX_DELAY
---help---
Set the GMAC Transmit Clock Delay Chain value.
 
+config SATAPWR
+   string "power pin for SATA"
+   default ""
+   ---help---
+   Set the power pin for SATA. This takes a string in the format
+   understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
+
 config SPL_STACK_R_ADDR
default 0x4fe0 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || 
MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
default 0x2fe0 if MACH_SUN9I
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 5365638..71b1ebf 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -80,7 +80,7 @@ DECLARE_GLOBAL_DATA_PTR;
 /* add board specific code here */
 int board_init(void)
 {
-   __maybe_unused int id_pfr1, ret;
+   __maybe_unused int id_pfr1, ret, pin;
 
gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
 
@@ -117,10 +117,11 @@ int board_init(void)
if (ret)
return ret;
 
-#ifdef CONFIG_SATAPWR
-   gpio_request(CONFIG_SATAPWR, "satapwr");
-   gpio_direction_output(CONFIG_SATAPWR, 1);
-#endif
+pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
+if (pin >= 0) {
+   gpio_request(pin, "satapwr");
+   gpio_direction_output(pin, 1);
+}
 #ifdef CONFIG_MACPWR
gpio_request(CONFIG_MACPWR, "macpwr");
gpio_direction_output(CONFIG_MACPWR, 1);
diff --git a/configs/A10-OLinuXino-Lime_defconfig 
b/configs/A10-OLinuXino-Lime_defconfig
index bb7eaf8..99b5744 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -9,7 +9,8 @@ CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_AHCI=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,SATAPWR=SUNXI_GPC(3)"
+CONFIG_SATAPWR="PC3"
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-OLinuXino-Lime2_defconfig 
b/configs/A20-OLinuXino-Lime2_defconfig
index d48e35d..824fc86 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -9,7 +9,8 @@ CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_AHCI=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,SATAPWR=SUNXI_GPC(3)"
+CONFIG_SATAPWR="PC3"
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-OLinuXino-Lime_defconfig 
b/configs/A20-OLinuXino-Lime_defconfig
index 7c5d84d..2791023 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -7,7 +7,8 @@ CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_AHCI=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPC(3)"
+CONFIG_SATAPWR="PC3"
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-OLinuXino_MICRO_defconfig 
b/configs/A20-OLinuXino_MICRO_defconfig
index 9eb5f1b..774099e 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -10,7 +10,8 @@ CONFIG_VIDEO_VGA=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_AHCI=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPB(8)"
+CONFIG_SATAPWR="PB8"
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig 
b/configs/A20-Olimex-SOM-EVB_defconfig
index 53d800f..139173e 100644
--- 

Re: [U-Boot] [PATCH v2 1/3] ARM: OMAP4+: Add support for dynamically selecting OPPs

[Tom Rini]

On Wed, Nov 23, 2016 at 12:54:39PM +0530, Lokesh Vutla wrote:

> It can be expected that different paper spins of a SoC can have
> different definitions for OPP and can have their own constraints
> on the boot up OPP for each voltage rail. In order to have this
> flexibility, add support for dynamically selecting the OPP voltage
> based on the board to handle any such exceptions.
> 
> Signed-off-by: Lokesh Vutla 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH v2 2/3] ARM: DRA7: Redefine voltage and efuse macros per OPP using Kconfig

[Tom Rini]

On Wed, Nov 23, 2016 at 12:54:40PM +0530, Lokesh Vutla wrote:

> From: Suman Anna 
> 
> Redefine the macros used to define the voltage values and the
> efuse register offsets based on OPP for all the voltage domains.
> This is done using Kconfig macros that can be set in a defconfig
> or selected during a config step. This allows a voltage domain
> to be configured/set to a corresponding voltage value depending
> on the OPP selection choice.
> 
> The Kconfig choices have been added for MPU, DSPEVE, IVA and GPU
> voltage domains, with the MPU domain restricted to OPP_NOM. The
> OPP_OD and OPP_HIGH options will be added when the support for
> configuring the MPU clock frequency is added. The clock
> configuration for other voltage domains is out of scope in
> u-boot code.
> 
> The CORE voltage domain does not have separate voltage values
> and efuse register offset at different OPPs, while the MPU
> voltage domain only has different efuse register offsets for
> different OPPs, but uses the same voltage value. Any different
> choices of OPPs for voltage domains on common ganged-rails
> is automatically taken care to select the corresponding
> highest OPP voltage value.
> 
> Signed-off-by: Suman Anna 
> Signed-off-by: Lokesh Vutla 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PULL] u-boot-pxa/master

[Tom Rini]

On Wed, Nov 23, 2016 at 01:54:45PM +0100, Marek Vasut wrote:

> The following changes since commit 543bd27353d2c5679057fe09aa2d02259687ff32:
> 
>   MAINTAINERS: SUNXI: Update maintainership (2016-11-22 09:07:26 -0500)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-pxa.git master
> 
> for you to fetch changes up to 136179bec19f4bc84227cba138214ea392a723ea:
> 
>   colibri_pxa270: transition to driver model for serial (2016-11-23
> 13:53:20 +0100)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH v2 3/3] ARM: DRA7: Fixup DSPEVE, IVA and GPU clock frequencies based on OPP

[Tom Rini]

On Wed, Nov 23, 2016 at 12:54:41PM +0530, Lokesh Vutla wrote:

> From: Suman Anna 
> 
> This patch adds support to update the device-tree blob to adjust the
> DSP and IVA DPLL clocks pertinent to the selected OPP choice, with
> the default being OPP_NOM. The voltage settings are done in u-boot,
> but the actual clock configuration itself is done in kernel because
> of the following reasons:
> 1. SoC definition constraints us to NOT to do dynamic voltage
>scaling ever after the initial avs0 setting in bootloader
>- so the voltage must be set in bootloader.
> 2. The voltage level must be set even if the IP blocks like
>GPU/DSP are unused.
> 3. The IVA, GPU and DSP DPLLs are not essential for u-boot functionality,
>and similar DPLL clock configuration code has been cleaned up in
>v2014.10 u-boot release. See commit, 02c41535b6a4 ("ARM: OMAP4/5:
>Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALL").
> 
> The non-essential DPLLs are configured within the kernel during
> the clock init step when parsing the device tree and creating
> the clock devices. This approach meets both the u-boot and kernel
> needs.
> 
> Signed-off-by: Suman Anna 
> Signed-off-by: Subhajit Paul 
> Signed-off-by: Lokesh Vutla 

Reviewed-by: Tom Rini 

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Re: [U-Boot] U-Boot x86 QEMU: Error on boot

[Eric Neblock]

On 11/23/2016 11:35 AM, Tom Rini wrote:
> On Wed, Nov 23, 2016 at 11:04:29AM -0600, Eric Neblock wrote:
>> On 11/22/2016 08:21 AM, Tom Rini wrote:
>>> On Mon, Nov 21, 2016 at 03:31:43PM -0600, Eric Neblock wrote:
 Hello,
   I'm trying to get u-boot working on QEMU so I understand how it works
 before moving to an embedded system.

   After following the instructions here:
 https://lists.nongnu.org/archive/html/qemu-devel/2015-05/msg04835.html

 U-Boot is always crashing, even when omitting the network stuff. Below
 is how I'm currently trying to boot:

 qemu-system-i386 -nographic -bios u-boot.rom

 And here is the ending result:

 U-Boot 2016.11 (Nov 21 2016 - 14:03:23 -0600)

 CPU: x86, vendor Intel, device 663h
 DRAM:  128 MiB
 Using default environment

 Video: General Protection
 EIP: 0010:[<07f685e4>] EFLAGS: 0046
 Original EIP :[]
 EAX: 0012 EBX: 0010 ECX:  EDX: 07d643cf
 ESI: 07fad1dc EDI: 07d643e0 EBP: 07fcf564 ESP: 07d64384
  DS: 0018 ES: 0018 FS: 0020 GS: 0018 SS: 0018
 CR0: 0033 CR2:  CR3:  CR4: 
 DR0:  DR1:  DR2:  DR3: 
 DR6: 0ff0 DR7: 0400
 Stack:
 0x07d643c4 : 0x001c
 0x07d643c0 : 0x7acd6388
 0x07d643bc : 0x0111
 0x07d643b8 : 0x000c
 0x07d643b4 : 0x
 0x07d643b0 : 0x074a7205
 0x07d643ac : 0x07f87d87
 0x07d643a8 : 0x7acd6388
 0x07d643a4 : 0x3b9aca00
 0x07d643a0 : 0x
 0x07d6439c : 0x07f8dbe9
 0x07d64398 : 0x07d67720
 0x07d64394 : 0x0002
 0x07d64390 : 0xc0010001
 0x07d6438c : 0x0246
 0x07d64388 : 0x0010
 --->0x07d64384 : 0x07f6a997
 0x07d64380 : 0x0046
 0x07d6437c : 0x0010
 0x07d64378 : 0x07f685e4
 ### ERROR ### Please RESET the board ###


 I think I'm on the bleeding edge branch, but even then when reverting to
 the v2016.09.01 tag, I still crash.

 If there is any additional information that I can provide please let me
 know.
>>>
>>> qemu-x86 is one of our regularly (every push to mainline) tested
>>> targets.  I invoke mine as:
>>> qemu-system-i386 -nographic -cpu qemu32 -bios u-boot.rom \
>>>   -netdev user,id=net0,tftp=/tftpboot -device e1000,netdev=net0
>>>
>>> What version of qemu are you running?
>>>
>> qemu-system-i386 --version:
>>
>> QEMU emulator version 2.3.1, Copyright (c) 2003-2008 Fabrice Bellard
>>
>> Perhaps important to note is I'm using OpenSuSE 42.1.
> 
> That is older than what we test with which is 2.5
> 
The newer version of qemu is not pushed in to the mainline repo, instead
using the Virtulization repo.

Even when upgrading to version:
QEMU emulator version 2.7.0(Virtualization / openSUSE_Leap_42.1),
Copyright (c) 2003-2016 Fabrice Bellard and the QEMU Project developers

We still see the same results, even when just running:

qemu-system-i386 -nographic -cpu qemu32 -bios u-boot.rom
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Re: [U-Boot] T2080 l2-cache-controller compatible string overwritten by ft_fixup_l2cache

[york sun]

On 11/23/2016 01:43 AM, Chris Packham wrote:
> Hi,
>
> I was just looking at what it would take to add the T2080 L2 cache to
> the mpc85xx_edac driver in Linux. At a cursory glance all the
> registers appear to be there so I figured I'd just add the appropriate
> entry to the of match table.
>
> To my surprise I found that the compatible string in my device tree
> was overwritten with "cache". I've tracked this down to the
> CONFIG_SYS_FSL_QORIQ_CHASSIS2 implementation of ft_fixup_l2cache in
> u-boot.
>
> The CONFIG_L2_CACHE version seems to take care to update the device tree node 
> to
>
>   compatible = "fsl,t2080-l2-cache-controller", "cache";
>
> but the CONFIG_SYS_FSL_QORIQ_CHASSIS2 version just sets this to
>
>   compatible = "cache";
>
> Is this an over-site or is it intentional?
>

I don't have any record of this discussion. Kumar wrote and committed 
this change. I hope he remembers.

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Re: [U-Boot] U-Boot x86 QEMU: Error on boot

[Tom Rini]

On Wed, Nov 23, 2016 at 11:04:29AM -0600, Eric Neblock wrote:
> On 11/22/2016 08:21 AM, Tom Rini wrote:
> > On Mon, Nov 21, 2016 at 03:31:43PM -0600, Eric Neblock wrote:
> >> Hello,
> >>   I'm trying to get u-boot working on QEMU so I understand how it works
> >> before moving to an embedded system.
> >>
> >>   After following the instructions here:
> >> https://lists.nongnu.org/archive/html/qemu-devel/2015-05/msg04835.html
> >>
> >> U-Boot is always crashing, even when omitting the network stuff. Below
> >> is how I'm currently trying to boot:
> >>
> >> qemu-system-i386 -nographic -bios u-boot.rom
> >>
> >> And here is the ending result:
> >>
> >> U-Boot 2016.11 (Nov 21 2016 - 14:03:23 -0600)
> >>
> >> CPU: x86, vendor Intel, device 663h
> >> DRAM:  128 MiB
> >> Using default environment
> >>
> >> Video: General Protection
> >> EIP: 0010:[<07f685e4>] EFLAGS: 0046
> >> Original EIP :[]
> >> EAX: 0012 EBX: 0010 ECX:  EDX: 07d643cf
> >> ESI: 07fad1dc EDI: 07d643e0 EBP: 07fcf564 ESP: 07d64384
> >>  DS: 0018 ES: 0018 FS: 0020 GS: 0018 SS: 0018
> >> CR0: 0033 CR2:  CR3:  CR4: 
> >> DR0:  DR1:  DR2:  DR3: 
> >> DR6: 0ff0 DR7: 0400
> >> Stack:
> >> 0x07d643c4 : 0x001c
> >> 0x07d643c0 : 0x7acd6388
> >> 0x07d643bc : 0x0111
> >> 0x07d643b8 : 0x000c
> >> 0x07d643b4 : 0x
> >> 0x07d643b0 : 0x074a7205
> >> 0x07d643ac : 0x07f87d87
> >> 0x07d643a8 : 0x7acd6388
> >> 0x07d643a4 : 0x3b9aca00
> >> 0x07d643a0 : 0x
> >> 0x07d6439c : 0x07f8dbe9
> >> 0x07d64398 : 0x07d67720
> >> 0x07d64394 : 0x0002
> >> 0x07d64390 : 0xc0010001
> >> 0x07d6438c : 0x0246
> >> 0x07d64388 : 0x0010
> >> --->0x07d64384 : 0x07f6a997
> >> 0x07d64380 : 0x0046
> >> 0x07d6437c : 0x0010
> >> 0x07d64378 : 0x07f685e4
> >> ### ERROR ### Please RESET the board ###
> >>
> >>
> >> I think I'm on the bleeding edge branch, but even then when reverting to
> >> the v2016.09.01 tag, I still crash.
> >>
> >> If there is any additional information that I can provide please let me
> >> know.
> > 
> > qemu-x86 is one of our regularly (every push to mainline) tested
> > targets.  I invoke mine as:
> > qemu-system-i386 -nographic -cpu qemu32 -bios u-boot.rom \
> >   -netdev user,id=net0,tftp=/tftpboot -device e1000,netdev=net0
> > 
> > What version of qemu are you running?
> > 
> qemu-system-i386 --version:
> 
> QEMU emulator version 2.3.1, Copyright (c) 2003-2008 Fabrice Bellard
> 
> Perhaps important to note is I'm using OpenSuSE 42.1.

That is older than what we test with which is 2.5

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Re: [U-Boot] U-Boot x86 QEMU: Error on boot

[Eric Neblock]

On 11/22/2016 08:21 AM, Tom Rini wrote:
> On Mon, Nov 21, 2016 at 03:31:43PM -0600, Eric Neblock wrote:
>> Hello,
>>   I'm trying to get u-boot working on QEMU so I understand how it works
>> before moving to an embedded system.
>>
>>   After following the instructions here:
>> https://lists.nongnu.org/archive/html/qemu-devel/2015-05/msg04835.html
>>
>> U-Boot is always crashing, even when omitting the network stuff. Below
>> is how I'm currently trying to boot:
>>
>> qemu-system-i386 -nographic -bios u-boot.rom
>>
>> And here is the ending result:
>>
>> U-Boot 2016.11 (Nov 21 2016 - 14:03:23 -0600)
>>
>> CPU: x86, vendor Intel, device 663h
>> DRAM:  128 MiB
>> Using default environment
>>
>> Video: General Protection
>> EIP: 0010:[<07f685e4>] EFLAGS: 0046
>> Original EIP :[]
>> EAX: 0012 EBX: 0010 ECX:  EDX: 07d643cf
>> ESI: 07fad1dc EDI: 07d643e0 EBP: 07fcf564 ESP: 07d64384
>>  DS: 0018 ES: 0018 FS: 0020 GS: 0018 SS: 0018
>> CR0: 0033 CR2:  CR3:  CR4: 
>> DR0:  DR1:  DR2:  DR3: 
>> DR6: 0ff0 DR7: 0400
>> Stack:
>> 0x07d643c4 : 0x001c
>> 0x07d643c0 : 0x7acd6388
>> 0x07d643bc : 0x0111
>> 0x07d643b8 : 0x000c
>> 0x07d643b4 : 0x
>> 0x07d643b0 : 0x074a7205
>> 0x07d643ac : 0x07f87d87
>> 0x07d643a8 : 0x7acd6388
>> 0x07d643a4 : 0x3b9aca00
>> 0x07d643a0 : 0x
>> 0x07d6439c : 0x07f8dbe9
>> 0x07d64398 : 0x07d67720
>> 0x07d64394 : 0x0002
>> 0x07d64390 : 0xc0010001
>> 0x07d6438c : 0x0246
>> 0x07d64388 : 0x0010
>> --->0x07d64384 : 0x07f6a997
>> 0x07d64380 : 0x0046
>> 0x07d6437c : 0x0010
>> 0x07d64378 : 0x07f685e4
>> ### ERROR ### Please RESET the board ###
>>
>>
>> I think I'm on the bleeding edge branch, but even then when reverting to
>> the v2016.09.01 tag, I still crash.
>>
>> If there is any additional information that I can provide please let me
>> know.
> 
> qemu-x86 is one of our regularly (every push to mainline) tested
> targets.  I invoke mine as:
> qemu-system-i386 -nographic -cpu qemu32 -bios u-boot.rom \
>   -netdev user,id=net0,tftp=/tftpboot -device e1000,netdev=net0
> 
> What version of qemu are you running?
> 
qemu-system-i386 --version:

QEMU emulator version 2.3.1, Copyright (c) 2003-2008 Fabrice Bellard

Perhaps important to note is I'm using OpenSuSE 42.1.

Eric Neblock
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Re: [U-Boot] Please pull u-boot-fsl-qoriq master

[york sun]

On 11/23/2016 04:22 AM, Tom Rini wrote:
> On Wed, Nov 23, 2016 at 01:06:12AM +, york sun wrote:
>> Tom,
>>
>> The following changes since commit 693d4c9f1dc40fcf24ced459bc4d1b46db33298a:
>>
>>spl: Remove CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (2016-11-18 21:20:59
>> -0500)
>>
>> are available in the git repository at:
>>
>>git://git.denx.de/u-boot-fsl-qoriq.git
>>
>> for you to fetch changes up to 3db86f4bbd7a723421c8c9bf9bd09d58e17e9736:
>>
>>armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled
>> (2016-11-22 11:40:24 -0800)
>
> NAK.  Two problems:
> +(ls1021aiot_sdcard)  static int mmc_load_image_raw_sector(struct 
> spl_image_info *spl_image,
> +(ls1021aiot_sdcard) ^
>   +(ls1021aiot_sdcard) Error: You 
> must add new CONFIG options using Kconfig   +(ls1021aiot_sdcard) 
> The following new ad-hoc CONFIG options were detected: 
> +(ls1021aiot_sdcard) CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS   
>   +(ls1021aiot_sdcard)
> +(ls1021aiot_sdcard) Please add these via Kconfig 
> instead. Find a suitable Kconfig  +(ls1021aiot_sdcard) file and add a 
> 'config' or 'menuconfig' option.+(ls1021aiot_sdcard) 
> make[1]: *** [all] Error 1
>
> And:
> +(odroid-xu3)  #define CONFIG_SYS_BOARD "smdk5420"
>   +(odroid-xu3)  ^
> +(odroid-xu3) In file included from include/config.h:5:0, 
>   +(odroid-xu3)  from 
> ../include/common.h:18, +(odroid-xu3) 
>  from ../common/image-fit.c:17:   +(odroid-xu3) 
> ../include/configs/odroid_xu3.h:107:0: note: this is the location of the 
> previous definition   
>+(odroid-xu3)  #define CONFIG_SYS_BOARD "odroid"
>

Hmm, I didn't see these issues. I will try again.

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Re: [U-Boot] [PATCH v2] mx6sx: Add initial support for Samtec VIN|ING 2000 board

[Marek Vasut]

On 11/23/2016 05:33 PM, Christoph Fritz wrote:
> This patch adds initial support for Samtec VIN|ING 2000 board.
> 
> Signed-off-by: Christoph Fritz 
> ---

[...]

> diff --git a/board/samtec/vining_2000/vining_2000.c 
> b/board/samtec/vining_2000/vining_2000.c
> new file mode 100644
> index 000..66ebe89
> --- /dev/null
> +++ b/board/samtec/vining_2000/vining_2000.c
> @@ -0,0 +1,504 @@
> +/*
> + * Copyright (C) 2016 samtec automotive software & electronics gmbh

Isn't GmbH written with caps at the beginning and end ? ;-)

> + *
> + * Author: Christoph Fritz 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 

This ehci-ci.h is probably unneeded.

> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;


[...]

> +int board_eth_init(bd_t *bis)
> +{
> + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
> + int ret;
> + unsigned char eth1addr[6];
> +
> + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
> + gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
> +
> + /*
> +  * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
> +  * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
> +  * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
> +  */
> + clrsetbits_le32(_regs->gpr[1],
> + IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
> + IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
> + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
> + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
> +
> + ret = enable_fec_anatop_clock(0, ENET_50MHZ);
> +
> + if (ret)
> + printf("FEC anatop MXC: %s:failed (%0x)\n",  __func__, ret);

If failure happens, you should likely bail out.

> + /* reset phy */
> + gpio_set_value(IMX_GPIO_NR(5, 9), 0);
> + mdelay(20);
> + gpio_set_value(IMX_GPIO_NR(5, 9), 1);
> + mdelay(1);
> +
> + ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR,
> + IMX_FEC_BASE);
> + if (ret)
> + printf("FEC MXC: %s:failed\n", __func__);

DTTO

> + /* just to get secound mac address */
> + imx_get_mac_from_fuse(1, eth1addr);
> + if (!getenv("eth1addr") && is_valid_ethaddr(eth1addr))
> + eth_setenv_enetaddr("eth1addr", eth1addr);
> +
> + return ret;
> +}

[...]

> +#ifdef CONFIG_USB_EHCI_MX6
> +#define USB_OTHERREGS_OFFSET 0x800
> +#define UCTRL_PWR_POL(1 << 9)

These two macros are unused

> +static iomux_v3_cfg_t const usb_otg_pads[] = {
> + /* OGT1 */
> + MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* OTG2 */
> + MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
> +};
> +
> +static void setup_iomux_usb(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
> +  ARRAY_SIZE(usb_otg_pads));
> +}
> +
> +int board_usb_phy_mode(int port)
> +{
> + if (port == 1)
> + return USB_INIT_HOST;
> + else
> + return usb_phy_mode(port);
> +}
> +#endif
> +
> +static int set_pwm_leds(void)
> +{
> +#ifdef CONFIG_PWM_IMX
> + imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
> +  ARRAY_SIZE(pwm_led_pads));
> + /* enable backlight PWM 2, green LED */
> + if (pwm_init(1, 0, 0))
> + goto error;
> + /* duty cycle 200ns, period: 8000ns */
> + if (pwm_config(1, 200, 8000))
> + goto error;
> + if (pwm_enable(1))
> + goto error;
> +
> + /* enable backlight PWM 1, blue LED */
> + if (pwm_init(0, 0, 0))
> + goto error;
> + /* duty cycle 200ns, period: 8000ns */
> + if (pwm_config(0, 200, 8000))
> + goto error;
> + if (pwm_enable(0))
> + goto error;
> +
> + /* enable backlight PWM 6, red LED */
> + if (pwm_init(5, 0, 0))
> + goto error;
> + /* duty cycle 200ns, period: 8000ns */
> + if (pwm_config(5, 200, 8000))
> + goto error;
> + if (pwm_enable(5))
> + goto error;
> +#endif
> +
> + return 0;
> +error:

Compiler will complain about unused label here if CONFIG_PWM_IMX is not set.

> + return -1;
> +}


[...]

> +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
> + {USDHC4_BASE_ADDR},

Fill the 0, 0 here for consistency, it triggers my OCD.

> + {USDHC2_BASE_ADDR, 0, 4},
> +};
> +
> +#define USDHC2_CD_GPIO IMX_GPIO_NR(3, 28)

[...]

> diff --git a/include/configs/vining_2000.h 

[U-Boot] [PATCH v2] mx6sx: Add initial support for Samtec VIN|ING 2000 board

[Christoph Fritz]

This patch adds initial support for Samtec VIN|ING 2000 board.

Signed-off-by: Christoph Fritz 
---

Changes since v1:

 - add more comments (enet phy init)
 - fix layout style e.g. multi-line-comments
 - use pinmux macros
 - use helper funcs clrsetbits_le32() and wait_for_bit()
 - make some functions static
 - drop board_ehci_hcd_init() and board_phy_config()
 - simplify environment

 arch/arm/cpu/armv7/mx6/Kconfig |   7 +
 board/samtec/vining_2000/Kconfig   |  12 +
 board/samtec/vining_2000/MAINTAINERS   |   6 +
 board/samtec/vining_2000/Makefile  |   6 +
 board/samtec/vining_2000/imximage.cfg  | 132 +
 board/samtec/vining_2000/vining_2000.c | 504 +
 configs/vining_2000_defconfig  |  31 ++
 include/configs/vining_2000.h  | 140 +
 8 files changed, 838 insertions(+)
 create mode 100644 board/samtec/vining_2000/Kconfig
 create mode 100644 board/samtec/vining_2000/MAINTAINERS
 create mode 100644 board/samtec/vining_2000/Makefile
 create mode 100644 board/samtec/vining_2000/imximage.cfg
 create mode 100644 board/samtec/vining_2000/vining_2000.c
 create mode 100644 configs/vining_2000_defconfig
 create mode 100644 include/configs/vining_2000.h

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 762a581..57e02d5 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -192,6 +192,12 @@ config TARGET_UDOO
bool "udoo"
select SUPPORT_SPL
 
+config TARGET_VINING_2000
+   bool "samtec VIN|ING 2000"
+   select MX6SX
+   select DM
+   select DM_THERMAL
+
 config TARGET_WANDBOARD
bool "wandboard"
select SUPPORT_SPL
@@ -247,6 +253,7 @@ source "board/freescale/mx6ullevk/Kconfig"
 source "board/phytec/pcm058/Kconfig"
 source "board/gateworks/gw_ventana/Kconfig"
 source "board/kosagi/novena/Kconfig"
+source "board/samtec/vining_2000/Kconfig"
 source "board/seco/Kconfig"
 source "board/solidrun/mx6cuboxi/Kconfig"
 source "board/technexion/pico-imx6ul/Kconfig"
diff --git a/board/samtec/vining_2000/Kconfig b/board/samtec/vining_2000/Kconfig
new file mode 100644
index 000..f40b3b4
--- /dev/null
+++ b/board/samtec/vining_2000/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_VINING_2000
+
+config SYS_BOARD
+   default "vining_2000"
+
+config SYS_VENDOR
+   default "samtec"
+
+config SYS_CONFIG_NAME
+   default "vining_2000"
+
+endif
diff --git a/board/samtec/vining_2000/MAINTAINERS 
b/board/samtec/vining_2000/MAINTAINERS
new file mode 100644
index 000..027e527
--- /dev/null
+++ b/board/samtec/vining_2000/MAINTAINERS
@@ -0,0 +1,6 @@
+VINING_2000 BOARD
+M: Ingo Schroeck 
+S: Maintained
+F: board/samtec/vining_2000/
+F: include/configs/vining_2000.h
+F: configs/vining_2000_defconfig
diff --git a/board/samtec/vining_2000/Makefile 
b/board/samtec/vining_2000/Makefile
new file mode 100644
index 000..1b32f66
--- /dev/null
+++ b/board/samtec/vining_2000/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 samtec automotive software & electronics gmbh
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := vining_2000.o
diff --git a/board/samtec/vining_2000/imximage.cfg 
b/board/samtec/vining_2000/imximage.cfg
new file mode 100644
index 000..4133dda
--- /dev/null
+++ b/board/samtec/vining_2000/imximage.cfg
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2016 samtec automotive software & electronics gmbh
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#define __ASSEMBLY__
+#include 
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM  sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type   AddressValue
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address   absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0x
+DATA 4 0x020c406c 0x
+DATA 4 0x020c4070 0x
+DATA 4 0x020c4074 0x
+DATA 4 0x020c4078 0x
+DATA 4 0x020c407c 0x
+DATA 4 0x020c4080 0x
+DATA 4 0x020c4084 0x
+
+/* IOMUX - DDR IO Type */
+DATA 4 0x020e0618 0x000c
+DATA 4 0x020e05fc 0x
+
+/* Clock */
+DATA 4 0x020e032c 0x0030
+
+/* Address */
+DATA 4 0x020e0300 0x0028
+DATA 4 0x020e02fc 0x0028
+DATA 4 0x020e05f4 0x0028
+
+/* Control */
+DATA 4 0x020e0340 0x0028
+
+DATA 4 0x020e0320 0x
+DATA 4 0x020e0310 0x0028
+DATA 4 0x020e0314 0x0028
+DATA 4 0x020e0614 0x0028
+
+/* Data Strobe */
+DATA 4 0x020e05f8 0x0002
+DATA 4 0x020e0330 0x0028
+DATA 4 0x020e0334 0x0028
+DATA 4 0x020e0338 0x0028
+DATA 4 0x020e033c 0x0028
+
+/* Data */
+DATA 4 0x020e0608 0x0002
+DATA 4 0x020e060c 0x0028
+DATA 4 0x020e0610 0x0028
+DATA 4 0x020e061c 0x0028

Re: [U-Boot] [PATCH] mx6sx: Add initial support for Samtec VIN|ING 2000 board

[Christoph Fritz]

On Tue, 2016-11-22 at 16:22 +0100, Marek Vasut wrote:
> On 11/22/2016 03:48 PM, Christoph Fritz wrote:

[...]

> > diff --git a/board/samtec/vining2000/imximage.cfg 
> > b/board/samtec/vining2000/imximage.cfg
> > new file mode 100644
> > index 000..4133dda
> > --- /dev/null
> > +++ b/board/samtec/vining2000/imximage.cfg
> > @@ -0,0 +1,132 @@
> > +/*
> > + * Copyright (C) 2016 samtec automotive software & electronics gmbh
> > + *
> > + * SPDX-License-Identifier:GPL-2.0+
> > + */
> > +
> > +#define __ASSEMBLY__
> > +#include 
> 
> Is this needed at all ?

yes

> > +{
> > +   unsigned char offset, i, switch_num;
> > +   u32 id;
> > +   int ret;
> > +
> > +   pmic_reg_read(p, PFUZE100_DEVICEID, );
> > +   id = id & 0xf;
> > +
> > +   if (id == 0) {
> > +   switch_num = 6;
> > +   offset = PFUZE100_SW1CMODE;
> > +   } else if (id == 1) {
> > +   switch_num = 4;
> > +   offset = PFUZE100_SW2MODE;
> > +   } else {
> > +   printf("Not supported, id=%d\n", id);
> > +   return -EINVAL;
> > +   }
> > +
> > +   ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
> 
> Why do you need to do this write ?

to init the PMIC mode to APS_PFM

[...]

> > +int board_phy_config(struct phy_device *phydev)
> > +{
> > +   if (phydev->drv->config)
> > +   phydev->drv->config(phydev);
> 
> Is this really needed?

no

[...]

Thanks,

I'll reroll this patch.

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Re: [U-Boot] [PATCH u-boot 4/5] aspeed: Added function to configure pins for I2C devices.

[Simon Glass]

[resend from correct address]

On 23 November 2016 at 09:13, Simon Glass  wrote:
> Hi Maxim,
>
> On 22 November 2016 at 16:56,   wrote:
>> From: Maxim Sloyko 
>>
>> In the absence of pinmux driver, I2C driver will be
>> configuring pins directly.
>
> Commit subject s/Added/Add/
>
> and please remove the '.' at the end.
>
>>
>> Signed-off-by: Maxim Sloyko 
>> ---
>>  arch/arm/include/asm/arch-aspeed/ast_scu.h |  5 +
>>  arch/arm/mach-aspeed/ast-scu.c | 28 
>>  2 files changed, 33 insertions(+)
>>
>> diff --git a/arch/arm/include/asm/arch-aspeed/ast_scu.h 
>> b/arch/arm/include/asm/arch-aspeed/ast_scu.h
>> index eb5aaa2..80ebd6f 100644
>> --- a/arch/arm/include/asm/arch-aspeed/ast_scu.h
>> +++ b/arch/arm/include/asm/arch-aspeed/ast_scu.h
>> @@ -46,4 +46,9 @@ extern void ast_scu_init_eth(u8 num);
>>  extern void ast_scu_multi_func_eth(u8 num);
>>  extern void ast_scu_multi_func_romcs(u8 num);
>>
>> +/* Enable I2C controller and pins for a particular device.
>> + * Device numbering starts at 1
>> + */
>> +extern void ast_scu_enable_i2c(u8 num);
>
> I suspect this should be done as a pinctrl driver. See for
> drivers/pinctrl for examples.
>
>> +
>>  #endif
>> diff --git a/arch/arm/mach-aspeed/ast-scu.c b/arch/arm/mach-aspeed/ast-scu.c
>> index e00dbe2..b5aa8bf 100644
>> --- a/arch/arm/mach-aspeed/ast-scu.c
>> +++ b/arch/arm/mach-aspeed/ast-scu.c
>> @@ -507,3 +507,31 @@ void ast_scu_get_who_init_dram(void)
>> break;
>> }
>>  }
>> +
>> +void ast_scu_enable_i2c(u8 bus_num)
>> +{
>> +   if (bus_num > SCU_I2C_MAX_BUS_NUM) {
>> +   debug("%s: bus_num is out of range, must be [%d - %d]\n",
>> + __func__, SCU_I2C_MIN_BUS_NUM, SCU_I2C_MAX_BUS_NUM);
>> +   return;
>> +   }
>> +
>> +   if (bus_num == 0) {
>> +   /* Enable I2C Controllers */
>> +   clrbits_le32(AST_SCU_BASE + AST_SCU_RESET, SCU_RESET_I2C);
>> +   } else if (bus_num >= 3) {
>> +   setbits_le32(AST_SCU_BASE + AST_SCU_FUN_PIN_CTRL5,
>> +SCU_FUN_PIN_I2C(bus_num));
>> +   /* In earlier versions of the SoC these pins are always assigned to
>> +* respective I2C buses and require no configuration.
>> +*/
>> +#ifdef AST_SOC_G5
>> +   } else if (bus_num == 1) {
>> +   setbits_le32(AST_SCU_BASE + AST_SCU_FUN_PIN_CTRL8,
>> +SCU_FUN_PIN_SDA1 | SCU_FUN_PIN_SCL1);
>> +   } else if (bus_num == 2) {
>> +   setbits_le32(AST_SCU_BASE + AST_SCU_FUN_PIN_CTRL8,
>> +SCU_FUN_PIN_SDA2 | SCU_FUN_PIN_SCL2);
>> +#endif
>> +   }
>> +}
>> --
>> 2.8.0.rc3.226.g39d4020
>>
>
> Regards,
> Simon
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Re: [U-Boot] [PATCH u-boot 5/5] aspeed: I2C driver.

[Simon Glass]

[resend from correct address]

On 23 November 2016 at 09:13, Simon Glass  wrote:
> Hi Maxim,
>
> On 22 November 2016 at 16:56,   wrote:
>> From: Maxim Sloyko 
>>
>> The driver is very limited: only single master mode is supported
>> and only byte-by-byte synchronous reads and writes are supported,
>> no Pool Buffers or DMA.
>
> Please add that into the Kconfig help too.
>
>>
>> Signed-off-by: Maxim Sloyko 
>> ---
>>  drivers/i2c/Kconfig   |   7 ++
>>  drivers/i2c/Makefile  |   1 +
>>  drivers/i2c/ast_i2c.c | 305 
>> ++
>>  drivers/i2c/ast_i2c.h | 143 +++
>>  4 files changed, 456 insertions(+)
>>  create mode 100644 drivers/i2c/ast_i2c.c
>>  create mode 100644 drivers/i2c/ast_i2c.h
>>
>> diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
>> index 6e22bba..720c475 100644
>> --- a/drivers/i2c/Kconfig
>> +++ b/drivers/i2c/Kconfig
>> @@ -90,6 +90,13 @@ config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
>>   enable status register. This config option can be enabled in such
>>   cases.
>>
>> +config SYS_I2C_AST
>> +   bool "Aspeed I2C Controller"
>> +   depends on DM_I2C
>> +   help
>> + Say yes here to select Aspeed I2C Host Controller. The driver
>> + supports AST2500 and AST2400 controllers.
>> +
>>  config SYS_I2C_INTEL
>> bool "Intel I2C/SMBUS driver"
>> depends on DM_I2C
>> diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
>> index 167424d..89e046e 100644
>> --- a/drivers/i2c/Makefile
>> +++ b/drivers/i2c/Makefile
>> @@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
>>  obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
>>  obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
>>  obj-$(CONFIG_SYS_I2C) += i2c_core.o
>> +obj-$(CONFIG_SYS_I2C_AST) += ast_i2c.o
>>  obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
>>  obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
>>  obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
>> diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c
>> new file mode 100644
>> index 000..f2c132e
>> --- /dev/null
>> +++ b/drivers/i2c/ast_i2c.c
>> @@ -0,0 +1,305 @@
>> +/*
>> + * Copyright (C) 2012-2020  ASPEED Technology Inc.
>> + * Copyright 2016 IBM Corporation
>> + * Copyright 2016 Google, Inc.
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include "ast_i2c.h"
>> +
>> +#define I2C_TIMEOUT_US (10)
>> +#define I2C_SLEEP_STEP (20)
>
> I2C_SLEEP_STEP_US
>
>> +#define EI2C_TIMEOUT (1001)
>
> EI2C_TIMEOUT_US
>
> Please drop the () on those
>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +struct ast_i2c {
>
> Please add a struct comment with member info.
>
>> +   u32 id;
>> +   struct ast_i2c_regs *regs;
>> +   int speed;
>> +};
>> +
>> +static u32 get_clk_reg_val(u32 divider_ratio)
>
> Function comment. Consider returning ulong.
>
>> +{
>> +   unsigned int inc = 0, div;
>> +   u32 scl_low, scl_high, data;
>> +
>> +   for (div = 0; divider_ratio >= 16; div++) {
>> +   inc |= (divider_ratio & 1);
>> +   divider_ratio >>= 1;
>> +   }
>> +   divider_ratio += inc;
>> +   scl_low = (divider_ratio >> 1) - 1;
>> +   scl_high = divider_ratio - scl_low - 2;
>> +   data = 0x77700300 | (scl_high << 16) | (scl_low << 12) | div;
>
> blank link here. What is the magic 0x77700300 for? Should either have
> a comment or a #define
>
>> +   return data;
>> +}
>> +
>> +static inline void ast_i2c_clear_interrupts(struct ast_i2c_regs *i2c_base)
>> +{
>> +   writel(~0, _base->isr);
>> +}
>> +
>> +static void ast_i2c_init_bus(struct ast_i2c *i2c_bus)
>> +{
>> +   /* Reset device */
>> +   writel(0, _bus->regs->fcr);
>> +   /* Enable Master Mode. Assuming single-master. */
>
> nit: Please avoid '.' at end of comments
>
>> +   debug("Enable Master for %p\n", i2c_bus->regs);
>> +   writel(AST_I2CD_MASTER_EN
>> +  | AST_I2CD_M_SDA_LOCK_EN
>> +  | AST_I2CD_MULTI_MASTER_DIS | AST_I2CD_M_SCL_DRIVE_EN,
>> +  _bus->regs->fcr);
>> +   debug("FCR: %p\n", _bus->regs->fcr);
>> +   /* Enable Interrupts */
>> +   writel(AST_I2CD_INTR_TX_ACK
>> +  | AST_I2CD_INTR_TX_NAK
>> +  | AST_I2CD_INTR_RX_DONE
>> +  | AST_I2CD_INTR_BUS_RECOVER_DONE
>> +  | AST_I2CD_INTR_NORMAL_STOP
>> +  | AST_I2CD_INTR_ABNORMAL, _bus->regs->icr);
>> +}
>> +
>> +static int ast_i2c_probe(struct udevice *dev)
>> +{
>> +   struct ast_i2c *i2c_bus = dev_get_priv(dev);
>> +
>> +   debug("Enabling I2C%u\n", dev->seq);
>> +   ast_scu_enable_i2c(dev->seq);
>> +
>> +   i2c_bus->id = dev->seq;
>> +   struct ast_i2c_regs *i2c_base =
>> +   (struct ast_i2c_regs *)dev_get_addr(dev);
>
> Can you use dev_get_addr_ptr()? Need 

Re: [U-Boot] [PATCH u-boot 3/5] aspeed: Added function to calculate APB Clock frequency.

[Simon Glass]

[resend from correct address]

On 23 November 2016 at 09:13, Simon Glass  wrote:
> Hi Maxim,
>
> On 22 November 2016 at 16:56,   wrote:
>> From: Maxim Sloyko 
>>
>
> For the subject, 'Add' rather than 'Added' (we use present tense)
>
>> This is needed by I2C driver.
>>
>> Signed-off-by: Maxim Sloyko 
>> ---
>>  arch/arm/include/asm/arch-aspeed/ast_scu.h |  1 +
>>  arch/arm/mach-aspeed/ast-scu.c | 11 +++
>>  2 files changed, 12 insertions(+)
>>
>> diff --git a/arch/arm/include/asm/arch-aspeed/ast_scu.h 
>> b/arch/arm/include/asm/arch-aspeed/ast_scu.h
>> index d248416..eb5aaa2 100644
>> --- a/arch/arm/include/asm/arch-aspeed/ast_scu.h
>> +++ b/arch/arm/include/asm/arch-aspeed/ast_scu.h
>> @@ -38,6 +38,7 @@ extern void ast_scu_get_who_init_dram(void);
>>  extern u32 ast_get_clk_source(void);
>>  extern u32 ast_get_h_pll_clk(void);
>>  extern u32 ast_get_ahbclk(void);
>> +extern u32 ast_get_apbclk(void);
>
> Please add a comment as to what this does and what it returns.
>
>>
>>  extern u32 ast_scu_get_vga_memsize(void);
>>
>> diff --git a/arch/arm/mach-aspeed/ast-scu.c b/arch/arm/mach-aspeed/ast-scu.c
>> index 280c421..e00dbe2 100644
>> --- a/arch/arm/mach-aspeed/ast-scu.c
>> +++ b/arch/arm/mach-aspeed/ast-scu.c
>> @@ -318,6 +318,17 @@ u32 ast_get_ahbclk(void)
>>
>>  #endif /* AST_SOC_G5 */
>>
>> +u32 ast_get_apbclk(void)
>> +{
>> +   u32 h_pll = ast_get_h_pll_clk();
>
> Can this be ulong, or is there a reason it has to be exactly 32 bits?
>
> blank line here (between declarations and code)
>
>> +   /* The formula for converting the bit pattern to divisor is
>
> /*
>  * The formula...
>  * ...
>  */
>
>> +* (4 + 4 * DIV), according to datasheet
>> +*/
>> +   u32 apb_div = 4 + 4 * 
>> SCU_GET_PCLK_DIV(ast_scu_read(AST_SCU_CLK_SEL));
>> +   return h_pll / apb_div;
>> +}
>> +
>> +
>>  void ast_scu_show_system_info(void)
>>  {
>>
>> --
>> 2.8.0.rc3.226.g39d4020
>>
>
> Regards,
> Simon
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Re: [U-Boot] [PATCH u-boot 2/5] aspeed: Fixed incosistency in some SCU registers naming.

[Simon Glass]

[resend from correct address]

On 23 November 2016 at 09:13, Simon Glass  wrote:
> Hi Maxim,
>
> On 22 November 2016 at 16:56,   wrote:
>> From: Maxim Sloyko 
>>
>> Basically fixed FUC/FUN typo that went out of hand.
>>
>> Signed-off-by: Maxim Sloyko 
>
> This looks like a mix of whiltespace changes and other changes? If so,
> can you split it into two patches?
>
>> ---
>>  arch/arm/include/asm/arch-aspeed/regs-scu.h | 73 
>> -
>>  arch/arm/mach-aspeed/ast-scu.c  |  2 +-
>>  2 files changed, 42 insertions(+), 33 deletions(-)
>>
>
> Regards,
> Simon
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Re: [U-Boot] [PATCH u-boot 1/5] aspeed/g5: Device Tree for ast2500, copied from openbmc/linux (include file), plus minimal device tree configuration for ast2500 eval board.

[Simon Glass]

[resend from correct address]

On 23 November 2016 at 09:13, Simon Glass  wrote:
> On 22 November 2016 at 16:56,   wrote:
>> From: Maxim Sloyko 
>>
>> aspeed-g5.dtsi include file is copied from
>> https://github.com/openbmc/linux/blob/c5682cb/arch/arm/boot/dts/aspeed-g5.dtsi
>>
>> Signed-off-by: Maxim Sloyko 
>> ---
>>  arch/arm/dts/Makefile  |2 +
>>  arch/arm/dts/aspeed-g5-evb.dts |   28 +
>>  arch/arm/dts/aspeed-g5.dtsi| 1278 
>> 
>>  3 files changed, 1308 insertions(+)
>>  create mode 100644 arch/arm/dts/aspeed-g5-evb.dts
>>  create mode 100644 arch/arm/dts/aspeed-g5.dtsi
>
> Reviewed-by: Simon Glass 
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