[U-Boot] Please pull u-boot-x86

[Bin Meng]

Hi Tom,

This PR includes the following changes to x86:
- Enable SD slot on Intel Edison
- Populate CSRT ACPI table for shared DMA controller on Intel Tangier
- Convert Intel ICH-SPI driver to use new spi-mem ops
- Enable config_distro_bootcmd for QEMU x86
- Support U-Boot as a payload for Intel Slim Bootloader
- Avoid writing temporary asl files into the source tree which fixes
the parallel build issue occasionally seen

The following changes since commit fef408679b2f634ebfd6298d9fc99db99e60fb1d:

  Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
(2019-08-08 09:19:08 -0400)

are available in the git repository at:

  https://gitlab.denx.de/u-boot/custodians/u-boot-x86.git

for you to fetch changes up to dbaec467671fd5b56cf380121340844863f5472d:

  x86: Skip setting up MTRRs in slimbootloader (2019-08-09 22:24:02 +0800)


Andy Shevchenko (5):
  x86: edison: Enable SD slot
  x86: acpi: Add CSRT description
  x86: acpi: Introduce a stub to generate CSRT
  x86: acpi: Enable ACPI companion for Intel iDMA 32-bit
  x86: tangier: Populate CSRT for shared DMA controller

Bernhard Messerklinger (1):
  x86: ich-spi: Convert driver to spi-mem ops

Bin Meng (1):
  x86: qemu: Fix non-working ramboot and nfsboot environment variables

Heinrich Schuchardt (1):
  bios_emulator: remove stray break

Joshua Watt (1):
  qemu-x86: Use config_distro_bootcmd

Park, Aiden (9):
  x86: Add new slimbootloader CPU type
  x86: lib: fsp: Use EFI_GUID and efi_guid_t
  x86: Add a common HOB library
  x86: slimbootloader: Add memory configuration
  x86: slimbootloader: Add serial driver
  x86: slimbootloader: Set TSC information for tsc_timer
  x86: slimbootloader: Add a slimbootloader device tree
  board: intel: Add new slimbootloader board
  x86: Skip setting up MTRRs in slimbootloader

Simon Glass (1):
  x86: Avoid writing temporary asl files into the source tree

 arch/x86/Kconfig  |   9 
 arch/x86/cpu/Makefile |   1 +
 arch/x86/cpu/slimbootloader/Kconfig   |  19 
 arch/x86/cpu/slimbootloader/Makefile  |   5 ++
 arch/x86/cpu/slimbootloader/car.S |  14 ++
 arch/x86/cpu/slimbootloader/sdram.c   | 151

 arch/x86/cpu/slimbootloader/serial.c  |  67
+++
 arch/x86/cpu/slimbootloader/slimbootloader.c  |  58
+++
 arch/x86/cpu/start.S  |   6 ++-
 arch/x86/cpu/tangier/acpi.c   |  38

 arch/x86/dts/Makefile |   1 +
 arch/x86/dts/edison.dts   |   5 --
 arch/x86/dts/slimbootloader.dts   |  27 +++
 arch/x86/include/asm/acpi_table.h |  32 +
 arch/x86/include/asm/arch-slimbootloader/slimbootloader.h | 115
++
 arch/x86/include/asm/arch-tangier/acpi/southcluster.asl   |  22 +
 arch/x86/include/asm/fsp/fsp_ffs.h|   4 +-
 arch/x86/include/asm/fsp/fsp_fv.h |   4 +-
 arch/x86/include/asm/fsp/fsp_hob.h| 252
+++-
 arch/x86/include/asm/fsp/fsp_support.h|  39
+---
 arch/x86/include/asm/fsp/fsp_types.h  |   8 
 arch/x86/include/asm/global_data.h|   2 +-
 arch/x86/include/asm/hob.h| 230
+++
 arch/x86/lib/Makefile |   1 +
 arch/x86/lib/acpi_table.c |  32 +
 arch/x86/lib/asm-offsets.c|   2 +-
 arch/x86/lib/fsp/fsp_support.c| 123
-
 arch/x86/lib/hob.c|  84
++
 arch/x86/lib/init_helpers.c   |   3 +-
 board/intel/Kconfig   |  14 ++
 board/intel/edison/edison.c   |  10 
 board/intel/slimbootloader/Kconfig|  28 
 board/intel/slimbootloader/MAINTAINERS|   6 +++
 board/intel/slimbootloader/Makefile   |   5 ++
 board/intel/slimbootloader/slimbootloader.c   |  21 +
 board/intel/slimbootloader/start.S|   9 
 

[U-Boot] [PATCH 1/1] network: set timeline for CONFIG_DM_ETH conversion

[Heinrich Schuchardt]

The driver model has been supported for network drivers since 2015. It is
time to convert the remaining boards. Set July 2020 as a timeline.

Signed-off-by: Heinrich Schuchardt 
---
 Makefile   | 11 +++
 doc/driver-model/migration.rst |  8 
 2 files changed, 19 insertions(+)

diff --git a/Makefile b/Makefile
index 8513db94e3..4d42602b3b 100644
--- a/Makefile
+++ b/Makefile
@@ -1025,6 +1025,17 @@ ifneq ($(CONFIG_WDT),y)
@echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
@echo >&2 ""
 endif
+endif
+ifneq ($(CONFIG_NET),)
+ifneq ($(CONFIG_DM_ETH),y)
+   @echo >&2 "= WARNING =="
+   @echo >&2 "This board does not use CONFIG_DM_ETH (Driver Model"
+   @echo >&2 "for Ethernet drivers). Please update the board to use"
+   @echo >&2 "CONFIG_DM_ETH before the v2020.07 release. Failure to"
+   @echo >&2 "update by the deadline may result in board removal."
+   @echo >&2 "See doc/driver-model/migration.rst for more info."
+   @echo >&2 ""
+endif
 endif
@# Check that this build does not use CONFIG options that we do not
@# know about unless they are in Kconfig. All the existing CONFIG
diff --git a/doc/driver-model/migration.rst b/doc/driver-model/migration.rst
index a26e7ab7e1..75b85235ef 100644
--- a/doc/driver-model/migration.rst
+++ b/doc/driver-model/migration.rst
@@ -97,3 +97,11 @@ Deadline: 2019.07
 The video subsystem has supported driver model since early 2016. Maintainers
 should submit patches switching over to using CONFIG_DM_VIDEO and other base
 driver model options in time for inclusion in the 2019.07 release.
+
+CONFIG_DM_ETH
+-
+Deadline: 2020.07
+
+The network subsystem has supported the driver model since early 2015.
+Maintainers should submit patches switching over to using CONFIG_DM_ETH and
+other base driver model options in time for inclusion in the 2020.07 release.
--
2.20.1

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Re: [U-Boot] RFC: Migration target date for DM_ETH

[Heinrich Schuchardt]

On 8/9/19 7:02 PM, Simon Glass wrote:

Hi Heinrich,

On Fri, 9 Aug 2019 at 00:31, Heinrich Schuchardt  wrote:


Currently dozens of boards still do not use the driver model for the
network devices. This makes integration between devices in the UEFI
sub-system with the U-Boot devices complicated.

See: https://travis-ci.org/xypron2/u-boot/builds/569675547

In doc/driver-model/migration.rst I am missing a migration target day
for DM_ETH. Shouldn't we define one? 2020-07 should be realistic.


Yes, good idea.

Also we need to convert the Ethernet PHYs to DM.


In drivers/net/phy/ there isn't even a uclass. It makes sense to convert
this class of drivers too. But I guess it can be handles as a separate task.

Best regards

Heinrich
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Re: [U-Boot] Booting Linux kernel on x86_64

[Ryan Wilkins]

> On Aug 9, 2019, at 12:00 PM, Bin Meng  wrote:
> 
> +Simon, Andy,
> 
> Hi Ryan,
> 
>> On Fri, Aug 9, 2019 at 11:52 PM Ryan Wilkins  
>> wrote:
>> 
>> Hello,
>> 
>> I’m trying to get u-boot 2019.04 to execute the Linux 4.19.55 kernel from 
>> u-boot on a generic Core i5 with 8 GB RAM and having issues.  The kernel 
>> that I’m trying to boot will boot fine from GRUB so I know it works but 
>> starting from u-boot just shows “Starting kernel” and the system appears to 
>> freeze.
> 
> Which specific Core i5 processor are you using? And what's the U-Boot
> target for that board? Is that U-Boot as EFI payload or something? Did
> you set up U-Boot environment variable "bootargs" with Linux kernel's
> command line, e.g.: I think you need at least specify console=tty0 or
> ttyS0?

I’m using a Core i5-6500 on a Supermicro X11SSV-Q mainboard.
U-boot is compiled as an EFI 64-bit payload which came from the 
efi-x86_payload64_defconfig.  I disabled xHCI USB support because it was 
freezing on this board and preventing u-boot from doing anything else.
I was setting bootargs to “console=tty0” during a few of the boot tests but it 
didn’t seem to make any difference.



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Re: [U-Boot] [PATCH 1/2] usb: kbd: simplify coding for arrow keys

[Heinrich Schuchardt]

On 6/24/19 8:49 PM, Simon Glass wrote:

Hi Heinrich,

On Mon, 24 Jun 2019 at 11:36, Heinrich Schuchardt  wrote:


On 6/24/19 3:56 PM, Simon Glass wrote:

On Sun, 16 Jun 2019 at 22:44, Heinrich Schuchardt  wrote:


Avoid duplicate translation of arrow key codes.

Signed-off-by: Heinrich Schuchardt 
---
   common/usb_kbd.c | 31 +--
   1 file changed, 9 insertions(+), 22 deletions(-)


Reviewed-by: Simon Glass 

We should really have a test for this input stuff...



We already have.

For low level analysis:

=> conitrace
Waiting for your input
To terminate type 'x'
61
1b 5b 32 30 7e

For a higher level view:

=> setenv efi_selftest extended text input
=> bootefi selftest
Executing 'extended text input'
Waiting for your input
To terminate type 'CTRL+x'
Unicode char 100 ('d'), scan code 0 (Null)
Unicode char 0 (Null), scan code 19 (+FN 9)
Unicode char 0 (Null), scan code 19 (SHIFT+FN 9)


I mean automated test :-)

Regards,
Simon


Hello Simon,

drivers/usb/emul/sandbox_keyb.c seems to bypass the driver in
common/usb_keyb.c instead of emulating a USB keyboard.

Shouldn't it pass keyboard scan codes to common/usb_keyb.c?

Would you know how to get this fixed? Then I can add the additional
keyboard scan codes.

Best regards

Heinrich
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[U-Boot] [PATCH 1/1] cmd/bdinfo: sandbox: print the relocation offset

[Heinrich Schuchardt]

On the sandbox provide the relocation offset. This value can be used for
debugging with GDB using the `add-symbol-file u-boot ' command.

Signed-off-by: Heinrich Schuchardt 
---
 cmd/bdinfo.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 86c17dc427..560c039d37 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -395,6 +395,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])

print_bi_boot_params(bd);
print_bi_dram(bd);
+   print_num("reloc off", (uintptr_t)(gd->reloc_off + gd->arch.ram_buf));
print_eth_ip_addr();

 #if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
--
2.20.1

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[U-Boot] [PATCH v2 6/7] ARM: renesas: Add R8A77980 V3H platform code

[Marek Vasut]

Add a few bits of platform code to support R8A77980 V3H SoC.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
V2: No change
---
 arch/arm/mach-rmobile/Kconfig.64 | 5 +
 arch/arm/mach-rmobile/cpu_info.c | 1 +
 arch/arm/mach-rmobile/include/mach/rmobile.h | 1 +
 3 files changed, 7 insertions(+)

diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 27d29f797f..2d549f7bb4 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -22,6 +22,11 @@ config R8A77970
imply CLK_R8A77970
imply PINCTRL_PFC_R8A77970
 
+config R8A77980
+   bool "Renesas SoC R8A77980"
+   imply CLK_R8A77980
+   imply PINCTRL_PFC_R8A77980
+
 config R8A77990
bool "Renesas SoC R8A77990"
imply CLK_R8A77990
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index 784a2a28d5..dc407d2a61 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -64,6 +64,7 @@ static const struct {
{ RMOBILE_CPU_TYPE_R8A7796, "R8A7796" },
{ RMOBILE_CPU_TYPE_R8A77965, "R8A77965" },
{ RMOBILE_CPU_TYPE_R8A77970, "R8A77970" },
+   { RMOBILE_CPU_TYPE_R8A77980, "R8A77980" },
{ RMOBILE_CPU_TYPE_R8A77990, "R8A77990" },
{ RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
{ 0x0, "CPU" },
diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h 
b/arch/arm/mach-rmobile/include/mach/rmobile.h
index aa8d43e59b..a50249dc96 100644
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -36,6 +36,7 @@
 #define RMOBILE_CPU_TYPE_R8A7796   0x52
 #define RMOBILE_CPU_TYPE_R8A77965  0x55
 #define RMOBILE_CPU_TYPE_R8A77970  0x54
+#define RMOBILE_CPU_TYPE_R8A77980  0x56
 #define RMOBILE_CPU_TYPE_R8A77990  0x57
 #define RMOBILE_CPU_TYPE_R8A77995  0x58
 
-- 
2.20.1

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[U-Boot] [PATCH v2 7/7] ARM: renesas: Add R8A77980 V3H Condor board code

[Marek Vasut]

Add board code for the R8A77980 V3H Condor board.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
V2: Use DTs from Linux 5.2.y
---
 arch/arm/dts/Makefile   |   1 +
 arch/arm/dts/r8a77980-condor-u-boot.dts |  34 +++
 arch/arm/dts/r8a77980-condor.dts| 292 
 arch/arm/mach-rmobile/Kconfig.64|   7 +
 board/renesas/condor/Kconfig|  15 ++
 board/renesas/condor/MAINTAINERS|   6 +
 board/renesas/condor/Makefile   |  13 ++
 board/renesas/condor/condor.c   |  55 +
 configs/r8a77980_condor_defconfig   |  69 ++
 include/configs/condor.h|  41 
 10 files changed, 533 insertions(+)
 create mode 100644 arch/arm/dts/r8a77980-condor-u-boot.dts
 create mode 100644 arch/arm/dts/r8a77980-condor.dts
 create mode 100644 board/renesas/condor/Kconfig
 create mode 100644 board/renesas/condor/MAINTAINERS
 create mode 100644 board/renesas/condor/Makefile
 create mode 100644 board/renesas/condor/condor.c
 create mode 100644 configs/r8a77980_condor_defconfig
 create mode 100644 include/configs/condor.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7c806eee9e..9e7d6d6490 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -645,6 +645,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a77965-m3nulcb-u-boot.dtb \
r8a77965-salvator-x-u-boot.dtb \
r8a77970-eagle-u-boot.dtb \
+   r8a77980-condor-u-boot.dtb \
r8a77990-ebisu-u-boot.dtb \
r8a77995-draak-u-boot.dtb
 
diff --git a/arch/arm/dts/r8a77980-condor-u-boot.dts 
b/arch/arm/dts/r8a77980-condor-u-boot.dts
new file mode 100644
index 00..1b22c7f0b9
--- /dev/null
+++ b/arch/arm/dts/r8a77980-condor-u-boot.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Condor board
+ *
+ * Copyright (C) 2019 Marek Vasut 
+ */
+
+#include "r8a77980-condor.dts"
+#include "r8a77980-u-boot.dtsi"
+
+/ {
+   aliases {
+   spi0 = 
+   };
+};
+
+ {
+   num-cs = <1>;
+   status = "okay";
+   spi-max-frequency = <5000>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   flash0: spi-flash@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "s25fs512s", "jedec,spi-nor";
+   spi-max-frequency = <5000>;
+   spi-tx-bus-width = <1>;
+   spi-rx-bus-width = <1>;
+   reg = <0>;
+   status = "okay";
+   };
+};
diff --git a/arch/arm/dts/r8a77980-condor.dts b/arch/arm/dts/r8a77980-condor.dts
new file mode 100644
index 00..5a7012be0d
--- /dev/null
+++ b/arch/arm/dts/r8a77980-condor.dts
@@ -0,0 +1,292 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Condor board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+
+/dts-v1/;
+#include "r8a77980.dtsi"
+
+/ {
+   model = "Renesas Condor board based on r8a77980";
+   compatible = "renesas,condor", "renesas,r8a77980";
+
+   aliases {
+   serial0 = 
+   ethernet0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory@4800 {
+   device_type = "memory";
+   /* first 128MB is reserved for secure area. */
+   reg = <0 0x4800 0 0x7800>;
+   };
+
+   d3_3v: regulator-0 {
+   compatible = "regulator-fixed";
+   regulator-name = "D3.3V";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
+   vddq_vin01: regulator-1 {
+   compatible = "regulator-fixed";
+   regulator-name = "VDDQ_VIN01";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
+   d1_8v: regulator-2 {
+   compatible = "regulator-fixed";
+   regulator-name = "D1.8V";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
+   hdmi-out {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con: endpoint {
+   remote-endpoint = <_out>;
+   };
+   };
+   };
+
+   lvds-decoder {
+   compatible = "thine,thc63lvd1024";
+   vcc-supply = <_3v>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = 

[U-Boot] [PATCH v2 3/7] pinctrl: renesas: Add R8A77980 V3H PFC tables

[Marek Vasut]

Import R8A77980 V3H PFC tables from Linux 5.2.7 , commit 5697a9d3d55f.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
V2: Use tables from Linux 5.2.y
---
 drivers/pinctrl/renesas/Kconfig|   10 +
 drivers/pinctrl/renesas/Makefile   |1 +
 drivers/pinctrl/renesas/pfc-r8a77980.c | 2897 
 drivers/pinctrl/renesas/pfc.c  |   11 +
 drivers/pinctrl/renesas/sh_pfc.h   |1 +
 5 files changed, 2920 insertions(+)
 create mode 100644 drivers/pinctrl/renesas/pfc-r8a77980.c

diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 0ffd7fcfd4..4d3d68d307 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -97,6 +97,16 @@ config PINCTRL_PFC_R8A77970
  the GPIO definitions and pin control functions for each available
  multiplex function.
 
+config PINCTRL_PFC_R8A77980
+   bool "Renesas RCar Gen3 R8A77980 pin control driver"
+   depends on PINCTRL_PFC
+   help
+ Support pin multiplexing control on Renesas RCar Gen3 R8A77980 SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
+
 config PINCTRL_PFC_R8A77990
bool "Renesas RCar Gen3 R8A77990 pin control driver"
depends on PINCTRL_PFC
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index e8703f681e..a92f787a89 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
 obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o
diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c 
b/drivers/pinctrl/renesas/pfc-r8a77980.c
new file mode 100644
index 00..32efb4409c
--- /dev/null
+++ b/drivers/pinctrl/renesas/pfc-r8a77980.c
@@ -0,0 +1,2897 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R8A77980 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ *
+ * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+ *
+ * R-Car Gen3 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "sh_pfc.h"
+
+#define CPU_ALL_PORT(fn, sfx)  \
+   PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),  \
+   PORT_GP_28(1, fn, sfx), \
+   PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),  \
+   PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+   PORT_GP_25(4, fn, sfx), \
+   PORT_GP_15(5, fn, sfx)
+
+/*
+ * F_() : just information
+ * FM() : macro for FN_xxx / xxx_MARK
+ */
+
+/* GPSR0 */
+#define GPSR0_21   F_(DU_EXODDF_DU_ODDF_DISP_CDE,  IP2_23_20)
+#define GPSR0_20   F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
+#define GPSR0_19   F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
+#define GPSR0_18   F_(DU_DOTCLKOUT,IP2_11_8)
+#define GPSR0_17   F_(DU_DB7,  IP2_7_4)
+#define GPSR0_16   F_(DU_DB6,  IP2_3_0)
+#define GPSR0_15   F_(DU_DB5,  IP1_31_28)
+#define GPSR0_14   F_(DU_DB4,  IP1_27_24)
+#define GPSR0_13   F_(DU_DB3,  IP1_23_20)
+#define GPSR0_12   F_(DU_DB2,  IP1_19_16)
+#define GPSR0_11   F_(DU_DG7,  IP1_15_12)
+#define GPSR0_10   F_(DU_DG6,  IP1_11_8)
+#define GPSR0_9F_(DU_DG5,  IP1_7_4)
+#define GPSR0_8F_(DU_DG4,  IP1_3_0)
+#define GPSR0_7F_(DU_DG3,  IP0_31_28)
+#define GPSR0_6F_(DU_DG2,  IP0_27_24)
+#define GPSR0_5F_(DU_DR7,  IP0_23_20)
+#define GPSR0_4F_(DU_DR6,  IP0_19_16)
+#define GPSR0_3F_(DU_DR5,  IP0_15_12)
+#define GPSR0_2F_(DU_DR4,  IP0_11_8)
+#define GPSR0_1F_(DU_DR3,  IP0_7_4)
+#define GPSR0_0F_(DU_DR2,  IP0_3_0)
+
+/* GPSR1 */
+#define GPSR1_27   F_(DIGRF_CLKOUT,IP8_31_28)
+#define GPSR1_26   F_(DIGRF_CLKIN, IP8_27_24)
+#define GPSR1_25   F_(CANFD_CLK_A, IP8_23_20)
+#define GPSR1_24   F_(CANFD1_RX,   IP8_19_16)
+#define GPSR1_23   F_(CANFD1_TX,   IP8_15_12)

[U-Boot] [PATCH v2 2/7] net: sh_eth: Fix 64bit build warnings

[Marek Vasut]

Fix various type warnings when building this driver for 64bit machine.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Nobuhiro Iwamatsu 
---
V2: No change
---
 drivers/net/sh_eth.c | 24 
 drivers/net/sh_eth.h |  8 
 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 485c4b71ad..2d5c97062f 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -37,8 +37,8 @@
 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #define flush_cache_wback(addr, len)\
-   flush_dcache_range((u32)addr, \
-   (u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
+   flush_dcache_range((unsigned long)addr, \
+   (unsigned long)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
 #else
 #define flush_cache_wback(...)
 #endif
@@ -46,11 +46,11 @@
 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
 #define invalidate_cache(addr, len)\
{   \
-   u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE;\
-   u32 start, end; \
+   unsigned long line_size = CONFIG_SH_ETHER_ALIGNE_SIZE;  \
+   unsigned long start, end;   \
\
-   start = (u32)addr;  \
-   end = start + len;  \
+   start = (unsigned long)addr;\
+   end = start + len;  \
start &= ~(line_size - 1);  \
end = ((end + line_size - 1) & ~(line_size - 1));   \
\
@@ -74,7 +74,7 @@ static int sh_eth_send_common(struct sh_eth_dev *eth, void 
*packet, int len)
}
 
/* packet must be a 4 byte boundary */
-   if ((int)packet & 3) {
+   if ((uintptr_t)packet & 3) {
printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
, __func__);
ret = -EFAULT;
@@ -211,7 +211,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 
/* Make sure we use a P2 address (non-cacheable) */
port_info->tx_desc_base =
-   (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc);
+   (struct tx_desc_s 
*)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc);
port_info->tx_desc_cur = port_info->tx_desc_base;
 
/* Initialize all descriptors */
@@ -265,7 +265,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 
/* Make sure we use a P2 address (non-cacheable) */
port_info->rx_desc_base =
-   (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc);
+   (struct rx_desc_s 
*)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc);
 
port_info->rx_desc_cur = port_info->rx_desc_base;
 
@@ -281,7 +281,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
goto err_buf_alloc;
}
 
-   port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc);
+   port_info->rx_buf_base = (u8 
*)ADDR_TO_P2((uintptr_t)port_info->rx_buf_alloc);
 
/* Initialize all descriptors */
for (cur_rx_desc = port_info->rx_desc_base,
@@ -700,7 +700,7 @@ static int sh_ether_recv(struct udevice *dev, int flags, 
uchar **packetp)
struct sh_ether_priv *priv = dev_get_priv(dev);
struct sh_eth_dev *eth = >shdev;
struct sh_eth_info *port_info = >port_info[eth->port];
-   uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
+   uchar *packet = (uchar 
*)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2);
int len;
 
len = sh_eth_recv_start(eth);
@@ -850,7 +850,7 @@ static int sh_ether_probe(struct udevice *udev)
eth->port = CONFIG_SH_ETHER_USE_PORT;
eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
eth->port_info[eth->port].iobase =
-   (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
+   (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);
 
 #if CONFIG_IS_ENABLED(CLK)
ret = clk_enable(>clk);
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 564cdaccb7..d197dfdc40 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -15,20 +15,20 @@
 #if defined(CONFIG_SH)
 /* Malloc returns addresses in the P1 area (cacheable). However we need to
use area P2 (non-cacheable) */
-#define ADDR_TO_P2(addr)   int)(addr) & ~0xe000) | 0xa000))
+#define ADDR_TO_P2(addr)   uintptr_t)(addr) & ~0xe000) | 
0xa000))
 
 /* The ethernet controller needs to use physical addresses */
 #if defined(CONFIG_SH_32BIT)
-#define ADDR_TO_PHY(addr)  int)(addr) & ~0xe000) | 0x4000))
+#define ADDR_TO_PHY(addr)  uintptr_t)(addr) & ~0xe000) | 
0x4000))
 #else
-#define ADDR_TO_PHY(addr)  ((int)(addr) & ~0xe000)
+#define ADDR_TO_PHY(addr)  ((uintptr_t)(addr) & ~0xe000)
 

[U-Boot] [PATCH v2 5/7] ARM: dts: renesas: Add R8A77980 V3H DTs and headers

[Marek Vasut]

Import R8A77980 V3H DTs and headers from Linux 5.2.7 , commit 5697a9d3d55f.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
V2: Use DTs from Linux 5.2.y
---
 arch/arm/dts/r8a77980-u-boot.dtsi |   24 +
 arch/arm/dts/r8a77980.dtsi| 1605 +
 include/dt-bindings/clock/r8a77980-cpg-mssr.h |   51 +
 include/dt-bindings/power/r8a77980-sysc.h |   43 +
 4 files changed, 1723 insertions(+)
 create mode 100644 arch/arm/dts/r8a77980-u-boot.dtsi
 create mode 100644 arch/arm/dts/r8a77980.dtsi
 create mode 100644 include/dt-bindings/clock/r8a77980-cpg-mssr.h
 create mode 100644 include/dt-bindings/power/r8a77980-sysc.h

diff --git a/arch/arm/dts/r8a77980-u-boot.dtsi 
b/arch/arm/dts/r8a77980-u-boot.dtsi
new file mode 100644
index 00..1050f6e991
--- /dev/null
+++ b/arch/arm/dts/r8a77980-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on RCar R8A77980 SoC
+ *
+ * Copyright (C) 2019 Marek Vasut 
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+_clk {
+   u-boot,dm-pre-reloc;
+};
+
+/ {
+   soc {
+   rpc: rpc@0xee20 {
+   compatible = "renesas,rpc-r8a77980", "renesas,rpc";
+   reg = <0 0xee20 0 0x100>, <0 0x0800 0 0>;
+   clocks = < CPG_MOD 917>;
+   bank-width = <2>;
+   status = "disabled";
+   };
+   };
+};
diff --git a/arch/arm/dts/r8a77980.dtsi b/arch/arm/dts/r8a77980.dtsi
new file mode 100644
index 00..a901a341dc
--- /dev/null
+++ b/arch/arm/dts/r8a77980.dtsi
@@ -0,0 +1,1605 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the R-Car V3H (R8A77980) SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   compatible = "renesas,r8a77980";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   aliases {
+   i2c0 = 
+   i2c1 = 
+   i2c2 = 
+   i2c3 = 
+   i2c4 = 
+   i2c5 = 
+   };
+
+   /* External CAN clock - to be overridden by boards that provide it */
+   can_clk: can {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   a53_0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53";
+   reg = <0>;
+   clocks = < CPG_CORE R8A77980_CLK_Z2>;
+   power-domains = < R8A77980_PD_CA53_CPU0>;
+   next-level-cache = <_CA53>;
+   enable-method = "psci";
+   };
+
+   a53_1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53";
+   reg = <1>;
+   clocks = < CPG_CORE R8A77980_CLK_Z2>;
+   power-domains = < R8A77980_PD_CA53_CPU1>;
+   next-level-cache = <_CA53>;
+   enable-method = "psci";
+   };
+
+   a53_2: cpu@2 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53";
+   reg = <2>;
+   clocks = < CPG_CORE R8A77980_CLK_Z2>;
+   power-domains = < R8A77980_PD_CA53_CPU2>;
+   next-level-cache = <_CA53>;
+   enable-method = "psci";
+   };
+
+   a53_3: cpu@3 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53";
+   reg = <3>;
+   clocks = < CPG_CORE R8A77980_CLK_Z2>;
+   power-domains = < R8A77980_PD_CA53_CPU3>;
+   next-level-cache = <_CA53>;
+   enable-method = "psci";
+   };
+
+   L2_CA53: cache-controller {
+   compatible = "cache";
+   power-domains = < R8A77980_PD_CA53_SCU>;
+   cache-unified;
+   cache-level = <2>;
+   };
+   };
+
+   extal_clk: extal {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   /* This value must be overridden by the board */
+   clock-frequency = <0>;
+   };
+
+   extalr_clk: extalr {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   /* This value must be overridden by the board */
+   clock-frequency = <0>;
+   };
+
+   /* External PCIe clock - can be overridden by the board */
+   pcie_bus_clk: pcie_bus {
+  

[U-Boot] [PATCH v2 4/7] clk: renesas: Add R8A77980 V3H clock tables

[Marek Vasut]

Import R8A77980 V3H clock tables from Linux 5.2.7 , commit 5697a9d3d55f.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
V2: Use tables from Linux 5.2.y
---
 drivers/clk/renesas/Kconfig |   6 +
 drivers/clk/renesas/Makefile|   1 +
 drivers/clk/renesas/r8a77980-cpg-mssr.c | 255 
 3 files changed, 262 insertions(+)
 create mode 100644 drivers/clk/renesas/r8a77980-cpg-mssr.c

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 3862c1b848..e78817829b 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -72,6 +72,12 @@ config CLK_R8A77970
help
  Enable this to support the clocks on Renesas R8A77970 SoC.
 
+config CLK_R8A77980
+   bool "Renesas R8A77980 clock driver"
+   depends on CLK_RCAR_GEN3
+   help
+ Enable this to support the clocks on Renesas R8A77980 SoC.
+
 config CLK_R8A77990
bool "Renesas R8A77990 clock driver"
depends on CLK_RCAR_GEN3
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 26b343994c..88339e9d7e 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -10,5 +10,6 @@ obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c 
b/drivers/clk/renesas/r8a77980-cpg-mssr.c
new file mode 100644
index 00..c076ac771f
--- /dev/null
+++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a77980 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ *
+ * Based on r8a7795-cpg-mssr.c
+ *
+ * Copyright (C) 2015 Glider bvba
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+   /* Core Clock Outputs exported to DT */
+   LAST_DT_CORE_CLK = R8A77980_CLK_OSC,
+
+   /* External Input Clocks */
+   CLK_EXTAL,
+   CLK_EXTALR,
+
+   /* Internal Core Clocks */
+   CLK_MAIN,
+   CLK_PLL1,
+   CLK_PLL2,
+   CLK_PLL3,
+   CLK_PLL1_DIV2,
+   CLK_PLL1_DIV4,
+   CLK_S0,
+   CLK_S1,
+   CLK_S2,
+   CLK_S3,
+   CLK_SDSRC,
+   CLK_RPCSRC,
+   CLK_OCO,
+
+   /* Module Clocks */
+   MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a77980_core_clks[] = {
+   /* External Clock Inputs */
+   DEF_INPUT("extal",  CLK_EXTAL),
+   DEF_INPUT("extalr", CLK_EXTALR),
+
+   /* Internal Core Clocks */
+   DEF_BASE(".main",   CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+   DEF_BASE(".pll1",   CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+   DEF_BASE(".pll2",   CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
+   DEF_BASE(".pll3",   CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+
+   DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1,   2, 1),
+   DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2,  2, 1),
+   DEF_FIXED(".s0",CLK_S0,CLK_PLL1_DIV2,  2, 1),
+   DEF_FIXED(".s1",CLK_S1,CLK_PLL1_DIV2,  3, 1),
+   DEF_FIXED(".s2",CLK_S2,CLK_PLL1_DIV2,  4, 1),
+   DEF_FIXED(".s3",CLK_S3,CLK_PLL1_DIV2,  6, 1),
+   DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2,  2, 1),
+   DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
+   DEF_RATE(".oco",CLK_OCO,   32768),
+
+   DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC,
+CLK_RPCSRC),
+   DEF_BASE("rpcd2",   R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+R8A77980_CLK_RPC),
+
+   /* Core Clock Outputs */
+   DEF_FIXED("ztr",R8A77980_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
+   DEF_FIXED("ztrd2",  R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+   DEF_FIXED("zt", R8A77980_CLK_ZT,CLK_PLL1_DIV2,  4, 1),
+   DEF_FIXED("zx", R8A77980_CLK_ZX,CLK_PLL1_DIV2,  2, 1),
+   DEF_FIXED("s0d1",   R8A77980_CLK_S0D1,  CLK_S0, 1, 1),
+   DEF_FIXED("s0d2",   R8A77980_CLK_S0D2,  CLK_S0, 2, 1),
+   DEF_FIXED("s0d3",   R8A77980_CLK_S0D3,  CLK_S0, 3, 1),
+   DEF_FIXED("s0d4",   R8A77980_CLK_S0D4,  CLK_S0, 4, 1),
+   DEF_FIXED("s0d6",   R8A77980_CLK_S0D6,  CLK_S0, 6, 1),
+   DEF_FIXED("s0d12",  R8A77980_CLK_S0D12, CLK_S0,12, 1),
+   DEF_FIXED("s0d24",  R8A77980_CLK_S0D24, CLK_S0,24, 1),
+   DEF_FIXED("s1d1",   R8A77980_CLK_S1D1,  CLK_S1,

[U-Boot] [PATCH v2 1/7] net: sh_eth: Add R8A77980 V3H gether support

[Marek Vasut]

The R8A77980 V3H gether needs a few minor adjustments to the sh_eth
driver, add them to support ethernet on R8A77980.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Nobuhiro Iwamatsu 
---
V2: No change
---
 drivers/net/sh_eth.c | 15 +++
 drivers/net/sh_eth.h |  6 +-
 2 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index da79b766a6..485c4b71ad 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -374,10 +374,16 @@ static void sh_eth_write_hwaddr(struct sh_eth_info 
*port_info,
 static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
 {
struct sh_eth_info *port_info = >port_info[eth->port];
+   unsigned long edmr;
 
/* Configure e-dmac registers */
-   sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
-   (EMDR_DESC | EDMR_EL), EDMR);
+   edmr = sh_eth_read(port_info, EDMR);
+   edmr &= ~EMDR_DESC_R;
+   edmr |= EMDR_DESC | EDMR_EL;
+#if defined(CONFIG_R8A77980)
+   edmr |= EDMR_NBST;
+#endif
+   sh_eth_write(port_info, edmr, EDMR);
 
sh_eth_write(port_info, 0, EESIPR);
sh_eth_write(port_info, 0, TRSCER);
@@ -407,7 +413,7 @@ static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, 
unsigned char *mac)
 
 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
-#elif defined(CONFIG_RCAR_GEN2)
+#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
 #endif
 }
@@ -426,7 +432,7 @@ static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
sh_eth_write(port_info, GECMR_100B, GECMR);
 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
sh_eth_write(port_info, 1, RTRATE);
-#elif defined(CONFIG_RCAR_GEN2)
+#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
val = ECMR_RTM;
 #endif
} else if (phy->speed == 10) {
@@ -931,6 +937,7 @@ static const struct udevice_id sh_ether_ids[] = {
{ .compatible = "renesas,ether-r8a7791" },
{ .compatible = "renesas,ether-r8a7793" },
{ .compatible = "renesas,ether-r8a7794" },
+   { .compatible = "renesas,gether-r8a77980" },
{ }
 };
 
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index e1bbd4913f..564cdaccb7 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -358,6 +358,9 @@ static const u16 
sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 #elif defined(CONFIG_R7S72100)
 #define SH_ETH_TYPE_RZ
 #define BASE_IO_ADDR   0xE8203000
+#elif defined(CONFIG_R8A77980)
+#define SH_ETH_TYPE_GETHER
+#define BASE_IO_ADDR   0xE740
 #endif
 
 /*
@@ -374,6 +377,7 @@ enum EDSR_BIT {
 
 /* EDMR */
 enum DMAC_M_BIT {
+   EDMR_NBST   = 0x80, /* DMA transfer burst mode */
EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
EDMR_SRST   = 0x03, /* Receive/Send reset */
@@ -563,7 +567,7 @@ enum FELIC_MODE_BIT {
ECMR_PRM = 0x0001,
 #ifdef CONFIG_CPU_SH7724
ECMR_RTM = 0x0010,
-#elif defined(CONFIG_RCAR_GEN2)
+#elif defined(CONFIG_RCAR_GEN2) || defined (CONFIG_R8A77980)
ECMR_RTM = 0x0004,
 #endif
 
-- 
2.20.1

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Re: [U-Boot] [PATCH V3 4/4] clk: imx: add i.MX8MM clk driver

[Fabio Estevam]

On Fri, Aug 9, 2019 at 5:02 AM Peng Fan  wrote:
>
> Add i.MX8MM clk driver support.
>
> Signed-off-by: Peng Fan 
> ---
>  drivers/clk/imx/Makefile |   2 +
>  drivers/clk/imx/clk-imx8mm.c | 415 
> +++
>  2 files changed, 417 insertions(+)
>  create mode 100644 drivers/clk/imx/clk-imx8mm.c
>
> diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> index 105a58ca90..5ad7967fe9 100644
> --- a/drivers/clk/imx/Makefile
> +++ b/drivers/clk/imx/Makefile
> @@ -10,3 +10,5 @@ ifdef CONFIG_CLK_IMX8
>  obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o
>  obj-$(CONFIG_IMX8QM) += clk-imx8qm.o
>  endif
> +obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \
> +   clk-composite-8m.o
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
> new file mode 100644
> index 00..a2a85b6a1a
> --- /dev/null
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -0,0 +1,415 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2019 NXP
> + * Peng Fan 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "clk.h"
> +
> +#define PLL_1416X_RATE(_rate, _m, _p, _s)  \
> +   {   \
> +   .rate   =   (_rate),\
> +   .mdiv   =   (_m),   \
> +   .pdiv   =   (_p),   \
> +   .sdiv   =   (_s),   \
> +   }
> +
> +#define PLL_1443X_RATE(_rate, _m, _p, _s, _k)  \
> +   {   \
> +   .rate   =   (_rate),\
> +   .mdiv   =   (_m),   \
> +   .pdiv   =   (_p),   \
> +   .sdiv   =   (_s),   \
> +   .kdiv   =   (_k),   \
> +   }
> +
> +static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
> +   PLL_1416X_RATE(18U, 225, 3, 0),
> +   PLL_1416X_RATE(16U, 200, 3, 0),
> +   PLL_1416X_RATE(12U, 300, 3, 1),
> +   PLL_1416X_RATE(10U, 250, 3, 1),
> +   PLL_1416X_RATE(8U,  200, 3, 1),
> +   PLL_1416X_RATE(75000U,  250, 2, 2),
> +   PLL_1416X_RATE(7U,  350, 3, 2),
> +   PLL_1416X_RATE(6U,  300, 3, 2),
> +};
> +
> +static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
> +   PLL_1443X_RATE(65000U, 325, 3, 2, 0),
> +};
> +
> +static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
> +   .type = PLL_1443X,
> +   .rate_table = imx8mm_drampll_tbl,
> +   .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
> +};
> +
> +static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
> +   .type = PLL_1416X,
> +   .rate_table = imx8mm_pll1416x_tbl,
> +   .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
> +};
> +
> +static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
> +   .type = PLL_1416X,
> +   .rate_table = imx8mm_pll1416x_tbl,
> +   .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
> +};
> +
> +static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", 
> "dummy", };
> +static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", 
> };
> +static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
> +static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", 
> };
> +static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", 
> };
> +static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", 
> };
> +
> +static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", 
> "sys_pll2_500m", "sys_pll2_1000m",
> +   "sys_pll1_800m", "sys_pll1_400m", 
> "audio_pll1_out", "sys_pll3_out", };
> +
> +static const char *imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", 
> "sys_pll1_800m", "sys_pll1_400m",
> +   "sys_pll2_125m", "sys_pll3_out", 
> "audio_pll1_out", "video_pll1_out", };
> +
> +static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", 
> "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
> +"sys_pll2_200m", 
> "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
> +
> +static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", 
> "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
> +  "sys_pll1_133m", 
> "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
> +
> +static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", 
> "sys_pll1_800m", "sys_pll2_500m",
> +  "sys_pll3_out", "sys_pll1_266m", 
> "audio_pll2_out", "sys_pll1_100m", 

[U-Boot] [PATCH] sunxi: video: HDMI: Fix LCD clock divider

[Mark Kettenis]

Currently we may end up with an LCD clock divider that differs from
the HDMI PHY clock divider if we can't exactly match the pixel clock.
Fix this by using DIV_ROUND_UP to calculate the divider.  This works
since the PLL is chosen such that the resulting pixel clock is
never higher than the requested pixel clock.

Fixes: 1feed358ed15 ("sunxi: video: HDMI: Fix clock setup")

Signed-off-by: Mark Kettenis 
---
 drivers/video/sunxi/sunxi_dw_hdmi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c 
b/drivers/video/sunxi/sunxi_dw_hdmi.c
index cec23295b5..66a319187c 100644
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -254,7 +254,7 @@ static void sunxi_dw_hdmi_lcdc_init(int mux, const struct 
display_timing *edid,
 {
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-   int div = clock_get_pll3() / edid->pixelclock.typ;
+   int div = DIV_ROUND_UP(clock_get_pll3(), edid->pixelclock.typ);
struct sunxi_lcdc_reg *lcdc;
 
if (mux == 0) {
-- 
2.22.0

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[U-Boot] [RFC] enforce CONFIG_DM=y

[Heinrich Schuchardt]

The time lines set force in doc/driver-model/migration.rst for different
subsystems to move to the driver model have been passed.

I ran a test on Travis CI
https://travis-ci.org/xypron2/u-boot/builds/569776600
that showed only 8 boards remain that cannot be built with CONFIG_DM=y.

H2200
* h2200

Renesas
* sh7757lcr
* sh7752evb
* r2dplus
* sh7753evb
* sh7763rdp
* MigoR
* r7780mp.

I think it is time that we enforce CONFIG_DM=y in U-Boot and remove
boards that do not support it.

Best regards

Heinrich
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Re: [U-Boot] [PATCH] board_f: reserve noncached space below malloc area

[Vikas MANOCHA]

Hi Simon,

> -Original Message-
> From: Simon Glass 
> Sent: Friday, August 9, 2019 10:00 AM
> To: Vikas MANOCHA 
> Cc: U-Boot Mailing List ; Bin Meng
> ; CITOOLS  revi...@lists.codex.cro.st.com>; Mario Six ; Patrick
> DELAUNAY 
> Subject: Re: [PATCH] board_f: reserve noncached space below malloc area
> 
> Hi Vikas,
> 
> On Thu, 8 Aug 2019 at 18:24, Vikas Manocha 
> wrote:
> >
> > Noncached area at present is being initialized to random space after
> > malloc area. It works in most the cases as it goes to stack area &
> > stack is not overwriting it being far from it.
> 
> Please can you add a motivation for this patch and what it does.

We are not reserving non-cached memory area (like for malloc, gd etc before 
relocation). 
With this patch we are reserving area just below memory area allocated to 
dynamic allocation.

> 
> >
> > Signed-off-by: Vikas Manocha 
> > ---
> >  common/board_f.c | 13 +
> >  1 file changed, 13 insertions(+)
> >
> > diff --git a/common/board_f.c b/common/board_f.c index
> > 59745d5..4910051 100644
> > --- a/common/board_f.c
> > +++ b/common/board_f.c
> > @@ -439,12 +439,25 @@ static int reserve_uboot(void)
> > return 0;
> >  }
> >
> > +#ifdef CONFIG_SYS_NONCACHED_MEMORY
> > +static int reserve_noncached(void)
> > +{
> > +   /* round down to SECTION SIZE (typicaly 1MB) limit */
> > +   gd->start_addr_sp &= ~(MMU_SECTION_SIZE - 1);
> > +   gd->start_addr_sp -= CONFIG_SYS_NONCACHED_MEMORY;
> 
> blank line before return.

Sure, I will add it in v2.

> > +   return 0;
> > +}
> > +#endif
> > +
> >  /* reserve memory for malloc() area */  static int
> > reserve_malloc(void)  {
> > gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
> > debug("Reserving %dk for malloc() at: %08lx\n",
> >   TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
> > +#ifdef CONFIG_SYS_NONCACHED_MEMORY
> > +   reserve_noncached(void);
> > +#endif
> 
> How about a new function for this (with the #ifndef inside it), and a debug()?

That is what I did first but this (non cached) memory area being tied to just 
below malloc, having it here enforces this contiguity.

> 
> Also I see noncached_init() calculates the size which seems brittle.
> Should it be added to gd?

Good point, creating new entry/ies in gd for it would make it bit cleaner but 
useless after initialization.
Static variables are used for this non cached memory init & allocation. It is 
just like for malloc, we don’t have entry in gd for it & I
think the reason is same.

Cheers,
Vikas

> 
> > return 0;
> >  }
> >
> > --
> > 2.7.4
> >
> 
> Regards,
> Simon
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[U-Boot] Pull request, u-boot-tegra/master

[Tom Warren]

Tom,

Please pull u-boot-tegra/master into U-Boot/master. Thanks!

All Tegra builds are OK on my system, and Igor has verified the Apalis
patches.

The following changes since commit 163bc1e4da425015000dd3f8f128aec994da9586:

  Merge tag 'mmc-8-9' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
(2019-08-09 07:29:54 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-tegra.git master

for you to fetch changes up to bd20266d1923f1230ed15020fbb12aa56f3f46b7:

  apalis-tk1: configs: remove legacy usbboot command (2019-08-09 10:01:35
-0700)


Dominik Sliwa (2):
  apalis-tk1/t30: colibri_t30: display reset reason
  apalis-tk1: remove non-essential power rails on boot

Igor Opaniuk (7):
  colibri/apalis tegra: drop DFU support
  apalis-tk1: set apalis gpio 8 aka fan_en
  apalis-tk1: provide proper USB vendor id
  apalis-tk1: enable user debug by default
  apalis-tk1: add pcie_aspm=off to defargs
  apalis-tk1: switch to zImage
  apalis-tk1: configs: remove legacy usbboot command

Marcel Ziswiler (3):
  apalis-tk1: do not explicitly release reset_moci#
  apalis-tk1: remove default vesa vga mode from vidargs
  apalis-tk1: support v1.2 hardware revision

Simon Glass (3):
  sound: snow: Add the binding file for snow
  sound: tegra: Add the binding file for tegra-audio
  sound: Add codec enable to the sound bindings

Trent Piepho (1):
  mmc: Move tegra loopback disable option to be under tegra

 arch/arm/dts/tegra124-apalis.dts   | 89
--
 arch/arm/mach-tegra/sys_info.c | 32 +---
 arch/arm/mach-tegra/tegra124/cpu.c | 45 +++
 board/toradex/apalis-tk1/apalis-tk1.c  | 47 
 board/toradex/apalis-tk1/as3722_init.c | 23 ++
 .../toradex/apalis-tk1/pinmux-config-apalis-tk1.h  | 21 +++--
 configs/apalis-tk1_defconfig   |  7 +-
 configs/apalis_t30_defconfig   |  3 -
 configs/colibri_t20_defconfig  |  3 -
 configs/colibri_t30_defconfig  |  3 -
 doc/device-tree-bindings/sound/intel-hda.txt   |  1 +
 .../sound/nvidia,tegra-audio-max98090.txt  | 54 +
 doc/device-tree-bindings/sound/snow.txt| 32 
 drivers/mmc/Kconfig| 22 +++---
 include/configs/apalis-tk1.h   | 44 ---
 15 files changed, 310 insertions(+), 116 deletions(-)
 create mode 100644
doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt
 create mode 100644 doc/device-tree-bindings/sound/snow.txt
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Re: [U-Boot] [PATCH v1] apalis-tk1: support v1.2 hardware revision

[Tom Warren]

Igor,

-Original Message-
From: Igor Opaniuk  
Sent: Friday, August 9, 2019 3:38 AM
To: Tom Warren 
Cc: Marcel Ziswiler ; Philippe Schenker 
; Oleksandr Suvorov 
; Dominik Sliwa ; 
Igor Opaniuk ; Albert Aribaud 
; Thierry Reding ; U-Boot 
Mailing List 
Subject: Re: [PATCH v1] apalis-tk1: support v1.2 hardware revision

Hi Tom,

On Fri, Aug 9, 2019 at 1:22 PM Igor Opaniuk  wrote:
>
> From: Marcel Ziswiler 
>
> Support the V1.2 hardware revision with the following pin muxing
> changes:
>
> Ddc_scl_pv4 and ddc_sda_pv5 previously used as Apalis GPIO3 and GPIO4 
> are now used as DDC pins.
>
> Gen2_i2c_scl_pt5 and gen2_i2c_sda_pt6 previously used as DDC pins are 
> now used as USB power enable signals.
>
> Usb_vbus_en0_pn4 and usb_vbus_en1_pn5 previously used as USB power 
> enable signals are now used as GPIO3 and GPIO4.
>
> Additionally a new device tree file tegra124-apalis-v1.2-eval.dtb is 
> loaded on V1.2 and later modules and resp. USB power enable signals 
> activated.
>
> Signed-off-by: Marcel Ziswiler 
> Signed-off-by: Igor Opaniuk 
> ---
>
>  arch/arm/dts/tegra124-apalis.dts  | 89 ++-
>  board/toradex/apalis-tk1/apalis-tk1.c | 37 
>  .../apalis-tk1/pinmux-config-apalis-tk1.h | 19 ++--
>  configs/apalis-tk1_defconfig  |  2 +-
>  include/configs/apalis-tk1.h  | 12 ++-
>  5 files changed, 103 insertions(+), 56 deletions(-)
>
> diff --git a/arch/arm/dts/tegra124-apalis.dts 
> b/arch/arm/dts/tegra124-apalis.dts
> index a962c0a2f0..08184ab3ac 100644
> --- a/arch/arm/dts/tegra124-apalis.dts
> +++ b/arch/arm/dts/tegra124-apalis.dts
> @@ -1,5 +1,5 @@
>  /*
> - * Copyright 2016 Toradex AG
> + * Copyright 2016-2019 Toradex AG
>   *
>   * This file is dual-licensed: you can use it either under the terms
>   * of the GPL or the X11 license, at your option. Note that this dual 
> @@ -230,19 +230,21 @@
> };
>
> /* Apalis GPIO */
> -   ddc_scl_pv4 {
> -   nvidia,pins = "ddc_scl_pv4";
> +   usb_vbus_en0_pn4 {
> +   nvidia,pins = "usb_vbus_en0_pn4";
> nvidia,function = "rsvd2";
> nvidia,pull = ;
> nvidia,tristate = ;
> nvidia,enable-input = 
> ;
> +   nvidia,open-drain = 
> + ;
> };
> -   ddc_sda_pv5 {
> -   nvidia,pins = "ddc_sda_pv5";
> +   usb_vbus_en1_pn5 {
> +   nvidia,pins = "usb_vbus_en1_pn5";
> nvidia,function = "rsvd2";
> nvidia,pull = ;
> nvidia,tristate = ;
> nvidia,enable-input = 
> ;
> +   nvidia,open-drain = 
> + ;
> };
> pex_l0_rst_n_pdd1 {
> nvidia,pins = "pex_l0_rst_n_pdd1"; @@ 
> -333,40 +335,40 @@
> nvidia,open-drain = ;
> };
>
> -   /* Apalis I2C2 (DDC) */
> -   gen2_i2c_scl_pt5 {
> -   nvidia,pins = "gen2_i2c_scl_pt5";
> -   nvidia,function = "i2c2";
> +   /* Apalis I2C3 (CAM) */
> +   cam_i2c_scl_pbb1 {
> +   nvidia,pins = "cam_i2c_scl_pbb1";
> +   nvidia,function = "i2c3";
> nvidia,pull = ;
> nvidia,tristate = ;
> nvidia,enable-input = ;
> nvidia,open-drain = ;
> };
> -   gen2_i2c_sda_pt6 {
> -   nvidia,pins = "gen2_i2c_sda_pt6";
> -   nvidia,function = "i2c2";
> +   cam_i2c_sda_pbb2 {
> +   nvidia,pins = "cam_i2c_sda_pbb2";
> +   nvidia,function = "i2c3";
> nvidia,pull = ;
> nvidia,tristate = ;
> nvidia,enable-input = ;
> nvidia,open-drain = ;
> };
>
> -   /* Apalis I2C3 (CAM) */
> -   cam_i2c_scl_pbb1 {
> -   nvidia,pins = "cam_i2c_scl_pbb1";
> -   nvidia,function = "i2c3";
> +   /* Apalis I2C4 (DDC) */
> +   ddc_scl_pv4 {
> +   nvidia,pins = "ddc_scl_pv4";
> +   nvidia,function = 

Re: [U-Boot] RFC: Migration target date for DM_ETH

[Simon Glass]

Hi Heinrich,

On Fri, 9 Aug 2019 at 00:31, Heinrich Schuchardt  wrote:
>
> Currently dozens of boards still do not use the driver model for the
> network devices. This makes integration between devices in the UEFI
> sub-system with the U-Boot devices complicated.
>
> See: https://travis-ci.org/xypron2/u-boot/builds/569675547
>
> In doc/driver-model/migration.rst I am missing a migration target day
> for DM_ETH. Shouldn't define one? 2020-07 should be realistic.

Yes, good idea.

Also we need to convert the Ethernet PHYs to DM.

Regards,
Simon
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Re: [U-Boot] [PATCH] board_f: reserve noncached space below malloc area

[Simon Glass]

Hi Vikas,

On Thu, 8 Aug 2019 at 18:24, Vikas Manocha  wrote:
>
> Noncached area at present is being initialized to random space after malloc
> area. It works in most the cases as it goes to stack area & stack is not
> overwriting it being far from it.

Please can you add a motivation for this patch and what it does.

>
> Signed-off-by: Vikas Manocha 
> ---
>  common/board_f.c | 13 +
>  1 file changed, 13 insertions(+)
>
> diff --git a/common/board_f.c b/common/board_f.c
> index 59745d5..4910051 100644
> --- a/common/board_f.c
> +++ b/common/board_f.c
> @@ -439,12 +439,25 @@ static int reserve_uboot(void)
> return 0;
>  }
>
> +#ifdef CONFIG_SYS_NONCACHED_MEMORY
> +static int reserve_noncached(void)
> +{
> +   /* round down to SECTION SIZE (typicaly 1MB) limit */
> +   gd->start_addr_sp &= ~(MMU_SECTION_SIZE - 1);
> +   gd->start_addr_sp -= CONFIG_SYS_NONCACHED_MEMORY;

blank line before return.
> +   return 0;
> +}
> +#endif
> +
>  /* reserve memory for malloc() area */
>  static int reserve_malloc(void)
>  {
> gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
> debug("Reserving %dk for malloc() at: %08lx\n",
>   TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
> +#ifdef CONFIG_SYS_NONCACHED_MEMORY
> +   reserve_noncached(void);
> +#endif

How about a new function for this (with the #ifndef inside it), and a debug()?

Also I see noncached_init() calculates the size which seems brittle.
Should it be added to gd?

> return 0;
>  }
>
> --
> 2.7.4
>

Regards,
Simon
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Re: [U-Boot] [PATCH V3 3/4] clk: imx: add i.MX8M composite clk support

[Fabio Estevam]

On Fri, Aug 9, 2019 at 5:02 AM Peng Fan  wrote:

> + * The clk are not binded to a dev, because it is part of composite clk

s/binded/bound

> + * use composite clk to get dev
> + */
> +static ulong imx8m_clk_composite_divider_set_rate(struct clk *clk,
> + unsigned long rate)
> +{
> +   struct clk_divider *divider = (struct clk_divider 
> *)to_clk_divider(clk);
> +   struct clk_composite *composite = (struct clk_composite *)clk->data;
> +   ulong parent_rate = clk_get_parent_rate(>clk);
> +   int prediv_value;
> +   int div_value;
> +   int ret;
> +   u32 val;
> +
> +   ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,
> +  _value, _value);
> +   if (ret)
> +   return -EINVAL;

What about returning ret directly instead?


> +struct clk *imx8m_clk_composite_flags(const char *name,
> + const char * const *parent_names,
> + int num_parents, void __iomem *reg,
> + unsigned long flags)
> +{
> +   struct clk *clk = ERR_PTR(-ENOMEM);
> +   struct clk_divider *div = NULL;
> +   struct clk_gate *gate = NULL;
> +   struct clk_mux *mux = NULL;

Why all these NULL assignments?

> +
> +   mux = kzalloc(sizeof(*mux), GFP_KERNEL);
> +   if (!mux)
> +   goto fail;

It would be better like this:

   mux = kzalloc(sizeof(*mux), GFP_KERNEL);
   if (!mux)
   return ERR_PTR(-ENOMEM);

> +
> +   mux->reg = reg;
> +   mux->shift = PCG_PCS_SHIFT;
> +   mux->mask = PCG_PCS_MASK;
> +   mux->num_parents = num_parents;
> +   mux->flags = flags;
> +   mux->parent_names = parent_names;
> +
> +   div = kzalloc(sizeof(*div), GFP_KERNEL);
> +   if (!div)
> +   goto fail;
> +
> +   div->reg = reg;
> +   div->shift = PCG_PREDIV_SHIFT;
> +   div->width = PCG_PREDIV_WIDTH;
> +   div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
> +
> +   gate = kzalloc(sizeof(*gate), GFP_KERNEL);
> +   if (!gate)
> +   goto fail;
> +
> +   gate->reg = reg;
> +   gate->bit_idx = PCG_CGC_SHIFT;
> +   gate->flags = flags;
> +
> +   clk = clk_register_composite(NULL, name,
> +parent_names, num_parents,
> +>clk, _mux_ops, >clk,
> +_clk_composite_divider_ops,
> +>clk, _gate_ops, flags);
> +   if (IS_ERR(clk))
> +   goto fail;
> +
> +   return clk;
> +
> +fail:
> +   kfree(gate);
> +   kfree(div);
> +   kfree(mux);
> +   return ERR_CAST(clk);

ERR_CAST(clk) is only valid when for the IS_ERR(clk) path.

Please rework the error handling.
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Re: [U-Boot] [PATCH V3 2/4] clk: imx: add pll14xx driver

[Fabio Estevam]

On Fri, Aug 9, 2019 at 5:02 AM Peng Fan  wrote:
>
> Add pll14xx driver

Please expand this commit log a bit by adding in which SoC it is used,
where this driver comes from (Linux, internal U-Boot tree, etc).
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Re: [U-Boot] [PATCH V3 1/4] clk: imx: add Kconfig entry for i.MX8MM

[Fabio Estevam]

Hi Peng,

On Fri, Aug 9, 2019 at 5:02 AM Peng Fan  wrote:
>
> Add Kconfig entry for i.MX8MM
>
> Signed-off-by: Peng Fan 
> ---
>  drivers/clk/Kconfig |  4 ++--
>  drivers/clk/imx/Kconfig | 16 
>  2 files changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index a3f0171b45..fce595b4b3 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -48,7 +48,7 @@ config CLK_BOSTON
>
>  config SPL_CLK_CCF
> bool "SPL Common Clock Framework [CCF] support "
> -   depends on SPL_CLK_IMX6Q
> +   depends on SPL_CLK_IMX6Q || ARCH_IMX8M

I am wondering why this depends on i.MX. Shouldn't it be SoC agnostic?

> help
>   Enable this option if you want to (re-)use the Linux kernel's Common
>   Clock Framework [CCF] code in U-Boot's SPL.
> @@ -62,7 +62,7 @@ config SPL_CLK_COMPOSITE_CCF
>
>  config CLK_CCF
> bool "Common Clock Framework [CCF] support "
> -   depends on CLK_IMX6Q || SANDBOX_CLK_CCF
> +   depends on CLK_IMX6Q || ARCH_IMX8M || SANDBOX_CLK_CCF

Same here.

It doesn't look like a good idea to keep expanding this Kconfig every
time a new SoC wants to use the CCF.
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Re: [U-Boot] drivers: net: driver for MDIO muxes controlled over I2C

[Joe Hershberger]

On Thu, Aug 8, 2019 at 3:16 PM Alex Marginean  wrote:
>
> Hi Joe,
>
> On 7/25/2019 9:41 PM, Joe Hershberger wrote:
> > Hi Alex,
> >
> > https://patchwork.ozlabs.org/patch/1132514/ was applied to 
> > http://git.denx.de/?p=u-boot/u-boot-net.git
>
> can you please check this commit (d9a9174), I think mdio_mux_i2creg.c
> was lost at merge.
> Do you want me to send a new patch with just the .c file?

Yes, it seems you're right... I'll reapply the original.

Apologies,
-Joe

>
> Thank you!
> Alex
>
>
> >
> > Thanks!
> > -Joe
> > ___
> > U-Boot mailing list
> > U-Boot@lists.denx.de
> > https://lists.denx.de/listinfo/u-boot
> >
>
> ___
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Re: [U-Boot] [PATCH v2 5/5] imx: add i.MX6ULZ board

[Fabio Estevam]

On Thu, Aug 8, 2019 at 6:55 AM Peng Fan  wrote:
>
> Add i.MX6ULZ board support. the i.MX6ULZ is SW compatible
> with i.MX6ULL. so most code of i.MX6ULL can be reused
> by i.MX6ULZ.
>
> Signed-off-by: Peng Fan 

Reviewed-by: Fabio Estevam 
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Re: [U-Boot] [PATCH v2 3/5] arm: dts: import dts for i.MX6ULZ

[Fabio Estevam]

On Thu, Aug 8, 2019 at 6:55 AM Peng Fan  wrote:
>
> Import kernel dts for i.MX6ULZ from
> commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of 
> git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux")
>
> Signed-off-by: Peng Fan 

Reviewed-by: Fabio Estevam 
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Re: [U-Boot] [PATCH v2 4/5] imx: add i.MX6ULZ cpu type

[Fabio Estevam]

On Thu, Aug 8, 2019 at 6:55 AM Peng Fan  wrote:
>
> Add i.MX6ULZ cpu type and helper.
>
> Signed-off-by: Peng Fan 

Reviewed-by: Fabio Estevam 
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Re: [U-Boot] [PATCH v2 2/5] arm: dts: sync dts for i.MX6ULL

[Fabio Estevam]

On Thu, Aug 8, 2019 at 6:55 AM Peng Fan  wrote:
>
> Sync kernel dts for i.MX6ULL from
> commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of 
> git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux")
>
> Signed-off-by: Peng Fan 

Reviewed-by: Fabio Estevam 
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Re: [U-Boot] [PATCH v2 1/5] arm: dts: sync dts for i.MX6UL

[Fabio Estevam]

On Thu, Aug 8, 2019 at 6:55 AM Peng Fan  wrote:
>
> Sync kernel dts for i.MX6UL from
> commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of 
> git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux")

Just a nit: I find it more readable when the version is stated like
5.2.8, 5.3-rc3, etc.

Reviewed-by: Fabio Estevam 
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[U-Boot] [PATCH] cmd: avb: Fix requested partitions list

[Sam Protsenko]

The requested_partitions[] array should contain only boot partitions.
Usually it's only 'boot' partition, as can be seen in [1]. Also, seems
like the requested_partitions[] are only used when there is no 'vbmeta'
partition [2], which is not a regular use-case.

Make requested_partitions[] contain only 'boot' partition as it was
supposed to be, and also make that array to be a local in
do_avb_verify_part() function, as nobody else needs that.

[1] 
https://android.googlesource.com/platform/external/avb/+/master/test/avb_slot_verify_unittest.cc#108
[2] 
https://android.googlesource.com/platform/external/avb/+/master/libavb/avb_slot_verify.c#1461

Signed-off-by: Sam Protsenko 
---
 cmd/avb.c | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/cmd/avb.c b/cmd/avb.c
index d1942d6605..8f2bb85fce 100644
--- a/cmd/avb.c
+++ b/cmd/avb.c
@@ -14,11 +14,6 @@
 #define AVB_BOOTARGS   "avb_bootargs"
 static struct AvbOps *avb_ops;
 
-static const char * const requested_partitions[] = {"boot",
-"system",
-"vendor",
-NULL};
-
 int do_avb_init(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
unsigned long mmc_dev;
@@ -231,6 +226,7 @@ int do_avb_get_uuid(cmd_tbl_t *cmdtp, int flag,
 int do_avb_verify_part(cmd_tbl_t *cmdtp, int flag,
   int argc, char *const argv[])
 {
+   const char * const requested_partitions[] = {"boot", NULL};
AvbSlotVerifyResult slot_result;
AvbSlotVerifyData *out_data;
char *cmdline;
-- 
2.20.1

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Re: [U-Boot] Please pull u-boot-mmc-20190809

[Tom Rini]

On Fri, Aug 09, 2019 at 09:38:21AM +, Peng Fan wrote:

> Hi Tom,
> 
> Please pull u-boot-mmc tree, update:
>  mmc test fix
>  sdhci driver fix
> 
> CI: https://travis-ci.org/MrVan/u-boot/builds/569664807
> 
> Thanks,
> Peng.
> 
> The following changes since commit fef408679b2f634ebfd6298d9fc99db99e60fb1d:
> 
>   Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell (2019-08-08 
> 09:19:08 -0400)
> 
> are available in the Git repository at:
> 
>   https://gitlab.denx.de/u-boot/custodians/u-boot-mmc.git tags/mmc-8-9
> 
> for you to fetch changes up to d569b4b0a4f34969f83ef8ec89b44f406553e72b:
> 
>   mmc: tangier_sdhci: fix uninitialized pointer deref on probe (2019-08-09 
> 13:45:25 +0800)
> 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] Pull request: u-boot-rockchip-20190809

[Tom Rini]

On Fri, Aug 09, 2019 at 03:10:31PM +0800, Kever Yang wrote:

> Hi Tom,
> 
> Please pull the rockchip update:
> - Add rk3399 boards Khadas Edge/-V/-Captain
> - Add fully souce code support for rk3328 including TPL/DRAM init
> - Enable boot from eMMC for rk3399 rock960/ficus boards
> - turn on the IO supply for dw_mmc
> 
> Travis:
> https://travis-ci.org/keveryang/u-boot/builds/567879982
> 
> Thanks,
> - Kever
> 
> The following changes since commit d0d07ba86afc8074d79e436b1ba4478fa0f0c1b5:
> 
>   Prepare v2019.10-rc1 (2019-07-29 21:16:16 -0400)
> 
> are available in the Git repository at:
> 
>   https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip.git 
> tags/u-boot-rockchip-20190809
> 
> for you to fetch changes up to 6a452e5bd33cf8f4e851445f29ab94b66485700a:
> 
>   doc: rockchip: Adapt Pine64 Rock64 board instructions (2019-08-05 21:18:35 
> +0800)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] Booting Linux kernel on x86_64

[Bin Meng]

+Simon, Andy,

Hi Ryan,

On Fri, Aug 9, 2019 at 11:52 PM Ryan Wilkins  wrote:
>
> Hello,
>
> I’m trying to get u-boot 2019.04 to execute the Linux 4.19.55 kernel from 
> u-boot on a generic Core i5 with 8 GB RAM and having issues.  The kernel that 
> I’m trying to boot will boot fine from GRUB so I know it works but starting 
> from u-boot just shows “Starting kernel” and the system appears to freeze.

Which specific Core i5 processor are you using? And what's the U-Boot
target for that board? Is that U-Boot as EFI payload or something? Did
you set up U-Boot environment variable "bootargs" with Linux kernel's
command line, e.g.: I think you need at least specify console=tty0 or
ttyS0?

>
> my bootcmd is
>   scsi reset; ext2load scsi 0:5 0x0400 bzImage; ext2load scsi 0:5 
> 0x0800 rootfs.cpio.uboot; zboot 0400 0 0800 ${filesize}
>
> The kernel bzip2 compressed file size is around 6 MB and the rootfs is about 
> 125 MB.
> The kernel and rootfs are loaded in OK and running zboot finds the kernel OK. 
>  The rootfs is a gzip compressed cpio with uboot wrapper.  I’m using 
> buildroot 2019.02 to create the system and rootfs.
>
> You might be asking why not just go with GRUB instead and the reason is the 
> company I’m working for has a lot of ARM-based devices out that all utilize 
> u-boot of which I’m quite familiar with, but this particular project is based 
> on the Intel Core i5.  It was decided to keep the system as similar as 
> possible to the ARM-based boards to keep support differences as minimal as 
> possible.  A number of utilities that we have already written are meant to 
> interact with the u-boot environment and depend on it.
>

Good to know!

> I realize this is rather sparse with information, but rather than make an 
> unnecessarily long email does anyone have any ideas of what to check or try 
> or requests for more information?
>
> Thanks in advance for any assistance.
>

Regards,
Bin
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[U-Boot] [PATCH] cmd: pxe: Use internal FDT if FDT file isn't found in FDTDIR

[Антон Леонтьев]

Original commit c61d94d86035 ("pxe: implement fdtdir extlinux.conf tag")
states, that if FDT file cannot be retrieved then FDT packaged in
firmware should be used.

If FDT file cannot be retrieved and it is specified explicitly using
FDT keyword then the label is skipped. If it cannot be found in
FDTDIR then internal FDT is tried first.

Signed-off-by: Anton Leontiev 
---
 cmd/pxe.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/cmd/pxe.c b/cmd/pxe.c
index 1dd0a74ea3..8175e342ee 100644
--- a/cmd/pxe.c
+++ b/cmd/pxe.c
@@ -794,9 +794,13 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label 
*label)
int err = get_relfile_envaddr(cmdtp, fdtfile, 
"fdt_addr_r");
free(fdtfilefree);
if (err < 0) {
-   printf("Skipping %s for failure retrieving 
fdt\n",
-   label->name);
-   goto cleanup;
+   bootm_argv[3] = NULL;
+
+   if (label->fdt) {
+   printf("Skipping %s for failure 
retrieving FDT\n",
+  label->name);
+   goto cleanup;
+   }
}
} else {
bootm_argv[3] = NULL;
-- 
2.21.0
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Re: [U-Boot] [PATCH v2 1/5] arm: dts: sync dts for i.MX6UL

[Ye Li]

> Sync kernel dts for i.MX6UL from
> commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of 
> git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux")
> 
> Signed-off-by: Peng Fan 
> ---
> 
> V2:
>  None
> 
>  arch/arm/dts/imx6ul-14x14-evk.dts| 422 +---
>  arch/arm/dts/imx6ul-14x14-evk.dtsi   | 531 
> +++
>  arch/arm/dts/imx6ul-pinfunc.h| 175 +-
>  arch/arm/dts/imx6ul.dtsi | 301 --
>  include/dt-bindings/clock/imx6ul-clock.h |  50 +--
>  5 files changed, 863 insertions(+), 616 deletions(-)
>  create mode 100644 arch/arm/dts/imx6ul-14x14-evk.dtsi
> 
> diff --git a/arch/arm/dts/imx6ul-14x14-evk.dts 
> b/arch/arm/dts/imx6ul-14x14-evk.dts
> index a642d77654..2438669f14 100644
> --- a/arch/arm/dts/imx6ul-14x14-evk.dts
> +++ b/arch/arm/dts/imx6ul-14x14-evk.dts
> @@ -1,427 +1,13 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright (C) 2015 Freescale Semiconductor, Inc.
> - * Copyright 2017-2018 NXP
> - */
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (C) 2015 Freescale Semiconductor, Inc.
>  
>  /dts-v1/;
>  
>  #include "imx6ul.dtsi"
> +#include "imx6ul-14x14-evk.dtsi"
>  
>  / {
>   model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
>   compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
> -
> - aliases {
> - spi5 = _spi;
> - };
> -
> - chosen {
> - stdout-path = 
> - };
> -
> - memory {
> - reg = <0x8000 0x2000>;
> - };
> -
> - regulators {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - reg_sd1_vmmc: regulator@1 {
> - compatible = "regulator-fixed";
> - regulator-name = "VSD_3V3";
> - regulator-min-microvolt = <330>;
> - regulator-max-microvolt = <330>;
> - gpio = < 9 GPIO_ACTIVE_HIGH>;
> - off-on-delay = <2>;
> - enable-active-high;
> - };
> -
> - reg_can_3v3: regulator@0 {
> - compatible = "regulator-fixed";
> - reg = <0>;
> - regulator-name = "can-3v3";
> - regulator-min-microvolt = <330>;
> - regulator-max-microvolt = <330>;
> - gpios = <_spi 3 GPIO_ACTIVE_LOW>;
> - };
> -
> - reg_gpio_dvfs: regulator-gpio {
> - compatible = "regulator-gpio";
> - pinctrl-names = "default";
> - pinctrl-0 = <_dvfs>;
> - regulator-min-microvolt = <130>;
> - regulator-max-microvolt = <140>;
> - regulator-name = "gpio_dvfs";
> - regulator-type = "voltage";
> - gpios = < 3 GPIO_ACTIVE_HIGH>;
> - states = <130 0x1 140 0x0>;
> - };
> - };
> -
> - soft_spi: soft-spi {
> - compatible = "spi-gpio";
> - pinctrl-names = "default";
> - pinctrl-0 = <_spi4>;
> - pinctrl-assert-gpios = < 8 GPIO_ACTIVE_LOW>;
> - status = "okay";
> - gpio-sck = < 11 0>;
> - gpio-mosi = < 10 0>;
> - cs-gpios = < 7 0>;
> - num-chipselects = <1>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - gpio_spi: gpio_spi@0 {
> - compatible = "fairchild,74hc595";
> - gpio-controller;
> - #gpio-cells = <2>;
> - reg = <0>;
> - registers-number = <1>;
> - registers-default = /bits/ 8 <0x57>;
> - spi-max-frequency = <10>;
> - };
> - };
> -};
> -
> - {
> - pinctrl-names = "default";
> - pinctrl-0 = <_enet1>;
> - phy-mode = "rmii";
> - phy-handle = <>;
> - status = "okay";
> -};
> -
> - {
> - pinctrl-names = "default";
> - pinctrl-0 = <_enet2>;
> - phy-mode = "rmii";
> - phy-handle = <>;
> - status = "okay";
> -
> - mdio {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - ethphy0: ethernet-phy@2 {
> - compatible = "ethernet-phy-ieee802.3-c22";
> - reg = <2>;
> - };
> -
> - ethphy1: ethernet-phy@1 {
> - compatible = "ethernet-phy-ieee802.3-c22";
> - reg = <1>;
> - };
> - };
> -};
> -
> - {
> - clock-frequency = <10>;
> - pinctrl-names = "default", "gpio";
> - pinctrl-0 = <_i2c1>;
> - pinctrl-1 = <_i2c1_gpio>;
> - scl-gpios = < 28 GPIO_ACTIVE_HIGH>;
> - sda-gpios = < 29 GPIO_ACTIVE_HIGH>;
> - 

[U-Boot] Booting Linux kernel on x86_64

[Ryan Wilkins]

Hello,

I’m trying to get u-boot 2019.04 to execute the Linux 4.19.55 kernel from 
u-boot on a generic Core i5 with 8 GB RAM and having issues.  The kernel that 
I’m trying to boot will boot fine from GRUB so I know it works but starting 
from u-boot just shows “Starting kernel” and the system appears to freeze.

my bootcmd is
  scsi reset; ext2load scsi 0:5 0x0400 bzImage; ext2load scsi 0:5 
0x0800 rootfs.cpio.uboot; zboot 0400 0 0800 ${filesize}

The kernel bzip2 compressed file size is around 6 MB and the rootfs is about 
125 MB.
The kernel and rootfs are loaded in OK and running zboot finds the kernel OK.  
The rootfs is a gzip compressed cpio with uboot wrapper.  I’m using buildroot 
2019.02 to create the system and rootfs.

You might be asking why not just go with GRUB instead and the reason is the 
company I’m working for has a lot of ARM-based devices out that all utilize 
u-boot of which I’m quite familiar with, but this particular project is based 
on the Intel Core i5.  It was decided to keep the system as similar as possible 
to the ARM-based boards to keep support differences as minimal as possible.  A 
number of utilities that we have already written are meant to interact with the 
u-boot environment and depend on it.

I realize this is rather sparse with information, but rather than make an 
unnecessarily long email does anyone have any ideas of what to check or try or 
requests for more information?

Thanks in advance for any assistance.

Ryan Wilkins
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Re: [U-Boot] [PATCH 0/3] Intel FPGA PCIe fixes

[Tom Rini]

On Fri, Aug 09, 2019 at 05:04:43PM +0800, Ley Foon Tan wrote:
> On Tue, Jun 11, 2019 at 8:30 AM Ley Foon Tan  wrote:
> >
> > On Fri, May 24, 2019 at 10:30 AM Ley Foon Tan  
> > wrote:
> > >
> > > This patchset fix issues in Intel FPGA PCIe driver.
> > > - Fix TLP polling timeout
> > > - Fix enumerating mult-function PCIe device issue
> > > - Fix PCIe switch read config register issue
> > >
> > > Ley Foon Tan (3):
> > >   pci: intel: Increase TLP polling counter
> > >   pci: intel: Fix error when enumerating multi-function PCIe device
> > >   pci: intel: Fix configuration type based on secondary number
> > >
> > >  drivers/pci/pcie_intel_fpga.c | 18 +++---
> > >  1 file changed, 11 insertions(+), 7 deletions(-)
> > Any comment on these patches?
> >
> > Thanks
> Hi Tom and Michal
> 
> Can you help to merge these patches?

I saw these as "FPGA" and gave them to Michal, in patchwork.  And I know
he's digging out from a vacation backlog.  Looking at the patches
themselves, I can see they're more "PCI" than anything else, I'll put
them in my queue.  Thanks for the reminder!

-- 
Tom


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Re: [U-Boot] [PATCH] board: ls1028a: set up integrated PCI stream IDs and cache attributes

[Alex Marginean]

On 8/9/2019 4:27 PM, Bin Meng wrote:

Hi Alex,

On Fri, Aug 9, 2019 at 9:15 PM Alex Marginean  wrote:


Hi Bin,

On 8/9/2019 12:58 PM, Bin Meng wrote:

Hi Alex,

On Fri, Aug 9, 2019 at 3:59 PM Alex Marginean
 wrote:


Configure stream IDs for integrated PCI devices.  There are hardware
defaults but unfortunately they are outside the acceptable range for
SMMU, so we need to tune them down.  Use values based on Linux device tree
iommu-map or, if missing, start from HW base value shifted down by 4.

Signed-off-by: Alex Marginean 
---
   board/freescale/ls1028a/ls1028a.c | 64 +++
   1 file changed, 64 insertions(+)

diff --git a/board/freescale/ls1028a/ls1028a.c 
b/board/freescale/ls1028a/ls1028a.c
index 49a9292c31..05eac6f9c4 100644
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -118,6 +118,67 @@ void detail_board_ddr_info(void)
   }

   #ifdef CONFIG_OF_BOARD_SETUP
+
+/*
+ * Hardware default stream IDs are 0x4000 + PCI function #, but that's outside
+ * the acceptable range for SMMU.  Use Linux DT values instead or at least
+ * smaller defaults.
+ */
+#define ECAM_NUM_PFS   7
+#define ECAM_IERB_BASE 0x1F080
+#define ECAM_PFAMQ(pf, vf) ((ECAM_IERB_BASE + 0x800 + (pf) * \
+ 0x1000 + (vf) * 4))
+/* cache related transaction attributes for PCIe functions */
+#define ECAM_IERB_MSICAR   (ECAM_IERB_BASE + 0xa400)
+#define ECAM_IERB_MSICAR_VALUE 0x30
+
+/* number of VFs per PF, VFs have their own AMQ settings */
+static const u8 enetc_vfs[ECAM_NUM_PFS] = { 2, 2 };
+
+void setup_ecam_amq(void *blob)


nits: this should be static


I'll send a v2.




+{
+   int streamid, sid_base, off;
+   int pf, vf, vfnn = 1;
+   u32 iommu_map[4];
+   int err;
+
+   /*
+* Look up the stream ID settings in the DT, if found apply the values
+* to HW, otherwise use HW values shifted down by 4.
+*/
+   off = fdt_node_offset_by_compatible(blob, 0, "pci-host-ecam-generic");
+   if (off < 0) {
+   debug("ECAM node not found\n");
+   return;
+   }
+
+   err = fdtdec_get_int_array(blob, off, "iommu-map", iommu_map, 4);
+   if (err) {
+   sid_base = in_le32(ECAM_PFAMQ(0, 0)) >> 4;
+   debug("\"iommu-map\" not found, using default SID base %04x\n",
+ sid_base);
+   } else {
+   sid_base = iommu_map[2];
+   }
+   /* set up AMQs for all integrated PCI functions */
+   for (pf = 0; pf < ECAM_NUM_PFS; pf++) {
+   streamid = sid_base + pf;
+   out_le32(ECAM_PFAMQ(pf, 0), streamid);
+
+   /* set up AMQs for VFs, if any */
+   for (vf = 0; vf < enetc_vfs[pf]; vf++, vfnn++) {
+   streamid = sid_base + ECAM_NUM_PFS + vfnn;
+   out_le32(ECAM_PFAMQ(pf, vf + 1), streamid);
+   }
+   }
+}
+
+void setup_ecam_cacheattr(void)


ditto


+{
+   /* set MSI cache attributes */
+   out_le32(ECAM_IERB_MSICAR, ECAM_IERB_MSICAR_VALUE);
+}
+
   int ft_board_setup(void *blob, bd_t *bd)
   {
  u64 base[CONFIG_NR_DRAM_BANKS];
@@ -143,6 +204,9 @@ int ft_board_setup(void *blob, bd_t *bd)

  fdt_fixup_memory_banks(blob, base, size, 2);

+   setup_ecam_amq(blob);
+   setup_ecam_cacheattr();
+
  return 0;
   }
   #endif


Not only programming the registers, but also I think we will need fix
up the  property used by the "pci-host-ecam-generic", just
like what it was done in fdt_pcie_set_msi_map_entry() in
pcie_layerscape_fixup.c


The DT loaded with the kernel has the two maps (iommu and msi) in sync,
they are both present and they start from same base ID.  For integrated


OK, I checked arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi, and
found pcie@1f000 (ecam) node has  and 
properties, both of which have the same ID 0x17.


PCI we use that as a reference in U-Boot rather than assign the value
from U-Boot.  Layerscape PCI node as far as I remember doesn't have the
msi/iommu-map properties, they are added by U-Boot using IDs it
allocates, but we don't do that here.  The intent is to try to keep


In the same kernel fsl-ls1028a.dtsi, I did not find any layescape PCI
nodes. I suspect they are not upstreamed yet?


I don't know for a fact, I assume they have been submitted but not
merged yet.


So if the we are doing layersacpe PCI  fix in U-Boot, but for
ECAM we are doing the other way around, I don't think it is
consistent. I believe we should either have DT provide  and
 for layersacpe PCI nodes and use that as a reference in
U-Boot, or we fix up all in U-Boot.


It's not consistent, no argument there.  For what is worth I would like
to stick to the concept of integrated HW using by default a valid set of
IDs and not do any fix-up at all.  I suppose the next best thing along
that line is to right shift 

Re: [U-Boot] [PATCH] board: ls1028a: set up integrated PCI stream IDs and cache attributes

[Bin Meng]

Hi Alex,

On Fri, Aug 9, 2019 at 9:15 PM Alex Marginean  wrote:
>
> Hi Bin,
>
> On 8/9/2019 12:58 PM, Bin Meng wrote:
> > Hi Alex,
> >
> > On Fri, Aug 9, 2019 at 3:59 PM Alex Marginean
> >  wrote:
> >>
> >> Configure stream IDs for integrated PCI devices.  There are hardware
> >> defaults but unfortunately they are outside the acceptable range for
> >> SMMU, so we need to tune them down.  Use values based on Linux device tree
> >> iommu-map or, if missing, start from HW base value shifted down by 4.
> >>
> >> Signed-off-by: Alex Marginean 
> >> ---
> >>   board/freescale/ls1028a/ls1028a.c | 64 +++
> >>   1 file changed, 64 insertions(+)
> >>
> >> diff --git a/board/freescale/ls1028a/ls1028a.c 
> >> b/board/freescale/ls1028a/ls1028a.c
> >> index 49a9292c31..05eac6f9c4 100644
> >> --- a/board/freescale/ls1028a/ls1028a.c
> >> +++ b/board/freescale/ls1028a/ls1028a.c
> >> @@ -118,6 +118,67 @@ void detail_board_ddr_info(void)
> >>   }
> >>
> >>   #ifdef CONFIG_OF_BOARD_SETUP
> >> +
> >> +/*
> >> + * Hardware default stream IDs are 0x4000 + PCI function #, but that's 
> >> outside
> >> + * the acceptable range for SMMU.  Use Linux DT values instead or at least
> >> + * smaller defaults.
> >> + */
> >> +#define ECAM_NUM_PFS   7
> >> +#define ECAM_IERB_BASE 0x1F080
> >> +#define ECAM_PFAMQ(pf, vf) ((ECAM_IERB_BASE + 0x800 + (pf) * \
> >> + 0x1000 + (vf) * 4))
> >> +/* cache related transaction attributes for PCIe functions */
> >> +#define ECAM_IERB_MSICAR   (ECAM_IERB_BASE + 0xa400)
> >> +#define ECAM_IERB_MSICAR_VALUE 0x30
> >> +
> >> +/* number of VFs per PF, VFs have their own AMQ settings */
> >> +static const u8 enetc_vfs[ECAM_NUM_PFS] = { 2, 2 };
> >> +
> >> +void setup_ecam_amq(void *blob)
> >
> > nits: this should be static
>
> I'll send a v2.
>
> >
> >> +{
> >> +   int streamid, sid_base, off;
> >> +   int pf, vf, vfnn = 1;
> >> +   u32 iommu_map[4];
> >> +   int err;
> >> +
> >> +   /*
> >> +* Look up the stream ID settings in the DT, if found apply the 
> >> values
> >> +* to HW, otherwise use HW values shifted down by 4.
> >> +*/
> >> +   off = fdt_node_offset_by_compatible(blob, 0, 
> >> "pci-host-ecam-generic");
> >> +   if (off < 0) {
> >> +   debug("ECAM node not found\n");
> >> +   return;
> >> +   }
> >> +
> >> +   err = fdtdec_get_int_array(blob, off, "iommu-map", iommu_map, 4);
> >> +   if (err) {
> >> +   sid_base = in_le32(ECAM_PFAMQ(0, 0)) >> 4;
> >> +   debug("\"iommu-map\" not found, using default SID base 
> >> %04x\n",
> >> + sid_base);
> >> +   } else {
> >> +   sid_base = iommu_map[2];
> >> +   }
> >> +   /* set up AMQs for all integrated PCI functions */
> >> +   for (pf = 0; pf < ECAM_NUM_PFS; pf++) {
> >> +   streamid = sid_base + pf;
> >> +   out_le32(ECAM_PFAMQ(pf, 0), streamid);
> >> +
> >> +   /* set up AMQs for VFs, if any */
> >> +   for (vf = 0; vf < enetc_vfs[pf]; vf++, vfnn++) {
> >> +   streamid = sid_base + ECAM_NUM_PFS + vfnn;
> >> +   out_le32(ECAM_PFAMQ(pf, vf + 1), streamid);
> >> +   }
> >> +   }
> >> +}
> >> +
> >> +void setup_ecam_cacheattr(void)
> >
> > ditto
> >
> >> +{
> >> +   /* set MSI cache attributes */
> >> +   out_le32(ECAM_IERB_MSICAR, ECAM_IERB_MSICAR_VALUE);
> >> +}
> >> +
> >>   int ft_board_setup(void *blob, bd_t *bd)
> >>   {
> >>  u64 base[CONFIG_NR_DRAM_BANKS];
> >> @@ -143,6 +204,9 @@ int ft_board_setup(void *blob, bd_t *bd)
> >>
> >>  fdt_fixup_memory_banks(blob, base, size, 2);
> >>
> >> +   setup_ecam_amq(blob);
> >> +   setup_ecam_cacheattr();
> >> +
> >>  return 0;
> >>   }
> >>   #endif
> >
> > Not only programming the registers, but also I think we will need fix
> > up the  property used by the "pci-host-ecam-generic", just
> > like what it was done in fdt_pcie_set_msi_map_entry() in
> > pcie_layerscape_fixup.c
>
> The DT loaded with the kernel has the two maps (iommu and msi) in sync,
> they are both present and they start from same base ID.  For integrated

OK, I checked arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi, and
found pcie@1f000 (ecam) node has  and 
properties, both of which have the same ID 0x17.

> PCI we use that as a reference in U-Boot rather than assign the value
> from U-Boot.  Layerscape PCI node as far as I remember doesn't have the
> msi/iommu-map properties, they are added by U-Boot using IDs it
> allocates, but we don't do that here.  The intent is to try to keep

In the same kernel fsl-ls1028a.dtsi, I did not find any layescape PCI
nodes. I suspect they are not upstreamed yet?

So if the we are doing layersacpe PCI  fix in U-Boot, but for
ECAM we are doing the other way around, 

Re: [U-Boot] [PATCH 06/11] drivers: net: aquantia: set MDI reversal based on DT property

[Alex Marginean]

On 8/8/2019 7:45 PM, Alex Marginean wrote:

MDI pins up to the RJ45 connector may be reversed on the board and the
default PHY configuration applied by firmware may or may not match that.
Add an optional DT property to configure MDI reversal for this case.

Signed-off-by: Alex Marginean 
---
  drivers/net/phy/aquantia.c | 39 ++
  1 file changed, 39 insertions(+)

diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index ab165e76f5..62a4d1ea6e 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -64,6 +64,13 @@
  #define UP_RUN_STALL_OVERRIDE BIT(6)
  #define UP_RUN_STALL BIT(0)
  
+#define AQUANTIA_PMA_RX_VENDOR_P1		0xe400

+#define  AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK GENMASK(1, 0)
+/* MDI reversal configured through registers */
+#define  AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG BIT(1)
+/* MDI reversal enabled */
+#define  AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV BIT(0)
+
  /*
   * global start rate, the protocol associated with this speed is used by 
default
   * on SI.
@@ -324,6 +331,36 @@ static int aquantia_set_proto(struct phy_device *phydev, 
int if_type)
return 0;
  }
  
+static int aquantia_dts_config(struct phy_device *phydev)

+{
+#ifdef CONFIG_OF_CONTROL


^ This should be CONFIG_DM_ETH


+   ofnode node = phydev->node;
+   u32 prop;
+   u16 reg;
+
+   /* this code only works on gen2 and gen3 PHYs */
+   if (phydev->drv->data != AQUANTIA_GEN2 &&
+   phydev->drv->data != AQUANTIA_GEN3)
+   return -ENOTSUPP;
+
+   if (!ofnode_valid(node))
+   return 0;
+
+   if (!ofnode_read_u32(node, "mdi-reversal", )) {
+   debug("mdi-reversal = %d\n", (int)prop);
+   reg =  phy_read(phydev, MDIO_MMD_PMAPMD,
+   AQUANTIA_PMA_RX_VENDOR_P1);
+   reg &= ~AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK;
+   reg |= AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG;
+   reg |= prop ? AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV : 0;
+   phy_write(phydev, MDIO_MMD_PMAPMD, AQUANTIA_PMA_RX_VENDOR_P1,
+ reg);
+   }
+
+#endif
+   return 0;
+}
+
  static bool aquantia_link_is_up(struct phy_device *phydev)
  {
u16 reg, regmask;
@@ -403,6 +440,8 @@ int aquantia_config(struct phy_device *phydev)
  
  		/* configure protocol based on phydev->interface */

aquantia_set_proto(phydev, if_type);
+   /* apply custom configuration based on DT */
+   aquantia_dts_config(phydev);
  
  		/* wake PHY back up */

phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);



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Re: [U-Boot] [PATCH] board: ls1028a: set up integrated PCI stream IDs and cache attributes

[Alex Marginean]

Hi Bin,

On 8/9/2019 12:58 PM, Bin Meng wrote:

Hi Alex,

On Fri, Aug 9, 2019 at 3:59 PM Alex Marginean
 wrote:


Configure stream IDs for integrated PCI devices.  There are hardware
defaults but unfortunately they are outside the acceptable range for
SMMU, so we need to tune them down.  Use values based on Linux device tree
iommu-map or, if missing, start from HW base value shifted down by 4.

Signed-off-by: Alex Marginean 
---
  board/freescale/ls1028a/ls1028a.c | 64 +++
  1 file changed, 64 insertions(+)

diff --git a/board/freescale/ls1028a/ls1028a.c 
b/board/freescale/ls1028a/ls1028a.c
index 49a9292c31..05eac6f9c4 100644
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -118,6 +118,67 @@ void detail_board_ddr_info(void)
  }

  #ifdef CONFIG_OF_BOARD_SETUP
+
+/*
+ * Hardware default stream IDs are 0x4000 + PCI function #, but that's outside
+ * the acceptable range for SMMU.  Use Linux DT values instead or at least
+ * smaller defaults.
+ */
+#define ECAM_NUM_PFS   7
+#define ECAM_IERB_BASE 0x1F080
+#define ECAM_PFAMQ(pf, vf) ((ECAM_IERB_BASE + 0x800 + (pf) * \
+ 0x1000 + (vf) * 4))
+/* cache related transaction attributes for PCIe functions */
+#define ECAM_IERB_MSICAR   (ECAM_IERB_BASE + 0xa400)
+#define ECAM_IERB_MSICAR_VALUE 0x30
+
+/* number of VFs per PF, VFs have their own AMQ settings */
+static const u8 enetc_vfs[ECAM_NUM_PFS] = { 2, 2 };
+
+void setup_ecam_amq(void *blob)


nits: this should be static


I'll send a v2.




+{
+   int streamid, sid_base, off;
+   int pf, vf, vfnn = 1;
+   u32 iommu_map[4];
+   int err;
+
+   /*
+* Look up the stream ID settings in the DT, if found apply the values
+* to HW, otherwise use HW values shifted down by 4.
+*/
+   off = fdt_node_offset_by_compatible(blob, 0, "pci-host-ecam-generic");
+   if (off < 0) {
+   debug("ECAM node not found\n");
+   return;
+   }
+
+   err = fdtdec_get_int_array(blob, off, "iommu-map", iommu_map, 4);
+   if (err) {
+   sid_base = in_le32(ECAM_PFAMQ(0, 0)) >> 4;
+   debug("\"iommu-map\" not found, using default SID base %04x\n",
+ sid_base);
+   } else {
+   sid_base = iommu_map[2];
+   }
+   /* set up AMQs for all integrated PCI functions */
+   for (pf = 0; pf < ECAM_NUM_PFS; pf++) {
+   streamid = sid_base + pf;
+   out_le32(ECAM_PFAMQ(pf, 0), streamid);
+
+   /* set up AMQs for VFs, if any */
+   for (vf = 0; vf < enetc_vfs[pf]; vf++, vfnn++) {
+   streamid = sid_base + ECAM_NUM_PFS + vfnn;
+   out_le32(ECAM_PFAMQ(pf, vf + 1), streamid);
+   }
+   }
+}
+
+void setup_ecam_cacheattr(void)


ditto


+{
+   /* set MSI cache attributes */
+   out_le32(ECAM_IERB_MSICAR, ECAM_IERB_MSICAR_VALUE);
+}
+
  int ft_board_setup(void *blob, bd_t *bd)
  {
 u64 base[CONFIG_NR_DRAM_BANKS];
@@ -143,6 +204,9 @@ int ft_board_setup(void *blob, bd_t *bd)

 fdt_fixup_memory_banks(blob, base, size, 2);

+   setup_ecam_amq(blob);
+   setup_ecam_cacheattr();
+
 return 0;
  }
  #endif


Not only programming the registers, but also I think we will need fix
up the  property used by the "pci-host-ecam-generic", just
like what it was done in fdt_pcie_set_msi_map_entry() in
pcie_layerscape_fixup.c


The DT loaded with the kernel has the two maps (iommu and msi) in sync,
they are both present and they start from same base ID.  For integrated
PCI we use that as a reference in U-Boot rather than assign the value
from U-Boot.  Layerscape PCI node as far as I remember doesn't have the
msi/iommu-map properties, they are added by U-Boot using IDs it
allocates, but we don't do that here.  The intent is to try to keep
fixups to a minimum, in this case the code is needed only because the HW
defaults are not OK.
For what is worth I tested ping in Linux with this U-Boot change and it
works.

I suppose one potential issue is to make sure U-Boot won't
allocate in the same range as the values used in DT for ECAM.  The
values we use now in Linux DT are OK in the sense that they are over the
range used by U-Boot (FSL_PEX_STREAM_ID_START-FSL_PEX_STREAM_ID_END).
There is no explicit check for overlap between layerscape PCI stream IDs
and ECAM stream IDs, I am guessing such a configuration issue would be
noticeable in Linux though.

Thank you!
Alex



Regards,
Bin
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[U-Boot] [PATCH] cmd: avb: Support A/B slots

[Sam Protsenko]

Add optional parameter to 'avb verify' sub-command, so that user is able
to specify which slot to use, in case when user's partitions are
slotted. If that parameter is omitted, the behavior of 'avb verify' will
be the same as before, so user API is content.

Signed-off-by: Sam Protsenko 
---
 cmd/avb.c | 13 +
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/cmd/avb.c b/cmd/avb.c
index 3f6fd763a0..d1942d6605 100644
--- a/cmd/avb.c
+++ b/cmd/avb.c
@@ -235,6 +235,7 @@ int do_avb_verify_part(cmd_tbl_t *cmdtp, int flag,
AvbSlotVerifyData *out_data;
char *cmdline;
char *extra_args;
+   char *slot_suffix = "";
 
bool unlocked = false;
int res = CMD_RET_FAILURE;
@@ -244,9 +245,12 @@ int do_avb_verify_part(cmd_tbl_t *cmdtp, int flag,
return CMD_RET_FAILURE;
}
 
-   if (argc != 1)
+   if (argc < 1 || argc > 2)
return CMD_RET_USAGE;
 
+   if (argc == 2)
+   slot_suffix = argv[1];
+
printf("## Android Verified Boot 2.0 version %s\n",
   avb_version_string());
 
@@ -259,7 +263,7 @@ int do_avb_verify_part(cmd_tbl_t *cmdtp, int flag,
slot_result =
avb_slot_verify(avb_ops,
requested_partitions,
-   "",
+   slot_suffix,
unlocked,
AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE,
_data);
@@ -419,7 +423,7 @@ static cmd_tbl_t cmd_avb[] = {
U_BOOT_CMD_MKENT(read_part, 5, 0, do_avb_read_part, "", ""),
U_BOOT_CMD_MKENT(read_part_hex, 4, 0, do_avb_read_part_hex, "", ""),
U_BOOT_CMD_MKENT(write_part, 5, 0, do_avb_write_part, "", ""),
-   U_BOOT_CMD_MKENT(verify, 1, 0, do_avb_verify_part, "", ""),
+   U_BOOT_CMD_MKENT(verify, 2, 0, do_avb_verify_part, "", ""),
 #ifdef CONFIG_OPTEE_TA_AVB
U_BOOT_CMD_MKENT(read_pvalue, 3, 0, do_avb_read_pvalue, "", ""),
U_BOOT_CMD_MKENT(write_pvalue, 3, 0, do_avb_write_pvalue, "", ""),
@@ -462,6 +466,7 @@ U_BOOT_CMD(
"avb read_pvalue   - read a persistent value \n"
"avb write_pvalue   - write a persistent value \n"
 #endif
-   "avb verify - run verification process using hash data\n"
+   "avb verify [slot_suffix] - run verification process using hash data\n"
"from vbmeta structure\n"
+   "[slot_suffix] - _a, _b, etc (if vbmeta partition is slotted)\n"
);
-- 
2.20.1

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[U-Boot] [PATCH] image: android: Fix possible build errors

[Sam Protsenko]

As android_image.h uses types like u32, we need to include corresponding
headers in place. Otherwise the user will be forced to include those in
C file, or next build error can occur:

include/android_image.h:32:5: error: unknown type name 'u32'
 u32 kernel_size; /* size in bytes */

Include required headers for data types used. While at it, remove
typedef struct, which is prohibited by kernel coding style, and fix the
comment.

Signed-off-by: Sam Protsenko 
---
 include/android_image.h | 11 ---
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/include/android_image.h b/include/android_image.h
index 0519ece368..54d25af068 100644
--- a/include/android_image.h
+++ b/include/android_image.h
@@ -11,18 +11,15 @@
 #ifndef _ANDROID_IMAGE_H_
 #define _ANDROID_IMAGE_H_
 
+#include 
+#include 
+
 #define ANDR_BOOT_MAGIC "ANDROID!"
 #define ANDR_BOOT_MAGIC_SIZE 8
 #define ANDR_BOOT_NAME_SIZE 16
 #define ANDR_BOOT_ARGS_SIZE 512
 #define ANDR_BOOT_EXTRA_ARGS_SIZE 1024
 
-/*
- * It is expected that callers would explicitly specify which version of the
- * boot image header they need to use.
- */
-typedef struct andr_img_hdr andr_img_hdr;
-
 /* The bootloader expects the structure of andr_img_hdr with header
  * version 0 to be as follows: */
 struct andr_img_hdr {
@@ -115,7 +112,7 @@ struct andr_img_hdr {
  * +-+
  * | dtb | q pages
  * +-+
-
+ *
  * n = (kernel_size + page_size - 1) / page_size
  * m = (ramdisk_size + page_size - 1) / page_size
  * o = (second_size + page_size - 1) / page_size
-- 
2.20.1

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Re: [U-Boot] GitLab: make pipeline status public

[Heinrich Schuchardt]

On 8/9/19 12:20 PM, Bin Meng wrote:

Hi Harald,

On Thu, Aug 8, 2019 at 7:21 PM Harald Seiler  wrote:


Hi Heinrich,

On Wed, 2019-08-07 at 21:26 +0200, Heinrich Schuchardt wrote:

Hello Harald,

Tom suggested you could help on this issue.

I suggest that the pipeline status should be public on all custodian
gits, e.g. page
https://gitlab.denx.de/u-boot/custodians/u-boot-efi/pipelines.

I set the flag "Public pipelines" in the CI settings but this seems
not be sufficient. I still get a 404 error code if I am not logged on.


There is another setting you need to enable, IIRC: Under

 Settings -> General -> Visibility, Permissions -> Pipelines

, you need to change the dropdown from "Only Project Members"
to "Everyone With Access".

Can you check whether that works?


The default setting for x86 repo has "Everyone With Access" for
"Pipelines", however it looks that I still cannot access:
https://gitlab.denx.de/u-boot/custodians/u-boot-x86/-/jobs/4613

when not logged on. Any ideas?


There are two settings needed:

Settings -> General -> Visibility, Permissions -> Pipelines
= "Everyone With Access"

Settings -> CI/CD -> General Pipelines -> Public pipelines
= true

Best regards

Heinrich
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Re: [U-Boot] [PATCH v1] apalis-tk1: support v1.2 hardware revision

[Igor Opaniuk]

Hi Tom,

On Fri, Aug 9, 2019 at 1:22 PM Igor Opaniuk  wrote:
>
> From: Marcel Ziswiler 
>
> Support the V1.2 hardware revision with the following pin muxing
> changes:
>
> Ddc_scl_pv4 and ddc_sda_pv5 previously used as Apalis GPIO3 and GPIO4
> are now used as DDC pins.
>
> Gen2_i2c_scl_pt5 and gen2_i2c_sda_pt6 previously used as DDC pins are
> now used as USB power enable signals.
>
> Usb_vbus_en0_pn4 and usb_vbus_en1_pn5 previously used as USB power
> enable signals are now used as GPIO3 and GPIO4.
>
> Additionally a new device tree file tegra124-apalis-v1.2-eval.dtb is
> loaded on V1.2 and later modules and resp. USB power enable signals
> activated.
>
> Signed-off-by: Marcel Ziswiler 
> Signed-off-by: Igor Opaniuk 
> ---
>
>  arch/arm/dts/tegra124-apalis.dts  | 89 ++-
>  board/toradex/apalis-tk1/apalis-tk1.c | 37 
>  .../apalis-tk1/pinmux-config-apalis-tk1.h | 19 ++--
>  configs/apalis-tk1_defconfig  |  2 +-
>  include/configs/apalis-tk1.h  | 12 ++-
>  5 files changed, 103 insertions(+), 56 deletions(-)
>
> diff --git a/arch/arm/dts/tegra124-apalis.dts 
> b/arch/arm/dts/tegra124-apalis.dts
> index a962c0a2f0..08184ab3ac 100644
> --- a/arch/arm/dts/tegra124-apalis.dts
> +++ b/arch/arm/dts/tegra124-apalis.dts
> @@ -1,5 +1,5 @@
>  /*
> - * Copyright 2016 Toradex AG
> + * Copyright 2016-2019 Toradex AG
>   *
>   * This file is dual-licensed: you can use it either under the terms
>   * of the GPL or the X11 license, at your option. Note that this dual
> @@ -230,19 +230,21 @@
> };
>
> /* Apalis GPIO */
> -   ddc_scl_pv4 {
> -   nvidia,pins = "ddc_scl_pv4";
> +   usb_vbus_en0_pn4 {
> +   nvidia,pins = "usb_vbus_en0_pn4";
> nvidia,function = "rsvd2";
> nvidia,pull = ;
> nvidia,tristate = ;
> nvidia,enable-input = ;
> +   nvidia,open-drain = ;
> };
> -   ddc_sda_pv5 {
> -   nvidia,pins = "ddc_sda_pv5";
> +   usb_vbus_en1_pn5 {
> +   nvidia,pins = "usb_vbus_en1_pn5";
> nvidia,function = "rsvd2";
> nvidia,pull = ;
> nvidia,tristate = ;
> nvidia,enable-input = ;
> +   nvidia,open-drain = ;
> };
> pex_l0_rst_n_pdd1 {
> nvidia,pins = "pex_l0_rst_n_pdd1";
> @@ -333,40 +335,40 @@
> nvidia,open-drain = ;
> };
>
> -   /* Apalis I2C2 (DDC) */
> -   gen2_i2c_scl_pt5 {
> -   nvidia,pins = "gen2_i2c_scl_pt5";
> -   nvidia,function = "i2c2";
> +   /* Apalis I2C3 (CAM) */
> +   cam_i2c_scl_pbb1 {
> +   nvidia,pins = "cam_i2c_scl_pbb1";
> +   nvidia,function = "i2c3";
> nvidia,pull = ;
> nvidia,tristate = ;
> nvidia,enable-input = ;
> nvidia,open-drain = ;
> };
> -   gen2_i2c_sda_pt6 {
> -   nvidia,pins = "gen2_i2c_sda_pt6";
> -   nvidia,function = "i2c2";
> +   cam_i2c_sda_pbb2 {
> +   nvidia,pins = "cam_i2c_sda_pbb2";
> +   nvidia,function = "i2c3";
> nvidia,pull = ;
> nvidia,tristate = ;
> nvidia,enable-input = ;
> nvidia,open-drain = ;
> };
>
> -   /* Apalis I2C3 (CAM) */
> -   cam_i2c_scl_pbb1 {
> -   nvidia,pins = "cam_i2c_scl_pbb1";
> -   nvidia,function = "i2c3";
> +   /* Apalis I2C4 (DDC) */
> +   ddc_scl_pv4 {
> +   nvidia,pins = "ddc_scl_pv4";
> +   nvidia,function = "i2c4";
> nvidia,pull = ;
> nvidia,tristate = ;
> nvidia,enable-input = ;
> -   nvidia,open-drain = ;
> +   nvidia,rcv-sel = ;
> };
> -   cam_i2c_sda_pbb2 {
> 

[U-Boot] [PATCH v1] apalis-tk1: support v1.2 hardware revision

[Igor Opaniuk]

From: Marcel Ziswiler 

Support the V1.2 hardware revision with the following pin muxing
changes:

Ddc_scl_pv4 and ddc_sda_pv5 previously used as Apalis GPIO3 and GPIO4
are now used as DDC pins.

Gen2_i2c_scl_pt5 and gen2_i2c_sda_pt6 previously used as DDC pins are
now used as USB power enable signals.

Usb_vbus_en0_pn4 and usb_vbus_en1_pn5 previously used as USB power
enable signals are now used as GPIO3 and GPIO4.

Additionally a new device tree file tegra124-apalis-v1.2-eval.dtb is
loaded on V1.2 and later modules and resp. USB power enable signals
activated.

Signed-off-by: Marcel Ziswiler 
Signed-off-by: Igor Opaniuk 
---

 arch/arm/dts/tegra124-apalis.dts  | 89 ++-
 board/toradex/apalis-tk1/apalis-tk1.c | 37 
 .../apalis-tk1/pinmux-config-apalis-tk1.h | 19 ++--
 configs/apalis-tk1_defconfig  |  2 +-
 include/configs/apalis-tk1.h  | 12 ++-
 5 files changed, 103 insertions(+), 56 deletions(-)

diff --git a/arch/arm/dts/tegra124-apalis.dts b/arch/arm/dts/tegra124-apalis.dts
index a962c0a2f0..08184ab3ac 100644
--- a/arch/arm/dts/tegra124-apalis.dts
+++ b/arch/arm/dts/tegra124-apalis.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 Toradex AG
+ * Copyright 2016-2019 Toradex AG
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -230,19 +230,21 @@
};
 
/* Apalis GPIO */
-   ddc_scl_pv4 {
-   nvidia,pins = "ddc_scl_pv4";
+   usb_vbus_en0_pn4 {
+   nvidia,pins = "usb_vbus_en0_pn4";
nvidia,function = "rsvd2";
nvidia,pull = ;
nvidia,tristate = ;
nvidia,enable-input = ;
+   nvidia,open-drain = ;
};
-   ddc_sda_pv5 {
-   nvidia,pins = "ddc_sda_pv5";
+   usb_vbus_en1_pn5 {
+   nvidia,pins = "usb_vbus_en1_pn5";
nvidia,function = "rsvd2";
nvidia,pull = ;
nvidia,tristate = ;
nvidia,enable-input = ;
+   nvidia,open-drain = ;
};
pex_l0_rst_n_pdd1 {
nvidia,pins = "pex_l0_rst_n_pdd1";
@@ -333,40 +335,40 @@
nvidia,open-drain = ;
};
 
-   /* Apalis I2C2 (DDC) */
-   gen2_i2c_scl_pt5 {
-   nvidia,pins = "gen2_i2c_scl_pt5";
-   nvidia,function = "i2c2";
+   /* Apalis I2C3 (CAM) */
+   cam_i2c_scl_pbb1 {
+   nvidia,pins = "cam_i2c_scl_pbb1";
+   nvidia,function = "i2c3";
nvidia,pull = ;
nvidia,tristate = ;
nvidia,enable-input = ;
nvidia,open-drain = ;
};
-   gen2_i2c_sda_pt6 {
-   nvidia,pins = "gen2_i2c_sda_pt6";
-   nvidia,function = "i2c2";
+   cam_i2c_sda_pbb2 {
+   nvidia,pins = "cam_i2c_sda_pbb2";
+   nvidia,function = "i2c3";
nvidia,pull = ;
nvidia,tristate = ;
nvidia,enable-input = ;
nvidia,open-drain = ;
};
 
-   /* Apalis I2C3 (CAM) */
-   cam_i2c_scl_pbb1 {
-   nvidia,pins = "cam_i2c_scl_pbb1";
-   nvidia,function = "i2c3";
+   /* Apalis I2C4 (DDC) */
+   ddc_scl_pv4 {
+   nvidia,pins = "ddc_scl_pv4";
+   nvidia,function = "i2c4";
nvidia,pull = ;
nvidia,tristate = ;
nvidia,enable-input = ;
-   nvidia,open-drain = ;
+   nvidia,rcv-sel = ;
};
-   cam_i2c_sda_pbb2 {
-   nvidia,pins = "cam_i2c_sda_pbb2";
-   nvidia,function = "i2c3";
+   ddc_sda_pv5 {
+   nvidia,pins = "ddc_sda_pv5";
+   nvidia,function = 

Re: [U-Boot] GitLab: make pipeline status public

[Bin Meng]

Hi Harald,

On Thu, Aug 8, 2019 at 7:21 PM Harald Seiler  wrote:
>
> Hi Heinrich,
>
> On Wed, 2019-08-07 at 21:26 +0200, Heinrich Schuchardt wrote:
> > Hello Harald,
> >
> > Tom suggested you could help on this issue.
> >
> > I suggest that the pipeline status should be public on all custodian
> > gits, e.g. page
> > https://gitlab.denx.de/u-boot/custodians/u-boot-efi/pipelines.
> >
> > I set the flag "Public pipelines" in the CI settings but this seems
> > not be sufficient. I still get a 404 error code if I am not logged on.
>
> There is another setting you need to enable, IIRC: Under
>
> Settings -> General -> Visibility, Permissions -> Pipelines
>
> , you need to change the dropdown from "Only Project Members"
> to "Everyone With Access".
>
> Can you check whether that works?

The default setting for x86 repo has "Everyone With Access" for
"Pipelines", however it looks that I still cannot access:
https://gitlab.denx.de/u-boot/custodians/u-boot-x86/-/jobs/4613

when not logged on. Any ideas?

Regards,
Bin
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Re: [U-Boot] [PATCH] board: ls1028a: set up integrated PCI stream IDs and cache attributes

[Bin Meng]

Hi Alex,

On Fri, Aug 9, 2019 at 3:59 PM Alex Marginean
 wrote:
>
> Configure stream IDs for integrated PCI devices.  There are hardware
> defaults but unfortunately they are outside the acceptable range for
> SMMU, so we need to tune them down.  Use values based on Linux device tree
> iommu-map or, if missing, start from HW base value shifted down by 4.
>
> Signed-off-by: Alex Marginean 
> ---
>  board/freescale/ls1028a/ls1028a.c | 64 +++
>  1 file changed, 64 insertions(+)
>
> diff --git a/board/freescale/ls1028a/ls1028a.c 
> b/board/freescale/ls1028a/ls1028a.c
> index 49a9292c31..05eac6f9c4 100644
> --- a/board/freescale/ls1028a/ls1028a.c
> +++ b/board/freescale/ls1028a/ls1028a.c
> @@ -118,6 +118,67 @@ void detail_board_ddr_info(void)
>  }
>
>  #ifdef CONFIG_OF_BOARD_SETUP
> +
> +/*
> + * Hardware default stream IDs are 0x4000 + PCI function #, but that's 
> outside
> + * the acceptable range for SMMU.  Use Linux DT values instead or at least
> + * smaller defaults.
> + */
> +#define ECAM_NUM_PFS   7
> +#define ECAM_IERB_BASE 0x1F080
> +#define ECAM_PFAMQ(pf, vf) ((ECAM_IERB_BASE + 0x800 + (pf) * \
> + 0x1000 + (vf) * 4))
> +/* cache related transaction attributes for PCIe functions */
> +#define ECAM_IERB_MSICAR   (ECAM_IERB_BASE + 0xa400)
> +#define ECAM_IERB_MSICAR_VALUE 0x30
> +
> +/* number of VFs per PF, VFs have their own AMQ settings */
> +static const u8 enetc_vfs[ECAM_NUM_PFS] = { 2, 2 };
> +
> +void setup_ecam_amq(void *blob)

nits: this should be static

> +{
> +   int streamid, sid_base, off;
> +   int pf, vf, vfnn = 1;
> +   u32 iommu_map[4];
> +   int err;
> +
> +   /*
> +* Look up the stream ID settings in the DT, if found apply the values
> +* to HW, otherwise use HW values shifted down by 4.
> +*/
> +   off = fdt_node_offset_by_compatible(blob, 0, "pci-host-ecam-generic");
> +   if (off < 0) {
> +   debug("ECAM node not found\n");
> +   return;
> +   }
> +
> +   err = fdtdec_get_int_array(blob, off, "iommu-map", iommu_map, 4);
> +   if (err) {
> +   sid_base = in_le32(ECAM_PFAMQ(0, 0)) >> 4;
> +   debug("\"iommu-map\" not found, using default SID base 
> %04x\n",
> + sid_base);
> +   } else {
> +   sid_base = iommu_map[2];
> +   }
> +   /* set up AMQs for all integrated PCI functions */
> +   for (pf = 0; pf < ECAM_NUM_PFS; pf++) {
> +   streamid = sid_base + pf;
> +   out_le32(ECAM_PFAMQ(pf, 0), streamid);
> +
> +   /* set up AMQs for VFs, if any */
> +   for (vf = 0; vf < enetc_vfs[pf]; vf++, vfnn++) {
> +   streamid = sid_base + ECAM_NUM_PFS + vfnn;
> +   out_le32(ECAM_PFAMQ(pf, vf + 1), streamid);
> +   }
> +   }
> +}
> +
> +void setup_ecam_cacheattr(void)

ditto

> +{
> +   /* set MSI cache attributes */
> +   out_le32(ECAM_IERB_MSICAR, ECAM_IERB_MSICAR_VALUE);
> +}
> +
>  int ft_board_setup(void *blob, bd_t *bd)
>  {
> u64 base[CONFIG_NR_DRAM_BANKS];
> @@ -143,6 +204,9 @@ int ft_board_setup(void *blob, bd_t *bd)
>
> fdt_fixup_memory_banks(blob, base, size, 2);
>
> +   setup_ecam_amq(blob);
> +   setup_ecam_cacheattr();
> +
> return 0;
>  }
>  #endif

Not only programming the registers, but also I think we will need fix
up the  property used by the "pci-host-ecam-generic", just
like what it was done in fdt_pcie_set_msi_map_entry() in
pcie_layerscape_fixup.c

Regards,
Bin
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[U-Boot] Please pull u-boot-mmc-20190809

[Peng Fan]

Hi Tom,

Please pull u-boot-mmc tree, update:
 mmc test fix
 sdhci driver fix

CI: https://travis-ci.org/MrVan/u-boot/builds/569664807

Thanks,
Peng.

The following changes since commit fef408679b2f634ebfd6298d9fc99db99e60fb1d:

  Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell (2019-08-08 
09:19:08 -0400)

are available in the Git repository at:

  https://gitlab.denx.de/u-boot/custodians/u-boot-mmc.git tags/mmc-8-9

for you to fetch changes up to d569b4b0a4f34969f83ef8ec89b44f406553e72b:

  mmc: tangier_sdhci: fix uninitialized pointer deref on probe (2019-08-09 
13:45:25 +0800)


Faiz Abbas (1):
  mmc: Select SPL_HS200_SUPPORT if SPL_HS400_SUPPORT is selected

Matwey V. Kornilov (1):
  mmc: zynq_sdhci: fix uninitialized pointer deref on probe

Michal Simek (1):
  test/py: Fix MMC/SD block write test dependency

Peng Fan (7):
  mmc: atmel_sdhci: fix uninitialized pointer deref on probe
  mmc: bcm: fix uninitialized pointer deref on probe
  mmc: msm_sdhci: fix uninitialized pointer deref on probe
  mmc: pci: fix uninitialized pointer deref on probe
  mmc: s5p: fix uninitialized pointer deref on probe
  mmc: sdhci-cadence: fix uninitialized pointer deref on probe
  mmc: tangier_sdhci: fix uninitialized pointer deref on probe

 drivers/mmc/Kconfig  | 1 +
 drivers/mmc/atmel_sdhci.c| 4 ++--
 drivers/mmc/bcm2835_sdhci.c  | 4 +++-
 drivers/mmc/bcmstb_sdhci.c   | 3 ++-
 drivers/mmc/msm_sdhci.c  | 4 ++--
 drivers/mmc/pci_mmc.c| 4 ++--
 drivers/mmc/s5p_sdhci.c  | 4 ++--
 drivers/mmc/sdhci-cadence.c  | 3 ++-
 drivers/mmc/tangier_sdhci.c  | 3 ++-
 drivers/mmc/zynq_sdhci.c | 7 ---
 test/py/tests/test_mmc_wr.py | 2 +-
 11 files changed, 23 insertions(+), 16 deletions(-)
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Re: [U-Boot] [PATCH 1/7] mmc: atmel_sdhci: fix uninitialized pointer deref on probe

[Peng Fan]

> Subject: [PATCH 1/7] mmc: atmel_sdhci: fix uninitialized pointer deref on
> probe
> 
> Commit 3d296365e4e8 ("mmc: sdhci: Add support for
> sdhci-caps-mask") sdhci_setup_cfg() expects a valid sdhci_host mmc field.
> 
> Fixes: 3d296365e4e8 ("mmc: sdhci: Add support for sdhci-caps-mask")
> Cc: Faiz Abbas 
> Cc: Wenyou Yang 
> Signed-off-by: Peng Fan 
> ---
>  drivers/mmc/atmel_sdhci.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c index
> 4be47ba75e..d930ed8da0 100644
> --- a/drivers/mmc/atmel_sdhci.c
> +++ b/drivers/mmc/atmel_sdhci.c
> @@ -88,13 +88,13 @@ static int atmel_sdhci_probe(struct udevice *dev)
>   return -EINVAL;
> 
>   host->max_clk = max_clk;
> + host->mmc = >mmc;
> + host->mmc->dev = dev;
> 
>   ret = sdhci_setup_cfg(>cfg, host, 0, ATMEL_SDHC_MIN_FREQ);
>   if (ret)
>   return ret;
> 
> - host->mmc = >mmc;
> - host->mmc->dev = dev;
>   host->mmc->priv = host;
>   upriv->mmc = host->mmc;

Patchset applied to mmc/master.

Thanks,
Peng.

> 
> --
> 2.16.4

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Re: [U-Boot] [PATCH] test/py: Fix MMC/SD block write test dependency

[Peng Fan]

> Subject: [PATCH] test/py: Fix MMC/SD block write test dependency
> 
> Test is using random command which has own Kconfig symbol CMD_RANDOM
> which already depends on CMD_MEMORY. That's why replace cmd_memory
> by cmd_random.
> 
> Fixes: 09da18deab8b ("test/py: add MMC/SD block write test")
> Signed-off-by: Michal Simek 
> ---
> 
>  test/py/tests/test_mmc_wr.py | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/test/py/tests/test_mmc_wr.py b/test/py/tests/test_mmc_wr.py
> index 601279a6a4a3..7678c3c9c181 100644
> --- a/test/py/tests/test_mmc_wr.py
> +++ b/test/py/tests/test_mmc_wr.py
> @@ -35,7 +35,7 @@ env__mmc_wr_configs = (
> 
>  """
> 
> -@pytest.mark.buildconfigspec('cmd_mmc','cmd_memory')
> +@pytest.mark.buildconfigspec('cmd_mmc','cmd_random')
>  def test_mmc_wr(u_boot_console, env__mmc_wr_config):
>  """Test the "mmc write" command.

Applied to mmc/master.

Thanks,
Peng

> 
> --
> 2.17.1

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Re: [U-Boot] [PATCH] mmc: zynq_sdhci: fix uninitialized pointer deref on probe

[Peng Fan]

> Subject: [PATCH] mmc: zynq_sdhci: fix uninitialized pointer deref on probe
> 
> Since commit 3d296365e4e8 ("mmc: sdhci: Add support for
> sdhci-caps-mask") sdhci_setup_cfg() expects a valid sdhci_host mmc field.
> Move the mmc field initialization before sdhci_setup_cfg() call to avoid crash
> on mmc pointer dereference.
> 
> [this patch is based on commit 41a9fab8dac8 ("mmc: mv_sdhci: fix
> uninitialized pointer deref on probe") by Baruch Siach]
> 
> Fixes: 3d296365e4e8 ("mmc: sdhci: Add support for sdhci-caps-mask")
> Cc: Faiz Abbas 
> Cc: Baruch Siach 
> Signed-off-by: Matwey V. Kornilov 
> ---
>  drivers/mmc/zynq_sdhci.c | 7 ---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index
> c525084250..3225a7ac93 100644
> --- a/drivers/mmc/zynq_sdhci.c
> +++ b/drivers/mmc/zynq_sdhci.c
> @@ -242,13 +242,14 @@ static int arasan_sdhci_probe(struct udevice *dev)
> 
>   host->max_clk = clock;
> 
> + host->mmc = >mmc;
> + host->mmc->dev = dev;
> + host->mmc->priv = host;
> +
>   ret = sdhci_setup_cfg(>cfg, host, plat->f_max,
> CONFIG_ZYNQ_SDHCI_MIN_FREQ);
> - host->mmc = >mmc;
>   if (ret)
>   return ret;
> - host->mmc->priv = host;
> - host->mmc->dev = dev;
>   upriv->mmc = host->mmc;
> 
>   return sdhci_probe(dev);

Applied to mmc/master.

Thanks,
Peng.

> --
> 2.16.4

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Re: [U-Boot] [PATCH] mmc: Select SPL_HS200_SUPPORT if SPL_HS400_SUPPORT is selected

[Peng Fan]

> Subject: [PATCH] mmc: Select SPL_HS200_SUPPORT if SPL_HS400_SUPPORT
> is selected
> 
> Select SPL_HS200_SUPPORT if SPL_HS400_SUPPORT is selected as is being
> done for the U-boot case.
> 
> Signed-off-by: Faiz Abbas 
> ---
>  drivers/mmc/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index
> 4cdae41b59..66097ce0e7 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -156,6 +156,7 @@ config MMC_HS400_SUPPORT
> 
>  config SPL_MMC_HS400_SUPPORT
>   bool "enable HS400 support in SPL"
> + select SPL_MMC_HS200_SUPPORT
>   help
> The HS400 mode is support by some eMMC. The bus frequency is up
> to
> 200MHz. This mode requires tuning the IO.

Applied to mmc/master.

Thanks,
Peng.
> --
> 2.19.2

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Re: [U-Boot] [PATCH V3 4/4] clk: imx: add i.MX8MM clk driver

[Ye Li]

> Add i.MX8MM clk driver support.
> 
> Signed-off-by: Peng Fan 
> ---
>  drivers/clk/imx/Makefile |   2 +
>  drivers/clk/imx/clk-imx8mm.c | 415 
> +++
>  2 files changed, 417 insertions(+)
>  create mode 100644 drivers/clk/imx/clk-imx8mm.c
> 
> diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> index 105a58ca90..5ad7967fe9 100644
> --- a/drivers/clk/imx/Makefile
> +++ b/drivers/clk/imx/Makefile
> @@ -10,3 +10,5 @@ ifdef CONFIG_CLK_IMX8
>  obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o
>  obj-$(CONFIG_IMX8QM) += clk-imx8qm.o
>  endif
> +obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \
> + clk-composite-8m.o
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
> new file mode 100644
> index 00..a2a85b6a1a
> --- /dev/null
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -0,0 +1,415 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2019 NXP
> + * Peng Fan 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "clk.h"
> +
> +#define PLL_1416X_RATE(_rate, _m, _p, _s)\
> + {   \
> + .rate   =   (_rate),\
> + .mdiv   =   (_m),   \
> + .pdiv   =   (_p),   \
> + .sdiv   =   (_s),   \
> + }
> +
> +#define PLL_1443X_RATE(_rate, _m, _p, _s, _k)\
> + {   \
> + .rate   =   (_rate),\
> + .mdiv   =   (_m),   \
> + .pdiv   =   (_p),   \
> + .sdiv   =   (_s),   \
> + .kdiv   =   (_k),   \
> + }
> +
> +static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
> + PLL_1416X_RATE(18U, 225, 3, 0),
> + PLL_1416X_RATE(16U, 200, 3, 0),
> + PLL_1416X_RATE(12U, 300, 3, 1),
> + PLL_1416X_RATE(10U, 250, 3, 1),
> + PLL_1416X_RATE(8U,  200, 3, 1),
> + PLL_1416X_RATE(75000U,  250, 2, 2),
> + PLL_1416X_RATE(7U,  350, 3, 2),
> + PLL_1416X_RATE(6U,  300, 3, 2),
> +};
> +
> +static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
> + PLL_1443X_RATE(65000U, 325, 3, 2, 0),
> +};
> +
> +static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
> + .type = PLL_1443X,
> + .rate_table = imx8mm_drampll_tbl,
> + .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
> +};
> +
> +static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
> + .type = PLL_1416X,
> + .rate_table = imx8mm_pll1416x_tbl,
> + .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
> +};
> +
> +static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
> + .type = PLL_1416X,
> + .rate_table = imx8mm_pll1416x_tbl,
> + .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
> +};
> +
> +static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", 
> "dummy", };
> +static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", 
> };
> +static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
> +static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", 
> };
> +static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", 
> };
> +static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", 
> };
> +
> +static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", 
> "sys_pll2_500m", "sys_pll2_1000m",
> + "sys_pll1_800m", "sys_pll1_400m", 
> "audio_pll1_out", "sys_pll3_out", };
> +
> +static const char *imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", 
> "sys_pll1_800m", "sys_pll1_400m",
> + "sys_pll2_125m", "sys_pll3_out", 
> "audio_pll1_out", "video_pll1_out", };
> +
> +static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", 
> "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
> +  "sys_pll2_200m", "audio_pll1_out", 
> "video_pll1_out", "sys_pll3_out", };
> +
> +static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", 
> "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
> +"sys_pll1_133m", "sys_pll3_out", 
> "sys_pll2_250m", "audio_pll1_out", };
> +
> +static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", 
> "sys_pll1_800m", "sys_pll2_500m",
> +"sys_pll3_out", "sys_pll1_266m", 
> "audio_pll2_out", "sys_pll1_100m", };
> +
> +static const char *imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", 
> "sys_pll1_800m", 

Re: [U-Boot] [PATCH V3 3/4] clk: imx: add i.MX8M composite clk support

[Ye Li]

> Import i.MX8M composite clk from Linux Kernel 5.3.0-rc2
> 
> Signed-off-by: Peng Fan 
> ---
>  drivers/clk/imx/clk-composite-8m.c | 170 
> +
>  1 file changed, 170 insertions(+)
>  create mode 100644 drivers/clk/imx/clk-composite-8m.c
> 
> diff --git a/drivers/clk/imx/clk-composite-8m.c 
> b/drivers/clk/imx/clk-composite-8m.c
> new file mode 100644
> index 00..57ebbc3bb0
> --- /dev/null
> +++ b/drivers/clk/imx/clk-composite-8m.c
> @@ -0,0 +1,170 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2019 NXP
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include "clk.h"
> +
> +#define UBOOT_DM_CLK_IMX_COMPOSITE "imx_clk_composite"
> +
> +#define PCG_PREDIV_SHIFT 16
> +#define PCG_PREDIV_WIDTH 3
> +#define PCG_PREDIV_MAX   8
> +
> +#define PCG_DIV_SHIFT0
> +#define PCG_DIV_WIDTH6
> +#define PCG_DIV_MAX  64
> +
> +#define PCG_PCS_SHIFT24
> +#define PCG_PCS_MASK 0x7
> +
> +#define PCG_CGC_SHIFT28
> +
> +static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk *clk)
> +{
> + struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
> + struct clk_composite *composite = (struct clk_composite *)clk->data;
> + ulong parent_rate = clk_get_parent_rate(>clk);
> + unsigned long prediv_rate;
> + unsigned int prediv_value;
> + unsigned int div_value;
> +
> + debug("%s: name %s prate: %lu reg: %p\n", __func__,
> +   (>clk)->dev->name, parent_rate, divider->reg);
> + prediv_value = readl(divider->reg) >> divider->shift;
> + prediv_value &= clk_div_mask(divider->width);
> +
> + prediv_rate = divider_recalc_rate(clk, parent_rate, prediv_value,
> +   NULL, divider->flags,
> +   divider->width);
> +
> + div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
> + div_value &= clk_div_mask(PCG_DIV_WIDTH);
> +
> + return divider_recalc_rate(clk, prediv_rate, div_value, NULL,
> +divider->flags, PCG_DIV_WIDTH);
> +}
> +
> +static int imx8m_clk_composite_compute_dividers(unsigned long rate,
> + unsigned long parent_rate,
> + int *prediv, int *postdiv)
> +{
> + int div1, div2;
> + int error = INT_MAX;
> + int ret = -EINVAL;
> +
> + *prediv = 1;
> + *postdiv = 1;
> +
> + for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) {
> + for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) {
> + int new_error = ((parent_rate / div1) / div2) - rate;
> +
> + if (abs(new_error) < abs(error)) {
> + *prediv = div1;
> + *postdiv = div2;
> + error = new_error;
> + ret = 0;
> + }
> + }
> + }
> + return ret;
> +}
> +
> +/*
> + * The clk are not binded to a dev, because it is part of composite clk
> + * use composite clk to get dev
> + */
> +static ulong imx8m_clk_composite_divider_set_rate(struct clk *clk,
> +   unsigned long rate)
> +{
> + struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
> + struct clk_composite *composite = (struct clk_composite *)clk->data;
> + ulong parent_rate = clk_get_parent_rate(>clk);
> + int prediv_value;
> + int div_value;
> + int ret;
> + u32 val;
> +
> + ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,
> +_value, _value);
> + if (ret)
> + return -EINVAL;
> +
> + val = readl(divider->reg);
> + val &= ~((clk_div_mask(divider->width) << divider->shift) |
> + (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
> +
> + val |= (u32)(prediv_value  - 1) << divider->shift;
> + val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
> + writel(val, divider->reg);
> +
> + return clk_get_rate(>clk);
> +}
> +
> +static const struct clk_ops imx8m_clk_composite_divider_ops = {
> + .get_rate = imx8m_clk_composite_divider_recalc_rate,
> + .set_rate = imx8m_clk_composite_divider_set_rate,
> +};
> +
> +struct clk *imx8m_clk_composite_flags(const char *name,
> +   const char * const *parent_names,
> +   int num_parents, void __iomem *reg,
> +   unsigned long flags)
> +{
> + struct clk *clk = ERR_PTR(-ENOMEM);
> + struct clk_divider *div = NULL;
> + struct clk_gate *gate = NULL;
> + struct clk_mux *mux = NULL;
> +
> + mux = kzalloc(sizeof(*mux), GFP_KERNEL);
> + if (!mux)
> + goto fail;
> +
> + mux->reg = 

Re: [U-Boot] [PATCH V3 2/4] clk: imx: add pll14xx driver

[Ye Li]

> Add pll14xx driver
> 
> Signed-off-by: Peng Fan 
> ---
>  drivers/clk/imx/clk-pll14xx.c | 381 
> ++
>  drivers/clk/imx/clk.h |  25 +++
>  2 files changed, 406 insertions(+)
>  create mode 100644 drivers/clk/imx/clk-pll14xx.c
> 
> diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
> new file mode 100644
> index 00..2246beb21b
> --- /dev/null
> +++ b/drivers/clk/imx/clk-pll14xx.c
> @@ -0,0 +1,381 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2017-2019 NXP.
> + *
> + * Peng Fan 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "clk.h"
> +
> +#define UBOOT_DM_CLK_IMX_PLL1443X "imx_clk_pll1443x"
> +#define UBOOT_DM_CLK_IMX_PLL1416X "imx_clk_pll1416x"
> +
> +#define GNRL_CTL 0x0
> +#define DIV_CTL  0x4
> +#define LOCK_STATUS  BIT(31)
> +#define LOCK_SEL_MASKBIT(29)
> +#define CLKE_MASKBIT(11)
> +#define RST_MASK BIT(9)
> +#define BYPASS_MASK  BIT(4)
> +#define MDIV_SHIFT   12
> +#define MDIV_MASKGENMASK(21, 12)
> +#define PDIV_SHIFT   4
> +#define PDIV_MASKGENMASK(9, 4)
> +#define SDIV_SHIFT   0
> +#define SDIV_MASKGENMASK(2, 0)
> +#define KDIV_SHIFT   0
> +#define KDIV_MASKGENMASK(15, 0)
> +
> +#define LOCK_TIMEOUT_US  1
> +
> +struct clk_pll14xx {
> + struct clk  clk;
> + void __iomem*base;
> + enum imx_pll14xx_type   type;
> + const struct imx_pll14xx_rate_table *rate_table;
> + int rate_count;
> +};
> +
> +#define to_clk_pll14xx(_clk) container_of(_clk, struct clk_pll14xx, clk)
> +
> +static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
> + struct clk_pll14xx *pll, unsigned long rate)
> +{
> + const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
> + int i;
> +
> + for (i = 0; i < pll->rate_count; i++)
> + if (rate == rate_table[i].rate)
> + return _table[i];
> +
> + return NULL;
> +}
> +
> +static unsigned long clk_pll1416x_recalc_rate(struct clk *clk)
> +{
> + struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
> + u64 fvco = clk_get_parent_rate(clk);
> + u32 mdiv, pdiv, sdiv, pll_div;
> +
> + pll_div = readl(pll->base + 4);
> + mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
> + pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
> + sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
> +
> + fvco *= mdiv;
> + do_div(fvco, pdiv << sdiv);
> +
> + return fvco;
> +}
> +
> +static unsigned long clk_pll1443x_recalc_rate(struct clk *clk)
> +{
> + struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
> + u64 fvco = clk_get_parent_rate(clk);
> + u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1;
> + short int kdiv;
> +
> + pll_div_ctl0 = readl(pll->base + 4);
> + pll_div_ctl1 = readl(pll->base + 8);
> + mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
> + pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
> + sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
> + kdiv = pll_div_ctl1 & KDIV_MASK;
> +
> + /* fvco = (m * 65536 + k) * Fin / (p * 65536) */
> + fvco *= (mdiv * 65536 + kdiv);
> + pdiv *= 65536;
> +
> + do_div(fvco, pdiv << sdiv);
> +
> + return fvco;
> +}
> +
> +static inline bool clk_pll1416x_mp_change(const struct 
> imx_pll14xx_rate_table *rate,
> +   u32 pll_div)
> +{
> + u32 old_mdiv, old_pdiv;
> +
> + old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
> + old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
> +
> + return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
> +}
> +
> +static inline bool clk_pll1443x_mpk_change(const struct 
> imx_pll14xx_rate_table *rate,
> +u32 pll_div_ctl0, u32 pll_div_ctl1)
> +{
> + u32 old_mdiv, old_pdiv, old_kdiv;
> +
> + old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
> + old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
> + old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
> +
> + return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
> + rate->kdiv != old_kdiv;
> +}
> +
> +static inline bool clk_pll1443x_mp_change(const struct 
> imx_pll14xx_rate_table *rate,
> +   u32 pll_div_ctl0, u32 pll_div_ctl1)
> +{
> + u32 old_mdiv, old_pdiv, old_kdiv;
> +
> + old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
> + old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
> + old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
> +
> + return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
> + rate->kdiv != old_kdiv;
> +}
> +
> +static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
> +{
> + u32 val;
> +
> + return readl_poll_timeout(pll->base, val, 

Re: [U-Boot] [PATCH 0/3] Intel FPGA PCIe fixes

[Ley Foon Tan]

On Tue, Jun 11, 2019 at 8:30 AM Ley Foon Tan  wrote:
>
> On Fri, May 24, 2019 at 10:30 AM Ley Foon Tan  wrote:
> >
> > This patchset fix issues in Intel FPGA PCIe driver.
> > - Fix TLP polling timeout
> > - Fix enumerating mult-function PCIe device issue
> > - Fix PCIe switch read config register issue
> >
> > Ley Foon Tan (3):
> >   pci: intel: Increase TLP polling counter
> >   pci: intel: Fix error when enumerating multi-function PCIe device
> >   pci: intel: Fix configuration type based on secondary number
> >
> >  drivers/pci/pcie_intel_fpga.c | 18 +++---
> >  1 file changed, 11 insertions(+), 7 deletions(-)
> Any comment on these patches?
>
> Thanks
Hi Tom and Michal

Can you help to merge these patches?

Thanks.

Regards
Ley Foon
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Re: [U-Boot] [PATCH u-boot-marvell 1/1] pci: pci_mvebu: set BAR0 after memory space is set

[Stefan Roese]

On 07.08.19 15:01, Marek Behún wrote:

The non-DM version of this driver used to set BAR0 register after the
calls to pci_set_region.
I found out that for some strange reason the ath10k driver in kernel
fails to work if this is done the other way around.
I know that Linux's driver should not depend on how U-Boot does things,
but for some strange reason it does and this seems to be the simplest
solution. Fix it since it caused regressions on Omnia.

Signed-off-by: Marek Behún 
Cc: Stefan Roese 
Cc: Dirk Eibach 
Cc: Mario Six 
Cc: Chris Packham 
Cc: Phil Sutter 
Cc: VlaoMao 


Reviewed-by: Stefan Roese 

Thanks,
Stefan
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Re: [U-Boot] [PATCH V3 1/4] clk: imx: add Kconfig entry for i.MX8MM

[Ye Li]

> Add Kconfig entry for i.MX8MM
> 
> Signed-off-by: Peng Fan 
> ---
>  drivers/clk/Kconfig |  4 ++--
>  drivers/clk/imx/Kconfig | 16 
>  2 files changed, 18 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index a3f0171b45..fce595b4b3 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -48,7 +48,7 @@ config CLK_BOSTON
>  
>  config SPL_CLK_CCF
>   bool "SPL Common Clock Framework [CCF] support "
> - depends on SPL_CLK_IMX6Q
> + depends on SPL_CLK_IMX6Q || ARCH_IMX8M
>   help
> Enable this option if you want to (re-)use the Linux kernel's Common
> Clock Framework [CCF] code in U-Boot's SPL.
> @@ -62,7 +62,7 @@ config SPL_CLK_COMPOSITE_CCF
>  
>  config CLK_CCF
>   bool "Common Clock Framework [CCF] support "
> - depends on CLK_IMX6Q || SANDBOX_CLK_CCF
> + depends on CLK_IMX6Q || ARCH_IMX8M || SANDBOX_CLK_CCF
>   help
> Enable this option if you want to (re-)use the Linux kernel's Common
> Clock Framework [CCF] code in U-Boot's clock driver.
> diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
> index 3e6a980c8c..aae69cf9b0 100644
> --- a/drivers/clk/imx/Kconfig
> +++ b/drivers/clk/imx/Kconfig
> @@ -20,3 +20,19 @@ config CLK_IMX8
>   select CLK
>   help
> This enables support clock driver for i.MX8 platforms.
> +
> +config SPL_CLK_IMX8MM
> + bool "SPL clock support for i.MX8MM"
> + depends on ARCH_IMX8M && SPL
> + select SPL_CLK
> + select SPL_CLK_CCF
> + help
> +   This enables SPL DM/DTS support for clock driver in i.MX8MM
> +
> +config CLK_IMX8MM
> + bool "Clock support for i.MX8MM"
> + depends on ARCH_IMX8M
> + select CLK
> + select CLK_CCF
> + help
> +   This enables support clock driver for i.MX8MM platforms.
> 
Reviewed-by: Ye Li 

Best regards,
Ye Li
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Re: [U-Boot] [PATCH v2 5/5] imx: add i.MX6ULZ board

[Ye Li]

> Add i.MX6ULZ board support. the i.MX6ULZ is SW compatible
> with i.MX6ULL. so most code of i.MX6ULL can be reused
> by i.MX6ULZ.
> 
> Signed-off-by: Peng Fan 
> ---
> 
> V2:
>  Add entry in MAINTAINERS
> 
>  arch/arm/dts/imx6ulz-14x14-evk.dts| 22 ++
>  board/freescale/mx6ullevk/MAINTAINERS |  1 +
>  board/freescale/mx6ullevk/mx6ullevk.c | 10 ++--
>  configs/mx6ulz_14x14_evk_defconfig| 44 
> +++
>  include/configs/mx6ullevk.h   | 13 ++-
>  5 files changed, 87 insertions(+), 3 deletions(-)
>  create mode 100644 arch/arm/dts/imx6ulz-14x14-evk.dts
>  create mode 100644 configs/mx6ulz_14x14_evk_defconfig
> 
> diff --git a/arch/arm/dts/imx6ulz-14x14-evk.dts 
> b/arch/arm/dts/imx6ulz-14x14-evk.dts
> new file mode 100644
> index 00..483d9732c0
> --- /dev/null
> +++ b/arch/arm/dts/imx6ulz-14x14-evk.dts
> @@ -0,0 +1,22 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +//
> +// Copyright 2018 NXP.
> +
> +/dts-v1/;
> +
> +#include "imx6ulz.dtsi"
> +#include "imx6ul-14x14-evk.dtsi"
> +
> +/delete-node/ 
> +/delete-node/ 
> +/delete-node/ 
> +/delete-node/ 
> +/delete-node/ 
> +/delete-node/ 
> +
> +/ {
> + model = "Freescale i.MX6 ULZ 14x14 EVK Board";
> + compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz";
> +
> + /delete-node/ panel;
> +};
> diff --git a/board/freescale/mx6ullevk/MAINTAINERS 
> b/board/freescale/mx6ullevk/MAINTAINERS
> index 73031cd121..3d1b256036 100644
> --- a/board/freescale/mx6ullevk/MAINTAINERS
> +++ b/board/freescale/mx6ullevk/MAINTAINERS
> @@ -5,3 +5,4 @@ F:board/freescale/mx6ullevk/
>  F:   include/configs/mx6ullevk.h
>  F:   configs/mx6ull_14x14_evk_defconfig
>  F:   configs/mx6ull_14x14_evk_plugin_defconfig
> +F:   configs/mx6ulz_14x14_evk_defconfig
> diff --git a/board/freescale/mx6ullevk/mx6ullevk.c 
> b/board/freescale/mx6ullevk/mx6ullevk.c
> index 1f0f70efbd..0a35eeb95e 100644
> --- a/board/freescale/mx6ullevk/mx6ullevk.c
> +++ b/board/freescale/mx6ullevk/mx6ullevk.c
> @@ -83,7 +83,10 @@ int board_late_init(void)
>  #endif
>  
>  #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> - env_set("board_name", "EVK");
> + if (is_cpu_type(MXC_CPU_MX6ULZ))
> + env_set("board_name", "ULZ-EVK");
> + else
> + env_set("board_name", "EVK");
>   env_set("board_rev", "14X14");
>  #endif
>  
> @@ -92,7 +95,10 @@ int board_late_init(void)
>  
>  int checkboard(void)
>  {
> - puts("Board: MX6ULL 14x14 EVK\n");
> + if (is_cpu_type(MXC_CPU_MX6ULZ))
> + puts("Board: MX6ULZ 14x14 EVK\n");
> + else
> + puts("Board: MX6ULL 14x14 EVK\n");
>  
>   return 0;
>  }
> diff --git a/configs/mx6ulz_14x14_evk_defconfig 
> b/configs/mx6ulz_14x14_evk_defconfig
> new file mode 100644
> index 00..f647d72c6e
> --- /dev/null
> +++ b/configs/mx6ulz_14x14_evk_defconfig
> @@ -0,0 +1,44 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_MX6=y
> +CONFIG_SYS_TEXT_BASE=0x8780
> +CONFIG_TARGET_MX6ULL_14X14_EVK=y
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg"
> +CONFIG_SUPPORT_RAW_INITRD=y
> +CONFIG_BOUNCE_BUFFER=y
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_CMD_BOOTZ=y
> +CONFIG_CMD_MEMTEST=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_EXT2=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_CMD_FS_GENERIC=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk"
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> +CONFIG_DM_GPIO=y
> +CONFIG_DM_74X164=y
> +CONFIG_DM_I2C=y
> +CONFIG_DM_MMC=y
> +CONFIG_FSL_ESDHC_IMX=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SF_DEFAULT_MODE=0
> +CONFIG_SF_DEFAULT_SPEED=4000
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_IMX6=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_SPI=y
> +CONFIG_DM_SPI=y
> +CONFIG_FSL_QSPI=y
> diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h
> index 1fc5c24dec..f5f3de6cd4 100644
> --- a/include/configs/mx6ullevk.h
> +++ b/include/configs/mx6ullevk.h
> @@ -55,7 +55,7 @@
>   "console=ttymxc0\0" \
>   "fdt_high=0x\0" \
>   "initrd_high=0x\0" \
> - "fdt_file=imx6ull-14x14-evk.dtb\0" \
> + "fdt_file=undefined\0" \
>   "fdt_addr=0x8300\0" \
>   "boot_fdt=try\0" \
>   "ip_dyn=yes\0" \
> @@ -87,6 +87,16 @@
>   "else " \
>   "bootz; " \
>   "fi;\0" \
> + "findfdt="\
> + "if test $fdt_file = undefined; then " \
> + "if test $board_name = ULZ-EVK && test 
> $board_rev = 14X14; then " \
> + "setenv fdt_file imx6ulz-14x14-evk.dtb; 
> fi; " \
> + "if test $board_name = EVK && test 

Re: [U-Boot] [PATCH v2 4/5] imx: add i.MX6ULZ cpu type

[Ye Li]

> Add i.MX6ULZ cpu type and helper.
> 
> Signed-off-by: Peng Fan 
> ---
> 
> V2:
>  None
> 
>  arch/arm/include/asm/arch-imx/cpu.h   | 1 +
>  arch/arm/include/asm/mach-imx/sys_proto.h | 1 +
>  arch/arm/mach-imx/cpu.c   | 2 ++
>  arch/arm/mach-imx/mx6/soc.c   | 4 
>  4 files changed, 8 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-imx/cpu.h 
> b/arch/arm/include/asm/arch-imx/cpu.h
> index d4a83eef72..073efcd1b4 100644
> --- a/arch/arm/include/asm/arch-imx/cpu.h
> +++ b/arch/arm/include/asm/arch-imx/cpu.h
> @@ -17,6 +17,7 @@
>  #define MXC_CPU_MX6Q 0x63
>  #define MXC_CPU_MX6UL0x64
>  #define MXC_CPU_MX6ULL   0x65
> +#define MXC_CPU_MX6ULZ   0x6B
>  #define MXC_CPU_MX6SOLO  0x66 /* dummy */
>  #define MXC_CPU_MX6SLL   0x67
>  #define MXC_CPU_MX6D 0x6A
> diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h 
> b/arch/arm/include/asm/mach-imx/sys_proto.h
> index 4925dd7894..260608062e 100644
> --- a/arch/arm/include/asm/mach-imx/sys_proto.h
> +++ b/arch/arm/include/asm/mach-imx/sys_proto.h
> @@ -38,6 +38,7 @@
>  #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
>  #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
>  #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
> +#define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ))
>  #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
>  
>  #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
> diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
> index 6e9a175210..73ce7f8d7d 100644
> --- a/arch/arm/mach-imx/cpu.c
> +++ b/arch/arm/mach-imx/cpu.c
> @@ -173,6 +173,8 @@ const char *get_imx_type(u32 imxtype)
>   return "6UL";   /* Ultra-Lite version of the mx6 */
>   case MXC_CPU_MX6ULL:
>   return "6ULL";  /* ULL version of the mx6 */
> + case MXC_CPU_MX6ULZ:
> + return "6ULZ";  /* ULZ version of the mx6 */
>   case MXC_CPU_MX51:
>   return "51";
>   case MXC_CPU_MX53:
> diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
> index 075d2467ce..d37d3856d3 100644
> --- a/arch/arm/mach-imx/mx6/soc.c
> +++ b/arch/arm/mach-imx/mx6/soc.c
> @@ -85,6 +85,10 @@ u32 get_cpu_rev(void)
>   type = MXC_CPU_MX6D;
>   }
>  
> + if (type == MXC_CPU_MX6ULL) {
> + if (readl(SRC_BASE_ADDR + 0x1c) & (1 << 6))
> + type = MXC_CPU_MX6ULZ;
> + }
>   }
>   major = ((reg >> 8) & 0xff);
>   if ((major >= 1) &&
> 
Reviewed-by: Ye Li 

Best regards,
Ye Li
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Re: [U-Boot] [PATCH v2 3/5] arm: dts: import dts for i.MX6ULZ

[Ye Li]

> Import kernel dts for i.MX6ULZ from
> commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of 
> git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux")
> 
> Signed-off-by: Peng Fan 
> ---
> 
> V2:
>  None
> 
>  arch/arm/dts/Makefile |  3 ++-
>  arch/arm/dts/imx6ulz.dtsi | 37 +
>  2 files changed, 39 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/imx6ulz.dtsi
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index ad4d2357bb..2088acdc60 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -599,7 +599,8 @@ dtb-$(CONFIG_MX6ULL) += \
>   imx6ull-14x14-evk.dtb \
>   imx6ull-colibri.dtb \
>   imx6ull-phycore-segin.dtb \
> - imx6ull-dart-6ul.dtb
> + imx6ull-dart-6ul.dtb \
> + imx6ulz-14x14-evk.dtb
>  
>  dtb-$(CONFIG_ARCH_MX6) += \
>   imx6-apalis.dtb \
> diff --git a/arch/arm/dts/imx6ulz.dtsi b/arch/arm/dts/imx6ulz.dtsi
> new file mode 100644
> index 00..aeb2ddc540
> --- /dev/null
> +++ b/arch/arm/dts/imx6ulz.dtsi
> @@ -0,0 +1,37 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +//
> +// Copyright 2018 NXP.
> +
> +#include "imx6ull.dtsi"
> +
> +/ {
> + aliases {
> + /delete-property/ ethernet0;
> + /delete-property/ ethernet1;
> + /delete-property/ i2c2;
> + /delete-property/ i2c3;
> + /delete-property/ serial4;
> + /delete-property/ serial5;
> + /delete-property/ serial6;
> + /delete-property/ serial7;
> + /delete-property/ spi2;
> + /delete-property/ spi3;
> + /delete-property/ spi4;
> + };
> +};
> +
> +/delete-node/ 
> +/delete-node/ 
> +/delete-node/ 
> +/delete-node/ 
> +/delete-node/ 
> +/delete-node/ 
> +/delete-node/ 
> +/delete-node/ 
> +/delete-node/ 
> +/delete-node/ 
> +/delete-node/ 
> +/delete-node/ 
> +/delete-node/ 
> +/delete-node/ 
> +/delete-node/ 
> 
Reviewed-by: Ye Li 

Best regards,
Ye Li

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Re: [U-Boot] [PATCH v2 2/5] arm: dts: sync dts for i.MX6ULL

[Ye Li]

> Sync kernel dts for i.MX6ULL from
> commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of 
> git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux")
> 
> Signed-off-by: Peng Fan 
> ---
> 
> V2:
>  None
> 
>  arch/arm/dts/imx6ull-14x14-evk.dts  |  523 +---
>  arch/arm/dts/imx6ull-pinfunc-snvs.h |7 +-
>  arch/arm/dts/imx6ull-pinfunc.h  |  116 ++--
>  arch/arm/dts/imx6ull.dtsi   | 1184 
> ++-
>  4 files changed, 127 insertions(+), 1703 deletions(-)
> 
> diff --git a/arch/arm/dts/imx6ull-14x14-evk.dts 
> b/arch/arm/dts/imx6ull-14x14-evk.dts
> index 9ebcfe1f4e..74aaa8a56a 100644
> --- a/arch/arm/dts/imx6ull-14x14-evk.dts
> +++ b/arch/arm/dts/imx6ull-14x14-evk.dts
> @@ -1,527 +1,18 @@
> -/*
> - * Copyright (C) 2016 Freescale Semiconductor, Inc.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - */
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +//
> +// Copyright (C) 2016 Freescale Semiconductor, Inc.
>  
>  /dts-v1/;
>  
>  #include "imx6ull.dtsi"
> +#include "imx6ul-14x14-evk.dtsi"
>  
>  / {
> - model = "Freescale i.MX6 ULL 14x14 EVK Board";
> + model = "Freescale i.MX6 UltraLiteLite 14x14 EVK Board";
>   compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
> -
> - chosen {
> - stdout-path = 
> - };
> -
> - memory {
> - reg = <0x8000 0x2000>;
> - };
> -
> - backlight {
> - compatible = "pwm-backlight";
> - pwms = < 0 500>;
> - brightness-levels = <0 4 8 16 32 64 128 255>;
> - default-brightness-level = <6>;
> - status = "okay";
> - };
> -
> - regulators {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - reg_can_3v3: regulator@0 {
> - compatible = "regulator-fixed";
> - reg = <0>;
> - regulator-name = "can-3v3";
> - regulator-min-microvolt = <330>;
> - regulator-max-microvolt = <330>;
> - gpios = <_spi 3 GPIO_ACTIVE_LOW>;
> - };
> -
> - reg_sd1_vmmc: regulator@1 {
> - compatible = "regulator-fixed";
> - regulator-name = "VSD_3V3";
> - regulator-min-microvolt = <330>;
> - regulator-max-microvolt = <330>;
> - gpio = < 9 GPIO_ACTIVE_HIGH>;
> - enable-active-high;
> - };
> -
> - reg_gpio_dvfs: regulator-gpio {
> - compatible = "regulator-gpio";
> - pinctrl-names = "default";
> - pinctrl-0 = <_dvfs>;
> - regulator-min-microvolt = <130>;
> - regulator-max-microvolt = <140>;
> - regulator-name = "gpio_dvfs";
> - regulator-type = "voltage";
> - gpios = < 3 GPIO_ACTIVE_HIGH>;
> - states = <130 0x1 140 0x0>;
> - };
> - };
> -
> - spi5 {
> - compatible = "spi-gpio";
> - pinctrl-names = "default";
> - pinctrl-0 = <_spi4>;
> - status = "okay";
> - gpio-sck = < 11 0>;
> - gpio-mosi = < 10 0>;
> - cs-gpios = < 7 0>;
> - num-chipselects = <1>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - gpio_spi: gpio_spi@0 {
> - compatible = "fairchild,74hc595";
> - gpio-controller;
> - oe-gpios = < 8 0>;
> - #gpio-cells = <2>;
> - reg = <0>;
> - registers-number = <1>;
> - registers-default = /bits/ 8 <0x57>;
> - spi-max-frequency = <10>;
> - };
> - };
> -};
> -
> - {
> - arm-supply = <_arm>;
> - soc-supply = <_soc>;
> - dc-supply = <_gpio_dvfs>;
>  };
>  
>   {
> - assigned-clocks = < IMX6UL_CLK_PLL4_AUDIO_DIV>;
> - assigned-clock-rates = <786432000>;
> -};
> -
> - {
> - pinctrl-names = "default";
> - pinctrl-0 = <_enet1>;
> - phy-mode = "rmii";
> - phy-handle = <>;
> - status = "okay";
> -};
> -
> - {
> - pinctrl-names = "default";
> - pinctrl-0 = <_enet2>;
> - phy-mode = "rmii";
> - phy-handle = <>;
> - status = "okay";
> -
> - mdio {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - ethphy0: ethernet-phy@2 {
> - compatible = "ethernet-phy-ieee802.3-c22";
> - reg = <2>;
> - };
> -
> - ethphy1: 

[U-Boot] [PATCH V3 4/4] clk: imx: add i.MX8MM clk driver

[Peng Fan]

Add i.MX8MM clk driver support.

Signed-off-by: Peng Fan 
---
 drivers/clk/imx/Makefile |   2 +
 drivers/clk/imx/clk-imx8mm.c | 415 +++
 2 files changed, 417 insertions(+)
 create mode 100644 drivers/clk/imx/clk-imx8mm.c

diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 105a58ca90..5ad7967fe9 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -10,3 +10,5 @@ ifdef CONFIG_CLK_IMX8
 obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o
 obj-$(CONFIG_IMX8QM) += clk-imx8qm.o
 endif
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \
+   clk-composite-8m.o
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
new file mode 100644
index 00..a2a85b6a1a
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -0,0 +1,415 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ * Peng Fan 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clk.h"
+
+#define PLL_1416X_RATE(_rate, _m, _p, _s)  \
+   {   \
+   .rate   =   (_rate),\
+   .mdiv   =   (_m),   \
+   .pdiv   =   (_p),   \
+   .sdiv   =   (_s),   \
+   }
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k)  \
+   {   \
+   .rate   =   (_rate),\
+   .mdiv   =   (_m),   \
+   .pdiv   =   (_p),   \
+   .sdiv   =   (_s),   \
+   .kdiv   =   (_k),   \
+   }
+
+static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
+   PLL_1416X_RATE(18U, 225, 3, 0),
+   PLL_1416X_RATE(16U, 200, 3, 0),
+   PLL_1416X_RATE(12U, 300, 3, 1),
+   PLL_1416X_RATE(10U, 250, 3, 1),
+   PLL_1416X_RATE(8U,  200, 3, 1),
+   PLL_1416X_RATE(75000U,  250, 2, 2),
+   PLL_1416X_RATE(7U,  350, 3, 2),
+   PLL_1416X_RATE(6U,  300, 3, 2),
+};
+
+static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
+   PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+};
+
+static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
+   .type = PLL_1443X,
+   .rate_table = imx8mm_drampll_tbl,
+   .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
+};
+
+static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
+   .type = PLL_1416X,
+   .rate_table = imx8mm_pll1416x_tbl,
+   .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
+};
+
+static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
+   .type = PLL_1416X,
+   .rate_table = imx8mm_pll1416x_tbl,
+   .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
+};
+
+static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", 
"dummy", };
+static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
+static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
+static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
+static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
+static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
+
+static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", 
"sys_pll2_500m", "sys_pll2_1000m",
+   "sys_pll1_800m", "sys_pll1_400m", 
"audio_pll1_out", "sys_pll3_out", };
+
+static const char *imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", 
"sys_pll1_800m", "sys_pll1_400m",
+   "sys_pll2_125m", "sys_pll3_out", 
"audio_pll1_out", "video_pll1_out", };
+
+static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", 
"sys_pll1_800m", "sys_pll2_250m",
+"sys_pll2_200m", "audio_pll1_out", 
"video_pll1_out", "sys_pll3_out", };
+
+static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", 
"sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
+  "sys_pll1_133m", "sys_pll3_out", 
"sys_pll2_250m", "audio_pll1_out", };
+
+static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", 
"sys_pll1_800m", "sys_pll2_500m",
+  "sys_pll3_out", "sys_pll1_266m", 
"audio_pll2_out", "sys_pll1_100m", };
+
+static const char *imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", 
"sys_pll1_800m", "sys_pll2_500m",
+  "sys_pll3_out", "sys_pll1_266m", 
"audio_pll2_out", "sys_pll1_100m", };
+
+static const char *imx8mm_i2c1_sels[] = {"clock-osc-24m", 

[U-Boot] [PATCH V3 2/4] clk: imx: add pll14xx driver

[Peng Fan]

Add pll14xx driver

Signed-off-by: Peng Fan 
---
 drivers/clk/imx/clk-pll14xx.c | 381 ++
 drivers/clk/imx/clk.h |  25 +++
 2 files changed, 406 insertions(+)
 create mode 100644 drivers/clk/imx/clk-pll14xx.c

diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
new file mode 100644
index 00..2246beb21b
--- /dev/null
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -0,0 +1,381 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2017-2019 NXP.
+ *
+ * Peng Fan 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clk.h"
+
+#define UBOOT_DM_CLK_IMX_PLL1443X "imx_clk_pll1443x"
+#define UBOOT_DM_CLK_IMX_PLL1416X "imx_clk_pll1416x"
+
+#define GNRL_CTL   0x0
+#define DIV_CTL0x4
+#define LOCK_STATUSBIT(31)
+#define LOCK_SEL_MASK  BIT(29)
+#define CLKE_MASK  BIT(11)
+#define RST_MASK   BIT(9)
+#define BYPASS_MASKBIT(4)
+#define MDIV_SHIFT 12
+#define MDIV_MASK  GENMASK(21, 12)
+#define PDIV_SHIFT 4
+#define PDIV_MASK  GENMASK(9, 4)
+#define SDIV_SHIFT 0
+#define SDIV_MASK  GENMASK(2, 0)
+#define KDIV_SHIFT 0
+#define KDIV_MASK  GENMASK(15, 0)
+
+#define LOCK_TIMEOUT_US1
+
+struct clk_pll14xx {
+   struct clk  clk;
+   void __iomem*base;
+   enum imx_pll14xx_type   type;
+   const struct imx_pll14xx_rate_table *rate_table;
+   int rate_count;
+};
+
+#define to_clk_pll14xx(_clk) container_of(_clk, struct clk_pll14xx, clk)
+
+static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
+   struct clk_pll14xx *pll, unsigned long rate)
+{
+   const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
+   int i;
+
+   for (i = 0; i < pll->rate_count; i++)
+   if (rate == rate_table[i].rate)
+   return _table[i];
+
+   return NULL;
+}
+
+static unsigned long clk_pll1416x_recalc_rate(struct clk *clk)
+{
+   struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
+   u64 fvco = clk_get_parent_rate(clk);
+   u32 mdiv, pdiv, sdiv, pll_div;
+
+   pll_div = readl(pll->base + 4);
+   mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
+   pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
+   sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
+
+   fvco *= mdiv;
+   do_div(fvco, pdiv << sdiv);
+
+   return fvco;
+}
+
+static unsigned long clk_pll1443x_recalc_rate(struct clk *clk)
+{
+   struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
+   u64 fvco = clk_get_parent_rate(clk);
+   u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1;
+   short int kdiv;
+
+   pll_div_ctl0 = readl(pll->base + 4);
+   pll_div_ctl1 = readl(pll->base + 8);
+   mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
+   pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
+   sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
+   kdiv = pll_div_ctl1 & KDIV_MASK;
+
+   /* fvco = (m * 65536 + k) * Fin / (p * 65536) */
+   fvco *= (mdiv * 65536 + kdiv);
+   pdiv *= 65536;
+
+   do_div(fvco, pdiv << sdiv);
+
+   return fvco;
+}
+
+static inline bool clk_pll1416x_mp_change(const struct imx_pll14xx_rate_table 
*rate,
+ u32 pll_div)
+{
+   u32 old_mdiv, old_pdiv;
+
+   old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
+   old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
+
+   return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
+}
+
+static inline bool clk_pll1443x_mpk_change(const struct imx_pll14xx_rate_table 
*rate,
+  u32 pll_div_ctl0, u32 pll_div_ctl1)
+{
+   u32 old_mdiv, old_pdiv, old_kdiv;
+
+   old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
+   old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
+   old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
+
+   return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
+   rate->kdiv != old_kdiv;
+}
+
+static inline bool clk_pll1443x_mp_change(const struct imx_pll14xx_rate_table 
*rate,
+ u32 pll_div_ctl0, u32 pll_div_ctl1)
+{
+   u32 old_mdiv, old_pdiv, old_kdiv;
+
+   old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
+   old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
+   old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
+
+   return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
+   rate->kdiv != old_kdiv;
+}
+
+static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
+{
+   u32 val;
+
+   return readl_poll_timeout(pll->base, val, val & LOCK_TIMEOUT_US,
+   LOCK_TIMEOUT_US);
+}
+
+static ulong clk_pll1416x_set_rate(struct clk *clk, unsigned long drate)
+{
+   struct clk_pll14xx *pll = 

[U-Boot] [PATCH V3 3/4] clk: imx: add i.MX8M composite clk support

[Peng Fan]

Import i.MX8M composite clk from Linux Kernel 5.3.0-rc2

Signed-off-by: Peng Fan 
---
 drivers/clk/imx/clk-composite-8m.c | 170 +
 1 file changed, 170 insertions(+)
 create mode 100644 drivers/clk/imx/clk-composite-8m.c

diff --git a/drivers/clk/imx/clk-composite-8m.c 
b/drivers/clk/imx/clk-composite-8m.c
new file mode 100644
index 00..57ebbc3bb0
--- /dev/null
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "clk.h"
+
+#define UBOOT_DM_CLK_IMX_COMPOSITE "imx_clk_composite"
+
+#define PCG_PREDIV_SHIFT   16
+#define PCG_PREDIV_WIDTH   3
+#define PCG_PREDIV_MAX 8
+
+#define PCG_DIV_SHIFT  0
+#define PCG_DIV_WIDTH  6
+#define PCG_DIV_MAX64
+
+#define PCG_PCS_SHIFT  24
+#define PCG_PCS_MASK   0x7
+
+#define PCG_CGC_SHIFT  28
+
+static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk *clk)
+{
+   struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
+   struct clk_composite *composite = (struct clk_composite *)clk->data;
+   ulong parent_rate = clk_get_parent_rate(>clk);
+   unsigned long prediv_rate;
+   unsigned int prediv_value;
+   unsigned int div_value;
+
+   debug("%s: name %s prate: %lu reg: %p\n", __func__,
+ (>clk)->dev->name, parent_rate, divider->reg);
+   prediv_value = readl(divider->reg) >> divider->shift;
+   prediv_value &= clk_div_mask(divider->width);
+
+   prediv_rate = divider_recalc_rate(clk, parent_rate, prediv_value,
+ NULL, divider->flags,
+ divider->width);
+
+   div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
+   div_value &= clk_div_mask(PCG_DIV_WIDTH);
+
+   return divider_recalc_rate(clk, prediv_rate, div_value, NULL,
+  divider->flags, PCG_DIV_WIDTH);
+}
+
+static int imx8m_clk_composite_compute_dividers(unsigned long rate,
+   unsigned long parent_rate,
+   int *prediv, int *postdiv)
+{
+   int div1, div2;
+   int error = INT_MAX;
+   int ret = -EINVAL;
+
+   *prediv = 1;
+   *postdiv = 1;
+
+   for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) {
+   for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) {
+   int new_error = ((parent_rate / div1) / div2) - rate;
+
+   if (abs(new_error) < abs(error)) {
+   *prediv = div1;
+   *postdiv = div2;
+   error = new_error;
+   ret = 0;
+   }
+   }
+   }
+   return ret;
+}
+
+/*
+ * The clk are not binded to a dev, because it is part of composite clk
+ * use composite clk to get dev
+ */
+static ulong imx8m_clk_composite_divider_set_rate(struct clk *clk,
+ unsigned long rate)
+{
+   struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
+   struct clk_composite *composite = (struct clk_composite *)clk->data;
+   ulong parent_rate = clk_get_parent_rate(>clk);
+   int prediv_value;
+   int div_value;
+   int ret;
+   u32 val;
+
+   ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,
+  _value, _value);
+   if (ret)
+   return -EINVAL;
+
+   val = readl(divider->reg);
+   val &= ~((clk_div_mask(divider->width) << divider->shift) |
+   (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
+
+   val |= (u32)(prediv_value  - 1) << divider->shift;
+   val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
+   writel(val, divider->reg);
+
+   return clk_get_rate(>clk);
+}
+
+static const struct clk_ops imx8m_clk_composite_divider_ops = {
+   .get_rate = imx8m_clk_composite_divider_recalc_rate,
+   .set_rate = imx8m_clk_composite_divider_set_rate,
+};
+
+struct clk *imx8m_clk_composite_flags(const char *name,
+ const char * const *parent_names,
+ int num_parents, void __iomem *reg,
+ unsigned long flags)
+{
+   struct clk *clk = ERR_PTR(-ENOMEM);
+   struct clk_divider *div = NULL;
+   struct clk_gate *gate = NULL;
+   struct clk_mux *mux = NULL;
+
+   mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+   if (!mux)
+   goto fail;
+
+   mux->reg = reg;
+   mux->shift = PCG_PCS_SHIFT;
+   mux->mask = PCG_PCS_MASK;
+   mux->num_parents = num_parents;
+   mux->flags = flags;
+   mux->parent_names = 

[U-Boot] [PATCH V3 1/4] clk: imx: add Kconfig entry for i.MX8MM

[Peng Fan]

Add Kconfig entry for i.MX8MM

Signed-off-by: Peng Fan 
---
 drivers/clk/Kconfig |  4 ++--
 drivers/clk/imx/Kconfig | 16 
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index a3f0171b45..fce595b4b3 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -48,7 +48,7 @@ config CLK_BOSTON
 
 config SPL_CLK_CCF
bool "SPL Common Clock Framework [CCF] support "
-   depends on SPL_CLK_IMX6Q
+   depends on SPL_CLK_IMX6Q || ARCH_IMX8M
help
  Enable this option if you want to (re-)use the Linux kernel's Common
  Clock Framework [CCF] code in U-Boot's SPL.
@@ -62,7 +62,7 @@ config SPL_CLK_COMPOSITE_CCF
 
 config CLK_CCF
bool "Common Clock Framework [CCF] support "
-   depends on CLK_IMX6Q || SANDBOX_CLK_CCF
+   depends on CLK_IMX6Q || ARCH_IMX8M || SANDBOX_CLK_CCF
help
  Enable this option if you want to (re-)use the Linux kernel's Common
  Clock Framework [CCF] code in U-Boot's clock driver.
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 3e6a980c8c..aae69cf9b0 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -20,3 +20,19 @@ config CLK_IMX8
select CLK
help
  This enables support clock driver for i.MX8 platforms.
+
+config SPL_CLK_IMX8MM
+   bool "SPL clock support for i.MX8MM"
+   depends on ARCH_IMX8M && SPL
+   select SPL_CLK
+   select SPL_CLK_CCF
+   help
+ This enables SPL DM/DTS support for clock driver in i.MX8MM
+
+config CLK_IMX8MM
+   bool "Clock support for i.MX8MM"
+   depends on ARCH_IMX8M
+   select CLK
+   select CLK_CCF
+   help
+ This enables support clock driver for i.MX8MM platforms.
-- 
2.16.4

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[U-Boot] [PATCH V3 0/4] Prepare i.MX8MM clk

[Peng Fan]

V3:
 2/4: Fix RST/BYPASS seq issue to avoid glitch
 4/4: ARM clk not use 24M for switch, use pll2_500m  Add R-b/A-b tag
  Fix pll gate shift bit.

V2:
 2/4: fix MASK/SHIFT usage

This is to support i.MX8MM clk driver.
i.MX8MM use similar clock design as i.MX7D, but it has use
different PLL, so we need to add pll14xx driver. And to simplify
the clock usage, import the composite clk driver from Linux Kernel,
then we could have simple clk tree.

This is to split the previous patchset
https://github.com/MrVan/u-boot/commits/imx8mmn-ccf
for i.MX8MM/N support

There are some checkpatch warnings that not addressed,
because import from Linux Kernel.

Peng Fan (4):
  clk: imx: add Kconfig entry for i.MX8MM
  clk: imx: add pll14xx driver
  clk: imx: add i.MX8M composite clk support
  clk: imx: add i.MX8MM clk driver

 drivers/clk/Kconfig|   4 +-
 drivers/clk/imx/Kconfig|  16 ++
 drivers/clk/imx/Makefile   |   2 +
 drivers/clk/imx/clk-composite-8m.c | 170 +++
 drivers/clk/imx/clk-imx8mm.c   | 415 +
 drivers/clk/imx/clk-pll14xx.c  | 381 ++
 drivers/clk/imx/clk.h  |  25 +++
 7 files changed, 1011 insertions(+), 2 deletions(-)
 create mode 100644 drivers/clk/imx/clk-composite-8m.c
 create mode 100644 drivers/clk/imx/clk-imx8mm.c
 create mode 100644 drivers/clk/imx/clk-pll14xx.c

-- 
2.16.4

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[U-Boot] [PATCH] board: ls1028a: set up integrated PCI stream IDs and cache attributes

[Alex Marginean]

Configure stream IDs for integrated PCI devices.  There are hardware
defaults but unfortunately they are outside the acceptable range for
SMMU, so we need to tune them down.  Use values based on Linux device tree
iommu-map or, if missing, start from HW base value shifted down by 4.

Signed-off-by: Alex Marginean 
---
 board/freescale/ls1028a/ls1028a.c | 64 +++
 1 file changed, 64 insertions(+)

diff --git a/board/freescale/ls1028a/ls1028a.c 
b/board/freescale/ls1028a/ls1028a.c
index 49a9292c31..05eac6f9c4 100644
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -118,6 +118,67 @@ void detail_board_ddr_info(void)
 }
 
 #ifdef CONFIG_OF_BOARD_SETUP
+
+/*
+ * Hardware default stream IDs are 0x4000 + PCI function #, but that's outside
+ * the acceptable range for SMMU.  Use Linux DT values instead or at least
+ * smaller defaults.
+ */
+#define ECAM_NUM_PFS   7
+#define ECAM_IERB_BASE 0x1F080
+#define ECAM_PFAMQ(pf, vf) ((ECAM_IERB_BASE + 0x800 + (pf) * \
+ 0x1000 + (vf) * 4))
+/* cache related transaction attributes for PCIe functions */
+#define ECAM_IERB_MSICAR   (ECAM_IERB_BASE + 0xa400)
+#define ECAM_IERB_MSICAR_VALUE 0x30
+
+/* number of VFs per PF, VFs have their own AMQ settings */
+static const u8 enetc_vfs[ECAM_NUM_PFS] = { 2, 2 };
+
+void setup_ecam_amq(void *blob)
+{
+   int streamid, sid_base, off;
+   int pf, vf, vfnn = 1;
+   u32 iommu_map[4];
+   int err;
+
+   /*
+* Look up the stream ID settings in the DT, if found apply the values
+* to HW, otherwise use HW values shifted down by 4.
+*/
+   off = fdt_node_offset_by_compatible(blob, 0, "pci-host-ecam-generic");
+   if (off < 0) {
+   debug("ECAM node not found\n");
+   return;
+   }
+
+   err = fdtdec_get_int_array(blob, off, "iommu-map", iommu_map, 4);
+   if (err) {
+   sid_base = in_le32(ECAM_PFAMQ(0, 0)) >> 4;
+   debug("\"iommu-map\" not found, using default SID base %04x\n",
+ sid_base);
+   } else {
+   sid_base = iommu_map[2];
+   }
+   /* set up AMQs for all integrated PCI functions */
+   for (pf = 0; pf < ECAM_NUM_PFS; pf++) {
+   streamid = sid_base + pf;
+   out_le32(ECAM_PFAMQ(pf, 0), streamid);
+
+   /* set up AMQs for VFs, if any */
+   for (vf = 0; vf < enetc_vfs[pf]; vf++, vfnn++) {
+   streamid = sid_base + ECAM_NUM_PFS + vfnn;
+   out_le32(ECAM_PFAMQ(pf, vf + 1), streamid);
+   }
+   }
+}
+
+void setup_ecam_cacheattr(void)
+{
+   /* set MSI cache attributes */
+   out_le32(ECAM_IERB_MSICAR, ECAM_IERB_MSICAR_VALUE);
+}
+
 int ft_board_setup(void *blob, bd_t *bd)
 {
u64 base[CONFIG_NR_DRAM_BANKS];
@@ -143,6 +204,9 @@ int ft_board_setup(void *blob, bd_t *bd)
 
fdt_fixup_memory_banks(blob, base, size, 2);
 
+   setup_ecam_amq(blob);
+   setup_ecam_cacheattr();
+
return 0;
 }
 #endif
-- 
2.17.1

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[U-Boot] Pull request: u-boot-rockchip-20190809

[Kever Yang]

Hi Tom,

Please pull the rockchip update:
- Add rk3399 boards Khadas Edge/-V/-Captain
- Add fully souce code support for rk3328 including TPL/DRAM init
- Enable boot from eMMC for rk3399 rock960/ficus boards
- turn on the IO supply for dw_mmc

Travis:
https://travis-ci.org/keveryang/u-boot/builds/567879982

Thanks,
- Kever

The following changes since commit d0d07ba86afc8074d79e436b1ba4478fa0f0c1b5:

  Prepare v2019.10-rc1 (2019-07-29 21:16:16 -0400)

are available in the Git repository at:

  https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip.git 
tags/u-boot-rockchip-20190809

for you to fetch changes up to 6a452e5bd33cf8f4e851445f29ab94b66485700a:

  doc: rockchip: Adapt Pine64 Rock64 board instructions (2019-08-05 21:18:35 
+0800)


Kever Yang (5):
  rockchip: rk3328: set DDR as non-secure in SPL
  rockchip: ram: add full feature rk3328 DRAM driver
  rockchip: dts: rk3328: update dmc node for driver
  rockchip: Kconfig: enable TPL support for rk3328
  rockchip: evb-rk3328: enable defconfig options for TPL/SPL

Manivannan Sadhasivam (2):
  arm: dts: rock960: Enable booting from eMMC when using SPL
  arm: dts: ficus: Enable booting from eMMC when using SPL

Matwey V. Kornilov (4):
  rockchip: rk3328: enable DMA for MMCs at Rock64
  rockchip: dts: rk3328: Add rk3328-evb-u-boot.dtsi
  configs: rk3328: enable TPL for rock64-rk3328_defconfig
  doc: rockchip: Adapt Pine64 Rock64 board instructions

Nick Xie (3):
  arm64: dts: rockchip: Add support for Khadas Edge
  arm64: dts: rockchip: Add support for Khadas Edge-V
  arm64: dts: rockchip: Add support for Khadas Edge-Captain

Urja Rannikko (1):
  dw_mmc: turn on the IO supply

 arch/arm/dts/Makefile  |3 +
 arch/arm/dts/rk3328-evb-u-boot.dtsi|   33 +
 arch/arm/dts/rk3328-rock64-u-boot.dtsi |4 +-
 arch/arm/dts/rk3328-sdram-ddr3-666.dtsi|  215 +
 arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi |  215 +
 arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi  |  215 +
 arch/arm/dts/rk3328.dtsi   |   11 +-
 arch/arm/dts/rk3399-ficus-u-boot.dtsi  |7 +
 .../arm/dts/rk3399-khadas-edge-captain-u-boot.dtsi |6 +
 arch/arm/dts/rk3399-khadas-edge-captain.dts|   27 +
 arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi|   13 +
 arch/arm/dts/rk3399-khadas-edge-v-u-boot.dtsi  |6 +
 arch/arm/dts/rk3399-khadas-edge-v.dts  |   27 +
 arch/arm/dts/rk3399-khadas-edge.dts|   13 +
 arch/arm/dts/rk3399-khadas-edge.dtsi   |  804 
 arch/arm/dts/rk3399-rock960-u-boot.dtsi|7 +
 arch/arm/include/asm/arch-rockchip/sdram_rk3328.h  |  441 +
 arch/arm/mach-rockchip/Kconfig |5 +
 arch/arm/mach-rockchip/rk3328/Kconfig  |   12 +
 arch/arm/mach-rockchip/rk3328/rk3328.c |5 +
 board/rockchip/evb_rk3399/MAINTAINERS  |   18 +
 configs/evb-rk3328_defconfig   |   37 +-
 configs/khadas-edge-captain-rk3399_defconfig   |   60 ++
 configs/khadas-edge-rk3399_defconfig   |   59 ++
 configs/khadas-edge-v-rk3399_defconfig |   60 ++
 configs/rock64-rk3328_defconfig|   14 +
 doc/README.rockchip|   10 +-
 drivers/mmc/dw_mmc.c   |   16 +
 drivers/ram/rockchip/sdram_rk3328.c| 1018 +++-
 29 files changed, 3343 insertions(+), 18 deletions(-)
 create mode 100644 arch/arm/dts/rk3328-evb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3328-sdram-ddr3-666.dtsi
 create mode 100644 arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi
 create mode 100644 arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi
 create mode 100644 arch/arm/dts/rk3399-khadas-edge-captain-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3399-khadas-edge-captain.dts
 create mode 100644 arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3399-khadas-edge-v-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3399-khadas-edge-v.dts
 create mode 100644 arch/arm/dts/rk3399-khadas-edge.dts
 create mode 100644 arch/arm/dts/rk3399-khadas-edge.dtsi
 create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
 create mode 100644 configs/khadas-edge-captain-rk3399_defconfig
 create mode 100644 configs/khadas-edge-rk3399_defconfig
 create mode 100644 configs/khadas-edge-v-rk3399_defconfig
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Re: [U-Boot] [PATCH v2 10/11] imx: spl: tpc70: Do not remove clock related properties from DTS

[Peng Fan]

> Subject: [PATCH v2 10/11] imx: spl: tpc70: Do not remove clock related
> properties from DTS
> 
> Those properties will be reused in the SPL to provide proper clock setting.
> 
> Signed-off-by: Lukasz Majewski 
> ---
> 
>  configs/kp_imx6q_tpc_defconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig
> index abf957f158..7b19323fb5 100644
> --- a/configs/kp_imx6q_tpc_defconfig
> +++ b/configs/kp_imx6q_tpc_defconfig
> @@ -44,7 +44,7 @@ CONFIG_CMD_EXT4_WRITE=y
> CONFIG_OF_CONTROL=y  CONFIG_SPL_OF_CONTROL=y
> CONFIG_DEFAULT_DEVICE_TREE="imx6q-kp"
> -CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent
> assigned-clocks assigned-clock-rates assigned-clock-parents interrupts clocks
> dmas dma-names"
> +CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks
> assigned-clock-rates assigned-clock-parents interrupts dmas dma-names"
>  CONFIG_ENV_IS_IN_MMC=y
>  # CONFIG_BLOCK_CACHE is not set
>  CONFIG_SPL_CLK_IMX6Q=y

Reviewed-by: Peng Fan 

> --
> 2.11.0

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Re: [U-Boot] [PATCH v2 07/11] imx: tpc70: dts: Add TPC70 board (imx6q based) device tree description

[Peng Fan]

> Subject: [PATCH v2 07/11] imx: tpc70: dts: Add TPC70 board (imx6q based)
> device tree description
> 
> This commit defines the TPC70 imx6q board with device tree description.

Is the imx6q-kp.dtsi usable for this board from Linux kernel?

Regards,
Peng.

> 
> Signed-off-by: Lukasz Majewski 
> ---
> 
>  arch/arm/dts/imx6q-kp.dts | 219
> ++
>  1 file changed, 219 insertions(+)
>  create mode 100644 arch/arm/dts/imx6q-kp.dts
> 
> diff --git a/arch/arm/dts/imx6q-kp.dts b/arch/arm/dts/imx6q-kp.dts new file
> mode 100644 index 00..12d6db6f80
> --- /dev/null
> +++ b/arch/arm/dts/imx6q-kp.dts
> @@ -0,0 +1,219 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018
> + * Lukasz Majewski, DENX Software Engineering, lu...@denx.de
> + *
> + * SPDX-License-Identifier: GPL-2.0+ or X11
> + */
> +
> +/dts-v1/;
> +#include 
> +#include "imx6q.dtsi"
> +
> +/ {
> + model = "K+P iMX6Q";
> + compatible = "kp,imx6-kp", "fsl,imx6";
> +
> + aliases {
> + mmc0 = 
> + mmc1 = 
> + usb1 = 
> + };
> +
> + chosen {
> + stdout-path = 
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <_leds>;
> +
> + green {
> + label = "green";
> + gpios = < 23 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "gpio";
> + default-state = "off";
> + };
> +
> + red {
> + label = "red";
> + gpios = < 16 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "gpio";
> + default-state = "off";
> + };
> + };
> +
> + memory@1000 {
> + reg = <0x1000 0x4000>;
> + };
> +
> + reg_usb_h1_vbus: regulator-usb_h1_vbus {
> + compatible = "regulator-fixed";
> + regulator-name = "usb_h1_vbus";
> + regulator-min-microvolt = <500>;
> + regulator-max-microvolt = <500>;
> + gpio = < 31 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +};
> +
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_enet>;
> + phy-reset-gpios = < 25 GPIO_ACTIVE_LOW>;
> + phy-reset-duration = <10>;
> + phy-mode = "rgmii";
> + fsl,magic-packet;
> + fsl,enet-loopback-clk; /* anatop reference clk via PAD loopback */
> + fsl,enet-freq = <1>; /* ENET_25MHZ  = 0, ENET_50MHZ  = 1 */
> +  /* ENET_100MHZ = 2, ENET_125MHZ = 3 */
> + status = "okay";
> +};
> +
> + {
> + clock-frequency = <40>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_i2c1>;
> + status = "okay";
> +};
> +
> + {
> + clock-frequency = <40>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_i2c2>;
> + status = "okay";
> +};
> +
> + {
> + pinctrl_enet: enetgrp {
> + fsl,pins = <
> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
> + MX6QDL_PAD_ENET_MDC__ENET_MDC   0x1b0b0
> + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
> + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
> + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
> + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
> + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
> + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
> + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK0x1b0b0
> + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
> + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
> + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
> + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
> + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
> + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
> + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
> + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25  0x1b0b0
> + >;
> + };
> +
> + pinctrl_leds: gpioledsgrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D23__GPIO3_IO23
> 0x4001b0b0
> + MX6QDL_PAD_EIM_D16__GPIO3_IO16
> 0x4001b0b0
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA  0x4001b8b1
> + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL  0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL3__I2C2_SCL   0x4001b8b1
> + MX6QDL_PAD_KEY_ROW3__I2C2_SDA   0x4001b8b1
> +  >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + 

Re: [U-Boot] [PATCH v2 06/11] imx: tpc70: led: Enable LED default state

[Peng Fan]

> Subject: [PATCH v2 06/11] imx: tpc70: led: Enable LED default state
> 
> This change sets the default state of LEDs on TPC70.
> 
> Signed-off-by: Lukasz Majewski 
> ---
> 
>  board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
> b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
> index 1dbd03efd8..97af6bd65b 100644
> --- a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
> +++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
> @@ -27,6 +27,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
> 
>  DECLARE_GLOBAL_DATA_PTR;
> 
> @@ -290,6 +291,9 @@ int board_late_init(void)
>   add_board_boot_modes(board_boot_modes);
>  #endif
> 
> + if (IS_ENABLED(CONFIG_LED))
> + led_default_state();
> +
>   env_set("boardname", "kp-tpc");
>   env_set("boardsoc", "imx6q");
>   return 0;

Reviewed-by: Peng Fan 

> --
> 2.11.0

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Re: [U-Boot] [PATCH v2 04/11] imx: tpc70: DTS: Explicitly add imx6q-kp.dtb to Makefile for DTB compilation

[Peng Fan]

> Subject: [PATCH v2 04/11] imx: tpc70: DTS: Explicitly add imx6q-kp.dtb to
> Makefile for DTB compilation
> 
> This commit is necessary to fix following error:
> 
> Device Tree Source is not correctly specified.
> Please define 'CONFIG_DEFAULT_DEVICE_TREE'
> or build with 'DEVICE_TREE=' argument
> 
> dts/Makefile:28: recipe for target 'arch/arm/dts/imx6q-kp.dtb' failed
> 
> Signed-off-by: Lukasz Majewski 
> ---
> 
>  arch/arm/dts/Makefile | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
> 49d1faef32..e7005663a8 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -564,6 +564,7 @@ dtb-$(CONFIG_MX6QDL) += \
>   imx6q-icore.dtb \
>   imx6q-icore-mipi.dtb \
>   imx6q-icore-rqs.dtb \
> + imx6q-kp.dtb \
>   imx6q-sabreauto.dtb \
>   imx6q-sabresd.dtb \
>   imx6q-wandboard-revb1.dtb \

Reviewed-by: Peng Fan 

> --
> 2.11.0

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Re: [U-Boot] [PATCH v2 05/11] imx: tpc70: cosmetic: Replace magic numbers when setting ENET clock

[Peng Fan]

> Subject: [PATCH v2 05/11] imx: tpc70: cosmetic: Replace magic numbers
> when setting ENET clock
> 
> This is a cosmetic change, just to use proper define instead of magic numbers.
> 
> Signed-off-by: Lukasz Majewski 
> ---
> 
>  board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
> b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
> index 7bdc64b1be..1dbd03efd8 100644
> --- a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
> +++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
> @@ -118,7 +118,8 @@ static int setup_fec_clock(void)
>   struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
> 
>   /* set gpr1[21] to select anatop clock */
> - clrsetbits_le32(_regs->gpr[1], 0x1 << 21, 0x1 << 21);
> + clrsetbits_le32(_regs->gpr[1],
> IOMUXC_GPR1_ENET_CLK_SEL_MASK,
> + IOMUXC_GPR1_ENET_CLK_SEL_MASK);

Would setbits_le32 work here?

Regards,
Peng.

> 
>   return enable_fec_anatop_clock(0, ENET_50MHZ);  }
> --
> 2.11.0

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Re: [U-Boot] [PATCH v2 02/11] imx: tpc70: config: Update TPC70 config to support eMMC's boot0 SPL update

[Peng Fan]

> Subject: [PATCH v2 02/11] imx: tpc70: config: Update TPC70 config to support
> eMMC's boot0 SPL update
> 
> The TPC70 can boot from eMMC's boot0. This patch allows it to update this
> HW partition's SPL.
> 
> Signed-off-by: Lukasz Majewski 
> ---
> 
>  include/configs/kp_imx6q_tpc.h | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h
> index 92f2bbb75b..2d1d1203b5 100644
> --- a/include/configs/kp_imx6q_tpc.h
> +++ b/include/configs/kp_imx6q_tpc.h
> @@ -43,6 +43,7 @@
>  #define CONFIG_SYS_FSL_ESDHC_ADDR0
>  #define CONFIG_SYS_FSL_USDHC_NUM 2
>  #define CONFIG_SYS_MMC_ENV_DEV   1 /* 0 = SDHC2, 1 = SDHC4
> (eMMC) */
> +#define CONFIG_SUPPORT_EMMC_BOOT
> 
>  /* UART */
>  #define CONFIG_MXC_UART
> @@ -103,6 +104,10 @@
>  "setexpr blkc ${blkc} + 1;" \
>  "mmc write ${loadaddr} 0x2 ${blkc};" \
>   "fi;\0" \
> + "upd_SPL_mmc=mmc dev 1; mmc partconf 1 0 1 1; run upd_SPL_sd\0" \
> + "upd_uboot_mmc=mmc dev 1; mmc partconf 1 0 1 1; run
> upd_uboot_sd\0" \
> + "up_mmc=run upd_SPL_mmc; run upd_uboot_mmc\0" \
> + "up_sd=run upd_SPL_sd; run upd_uboot_sd\0" \
>   "upd_wic=" \
>   "if tftp ${loadaddr} ${wic_file}; then " \
>  "setexpr blkc ${filesize} / 0x200;" \

Reviewed-by: Peng Fan 

> --
> 2.11.0

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Re: [U-Boot] [PATCH v2 03/11] imx: tpc70: Add board_boot_order() to distinguish between eMMC and SD boot

[Peng Fan]

> Subject: [PATCH v2 03/11] imx: tpc70: Add board_boot_order() to distinguish
> between eMMC and SD boot
> 
> The TPC70 can boot from SD card (debug/development) and eMMC
> (production).
> The board_boot_order() function provides a run time check for the device
> from which one wants to boot (it is selected by GPIO pins setup).
> 
> Moreover, a fallback to SD card is provided if the detection is not possible 
> or
> working properly.
> 
> Signed-off-by: Lukasz Majewski 
> ---
> 
>  board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c | 20
> 
>  1 file changed, 20 insertions(+)
> 
> diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
> b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
> index e284d5ec57..e48a577f79 100644
> --- a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
> +++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
> @@ -308,6 +308,26 @@ int board_mmc_init(bd_t *bd)
>   return fsl_esdhc_initialize(bd, _cfg[0]);  }
> 
> +void board_boot_order(u32 *spl_boot_list) {
> + u32 boot_device = spl_boot_device();
> + u32 reg = imx6_src_get_boot_mode();
> +
> + reg = (reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT;
> +
> + debug("%s: boot device: 0x%x (0x4 SD, 0x6 eMMC)\n", __func__, reg);
> + if (boot_device == BOOT_DEVICE_MMC1)
> + if (reg == IMX6_BMODE_MMC || reg == IMX6_BMODE_EMMC)
> + boot_device = BOOT_DEVICE_MMC2;
> +
> + spl_boot_list[0] = boot_device;
> + /*
> +  * Below boot device is a 'fallback' - it shall always be possible to
> +  * boot from SD card
> +  */
> + spl_boot_list[1] = BOOT_DEVICE_MMC1;
> +}
> +
>  void board_init_f(ulong dummy)
>  {
>   /* setup AIPS and disable watchdog */

Reviewed-by: Peng Fan 

> --
> 2.11.0

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Re: [U-Boot] [PATCH V2 4/4] clk: imx: add i.MX8MM clk driver

[Ye Li]

Hi Peng,

> Add i.MX8MM clk driver support.
> 
> Signed-off-by: Peng Fan 
> ---
>  drivers/clk/imx/Makefile |   2 +
>  drivers/clk/imx/clk-imx8mm.c | 414 
> +++
>  2 files changed, 416 insertions(+)
>  create mode 100644 drivers/clk/imx/clk-imx8mm.c
> 
> diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> index 105a58ca90..5ad7967fe9 100644
> --- a/drivers/clk/imx/Makefile
> +++ b/drivers/clk/imx/Makefile
> @@ -10,3 +10,5 @@ ifdef CONFIG_CLK_IMX8
>  obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o
>  obj-$(CONFIG_IMX8QM) += clk-imx8qm.o
>  endif
> +obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \
> + clk-composite-8m.o
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
> new file mode 100644
> index 00..9459d8ab8e
> --- /dev/null
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -0,0 +1,414 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2019 NXP
> + * Peng Fan 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "clk.h"
> +
> +#define PLL_1416X_RATE(_rate, _m, _p, _s)\
> + {   \
> + .rate   =   (_rate),\
> + .mdiv   =   (_m),   \
> + .pdiv   =   (_p),   \
> + .sdiv   =   (_s),   \
> + }
> +
> +#define PLL_1443X_RATE(_rate, _m, _p, _s, _k)\
> + {   \
> + .rate   =   (_rate),\
> + .mdiv   =   (_m),   \
> + .pdiv   =   (_p),   \
> + .sdiv   =   (_s),   \
> + .kdiv   =   (_k),   \
> + }
> +
> +static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
> + PLL_1416X_RATE(18U, 225, 3, 0),
> + PLL_1416X_RATE(16U, 200, 3, 0),
> + PLL_1416X_RATE(12U, 300, 3, 1),
> + PLL_1416X_RATE(10U, 250, 3, 1),
> + PLL_1416X_RATE(8U,  200, 3, 1),
> + PLL_1416X_RATE(75000U,  250, 2, 2),
> + PLL_1416X_RATE(7U,  350, 3, 2),
> + PLL_1416X_RATE(6U,  300, 3, 2),
> +};
> +
> +static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
> + PLL_1443X_RATE(65000U, 325, 3, 2, 0),
> +};
> +
> +static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
> + .type = PLL_1443X,
> + .rate_table = imx8mm_drampll_tbl,
> + .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
> +};
> +
> +static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
> + .type = PLL_1416X,
> + .rate_table = imx8mm_pll1416x_tbl,
> + .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
> +};
> +
> +static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
> + .type = PLL_1416X,
> + .rate_table = imx8mm_pll1416x_tbl,
> + .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
> +};
> +
> +static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", 
> "dummy", };
> +static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", 
> };
> +static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
> +static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", 
> };
> +static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", 
> };
> +static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", 
> };
> +
> +static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", 
> "sys_pll2_500m", "sys_pll2_1000m",
> + "sys_pll1_800m", "sys_pll1_400m", 
> "audio_pll1_out", "sys_pll3_out", };
> +
> +static const char *imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", 
> "sys_pll1_800m", "sys_pll1_400m",
> + "sys_pll2_125m", "sys_pll3_out", 
> "audio_pll1_out", "video_pll1_out", };
> +
> +static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", 
> "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
> +  "sys_pll2_200m", "audio_pll1_out", 
> "video_pll1_out", "sys_pll3_out", };
> +
> +static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", 
> "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
> +"sys_pll1_133m", "sys_pll3_out", 
> "sys_pll2_250m", "audio_pll1_out", };
> +
> +static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", 
> "sys_pll1_800m", "sys_pll2_500m",
> +"sys_pll3_out", "sys_pll1_266m", 
> "audio_pll2_out", "sys_pll1_100m", };
> +
> +static const char *imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", 
> "sys_pll1_800m", 

Re: [U-Boot] [PATCH V2 2/4] clk: imx: add pll14xx driver

[Ye Li]

Hi Peng,

> Add pll14xx driver
> 
> Signed-off-by: Peng Fan 
> ---
>  drivers/clk/imx/clk-pll14xx.c | 371 
> ++
>  drivers/clk/imx/clk.h |  25 +++
>  2 files changed, 396 insertions(+)
>  create mode 100644 drivers/clk/imx/clk-pll14xx.c
> 
> diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
> new file mode 100644
> index 00..8b47b0dea9
> --- /dev/null
> +++ b/drivers/clk/imx/clk-pll14xx.c
> @@ -0,0 +1,371 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2017-2019 NXP.
> + *
> + * Peng Fan 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "clk.h"
> +
> +#define UBOOT_DM_CLK_IMX_PLL1443X "imx_clk_pll1443x"
> +#define UBOOT_DM_CLK_IMX_PLL1416X "imx_clk_pll1416x"
> +
> +#define GNRL_CTL 0x0
> +#define DIV_CTL  0x4
> +#define LOCK_STATUS  BIT(31)
> +#define LOCK_SEL_MASKBIT(29)
> +#define CLKE_MASKBIT(11)
> +#define RST_MASK BIT(9)
> +#define BYPASS_MASK  BIT(4)
> +#define MDIV_SHIFT   12
> +#define MDIV_MASKGENMASK(21, 12)
> +#define PDIV_SHIFT   4
> +#define PDIV_MASKGENMASK(9, 4)
> +#define SDIV_SHIFT   0
> +#define SDIV_MASKGENMASK(2, 0)
> +#define KDIV_SHIFT   0
> +#define KDIV_MASKGENMASK(15, 0)
> +
> +#define LOCK_TIMEOUT_US  1
> +
> +struct clk_pll14xx {
> + struct clk  clk;
> + void __iomem*base;
> + enum imx_pll14xx_type   type;
> + const struct imx_pll14xx_rate_table *rate_table;
> + int rate_count;
> +};
> +
> +#define to_clk_pll14xx(_clk) container_of(_clk, struct clk_pll14xx, clk)
> +
> +static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
> + struct clk_pll14xx *pll, unsigned long rate)
> +{
> + const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
> + int i;
> +
> + for (i = 0; i < pll->rate_count; i++)
> + if (rate == rate_table[i].rate)
> + return _table[i];
> +
> + return NULL;
> +}
> +
> +static unsigned long clk_pll1416x_recalc_rate(struct clk *clk)
> +{
> + struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
> + u64 fvco = clk_get_parent_rate(clk);
> + u32 mdiv, pdiv, sdiv, pll_div;
> +
> + pll_div = readl(pll->base + 4);
> + mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
> + pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
> + sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
> +
> + fvco *= mdiv;
> + do_div(fvco, pdiv << sdiv);
> +
> + return fvco;
> +}
> +
> +static unsigned long clk_pll1443x_recalc_rate(struct clk *clk)
> +{
> + struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
> + u64 fvco = clk_get_parent_rate(clk);
> + u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1;
> + short int kdiv;
> +
> + pll_div_ctl0 = readl(pll->base + 4);
> + pll_div_ctl1 = readl(pll->base + 8);
> + mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
> + pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
> + sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
> + kdiv = pll_div_ctl1 & KDIV_MASK;
> +
> + /* fvco = (m * 65536 + k) * Fin / (p * 65536) */
> + fvco *= (mdiv * 65536 + kdiv);
> + pdiv *= 65536;
> +
> + do_div(fvco, pdiv << sdiv);
> +
> + return fvco;
> +}
> +
> +static inline bool clk_pll1416x_mp_change(const struct 
> imx_pll14xx_rate_table *rate,
> +   u32 pll_div)
> +{
> + u32 old_mdiv, old_pdiv;
> +
> + old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
> + old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
> +
> + return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
> +}
> +
> +static inline bool clk_pll1443x_mpk_change(const struct 
> imx_pll14xx_rate_table *rate,
> +u32 pll_div_ctl0, u32 pll_div_ctl1)
> +{
> + u32 old_mdiv, old_pdiv, old_kdiv;
> +
> + old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
> + old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
> + old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
> +
> + return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
> + rate->kdiv != old_kdiv;
> +}
> +
> +static inline bool clk_pll1443x_mp_change(const struct 
> imx_pll14xx_rate_table *rate,
> +   u32 pll_div_ctl0, u32 pll_div_ctl1)
> +{
> + u32 old_mdiv, old_pdiv, old_kdiv;
> +
> + old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
> + old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
> + old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
> +
> + return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
> + rate->kdiv != old_kdiv;
> +}
Not used. And it should not check kdiv.

> +
> +static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
> +{
> + u32 val;
> +

Re: [U-Boot] [PATCH v2 01/11] imx: tpc70: config: Add script commands to update u-boot and OE's wic

[Peng Fan]

> Subject: [PATCH v2 01/11] imx: tpc70: config: Add script commands to update
> u-boot and OE's wic
> 
> Signed-off-by: Lukasz Majewski 
> ---
> 
>  include/configs/kp_imx6q_tpc.h | 21 +
>  1 file changed, 21 insertions(+)
> 
> diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h
> index dbae276121..92f2bbb75b 100644
> --- a/include/configs/kp_imx6q_tpc.h
> +++ b/include/configs/kp_imx6q_tpc.h
> @@ -83,11 +83,32 @@
>   "rdinit=/sbin/init\0" \
>   "addinitrd=setenv bootargs ${bootargs} rdinit=${rdinit} ${debug} \0" \
>   "fit_config=mx6q_tpc70_conf\0" \
> + "uboot_file=u-boot.img\0" \
> + "SPL_file=SPL\0" \
> + "wic_file=kp-image-kpimx6qtpc.wic\0" \
>   "upd_image=st.4k\0" \
>   "updargs=setenv bootargs console=${console} ${smp}"\
>  "rdinit=${rdinit} ${debug} ${displayargs}\0" \
>   "loadusb=usb start; " \
>  "fatload usb 0 ${loadaddr} ${upd_image}\0" \
> + "upd_uboot_sd=" \
> + "if tftp ${loadaddr} ${uboot_file}; then " \
> +"setexpr blkc ${filesize} / 0x200;" \
> +"setexpr blkc ${blkc} + 1;" \
> +"mmc write ${loadaddr} 0x8A ${blkc};" \
> + "fi;\0" \
> + "upd_SPL_sd=" \
> + "if tftp ${loadaddr} ${SPL_file}; then " \
> +"setexpr blkc ${filesize} / 0x200;" \
> +"setexpr blkc ${blkc} + 1;" \
> +"mmc write ${loadaddr} 0x2 ${blkc};" \
> + "fi;\0" \
> + "upd_wic=" \
> + "if tftp ${loadaddr} ${wic_file}; then " \
> +"setexpr blkc ${filesize} / 0x200;" \
> +"setexpr blkc ${blkc} + 1;" \
> +"mmc write ${loadaddr} 0x0 ${blkc};" \
> + "fi;\0" \
>   "usbupd=echo Booting update from usb ...; " \
>  "setenv bootargs; " \
>  "run updargs; " \

Reviewed-by: Peng Fan 

> --
> 2.11.0

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[U-Boot] RFC: Migration target date for DM_ETH

[Heinrich Schuchardt]

Currently dozens of boards still do not use the driver model for the
network devices. This makes integration between devices in the UEFI
sub-system with the U-Boot devices complicated.

See: https://travis-ci.org/xypron2/u-boot/builds/569675547

In doc/driver-model/migration.rst I am missing a migration target day
for DM_ETH. Shouldn't define one? 2020-07 should be realistic.

Best regards

Heinrich
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Re: [U-Boot] GitLab: make pipeline status public

[Heinrich Schuchardt]

On 8/8/19 1:21 PM, Harald Seiler wrote:

Hi Heinrich,

On Wed, 2019-08-07 at 21:26 +0200, Heinrich Schuchardt wrote:

Hello Harald,

Tom suggested you could help on this issue.

I suggest that the pipeline status should be public on all custodian
gits, e.g. page
https://gitlab.denx.de/u-boot/custodians/u-boot-efi/pipelines.

I set the flag "Public pipelines" in the CI settings but this seems
not be sufficient. I still get a 404 error code if I am not logged on.


There is another setting you need to enable, IIRC: Under

Settings -> General -> Visibility, Permissions -> Pipelines

, you need to change the dropdown from "Only Project Members"
to "Everyone With Access".

Can you check whether that works?


The page is visible now without logging in. Thanks.

Best regards

Heinrich
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[U-Boot] 答复: 答复: 答复: [PATCH 0/4] Make some changes to SDP

[Sherry Sun]

Hi Angus,


Hi Sherry,

On Aug. 8, 2019 2:38 a.m., Sherry Sun 
mailto:sherry@nxp.com>> wrote:

Hi Angus,

Sorry for the late reply.

> -邮件原件-
> 发件人: Angus Ainslie mailto:an...@akkea.ca>>
> 发送时间: 2019年8月2日 10:30
> 收件人: Peng Fan mailto:peng@nxp.com>>
> 抄送: Sherry Sun mailto:sherry@nxp.com>>; 
> sba...@denx.de;
> feste...@gmail.com; 
> lu...@denx.de; ma...@denx.de;
> u-boot@lists.denx.de; dl-uboot-imx 
> mailto:uboot-...@nxp.com>>
> 主题: Re: 答复: [U-Boot] [PATCH 0/4] Make some changes to SDP
>
> Hi Peng,
>
> On 2019-08-01 18:01, Peng Fan wrote:
> > Angus,
> >
> >> Subject: Re: 答复: [U-Boot] [PATCH 0/4] Make some changes to SDP
> >>
> >> Hi Sherry,
> >>
> >> On 2019-07-31 19:56, Sherry Sun wrote:
> >> > Hi Angus
> >> >
> >> >>
> >> >> Hi Sherry,
> >> >>
> >> >> On 2019-07-17 18:40, sherry sun wrote:
> >> >> > From: Sherry Sun mailto:sherry@nxp.com>>
> >> >> >
> >> >> > This patchset adds:
> >> >> > 1. Add usb_gadget_initialize() and usb_gadget_release() to
> >> >> > initialize and release UDC during sdp download.
> >> >> > 2. Add high speed endpoint descriptor for sdp.
> >> >> > 3. Add a macro definition--CONFIG_SDP_LOADADDR as default sdp
> >> >> > load address while SDP_WRITE and SDP_JUMP command addr is zero.
> >> >> >
> >> >> > Sherry Sun (4):
> >> >> >   imx: spl: Change USB boot device type
> >> >> >   SDP: use CONFIG_SDP_LOADADDR as default load address
> >> >> >   SDP: fix wrong usb request size and add high speed endpoint
> >> >> > descriptor
> >> >> >   SDP: Call usb_gadget_initialize and usb_gadget_release to
> >> >> > support UDC
> >> >>
> >> >> These changes look like like they target SDP on imx8. For imx8mq
> >> >> is this all that is required to get SDP working with uuu or are
> >> >> there additional changes required ?
> >> >>
> >> >
> >> > The changes in patch 1/4 are target on both imx8 and imx8m.
> >> > The rest three patches are target on all boards which used SDP.
> >> > So for imx8mq, if your usb gadget driver is ready ,these changes
> >> > are enough to get SDP working with UUU.
> >> >
> >>
> >> I'm trying to use SDP on the imx8mq-evk but it doesn't look like it's
> >> enabled there. Do you have patches to enable SDP on the imx8mq-evk ,
> >> even if they aren't ready to go upstream ?
> >
> > You could try downstream code,
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsour
> >
> ce.codeaurora.org%2Fexternal%2Fimx%2Fuboot-imx%2Fdata=02%7C01
> %7Cs
> >
> herry.sun%40nxp.com%7C6d63289fbb104168bce308d716f157c4%7C686ea1
> d3bc2b4
> >
> c6fa92cd99c5c301635%7C0%7C0%7C637003098143081621sdata=beh
> 08%2Fv3f
> > s8ZZPP29F1iVMfo3uNTWGf91SYYyak2GVU%3Dreserved=0
> > branch: imx_v2019.04_4.19.35_1.0.0
> >
>
> I already have SDP  working with the vendor u-boot. I'm trying to switch to
> mainline u-boot so I'm looking for mainline patches.
>

May I ask, is your usb gadget driver is working? Such as you can use it for 
fastboot or ums.
>If I enable dwc3 gadget and DM for the SPL then I must start removing other 
>SPL features to get it to fit in the 124k allocation.
>
>It sounds like you haven't tested this on the imx8mq-evk then ?

Yes, I  have not used imx8mq-evk yet. I will try to test it later.

Best regards
Sherry sun

>Thanks
>Angus

Best regards
Sherry sun

> Thanks
> Angus
>
> > Regards,
> > Peng.
> >
> >>
> >> Thanks
> >> Angus
> >>
> >> > Best regards
> >> > Sherry sun
> >> >
> >> >> Thanks
> >> >> Angus
> >> >>
> >> >> >
> >> >> >  arch/arm/mach-imx/spl.c|  2 +-
> >> >> >  common/spl/spl_sdp.c   |  4 
> >> >> >  drivers/usb/gadget/Kconfig |  4 
> >> >> > drivers/usb/gadget/f_sdp.c |
> >> >> > 39
> >> >> > +-
> >> >> >  4 files changed, 43 insertions(+), 6 deletions(-)

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