[PATCH] rockchip: sdram: fix LPDDR5 bank info for sys_reg version 3

[Kever Yang]

From: YouMin Chen 

This patch add support for additional bank info used by LPDDR5.

Signed-off-by: YouMin Chen 
Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/sdram.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 99ecbdc3412..d65c48bf515 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -110,6 +110,13 @@ size_t rockchip_sdram_size(phys_addr_t reg)
  SYS_REG_COL_MASK);
cs1_col = cs0_col;
bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
+   /*
+* SYS_REG_BK(Version 3):
+* 1) Except LPDDR5 0:8bank(bk=3), 1:4bank(bk=2)
+* 2) LPDDR5 0:8bank(bk=3), 1:16bank(bk=4)
+*/
+   if (version == 3 && dram_type == LPDDR5 && bk == 2)
+   bk = 4;
if (version >= 2) {
cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
  SYS_REG_CS1_COL_MASK);
-- 
2.25.1

[PATCH] efi_loader: check efi_get_variable_int return value

[Masahisa Kojima]

efi_get_variable_int() may fail, the buffer should be
cleared before using it.

Signed-off-by: Masahisa Kojima 
Addresses-Coverity-ID: 478333 ("Error handling issues")
---
 lib/efi_loader/efi_firmware.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c
index 9fd13297a6..fb83fa8113 100644
--- a/lib/efi_loader/efi_firmware.c
+++ b/lib/efi_loader/efi_firmware.c
@@ -407,11 +407,11 @@ efi_status_t efi_firmware_set_fmp_state_var(struct 
fmp_state *state, u8 image_in
/*
 * GetVariable may fail, EFI_NOT_FOUND is returned if FmpState
 * variable has not been set yet.
-* Ignore the error here since the correct FmpState variable
-* is set later.
 */
-   efi_get_variable_int(varname, image_type_id, NULL, , var_state,
-NULL);
+   ret = efi_get_variable_int(varname, image_type_id, NULL, ,
+  var_state, NULL);
+   if (ret != EFI_SUCCESS)
+   memset(var_state, 0, num_banks * sizeof(*var_state));
 
/*
 * Only the fw_version is set here.
-- 
2.34.1

Re: New Defects reported by Coverity Scan for Das U-Boot

[Masahisa Kojima]

Hi Heinrich,

On Fri, 19 Jan 2024 at 17:47, Heinrich Schuchardt  wrote:
>
>
>
> 
> *** CID 478333:  Error handling issues  (CHECKED_RETURN)
> /lib/efi_loader/efi_firmware.c: 413 in efi_firmware_set_fmp_state_var()
> 407 /*
> 408  * GetVariable may fail, EFI_NOT_FOUND is returned if FmpState
> 409  * variable has not been set yet.
> 410  * Ignore the error here since the correct FmpState variable
> 411  * is set later.
> 412  */
> >>> CID 478333:  Error handling issues  (CHECKED_RETURN)
> >>> Calling "efi_get_variable_int" without checking return value (as is 
> >>> done elsewhere 29 out of 33 times).
> 413 efi_get_variable_int(varname, image_type_id, NULL, ,
> var_state,
> 414  NULL);
> 415 416 /*
> 417  * Only the fw_version is set here.
> 418  * lowest_supported_version in FmpState variable is ignored 
> since
>
> There are a lot of different return values that may occur when calling
> efi_get_variable_int, e.g.
>
> * EFI_BUFFER_TOO_SMALL
> * EFI_DEVICE_ERROR
>
> Should we overwrite the variable in these cases with NUL values except
> for var_state[update_bank].fw_version?

The var_state buffer is allocated by calloc(), and efi_get_variable_int()
will not update the buffer in case of error.
But it is better to set NUL values to var_state, I will send a fix.

Thanks,
Masahisa Kojima

>
> Best regards
>
> Heinrich

Re: [PATCH 01/10] board: ti: am62x: Init DRAM size in R5/A53 SPL

[Siddharth Vadapalli]

On 20/01/24 22:11, Tom Rini wrote:
> On Mon, Jan 15, 2024 at 01:42:51PM +0530, Siddharth Vadapalli wrote:
>> Hello Tom,
>>
>> On 12/01/24 18:56, Tom Rini wrote:

...

>>> The list of conditionals in common/spl/spl.c::board_init_r() should be
>>> updated and probably use SPL_NET as the option to check for.
>>
>> Thank you for reviewing the patch and pointing this out. I wasn't aware of 
>> it. I
>> assume that you are referring to the following change:
>>
>> if (IS_ENABLED(CONFIG_SPL_OS_BOOT) || CONFIG_IS_ENABLED(HANDOFF) ||
>> -   IS_ENABLED(CONFIG_SPL_ATF))
>> +   IS_ENABLED(CONFIG_SPL_ATF) || IS_ENABLED(CONFIG_SPL_NET))
>> dram_init_banksize();
>>
>> I shall replace the current patch with the above change in the v2 series. 
>> Since
>> this is in the common section, is there a generic reason I could provide in 
>> the
>> commit message rather than the existing commit message which seems to be 
>> board
>> specific? Also, I hope that the above change will not cause regressions for
>> other non-TI devices. Please let me know.
> 
> Yes, that's the area, and just note that networking also requires the
> DDR to be initialized.
> 

Thank you for confirming and providing your suggestion for the contents of the
commit message.

-- 
Regards,
Siddharth.

[PATCH 03/60] net: mediatek: add support for XGMII interface

[Weijie Gao]

This patch add XGMII support for connecting 2.5G PHY.

Signed-off-by: Bo-Cun Chen 
Signed-off-by: Weijie Gao 
---
 drivers/net/mtk_eth.c | 22 ++
 drivers/net/mtk_eth.h |  2 +-
 2 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c
index 726aedad3f..75e7bcf83b 100644
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -1246,7 +1246,8 @@ static int mtk_phy_start(struct mtk_eth_priv *priv)
}
 
if (!priv->force_mode) {
-   if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII)
+   if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
+   priv->phy_interface == PHY_INTERFACE_MODE_XGMII)
mtk_xphy_link_adjust(priv);
else
mtk_phy_link_adjust(priv);
@@ -1516,7 +1517,7 @@ static void mtk_mac_init(struct mtk_eth_priv *priv)
 
 static void mtk_xmac_init(struct mtk_eth_priv *priv)
 {
-   u32 sts;
+   u32 force_link = 0;
 
switch (priv->phy_interface) {
case PHY_INTERFACE_MODE_USXGMII:
@@ -1531,15 +1532,19 @@ static void mtk_xmac_init(struct mtk_eth_priv *priv)
   SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id),
   0);
 
-   if (priv->gmac_id == 1) {
+   if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII &&
+   priv->gmac_id == 1) {
mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX,
  NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL);
-   } else if (priv->gmac_id == 2) {
-   sts = mtk_gmac_read(priv, XGMAC_STS(priv->gmac_id));
-   sts |= XGMAC_FORCE_LINK;
-   mtk_gmac_write(priv, XGMAC_STS(priv->gmac_id), sts);
}
 
+   if (priv->phy_interface == PHY_INTERFACE_MODE_XGMII ||
+   priv->gmac_id == 2)
+   force_link = XGMAC_FORCE_LINK(priv->gmac_id);
+
+   mtk_gmac_rmw(priv, XGMAC_STS(priv->gmac_id),
+XGMAC_FORCE_LINK(priv->gmac_id), force_link);
+
/* Force GMAC link down */
mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE);
 }
@@ -1828,7 +1833,8 @@ static int mtk_eth_probe(struct udevice *dev)
mtk_eth_mdc_init(priv);
 
/* Set MAC mode */
-   if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII)
+   if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
+   priv->phy_interface == PHY_INTERFACE_MODE_XGMII)
mtk_xmac_init(priv);
else
mtk_mac_init(priv);
diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h
index 45229c0f9a..fd31c782c7 100644
--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
@@ -268,7 +268,7 @@ enum mkt_eth_capabilities {
 
 /* XGMAC Status Registers */
 #define XGMAC_STS(x)   (((x) == 2) ? 0x001C : 0x000C)
-#define XGMAC_FORCE_LINK   BIT(15)
+#define XGMAC_FORCE_LINK(x)(((x) == 1) ? BIT(31) : BIT(15))
 
 /* XGMAC Registers */
 #define XGMAC_PORT_MCR(x)  (0x2000 + (((x) - 1) * 0x1000))
-- 
2.34.1

[PATCH 02/60] net: mediatek: add support for adjusting MDIO clock

[Weijie Gao]

User can assign a specific MDC speed to the eth node as follow:

 {
...
phy-mode = "usxgmii";
phy-handle = <>;

mdio {
clock-frequency = <1050>;
};

phy8: eth-phy@8 {
  compatible = "ethernet-phy-id31c3.1c12";
...
};

Signed-off-by: Bo-Cun Chen 
Signed-off-by: Weijie Gao 
---
 drivers/net/mtk_eth.c | 35 +++
 drivers/net/mtk_eth.h |  7 +++
 2 files changed, 42 insertions(+)

diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c
index 3cfce05845..726aedad3f 100644
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -137,6 +137,7 @@ struct mtk_eth_priv {
int force_mode;
int speed;
int duplex;
+   int mdc;
bool pn_swap;
 
struct phy_device *phydev;
@@ -1607,6 +1608,26 @@ static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
mtk_pdma_write(priv, PDMA_RST_IDX_REG, RST_DTX_IDX0 | RST_DRX_IDX0);
 }
 
+static void mtk_eth_mdc_init(struct mtk_eth_priv *priv)
+{
+   u32 divider;
+
+   if (priv->mdc == 0)
+   return;
+
+   divider = min_t(u32, DIV_ROUND_UP(MDC_MAX_FREQ, priv->mdc), 
MDC_MAX_DIVIDER);
+
+   /* Configure MDC turbo mode */
+   if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
+   mtk_gmac_rmw(priv, GMAC_MAC_MISC_REG, 0, MISC_MDC_TURBO);
+   else
+   mtk_gmac_rmw(priv, GMAC_PPSC_REG, 0, MISC_MDC_TURBO);
+
+   /* Configure MDC divider */
+   mtk_gmac_rmw(priv, GMAC_PPSC_REG, PHY_MDC_CFG,
+FIELD_PREP(PHY_MDC_CFG, divider));
+}
+
 static int mtk_eth_start(struct udevice *dev)
 {
struct mtk_eth_priv *priv = dev_get_priv(dev);
@@ -1803,6 +1824,9 @@ static int mtk_eth_probe(struct udevice *dev)
noncached_alloc(priv->soc->rxd_size * NUM_RX_DESC,
ARCH_DMA_MINALIGN);
 
+   /* Set MDC divider */
+   mtk_eth_mdc_init(priv);
+
/* Set MAC mode */
if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII)
mtk_xmac_init(priv);
@@ -1881,6 +1905,17 @@ static int mtk_eth_of_to_plat(struct udevice *dev)
 
priv->gmac_id = dev_read_u32_default(dev, "mediatek,gmac-id", 0);
 
+   priv->mdc = 0;
+   subnode = ofnode_find_subnode(dev_ofnode(dev), "mdio");
+   if (ofnode_valid(subnode)) {
+   priv->mdc = ofnode_read_u32_default(subnode, "clock-frequency", 
250);
+   if (priv->mdc > MDC_MAX_FREQ ||
+   priv->mdc < MDC_MAX_FREQ / MDC_MAX_DIVIDER) {
+   printf("error: MDIO clock frequency out of range\n");
+   return -EINVAL;
+   }
+   }
+
/* Interface mode is required */
pdata->phy_interface = dev_read_phy_mode(dev);
priv->phy_interface = pdata->phy_interface;
diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h
index 491cac56a8..45229c0f9a 100644
--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
@@ -180,6 +180,12 @@ enum mkt_eth_capabilities {
 
 /* GMAC Registers */
 
+#define GMAC_PPSC_REG  0x
+#define PHY_MDC_CFGGENMASK(29, 24)
+#define MDC_TURBO  BIT(20)
+#define MDC_MAX_FREQ   2500
+#define MDC_MAX_DIVIDER63
+
 #define GMAC_PIAC_REG  0x0004
 #define PHY_ACS_ST BIT(31)
 #define MDIO_REG_ADDR_S25
@@ -197,6 +203,7 @@ enum mkt_eth_capabilities {
 #define P1_XGMAC_FORCE_LINKBIT(15)
 
 #define GMAC_MAC_MISC_REG  0x0010
+#define MISC_MDC_TURBO BIT(4)
 
 #define GMAC_GSW_CFG_REG   0x0080
 #define GSWTX_IPG_M0xF
-- 
2.34.1

[PATCH 01/60] arm: dts: mt7988-sd-rfb: add SD pin driving settings

[Weijie Gao]

Set SD pin driving to 4mA

Signed-off-by: Dong Huang 
Signed-off-by: Weijie Gao 
---
 arch/arm/dts/mt7988-sd-rfb.dts | 2 ++
 arch/arm/dts/mt7988.dtsi   | 1 +
 2 files changed, 3 insertions(+)

diff --git a/arch/arm/dts/mt7988-sd-rfb.dts b/arch/arm/dts/mt7988-sd-rfb.dts
index a3df37d252..9aa198b84a 100644
--- a/arch/arm/dts/mt7988-sd-rfb.dts
+++ b/arch/arm/dts/mt7988-sd-rfb.dts
@@ -87,10 +87,12 @@
pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI",
   "SPI2_CLK", "SPI2_HOLD";
input-enable;
+   drive-strength = ;
};
 
conf-clk {
pins = "SPI2_WP";
+   drive-strength = ;
};
};
 };
diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi
index ac476d5cdd..5c0c5bcfd6 100644
--- a/arch/arm/dts/mt7988.dtsi
+++ b/arch/arm/dts/mt7988.dtsi
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 / {
-- 
2.34.1

Re: [PATCH 09/11] ARM: dts: renesas: Add Renesas R8A779H0 V4M DT extras

[Marek Vasut]

On 1/21/24 21:52, Paul Barker wrote:

On 21/01/2024 17:41, Marek Vasut wrote:

From: Hai Pham 

Add Renesas R8A779H0 V4M DT extras for U-Boot.

Signed-off-by: Hai Pham 
---
Cc: Paul Barker 
---
  arch/arm/dts/r8a779h0-u-boot.dtsi | 27 +++
  1 file changed, 27 insertions(+)
  create mode 100644 arch/arm/dts/r8a779h0-u-boot.dtsi

diff --git a/arch/arm/dts/r8a779h0-u-boot.dtsi 
b/arch/arm/dts/r8a779h0-u-boot.dtsi
new file mode 100644
index 000..b2f7e054eef
--- /dev/null
+++ b/arch/arm/dts/r8a779h0-u-boot.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on R-Car R8A779H0 SoC
+ *
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ */
+
+#include "r8a779x-u-boot.dtsi"
+/ {
+   soc {
+   rpc: spi@ee20 {
+   compatible = "renesas,r8a779h0-rpc-if", 
"renesas,rcar-gen4-rpc-if";
+   reg = <0 0xee20 0 0x200>, <0 0x0800 0 
0x0400>;
+   interrupts = ;
+   clocks = < CPG_MOD 629>;
+   power-domains = < R8A779H0_PD_ALWAYS_ON>;
+   resets = < 629>;
+   bank-width = <2>;
+   num-cs = <1>;
+   status = "disabled";
+   };


Either the commit message or a comment should give some idea why this
node is in a -u-boot.dtsi file instead of the r8a779h0.dtsi file itself.


I suspect this won't be in the initial Linux DT, so its kept as an 
extension here, so the GH board can use RPC to access SPI NOR . I 
suspect this will go away once the RPC node lands in Linux DT. I will 
add comment like that in V2 commit message.

Re: [PATCH 01/11] dt-bindings: power: Add R8A779H0 V4M SYSC power domain definitions

[Marek Vasut]

On 1/21/24 22:21, Paul Barker wrote:

On 21/01/2024 17:41, Marek Vasut wrote:

From: Duy Nguyen 

Add power domain indices for R-Car V4M (R8A779H0).

Signed-off-by: Duy Nguyen 
Signed-off-by: Hai Pham 
---
Cc: Paul Barker 
---
  include/dt-bindings/power/r8a779h0-sysc.h | 49 +++
  1 file changed, 49 insertions(+)
  create mode 100644 include/dt-bindings/power/r8a779h0-sysc.h


We should reference the corresponding Linux kernel patch via
lore.kernel.org if this isn't in the mainline kernel yet.

Also, as a general series comment: I'd prefer to see a cover letter to
say which interfaces and key features are supported on the V4M by this
series. Is this enough to boot Linux from at least one interface (SDHI,
Ethernet, etc)?


Yes, SDHI and Ethernet should both work.

Re: [PATCH 02/11] dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions

[Marek Vasut]

On 1/21/24 22:14, Paul Barker wrote:

On 21/01/2024 17:41, Marek Vasut wrote:

From: Duy Nguyen 

Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
V4M (R8A779H0) SoC.

Signed-off-by: Duy Nguyen 
Signed-off-by: Hai Pham 
---
Cc: Paul Barker 
---
  include/dt-bindings/clock/r8a779h0-cpg-mssr.h | 100 ++
  1 file changed, 100 insertions(+)
  create mode 100644 include/dt-bindings/clock/r8a779h0-cpg-mssr.h


We should reference the corresponding Linux kernel patch via
lore.kernel.org if this isn't in the mainline kernel yet.


There is no corresponding Linux patch.

Re: [PATCH 03/11] clk: renesas: Add R8A779H0 V4M clock tables

[Marek Vasut]

On 1/21/24 22:08, Paul Barker wrote:

On 21/01/2024 17:41, Marek Vasut wrote:

From: Hai Pham 

Add clock tables for R8A779H0 V4M SoC.

Signed-off-by: Hai Pham 
---
Cc: Lukasz Majewski 
Cc: Paul Barker 
Cc: Sean Anderson 
---
  drivers/clk/renesas/Kconfig |   6 +
  drivers/clk/renesas/Makefile|   1 +
  drivers/clk/renesas/r8a779h0-cpg-mssr.c | 294 
  drivers/clk/renesas/rcar-gen3-cpg.h |   1 +
  4 files changed, 302 insertions(+)
  create mode 100644 drivers/clk/renesas/r8a779h0-cpg-mssr.c


How does this relate to the Linux kernel clk patch sent by Geert [1]? If
this patch is based on that, then we should have a link to that patch in
the commit message (since it hasn't appeared in a mainline kernel
release yet).


This is still pulled from renesas U-Boot port, once clock/pinmux/DTs 
appears in next, I will sync them from next into U-Boot.

Re: [PATCH 10/11] ARM: dts: renesas: Add Renesas Gray Hawk boards support

[Marek Vasut]

On 1/21/24 21:46, Paul Barker wrote:

On 21/01/2024 17:41, Marek Vasut wrote:

From: Hai Pham 

Initial support for the Renesas Gray Hawk CPU and BreakOut boards.

Signed-off-by: Hai Pham 
---
Cc: Paul Barker 
---
  arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi  | 165 ++
  arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi  |  15 ++
  arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi |  15 ++
  arch/arm/dts/r8a779h0-gray-hawk.dts   |  25 +++
  4 files changed, 220 insertions(+)
  create mode 100644 arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi
  create mode 100644 arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi
  create mode 100644 arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi
  create mode 100644 arch/arm/dts/r8a779h0-gray-hawk.dts


Is this a sync from the Linux kernel? If so we should say which commit
the dts/dtsi files are taken from.


It is not, not yet anyway. Once the DTs land in next, I will sync them in.

Re: [PATCH 3/3] net: ravb: Use PHY MDIO address from DT if available

[Marek Vasut]

On 1/21/24 22:37, Paul Barker wrote:

On 21/01/2024 17:29, Marek Vasut wrote:

In case the PHY is fully described in DT, use PHY MDIO address
from DT directly instead of always using auto-detection. This
also fixes the behavior of 'mdio list' in such DT setup, which
now prints the PHY connected to the MAC correctly.

Signed-off-by: Marek Vasut 
---
Cc: Joe Hershberger 
Cc: Paul Barker 
Cc: Ramon Fried 
---
  drivers/net/sh_eth.c | 10 --
  1 file changed, 8 insertions(+), 2 deletions(-)


I think the commit summaries are mixed up here - this patch says 'ravb'
but changes 'sh_eth.c' and vice-versa with the other patch.


Sigh ... too much git commit --fixup/rebase --autosquash .


diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 7b1f59dc498..5e2e3054ecf 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -12,6 +12,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -597,11 +598,16 @@ static int sh_eth_phy_config(struct udevice *dev)
struct sh_ether_priv *priv = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_plat(dev);
struct sh_eth_dev *eth = >shdev;
-   int ret = 0;
struct sh_eth_info *port_info = >port_info[eth->port];
struct phy_device *phydev;
+   int phy_addr;
+   int ret = 0;
+
+   phy_addr = eth_phy_get_addr(dev);
+   if (phy_addr < 0)
+   phy_addr = -1;
  
-	phydev = phy_connect(priv->bus, -1, dev, pdata->phy_interface);

+   phydev = phy_connect(priv->bus, phy_addr, dev, pdata->phy_interface);
if (!phydev)
return -ENODEV;
  


I have a local patch to handle (phy_addr < 0) in phy_connect_phy_id()
and lookup the address there. I think that's the better place to handle
this as it's a universal fix for all users of CONFIG_PHY_ETHERNET_ID.
Unfortunately I've been distracted by some higher priority work but I'm
hoping to get back to this soon.

I can do some quick testing with that patch and send it this week if
that's helpful.


Please do send it, yes.

Re: [PATCH] usb: dwc3-of-simple: Remove Amlogic and Rockchip compatible

[Marek Vasut]

On 1/21/24 21:38, Jonas Karlman wrote:

Remove the rockchip,rk3399-dwc3 compatible from the dwc3-of-simple
driver now that all boards have changed to use the dwc3-generic driver.

Also remove the amlogic,meson-gxl-dwc3 compatible, it is no longer in
use by any device tree in mainline linux or U-Boot.

Signed-off-by: Jonas Karlman 


Reviewed-by: Marek Vasut 

Re: [PATCH v4 00/11] An effort to bring DT bindings compliance within U-Boot

[Marek Vasut]

On 1/21/24 23:41, Caleb Connolly wrote:

Hi,

[...]

How do you propose to handle fixes to DTs which are applied to 
linux-stable releases ? For example, if Linux 6.6(.0) ships a DT which 
has some defect that is fixed in 6.6.1, how will that fix get into 
U-Boot DTs ?


This fix would also be in the latest Linux tags, so I think it would 
find its way here - as I understand it patches aren't accepted into 
Linux stable unless they land in torvalds tree.


See the devicetree-rebasing.git:

https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/refs/

That only contains refs for release versions (v6.6-dts, v6.7-dts etc), 
not any follow-up updates from linux-stable (like current 6.6.13 etc).


Would this require syncing in -rc versions of Linux DTs to get the 
latest fixes in ?


Assume that there is some large breaking change in Linux 6.(n+1), 
something which would be problematic for specific U-Boot platform 
(e.g. i.MX) or would require a lot of work to sort out, will there be 
a way to temporarily pin DTs for specific platform to older DT version 
until that is resolved (e.g. pin to 6.n) ?


(Upstream) devicetree has to be forwards and backwards compatible, were 
such a breaking change to get merged without prior discussion with DT 
users (i.e. U-Boot) then I think the correct course of action would be 
to revert it.


Not really, this could be a perfectly valid change, and would work for 
Linux just fine, it might simply be pulling in something which is not 
supported by U-Boot just yet and therefore syncing the DTs into U-Boot 
would break U-Boot on that platform . Using older version of DTs for a 
platform could work as a stopgap measure until the functionality is 
implemented. Is this possible ?


On a tangential note: as I understand it, DTs built from dt-rebasing are 
still subject to U-Boot customisations via the "-u-boot.dtsi" include 
files, this allows for dealing with incompatibilities due to missing 
features in U-Boot.


Would it be possible to auto-update those -u-boot.dtsi files during 
sync, to minimize the resulting DT blob delta before/after update, and 
thus also minimize the likelihood of causing breakage ?

Re: [PATCH v4 00/11] An effort to bring DT bindings compliance within U-Boot

[Tom Rini]

On Sun, Jan 21, 2024 at 10:41:51PM +, Caleb Connolly wrote:
> 
> 
> On 21/01/2024 15:33, Marek Vasut wrote:
[snip]
> > Assume that there is some large breaking change in Linux 6.(n+1),
> > something which would be problematic for specific U-Boot platform (e.g.
> > i.MX) or would require a lot of work to sort out, will there be a way to
> > temporarily pin DTs for specific platform to older DT version until that
> > is resolved (e.g. pin to 6.n) ?
> 
> (Upstream) devicetree has to be forwards and backwards compatible, were such
> a breaking change to get merged without prior discussion with DT users (i.e.
> U-Boot) then I think the correct course of action would be to revert it.

The caveat is "unless it was wrong before", which happens more often
than is generally thought of I think. I'm not sure off-hand the best way
to deal with that.

-- 
Tom


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Description: PGP signature

Re: [PATCH 03/11] clk: renesas: Add R8A779H0 V4M clock tables

[Mohammed Emad]

wdomd...@gmail.com

 ??? Outlook for Android

From: U-Boot  on behalf of Marek Vasut 

Sent: Sunday, January 21, 2024 11:11:06 PM
To: u-boot@lists.denx.de 
Cc: Hai Pham ; Lukasz Majewski ; Paul 
Barker ; Sean Anderson 
Subject: [PATCH 03/11] clk: renesas: Add R8A779H0 V4M clock tables

From: Hai Pham 

Add clock tables for R8A779H0 V4M SoC.

Signed-off-by: Hai Pham 
---
Cc: Lukasz Majewski 
Cc: Paul Barker 
Cc: Sean Anderson 
---
 drivers/clk/renesas/Kconfig |   6 +
 drivers/clk/renesas/Makefile|   1 +
 drivers/clk/renesas/r8a779h0-cpg-mssr.c | 294 
 drivers/clk/renesas/rcar-gen3-cpg.h |   1 +
 4 files changed, 302 insertions(+)
 create mode 100644 drivers/clk/renesas/r8a779h0-cpg-mssr.c

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 927d62cf99a..e9296ed9fe2 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -151,6 +151,12 @@ config CLK_R8A779G0
 help
   Enable this to support the clocks on Renesas R8A779G0 SoC.

+config CLK_R8A779H0
+   bool "Renesas R8A779H0 clock driver"
+   depends on CLK_RCAR_GEN3
+   help
+ Enable this to support the clocks on Renesas R8A779H0 SoC.
+
 config CLK_R9A06G032
 bool "Renesas R9A06G032 clock driver"
 depends on CLK_RENESAS
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index df7e225e9ca..6c742553091 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A779H0) += r8a779h0-cpg-mssr.o
 obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
 obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o
 obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c 
b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
new file mode 100644
index 000..1399bfc8483
--- /dev/null
+++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
@@ -0,0 +1,294 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a779h0 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ *
+ * Based on r8a779g0-cpg-mssr.c
+ */
+
+#include 
+#include 
+
+#include 
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+   /* Core Clock Outputs exported to DT */
+   LAST_DT_CORE_CLK = R8A779H0_CLK_R,
+
+   /* External Input Clocks */
+   CLK_EXTAL,
+   CLK_EXTALR,
+
+   /* Internal Core Clocks */
+   CLK_MAIN,
+   CLK_PLL1,
+   CLK_PLL2,
+   CLK_PLL3,
+   CLK_PLL4,
+   CLK_PLL5,
+   CLK_PLL6,
+   CLK_PLL7,
+   CLK_PLL1_DIV2,
+   CLK_PLL2_DIV2,
+   CLK_PLL3_DIV2,
+   CLK_PLL4_DIV2,
+   CLK_PLL4_DIV5,
+   CLK_PLL5_DIV2,
+   CLK_PLL5_DIV4,
+   CLK_PLL6_DIV2,
+   CLK_PLL7_DIV2,
+   CLK_S0,
+   CLK_S0_VIO,
+   CLK_S0_VC,
+   CLK_S0_HSC,
+   CLK_SASYNCPER,
+   CLK_SV_VIP,
+   CLK_SV_IR,
+   CLK_IMPASRC,
+   CLK_IMPBSRC,
+   CLK_VIOSCR,
+   CLK_VCSCR,
+   CLK_SDSRC,
+   CLK_RPCSRC,
+   CLK_OCO,
+
+   /* Module Clocks */
+   MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a779h0_core_clks[] = {
+   /* External Clock Inputs */
+   DEF_INPUT("extal",  CLK_EXTAL),
+   DEF_INPUT("extalr", CLK_EXTALR),
+
+   /* Internal Core Clocks */
+   DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
+   DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
+   DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN),
+   DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
+   DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN),
+   DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
+   DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
+   DEF_BASE(".pll7", CLK_PLL7, CLK_TYPE_GEN4_PLL7, CLK_MAIN),
+
+   DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,  CLK_PLL1,   2, 1),
+   DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2,  CLK_PLL2,   2, 1),
+   DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2,  CLK_PLL3,   2, 1),
+   DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2,  CLK_PLL4,   2, 1),
+   DEF_FIXED(".pll4_div5", CLK_PLL4_DIV5,  CLK_PLL4,   5, 1),
+   DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2,  CLK_PLL5,   2, 1),
+   DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4,  CLK_PLL5_DIV2,  2, 1),
+   DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2,  CLK_PLL6,   2, 1),
+   DEF_FIXED(".pll7_div2", CLK_PLL7_DIV2,  CLK_PLL7,   2, 1),
+   DEF_FIXED(".s0",CLK_S0, CLK_PLL1_DIV2,  2, 1),
+   DEF_FIXED(".s0_vio",

Re: [PATCH v4 00/11] An effort to bring DT bindings compliance within U-Boot

[Caleb Connolly]

On 21/01/2024 15:33, Marek Vasut wrote:

On 1/10/24 11:35, Sumit Garg wrote:

Changes in v4:
--
- Switched subtree to be imported as dts/upstream sub-directory rather
   than devicetree-rebasing sub-directory to better suite U-Boot
   directory structure.
- Since we now have v6.7-dts tag available now, so switch subtree to
   that from its beginning.
- Patch #2: Incorporate build fix to adjust Bindings Makefile rules to
   old U-Boot Kbuild infrastructure.
- Patch #3: Incorporate fix to resolve rk3399 migration issue reported
   by Simon.
- Patch #4: New patch to reuse upstream DT includes by U-Boot as per
   Brian's use-case for TI K3 SoCs.
- Patch #5: Added a note to OF_UPSTREAM Kconfig option.
- Patch #6: New patch to add script dts/update-dts-subtree.sh as per
   Rob's comments.
- Patch #7: Separate patch to align documentation to use Kconfig symbols
   instead.
- Patch #8: Clarify subtree uprev schedule as a separate documentation
   section. Also, fixed documentation typos.
- Patch #9: Added commit description.

Changes in v3:
--
- Patch #4: Minor commit message update
- Patch #5: Replace CONFIG_* with Kconfig options
- Patch #7: Dropped Makefile portion and enabled OF_UPSTREAM for SoC
   instead.
- Patch #1, #3, #6 and #8: Picked up review tags

Changes in v2:
--
- Patch #1: excluded gitab CI config check and added commit description.
- Patch #3: s/UBOOT_DTSI_LOC/u_boot_dtsi_loc/
- Patch #4: s/DEVICE_TREE_LOC/dt_dir/ and s/U-boot/U-Boot/
- Patch #5: s/U-boot/U-Boot/
- Patch #6 and #7: Picked up review tags

Prerequisite


This patch series requires devicetree-rebasing git repo to be added as a
subtree to the main U-Boot repo via:

$ git subtree add --prefix dts/upstream \
   
git://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git \

   v6.7-dts --squash

Background
--

This effort started while I was reviewing patch series corresponding to
Qcom platforms [1] which was about to import modified devicetree source
files from Linux kernel. I suppose keeping devicetree files sync with
Linux kernel without any DT bindings schema validation has been a pain
for U-Boot SoC/platform maintainers. There has been past discussions
about a single DT repo but that hasn't come up and Linux kernel remained
the place where DT source files as well as bindings are placed and
maintained.

However, Linux kernel DT maintainers proposed [2] for U-Boot to rather
use devicetree-rebasing repo [3] which is a forked copy from Linux
kernel for DT source files as well as bindings. It is tagged at every
Linux kernel major release or intermideate release candidates. So here I
have tried to reuse that to bring DT bingings compliance as well as a
standard way to maintain a regular sync of DT source files with Linux
kernel.

In order to maintain devicetree files sync, U-Boot will maintains a Git
subtree for devicetee-rebasing repo as `dts/upstream` sub-directory.
U-Boot will regularly sync `dts/upstream/` subtree whenever the next 
window

opens with the next available kernel major release.
`dts/update-dts-subtree.sh` script provides a wrapper around git subtree
pull command, usage from the top level U-Boot source tree, run:

$ ./dts/update-dts-subtree.sh 

The RFC/prototype for this series has been discussed with Linux DT
maintainers as well as U-Boot maintainers here [4]. Now we would like to
reach out to wider U-Boot community to seek feedback.


I very much agree with the direction this is going in, but I do have two 
simple questions:


How do you propose to handle fixes to DTs which are applied to 
linux-stable releases ? For example, if Linux 6.6(.0) ships a DT which 
has some defect that is fixed in 6.6.1, how will that fix get into 
U-Boot DTs ?


This fix would also be in the latest Linux tags, so I think it would 
find its way here - as I understand it patches aren't accepted into 
Linux stable unless they land in torvalds tree.


Assume that there is some large breaking change in Linux 6.(n+1), 
something which would be problematic for specific U-Boot platform (e.g. 
i.MX) or would require a lot of work to sort out, will there be a way to 
temporarily pin DTs for specific platform to older DT version until that 
is resolved (e.g. pin to 6.n) ?


(Upstream) devicetree has to be forwards and backwards compatible, were 
such a breaking change to get merged without prior discussion with DT 
users (i.e. U-Boot) then I think the correct course of action would be 
to revert it.


On a tangential note: as I understand it, DTs built from dt-rebasing are 
still subject to U-Boot customisations via the "-u-boot.dtsi" include 
files, this allows for dealing with incompatibilities due to missing 
features in U-Boot.


--
// Caleb (they/them)

Re: [PATCH v3] arch: arm: Kconfig: Enable BOOTSTD_FULL for Rockchip SoCs

[Shantur Rathore]

Hi Kever,

On Thu, Jan 18, 2024 at 3:10 AM Kever Yang  wrote:
>
> Hi Shantur,
>
> On 2024/1/17 17:38, Shantur Rathore wrote:
> > Hi Kever,
> >
> > On Wed, Jan 17, 2024 at 9:18 AM Kever Yang  
> > wrote:
> >> Hi Shantur,
> >>
> >> On 2024/1/17 14:26, Shantur Rathore wrote:
> >>
> >> Hi Kever,
> >>
> >> On Wed, Jan 10, 2024 at 11:58 AM Shantur Rathore  wrote:
> >>
> >> Hi Kever,
> >>
> >> On Tue, Jan 9, 2024 at 10:55 AM Kever Yang  
> >> wrote:
> >>
> >> Hi Shantur, Tom,
> >>
> >> On 2023/12/10 04:45, Tom Rini wrote:
> >>
> >> On Sat, Dec 09, 2023 at 07:49:04PM +, Shantur Rathore wrote:
> >>
> >> On Sat, Dec 9, 2023 at 7:18 PM Tom Rini  wrote:
> >>
> >> On Fri, Dec 08, 2023 at 10:52:02AM +, Shantur Rathore wrote:
> >>
> >> Hi Tom / Kever
> >>
> >> On Sun, Nov 19, 2023 at 5:24 PM Shantur Rathore  wrote:
> >>
> >> Rockchip SoCs can support wide range of bootflows.
> >> Without full bootflow commands, it can be difficult to
> >> figure out issues if any, hence enable by default.
> >>
> >> Reviewed-by: Simon Glass 
> >>
> >> Signed-off-by: Shantur Rathore 
> >> ---
> >>
> >> (no changes since v1)
> >>
> >>arch/arm/Kconfig | 1 +
> >>1 file changed, 1 insertion(+)
> >>
> >> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> >> index d812685c98..fca6ef6d7e 100644
> >> --- a/arch/arm/Kconfig
> >> +++ b/arch/arm/Kconfig
> >> @@ -1986,6 +1986,7 @@ config ARCH_ROCKCHIP
> >>   imply CMD_DM
> >>   imply DEBUG_UART_BOARD_INIT
> >>   imply BOOTSTD_DEFAULTS
> >> +   imply BOOTSTD_FULL if BOOTSTD_DEFAULTS
> >>   imply FAT_WRITE
> >>   imply SARADC_ROCKCHIP
> >>   imply SPL_SYSRESET
> >>
> >> Can this please be merged in ?
> >>
> >> I wonder if we shouldn't really globally default to BOOTSTD_FULL if
> >> BOOTSTD_DEFAULTS for everyone.
> >>
> >> Its matter of ~21KB in size, unless any platform is really to its
> >> limits it should be alright.
> >>
> >> Maybe I need to re-check things too, since I wonder how much of that
> >> growth is re-enabling things that were removed when dropping the DISTRO
> >> stuff, and so for platforms just migrating over now it would be smaller
> >> in size if much.
> >>
> >> A board maintainer is free to enable this option, but I don't agree to
> >> enable this for everyone.
> >>
> >> Not like rk3399 and rk3588, some of other SoCs always want a clean and
> >> simple but usable U-Boot,
> >>
> >> eg. rk3036 and rk3308 are still in the list.
> >>
> >> The discussion is what we consider "usable U-Boot"
> >> By default bootstd doesn't have any options and not even to show what
> >> it's going to boot.
> >>
> >> Would it be acceptable if BOOTSTD_FULL is enabled for SoCs rather than 
> >> boards?
> >>
> >> Can you please suggest the way forward?
> >> Initially the patch was for RockPro64 and then after discussion it was
> >> suggested that as BOOTSTD_DEFAULT is very very limited
> >> we should enable BOOTSTD_FULL for SoCs that can support multiple boot 
> >> modes.
> >>
> >> Let's enable it for RK3588 first and then maybe other SoCs which not code 
> >> size sensitive.
> >>
> > My requirement is for RK3399, so I will enable BOOTSTD_FULL for it.
> > While at it do you want me to enable it for RK3588 as well ?
>
> You can add for RK3399 or both RK3399 and RK3588.
>

Patch v5 [0] has been submitted with RK3399 and RK3588

[0] - 
https://patchwork.ozlabs.org/project/uboot/patch/20240121220447.663407-...@shantur.com/

Kind regards,
Shantur

[PATCH v5] arch: arm: mach-rockchip: Kconfig: Enable BOOTSTD_FULL for RK3399 and RK3588

[Shantur Rathore]

Rockchip RK3399 and RK3588 SoCs can support wide range of bootflows.
Without full bootflow commands, it can be difficult to
figure out issues if any, hence enable by default.

Reviewed-by: Simon Glass 

Signed-off-by: Shantur Rathore 
---

Changes in v5:
- Only enable it for RK3399 and RK3588 as suggested by Kever

Changes in v4:
- Replace BOOTSTD_DEFAULT with BOOTSTD_FULL as previous version
didn't apply on next

 arch/arm/mach-rockchip/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 6ff0aa6911..5a46c986ef 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -265,6 +265,7 @@ config ROCKCHIP_RK3399
imply TPL_TINY_MEMSET
imply TPL_ROCKCHIP_COMMON_BOARD
imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
+   imply BOOTSTD_FULL
imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
help
  The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
@@ -319,6 +320,7 @@ config ROCKCHIP_RK3588
imply MISC_INIT_R
imply CLK_SCMI
imply SCMI_FIRMWARE
+   imply BOOTSTD_FULL
help
  The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and
  quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4,
-- 
2.40.1

Re: [PATCH 3/3] net: ravb: Use PHY MDIO address from DT if available

[Paul Barker]

On 21/01/2024 17:29, Marek Vasut wrote:
> In case the PHY is fully described in DT, use PHY MDIO address
> from DT directly instead of always using auto-detection. This
> also fixes the behavior of 'mdio list' in such DT setup, which
> now prints the PHY connected to the MAC correctly.
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: Joe Hershberger 
> Cc: Paul Barker 
> Cc: Ramon Fried 
> ---
>  drivers/net/sh_eth.c | 10 --
>  1 file changed, 8 insertions(+), 2 deletions(-)

I think the commit summaries are mixed up here - this patch says 'ravb'
but changes 'sh_eth.c' and vice-versa with the other patch.

> 
> diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
> index 7b1f59dc498..5e2e3054ecf 100644
> --- a/drivers/net/sh_eth.c
> +++ b/drivers/net/sh_eth.c
> @@ -12,6 +12,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -597,11 +598,16 @@ static int sh_eth_phy_config(struct udevice *dev)
>   struct sh_ether_priv *priv = dev_get_priv(dev);
>   struct eth_pdata *pdata = dev_get_plat(dev);
>   struct sh_eth_dev *eth = >shdev;
> - int ret = 0;
>   struct sh_eth_info *port_info = >port_info[eth->port];
>   struct phy_device *phydev;
> + int phy_addr;
> + int ret = 0;
> +
> + phy_addr = eth_phy_get_addr(dev);
> + if (phy_addr < 0)
> + phy_addr = -1;
>  
> - phydev = phy_connect(priv->bus, -1, dev, pdata->phy_interface);
> + phydev = phy_connect(priv->bus, phy_addr, dev, pdata->phy_interface);
>   if (!phydev)
>   return -ENODEV;
>  

I have a local patch to handle (phy_addr < 0) in phy_connect_phy_id()
and lookup the address there. I think that's the better place to handle
this as it's a universal fix for all users of CONFIG_PHY_ETHERNET_ID.
Unfortunately I've been distracted by some higher priority work but I'm
hoping to get back to this soon.

I can do some quick testing with that patch and send it this week if
that's helpful.

Thanks,
Paul

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Description: OpenPGP public key


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Description: OpenPGP digital signature

Re: [PATCH v3] common: usb-hub: Reset hub port before scanning

[Shantur Rathore]

On Tue, Jan 16, 2024 at 12:45 AM Marek Vasut  wrote:
>
> On 1/8/24 23:11, Shantur Rathore wrote:
> > Hi Marex,
> >
> > On Sat, Dec 9, 2023 at 6:12 PM Shantur Rathore  wrote:
> >>
> >> Currently when a hub is turned on, all the ports are powered on.
> >> This works well for hubs which have individual power control.
> >>
> >> For the hubs without individual power control this has no effect.
> >> Mostly in these scenarios the hub port is powered before the USB
> >> controller is enabled, this can lead to some devices in unexpected
> >> state.
> >>
> >> With this patch, we explicitly reset the port while powering up hub
> >> This resets the port for hubs without port power control and has
> >> no effect on hubs with port power control as the port is still off.
> >>
> >> Before this patch AMicro AM8180 based NVME to USB adapter won't be
> >> detected as a USB3.0 Mass Storage device but with this it works as
> >> expected.
> >>
> >> Tested working after this patch:
> >> 1. AMicro AM8180 based NVME to USB Adapter
> >> 2. Kingston DataTraveler 3.0
> >> 3. GenesysLogic USB3.0 Hub
> >>
> >> The drives were tested while connected directly and via the hub.
> >>
> >> Signed-off-by: Shantur Rathore 
> >>
> >> ---
> >>
> >> Changes in v3:
> >> - Split up patches as seperate series
> >>
> >> Changes in v2:
> >> - As requested, added fix for regulator-always-on in RockPro64
> >>
> >>   common/usb_hub.c | 4 +++-
> >>   1 file changed, 3 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/common/usb_hub.c b/common/usb_hub.c
> >> index 70279f301d..3fb7e14d10 100644
> >> --- a/common/usb_hub.c
> >> +++ b/common/usb_hub.c
> >> @@ -174,8 +174,10 @@ static void usb_hub_power_on(struct usb_hub_device 
> >> *hub)
> >>
> >>  debug("enabling power on all ports\n");
> >>  for (i = 0; i < dev->maxchild; i++) {
> >> +   usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_RESET);
> >> +   debug("Reset : port %d returns %lX\n", i + 1, dev->status);
> >>  usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER);
> >> -   debug("port %d returns %lX\n", i + 1, dev->status);
> >> +   debug("PowerOn : port %d returns %lX\n", i + 1, 
> >> dev->status);
> >>  }
> >>
> >>   #ifdef CONFIG_SANDBOX
> >> --
> >> 2.40.1
> >>
> >
> > Do you think it is the right time to get this in early so it can be
> > tested for a longer time before the next release ?
>
> Yes, I think so, sorry for the delay.
>
> I asked Tom to pick it directly and provided RB .

Thanks Marek,

Just realised Tom isn't included in this chain.

@Tom Rini - Can I request you to please merge this earlier in this release.

Kind regards,
Shantur

Re: [PATCH] ARM: renesas: whitehawk: Drop extra leading space

[Paul Barker]

On 21/01/2024 17:33, Marek Vasut wrote:
> Drop leading space in front of a comment. No functional change.
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: Paul Barker 
> ---
>  board/renesas/whitehawk/whitehawk.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/board/renesas/whitehawk/whitehawk.c 
> b/board/renesas/whitehawk/whitehawk.c
> index 3423ebd2995..a72f5e0a7a5 100644
> --- a/board/renesas/whitehawk/whitehawk.c
> +++ b/board/renesas/whitehawk/whitehawk.c
> @@ -31,7 +31,7 @@ static void init_generic_timer(void)
>  
>  static void init_gic_v3(void)
>  {
> -  /* GIC v3 power on */
> + /* GIC v3 power on */
>   writel(BIT(1), GICR_LPI_PWRR);
>  
>   /* Wait till the WAKER_CA_BIT changes to 0 */

Simple enough.

Reviewed-by: Paul Barker 

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Re: [PATCH 01/11] dt-bindings: power: Add R8A779H0 V4M SYSC power domain definitions

[Paul Barker]

On 21/01/2024 17:41, Marek Vasut wrote:
> From: Duy Nguyen 
> 
> Add power domain indices for R-Car V4M (R8A779H0).
> 
> Signed-off-by: Duy Nguyen 
> Signed-off-by: Hai Pham 
> ---
> Cc: Paul Barker 
> ---
>  include/dt-bindings/power/r8a779h0-sysc.h | 49 +++
>  1 file changed, 49 insertions(+)
>  create mode 100644 include/dt-bindings/power/r8a779h0-sysc.h

We should reference the corresponding Linux kernel patch via
lore.kernel.org if this isn't in the mainline kernel yet.

Also, as a general series comment: I'd prefer to see a cover letter to
say which interfaces and key features are supported on the V4M by this
series. Is this enough to boot Linux from at least one interface (SDHI,
Ethernet, etc)?

Thanks,
Paul

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Re: [PATCH 02/11] dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions

[Paul Barker]

On 21/01/2024 17:41, Marek Vasut wrote:
> From: Duy Nguyen 
> 
> Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
> V4M (R8A779H0) SoC.
> 
> Signed-off-by: Duy Nguyen 
> Signed-off-by: Hai Pham 
> ---
> Cc: Paul Barker 
> ---
>  include/dt-bindings/clock/r8a779h0-cpg-mssr.h | 100 ++
>  1 file changed, 100 insertions(+)
>  create mode 100644 include/dt-bindings/clock/r8a779h0-cpg-mssr.h

We should reference the corresponding Linux kernel patch via
lore.kernel.org if this isn't in the mainline kernel yet.

Thanks,
Paul

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Re: [PATCH 03/11] clk: renesas: Add R8A779H0 V4M clock tables

[Paul Barker]

On 21/01/2024 17:41, Marek Vasut wrote:
> From: Hai Pham 
> 
> Add clock tables for R8A779H0 V4M SoC.
> 
> Signed-off-by: Hai Pham 
> ---
> Cc: Lukasz Majewski 
> Cc: Paul Barker 
> Cc: Sean Anderson 
> ---
>  drivers/clk/renesas/Kconfig |   6 +
>  drivers/clk/renesas/Makefile|   1 +
>  drivers/clk/renesas/r8a779h0-cpg-mssr.c | 294 
>  drivers/clk/renesas/rcar-gen3-cpg.h |   1 +
>  4 files changed, 302 insertions(+)
>  create mode 100644 drivers/clk/renesas/r8a779h0-cpg-mssr.c

How does this relate to the Linux kernel clk patch sent by Geert [1]? If
this patch is based on that, then we should have a link to that patch in
the commit message (since it hasn't appeared in a mainline kernel
release yet).

[1]: 
https://lore.kernel.org/all/0eb04b570d65d67de72069167e16d49e189dec54.1704726960.git.geert+rene...@glider.be/

Thanks,
Paul

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[PATCH v2 0/4] net: hifemac: a few cleanups

[Yang Xiwen via B4 Relay]

Fix the use of log_msg_ret() and add dev_xxx() for error reporting.

Register mdio subnode as a mdio bus device for hifemac.

Implement ops needed by `net stats`

Signed-off-by: Yang Xiwen 
---
Changes in v2:
- hisi-femac: add statistics related operations
- Link to v1: 
https://lore.kernel.org/r/20240119-net-v1-0-d1feb8e16...@outlook.com

---
Yang Xiwen (4):
  net: hifemac_mdio: use log_msg_ret() correctly, report error by dev_err()
  net: hifemac: fix log reporting
  net: hifemac: register MDIO bus device for subnode
  net: hifemac: implement `net stats` needed ops

 drivers/net/hifemac.c  | 225 +
 drivers/net/hifemac_mdio.c |  11 ++-
 2 files changed, 196 insertions(+), 40 deletions(-)
---
base-commit: f7cca7ccc5117eaafcc2bde91ad1bed6fee7cfc3
change-id: 20240119-net-72a32675eeb4

Best regards,
-- 
Yang Xiwen 

[PATCH v2 4/4] net: hifemac: implement `net stats` needed ops

[Yang Xiwen via B4 Relay]

From: Yang Xiwen 

3 operations needed by `net stats` are implemented. New `net stats`
output some useful info.

Signed-off-by: Yang Xiwen 
---
 drivers/net/hifemac.c | 87 +++
 1 file changed, 87 insertions(+)

diff --git a/drivers/net/hifemac.c b/drivers/net/hifemac.c
index 39c0233b62..24108bee4b 100644
--- a/drivers/net/hifemac.c
+++ b/drivers/net/hifemac.c
@@ -16,6 +16,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 
@@ -125,6 +127,57 @@ struct hisi_femac_priv {
u32 link_status;
 };
 
+struct hisi_femac_stat_entry {
+   const char *name;
+   u32 offset;
+   u32 mask;
+};
+
+/* please refer to the datasheet for the description of these entries */
+const struct hisi_femac_stat_entry hisi_femac_stats_table[] = {
+   { "rxsof_cnt",  0x584,  GENMASK(31, 28) },
+   { "rxeof_cnt",  0x584,  GENMASK(27, 24) },
+   { "rxcrcok_cnt",0x584,  GENMASK(23, 20) },
+   { "rxcrcbad_cnt",   0x584,  GENMASK(19, 16) },
+   { "txsof_cnt",  0x584,  GENMASK(15, 12) },
+   { "txeof_cnt",  0x584,  GENMASK(11, 8) },
+   { "txcrcok_cnt",0x584,  GENMASK(7, 4) },
+   { "txcrcbad_cnt",   0x584,  GENMASK(3, 0) },
+   { "pkts_cpu",   0x5a0,  GENMASK(15, 0) },
+   { "addr_cpu",   0x5a4,  GENMASK(15, 0) },
+   { "pkts_port",  0x5a8,  GENMASK(15, 0) },
+   { "pkts_cpu2tx",0x5ac,  GENMASK(15, 0) },
+   { "rxdvrise",   0x600,  GENMASK(31, 0) },
+   { "ifinoctets", 0x604,  GENMASK(31, 0) },
+   { "octets_rx",  0x608,  GENMASK(31, 0) },
+   { "local_mac_match",0x60c,  GENMASK(31, 0) },
+   { "pkts",   0x610,  GENMASK(31, 0) },
+   { "broadcastpkts",  0x614,  GENMASK(31, 0) },
+   { "multicastpkts",  0x618,  GENMASK(31, 0) },
+   { "ifinucastpkts",  0x61c,  GENMASK(31, 0) },
+   { "ifinerrors", 0x620,  GENMASK(31, 0) },
+   { "crcerr", 0x624,  GENMASK(31, 0) },
+   { "abnormalsizepkts",   0x628,  GENMASK(31, 0) },
+   { "dot3alignmenterr",   0x62c,  GENMASK(31, 0) },
+   { "dot3pause",  0x630,  GENMASK(31, 0) },
+   { "dropevents", 0x634,  GENMASK(31, 0) },
+   { "flux_frame_cnt", 0x638,  GENMASK(31, 0) },
+   { "flux_drop_cnt",  0x63c,  GENMASK(31, 0) },
+   { "mac_not2cpu_pkts",   0x64c,  GENMASK(31, 0) },
+   { "pkts_tx",0x780,  GENMASK(31, 0) },
+   { "broadcastpkts_tx",   0x784,  GENMASK(31, 0) },
+   { "multicastpkts_tx",   0x788,  GENMASK(31, 0) },
+   { "ifoutucastpkts_tx",  0x78c,  GENMASK(31, 0) },
+   { "octets_tx",  0x790,  GENMASK(31, 0) },
+   { "dot3pause",  0x794,  GENMASK(31, 0) },
+   { "retry_times_tx", 0x798,  GENMASK(31, 0) },
+   { "collisions", 0x79c,  GENMASK(31, 0) },
+   { "dot3latecol",0x7a0,  GENMASK(31, 0) },
+   { "dot3colok",  0x7a4,  GENMASK(31, 0) },
+   { "dot3excessivecol",   0x7a8,  GENMASK(31, 0) },
+   { "dot3colcnt", 0x7ac,  GENMASK(31, 0) },
+};
+
 static void hisi_femac_irq_enable(struct hisi_femac_priv *priv, int irqs)
 {
u32 val;
@@ -334,6 +387,37 @@ static void hisi_femac_stop(struct udevice *dev)
writel(SOFT_RESET_ALL, priv->glb_base + GLB_SOFT_RESET);
 }
 
+static int hisi_femac_get_sset_count(struct udevice *dev)
+{
+   return ARRAY_SIZE(hisi_femac_stats_table);
+}
+
+static void hisi_femac_get_strings(struct udevice *dev, u8 *data)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(hisi_femac_stats_table); i++)
+   strcpy(data + i * ETH_GSTRING_LEN, 
hisi_femac_stats_table[i].name);
+}
+
+/* Non-constant mask variant of FIELD_GET/FIELD_PREP */
+#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
+
+static void hisi_femac_get_stats(struct udevice *dev, u64 *data)
+{
+   int i;
+   u32 mask, reg;
+   struct hisi_femac_priv *priv = dev_get_priv(dev);
+   void __iomem *port_base = priv->port_base;
+
+   for (i = 0; i < ARRAY_SIZE(hisi_femac_stats_table); i++) {
+   mask = hisi_femac_stats_table[i].mask;
+   reg = readl(port_base + hisi_femac_stats_table[i].offset);
+
+   data[i] = field_get(mask, reg);
+   }
+}
+
 int hisi_femac_of_to_plat(struct udevice *dev)
 {
int ret, i;
@@ -523,6 +607,9 @@ static const struct eth_ops hisi_femac_ops = {
.free_pkt   = hisi_femac_free_pkt,
.stop   = hisi_femac_stop,
.write_hwaddr   = hisi_femac_set_hw_mac_addr,
+   .get_sset_count = hisi_femac_get_sset_count,
+   .get_strings= hisi_femac_get_strings,
+   .get_stats  = hisi_femac_get_stats,
 };
 
 static const struct udevice_id hisi_femac_ids[] = {

-- 
2.43.0

[PATCH v2 3/4] net: hifemac: register MDIO bus device for subnode

[Yang Xiwen via B4 Relay]

From: Yang Xiwen 

register internal MDIO bus device if it is a subnode.

Signed-off-by: Yang Xiwen 
---
 drivers/net/hifemac.c | 28 
 1 file changed, 28 insertions(+)

diff --git a/drivers/net/hifemac.c b/drivers/net/hifemac.c
index 1088f3eca3..39c0233b62 100644
--- a/drivers/net/hifemac.c
+++ b/drivers/net/hifemac.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -337,6 +338,8 @@ int hisi_femac_of_to_plat(struct udevice *dev)
 {
int ret, i;
struct hisi_femac_priv *priv = dev_get_priv(dev);
+   ofnode mdio_node;
+   bool mdio_registered = false;
static const char * const clk_strs[] = {
[CLK_MAC] = "mac",
[CLK_BUS] = "bus",
@@ -388,6 +391,31 @@ int hisi_femac_of_to_plat(struct udevice *dev)
 MAC_RESET_DELAY_PROPERTY,
 MAC_RESET_ASSERT_PERIOD);
 
+   /* Create MDIO bus */
+   ofnode_for_each_subnode(mdio_node, dev_ofnode(dev)) {
+   const char *subnode_name = ofnode_get_name(mdio_node);
+   struct udevice *mdiodev;
+
+   // Skip subnodes not starting with "mdio"
+   if (strncmp(subnode_name, "mdio", 4))
+   continue;
+
+   ret = device_bind_driver_to_node(dev, "hisi-femac-mdio",
+subnode_name, mdio_node, 
);
+   if (ret) {
+   dev_err(dev, "Failed to register MDIO bus device %d\n", 
ret);
+   return log_msg_ret("net", ret);
+   }
+
+   mdio_registered = true;
+   break;
+   }
+
+   if (!mdio_registered) {
+   dev_err(dev, "No MDIO subnode is found!\n");
+   return log_msg_ret("mdio", -ENODATA);
+   }
+
return 0;
 }
 

-- 
2.43.0

[PATCH v2 2/4] net: hifemac: fix log reporting

[Yang Xiwen via B4 Relay]

From: Yang Xiwen 

shrink the first argument of log_msg_ret(), add dev_xxx() functions for
error reporting.

Fixes: 9d8f78a2a79f7 ("net: add hifemac Ethernet driver for HiSilicon platform")

Signed-off-by: Yang Xiwen 
---
 drivers/net/hifemac.c | 110 +-
 1 file changed, 73 insertions(+), 37 deletions(-)

diff --git a/drivers/net/hifemac.c b/drivers/net/hifemac.c
index b61a29e636..1088f3eca3 100644
--- a/drivers/net/hifemac.c
+++ b/drivers/net/hifemac.c
@@ -245,8 +245,10 @@ static int hisi_femac_start(struct udevice *dev)
hisi_femac_rx_refill(priv);
 
ret = phy_startup(priv->phy);
-   if (ret)
-   return log_msg_ret("Failed to startup phy", ret);
+   if (ret) {
+   dev_err(dev, "Failed to startup phy: %d\n", ret);
+   return log_msg_ret("phy", ret);
+   }
 
if (!priv->phy->link) {
debug("%s: link down\n", __func__);
@@ -281,8 +283,10 @@ static int hisi_femac_send(struct udevice *dev, void 
*packet, int length)
 
// wait until FIFO is empty
ret = wait_for_bit_le32(priv->glb_base + GLB_IRQ_RAW, 
IRQ_INT_TX_PER_PACKET, true, 50, false);
-   if (ret == -ETIMEDOUT)
-   return log_msg_ret("FIFO timeout", ret);
+   if (ret == -ETIMEDOUT) {
+   dev_err(dev, "FIFO timeout\n");
+   return log_msg_ret("net", ret);
+   }
 
return 0;
 }
@@ -340,35 +344,45 @@ int hisi_femac_of_to_plat(struct udevice *dev)
};
 
priv->port_base = dev_remap_addr_name(dev, "port");
-   if (IS_ERR(priv->port_base))
-   return log_msg_ret("Failed to remap port address space", 
PTR_ERR(priv->port_base));
+   if (!priv->port_base) {
+   dev_err(dev, "Failed to remap port address space\n");
+   return log_msg_ret("net", -EINVAL);
+   }
 
priv->glb_base = dev_remap_addr_name(dev, "glb");
-   if (IS_ERR(priv->glb_base))
-   return log_msg_ret("Failed to remap global address space", 
PTR_ERR(priv->glb_base));
+   if (IS_ERR(priv->glb_base)) {
+   dev_err(dev, "Failed to remap global address space\n");
+   return log_msg_ret("net", -EINVAL);
+   }
 
for (i = 0; i < ARRAY_SIZE(clk_strs); i++) {
priv->clks[i] = devm_clk_get(dev, clk_strs[i]);
if (IS_ERR(priv->clks[i])) {
dev_err(dev, "Error getting clock %s\n", clk_strs[i]);
-   return log_msg_ret("Failed to get clocks", 
PTR_ERR(priv->clks[i]));
+   return log_msg_ret("clk", PTR_ERR(priv->clks[i]));
}
}
 
priv->mac_rst = devm_reset_control_get(dev, "mac");
-   if (IS_ERR(priv->mac_rst))
-   return log_msg_ret("Failed to get MAC reset", 
PTR_ERR(priv->mac_rst));
+   if (IS_ERR(priv->mac_rst)) {
+   dev_err(dev, "Failed to get MAC reset %ld\n", 
PTR_ERR(priv->mac_rst));
+   return log_msg_ret("rst", PTR_ERR(priv->mac_rst));
+   }
 
priv->phy_rst = devm_reset_control_get(dev, "phy");
-   if (IS_ERR(priv->phy_rst))
-   return log_msg_ret("Failed to get PHY reset", 
PTR_ERR(priv->phy_rst));
+   if (IS_ERR(priv->phy_rst)) {
+   dev_err(dev, "Failed to get PHY reset %ld\n", 
PTR_ERR(priv->phy_rst));
+   return log_msg_ret("rst", PTR_ERR(priv->phy_rst));
+   }
 
ret = dev_read_u32_array(dev,
 PHY_RESET_DELAYS_PROPERTY,
 priv->phy_reset_delays,
 DELAYS_NUM);
-   if (ret < 0)
-   return log_msg_ret("Failed to get PHY reset delays", ret);
+   if (ret < 0) {
+   dev_err(dev, "Failed to get PHY reset delays %d\n", ret);
+   return log_msg_ret("rst", ret);
+   }
 
priv->mac_reset_delay = dev_read_u32_default(dev,
 MAC_RESET_DELAY_PROPERTY,
@@ -385,32 +399,44 @@ static int hisi_femac_phy_reset(struct hisi_femac_priv 
*priv)
 
// Disable MAC clk before phy reset
ret = clk_disable(priv->clks[CLK_MAC]);
-   if (ret < 0)
-   return log_msg_ret("Failed to disable MAC clock", ret);
+   if (ret < 0) {
+   pr_err("%s: Failed to disable MAC clock %d\n", __func__, ret);
+   return log_msg_ret("clk", ret);
+   }
ret = clk_disable(priv->clks[CLK_BUS]);
-   if (ret < 0)
-   return log_msg_ret("Failed to disable bus clock", ret);
+   if (ret < 0) {
+   pr_err("%s: Failed to disable bus clock %d\n", __func__, ret);
+   return log_msg_ret("clk", ret);
+   }
 
udelay(delays[PRE_DELAY]);
 
ret = reset_assert(rst);
-   if (ret < 0)
-   return log_msg_ret("Failed to assert reset", ret);
+   if (ret < 0) {
+   

[PATCH v2 1/4] net: hifemac_mdio: use log_msg_ret() correctly, report error by dev_err()

[Yang Xiwen via B4 Relay]

From: Yang Xiwen 

The initial commit used log_msg_ret() wrongly. Fix that by moving error
report to a separate dev_err() call and shrink the first argument of
log_msg_ret() to no more than 4 chars.

Fixes: 6b5c8d98e204 ("net: add hifemac_mdio MDIO bus driver for HiSilicon 
platform")

Signed-off-by: Yang Xiwen 
---
 drivers/net/hifemac_mdio.c | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/net/hifemac_mdio.c b/drivers/net/hifemac_mdio.c
index 343c5f3a38..0b59d06091 100644
--- a/drivers/net/hifemac_mdio.c
+++ b/drivers/net/hifemac_mdio.c
@@ -8,6 +8,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -74,7 +75,8 @@ static int hisi_femac_mdio_of_to_plat(struct udevice *dev)
data->membase = dev_remap_addr(dev);
if (IS_ERR(data->membase)) {
ret = PTR_ERR(data->membase);
-   return log_msg_ret("Failed to remap base addr", ret);
+   dev_err(dev, "Failed to remap base addr %d\n", ret);
+   return log_msg_ret("mdio", ret);
}
 
// clk is optional
@@ -89,8 +91,10 @@ static int hisi_femac_mdio_probe(struct udevice *dev)
int ret;
 
ret = clk_prepare_enable(data->clk);
-   if (ret)
-   return log_msg_ret("Failed to enable clk", ret);
+   if (ret) {
+   dev_err(dev, "Failed to enable clock: %d\n", ret);
+   return log_msg_ret("clk", ret);
+   }
 
return 0;
 }
@@ -112,5 +116,6 @@ U_BOOT_DRIVER(hisi_femac_mdio_driver) = {
.of_to_plat = hisi_femac_mdio_of_to_plat,
.probe = hisi_femac_mdio_probe,
.ops = _femac_mdio_ops,
+   .plat_auto = sizeof(struct mdio_perdev_priv),
.priv_auto = sizeof(struct hisi_femac_mdio_data),
 };

-- 
2.43.0

[PATCH v2] rng: Add Turris Mox rWTM RNG driver

[Max Resch]

A RNG driver for Armada 3720 boards running the Turris Mox rWTM firmware
from CZ.NIC in the secure processor.

Signed-off-by: Max Resch 
---

Changes in v2:
 - Removed ring buffer implementation

 drivers/rng/Kconfig   |   8 +++
 drivers/rng/Makefile  |   1 +
 drivers/rng/turris_rwtm_rng.c | 122 ++
 3 files changed, 131 insertions(+)
 create mode 100644 drivers/rng/turris_rwtm_rng.c

diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index a89c899568..cd72852a47 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -105,4 +105,12 @@ config RNG_JH7110
help
  Enable True Random Number Generator in StarFive JH7110 SoCs.
 
+config RNG_TURRIS_RWTM
+   bool "Turris Mox TRNG in Secure Processor"
+   depends on DM_RNG && ARMADA_3700
+   help
+ Use TRNG in Turris Mox Secure Processor Firmware. Can be used
+ on other Armada-3700 devices (like EspressoBin) if Secure
+ Firmware from CZ.NIC is used.
+
 endif
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index 7e64c4cdfc..ecae1a3da3 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o
 obj-$(CONFIG_RNG_ARM_RNDR) += arm_rndr.o
 obj-$(CONFIG_TPM_RNG) += tpm_rng.o
 obj-$(CONFIG_RNG_JH7110) += jh7110_rng.o
+obj-$(CONFIG_RNG_TURRIS_RWTM) += turris_rwtm_rng.o
diff --git a/drivers/rng/turris_rwtm_rng.c b/drivers/rng/turris_rwtm_rng.c
new file mode 100644
index 00..143fe0b47f
--- /dev/null
+++ b/drivers/rng/turris_rwtm_rng.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (c) 2024, Max Resch
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* size of entropy buffer */
+#define RNG_BUFFER_SIZE128U
+
+struct turris_rwtm_rng_priv {
+   phys_addr_t buffer;
+};
+
+static int turris_rwtm_rng_fill_entropy(phys_addr_t entropy, size_t size)
+{
+   u32 args[3] = { 1, (u32)entropy, size };
+   int ret;
+
+   /* flush data cache */
+   flush_dcache_range(entropy, entropy + size);
+
+   /*
+* get entropy
+* args[0] = 1 copies BYTES array in args[1] of length args[2]
+*/
+   ret = mbox_do_cmd(MBOX_CMD_GET_RANDOM, args, 3, NULL, 0);
+   if (ret < 0)
+   return ret;
+
+   /* invalidate data cache */
+   invalidate_dcache_range(entropy, entropy + size);
+
+   return 0;
+}
+
+static int turris_rwtm_rng_random_read(struct udevice *dev, void *data, size_t 
count)
+{
+   phys_addr_t p;
+   size_t size;
+   int ret;
+
+   p = ((struct turris_rwtm_rng_priv *)dev_get_priv(dev))->buffer;
+
+   while (count) {
+   size = min_t(size_t, RNG_BUFFER_SIZE, count);
+
+   ret = turris_rwtm_rng_fill_entropy(p, size);
+
+   memcpy(data, (void *)p, size);
+   count -= size;
+   data = (u8 *)data + size;
+   }
+
+   return 0;
+}
+
+static int turris_rwtm_rng_probe(struct udevice *dev)
+{
+   struct turris_rwtm_rng_priv *priv;
+   u32 args[] = { 0 };
+   int ret;
+
+   /*
+* check if the random command is supported
+* args[0] = 0 would copy 16 DWORDS entropy to out but we ignore them
+*/
+   ret = mbox_do_cmd(MBOX_CMD_GET_RANDOM, args, ARRAY_SIZE(args), NULL, 0);
+
+   if (ret < 0)
+   return ret;
+
+   /* entropy buffer */
+   priv = (struct turris_rwtm_rng_priv *)dev_get_priv(dev);
+   priv->buffer = 0;
+
+   /* buffer address need to be aligned */
+   dma_alloc_coherent(RNG_BUFFER_SIZE, (unsigned long *)>buffer);
+   if (!priv->buffer)
+   return -ENOMEM;
+
+   return 0;
+}
+
+static int turris_rwtm_rng_remove(struct udevice *dev)
+{
+   phys_addr_t p;
+
+   p = ((struct turris_rwtm_rng_priv *)dev_get_priv(dev))->buffer;
+   dma_free_coherent((void *)p);
+
+   return 0;
+}
+
+static const struct dm_rng_ops turris_rwtm_rng_ops = {
+   .read = turris_rwtm_rng_random_read,
+};
+
+/*
+ * only Turris MOX firmware has the RNG but allow all probable devices to be
+ * probed the default firmware will just reject the probe
+ */
+static const struct udevice_id turris_rwtm_rng_match[] = {
+   { .compatible = "cznic,turris-mox-rwtm" },
+   { .compatible = "marvell,armada-3700-rwtm-firmware" },
+   {},
+};
+
+U_BOOT_DRIVER(turris_rwtm_rng) = {
+   .name   = "turris-rwtm-rng",
+   .id = UCLASS_RNG,
+   .of_match = turris_rwtm_rng_match,
+   .ops= _rwtm_rng_ops,
+   .probe  = turris_rwtm_rng_probe,
+   .remove = turris_rwtm_rng_remove,
+   .priv_auto = sizeof(struct turris_rwtm_rng_priv),
+};
-- 
2.43.0

Re: [PATCH 06/11] mtd: spi: renesas: Add R8A779H0 V4M support

[Paul Barker]

On 21/01/2024 17:41, Marek Vasut wrote:
> From: Hai Pham 
> 
> Support RPC SPI on R8A779H0 V4M SoC.
> 
> Signed-off-by: Hai Pham 
> ---
> Cc: Jagan Teki 
> Cc: Paul Barker 
> ---
>  drivers/spi/renesas_rpc_spi.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
> index 51c37d72eb6..3eb14061c81 100644
> --- a/drivers/spi/renesas_rpc_spi.c
> +++ b/drivers/spi/renesas_rpc_spi.c
> @@ -215,7 +215,8 @@ static u32 rpc_spi_get_strobe_delay(void)
>   if (cpu_type == RMOBILE_CPU_TYPE_R8A7796 && 
> rmobile_get_cpu_rev_integer() == 1)
>   return RPC_PHYCNT_STRTIM(6);
>   else if (cpu_type == RMOBILE_CPU_TYPE_R8A779F0 ||
> -  cpu_type == RMOBILE_CPU_TYPE_R8A779G0)
> +  cpu_type == RMOBILE_CPU_TYPE_R8A779G0 ||
> +  cpu_type == RMOBILE_CPU_TYPE_R8A779H0)
>   return RPC_PHYCNT_STRTIM2(15);
>   else
>  #endif

Reviewed-by: Paul Barker 

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Re: [PATCH 07/11] ARM: renesas: Add R8A779H0 V4M Kconfig entry and PRR ID

[Paul Barker]

On 21/01/2024 17:41, Marek Vasut wrote:
> From: Hai Pham 
> 
> Add Kconfig entry and PRR ID to support R8A779H0 V4M SoC.
> 
> Signed-off-by: Hai Pham 
> ---
> Cc: Paul Barker 
> ---
>  arch/arm/mach-rmobile/Kconfig.rcar4  | 6 ++
>  arch/arm/mach-rmobile/cpu_info.c | 1 +
>  arch/arm/mach-rmobile/include/mach/rmobile.h | 1 +
>  3 files changed, 8 insertions(+)
> 
> diff --git a/arch/arm/mach-rmobile/Kconfig.rcar4 
> b/arch/arm/mach-rmobile/Kconfig.rcar4
> index d4f93c89cac..3c8d683974c 100644
> --- a/arch/arm/mach-rmobile/Kconfig.rcar4
> +++ b/arch/arm/mach-rmobile/Kconfig.rcar4
> @@ -20,6 +20,12 @@ config R8A779G0
>   imply CLK_R8A779G0
>   imply PINCTRL_PFC_R8A779G0
>  
> +config R8A779H0
> + bool "Renesas SoC R8A779H0"
> + select GICV3
> + imply CLK_R8A779H0
> + imply PINCTRL_PFC_R8A779H0
> +
>  endmenu
>  
>  choice
> diff --git a/arch/arm/mach-rmobile/cpu_info.c 
> b/arch/arm/mach-rmobile/cpu_info.c
> index 895c0f5336b..3d5d5ba79a9 100644
> --- a/arch/arm/mach-rmobile/cpu_info.c
> +++ b/arch/arm/mach-rmobile/cpu_info.c
> @@ -78,6 +78,7 @@ static const struct {
>   { RMOBILE_CPU_TYPE_R8A779A0, "R8A779A0" },
>   { RMOBILE_CPU_TYPE_R8A779F0, "R8A779F0" },
>   { RMOBILE_CPU_TYPE_R8A779G0, "R8A779G0" },
> + { RMOBILE_CPU_TYPE_R8A779H0, "R8A779H0" },
>   { 0x0, "CPU" },
>  };
>  
> diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h 
> b/arch/arm/mach-rmobile/include/mach/rmobile.h
> index 88b8b78671b..f0216210ba9 100644
> --- a/arch/arm/mach-rmobile/include/mach/rmobile.h
> +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
> @@ -43,6 +43,7 @@
>  #define RMOBILE_CPU_TYPE_R8A779A00x59
>  #define RMOBILE_CPU_TYPE_R8A779F00x5A
>  #define RMOBILE_CPU_TYPE_R8A779G00x5C
> +#define RMOBILE_CPU_TYPE_R8A779H00x5D
>  #define RMOBILE_CPU_TYPE_R9A07G044L  0x9A070440
>  
>  #ifndef __ASSEMBLY__

Reviewed-by: Paul Barker 

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Re: [PATCH 09/11] ARM: dts: renesas: Add Renesas R8A779H0 V4M DT extras

[Paul Barker]

On 21/01/2024 17:41, Marek Vasut wrote:
> From: Hai Pham 
> 
> Add Renesas R8A779H0 V4M DT extras for U-Boot.
> 
> Signed-off-by: Hai Pham 
> ---
> Cc: Paul Barker 
> ---
>  arch/arm/dts/r8a779h0-u-boot.dtsi | 27 +++
>  1 file changed, 27 insertions(+)
>  create mode 100644 arch/arm/dts/r8a779h0-u-boot.dtsi
> 
> diff --git a/arch/arm/dts/r8a779h0-u-boot.dtsi 
> b/arch/arm/dts/r8a779h0-u-boot.dtsi
> new file mode 100644
> index 000..b2f7e054eef
> --- /dev/null
> +++ b/arch/arm/dts/r8a779h0-u-boot.dtsi
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source extras for U-Boot on R-Car R8A779H0 SoC
> + *
> + * Copyright (C) 2023 Renesas Electronics Corp.
> + */
> +
> +#include "r8a779x-u-boot.dtsi"
> +/ {
> + soc {
> + rpc: spi@ee20 {
> + compatible = "renesas,r8a779h0-rpc-if", 
> "renesas,rcar-gen4-rpc-if";
> + reg = <0 0xee20 0 0x200>, <0 0x0800 0 
> 0x0400>;
> + interrupts = ;
> + clocks = < CPG_MOD 629>;
> + power-domains = < R8A779H0_PD_ALWAYS_ON>;
> + resets = < 629>;
> + bank-width = <2>;
> + num-cs = <1>;
> + status = "disabled";
> + };

Either the commit message or a comment should give some idea why this
node is in a -u-boot.dtsi file instead of the r8a779h0.dtsi file itself.

Thanks,
Paul

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Re: [PATCH 08/11] ARM: dts: renesas: Add Renesas R8A779H0 V4M SoC support

[Paul Barker]

On 21/01/2024 17:41, Marek Vasut wrote:
> From: Hai Pham 
> 
> Add initial support for the Renesas R8A779H0 (R-Car V4M) SoC.
> 
> Signed-off-by: Hai Pham 
> ---
> Cc: Paul Barker 
> ---
>  arch/arm/dts/r8a779h0.dtsi | 461 +
>  1 file changed, 461 insertions(+)
>  create mode 100644 arch/arm/dts/r8a779h0.dtsi

Is this a sync from the Linux kernel? If so we should say which commit
the dtsi file is taken from.

Thanks,
Paul


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Re: [PATCH 10/11] ARM: dts: renesas: Add Renesas Gray Hawk boards support

[Paul Barker]

On 21/01/2024 17:41, Marek Vasut wrote:
> From: Hai Pham 
> 
> Initial support for the Renesas Gray Hawk CPU and BreakOut boards.
> 
> Signed-off-by: Hai Pham 
> ---
> Cc: Paul Barker 
> ---
>  arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi  | 165 ++
>  arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi  |  15 ++
>  arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi |  15 ++
>  arch/arm/dts/r8a779h0-gray-hawk.dts   |  25 +++
>  4 files changed, 220 insertions(+)
>  create mode 100644 arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi
>  create mode 100644 arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi
>  create mode 100644 arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi
>  create mode 100644 arch/arm/dts/r8a779h0-gray-hawk.dts

Is this a sync from the Linux kernel? If so we should say which commit
the dts/dtsi files are taken from.

Thanks,
Paul

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[PATCH] usb: dwc3-of-simple: Remove Amlogic and Rockchip compatible

[Jonas Karlman]

Remove the rockchip,rk3399-dwc3 compatible from the dwc3-of-simple
driver now that all boards have changed to use the dwc3-generic driver.

Also remove the amlogic,meson-gxl-dwc3 compatible, it is no longer in
use by any device tree in mainline linux or U-Boot.

Signed-off-by: Jonas Karlman 
---
 drivers/usb/host/dwc3-of-simple.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/usb/host/dwc3-of-simple.c 
b/drivers/usb/host/dwc3-of-simple.c
index f9df59d2e5d7..de1797d02ec0 100644
--- a/drivers/usb/host/dwc3-of-simple.c
+++ b/drivers/usb/host/dwc3-of-simple.c
@@ -90,8 +90,6 @@ static int dwc3_of_simple_remove(struct udevice *dev)
 }
 
 static const struct udevice_id dwc3_of_simple_ids[] = {
-   { .compatible = "amlogic,meson-gxl-dwc3" },
-   { .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "ti,dwc3" },
{ }
 };
-- 
2.43.0

Re: [PATCH 11/11] ARM: renesas: Add Renesas R8A779H0 V4M Gray Hawk board code

[Paul Barker]

On 21/01/2024 17:41, Marek Vasut wrote:
> diff --git a/board/renesas/grayhawk/MAINTAINERS 
> b/board/renesas/grayhawk/MAINTAINERS
> new file mode 100644
> index 000..b3532141ce7
> --- /dev/null
> +++ b/board/renesas/grayhawk/MAINTAINERS
> @@ -0,0 +1,7 @@
> +GRAYHAWK BOARD
> +M:   Marek Vasut 
> +S:   Maintained
> +F:   arch/arm/dts/r8a779h0*
> +F:   board/renesas/grayhawk/
> +F:   configs/r8a779h0_grayhawk_defconfig
> +F:   include/configs/grayhawk.h

You could use the following here to catch everything with 'r8a779h0' or
'grayhawk' in the filename:

  N:  r8a779h0
  N:  grayhawk

Otherwise, LGTM.

Reviewed-by: Paul Barker 

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[PATCH 11/11] ARM: renesas: Add Renesas R8A779H0 V4M Gray Hawk board code

[Marek Vasut]

From: Hai Pham 

Add board code for the Renesas R8A779H0 V4M Gray Hawk board.

Signed-off-by: Hai Pham 
---
Cc: Paul Barker 
---
 arch/arm/dts/Makefile  |  3 +-
 arch/arm/dts/r8a779h0-gray-hawk-u-boot.dts | 42 
 arch/arm/mach-rmobile/Kconfig.rcar4|  7 ++
 board/renesas/grayhawk/Kconfig | 15 +
 board/renesas/grayhawk/MAINTAINERS |  7 ++
 board/renesas/grayhawk/Makefile|  9 +++
 board/renesas/grayhawk/grayhawk.c  | 66 +++
 configs/r8a779h0_grayhawk_defconfig| 75 ++
 include/configs/grayhawk.h | 14 
 9 files changed, 237 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/r8a779h0-gray-hawk-u-boot.dts
 create mode 100644 board/renesas/grayhawk/Kconfig
 create mode 100644 board/renesas/grayhawk/MAINTAINERS
 create mode 100644 board/renesas/grayhawk/Makefile
 create mode 100644 board/renesas/grayhawk/grayhawk.c
 create mode 100644 configs/r8a779h0_grayhawk_defconfig
 create mode 100644 include/configs/grayhawk.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b5c588c3363..5e26f019436 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1169,7 +1169,8 @@ dtb-$(CONFIG_RCAR_GEN3) += \
 dtb-$(CONFIG_RCAR_GEN4) += \
r8a779a0-falcon-u-boot.dtb \
r8a779f0-spider-u-boot.dtb \
-   r8a779g0-white-hawk-u-boot.dtb
+   r8a779g0-white-hawk-u-boot.dtb \
+   r8a779h0-gray-hawk-u-boot.dtb
 
 dtb-$(CONFIG_TARGET_RZG2L) += \
r9a07g044l2-smarc.dts
diff --git a/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dts 
b/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dts
new file mode 100644
index 000..935ba9465dc
--- /dev/null
+++ b/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Gray Hawk board
+ *
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ */
+
+#include "r8a779h0-gray-hawk.dts"
+#include "r8a779h0-u-boot.dtsi"
+
+/ {
+   aliases {
+   spi0 = 
+   };
+};
+
+ {
+   qspi0_pins: qspi0 {
+   groups = "qspi0_ctrl", "qspi0_data4";
+   function = "qspi0";
+   };
+};
+
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+
+   #address-cells = <1>;
+   #size-cells = <0>;
+   spi-max-frequency = <4000>;
+   status = "okay";
+
+   flash@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "s25fs512s", "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <4000>;
+   spi-tx-bus-width = <1>;
+   spi-rx-bus-width = <1>;
+   };
+};
diff --git a/arch/arm/mach-rmobile/Kconfig.rcar4 
b/arch/arm/mach-rmobile/Kconfig.rcar4
index 3c8d683974c..e80dce11f54 100644
--- a/arch/arm/mach-rmobile/Kconfig.rcar4
+++ b/arch/arm/mach-rmobile/Kconfig.rcar4
@@ -50,10 +50,17 @@ config TARGET_WHITEHAWK
help
  Support for Renesas R-Car Gen4 White Hawk platform
 
+config TARGET_GRAYHAWK
+   bool "Gray Hawk board"
+   imply R8A779H0
+   help
+ Support for Renesas R-Car Gen4 Gray Hawk platform
+
 endchoice
 
 source "board/renesas/falcon/Kconfig"
 source "board/renesas/spider/Kconfig"
 source "board/renesas/whitehawk/Kconfig"
+source "board/renesas/grayhawk/Kconfig"
 
 endif
diff --git a/board/renesas/grayhawk/Kconfig b/board/renesas/grayhawk/Kconfig
new file mode 100644
index 000..97621a30ad0
--- /dev/null
+++ b/board/renesas/grayhawk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_GRAYHAWK
+
+config SYS_SOC
+   default "rmobile"
+
+config SYS_BOARD
+   default "grayhawk"
+
+config SYS_VENDOR
+   default "renesas"
+
+config SYS_CONFIG_NAME
+   default "grayhawk"
+
+endif
diff --git a/board/renesas/grayhawk/MAINTAINERS 
b/board/renesas/grayhawk/MAINTAINERS
new file mode 100644
index 000..b3532141ce7
--- /dev/null
+++ b/board/renesas/grayhawk/MAINTAINERS
@@ -0,0 +1,7 @@
+GRAYHAWK BOARD
+M: Marek Vasut 
+S: Maintained
+F: arch/arm/dts/r8a779h0*
+F: board/renesas/grayhawk/
+F: configs/r8a779h0_grayhawk_defconfig
+F: include/configs/grayhawk.h
diff --git a/board/renesas/grayhawk/Makefile b/board/renesas/grayhawk/Makefile
new file mode 100644
index 000..9c5b8c9a12f
--- /dev/null
+++ b/board/renesas/grayhawk/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/grayhawk/Makefile
+#
+# Copyright (C) 2023 Renesas Electronics Corp.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := grayhawk.o ../rcar-common/common.o
diff --git a/board/renesas/grayhawk/grayhawk.c 
b/board/renesas/grayhawk/grayhawk.c
new file mode 100644
index 000..6f2e73f7d38
--- /dev/null
+++ b/board/renesas/grayhawk/grayhawk.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board/renesas/grayhawk/grayhawk.c
+ * This file is Gray Hawk board support.
+ *
+ * Copyright (C) 2023 Renesas 

[PATCH 10/11] ARM: dts: renesas: Add Renesas Gray Hawk boards support

[Marek Vasut]

From: Hai Pham 

Initial support for the Renesas Gray Hawk CPU and BreakOut boards.

Signed-off-by: Hai Pham 
---
Cc: Paul Barker 
---
 arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi  | 165 ++
 arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi  |  15 ++
 arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi |  15 ++
 arch/arm/dts/r8a779h0-gray-hawk.dts   |  25 +++
 4 files changed, 220 insertions(+)
 create mode 100644 arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi
 create mode 100644 arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi
 create mode 100644 arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi
 create mode 100644 arch/arm/dts/r8a779h0-gray-hawk.dts

diff --git a/arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi 
b/arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi
new file mode 100644
index 000..1f6de45e502
--- /dev/null
+++ b/arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the Gray Hawk CPU board
+ *
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ */
+
+#include 
+#include 
+
+#include "r8a779h0.dtsi"
+
+/ {
+   model = "Renesas Gray Hawk CPU board";
+   compatible = "renesas,grayhawk-cpu", "renesas,r8a779h0";
+
+   aliases {
+   ethernet0 = 
+   serial0 = 
+   };
+
+   chosen {
+   bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
+   stdout-path = "serial0:921600n8";
+   };
+
+   memory@4800 {
+   device_type = "memory";
+   /* first 128MB is reserved for secure area. */
+   reg = <0x0 0x4800 0x0 0x7800>;
+   };
+
+   memory@48000 {
+   device_type = "memory";
+   reg = <0x4 0x8000 0x1 0x8000>;
+   };
+
+   reg_1p8v: regulator-1p8v {
+   compatible = "regulator-fixed";
+   regulator-name = "fixed-1.8V";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
+   reg_3p3v: regulator-3p3v {
+   compatible = "regulator-fixed";
+   regulator-name = "fixed-3.3V";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+};
+
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   phy-handle = <>;
+   tx-internal-delay-ps = <2000>;
+   status = "okay";
+
+   phy0: ethernet-phy@0 {
+   compatible = "ethernet-phy-id0022.1622",
+"ethernet-phy-ieee802.3-c22";
+   rxc-skew-ps = <1500>;
+   reg = <0>;
+   interrupt-parent = <>;
+   interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+   reset-gpios = < 10 GPIO_ACTIVE_LOW>;
+   };
+};
+
+_clk {
+   clock-frequency = <1666>;
+};
+
+_clk {
+   clock-frequency = <32768>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+
+   status = "okay";
+   clock-frequency = <40>;
+
+   eeprom@50 {
+   compatible = "rohm,br24g01", "atmel,24c01";
+   label = "cpu-board";
+   reg = <0x50>;
+   pagesize = <8>;
+   };
+};
+
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-1 = <_pins>;
+   pinctrl-names = "default", "state_uhs";
+
+   vmmc-supply = <_3p3v>;
+   vqmmc-supply = <_1p8v>;
+   mmc-hs200-1_8v;
+   mmc-hs400-1_8v;
+   bus-width = <8>;
+   no-sd;
+   no-sdio;
+   non-removable;
+   full-pwr-cycle-in-suspend;
+   status = "okay";
+};
+
+ {
+   pinctrl-0 = <_clk_pins>;
+   pinctrl-names = "default";
+
+   avb0_pins: avb0 {
+   mux {
+   groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
+"avb0_txcrefclk";
+   function = "avb0";
+   };
+
+   pins_mdio {
+   groups = "avb0_mdio";
+   drive-strength = <21>;
+   };
+
+   pins_mii {
+   groups = "avb0_rgmii";
+   drive-strength = <21>;
+   };
+   };
+
+   hscif0_pins: hscif0 {
+   groups = "hscif0_data", "hscif0_ctrl";
+   function = "hscif0";
+   };
+
+   i2c0_pins: i2c0 {
+   groups = "i2c0";
+   function = "i2c0";
+   };
+
+   mmc_pins: mmc {
+   groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
+   function = "mmc";
+   power-source = <1800>;
+   };
+
+   scif_clk_pins: scif_clk {
+   groups = 

[PATCH 09/11] ARM: dts: renesas: Add Renesas R8A779H0 V4M DT extras

[Marek Vasut]

From: Hai Pham 

Add Renesas R8A779H0 V4M DT extras for U-Boot.

Signed-off-by: Hai Pham 
---
Cc: Paul Barker 
---
 arch/arm/dts/r8a779h0-u-boot.dtsi | 27 +++
 1 file changed, 27 insertions(+)
 create mode 100644 arch/arm/dts/r8a779h0-u-boot.dtsi

diff --git a/arch/arm/dts/r8a779h0-u-boot.dtsi 
b/arch/arm/dts/r8a779h0-u-boot.dtsi
new file mode 100644
index 000..b2f7e054eef
--- /dev/null
+++ b/arch/arm/dts/r8a779h0-u-boot.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on R-Car R8A779H0 SoC
+ *
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ */
+
+#include "r8a779x-u-boot.dtsi"
+/ {
+   soc {
+   rpc: spi@ee20 {
+   compatible = "renesas,r8a779h0-rpc-if", 
"renesas,rcar-gen4-rpc-if";
+   reg = <0 0xee20 0 0x200>, <0 0x0800 0 
0x0400>;
+   interrupts = ;
+   clocks = < CPG_MOD 629>;
+   power-domains = < R8A779H0_PD_ALWAYS_ON>;
+   resets = < 629>;
+   bank-width = <2>;
+   num-cs = <1>;
+   status = "disabled";
+   };
+   };
+};
+
+_clk {
+   bootph-all;
+};
-- 
2.43.0

[PATCH 08/11] ARM: dts: renesas: Add Renesas R8A779H0 V4M SoC support

[Marek Vasut]

From: Hai Pham 

Add initial support for the Renesas R8A779H0 (R-Car V4M) SoC.

Signed-off-by: Hai Pham 
---
Cc: Paul Barker 
---
 arch/arm/dts/r8a779h0.dtsi | 461 +
 1 file changed, 461 insertions(+)
 create mode 100644 arch/arm/dts/r8a779h0.dtsi

diff --git a/arch/arm/dts/r8a779h0.dtsi b/arch/arm/dts/r8a779h0.dtsi
new file mode 100644
index 000..75d6a01e12d
--- /dev/null
+++ b/arch/arm/dts/r8a779h0.dtsi
@@ -0,0 +1,461 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the R-Car V4M (R8A779H0) SoC
+ *
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ */
+
+#include 
+#include 
+#include 
+
+/ {
+   compatible = "renesas,r8a779h0";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   a76_0: cpu@0 {
+   compatible = "arm,cortex-a76";
+   reg = <0>;
+   device_type = "cpu";
+   power-domains = < R8A779H0_PD_A1E0D0C0>;
+   };
+   };
+
+   extal_clk: extal {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   /* This value must be overridden by the board */
+   clock-frequency = <0>;
+   };
+
+   extalr_clk: extalr {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   /* This value must be overridden by the board */
+   clock-frequency = <0>;
+   };
+
+   pmu_a76 {
+   compatible = "arm,cortex-a76-pmu";
+   interrupts-extended = < GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+   };
+
+   /* External SCIF clock - to be overridden by boards that provide it */
+   scif_clk: scif {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   soc: soc {
+   compatible = "simple-bus";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   pfc: pinctrl@e605 {
+   compatible = "renesas,pfc-r8a779h0";
+   reg = <0 0xe605 0 0x16c>, <0 0xe6050800 0 0x16c>,
+ <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
+ <0 0xe606 0 0x16c>, <0 0xe6060800 0 0x16c>,
+ <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>;
+   };
+
+   gpio0: gpio@e6050180 {
+   compatible = "renesas,gpio-r8a779h0",
+"renesas,rcar-gen4-gpio";
+   reg = <0 0xe6050180 0 0x54>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 0 19>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 915>;
+   power-domains = < R8A779H0_PD_ALWAYS_ON>;
+   resets = < 915>;
+   };
+
+   gpio1: gpio@e6050980 {
+   compatible = "renesas,gpio-r8a779h0",
+"renesas,rcar-gen4-gpio";
+   reg = <0 0xe6050980 0 0x54>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 32 30>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 915>;
+   power-domains = < R8A779H0_PD_ALWAYS_ON>;
+   resets = < 915>;
+   };
+
+   gpio2: gpio@e6058180 {
+   compatible = "renesas,gpio-r8a779h0",
+"renesas,rcar-gen4-gpio";
+   reg = <0 0xe6058180 0 0x54>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 64 20>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 916>;
+   power-domains = < R8A779H0_PD_ALWAYS_ON>;
+   resets = < 916>;
+   };
+
+   gpio3: gpio@e6058980 {
+   compatible = "renesas,gpio-r8a779h0",
+"renesas,rcar-gen4-gpio";
+   reg = <0 0xe6058980 0 0x54>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 96 32>;
+ 

[PATCH 07/11] ARM: renesas: Add R8A779H0 V4M Kconfig entry and PRR ID

[Marek Vasut]

From: Hai Pham 

Add Kconfig entry and PRR ID to support R8A779H0 V4M SoC.

Signed-off-by: Hai Pham 
---
Cc: Paul Barker 
---
 arch/arm/mach-rmobile/Kconfig.rcar4  | 6 ++
 arch/arm/mach-rmobile/cpu_info.c | 1 +
 arch/arm/mach-rmobile/include/mach/rmobile.h | 1 +
 3 files changed, 8 insertions(+)

diff --git a/arch/arm/mach-rmobile/Kconfig.rcar4 
b/arch/arm/mach-rmobile/Kconfig.rcar4
index d4f93c89cac..3c8d683974c 100644
--- a/arch/arm/mach-rmobile/Kconfig.rcar4
+++ b/arch/arm/mach-rmobile/Kconfig.rcar4
@@ -20,6 +20,12 @@ config R8A779G0
imply CLK_R8A779G0
imply PINCTRL_PFC_R8A779G0
 
+config R8A779H0
+   bool "Renesas SoC R8A779H0"
+   select GICV3
+   imply CLK_R8A779H0
+   imply PINCTRL_PFC_R8A779H0
+
 endmenu
 
 choice
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index 895c0f5336b..3d5d5ba79a9 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -78,6 +78,7 @@ static const struct {
{ RMOBILE_CPU_TYPE_R8A779A0, "R8A779A0" },
{ RMOBILE_CPU_TYPE_R8A779F0, "R8A779F0" },
{ RMOBILE_CPU_TYPE_R8A779G0, "R8A779G0" },
+   { RMOBILE_CPU_TYPE_R8A779H0, "R8A779H0" },
{ 0x0, "CPU" },
 };
 
diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h 
b/arch/arm/mach-rmobile/include/mach/rmobile.h
index 88b8b78671b..f0216210ba9 100644
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -43,6 +43,7 @@
 #define RMOBILE_CPU_TYPE_R8A779A0  0x59
 #define RMOBILE_CPU_TYPE_R8A779F0  0x5A
 #define RMOBILE_CPU_TYPE_R8A779G0  0x5C
+#define RMOBILE_CPU_TYPE_R8A779H0  0x5D
 #define RMOBILE_CPU_TYPE_R9A07G044L0x9A070440
 
 #ifndef __ASSEMBLY__
-- 
2.43.0

[PATCH 06/11] mtd: spi: renesas: Add R8A779H0 V4M support

[Marek Vasut]

From: Hai Pham 

Support RPC SPI on R8A779H0 V4M SoC.

Signed-off-by: Hai Pham 
---
Cc: Jagan Teki 
Cc: Paul Barker 
---
 drivers/spi/renesas_rpc_spi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
index 51c37d72eb6..3eb14061c81 100644
--- a/drivers/spi/renesas_rpc_spi.c
+++ b/drivers/spi/renesas_rpc_spi.c
@@ -215,7 +215,8 @@ static u32 rpc_spi_get_strobe_delay(void)
if (cpu_type == RMOBILE_CPU_TYPE_R8A7796 && 
rmobile_get_cpu_rev_integer() == 1)
return RPC_PHYCNT_STRTIM(6);
else if (cpu_type == RMOBILE_CPU_TYPE_R8A779F0 ||
-cpu_type == RMOBILE_CPU_TYPE_R8A779G0)
+cpu_type == RMOBILE_CPU_TYPE_R8A779G0 ||
+cpu_type == RMOBILE_CPU_TYPE_R8A779H0)
return RPC_PHYCNT_STRTIM2(15);
else
 #endif
-- 
2.43.0

[PATCH 04/11] clk: renesas: Implement R8A779H0 V4M PLL7 support

[Marek Vasut]

Add PLL7 support to Gen3/Gen4 common clock driver. Add initial PLL7
multiplier and divider values into table in R8A779H0 V4M clock driver.

The PLL7 is new PLL added in R8A779H0 V4M SoC. Only integer multiplication
mode is supported by PLL7. The PLL reference clock are either 16.66 MHz or
20 MHz on R8A779H0 V4M SoC, and the output frequency must be 2000 MHz. The
multiplier values fitting this requirement are calculated to 120 or 100.

Signed-off-by: Marek Vasut 
---
Cc: Lukasz Majewski 
Cc: Paul Barker 
Cc: Sean Anderson 
---
 drivers/clk/renesas/clk-rcar-gen3.c |  6 ++
 drivers/clk/renesas/r8a779h0-cpg-mssr.c | 10 +-
 drivers/clk/renesas/rcar-gen3-cpg.h |  2 ++
 3 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/renesas/clk-rcar-gen3.c 
b/drivers/clk/renesas/clk-rcar-gen3.c
index 196903e406c..b84024266f4 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -306,6 +306,12 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
gen4_pll_config->pll6_div,
"PLL6");
 
+   case CLK_TYPE_GEN4_PLL7:
+   return gen3_clk_get_rate64_pll_mul_reg(priv, ,
+   0, gen4_pll_config->pll7_mult,
+   gen4_pll_config->pll7_div,
+   "PLL7");
+
case CLK_TYPE_FF:
return gen3_clk_get_rate64_pll_mul_reg(priv, ,
0, core->mult, core->div,
diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c 
b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
index 1399bfc8483..193884463ad 100644
--- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
@@ -207,11 +207,11 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
 (((md) & BIT(13)) >> 13))
 
 static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
-   /* EXTAL divPLL1 mult/div   PLL2 mult/div   PLL3 mult/div   PLL4 
mult/div   PLL5 mult/div   PLL6 mult/div   OSC prediv */
-   { 1,192,1,  240,1,  192,1,  240,
1,  192,1,  168,1,  16, },
-   { 1,160,1,  200,1,  160,1,  200,
1,  160,1,  140,1,  19, },
-   { 0,0,  0,  0,  0,  0,  0,  0,  
0,  0,  0,  0,  0,  0,  },
-   { 2,192,1,  240,1,  192,1,  240,
1,  192,1,  168,1,  32, },
+   /* EXTAL divPLL1 mult/div   PLL2 mult/div   PLL3 mult/div   PLL4 
mult/div   PLL5 mult/div   PLL6 mult/div   OSC prediv  PLL7 mult/div */
+   { 1,192,1,  240,1,  192,1,  240,
1,  192,1,  168,1,  16, 120,1,  },
+   { 1,160,1,  200,1,  160,1,  200,
1,  160,1,  140,1,  19, 100,1,  },
+   { 0,0,  0,  0,  0,  0,  0,  0,  
0,  0,  0,  0,  0,  0,  0,  0,  },
+   { 2,192,1,  240,1,  192,1,  240,
1,  192,1,  168,1,  32, 120,1,  },
 };
 
 /*
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h 
b/drivers/clk/renesas/rcar-gen3-cpg.h
index 7bea09c4827..4efb9b6ceef 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -131,6 +131,8 @@ struct rcar_gen4_cpg_pll_config {
u8 pll6_mult;
u8 pll6_div;
u8 osc_prediv;
+   u8 pll7_mult;
+   u8 pll7_div;
 };
 
 #define CPG_RST_MODEMR 0x060
-- 
2.43.0

[PATCH 03/11] clk: renesas: Add R8A779H0 V4M clock tables

[Marek Vasut]

From: Hai Pham 

Add clock tables for R8A779H0 V4M SoC.

Signed-off-by: Hai Pham 
---
Cc: Lukasz Majewski 
Cc: Paul Barker 
Cc: Sean Anderson 
---
 drivers/clk/renesas/Kconfig |   6 +
 drivers/clk/renesas/Makefile|   1 +
 drivers/clk/renesas/r8a779h0-cpg-mssr.c | 294 
 drivers/clk/renesas/rcar-gen3-cpg.h |   1 +
 4 files changed, 302 insertions(+)
 create mode 100644 drivers/clk/renesas/r8a779h0-cpg-mssr.c

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 927d62cf99a..e9296ed9fe2 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -151,6 +151,12 @@ config CLK_R8A779G0
help
  Enable this to support the clocks on Renesas R8A779G0 SoC.
 
+config CLK_R8A779H0
+   bool "Renesas R8A779H0 clock driver"
+   depends on CLK_RCAR_GEN3
+   help
+ Enable this to support the clocks on Renesas R8A779H0 SoC.
+
 config CLK_R9A06G032
bool "Renesas R9A06G032 clock driver"
depends on CLK_RENESAS
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index df7e225e9ca..6c742553091 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A779H0) += r8a779h0-cpg-mssr.o
 obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
 obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o
 obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c 
b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
new file mode 100644
index 000..1399bfc8483
--- /dev/null
+++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
@@ -0,0 +1,294 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a779h0 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ *
+ * Based on r8a779g0-cpg-mssr.c
+ */
+
+#include 
+#include 
+
+#include 
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+   /* Core Clock Outputs exported to DT */
+   LAST_DT_CORE_CLK = R8A779H0_CLK_R,
+
+   /* External Input Clocks */
+   CLK_EXTAL,
+   CLK_EXTALR,
+
+   /* Internal Core Clocks */
+   CLK_MAIN,
+   CLK_PLL1,
+   CLK_PLL2,
+   CLK_PLL3,
+   CLK_PLL4,
+   CLK_PLL5,
+   CLK_PLL6,
+   CLK_PLL7,
+   CLK_PLL1_DIV2,
+   CLK_PLL2_DIV2,
+   CLK_PLL3_DIV2,
+   CLK_PLL4_DIV2,
+   CLK_PLL4_DIV5,
+   CLK_PLL5_DIV2,
+   CLK_PLL5_DIV4,
+   CLK_PLL6_DIV2,
+   CLK_PLL7_DIV2,
+   CLK_S0,
+   CLK_S0_VIO,
+   CLK_S0_VC,
+   CLK_S0_HSC,
+   CLK_SASYNCPER,
+   CLK_SV_VIP,
+   CLK_SV_IR,
+   CLK_IMPASRC,
+   CLK_IMPBSRC,
+   CLK_VIOSCR,
+   CLK_VCSCR,
+   CLK_SDSRC,
+   CLK_RPCSRC,
+   CLK_OCO,
+
+   /* Module Clocks */
+   MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a779h0_core_clks[] = {
+   /* External Clock Inputs */
+   DEF_INPUT("extal",  CLK_EXTAL),
+   DEF_INPUT("extalr", CLK_EXTALR),
+
+   /* Internal Core Clocks */
+   DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
+   DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
+   DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN),
+   DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
+   DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN),
+   DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
+   DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
+   DEF_BASE(".pll7", CLK_PLL7, CLK_TYPE_GEN4_PLL7, CLK_MAIN),
+
+   DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,  CLK_PLL1,   2, 1),
+   DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2,  CLK_PLL2,   2, 1),
+   DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2,  CLK_PLL3,   2, 1),
+   DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2,  CLK_PLL4,   2, 1),
+   DEF_FIXED(".pll4_div5", CLK_PLL4_DIV5,  CLK_PLL4,   5, 1),
+   DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2,  CLK_PLL5,   2, 1),
+   DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4,  CLK_PLL5_DIV2,  2, 1),
+   DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2,  CLK_PLL6,   2, 1),
+   DEF_FIXED(".pll7_div2", CLK_PLL7_DIV2,  CLK_PLL7,   2, 1),
+   DEF_FIXED(".s0",CLK_S0, CLK_PLL1_DIV2,  2, 1),
+   DEF_FIXED(".s0_vio",CLK_S0_VIO, CLK_PLL1_DIV2,  2, 1),
+   DEF_FIXED(".s0_vc", CLK_S0_VC,  CLK_PLL1_DIV2,  2, 1),
+   DEF_FIXED(".s0_hsc",CLK_S0_HSC, CLK_PLL1_DIV2,  2, 1),
+   DEF_FIXED(".sasyncper", CLK_SASYNCPER,  CLK_PLL5_DIV4,  3, 1),
+   DEF_FIXED(".sv_vip",CLK_SV_VIP, CLK_PLL1,   5, 1),
+   DEF_FIXED(".sv_ir", 

[PATCH 02/11] dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions

[Marek Vasut]

From: Duy Nguyen 

Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
V4M (R8A779H0) SoC.

Signed-off-by: Duy Nguyen 
Signed-off-by: Hai Pham 
---
Cc: Paul Barker 
---
 include/dt-bindings/clock/r8a779h0-cpg-mssr.h | 100 ++
 1 file changed, 100 insertions(+)
 create mode 100644 include/dt-bindings/clock/r8a779h0-cpg-mssr.h

diff --git a/include/dt-bindings/clock/r8a779h0-cpg-mssr.h 
b/include/dt-bindings/clock/r8a779h0-cpg-mssr.h
new file mode 100644
index 000..d2efd2b8f96
--- /dev/null
+++ b/include/dt-bindings/clock/r8a779h0-cpg-mssr.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A779H0_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A779H0_CPG_MSSR_H__
+
+#include 
+
+/* r8a779h0 CPG Core Clocks */
+
+#define R8A779H0_CLK_ZX0
+#define R8A779H0_CLK_ZD1
+#define R8A779H0_CLK_ZS2
+#define R8A779H0_CLK_ZT3
+#define R8A779H0_CLK_ZTR   4
+#define R8A779H0_CLK_S0D2  5
+#define R8A779H0_CLK_S0D3  6
+#define R8A779H0_CLK_S0D4  7
+#define R8A779H0_CLK_S0D1_VIO  8
+#define R8A779H0_CLK_S0D2_VIO  9
+#define R8A779H0_CLK_S0D4_VIO  10
+#define R8A779H0_CLK_S0D8_VIO  11
+#define R8A779H0_CLK_VIOBUSD1  12
+#define R8A779H0_CLK_VIOBUSD2  13
+#define R8A779H0_CLK_S0D1_VC   14
+#define R8A779H0_CLK_S0D2_VC   15
+#define R8A779H0_CLK_S0D4_VC   16
+#define R8A779H0_CLK_VCBUSD1   17
+#define R8A779H0_CLK_VCBUSD2   18
+#define R8A779H0_CLK_S0D2_MM   19
+#define R8A779H0_CLK_S0D4_MM   20
+#define R8A779H0_CLK_S0D2_U3DG 21
+#define R8A779H0_CLK_S0D4_U3DG 22
+#define R8A779H0_CLK_S0D2_RT   23
+#define R8A779H0_CLK_S0D3_RT   24
+#define R8A779H0_CLK_S0D4_RT   25
+#define R8A779H0_CLK_S0D6_RT   26
+#define R8A779H0_CLK_S0D2_PER  27
+#define R8A779H0_CLK_S0D3_PER  28
+#define R8A779H0_CLK_S0D4_PER  29
+#define R8A779H0_CLK_S0D6_PER  30
+#define R8A779H0_CLK_S0D12_PER 31
+#define R8A779H0_CLK_S0D24_PER 32
+#define R8A779H0_CLK_S0D1_HSC  33
+#define R8A779H0_CLK_S0D2_HSC  34
+#define R8A779H0_CLK_S0D4_HSC  35
+#define R8A779H0_CLK_S0D8_HSC  36
+#define R8A779H0_CLK_SVD1_IR   37
+#define R8A779H0_CLK_SVD2_IR   38
+#define R8A779H0_CLK_IMPAD139
+#define R8A779H0_CLK_IMPAD440
+#define R8A779H0_CLK_IMPB  41
+#define R8A779H0_CLK_SVD1_VIP  42
+#define R8A779H0_CLK_SVD2_VIP  43
+#define R8A779H0_CLK_CL44
+#define R8A779H0_CLK_CL16M 45
+#define R8A779H0_CLK_CL16M_MM  46
+#define R8A779H0_CLK_CL16M_RT  47
+#define R8A779H0_CLK_CL16M_PER 48
+#define R8A779H0_CLK_CL16M_HSC 49
+#define R8A779H0_CLK_ZC0   50
+#define R8A779H0_CLK_ZC1   51
+#define R8A779H0_CLK_ZC2   52
+#define R8A779H0_CLK_ZC3   53
+#define R8A779H0_CLK_ZB3   54
+#define R8A779H0_CLK_ZB3D2 55
+#define R8A779H0_CLK_ZB3D4 56
+#define R8A779H0_CLK_ZG57
+#define R8A779H0_CLK_SD0H  58
+#define R8A779H0_CLK_SD0   59
+#define R8A779H0_CLK_RPC   60
+#define R8A779H0_CLK_RPCD2 61
+#define R8A779H0_CLK_MSO   62
+#define R8A779H0_CLK_CANFD 63
+#define R8A779H0_CLK_CSI   64
+#define R8A779H0_CLK_FRAY  65
+#define R8A779H0_CLK_IPC   66
+#define R8A779H0_CLK_POST2 67
+#define R8A779H0_CLK_POST3 68
+#define R8A779H0_CLK_POST4 69
+#define R8A779H0_CLK_POST  70
+#define R8A779H0_CLK_SASYNCRT  71
+#define R8A779H0_CLK_SASYNCPERD1   72
+#define R8A779H0_CLK_SASYNCPERD2   73
+#define R8A779H0_CLK_SASYNCPERD4   74
+#define R8A779H0_CLK_DSIEXT75
+#define R8A779H0_CLK_DSIREF76
+#define R8A779H0_CLK_ADGH  77
+#define R8A779H0_CLK_OSC   78
+#define R8A779H0_CLK_ZR0   79
+#define R8A779H0_CLK_ZR1   80
+#define R8A779H0_CLK_ZR2   81
+#define R8A779H0_CLK_RGMII 82
+#define R8A779H0_CLK_CPEX  83
+#define R8A779H0_CLK_CP84
+#define R8A779H0_CLK_CBFUSA85
+#define R8A779H0_CLK_R 86
+
+#endif /* __DT_BINDINGS_CLOCK_R8A779H0_CPG_MSSR_H__ */
-- 
2.43.0

[PATCH 01/11] dt-bindings: power: Add R8A779H0 V4M SYSC power domain definitions

[Marek Vasut]

From: Duy Nguyen 

Add power domain indices for R-Car V4M (R8A779H0).

Signed-off-by: Duy Nguyen 
Signed-off-by: Hai Pham 
---
Cc: Paul Barker 
---
 include/dt-bindings/power/r8a779h0-sysc.h | 49 +++
 1 file changed, 49 insertions(+)
 create mode 100644 include/dt-bindings/power/r8a779h0-sysc.h

diff --git a/include/dt-bindings/power/r8a779h0-sysc.h 
b/include/dt-bindings/power/r8a779h0-sysc.h
new file mode 100644
index 000..29f05f0401a
--- /dev/null
+++ b/include/dt-bindings/power/r8a779h0-sysc.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A779H0_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A779H0_SYSC_H__
+
+/*
+ * These power domain indices match the Power Domain Register Numbers (PDR)
+ */
+
+#define R8A779H0_PD_A1E0D0C0   0
+#define R8A779H0_PD_A1E0D0C1   1
+#define R8A779H0_PD_A1E0D0C2   2
+#define R8A779H0_PD_A1E0D0C3   3
+#define R8A779H0_PD_A2E0D0 16
+#define R8A779H0_PD_A3CR0  21
+#define R8A779H0_PD_A3CR1  22
+#define R8A779H0_PD_A3CR2  23
+#define R8A779H0_PD_A33DGA 24
+#define R8A779H0_PD_A23DGB 25
+#define R8A779H0_PD_C4 31
+#define R8A779H0_PD_A1DSP0 33
+#define R8A779H0_PD_A2IMP0134
+#define R8A779H0_PD_A2PSC  35
+#define R8A779H0_PD_A2CV0  36
+#define R8A779H0_PD_A2CV1  37
+#define R8A779H0_PD_A3IMR0 38
+#define R8A779H0_PD_A3IMR1 39
+#define R8A779H0_PD_A3VC   40
+#define R8A779H0_PD_A2CN0  42
+#define R8A779H0_PD_A1CN0  44
+#define R8A779H0_PD_A1DSP1 45
+#define R8A779H0_PD_A2DMA  47
+#define R8A779H0_PD_A2CV2  48
+#define R8A779H0_PD_A2CV3  49
+#define R8A779H0_PD_A3IMR2 50
+#define R8A779H0_PD_A3IMR3 51
+#define R8A779H0_PD_A3PCI  52
+#define R8A779H0_PD_A2PCIPHY   53
+#define R8A779H0_PD_A3VIP0 56
+#define R8A779H0_PD_A3VIP2 58
+#define R8A779H0_PD_A3ISP0 60
+#define R8A779H0_PD_A3DUL  62
+
+/* Always-on power area */
+#define R8A779H0_PD_ALWAYS_ON  64
+
+#endif /* __DT_BINDINGS_POWER_R8A779H0_SYSC_H__ */
-- 
2.43.0

[PATCH] ARM: renesas: whitehawk: Drop extra leading space

[Marek Vasut]

Drop leading space in front of a comment. No functional change.

Signed-off-by: Marek Vasut 
---
Cc: Paul Barker 
---
 board/renesas/whitehawk/whitehawk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/renesas/whitehawk/whitehawk.c 
b/board/renesas/whitehawk/whitehawk.c
index 3423ebd2995..a72f5e0a7a5 100644
--- a/board/renesas/whitehawk/whitehawk.c
+++ b/board/renesas/whitehawk/whitehawk.c
@@ -31,7 +31,7 @@ static void init_generic_timer(void)
 
 static void init_gic_v3(void)
 {
-/* GIC v3 power on */
+   /* GIC v3 power on */
writel(BIT(1), GICR_LPI_PWRR);
 
/* Wait till the WAKER_CA_BIT changes to 0 */
-- 
2.43.0

[PATCH 3/3] ARM: renesas: Drop include common.h

[Marek Vasut]

The header file is not necessary in either of those files,
remove it as common.h is going away.

Include missing asm/arch/rmobile.h in board/renesas/rcar-common/v3-common.c
to prevent build failure of r8a77970_eagle r8a779a0_falcon r8a77980_v3hsk
and r8a77970_v3msk .

Include missing asm/u-boot.h in falcon.c and grpeach.c to fix build failure
due to missing definition of struct bd_info . Include errno.h in grpeach.c
to fix build error due to missing definition of EINVAL.

Signed-off-by: Marek Vasut 
---
Cc: Adam Ford 
Cc: Paul Barker 
---
 board/renesas/alt/alt.c   | 1 -
 board/renesas/alt/alt_spl.c   | 1 -
 board/renesas/alt/qos.c   | 1 -
 board/renesas/blanche/blanche.c   | 1 -
 board/renesas/blanche/qos.c   | 1 -
 board/renesas/draak/draak.c   | 1 -
 board/renesas/falcon/falcon.c | 2 +-
 board/renesas/gose/gose.c | 1 -
 board/renesas/gose/gose_spl.c | 1 -
 board/renesas/gose/qos.c  | 1 -
 board/renesas/grpeach/grpeach.c   | 3 ++-
 board/renesas/koelsch/koelsch.c   | 1 -
 board/renesas/koelsch/koelsch_spl.c   | 1 -
 board/renesas/koelsch/qos.c   | 1 -
 board/renesas/lager/lager.c   | 1 -
 board/renesas/lager/lager_spl.c   | 1 -
 board/renesas/lager/qos.c | 1 -
 board/renesas/porter/porter.c | 1 -
 board/renesas/porter/porter_spl.c | 1 -
 board/renesas/porter/qos.c| 1 -
 board/renesas/r2dplus/r2dplus.c   | 1 -
 board/renesas/rcar-common/common.c| 1 -
 board/renesas/rcar-common/gen3-spl.c  | 1 -
 board/renesas/rcar-common/v3-common.c | 2 +-
 board/renesas/salvator-x/salvator-x.c | 1 -
 board/renesas/silk/qos.c  | 1 -
 board/renesas/silk/silk.c | 1 -
 board/renesas/silk/silk_spl.c | 1 -
 board/renesas/spider/spider.c | 1 -
 board/renesas/stout/cpld.c| 1 -
 board/renesas/stout/qos.c | 1 -
 board/renesas/stout/stout.c   | 1 -
 board/renesas/stout/stout_spl.c   | 1 -
 board/renesas/ulcb/cpld.c | 1 -
 board/renesas/ulcb/ulcb.c | 1 -
 board/renesas/v3hsk/cpld.c| 1 -
 board/renesas/v3msk/cpld.c| 1 -
 board/renesas/whitehawk/whitehawk.c   | 1 -
 38 files changed, 4 insertions(+), 38 deletions(-)

diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c
index 85fbaf0b28b..be77cade01b 100644
--- a/board/renesas/alt/alt.c
+++ b/board/renesas/alt/alt.c
@@ -5,7 +5,6 @@
  * Copyright (C) 2014, 2015 Renesas Electronics Corporation
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/board/renesas/alt/alt_spl.c b/board/renesas/alt/alt_spl.c
index cdaa04e4f4c..fc9dac55e6a 100644
--- a/board/renesas/alt/alt_spl.c
+++ b/board/renesas/alt/alt_spl.c
@@ -5,7 +5,6 @@
  * Copyright (C) 2018 Marek Vasut 
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/board/renesas/alt/qos.c b/board/renesas/alt/qos.c
index 2f657505ceb..38dfa647e81 100644
--- a/board/renesas/alt/qos.c
+++ b/board/renesas/alt/qos.c
@@ -6,7 +6,6 @@
  *
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c
index 8e1ae29e221..c6ecea2afcf 100644
--- a/board/renesas/blanche/blanche.c
+++ b/board/renesas/blanche/blanche.c
@@ -6,7 +6,6 @@
  * Copyright (C) 2016 Renesas Electronics Corporation
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/board/renesas/blanche/qos.c b/board/renesas/blanche/qos.c
index e3ad83ee0c2..3134b36a443 100644
--- a/board/renesas/blanche/qos.c
+++ b/board/renesas/blanche/qos.c
@@ -5,7 +5,6 @@
  * Copyright (C) 2016 Renesas Electronics Corporation
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c
index 1ed72d34a74..06a3a832984 100644
--- a/board/renesas/draak/draak.c
+++ b/board/renesas/draak/draak.c
@@ -6,7 +6,6 @@
  * Copyright (C) 2017 Marek Vasut 
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c
index 0aa0f1afcbf..cd86bb3108c 100644
--- a/board/renesas/falcon/falcon.c
+++ b/board/renesas/falcon/falcon.c
@@ -6,7 +6,6 @@
  * Copyright (C) 2020 Renesas Electronics Corp.
  */
 
-#include 
 #include 
 #include 
 #include 
@@ -15,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c
index 2d1435acff6..6edbdac3ded 100644
--- a/board/renesas/gose/gose.c
+++ b/board/renesas/gose/gose.c
@@ -5,7 +5,6 @@
  * Copyright (C) 2014 Renesas Electronics Corporation
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/board/renesas/gose/gose_spl.c b/board/renesas/gose/gose_spl.c
index c0bf7204439..87126a0fc15 100644
--- a/board/renesas/gose/gose_spl.c
+++ b/board/renesas/gose/gose_spl.c
@@ -5,7 +5,6 @@
  * Copyright (C) 2018 Marek Vasut 
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git 

[PATCH 2/3] pinctrl: renesas: Drop include common.h

[Marek Vasut]

The header file is not necessary in either of those files,
remove it as common.h is going away.

Signed-off-by: Marek Vasut 
---
Cc: Paul Barker 
---
 drivers/pinctrl/renesas/pfc-r8a7790.c  | 1 -
 drivers/pinctrl/renesas/pfc-r8a7791.c  | 1 -
 drivers/pinctrl/renesas/pfc-r8a7792.c  | 1 -
 drivers/pinctrl/renesas/pfc-r8a7794.c  | 1 -
 drivers/pinctrl/renesas/pfc-r8a77951.c | 1 -
 drivers/pinctrl/renesas/pfc-r8a7796.c  | 1 -
 drivers/pinctrl/renesas/pfc-r8a77965.c | 1 -
 drivers/pinctrl/renesas/pfc-r8a77970.c | 1 -
 drivers/pinctrl/renesas/pfc-r8a77980.c | 1 -
 drivers/pinctrl/renesas/pfc-r8a77990.c | 1 -
 drivers/pinctrl/renesas/pfc-r8a77995.c | 1 -
 drivers/pinctrl/renesas/pfc-r8a779a0.c | 1 -
 drivers/pinctrl/renesas/pfc-r8a779f0.c | 1 -
 drivers/pinctrl/renesas/pfc-r8a779g0.c | 1 -
 drivers/pinctrl/renesas/pfc.c  | 1 -
 drivers/pinctrl/renesas/pinctrl-rza1.c | 1 -
 16 files changed, 16 deletions(-)

diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c 
b/drivers/pinctrl/renesas/pfc-r8a7790.c
index 7203648bbc8..e1811c4c908 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7790.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7790.c
@@ -8,7 +8,6 @@
  * Copyright (C) 2012  Kuninori Morimoto 
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c 
b/drivers/pinctrl/renesas/pfc-r8a7791.c
index b25453ed285..fa94a51e5e7 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7791.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7791.c
@@ -6,7 +6,6 @@
  * Copyright (C) 2014-2017 Cogent Embedded, Inc.
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c 
b/drivers/pinctrl/renesas/pfc-r8a7792.c
index 08f1f97af6e..7c1e6d40749 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7792.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7792.c
@@ -6,7 +6,6 @@
  * Copyright (C) 2016 Cogent Embedded, Inc., 
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c 
b/drivers/pinctrl/renesas/pfc-r8a7794.c
index e5d125ceca0..29eab2610c1 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7794.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7794.c
@@ -7,7 +7,6 @@
  * Copyright (C) 2015-2017 Cogent Embedded, Inc. 
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c 
b/drivers/pinctrl/renesas/pfc-r8a77951.c
index 5d1c81c3eae..81568ae4a5e 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77951.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77951.c
@@ -5,7 +5,6 @@
  * Copyright (C) 2015-2019 Renesas Electronics Corporation
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c 
b/drivers/pinctrl/renesas/pfc-r8a7796.c
index 163d1805dfb..3de43febbd3 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7796.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7796.c
@@ -11,7 +11,6 @@
  * Copyright (C) 2015  Renesas Electronics Corporation
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c 
b/drivers/pinctrl/renesas/pfc-r8a77965.c
index 377143d3918..3a6813cee61 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77965.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77965.c
@@ -12,7 +12,6 @@
  * Copyright (C) 2015  Renesas Electronics Corporation
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c 
b/drivers/pinctrl/renesas/pfc-r8a77970.c
index 1cc6fa4f3fc..3c9c060d245 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77970.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77970.c
@@ -12,7 +12,6 @@
  * Copyright (C) 2015  Renesas Electronics Corporation
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c 
b/drivers/pinctrl/renesas/pfc-r8a77980.c
index 523faa0ac8f..14a4b4dc731 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77980.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77980.c
@@ -12,7 +12,6 @@
  * Copyright (C) 2015 Renesas Electronics Corporation
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c 
b/drivers/pinctrl/renesas/pfc-r8a77990.c
index 215a19ef9cd..e3a9c5e053d 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -11,7 +11,6 @@
  * Copyright (C) 2016-2017 Renesas Electronics Corp.
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c 
b/drivers/pinctrl/renesas/pfc-r8a77995.c
index c0d69937ddb..eccf5c15907 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77995.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77995.c
@@ -11,7 +11,6 @@
  * Copyright (C) 2015  Renesas Electronics Corporation
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c 
b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index 3c4b03b1b4c..6f898385027 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -7,7 +7,6 @@
  * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
  */
 

[PATCH 1/3] clk: renesas: Drop include common.h

[Marek Vasut]

The header file is not necessary in either of those files,
remove it as common.h is going away.

Signed-off-by: Marek Vasut 
---
Cc: Lukasz Majewski 
Cc: Paul Barker 
Cc: Sean Anderson 
---
 drivers/clk/renesas/clk-rcar-gen2.c | 1 -
 drivers/clk/renesas/clk-rcar-gen3.c | 1 -
 drivers/clk/renesas/r8a774a1-cpg-mssr.c | 1 -
 drivers/clk/renesas/r8a774b1-cpg-mssr.c | 1 -
 drivers/clk/renesas/r8a774c0-cpg-mssr.c | 1 -
 drivers/clk/renesas/r8a774e1-cpg-mssr.c | 1 -
 drivers/clk/renesas/r8a7790-cpg-mssr.c  | 1 -
 drivers/clk/renesas/r8a7791-cpg-mssr.c  | 1 -
 drivers/clk/renesas/r8a7792-cpg-mssr.c  | 1 -
 drivers/clk/renesas/r8a7794-cpg-mssr.c  | 1 -
 drivers/clk/renesas/r8a7795-cpg-mssr.c  | 1 -
 drivers/clk/renesas/r8a7796-cpg-mssr.c  | 1 -
 drivers/clk/renesas/r8a77965-cpg-mssr.c | 1 -
 drivers/clk/renesas/r8a77970-cpg-mssr.c | 1 -
 drivers/clk/renesas/r8a77980-cpg-mssr.c | 1 -
 drivers/clk/renesas/r8a77990-cpg-mssr.c | 1 -
 drivers/clk/renesas/r8a77995-cpg-mssr.c | 1 -
 drivers/clk/renesas/r8a779a0-cpg-mssr.c | 1 -
 drivers/clk/renesas/r8a779f0-cpg-mssr.c | 1 -
 drivers/clk/renesas/r8a779g0-cpg-mssr.c | 1 -
 drivers/clk/renesas/r9a06g032-clocks.c  | 1 -
 drivers/clk/renesas/rcar-cpg-lib.c  | 1 -
 drivers/clk/renesas/renesas-cpg-mssr.c  | 1 -
 23 files changed, 23 deletions(-)

diff --git a/drivers/clk/renesas/clk-rcar-gen2.c 
b/drivers/clk/renesas/clk-rcar-gen2.c
index 850d6411190..66ffef96b69 100644
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -10,7 +10,6 @@
  * Copyright (C) 2016 Glider bvba
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c 
b/drivers/clk/renesas/clk-rcar-gen3.c
index 0d274bb986e..196903e406c 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -10,7 +10,6 @@
  * Copyright (C) 2016 Glider bvba
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c 
b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index 6f94906cc99..d23041a8026 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -9,7 +9,6 @@
  * Copyright (C) 2016 Glider bvba
  */
 
-#include 
 #include 
 #include 
 
diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c 
b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
index 1a794980319..81d7dfe5421 100644
--- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
@@ -9,7 +9,6 @@
  * Copyright (C) 2016 Glider bvba
  */
 
-#include 
 #include 
 #include 
 
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c 
b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index ec8ce6ad7d6..f92fd25c0f7 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -10,7 +10,6 @@
  * Copyright (C) 2015 Renesas Electronics Corp.
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/clk/renesas/r8a774e1-cpg-mssr.c 
b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
index 6a8fe92b975..7c7cb7b6a05 100644
--- a/drivers/clk/renesas/r8a774e1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
@@ -9,7 +9,6 @@
  * Copyright (C) 2015 Glider bvba
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c 
b/drivers/clk/renesas/r8a7790-cpg-mssr.c
index 686f2af0052..190b68ee7d3 100644
--- a/drivers/clk/renesas/r8a7790-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c
@@ -9,7 +9,6 @@
  * Copyright (C) 2013 Ideas On Board SPRL
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c 
b/drivers/clk/renesas/r8a7791-cpg-mssr.c
index dcb0fd85c52..30711bf8921 100644
--- a/drivers/clk/renesas/r8a7791-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c
@@ -9,7 +9,6 @@
  * Copyright (C) 2013 Ideas On Board SPRL
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c 
b/drivers/clk/renesas/r8a7792-cpg-mssr.c
index 496e51aa73f..623981e9c38 100644
--- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
@@ -9,7 +9,6 @@
  * Copyright (C) 2013 Ideas On Board SPRL
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c 
b/drivers/clk/renesas/r8a7794-cpg-mssr.c
index f1828a6e543..c4124917923 100644
--- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
@@ -9,7 +9,6 @@
  * Copyright (C) 2013 Ideas On Board SPRL
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c 
b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index 0e9b9ccf979..e511f74982b 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -10,7 +10,6 @@
  * Copyright (C) 2015 Renesas Electronics Corp.
  */
 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c 

[PATCH 3/3] net: ravb: Use PHY MDIO address from DT if available

[Marek Vasut]

In case the PHY is fully described in DT, use PHY MDIO address
from DT directly instead of always using auto-detection. This
also fixes the behavior of 'mdio list' in such DT setup, which
now prints the PHY connected to the MAC correctly.

Signed-off-by: Marek Vasut 
---
Cc: Joe Hershberger 
Cc: Paul Barker 
Cc: Ramon Fried 
---
 drivers/net/sh_eth.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 7b1f59dc498..5e2e3054ecf 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -597,11 +598,16 @@ static int sh_eth_phy_config(struct udevice *dev)
struct sh_ether_priv *priv = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_plat(dev);
struct sh_eth_dev *eth = >shdev;
-   int ret = 0;
struct sh_eth_info *port_info = >port_info[eth->port];
struct phy_device *phydev;
+   int phy_addr;
+   int ret = 0;
+
+   phy_addr = eth_phy_get_addr(dev);
+   if (phy_addr < 0)
+   phy_addr = -1;
 
-   phydev = phy_connect(priv->bus, -1, dev, pdata->phy_interface);
+   phydev = phy_connect(priv->bus, phy_addr, dev, pdata->phy_interface);
if (!phydev)
return -ENODEV;
 
-- 
2.43.0

[PATCH 2/3] net: sh_eth: Use PHY MDIO address from DT if available

[Marek Vasut]

In case the PHY is fully described in DT, use PHY MDIO address
from DT directly instead of always using auto-detection. This
also fixes the behavior of 'mdio list' in such DT setup, which
now prints the PHY connected to the MAC correctly.

Signed-off-by: Marek Vasut 
---
Cc: Joe Hershberger 
Cc: Paul Barker 
Cc: Ramon Fried 
---
 drivers/net/ravb.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index 0bcd6cfd3f3..e1f61f514c8 100644
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -309,9 +310,14 @@ static int ravb_phy_config(struct udevice *dev)
struct ravb_priv *eth = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_plat(dev);
struct phy_device *phydev;
+   int phy_addr;
int reg;
 
-   phydev = phy_connect(eth->bus, -1, dev, pdata->phy_interface);
+   phy_addr = eth_phy_get_addr(dev);
+   if (phy_addr < 0)
+   phy_addr = -1;
+
+   phydev = phy_connect(eth->bus, phy_addr, dev, pdata->phy_interface);
if (!phydev)
return -ENODEV;
 
-- 
2.43.0

[PATCH 1/3] net: phy: Make eth_phy_get_addr() generic

[Marek Vasut]

Move eth_phy_get_addr() from drivers/net/eth-phy-uclass.c to
drivers/net/phy/phy.c . The eth_phy_get_addr() code is generic
and does not depend on DM_ETH_PHY , make it always available.

The dm/device_compat.h is pulled in to make dev_dbg() available.

Signed-off-by: Marek Vasut 
---
Cc: Joe Hershberger 
Cc: Paul Barker 
Cc: Ramon Fried 
---
 drivers/net/eth-phy-uclass.c | 16 
 drivers/net/phy/phy.c| 25 +
 2 files changed, 25 insertions(+), 16 deletions(-)

diff --git a/drivers/net/eth-phy-uclass.c b/drivers/net/eth-phy-uclass.c
index 9d1e8d38ffa..237c3b7de15 100644
--- a/drivers/net/eth-phy-uclass.c
+++ b/drivers/net/eth-phy-uclass.c
@@ -109,22 +109,6 @@ struct mii_dev *eth_phy_get_mdio_bus(struct udevice 
*eth_dev)
return NULL;
 }
 
-int eth_phy_get_addr(struct udevice *dev)
-{
-   struct ofnode_phandle_args phandle_args;
-   int reg;
-
-   if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
-  _args)) {
-   dev_dbg(dev, "Failed to find phy-handle");
-   return -ENODEV;
-   }
-
-   reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
-
-   return reg;
-}
-
 /* parsing generic properties of devicetree/bindings/net/ethernet-phy.yaml */
 static int eth_phy_of_to_plat(struct udevice *dev)
 {
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 63b3e46f101..0d1a98bbbca 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -28,6 +29,30 @@ DECLARE_GLOBAL_DATA_PTR;
 
 /* Generic PHY support and helper functions */
 
+/**
+ * eth_phy_get_addr - get PHY MDIO address from DT
+ * @dev: the udevice struct of the MAC
+ *
+ * Return PHY MDIO address read out of a PHY DT node "reg" property.
+ * The PHY DT node is located by resolving MAC "phy-handle" property.
+ * Returns PHY MDIO address on success, negative on failure.
+ */
+int eth_phy_get_addr(struct udevice *dev)
+{
+   struct ofnode_phandle_args phandle_args;
+   int reg;
+
+   if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+  _args)) {
+   dev_dbg(dev, "Failed to find phy-handle");
+   return -ENODEV;
+   }
+
+   reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
+
+   return reg;
+}
+
 /**
  * genphy_config_advert - sanitize and advertise auto-negotiation parameters
  * @phydev: target phy_device struct
-- 
2.43.0

Re: ACPI Vendor ID Request

[Tom Rini]

On Sun, Jan 21, 2024 at 03:42:16PM +0100, Heinrich Schuchardt wrote:
> Hello Tom,
> 
> as we have started to generate ACPI tables in U-Boot we should request an
> ACPI vendor ID for the U-Boot project.
> 
> As described in https://uefi.org/PNP_ACPI_Registry this is done by sending a
> mail to vid-requ...@uefi.org.
> 
> As the ID is meant to have 4 letters I suggest to use 'UBOO'.
> 
> https://uefi.org/ACPI_ID_List shows existing IDs. I don't know if the owner
> must be a legal company (which probably needs to be member of the UEFI
> forum) or we simply can have "Das U-Boot project" as owner.

I see from the list that Coreboot has "BOOT" so presumably we can
request UBOO for the project, and I've done so now.

-- 
Tom


signature.asc
Description: PGP signature

[PATCH v3 3/3] doc: sophgo: milkv_duo: document Milk-V Duo board

[Kongyang Liu]

Add document for Milk-V Duo board which based on Sophgo's CV1800B SoC.

Signed-off-by: Kongyang Liu 

---

Changes in v3:
- Add brief description of the procedure to run u-boot-dtb.bin

 doc/board/index.rst|  1 +
 doc/board/sophgo/index.rst |  8 +
 doc/board/sophgo/milkv_duo.rst | 64 ++
 3 files changed, 73 insertions(+)
 create mode 100644 doc/board/sophgo/index.rst
 create mode 100644 doc/board/sophgo/milkv_duo.rst

diff --git a/doc/board/index.rst b/doc/board/index.rst
index c96e5fda28..d0f9f355d2 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -46,6 +46,7 @@ Board-specific doc
sifive/index
sipeed/index
socionext/index
+   sophgo/index
st/index
starfive/index
ste/index
diff --git a/doc/board/sophgo/index.rst b/doc/board/sophgo/index.rst
new file mode 100644
index 00..e097afdac6
--- /dev/null
+++ b/doc/board/sophgo/index.rst
@@ -0,0 +1,8 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Sophgo
+==
+.. toctree::
+   :maxdepth: 1
+
+   milkv_duo
diff --git a/doc/board/sophgo/milkv_duo.rst b/doc/board/sophgo/milkv_duo.rst
new file mode 100644
index 00..cb2ed1ad98
--- /dev/null
+++ b/doc/board/sophgo/milkv_duo.rst
@@ -0,0 +1,64 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Milk-V Duo
+==
+
+CV1800B RISC-V SoC
+--
+The CV1800B is a high-performance, low-power 1+1 64-bit RISC-V SoC from Sophgo.
+
+Mainline support
+
+The support for following drivers are already enabled:
+1. ns16550 UART Driver.
+
+Building
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: console
+
+   export CROSS_COMPILE=
+   cd 
+   make milkv_duo_defconfig
+   make
+
+This will generate u-boot-dtb.bin
+
+Booting
+~~~
+Currently, we rely on vendor FSBL(First Stage Boot Loader) to initialize the
+clock and load the u-boot image, then bootup from it.
+
+Alternatively, to run u-boot-dtb.bin on top of FSBL, follow these steps:
+
+1. Use the vendor-provided tool to create a unified fip.bin file containing
+   FSBL, OpenSBI, and U-Boot.
+
+2. Place the generated fip.bin file into the FAT partition of the SD card.
+
+3. Insert the SD card into the board and power it on.
+
+The board will automatically execute the FSBL from the fip.bin file.
+Subsequently, it will transition to OpenSBI, and finally, OpenSBI will invoke
+U-Boot.
+
+
+Sample boot log from Milk-V Duo board
+~
+.. code-block:: none
+
+   U-Boot 2024.01-rc5-00010-g51965baa36 (Dec 28 2023 - 13:15:53 +0800)milkv_duo
+
+   DRAM:  63.3 MiB
+   Core:  10 devices, 8 uclasses, devicetree: separate
+   Loading Environment from nowhere... OK
+   In:serial@414
+   Out:   serial@414
+   Err:   serial@414
+   Net:   No ethernet found.
+   milkv_duo# cpu detail
+ 0: cpu@0  rv64imafdc
+  ID = 0, freq = 0 Hz: L1 cache, MMU
+   milkv_duo#
-- 
2.41.0

[PATCH v3 2/3] riscv: sophgo: milkv_duo: initial support added

[Kongyang Liu]

Add support for Sophgo's Milk-V Duo board, only minimal device tree and
serial console are enabled, and it can boot via vendor first stage
bootloader.

Signed-off-by: Kongyang Liu 

---

Changes in v3:
- Enable EFI loader

Changes in v2:
- Fold the defconfig patch to first patch
- Remove unnecessary environment settings of consoledev and baudrate in
  config

 arch/riscv/Kconfig |  4 
 board/sophgo/milkv_duo/Kconfig | 28 
 board/sophgo/milkv_duo/MAINTAINERS |  6 ++
 board/sophgo/milkv_duo/Makefile|  5 +
 board/sophgo/milkv_duo/board.c |  9 +
 configs/milkv_duo_defconfig| 23 +++
 include/configs/milkv_duo.h| 12 
 7 files changed, 87 insertions(+)
 create mode 100644 board/sophgo/milkv_duo/Kconfig
 create mode 100644 board/sophgo/milkv_duo/MAINTAINERS
 create mode 100644 board/sophgo/milkv_duo/Makefile
 create mode 100644 board/sophgo/milkv_duo/board.c
 create mode 100644 configs/milkv_duo_defconfig
 create mode 100644 include/configs/milkv_duo.h

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 67126d96af..ac52c5e6da 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -14,6 +14,9 @@ config TARGET_ANDES_AE350
 config TARGET_MICROCHIP_ICICLE
bool "Support Microchip PolarFire-SoC Icicle Board"
 
+config TARGET_MILKV_DUO
+   bool "Support Milk-v Duo Board"
+
 config TARGET_OPENPITON_RISCV64
bool "Support RISC-V cores on OpenPiton SoC"
 
@@ -83,6 +86,7 @@ source "board/openpiton/riscv64/Kconfig"
 source "board/sifive/unleashed/Kconfig"
 source "board/sifive/unmatched/Kconfig"
 source "board/sipeed/maix/Kconfig"
+source "board/sophgo/milkv_duo/Kconfig"
 source "board/starfive/visionfive2/Kconfig"
 source "board/thead/th1520_lpi4a/Kconfig"
 source "board/xilinx/mbv/Kconfig"
diff --git a/board/sophgo/milkv_duo/Kconfig b/board/sophgo/milkv_duo/Kconfig
new file mode 100644
index 00..2a458f291c
--- /dev/null
+++ b/board/sophgo/milkv_duo/Kconfig
@@ -0,0 +1,28 @@
+if TARGET_MILKV_DUO
+
+config SYS_BOARD
+   default "milkv_duo"
+
+config SYS_VENDOR
+   default "sophgo"
+
+config SYS_CPU
+   default "generic"
+
+config SYS_CONFIG_NAME
+   default "milkv_duo"
+
+config TEXT_BASE
+   default 0x8020
+
+config ENV_SIZE
+   default 0x2
+
+config ENV_SECT_SIZE
+   default 0x4
+
+config BOARD_SPECIFIC_OPTIONS
+   def_bool y
+   select GENERIC_RISCV
+
+endif
diff --git a/board/sophgo/milkv_duo/MAINTAINERS 
b/board/sophgo/milkv_duo/MAINTAINERS
new file mode 100644
index 00..651a0592f7
--- /dev/null
+++ b/board/sophgo/milkv_duo/MAINTAINERS
@@ -0,0 +1,6 @@
+Milk-V Duo
+M: Kongyang Liu 
+S: Maintained
+F: board/sophgo/milkv_duo/
+F: configs/milkv_duo_defconfig
+F: doc/board/sophgo/milkv_duo.rst
diff --git a/board/sophgo/milkv_duo/Makefile b/board/sophgo/milkv_duo/Makefile
new file mode 100644
index 00..a087013f5c
--- /dev/null
+++ b/board/sophgo/milkv_duo/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024, Kongyang Liu 
+
+obj-y := board.o
diff --git a/board/sophgo/milkv_duo/board.c b/board/sophgo/milkv_duo/board.c
new file mode 100644
index 00..eaa47be173
--- /dev/null
+++ b/board/sophgo/milkv_duo/board.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu 
+ */
+
+int board_init(void)
+{
+   return 0;
+}
diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig
new file mode 100644
index 00..9eca6abfbc
--- /dev/null
+++ b/configs/milkv_duo_defconfig
@@ -0,0 +1,23 @@
+CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x82
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8230
+CONFIG_DEFAULT_DEVICE_TREE="cv1800b-milkv-duo"
+CONFIG_IDENT_STRING="milkv_duo"
+CONFIG_SYS_LOAD_ADDR=0x8008
+CONFIG_TARGET_MILKV_DUO=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_FIT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="milkv_duo# "
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=544
+CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
diff --git a/include/configs/milkv_duo.h b/include/configs/milkv_duo.h
new file mode 100644
index 00..0b4109dc1f
--- /dev/null
+++ b/include/configs/milkv_duo.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024, Kongyang Liu 
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CFG_SYS_SDRAM_BASE 0x8000
+
+#endif /* __CONFIG_H */
-- 
2.41.0

[PATCH v3 1/3] riscv: dts: sophgo: add basic device tree for Milk-V Duo board

[Kongyang Liu]

Import device tree from Linux kernel to add basic support for CPU, PLIC,
UART and Timer. The name cv1800b in the filename represent the chip used
on Milk-V Duo board.

Signed-off-by: Kongyang Liu 

---

Changes in v3:
- Swap patch 1 and 2 duo to dependency of defconfig and device tree

 arch/riscv/dts/Makefile  |   1 +
 arch/riscv/dts/cv1800b-milkv-duo.dts |  38 +
 arch/riscv/dts/cv1800b.dtsi  | 123 +++
 3 files changed, 162 insertions(+)
 create mode 100644 arch/riscv/dts/cv1800b-milkv-duo.dts
 create mode 100644 arch/riscv/dts/cv1800b.dtsi

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index b05bb5607f..17cda483e1 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -2,6 +2,7 @@
 
 dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb
 dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
+dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb
 dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
 dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
diff --git a/arch/riscv/dts/cv1800b-milkv-duo.dts 
b/arch/riscv/dts/cv1800b-milkv-duo.dts
new file mode 100644
index 00..3af9e34b3b
--- /dev/null
+++ b/arch/riscv/dts/cv1800b-milkv-duo.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang 
+ */
+
+/dts-v1/;
+
+#include "cv1800b.dtsi"
+
+/ {
+   model = "Milk-V Duo";
+   compatible = "milkv,duo", "sophgo,cv1800b";
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   serial3 = 
+   serial4 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory@8000 {
+   device_type = "memory";
+   reg = <0x8000 0x3f4>;
+   };
+};
+
+ {
+   clock-frequency = <2500>;
+};
+
+ {
+   status = "okay";
+};
diff --git a/arch/riscv/dts/cv1800b.dtsi b/arch/riscv/dts/cv1800b.dtsi
new file mode 100644
index 00..df40e87ee0
--- /dev/null
+++ b/arch/riscv/dts/cv1800b.dtsi
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang 
+ */
+
+#include 
+
+/ {
+   compatible = "sophgo,cv1800b";
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   cpus: cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   timebase-frequency = <2500>;
+
+   cpu0: cpu@0 {
+   compatible = "thead,c906", "riscv";
+   device_type = "cpu";
+   reg = <0>;
+   d-cache-block-size = <64>;
+   d-cache-sets = <512>;
+   d-cache-size = <65536>;
+   i-cache-block-size = <64>;
+   i-cache-sets = <128>;
+   i-cache-size = <32768>;
+   mmu-type = "riscv,sv39";
+   riscv,isa = "rv64imafdc";
+   riscv,isa-base = "rv64i";
+   riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 
"zicntr", "zicsr",
+  "zifencei", "zihpm";
+
+   cpu0_intc: interrupt-controller {
+   compatible = "riscv,cpu-intc";
+   interrupt-controller;
+   #address-cells = <0>;
+   #interrupt-cells = <1>;
+   };
+   };
+   };
+
+   osc: oscillator {
+   compatible = "fixed-clock";
+   clock-output-names = "osc_25m";
+   #clock-cells = <0>;
+   };
+
+   soc {
+   compatible = "simple-bus";
+   interrupt-parent = <>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   dma-noncoherent;
+   ranges;
+
+   uart0: serial@414 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x0414 0x100>;
+   interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = <>;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   status = "disabled";
+   };
+
+   uart1: serial@415 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x0415 0x100>;
+   interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = <>;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   status = "disabled";
+   };
+
+   uart2: serial@416 {
+   compatible = 

[PATCH v3 0/3] riscv: sophgo: milkv_duo: add support for Milk-V Duo board

[Kongyang Liu]

The Milk-V Duo board is built upon Sophgo's CV1800B SoC, featuring two
XuanTie C906 CPUs running at 1.0GHz and 700MHz, respectively.

This series introduces fundamental support for the Milk-V Duo board,
encompassing UART, CPU, and PLIC support. This ensures that U-Boot can
operate in serial console mode.

Changes in v3:
- Swap patch 1 and 2 duo to dependency of defconfig and device tree
- Enable EFI loader
- Add brief description of the procedure to run u-boot-dtb.bin

Changes in v2:
- Fold the defconfig patch to first patch
- Remove unnecessary environment settings of consoledev and baudrate in
  config

Kongyang Liu (3):
  riscv: dts: sophgo: add basic device tree for Milk-V Duo board
  riscv: sophgo: milkv_duo: initial support added
  doc: sophgo: milkv_duo: document Milk-V Duo board

 arch/riscv/Kconfig   |   4 +
 arch/riscv/dts/Makefile  |   1 +
 arch/riscv/dts/cv1800b-milkv-duo.dts |  38 +
 arch/riscv/dts/cv1800b.dtsi  | 123 +++
 board/sophgo/milkv_duo/Kconfig   |  28 ++
 board/sophgo/milkv_duo/MAINTAINERS   |   6 ++
 board/sophgo/milkv_duo/Makefile  |   5 ++
 board/sophgo/milkv_duo/board.c   |   9 ++
 configs/milkv_duo_defconfig  |  23 +
 doc/board/index.rst  |   1 +
 doc/board/sophgo/index.rst   |   8 ++
 doc/board/sophgo/milkv_duo.rst   |  64 ++
 include/configs/milkv_duo.h  |  12 +++
 13 files changed, 322 insertions(+)
 create mode 100644 arch/riscv/dts/cv1800b-milkv-duo.dts
 create mode 100644 arch/riscv/dts/cv1800b.dtsi
 create mode 100644 board/sophgo/milkv_duo/Kconfig
 create mode 100644 board/sophgo/milkv_duo/MAINTAINERS
 create mode 100644 board/sophgo/milkv_duo/Makefile
 create mode 100644 board/sophgo/milkv_duo/board.c
 create mode 100644 configs/milkv_duo_defconfig
 create mode 100644 doc/board/sophgo/index.rst
 create mode 100644 doc/board/sophgo/milkv_duo.rst
 create mode 100644 include/configs/milkv_duo.h

-- 
2.41.0

ACPI Vendor ID Request

[Heinrich Schuchardt]

Hello Tom,

as we have started to generate ACPI tables in U-Boot we should request 
an ACPI vendor ID for the U-Boot project.


As described in https://uefi.org/PNP_ACPI_Registry this is done by 
sending a mail to vid-requ...@uefi.org.


As the ID is meant to have 4 letters I suggest to use 'UBOO'.

https://uefi.org/ACPI_ID_List shows existing IDs. I don't know if the 
owner must be a legal company (which probably needs to be member of the 
UEFI forum) or we simply can have "Das U-Boot project" as owner.


Best regards

Heinrich

Re: [PATCH v4 00/11] An effort to bring DT bindings compliance within U-Boot

[Marek Vasut]

On 1/10/24 11:35, Sumit Garg wrote:

Changes in v4:
--
- Switched subtree to be imported as dts/upstream sub-directory rather
   than devicetree-rebasing sub-directory to better suite U-Boot
   directory structure.
- Since we now have v6.7-dts tag available now, so switch subtree to
   that from its beginning.
- Patch #2: Incorporate build fix to adjust Bindings Makefile rules to
   old U-Boot Kbuild infrastructure.
- Patch #3: Incorporate fix to resolve rk3399 migration issue reported
   by Simon.
- Patch #4: New patch to reuse upstream DT includes by U-Boot as per
   Brian's use-case for TI K3 SoCs.
- Patch #5: Added a note to OF_UPSTREAM Kconfig option.
- Patch #6: New patch to add script dts/update-dts-subtree.sh as per
   Rob's comments.
- Patch #7: Separate patch to align documentation to use Kconfig symbols
   instead.
- Patch #8: Clarify subtree uprev schedule as a separate documentation
   section. Also, fixed documentation typos.
- Patch #9: Added commit description.

Changes in v3:
--
- Patch #4: Minor commit message update
- Patch #5: Replace CONFIG_* with Kconfig options
- Patch #7: Dropped Makefile portion and enabled OF_UPSTREAM for SoC
   instead.
- Patch #1, #3, #6 and #8: Picked up review tags

Changes in v2:
--
- Patch #1: excluded gitab CI config check and added commit description.
- Patch #3: s/UBOOT_DTSI_LOC/u_boot_dtsi_loc/
- Patch #4: s/DEVICE_TREE_LOC/dt_dir/ and s/U-boot/U-Boot/
- Patch #5: s/U-boot/U-Boot/
- Patch #6 and #7: Picked up review tags

Prerequisite


This patch series requires devicetree-rebasing git repo to be added as a
subtree to the main U-Boot repo via:

$ git subtree add --prefix dts/upstream \
   
git://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
 \
   v6.7-dts --squash

Background
--

This effort started while I was reviewing patch series corresponding to
Qcom platforms [1] which was about to import modified devicetree source
files from Linux kernel. I suppose keeping devicetree files sync with
Linux kernel without any DT bindings schema validation has been a pain
for U-Boot SoC/platform maintainers. There has been past discussions
about a single DT repo but that hasn't come up and Linux kernel remained
the place where DT source files as well as bindings are placed and
maintained.

However, Linux kernel DT maintainers proposed [2] for U-Boot to rather
use devicetree-rebasing repo [3] which is a forked copy from Linux
kernel for DT source files as well as bindings. It is tagged at every
Linux kernel major release or intermideate release candidates. So here I
have tried to reuse that to bring DT bingings compliance as well as a
standard way to maintain a regular sync of DT source files with Linux
kernel.

In order to maintain devicetree files sync, U-Boot will maintains a Git
subtree for devicetee-rebasing repo as `dts/upstream` sub-directory.
U-Boot will regularly sync `dts/upstream/` subtree whenever the next window
opens with the next available kernel major release.
`dts/update-dts-subtree.sh` script provides a wrapper around git subtree
pull command, usage from the top level U-Boot source tree, run:

$ ./dts/update-dts-subtree.sh 

The RFC/prototype for this series has been discussed with Linux DT
maintainers as well as U-Boot maintainers here [4]. Now we would like to
reach out to wider U-Boot community to seek feedback.


I very much agree with the direction this is going in, but I do have two 
simple questions:


How do you propose to handle fixes to DTs which are applied to 
linux-stable releases ? For example, if Linux 6.6(.0) ships a DT which 
has some defect that is fixed in 6.6.1, how will that fix get into 
U-Boot DTs ?


Assume that there is some large breaking change in Linux 6.(n+1), 
something which would be problematic for specific U-Boot platform (e.g. 
i.MX) or would require a lot of work to sort out, will there be a way to 
temporarily pin DTs for specific platform to older DT version until that 
is resolved (e.g. pin to 6.n) ?

[PATCH 1/1] acpi: remove duplicate declaration of acpi_fill_header()

[Heinrich Schuchardt]

acpi_fill_header() is declared twice in include/acpi/acpi_table.h

Signed-off-by: Heinrich Schuchardt 
---
 include/acpi/acpi_table.h | 10 --
 1 file changed, 10 deletions(-)

diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index e67562ef654..2e22ce92996 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -828,16 +828,6 @@ void acpi_create_dbg2(struct acpi_dbg2_header *dbg2,
  struct acpi_gen_regaddr *address, uint32_t address_size,
  const char *device_path);
 
-/**
- * acpi_fill_header() - Set up a new table header
- *
- * This sets all fields except length, revision, checksum and aslc_revision
- *
- * @header: ACPI header to update
- * @signature: Table signature to use (4 characters)
- */
-void acpi_fill_header(struct acpi_table_header *header, char *signature);
-
 /**
  * acpi_align() - Align the ACPI output pointer to a 16-byte boundary
  *
-- 
2.43.0

[PATCH 1/1] acpi: document HETP table

[Heinrich Schuchardt]

Document struct acpi_gen_regaddr and struct acpi_hpet.

Sphinx requires that the __packed attribute is at the end of the structure
definitions.

Signed-off-by: Heinrich Schuchardt 
---
 include/acpi/acpi_table.h | 81 ---
 1 file changed, 58 insertions(+), 23 deletions(-)

diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index 8256af6d29e..954e3e95037 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -61,13 +61,37 @@ struct __packed acpi_table_header {
u32 creator_revision;   /* ASL compiler revision number */
 };
 
+/**
+ * struct acpi_gen_regaddr - generic address structure (GAS)
+ */
 struct acpi_gen_regaddr {
-   u8 space_id;/* Address space ID */
-   u8 bit_width;   /* Register size in bits */
-   u8 bit_offset;  /* Register bit offset */
-   u8 access_size; /* Access size */
-   u32 addrl;  /* Register address, low 32 bits */
-   u32 addrh;  /* Register address, high 32 bits */
+   /**
+* @space_id: address space ID
+*
+* See table "Operation Region Address Space Identifiers" in the ACPI
+* specification.
+*/
+   u8 space_id;
+   /** @bit_width: size in bits of the register */
+   u8 bit_width;
+   /** @bit_offset: bit offset of the register */
+   u8 bit_offset;
+   /**
+* @access_size: access size
+*
+* * 0 - undefined
+* * 1 - byte access
+* * 2 - word (2 bytes) access
+* * 3 - Dword (4 bytes) access
+* * 4 - Qword (8 bytes) access
+*
+* See ACPI_ACCESS_SIZE_*_ACCESS macros.
+*/
+   u8 access_size;
+   /** @addrl: register address, low 32 bits */
+   u32 addrl;
+   /** @addrh: register address, high 32 bits */
+   u32 addrh;
 };
 
 /* A maximum number of 32 ACPI tables ought to be enough for now */
@@ -85,15 +109,26 @@ struct __packed acpi_xsdt {
u64 entry[MAX_ACPI_TABLES];
 };
 
-/* HPET timers */
-struct __packed acpi_hpet {
+/**
+ * struct acpi_hpet: High Precision Event Timers (HETP)
+ *
+ * The structure is defined in the
+ * "IA-PC HPET (High Precision Event Timers) Specification", rev 1.0a, Oct 2004
+ */
+struct acpi_hpet {
+   /** @header: table header */
struct acpi_table_header header;
+   /** @id hardware ID of Event Timer Block */
u32 id;
+   /** @addr: address of Event Timer Block */
struct acpi_gen_regaddr addr;
+   /** @number: HPET sequence number */
u8 number;
+   /** @min_tick: minimum clock ticks without lost interrupts */
u16 min_tick;
+   /** @attributes: page protection and OEM atttribute */
u8 attributes;
-};
+} __packed;
 
 struct __packed acpi_tpm2 {
struct acpi_table_header header;
@@ -364,7 +399,7 @@ enum {
  * This holds information about the Generic Interrupt Controller (GIC) CPU
  * interface. See ACPI Spec v6.3 section 5.2.12.14
  */
-struct __packed acpi_madr_gicc {
+struct acpi_madr_gicc {
u8 type;
u8 length;
u16 reserved;
@@ -383,7 +418,7 @@ struct __packed acpi_madr_gicc {
u8 efficiency;
u8 reserved2;
u16 spi_overflow_irq;
-};
+} __packed;
 
 /**
  * struct __packed acpi_madr_gicc - GIC distributor (type 0xc)
@@ -391,7 +426,7 @@ struct __packed acpi_madr_gicc {
  * This holds information about the Generic Interrupt Controller (GIC)
  * Distributor interface. See ACPI Spec v6.3 section 5.2.12.15
  */
-struct __packed acpi_madr_gicd {
+struct acpi_madr_gicd {
u8 type;
u8 length;
u16 reserved;
@@ -400,7 +435,7 @@ struct __packed acpi_madr_gicd {
u32 reserved2;
u8 gic_version;
u8 reserved3[3];
-};
+} __packed;
 
 /* MCFG (PCI Express MMIO config space BAR description table) */
 struct acpi_mcfg {
@@ -653,7 +688,7 @@ struct __packed acpi_spcr {
  *
  * See ACPI Spec v6.3 section 5.2.24 for details
  */
-struct __packed acpi_gtdt {
+struct acpi_gtdt {
struct acpi_table_header header;
u64 cnt_ctrl_base;
u32 reserved0;
@@ -670,7 +705,7 @@ struct __packed acpi_gtdt {
u32 plat_timer_offset;
u32 virt_el2_gsiv;
u32 virt_el2_flags;
-};
+} __packed;
 
 /**
  * struct acpi_bgrt -  Boot Graphics Resource Table (BGRT)
@@ -680,7 +715,7 @@ struct __packed acpi_gtdt {
  *
  * See ACPI Spec v6.3 section 5.2.22 for details
  */
-struct __packed acpi_bgrt {
+struct acpi_bgrt {
struct acpi_table_header header;
u16 version;
u8 status;
@@ -688,7 +723,7 @@ struct __packed acpi_bgrt {
u64 addr;
u32 offset_x;
u32 offset_y;
-};
+} __packed;
 
 /* Types for PPTT */
 #define ACPI_PPTT_TYPE_PROC0
@@ -709,22 +744,22 @@ struct __packed acpi_bgrt {
  *
  * See ACPI Spec v6.3 section 5.2.29 for details
  */
-struct __packed acpi_pptt_header {
+struct acpi_pptt_header {
u8 type;/* ACPI_PPTT_TYPE_... */
u8 

[PATCH 1/1] MAINTAINERS: add include/acpi/ to ACPI

[Heinrich Schuchardt]

Add include/acpi/ to the realm of the ACPI maintainer.

Signed-off-by: Heinrich Schuchardt 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index da477a4e6ad..d8284da0ddb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -55,6 +55,7 @@ M:Simon Glass 
 S: Maintained
 F: board/emulation/configs/acpi.config
 F: cmd/acpi.c
+F: include/acpi/
 F: lib/acpi/
 
 ANDROID AB
-- 
2.43.0

[PATCH 1/1] acpi: rename aslc_id, aslc_revision

[Heinrich Schuchardt]

The fields Creator ID and Creator Revision contain information about the
tool that created an ACPI table. This may be the ASL compiler for some
tables but it is not for others. Naming these fields aslc_id and
aslc_revision is misleading.

It is usual to see diverse values of Creator ID. On a laptop I saw these:
'AMD ', 'INTL, 'MSFT', 'PTEC'. Obviously not all relate to the Intel
ASL compiler.

Signed-off-by: Heinrich Schuchardt 
---
 arch/x86/lib/acpi_nhlt.c  | 2 +-
 arch/x86/lib/acpi_table.c | 8 
 cmd/acpi.c| 2 +-
 include/acpi/acpi_table.h | 6 +++---
 lib/acpi/acpi_table.c | 4 ++--
 lib/acpi/ssdt.c   | 2 +-
 test/dm/acpi.c| 6 +++---
 7 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/arch/x86/lib/acpi_nhlt.c b/arch/x86/lib/acpi_nhlt.c
index 6c8cd83e12d..08e13fdea67 100644
--- a/arch/x86/lib/acpi_nhlt.c
+++ b/arch/x86/lib/acpi_nhlt.c
@@ -409,7 +409,7 @@ int nhlt_serialise_oem_overrides(struct acpi_ctx *ctx, 
struct nhlt *nhlt,
memcpy(header->oem_table_id, oem_table_id, oem_table_id_len);
}
header->oem_revision = oem_revision;
-   memcpy(header->aslc_id, ASLC_ID, 4);
+   memcpy(header->creator_id, ASLC_ID, 4);
 
cur.buf = (void *)(header + 1);
cur.start = (void *)header;
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 5ecd3d4b651..a5683132b01 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -253,7 +253,7 @@ static int acpi_write_tpm2(struct acpi_ctx *ctx,
 
/* Fill out header fields. */
acpi_fill_header(header, "TPM2");
-   memcpy(header->aslc_id, ASLC_ID, 4);
+   memcpy(header->creator_id, ASLC_ID, 4);
 
header->length = sizeof(struct acpi_tpm2);
header->revision = acpi_get_table_revision(ACPITAB_TPM2);
@@ -479,7 +479,7 @@ static int acpi_create_hpet(struct acpi_hpet *hpet)
/* Fill out header fields. */
acpi_fill_header(header, "HPET");
 
-   header->aslc_revision = ASL_REVISION;
+   header->creator_revision = ASL_REVISION;
header->length = sizeof(struct acpi_hpet);
header->revision = acpi_get_table_revision(ACPITAB_HPET);
 
@@ -569,8 +569,8 @@ void acpi_fadt_common(struct acpi_fadt *fadt, struct 
acpi_facs *facs,
header->revision = 4;
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
-   memcpy(header->aslc_id, ASLC_ID, 4);
-   header->aslc_revision = 1;
+   memcpy(header->creator_id, ASLC_ID, 4);
+   header->creator_revision = 1;
 
fadt->x_firmware_ctrl = map_to_sysmem(facs);
fadt->x_dsdt = map_to_sysmem(dsdt);
diff --git a/cmd/acpi.c b/cmd/acpi.c
index 65caaa5c98e..928e5dc525e 100644
--- a/cmd/acpi.c
+++ b/cmd/acpi.c
@@ -32,7 +32,7 @@ static void dump_hdr(struct acpi_table_header *hdr)
if (has_hdr) {
printf("  v%02d %.6s %.8s %x %.4s %x\n", hdr->revision,
   hdr->oem_id, hdr->oem_table_id, hdr->oem_revision,
-  hdr->aslc_id, hdr->aslc_revision);
+  hdr->creator_id, hdr->creator_revision);
} else {
printf("\n");
}
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index e67562ef654..8256af6d29e 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -57,8 +57,8 @@ struct __packed acpi_table_header {
char oem_id[6]; /* OEM identification */
char oem_table_id[8];   /* OEM table identification */
u32 oem_revision;   /* OEM revision number */
-   char aslc_id[4];/* ASL compiler vendor ID */
-   u32 aslc_revision;  /* ASL compiler revision number */
+   char creator_id[4]; /* ASL compiler vendor ID */
+   u32 creator_revision;   /* ASL compiler revision number */
 };
 
 struct acpi_gen_regaddr {
@@ -831,7 +831,7 @@ void acpi_create_dbg2(struct acpi_dbg2_header *dbg2,
 /**
  * acpi_fill_header() - Set up a new table header
  *
- * This sets all fields except length, revision, checksum and aslc_revision
+ * This sets all fields except length, revision, checksum and creator_revision
  *
  * @header: ACPI header to update
  * @signature: Table signature to use (4 characters)
diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c
index 39dd53ec402..c16ead6a6ec 100644
--- a/lib/acpi/acpi_table.c
+++ b/lib/acpi/acpi_table.c
@@ -116,7 +116,7 @@ void acpi_fill_header(struct acpi_table_header *header, 
char *signature)
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
header->oem_revision = OEM_REVISION;
-   memcpy(header->aslc_id, ASLC_ID, 4);
+   memcpy(header->creator_id, ASLC_ID, 4);
 }
 
 void acpi_align(struct acpi_ctx *ctx)
@@ -219,7 +219,7 @@ void acpi_create_dbg2(struct acpi_dbg2_header *dbg2,
 
header->revision = acpi_get_table_revision(ACPITAB_DBG2);
acpi_fill_header(header, 

[PATCH v1] sunxi: R528: add UART1 support

[Maksim Kiselev]

Add PG6-PG7 pins configuration for the SPL to allow use UART1
on boards with the Allwinner R528/T113 family.

Signed-off-by: Maksim Kiselev 
---

I tested this patch on LC-PI-T113 board.
This board can be found on eBay or Aliexpress, and looks like
that it is widespread enough to send this patch to the upstream :)


 arch/arm/mach-sunxi/board.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 11a4941822..9dedcd45f5 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -159,6 +159,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I_R528)
+   sunxi_gpio_set_cfgpin(SUNXI_GPG(6), 2);
+   sunxi_gpio_set_cfgpin(SUNXI_GPG(7), 2);
+   sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I_H3)
sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_H3_GPA_UART2);
sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_H3_GPA_UART2);
-- 
2.40.1

Pull request efi-2024-04-rc1-3

[Heinrich Schuchardt]

Dear Tom,

The following changes since commit 3c04fcf3137d5f694d52b8f355373e4baabe5f78:

  Merge patch series "k3-j721e: beagleboneai: Fix USB" (2024-01-20
11:39:13 -0500)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-efi.git
tags/efi-2024-04-rc1-3

for you to fetch changes up to 2c98f7435cc5edb2a0b96e9f398c0b7f084e83cd:

  efi_loader: return immediately in UCLASS_EFI_LOADER removal
(2024-01-21 11:24:24 +0100)

Gitlab CI showed no issues:
https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/19394


Pull request efi-2024-04-rc1-3

Documentation:

* correct documentation of part_get_bootable()
* remove duplicate word "has" in UEFI documentation

UEFI:

* rename check_disk_has_default_file function
* auto-generate boot option for each blkio device
* auto-generate removable media boot option first
* avoid pointer access after calling efi_delete_handle
* create common function to free struct efi_disk_obj
* return immediately in UCLASS_EFI_LOADER removal


Heinrich Schuchardt (1):
  part: correct documentation of part_get_bootable()

Masahisa Kojima (6):
  efi_loader: rename check_disk_has_default_file function
  efi_loader: auto-generate boot option for each blkio device
  efi_loader: auto-generate removable media boot option first
  efi_loader: avoid pointer access after calling efi_delete_handle
  efi_loader: create common function to free struct efi_disk_obj
  efi_loader: return immediately in UCLASS_EFI_LOADER removal

Wei Ming Chen (1):
  doc: uefi: remove duplicate word "has"

 doc/develop/uefi/uefi.rst|   2 +-
 include/part.h   |   4 +-
 lib/efi_loader/efi_bootmgr.c | 141
---
 lib/efi_loader/efi_disk.c|  52 +++-
 4 files changed, 147 insertions(+), 52 deletions(-)

Re: [PATCH] doc: uefi: remove duplicate word "has"

[Heinrich Schuchardt]

On 1/19/24 02:34, Wei Ming Chen wrote:

There should be only one "has" instead of "has has"

Signed-off-by: Wei Ming Chen 


Reviewed-by: Heinrich Schuchardt