[PATCH 1/2] spl: Make SPL_STACK available for ROCKCHIP_RK3036 without spl framework
rk3036 soc has limit internal sram, and not able to support spl framework. Signed-off-by: Kever Yang --- common/spl/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index e7b84fc1fa6..9deee0fdbea 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -372,7 +372,8 @@ config SPL_SHARES_INIT_SP_ADDR config SPL_STACK hex "Initial stack pointer location" - depends on (ARM || ARCH_JZ47XX || MICROBLAZE || RISCV) && SPL_FRAMEWORK + depends on (ARM || ARCH_JZ47XX || MICROBLAZE || RISCV) && \ + SPL_FRAMEWORK || ROCKCHIP_RK3036 depends on !SPL_SHARES_INIT_SP_ADDR default 0x946bb8 if ARCH_MX7 default 0x93ffb8 if ARCH_MX6 && MX6_OCRAM_256KB -- 2.25.1
[PATCH 2/2] configs: rockchip: rk3036: Fix CONFIG_SPL_STACK define
The CONFIG_SPL_STACK for rk3036 is removed in below patch, need to add
it back.
Fixes: f113d7d3034 ("Convert CONFIG_SPL_STACK to Kconfig")
Signed-off-by: Kever Yang
---
configs/evb-rk3036_defconfig | 1 +
configs/kylin-rk3036_defconfig | 1 +
2 files changed, 2 insertions(+)
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 21c657a441c..df6aaa97a0c 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -15,6 +15,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
CONFIG_SPL_TEXT_BASE=0x10081000
CONFIG_ROCKCHIP_RK3036=y
CONFIG_SPL_STACK_R_ADDR=0x8
+CONFIG_SPL_STACK=0x10081fff
CONFIG_DEBUG_UART_BASE=0x20068000
CONFIG_DEBUG_UART_CLOCK=2400
CONFIG_SYS_LOAD_ADDR=0x60800800
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 8d3f1a7b098..17360c552c7 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -17,6 +17,7 @@ CONFIG_SPL_TEXT_BASE=0x10081000
CONFIG_ROCKCHIP_RK3036=y
CONFIG_TARGET_KYLIN_RK3036=y
CONFIG_SPL_STACK_R_ADDR=0x8
+CONFIG_SPL_STACK=0x10081fff
CONFIG_DEBUG_UART_BASE=0x20068000
CONFIG_DEBUG_UART_CLOCK=2400
CONFIG_SYS_LOAD_ADDR=0x60800800
--
2.25.1
Re: [PATCH 01/20] Convert CONFIG_SPL_STACK to Kconfig
Hi Tom, On 2024/1/24 09:34, Tom Rini wrote: On Wed, Jan 24, 2024 at 09:15:07AM +0800, Kever Yang wrote: Hi Tom, On 2024/1/24 01:58, Tom Rini wrote: On Tue, Jan 23, 2024 at 11:53:18AM +0800, Kever Yang wrote: Hi Tom, rk3036 only has small size internal sram, so it can only use very simple SPL which only including dram init, and no SPL_FRAMEWORK support. In this convert, the CONFIG_SPL_STACK is lost for this SoC, any suggestions on this kind of issue? Does this work? diff --git a/common/spl/Kconfig b/common/spl/Kconfig index e7b84fc1fa68..9deee0fdbea8 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -372,7 +372,8 @@ config SPL_SHARES_INIT_SP_ADDR config SPL_STACK hex "Initial stack pointer location" - depends on (ARM || ARCH_JZ47XX || MICROBLAZE || RISCV) && SPL_FRAMEWORK + depends on (ARM || ARCH_JZ47XX || MICROBLAZE || RISCV) && \ + SPL_FRAMEWORK || ROCKCHIP_RK3036 This works with adding CONFIG_SPL_STACK in rk3036 board defconfig. depends on !SPL_SHARES_INIT_SP_ADDR default 0x946bb8 if ARCH_MX7 default 0x93ffb8 if ARCH_MX6 && MX6_OCRAM_256KB You will have to update the ROCKCHIP_RK3036 platforms otherwise the build will hang now. What do you mean to update the platform? The rk3036 case should be one of the available option for those "small"/low end SoCs has very limit size of internal dram, only need minimal SPL+ U-Boot, and no requirement for ATF/OPTEEwhich will have to use TPL+SPL+U-Boot. The CONFIG_SPL_STACK is used in assemble init code, it doesn't need to depends on SPL_FRAMEWORK, isn't it? I just mean that with the above Kconfig change, all RK3036 platforms must set a value for CONFIG_SPL_STACK at the same time, or they will fail to build (and CI will get hung). It doesn't hang because the build goes to another branch which not defined CONFIG_SPL_STACK, the board get panic when it run the firmware. It sounds like all RK3036 platforms need to set the value in order to work, Yes, this is correct. The init code doesn't define a correct SP, that should be a bug. Thanks, - Kever so this isn't a bug, just a feature. Is that clearer?
[PATCH] doc: dm: Fix typo
That's most probably a typo, because driver model design documents seem
to be from 2012 and there is no 2010.01 release.
Fixes: 282ed24fb3ca ("dm: MIGRATION: Add migration plan for CONFIG_DM")
Signed-off-by: Alexander Dahl
---
Notes:
This was still in an old local branch of my working copy, but it applies
cleanly to master so I guess it is still valid?! ;-)
doc/develop/driver-model/migration.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/doc/develop/driver-model/migration.rst
b/doc/develop/driver-model/migration.rst
index 03fea943b29..b40a6af9d11 100644
--- a/doc/develop/driver-model/migration.rst
+++ b/doc/develop/driver-model/migration.rst
@@ -13,7 +13,7 @@ CONFIG_DM
* Status: In progress
* Deadline: 2020.01
-Starting with the 2010.01 release CONFIG_DM will be enabled for all boards.
+Starting with the 2020.01 release CONFIG_DM will be enabled for all boards.
This does not concern CONFIG_DM_SPL and CONFIG_DM_TPL. The conversion date for
these configuration items still needs to be defined.
base-commit: 15e7927b5a2d33666af19879577bf0c30ab088fe
--
2.39.2
Re: [PATCH v4 00/11] An effort to bring DT bindings compliance within U-Boot
On Mon, 22 Jan 2024 at 05:31, Tom Rini wrote: > > On Sun, Jan 21, 2024 at 10:41:51PM +, Caleb Connolly wrote: > > > > > > On 21/01/2024 15:33, Marek Vasut wrote: > [snip] > > > Assume that there is some large breaking change in Linux 6.(n+1), > > > something which would be problematic for specific U-Boot platform (e.g. > > > i.MX) or would require a lot of work to sort out, will there be a way to > > > temporarily pin DTs for specific platform to older DT version until that > > > is resolved (e.g. pin to 6.n) ? > > > > (Upstream) devicetree has to be forwards and backwards compatible, were such > > a breaking change to get merged without prior discussion with DT users (i.e. > > U-Boot) then I think the correct course of action would be to revert it. > > The caveat is "unless it was wrong before", which happens more often > than is generally thought of I think. I'm not sure off-hand the best way > to deal with that. I think that's the reason we just want to pull DT at once in the beginning of the next window and allow U-Boot developers/maintainers to detect and fix problems during the full U-Boot release cycle. However, we are open to discussions for a revert if there is a major DT ABI break among Linux major (.0) releases affecting many U-Boot platforms. -Sumit > > -- > Tom
[PATCH 2/2] doc: k3: update documentation for uEnv.txt
Add the information for the save_uenv command and refactor the
documentation to remove the eMMC information that was wrong.
Signed-off-by: Manorit Chawdhry
---
doc/board/ti/k3.rst | 24 ++--
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst
index 7dfe39c5fa57..e95779e32566 100644
--- a/doc/board/ti/k3.rst
+++ b/doc/board/ti/k3.rst
@@ -594,20 +594,21 @@ Refer (:ref:`U-boot ARMV8 build
`)
Saving environment
--
-SAVEENV is disabled by default and for the new flow uses Uenv.txt as the
default
-way for saving the environments. This has been done as Uenv.txt is more
granular
-then the saveenv command and can be used across various bootmodes too.
+CONFIG_CMD_SAVEENV is disabled by default and for the new flow uses
+uEnv.txt as the default way for saving the environments. This has been done
+as uEnv.txt is more granular then the saveenv command and can be used
+across various bootmodes too.
-**Writing to MMC/EMMC**
+**Writing to MMC**
.. prompt:: bash =>
- env export -t $loadaddr
- fatwrite mmc ${mmcdev} ${loadaddr} ${bootenvfile} ${filesize}
+ setenv save_to_env
+ run save_uenv
-**Reading from MMC/EMMC**
+**Reading from MMC**
-By default run envboot will read it from the MMC/EMMC partition ( based on
+By default run envboot will read it from the MMC partition ( based on
mmcdev) and set the environments.
If manually needs to be done then the environment can be read from the
@@ -615,8 +616,11 @@ filesystem and then imported
.. prompt:: bash =>
- fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}
- env import -t ${loadaddr} ${filesize}
+ run envboot
+
+To read from eMMC, the save_uenv and envboot commands would need to be
+changed to pickup the bootenvfile from eMMC. Mainly the write and read
+commands would change to eMMC.
.. _k3_rst_refer_openocd:
--
2.43.0
[PATCH 1/2] env: ti: mmc: add save_uenv command
This is to make easier development with uEnv.txt to update from the
board on the fly from u-boot to MMC boot media.
Signed-off-by: Manorit Chawdhry
---
include/env/ti/mmc.env | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/env/ti/mmc.env b/include/env/ti/mmc.env
index 0256a2d2aaca..886e4cab36fe 100644
--- a/include/env/ti/mmc.env
+++ b/include/env/ti/mmc.env
@@ -34,6 +34,9 @@ envboot=if mmc dev ${mmcdev}; then
fi;
fi;
fi;
+save_uenv=
+ env export -t $loadaddr $save_to_env save_to_env;
+ fatwrite mmc ${mmcdev} ${loadaddr} ${bootenvfile} ${filesize};
mmcloados=
if test ${boot_fdt} = yes || test ${boot_fdt} = try; then
if run get_fdt_mmc; then
--
2.43.0
[PATCH 0/2] Add save_uenv command
Adding this command for easier development to update uEnv.txt from u-boot on the u-boot prompt and track the variables being updated in uEnv.txt as well. Signed-off-by: Manorit Chawdhry --- Manorit Chawdhry (2): env: ti: mmc: add save_uenv command doc: k3: update documentation for uEnv.txt doc/board/ti/k3.rst| 24 ++-- include/env/ti/mmc.env | 3 +++ 2 files changed, 17 insertions(+), 10 deletions(-) --- base-commit: f28a77589e7505535a4eebdc7269df98f67dbe68 change-id: 20240124-b4-upstream-save_uenv-1784463fe4da Best regards, -- Manorit Chawdhry
Re: [PATCH 02/16] xilinx_mbv: Remove empty config header
On 1/23/24 18:58, Tom Rini wrote: On Tue, Jan 23, 2024 at 08:53:21AM +0100, Michal Simek wrote: On 1/22/24 23:39, Tom Rini wrote: Now that we support having CONFIG_SYS_CONFIG_NAME be unset to indicate a lack of board.h file, unset this on the xilinx_mbv platforms and remove the otherwise empty file. Signed-off-by: Tom Rini --- Cc: Michal Simek --- board/xilinx/mbv/Kconfig | 3 --- board/xilinx/mbv/MAINTAINERS | 1 - include/configs/xilinx_mbv.h | 6 -- 3 files changed, 10 deletions(-) delete mode 100644 include/configs/xilinx_mbv.h diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig index 4bc9f72c541b..d2dec397ed6f 100644 --- a/board/xilinx/mbv/Kconfig +++ b/board/xilinx/mbv/Kconfig @@ -9,9 +9,6 @@ config SYS_VENDOR config SYS_CPU default "generic" -config SYS_CONFIG_NAME - default "xilinx_mbv" - config TEXT_BASE default 0x8000 if !RISCV_SMODE default 0x8040 if RISCV_SMODE && ARCH_RV32I diff --git a/board/xilinx/mbv/MAINTAINERS b/board/xilinx/mbv/MAINTAINERS index 445654fe740e..db9f03388df9 100644 --- a/board/xilinx/mbv/MAINTAINERS +++ b/board/xilinx/mbv/MAINTAINERS @@ -4,4 +4,3 @@ S: Maintained F: arch/riscv/dts/xilinx-mbv* F: board/xilinx/mbv/ F: configs/xilinx_mbv* -F: include/configs/xilinx_mbv.h diff --git a/include/configs/xilinx_mbv.h b/include/configs/xilinx_mbv.h deleted file mode 100644 index dba398aeec49.. --- a/include/configs/xilinx_mbv.h +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2023, Advanced Micro Devices, Inc. - * - * Michal Simek - */ Acked-by: Michal Simek But maybe in future we need to revert this patch to add more options there. Or do you plan to remove all of these configs? I can imagine distro boot wiring but that can be done via vars file only but it is not practical. Do you mean that plain text environment feels impractical for standard boot (which should be used instead of the pure scripts of distro_boot) ? I didn't play with standard boot yet to find out how to prioritize certain devices at run time. But normally we are trying to keep all amd platforms in sync to make sure that from user perspective doesn't really matter if you are on microblaze, arm32, arm64 or risc-v based platform. There are still a lot of configs like GUIDs, dfu and others that I don't think we will end up without these config files anytime soon. But it doesn't mean we shouldn't aim for it. Thanks, Michal
Re: [PATCH v4 00/11] An effort to bring DT bindings compliance within U-Boot
Hi Nishanth, Apologies for the delayed response as I was on a long weekend vacation. On Fri, 19 Jan 2024 at 21:27, Nishanth Menon wrote: > > On 16:05-20240110, Sumit Garg wrote: > [...] > > Prerequisite > > > > > > This patch series requires devicetree-rebasing git repo to be added as a > > subtree to the main U-Boot repo via: > > > > $ git subtree add --prefix dts/upstream \ > > > > git://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git > > \ > > Please use https:// Okay I can do that given the widespread use of https:// > > also what is the baseline? didn't seem to apply on (fails at patch #2): > next f28a77589e75 Merge tag 'dm-next-7jan23' of > https://source.denx.de/u-boot/custodians/u-boot-dm into next > master f7cca7ccc511 Revert "test: hush: dollar: fix bugous behavior" Okay looks like recent merges caused conflicts, needs a rebase. However, for v4 you can use this branch [1] for testing. [1] https://github.com/b49020/u-boot/tree/v4_dt -Sumit > > -- > Regards, > Nishanth Menon > Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 > 849D 1736 249D
Re: [PATCH 2/4] doc: Document capsule generation through a config file
hi Ilias,
On Tue, 23 Jan 2024 at 21:53, Ilias Apalodimas
wrote:
>
> Hi Sughosh,
>
> On Tue, Nov 21, 2023 at 12:30:26PM +0530, Sughosh Ganu wrote:
> > The UEFI capsule can now be generate by specifying the capsule
> > parameters through a config file. Additionally, the capsules can be
> > generated as part of u-boot build, through binman. Highlight these
> > changes in the documentation.
> >
> > Signed-off-by: Sughosh Ganu
> > ---
> > doc/develop/uefi/uefi.rst | 70 +++
> > 1 file changed, 70 insertions(+)
> >
> > diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst
> > index fb16ac743a..b9a9ed5491 100644
> > --- a/doc/develop/uefi/uefi.rst
> > +++ b/doc/develop/uefi/uefi.rst
> > @@ -318,6 +318,76 @@ Run the following command
> >--guid \
> >
> >
> > +Alternatively, the capsules can be generated through a config
> > +file. When generating the capsules through a config file, the Kconfig
> > +symbol CONFIG_EFI_CAPSULE_CFG_FILE is to be used for specifying the
> > +path to the config file.
>
> This sounds a bit weird. The tool is compiled and used by distros. How are
> they supposed to use the config file?
>
> Briefly looking at the patches, we use those config options on testing.
> Can't we add a flag in the tool itself that can be used for normal use
> cases and limit those Kconfig flags in our testing only? Or alternatively
> the paths for the config files can be hardcoded for sandbox and we get rid
> of the config options entirely?
It is correct that the Kconfig symbol is used primarily for testing.
We can indeed use a fixed path for the sandbox based testing. That is
the approach that was taken for the public keys used for capsule
authentication. Will make changes to the patches accordingly. Thanks.
-sughosh
>
> Thanks
> /Ilias
> > +
> > +The config file describes the parameters that are used for generating
> > +one or more capsules. The parameters for a given capsule file are
> > +specified within curly braces, in the form of "key:value" pairs. All
> > +the parameters that are currently supported by the mkeficapsule tool
> > +can be specified through the config file.
> > +
> > +The following are some example payload parameters specified through
> > +the config file.
> > +
> > +.. code-block:: none
> > +
> > + {
> > + image-guid: 02f4d760-cfd5-43bd-8e2d-a42acb33c660
> > + hardware-instance: 0
> > + monotonic-count: 1
> > + payload: u-boot.bin
> > + image-index: 1
> > + fw-version: 2
> > + private-key: /path/to/priv/key
> > + pub-key-cert: /path/to/pub/key
> > + capsule: u-boot.capsule
> > + }
> > + {
> > + image-guid: 4ce292da-1dd8-428d-a1c2-77743ef8b96e
> > + hardware-instance: 0
> > + payload: u-boot.itb
> > + image-index: 2
> > + fw-version: 7
> > + oemflags: 0x8000
> > + capsule: fit.capsule
> > + }
> > + {
> > + capsule-type: accept
> > + image-guid: 4ce292da-1dd8-428d-a1c2-77743ef8b96e
> > + capsule: accept.capsule
> > + }
> > + {
> > + capsule-type: revert
> > + capsule: revert.capsule
> > + }
> > +
> > +The following are the keys that specify the capsule parameters
> > +
> > +..code-block:: none
> > +
> > +image-guid: Image GUID
> > +image-index: Image index value
> > +fw-version: Image version
> > +private-key: Path to the private key file used for capsule signing
> > +pub-key-cert: Path to the public key crt file used for capsule signing
> > +payload: Path to the capsule payload file
> > +capsule: Path to the output capsule file that is generated
> > +hardware-instance: Hardware Instance value
> > +monotonic-count: Monotonic count value
> > +capsule-type: Specifies capsule type. normal(default), accept or revert
> > +oemflags: 16bit Oemflags value to be used(populated in capsule header)
> > +
> > +When generating capsules through a config file, the command would look
> > +like
> > +
> > +.. code-block:: console
> > +
> > +$ mkeficapsule --cfg-file
> > +
> > +
> > Capsule with firmware version
> > *
> >
> > --
> > 2.34.1
> >
[PATCH V4 2/2] configs: andes: add watchdog support fot andes ae350
It adds the ATCWDT200 support for Andes AE350 platform. It also enables wdt command support. Signed-off-by: CL Wang Signed-off-by: Randolph Reviewed-by: Leo Yu-Chi Liang --- configs/ae350_rv32_defconfig | 4 configs/ae350_rv32_spl_defconfig | 4 configs/ae350_rv32_spl_xip_defconfig | 4 configs/ae350_rv32_xip_defconfig | 4 configs/ae350_rv64_defconfig | 4 configs/ae350_rv64_spl_defconfig | 4 configs/ae350_rv64_spl_xip_defconfig | 4 configs/ae350_rv64_xip_defconfig | 4 8 files changed, 32 insertions(+) diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 3bfa3e9f8e..35ad62c845 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -49,3 +50,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index aeb50206d2..41cd457bc3 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -58,3 +59,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index f15ec301ce..954e2f2de7 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -34,6 +34,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -59,3 +60,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index c40eb043c5..95863595d2 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -24,6 +24,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -50,3 +51,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index 7ae938aeb2..988214285a 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -49,3 +50,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 68ac4325ab..e929320433 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -58,3 +59,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 839ca335d4..3f92643b07 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -34,6 +34,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -59,3 +60,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index 5432b6d6d7..835f020990 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -24,6 +24,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y
[PATCH V4 1/2] drivers: watchdog: add andes atcwdt200 support
This patch adds an implementation of the Andes watchdog ATCWDT200 driver.
Signed-off-by: CL Wang
Signed-off-by: Randolph
Reviewed-by: Leo Yu-Chi Liang
---
drivers/watchdog/Kconfig | 6 +
drivers/watchdog/Makefile| 1 +
drivers/watchdog/atcwdt200_wdt.c | 220 +++
3 files changed, 227 insertions(+)
create mode 100644 drivers/watchdog/atcwdt200_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 569726119c..8318fd77a3 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -130,6 +130,12 @@ config WDT_AT91
Select this to enable Microchip watchdog timer, which can be found on
some AT91 devices.
+config WDT_ATCWDT200
+ bool "Andes watchdog timer support"
+ depends on WDT
+ help
+ Select this to enable Andes ATCWDT200 watchdog timer
+
config WDT_BCM6345
bool "BCM6345 watchdog timer support"
depends on WDT && (ARCH_BMIPS || BCM6856 || \
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 5520d3d9ae..7b39adcf0f 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_WDT_ARM_SMC) += arm_smc_wdt.o
obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o
obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o
+obj-$(CONFIG_WDT_ATCWDT200) += atcwdt200_wdt.o
obj-$(CONFIG_WDT_BCM2835) += bcm2835_wdt.o
obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o
diff --git a/drivers/watchdog/atcwdt200_wdt.c b/drivers/watchdog/atcwdt200_wdt.c
new file mode 100644
index 00..a29b42d607
--- /dev/null
+++ b/drivers/watchdog/atcwdt200_wdt.c
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Andes Technology Corporation.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define NODE_NOT_FOUND 0x
+
+#define WDT_WP_MAGIC 0x5aa5
+#define WDT_RESTART_MAGIC 0xcafe
+
+/* Control Register */
+#define REG_WDT_ID 0x00
+#define REG_WDT_CFG0x10
+#define REG_WDT_RS 0x14
+#define REG_WDT_WE 0x18
+#define REG_WDT_STA0x1C
+
+#define RST_TIME_OFF 8
+#define RST_TIME_MSK (0x7 << RST_TIME_OFF)
+#define RST_CLK_128(0 << RST_TIME_OFF)
+#define RST_CLK_256(1 << RST_TIME_OFF)
+#define RST_CLK_512(2 << RST_TIME_OFF)
+#define RST_CLK_1024 (3 << RST_TIME_OFF)
+#define INT_TIME_OFF 4
+#define INT_TIME_MSK (0xf << INT_TIME_OFF)
+#define INT_CLK_2_6(0 << INT_TIME_OFF) /* clk period*2^6 */
+#define INT_CLK_2_8(1 << INT_TIME_OFF) /* clk period*2^8 */
+#define INT_CLK_2_10 (2 << INT_TIME_OFF) /* clk period*2^10 */
+#define INT_CLK_2_11 (3 << INT_TIME_OFF) /* clk period*2^11 */
+#define INT_CLK_2_12 (4 << INT_TIME_OFF) /* clk period*2^12 */
+#define INT_CLK_2_13 (5 << INT_TIME_OFF) /* clk period*2^13 */
+#define INT_CLK_2_14 (6 << INT_TIME_OFF) /* clk period*2^14 */
+#define INT_CLK_2_15 (7 << INT_TIME_OFF) /* clk period*2^15 */
+#define INT_CLK_2_17 (8 << INT_TIME_OFF) /* clk period*2^17 */
+#define INT_CLK_2_19 (9 << INT_TIME_OFF) /* clk period*2^19 */
+#define INT_CLK_2_21 (10 << INT_TIME_OFF) /* clk period*2^21 */
+#define INT_CLK_2_23 (11 << INT_TIME_OFF) /* clk period*2^23 */
+#define INT_CLK_2_25 (12 << INT_TIME_OFF) /* clk period*2^25 */
+#define INT_CLK_2_27 (13 << INT_TIME_OFF) /* clk period*2^27 */
+#define INT_CLK_2_29 (14 << INT_TIME_OFF) /* clk period*2^29 */
+#define INT_CLK_2_31 (15 << INT_TIME_OFF) /* clk period*2^31 */
+#define INT_CLK_MIN0x0
+#define INT_CLK_MAX_16B0x7
+#define INT_CLK_MAX_32B0xF
+#define RST_EN BIT(3)
+#define INT_EN BIT(2)
+#define CLK_PCLK BIT(1)
+#define WDT_EN BIT(0)
+#define INT_EXPIREDBIT(0)
+
+#define INT_TIME_ARRAY 16
+#define RST_TIME_ARRAY 8
+
+struct wdt_priv {
+ void __iomem *base;
+ u32 wdt_clk_src;
+ u32 clk_freq;
+ u8 max_clk;
+};
+
+static inline u8 atcwdt_get_2_power_of_n(u8 index, u8 type)
+{
+ const u8 div_int[INT_TIME_ARRAY] = {6, 8, 10, 11, 12, 13, 14, 15,
+ 17, 19, 21, 23, 25, 27, 29, 31};
+ const u8 div_rst[RST_TIME_ARRAY] = {7, 8, 9, 10, 11, 12, 13, 14};
+ const u8 *pdiv;
+
+ if (type == RST_TIME_ARRAY)
+ pdiv = div_rst;
+ else
+ pdiv = div_int;
+
+ if (index >= type)
+ index = type - 1;
+
+ return pdiv[index];
+}
+
+static u8 atcwdt_search_msb(u64 freq_ms, u8 type)
+{
+ u64 result;
+ u64 freq_sec;
+ u8 index;
+
+ freq_sec = freq_ms / 1000;
+ for (index = 0; index < type; index++) {
+ result = freq_sec >> atcwdt_get_2_power_of_n(index, type);
+
+ if (result <= 1)
+
Re: [PATCH 0/4] Facilitate new atmel raw nand driver for SAMA5D2
On 12/12/23 18:04, Alexander Dahl wrote:
> Hei hei,
>
> for some downstream boards with SAMA5D27 SiP SoCs with raw NAND flash I
> added the necessary nodes to sama5d2.dtsi with just one little
> guesswork: the clocks. Motivation was to fix reading from raw nand
> flash which failed on some of those boards, while others worked fine.
> So I suppose the timings for the external interface were set to too slow
> values. (IIRC I took them from the sama5d2_ptc_ek_nandflash board code
> back in 2019.)
>
> The solution was basically to switch from the old non-DM driver with
> hardcoded timings for the external memory interface to the new DM based
> driver introduced earlier this year, which sets the timings based on
> ONFI parameters read from the flash chip.
>
> Works for me, but I have no boards with that SoC _and_ a raw NAND flash
> at hand, which are supported by upstream U-Boot. The only matching
> upstream config is sama5d2_ptc_ek_nandflash_defconfig but because we
> don't have that board, I did not touch it.
>
> (When that driver was added with 6a8dfd57220d ("nand: atmel: Add DM
> based NAND driver") the author claims in the commit message it was
> tested on SAMA5D3, but none of the sama5d3 configs actually uses it.)
>
> Some more changes to the board dts are necessary, but porting from Linux
> is straightforward. The necessary changes to the defconfig should look
> like this:
>
> # CONFIG_I2C is not set
> CONFIG_LED=y
> CONFIG_LED_GPIO=y
> +CONFIG_ATMEL_EBI=y
> +CONFIG_MFD_ATMEL_SMC=y
> # CONFIG_MMC is not set
> CONFIG_MTD=y
> -CONFIG_NAND_ATMEL=y
> -CONFIG_ATMEL_NAND_HW_PMECC=y
> -CONFIG_PMECC_CAP=8
> +CONFIG_DM_MTD=y
> +CONFIG_DM_NAND_ATMEL=y
> CONFIG_SYS_NAND_ONFI_DETECTION=y
> CONFIG_PHY_SMSC=y
> CONFIG_MACB=y
>
> Hope the changes are acceptable nevertheless. The last patch has a
> trivial fix for the new atmel raw nand driver which I came up with while
> working on this.
>
> Greets
> Alex
>
> Cc: Eugen Hristev
> Cc: Dario Binacchi
> Cc: Michael Trimarchi
> Cc: Wenyou Yang
> Cc: Balamanikandan Gunasundar
>
> Alexander Dahl (4):
> ARM: dts: at91: sama5d2: Move sfr node
> ARM: dts: at91: sama5d2: Port ebi/nand nodes from linux
> ARM: dts: at91: sama5d2: Align more node names with Linux
> mtd: nand: raw: atmel: Remove duplicate definitions
>
> arch/arm/dts/sama5d2.dtsi | 74 ++
> drivers/mtd/nand/raw/atmel/pmecc.c | 3 --
> 2 files changed, 65 insertions(+), 12 deletions(-)
>
>
> base-commit: 2f0282922b2c458eea7f85c500a948a587437b63
Applied series to u-boot-at91/master, thanks !
Re: [PATCH 4/4] mtd: nand: raw: atmel: Remove duplicate definitions
On 12/19/23 18:39, Alexander Dahl wrote:
> Hello Eugen,
>
> Am Tue, Dec 19, 2023 at 04:32:07PM +0200 schrieb Eugen Hristev:
>> On 12/12/23 18:04, Alexander Dahl wrote:
>>> These removed definitions were specific to some sam9 SoCs, but not
>>> generic over all at91 SoCs. The correct SoC specific definitions for
>>> ATMEL_BASE_PMECC are spread over different header files in
>>> arch/arm/mach-at91/include/mach directory.
>>>
>>> Fixes a build error on a custon board based on SAMA5D2:
>>>
>>> Building current source for 73 boards (16 threads, 1 job per thread)
>>>arm: + vera2
>>> +drivers/mtd/nand/raw/atmel/pmecc.c:819: warning: "ATMEL_BASE_PMECC"
>>> redefined
>>> + 819 | #define ATMEL_BASE_PMECC0xe000
>>> + |
>>> +In file included from include/configs/vera2.h:11,
>>> + from include/config.h:3,
>>> + from include/linux/mtd/rawnand.h:16,
>>> + from drivers/mtd/nand/raw/atmel/pmecc.c:44:
>>> +include/asm/arch/sama5d2.h:171: note: this is the location of the
>>> previous definition
>>> + 171 | #define ATMEL_BASE_PMECC(ATMEL_BASE_HSMC + 0x70)
>>> +drivers/mtd/nand/raw/atmel/pmecc.c:820: warning: "ATMEL_BASE_PMERRLOC"
>>> redefined
>>> + 820 | #define ATMEL_BASE_PMERRLOC 0xe600
>>> +include/asm/arch/sama5d2.h:172: note: this is the location of the
>>> previous definition
>>> + 172 | #define ATMEL_BASE_PMERRLOC (ATMEL_BASE_HSMC + 0x500)
>>>
>>> Fixes: a490e1b7c017 ("nand: atmel: Add pmecc driver")
>>> Signed-off-by: Alexander Dahl
>>> ---
>>> drivers/mtd/nand/raw/atmel/pmecc.c | 3 ---
>>> 1 file changed, 3 deletions(-)
>>>
>>> diff --git a/drivers/mtd/nand/raw/atmel/pmecc.c
>>> b/drivers/mtd/nand/raw/atmel/pmecc.c
>>> index e2e3f1ee6b5..51f6bd2e65b 100644
>>> --- a/drivers/mtd/nand/raw/atmel/pmecc.c
>>> +++ b/drivers/mtd/nand/raw/atmel/pmecc.c
>>> @@ -816,9 +816,6 @@ int atmel_pmecc_wait_rdy(struct atmel_pmecc_user *user)
>>> }
>>> EXPORT_SYMBOL_GPL(atmel_pmecc_wait_rdy);
>>>
>>> -#define ATMEL_BASE_PMECC 0xe000
>>> -#define ATMEL_BASE_PMERRLOC0xe600
>>> -
>>> static struct atmel_pmecc *
>>> atmel_pmecc_create(struct udevice *dev,
>>>const struct atmel_pmecc_caps *caps,
>>
>>
>> Hi Alexander,
>>
>> What happens if we try to select and build this driver without
>> sama5d2/sama5d3/sama5d4/sam9x5/sam9x60 ?
>> Is it even possible ?
>
> It is not possible on non-at91 boards because is
> included so you need to select arch at91. But it is possible on older
> sam9 boards like sam9260, sam9g20 and the like. Tried that by using
> at91sam9g20ek_nandflash_defconfig as a base, then disabling
> CONFIG_NAND_ATMEL, then enabling CONFIG_DM_NAND_ATMEL (which activates
> build of drivers/mtd/nand/raw/atmel/pmecc.c), then enabling some more
> missing dependencies (CONFIG_MFD_ATMEL_SMC, CONFIG_REGMAP,
> CONFIG_SYSCON) and then it builds just fine.
>
> (btw: should those be selected or implied by CONFIG_DM_NAND_ATMEL in
> 'drivers/mtd/nand/raw/Kconfig' then in another patch or is this stuff
> rather loose coupled?)
Hi Alexander,
I tried to look around the drivers and the symbols, but it appears enabling any
sort of driver makes things stop building, as the dependencies are not at all
stated correctly.
Thus, I cannot really answer that.
About this modification in particular, I ran the CI loop, it appears to be fine,
and I agree with the duplication, I was a bit reluctant to not break old
platforms,
but since the CI says it's fine... I applied your set to u-boot-at91/master .
Eugen
>
>> Because it appears these defines are done for those SoCs in their
>> mach header, but the driver uses them in any situation.
>
> I don't think so. There are two drivers, the old one is
> 'drivers/mtd/nand/raw/atmel_nand.c' selected by CONFIG_NAND_ATMEL
> while the new one is 'drivers/mtd/nand/raw/atmel/nand-controller.c'
> selected by CONFIG_DM_NAND_ATMEL (note the extra sub-directory). Only
> the new one leads to building the file in question. The symbols
> removed from pmecc.c are not used in pmecc.c but only in the old
> driver. The scope of those removed symbols would have been in pmecc.c
> only however, they are pointless at the place where they are currently
> defined. (Unless someone would #include that .c file, but that
> seems rather unusual.)
>
> And the part where the symbols of the same name are used is
> conditionally built only if CONFIG_ATMEL_NAND_HW_PMECC is set. From a
> quick glance I would say that one is set only for newer boards, those
> families you mentioned below. But as said, all this is for the old
> driver.
>
>> And currently, these warnings are being ignored if the driver is
>> built with sama5d2/sama5d3/sama5d4/sam9x5/sam9x60 ?
>
> The warning only popped up for a custom board build, where I include
> in file 'include/configs/myboard.h' and keep some
> old definitions for the old driver and then
[PATCH v2 6/6] rockchip: rv1126: Move RAM disk address
OPTEE gets loaded into a memory region overlapping with the ram disk. Fix the ramdisk address so it doesn't overlap with the OPTEE memory region. Signed-off-by: Tim Lunn --- (no changes since v1) include/configs/rv1126_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/rv1126_common.h b/include/configs/rv1126_common.h index 168cd8b167..ea290f763c 100644 --- a/include/configs/rv1126_common.h +++ b/include/configs/rv1126_common.h @@ -26,7 +26,7 @@ "fdt_addr_r=0x0830\0" \ "fdtoverlay_addr_r=0x0200\0" \ "kernel_addr_r=0x02008000\0" \ - "ramdisk_addr_r=0x0a20\0" + "ramdisk_addr_r=0x0a40\0" #define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x0fff\0" \ -- 2.40.1
[PATCH v2 5/6] rockchip: rv1126: select SPL_OPTEE_IMAGE
rv1126 requires OPTEE as it provides pcsi support. Mainline Linux kernel will fail to boot without this. Select SPL_OPTEE_IMAGE when building FIT image. TEE must be provided when building. Signed-off-by: Tim Lunn --- (no changes since v1) arch/arm/mach-rockchip/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 6ff0aa6911..cce118a004 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -359,6 +359,7 @@ config ROCKCHIP_RV1126 select PMIC_RK8XX select BOARD_LATE_INIT imply ROCKCHIP_COMMON_BOARD + select SPL_OPTEE_IMAGE if SPL_FIT imply OF_LIBFDT_OVERLAY imply ROCKCHIP_OTP imply MISC_INIT_R -- 2.40.1
[PATCH v2 4/6] board: rockchip: Add Sonoff iHost board
Sonoff iHost is gateway device designed to provide a Smart Home Hub,
it is based on Rockchip RV1126. There is also a version with 2GB RAM
based off the RV1109 dual core SoC however this works with the same
config as the RV1126 for uboot purposes.
Features:
- Rockchip RV1126
- 4GB DDR4
- 8GB eMMC
- microSD slot
- RMII Ethernet PHY
- 1x USB 2.0 Host
- 1x USB 2.0 OTG
- Realtek RTL8723DS WiFi/BT
- EFR32MG21 Silabs Zigbee radio
- Speaker/Microphone
Signed-off-by: Tim Lunn
---
Changes in v2:
- Remove board config not required with standard boot
arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi | 13 +
arch/arm/mach-rockchip/rv1126/Kconfig| 8 +++
board/itead/sonoff-ihost/Kconfig | 16 ++
board/itead/sonoff-ihost/MAINTAINERS | 6 ++
configs/sonoff-ihost-rv1126_defconfig| 60
doc/board/rockchip/rockchip.rst | 1 +
include/configs/sonoff-ihost.h | 10
7 files changed, 114 insertions(+)
create mode 100644 arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi
create mode 100644 board/itead/sonoff-ihost/Kconfig
create mode 100644 board/itead/sonoff-ihost/MAINTAINERS
create mode 100644 configs/sonoff-ihost-rv1126_defconfig
create mode 100644 include/configs/sonoff-ihost.h
diff --git a/arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi
b/arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi
new file mode 100644
index 00..a625660d58
--- /dev/null
+++ b/arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rv1126-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", ,
+ };
+};
+
+ {
+ status = "disabled";
+};
diff --git a/arch/arm/mach-rockchip/rv1126/Kconfig
b/arch/arm/mach-rockchip/rv1126/Kconfig
index a6e2b5903c..55b1112120 100644
--- a/arch/arm/mach-rockchip/rv1126/Kconfig
+++ b/arch/arm/mach-rockchip/rv1126/Kconfig
@@ -14,6 +14,13 @@ config TARGET_RV1126_NEU2
IO board and Neu2 needs to mount on top of this IO board in order to
create complete Edgeble Neural Compute Module 2(Neu2) IO platform.
+config TARGET_RV1126_SONOFF_IHOST
+ bool "Sonoff iHost smart home hub"
+ help
+ Sonoff iHost is a smart home gateway based on Rockchip RV1126 SoC.
+ It features Wifi, Bluetooth and Zigbee radios that are used by many
+ smart home devices.
+
config SOC_SPECIFIC_OPTIONS # dummy
def_bool y
select HAS_CUSTOM_SYS_INIT_SP_ADDR
@@ -58,5 +65,6 @@ config TEXT_BASE
default 0x60
source board/edgeble/neural-compute-module-2/Kconfig
+source board/itead/sonoff-ihost/Kconfig
endif
diff --git a/board/itead/sonoff-ihost/Kconfig b/board/itead/sonoff-ihost/Kconfig
new file mode 100644
index 00..30d9a6b3e6
--- /dev/null
+++ b/board/itead/sonoff-ihost/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_RV1126_SONOFF_IHOST
+
+config SYS_BOARD
+ default "sonoff-ihost"
+
+config SYS_VENDOR
+ default "itead"
+
+config SYS_CONFIG_NAME
+ default "sonoff-ihost"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select RAM_ROCKCHIP_DDR4
+
+endif
diff --git a/board/itead/sonoff-ihost/MAINTAINERS
b/board/itead/sonoff-ihost/MAINTAINERS
new file mode 100644
index 00..eff9274bea
--- /dev/null
+++ b/board/itead/sonoff-ihost/MAINTAINERS
@@ -0,0 +1,6 @@
+RV1126-SONOFF-IHOST
+M: Tim Lunn
+S: Maintained
+F: board/itead/sonoff-ihost
+F: include/configs/sonoff-ihost.h
+F: configs/sonoff-ihost-rv1126_defconfig
diff --git a/configs/sonoff-ihost-rv1126_defconfig
b/configs/sonoff-ihost-rv1126_defconfig
new file mode 100644
index 00..fe99bd92f9
--- /dev/null
+++ b/configs/sonoff-ihost-rv1126_defconfig
@@ -0,0 +1,60 @@
+CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_SYS_ARCH_TIMER=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="rv1126-sonoff-ihost"
+CONFIG_SYS_MONITOR_LEN=614400
+CONFIG_ROCKCHIP_RV1126=y
+CONFIG_TARGET_RV1126_SONOFF_IHOST=y
+CONFIG_DEBUG_UART_BASE=0xff57
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SYS_LOAD_ADDR=0xe00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_DEFAULT_FDT_FILE="rv1126-sonoff-ihost.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_NO_BSS_LIMIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+#
[PATCH v2 3/6] rockchip: Convert rv1126 to standard boot
RV1126 soc appears to have been missed with the conversion of rockchip socs to standard boot. Remove remnants of distro boot for rv1126 common and the one existing board. Signed-off-by: Tim Lunn Link: https://lore.kernel.org/all/20230407223645.v8.8.I4cf7708a1ba953b9abd81375d93af34665c7b251@changeid/ --- Changes in v2: - New patch to clean up distro boot from rv1126_common.h include/configs/neural-compute-module-2.h | 6 -- include/configs/rv1126_common.h | 3 +-- 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/include/configs/neural-compute-module-2.h b/include/configs/neural-compute-module-2.h index f0934ae00c..43a560906a 100644 --- a/include/configs/neural-compute-module-2.h +++ b/include/configs/neural-compute-module-2.h @@ -12,10 +12,4 @@ #include -#undef BOOT_TARGET_DEVICES - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) - #endif /* __NEURAL_COMPUTE_MODULE_2_H */ diff --git a/include/configs/rv1126_common.h b/include/configs/rv1126_common.h index a64c0c6364..168cd8b167 100644 --- a/include/configs/rv1126_common.h +++ b/include/configs/rv1126_common.h @@ -28,7 +28,6 @@ "kernel_addr_r=0x02008000\0" \ "ramdisk_addr_r=0x0a20\0" -#include #define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x0fff\0" \ "initrd_high=0x0fff\0" \ @@ -36,6 +35,6 @@ "partitions=" PARTS_DEFAULT \ ENV_MEM_LAYOUT_SETTINGS \ ROCKCHIP_DEVICE_SETTINGS \ - BOOTENV + "boot_targets=" BOOT_TARGETS "\0" #endif /* __CONFIG_RV1126_COMMON_H */ -- 2.40.1
[PATCH v2 2/6] ram: rockchip: Add rv1126 ddr4 support
Add support for ddr4 on rv1126. Timing detection files are imported
from downstream Rockchip BSP u-boot. Allow selecting ddr4 ram with
define CONFIG_RAM_ROCKCHIP_DDR4.
Signed-off-by: Tim Lunn
---
(no changes since v1)
.../sdram-rv1126-ddr4-detect-1056.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-328.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-396.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-528.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-664.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-784.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-924.inc | 75 +++
drivers/ram/rockchip/sdram_rv1126.c | 8 ++
8 files changed, 533 insertions(+)
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-328.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-396.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-528.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-664.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-784.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-924.inc
diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc
b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc
new file mode 100644
index 00..295b0871e0
--- /dev/null
+++ b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc
@@ -0,0 +1,75 @@
+{
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x2,
+ .bw = 0x1,
+ .dbw = 0x0,
+ .row_3_4 = 0x0,
+ .cs0_row = 0x11,
+ .cs1_row = 0x0,
+ .cs0_high16bit_row = 0x11,
+ .cs1_high16bit_row = 0x0,
+ .ddrconfig = 0
+ },
+ {
+ {0x561d1219},
+ {0x10030703},
+ {0x0002},
+ {0x},
+ {0x000c},
+ {0x034b},
+ 0x00ff
+ }
+ },
+ {
+ .ddr_freq = 1056, /* clock rate(MHz) */
+ .dramtype = DDR4,
+ .num_channels = 1,
+ .stride = 0,
+ .odt = 1
+ },
+ {
+ {
+ {0x, 0x43041010}, /* MSTR */
+ {0x0064, 0x008000b9}, /* RFSHTMG */
+ {0x00d0, 0x00020103}, /* INIT0 */
+ {0x00d4, 0x0069}, /* INIT1 */
+ {0x00d8, 0x0100}, /* INIT2 */
+ {0x00dc, 0x07340401}, /* INIT3 */
+ {0x00e0, 0x0010}, /* INIT4 */
+ {0x00e4, 0x0011}, /* INIT5 */
+ {0x00e8, 0x0420}, /* INIT6 */
+ {0x00ec, 0x0800}, /* INIT7 */
+ {0x00f4, 0x000f011f}, /* RANKCTL */
+ {0x0100, 0x0f102411}, /* DRAMTMG0 */
+ {0x0104, 0x0004041a}, /* DRAMTMG1 */
+ {0x0108, 0x0608060d}, /* DRAMTMG2 */
+ {0x010c, 0x0040400c}, /* DRAMTMG3 */
+ {0x0110, 0x08030409}, /* DRAMTMG4 */
+ {0x0114, 0x06060403}, /* DRAMTMG5 */
+ {0x0120, 0x07070d07}, /* DRAMTMG8 */
+ {0x0124, 0x00020309}, /* DRAMTMG9 */
+ {0x0180, 0x0140}, /* ZQCTL0 */
+ {0x0184, 0x}, /* ZQCTL1 */
+ {0x0190, 0x07060004}, /* DFITMG0 */
+ {0x0198, 0x07000101}, /* DFILPCFG0 */
+ {0x01a0, 0xc043}, /* DFIUPD0 */
+ {0x0240, 0x06000614}, /* ODTCFG */
+ {0x0244, 0x0201}, /* ODTMAP */
+ {0x0250, 0x1f00}, /* SCHED */
+ {0x0490, 0x0001}, /* PCTRL_0 */
+ {0x, 0x}
+ }
+ },
+ {
+ {
+ {0x0004, 0x008c}, /* PHYREG01 */
+ {0x0014, 0x0010}, /* PHYREG05 */
+ {0x0018, 0x}, /* PHYREG06 */
+ {0x001c, 0x000b}, /* PHYREG07 */
+
[PATCH v2 1/6] arm: dts: rockchip: Sync rv1126 dts from linux 6.8-rc1
Sync linux dts files for rv1126 boards from linux v6.8-rc1 tag. Includes
the newly added dts for Sonoff iHost.
Signed-off-by: Tim Lunn
---
(no changes since v1)
arch/arm/dts/rv1126-edgeble-neu2-io.dts | 70
arch/arm/dts/rv1126-edgeble-neu2.dtsi | 27 +-
arch/arm/dts/rv1126-pinctrl.dtsi| 130
arch/arm/dts/rv1126-sonoff-ihost.dts| 29 ++
arch/arm/dts/rv1126-sonoff-ihost.dtsi | 404
arch/arm/dts/rv1126.dtsi| 185 +++
6 files changed, 835 insertions(+), 10 deletions(-)
create mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dts
create mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dtsi
diff --git a/arch/arm/dts/rv1126-edgeble-neu2-io.dts
b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
index dded0a12f0..0c2396b8f8 100644
--- a/arch/arm/dts/rv1126-edgeble-neu2-io.dts
+++ b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
@@ -20,6 +20,76 @@
chosen {
stdout-path = "serial2:150n8";
};
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <_dcin>;
+ };
+
+ v3v3_sys: v3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "v3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <_sys>;
+ };
+};
+
+ {
+ assigned-clocks = < CLK_GMAC_SRC>, < CLK_GMAC_TX_RX>,
+ < CLK_GMAC_ETHERNET_OUT>;
+ assigned-clock-parents = < CLK_GMAC_SRC_M1>, < RGMII_MODE_CLK>;
+ assigned-clock-rates = <12500>, <0>, <2500>;
+ clock_in_out = "input";
+ phy-handle = <>;
+ phy-mode = "rgmii";
+ phy-supply = <_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_miim _bus2 _bus4
_out_ethernetm1_pins>;
+ tx_delay = <0x2a>;
+ rx_delay = <0x1a>;
+ status = "okay";
+};
+
+ {
+ phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-id001c.c916",
+"ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_phy_rst>;
+ reset-assert-us = <2>;
+ reset-deassert-us = <10>;
+ reset-gpios = < RK_PB6 GPIO_ACTIVE_LOW>;
+ };
+};
+
+ {
+ ethernet {
+ eth_phy_rst: eth-phy-rst {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO _pull_down>;
+ };
+ };
+};
+
+ {
+ status = "okay";
};
{
diff --git a/arch/arm/dts/rv1126-edgeble-neu2.dtsi
b/arch/arm/dts/rv1126-edgeble-neu2.dtsi
index cc64ba4be3..7ea8d7d16f 100644
--- a/arch/arm/dts/rv1126-edgeble-neu2.dtsi
+++ b/arch/arm/dts/rv1126-edgeble-neu2.dtsi
@@ -11,15 +11,6 @@
mmc0 =
};
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
- };
-
vccio_flash: vccio-flash-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -52,7 +43,7 @@
bus-width = <8>;
non-removable;
pinctrl-names = "default";
- pinctrl-0 = <_bus8 _cmd _clk _rstnout>;
+ pinctrl-0 = <_bus8 _cmd _clk>;
rockchip,default-sample-phase = <90>;
vmmc-supply = <_3v3>;
vqmmc-supply = <_flash>;
@@ -301,6 +292,22 @@
status = "okay";
};
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <5000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
{
bus-width = <4>;
cap-sd-highspeed;
diff --git a/arch/arm/dts/rv1126-pinctrl.dtsi b/arch/arm/dts/rv1126-pinctrl.dtsi
index 28d8d29942..f84f5f2d96 100644
--- a/arch/arm/dts/rv1126-pinctrl.dtsi
+++ b/arch/arm/dts/rv1126-pinctrl.dtsi
@@ -11,6 +11,14 @@
* by
[PATCH v2 0/6] rockchip: Add support for rv1126 based Sonoff iHost Gateway
Sonoff iHost is gateway device designed to provide a Smart Home Hub, it is based on Rockchip RV1126. It features Wifi, BT and Zigbee radios as required by many smart home devices. Features: - Rockchip RV1126 - 4GB DDR4 - 8GB eMMC - microSD slot - RMII Ethernet PHY - 1x USB 2.0 Host - 1x USB 2.0 OTG - Realtek RTL8723DS WiFi/BT - EFR32MG21 Silabs Zigbee radio - Speaker/Microphone Sync rv1126 dts from linux v6.8-rc1, add support for ddr4 ram and add board support for the Sonoff ihost. Changes in v2: - New patch to clean up distro boot from rv1126_common.h - Remove board config not required with standard boot Tim Lunn (6): arm: dts: rockchip: Sync rv1126 dts from linux 6.8-rc1 ram: rockchip: Add rv1126 ddr4 support rockchip: Convert rv1126 to standard boot board: rockchip: Add Sonoff iHost board rockchip: rv1126: select SPL_OPTEE_IMAGE rockchip: rv1126: Move RAM disk address arch/arm/dts/rv1126-edgeble-neu2-io.dts | 70 +++ arch/arm/dts/rv1126-edgeble-neu2.dtsi | 27 +- arch/arm/dts/rv1126-pinctrl.dtsi | 130 ++ arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi | 13 + arch/arm/dts/rv1126-sonoff-ihost.dts | 29 ++ arch/arm/dts/rv1126-sonoff-ihost.dtsi | 404 ++ arch/arm/dts/rv1126.dtsi | 185 arch/arm/mach-rockchip/Kconfig| 1 + arch/arm/mach-rockchip/rv1126/Kconfig | 8 + board/itead/sonoff-ihost/Kconfig | 16 + board/itead/sonoff-ihost/MAINTAINERS | 6 + configs/sonoff-ihost-rv1126_defconfig | 60 +++ doc/board/rockchip/rockchip.rst | 1 + .../sdram-rv1126-ddr4-detect-1056.inc | 75 .../rockchip/sdram-rv1126-ddr4-detect-328.inc | 75 .../rockchip/sdram-rv1126-ddr4-detect-396.inc | 75 .../rockchip/sdram-rv1126-ddr4-detect-528.inc | 75 .../rockchip/sdram-rv1126-ddr4-detect-664.inc | 75 .../rockchip/sdram-rv1126-ddr4-detect-784.inc | 75 .../rockchip/sdram-rv1126-ddr4-detect-924.inc | 75 drivers/ram/rockchip/sdram_rv1126.c | 8 + include/configs/neural-compute-module-2.h | 6 - include/configs/rv1126_common.h | 5 +- include/configs/sonoff-ihost.h| 10 + 24 files changed, 1485 insertions(+), 19 deletions(-) create mode 100644 arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi create mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dts create mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dtsi create mode 100644 board/itead/sonoff-ihost/Kconfig create mode 100644 board/itead/sonoff-ihost/MAINTAINERS create mode 100644 configs/sonoff-ihost-rv1126_defconfig create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-328.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-396.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-528.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-664.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-784.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-924.inc create mode 100644 include/configs/sonoff-ihost.h -- 2.40.1
[PATCH v1] tools: mkimage: Add support for i.MXRT FlexSPI Header
Modify imx8m Flex SPI Configuration Block to work with imxrt.
Add more Flex SPI configuration options to Kconfig.
Signed-off-by: Jesse Taube
---
include/imximage.h | 42 +
tools/Kconfig | 21 +
tools/imx8mimage.c | 41
tools/imximage.c | 77 ++
4 files changed, 143 insertions(+), 38 deletions(-)
diff --git a/include/imximage.h b/include/imximage.h
index c1ecc0b7cb..a951699d0a 100644
--- a/include/imximage.h
+++ b/include/imximage.h
@@ -210,33 +210,37 @@ typedef struct {
uint8_t datasetup;
uint8_t coladdrwidth;
uint8_t devcfgenable;
- uint8_t reserved_2[3];
+ uint8_t deviceModeType;
+ uint16_t waitTimeCfgCommands;
uint8_t devmodeseq[4];
- uint8_t devmodearg[4];
+ uint32_t devmodearg;
uint8_t cmd_enable;
- uint8_t reserved_3[3];
+ uint8_t configModeType[3];
uint8_t cmd_seq[16] ;
uint8_t cmd_arg[16];
- uint8_t controllermisc[4];
+ uint32_t controllermisc;
uint8_t dev_type;
uint8_t sflash_pad;
uint8_t serial_clk;
- uint8_t lut_custom ;
- uint8_t reserved_4[8];
- uint8_t sflashA1[4];
- uint8_t sflashA2[4];
- uint8_t sflashB1[4];
- uint8_t sflashB2[4];
- uint8_t cspadover[4];
- uint8_t sclkpadover[4];
- uint8_t datapadover[4];
- uint8_t dqspadover[4];
- uint8_t timeout[4];
- uint8_t commandInt[4];
- uint8_t datavalid[4];
- uint8_t busyoffset[2];
- uint8_t busybitpolarity[2];
+ uint8_t lut_custom;
+ uint8_t reserved_2[8];
+ uint32_t sflashA1;
+ uint32_t sflashA2;
+ uint32_t sflashB1;
+ uint32_t sflashB2;
+ uint32_t cspadover;
+ uint32_t sclkpadover;
+ uint32_t datapadover;
+ uint32_t dqspadover;
+ uint32_t timeout;
+ uint32_t commandInt;
+ uint16_t datavalid[2];
+ uint16_t busyoffset;
+ uint16_t busybitpolarity;
uint8_t lut[256];
+ uint8_t lutCustomSeq[48];
+ uint8_t reserved_3[16];
+
} __attribute__((packed)) fspi_conf;
typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
diff --git a/tools/Kconfig b/tools/Kconfig
index f01ed783e6..667807b331 100644
--- a/tools/Kconfig
+++ b/tools/Kconfig
@@ -148,6 +148,27 @@ config SERIAL_CLK_FREQUENCY
Chip specific frequency: other value 30MHz
1-30MHz 2-50MHz 3-60MHz 4-75MHz 5-80MHz 6-100MHz 7-133MHz 8-166MHz
+config FSPI_COL_ADDR_W
+ hex "Column Address With"
+ default 0x00
+ depends on FSPI_CONF_HEADER
+ help
+ Default 0. For HyperBus protocol, it is fixed to 3
+
+config FSPI_CONTROLLER_MISC
+ hex "FSPI miscellaneous control"
+ default 0x
+ depends on FSPI_CONF_HEADER
+ help
+ Default 0. [0x40] Controller Misc Options
+
+config FSPI_FLASH_A1_SIZE
+ hex "Size in bytes of Flash A1"
+ default 0x1000
+ depends on FSPI_CONF_HEADER
+ help
+ Size of Flash connected to A1 in bytes
+
config LUT_CUSTOM_SEQUENCE
hex "Enable Custom Look Up Table(LUT) Sequence"
default 0x00
diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c
index 21075c2379..939f829a9f 100644
--- a/tools/imx8mimage.c
+++ b/tools/imx8mimage.c
@@ -426,36 +426,39 @@ static int generate_fspi_header (int ifd)
.read_sample = CONFIG_READ_CLK_SOURCE,
.datahold = 0x03,
.datasetup = 0x03,
- .coladdrwidth = 0x00,
+ .coladdrwidth = CONFIG_FSPI_COL_ADDR_W,
.devcfgenable = 0x00,
- .reserved_2 = {0x00, 0x00, 0x00},
+ .deviceModeType = 0x00,
+ .waitTimeCfgCommands = 0x,
.devmodeseq = {0x00, 0x00, 0x00, 0x00},
- .devmodearg = {0x00, 0x00, 0x00, 0x00},
+ .devmodearg = 0x,
.cmd_enable = 0x00,
- .reserved_3 = {0x00},
+ .configModeType = {0x00},
.cmd_seq = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00},
.cmd_arg = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00},
- .controllermisc = {0x00, 0x00, 0x00, 0x00},
+ .controllermisc = cpu_to_le32(CONFIG_FSPI_CONTROLLER_MISC),
.dev_type = CONFIG_DEVICE_TYPE,
.sflash_pad = CONFIG_FLASH_PAD_TYPE,
.serial_clk = CONFIG_SERIAL_CLK_FREQUENCY,
.lut_custom = CONFIG_LUT_CUSTOM_SEQUENCE,
- .reserved_4 = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .sflashA1 = {0x00, 0x00, 0x00, 0x10},
- .sflashA2 = {0x00, 0x00, 0x00, 0x00},
- .sflashB1 = {0x00, 0x00, 0x00, 0x00},
- .sflashB2 = {0x00, 0x00, 0x00, 0x00},
- .cspadover = {0x00, 0x00, 0x00, 0x00},
- .sclkpadover = {0x00, 0x00, 0x00,
[PATCH v1] arm: dts: nuvoton: modify npcm8xx reset property
Change reset method from generic to reset driver
Signed-off-by: Jim Liu
---
arch/arm/dts/nuvoton-common-npcm8xx.dtsi | 2 +
arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi | 71
2 files changed, 24 insertions(+), 49 deletions(-)
diff --git a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
index 1694ef8849..db7517cc9b 100644
--- a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
+++ b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
@@ -5,6 +5,7 @@
#include
#include
#include
+#include
/ {
#address-cells = <2>;
@@ -152,6 +153,7 @@
interrupts = ;
clocks = < NPCM8XX_CLK_APB5>;
clock-names = "clk_apb5";
+ resets = < NPCM8XX_RESET_IPSRST2
NPCM8XX_RESET_PSPI2>;
status = "disabled";
};
diff --git a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
index 4c6d5bed44..bc047d4b44 100644
--- a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
+++ b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
@@ -20,34 +20,7 @@
compatible = "nuvoton,npcm845-reset", "syscon",
"simple-mfd";
reg = <0x0 0xf0801000 0x0 0xC4>;
- rstc1: reset-controller1 {
- compatible = "syscon-reset";
- #reset-cells = <1>;
- regmap = <>;
- offset = ;
- mask = <0x>;
- };
- rstc2: reset-controller2 {
- compatible = "syscon-reset";
- #reset-cells = <1>;
- regmap = <>;
- offset = ;
- mask = <0x>;
- };
- rstc3: reset-controller3 {
- compatible = "syscon-reset";
- #reset-cells = <1>;
- regmap = <>;
- offset = ;
- mask = <0x>;
- };
- rstc4: reset-controller4 {
- compatible = "syscon-reset";
- #reset-cells = <1>;
- regmap = <>;
- offset = ;
- mask = <0x>;
- };
+ #reset-cells = <2>;
};
clk: clock-controller@f0801000 {
@@ -70,7 +43,7 @@
clock-names = "stmmaceth";
pinctrl-names = "default";
pinctrl-0 = <_pins>;
- resets = < NPCM8XX_RESET_GMAC1>;
+ resets = < NPCM8XX_RESET_IPSRST2
NPCM8XX_RESET_GMAC1>;
status = "disabled";
};
@@ -85,7 +58,7 @@
pinctrl-names = "default";
pinctrl-0 = <_pins
_pins>;
- resets = < NPCM8XX_RESET_GMAC2>;
+ resets = < NPCM8XX_RESET_IPSRST2
NPCM8XX_RESET_GMAC2>;
status = "disabled";
};
@@ -101,7 +74,7 @@
pinctrl-0 = <_pins
_pins
_pins>;
- resets = < NPCM8XX_RESET_GMAC3>;
+ resets = < NPCM8XX_RESET_IPSRST1
NPCM8XX_RESET_GMAC3>;
status = "disabled";
};
@@ -117,7 +90,7 @@
pinctrl-0 = <_pins
_pins
_pins>;
- resets = < NPCM8XX_RESET_GMAC4>;
+ resets = < NPCM8XX_RESET_IPSRST1
NPCM8XX_RESET_GMAC4>;
status = "disabled";
};
@@ -125,7 +98,7 @@
compatible = "nuvoton,npcm845-ehci";
reg = <0x0 0xf0828100 0x0 0x1000>;
interrupts = ;
- resets = < NPCM8XX_RESET_USBH1>;
+ resets = < NPCM8XX_RESET_IPSRST2
NPCM8XX_RESET_USBH1>;
status = "disabled";
};
@@ -133,21 +106,21 @@
compatible = "nuvoton,npcm845-ehci";
reg = <0x0 0xf082a100 0x0 0x1000>;
interrupts = ;
- resets = < NPCM8XX_RESET_USBH2>;
+ resets = < NPCM8XX_RESET_IPSRST4
NPCM8XX_RESET_USBH2>;
status = "disabled";
Re: Could you please help me in resolving the " /reset.c:42:(.text.do_reset+0x20): undefined reference to `reset_cpu'?"
Hi Fabio, Thank you you review. Sincerely, Liu Wang > On Jan 23, 2024, at 4:44 PM, Fabio Estevam wrote: > > [CAUTION: External Mail] > >> On Tue, Jan 23, 2024 at 4:20 PM Liu Wang wrote: >> >> Hi Fabio, >> >> Thank you for your help. >> >> Attached is the 'git status' and 'git log' in my porting u-boot to my >> cse_ptjob_cb3_r102 control board by following README in u-boot and being >> blocked with the hurdle of "undefined reference to `reset_cpu'" in hope you >> spot something familiar and shed a light in my building effort. > > I don't have any insight into the problem, unfortunately. > > Also, v2020.10 is too old. > > You should use mainline U-Boot and upstream your board (or hire > someone to do it for you).
Re: [PATCH 01/20] Convert CONFIG_SPL_STACK to Kconfig
On Wed, Jan 24, 2024 at 09:15:07AM +0800, Kever Yang wrote: > Hi Tom, > > On 2024/1/24 01:58, Tom Rini wrote: > > On Tue, Jan 23, 2024 at 11:53:18AM +0800, Kever Yang wrote: > > > > > Hi Tom, > > > > > > rk3036 only has small size internal sram, so it can only use very > > > simple SPL which only including dram init, and no SPL_FRAMEWORK > > > support. > > > In this convert, the CONFIG_SPL_STACK is lost for this SoC, any > > > suggestions on this kind of issue? > > Does this work? > > > > diff --git a/common/spl/Kconfig b/common/spl/Kconfig > > index e7b84fc1fa68..9deee0fdbea8 100644 > > --- a/common/spl/Kconfig > > +++ b/common/spl/Kconfig > > @@ -372,7 +372,8 @@ config SPL_SHARES_INIT_SP_ADDR > > config SPL_STACK > > hex "Initial stack pointer location" > > - depends on (ARM || ARCH_JZ47XX || MICROBLAZE || RISCV) && SPL_FRAMEWORK > > + depends on (ARM || ARCH_JZ47XX || MICROBLAZE || RISCV) && \ > > + SPL_FRAMEWORK || ROCKCHIP_RK3036 > This works with adding CONFIG_SPL_STACK in rk3036 board defconfig. > > depends on !SPL_SHARES_INIT_SP_ADDR > > default 0x946bb8 if ARCH_MX7 > > default 0x93ffb8 if ARCH_MX6 && MX6_OCRAM_256KB > > > > You will have to update the ROCKCHIP_RK3036 platforms otherwise the > > build will hang now. > > What do you mean to update the platform? > > The rk3036 case should be one of the available option for those "small"/low > end SoCs has very limit > > size of internal dram, only need minimal SPL+ U-Boot, and no requirement > for ATF/OPTEEwhich will have to use TPL+SPL+U-Boot. > > > The CONFIG_SPL_STACK is used in assemble init code, it doesn't need to > depends on SPL_FRAMEWORK, isn't it? I just mean that with the above Kconfig change, all RK3036 platforms must set a value for CONFIG_SPL_STACK at the same time, or they will fail to build (and CI will get hung). It sounds like all RK3036 platforms need to set the value in order to work, so this isn't a bug, just a feature. Is that clearer? -- Tom signature.asc Description: PGP signature
Re: [PATCH v3 07/11] lib: vsprintf: enable '%pbl' format specifier
On Tue, Jan 23, 2024 at 03:48:10PM +0100, Lukas Funke wrote: > Hi Tom, > > On 18.01.2024 21:22, Tom Rini wrote: > > On Wed, Jan 10, 2024 at 10:10:33AM +0100, lukas.funke-...@weidmueller.com > > wrote: > > > > > From: Lukas Funke > > > > > > The commit enables vsprintf() to handle the '%pbl' format specifier > > > in order to print bitmaps and its derivatives such as cpumask and > > > nodemask [1]. This can be used to derive kernel boot parameters from > > > bitmaks such as 'isolcpu' or 'nohz_full' [2]. > > > > > > [1] https://www.kernel.org/doc/Documentation/printk-formats.txt > > > [2] > > > https://www.kernel.org/doc/html/latest/admin-guide/kernel-parameters.html > > > > > > Signed-off-by: Lukas Funke > > > > This breaks building ARC platforms, and possibly others. Note that > > tools/buildman/buildman is happy to fetch toolchains for you, and in > > this case it's also just the current kernel.org cross-toolchain. Please > > see https://docs.u-boot.org/en/latest/develop/ci_testing.html about how > > to trigger a CI run prior to sending v4, thanks. > > > > Thanks for the input. I ran the pipeline on github and it failed for riscv, > m86k, x86_64. The reason is the missing 'find_next_zero_bit()' > implementation (actually it's faulty on x86_64). What is a good way to cope > with this problem? My suggestions would be: > > - Add a generic 'find_next_zero_bit()'. This would be the > 'Linux way' and requires refactoring of the bitops header. Yes, this way please, thanks. -- Tom signature.asc Description: PGP signature
Re: [PATCH 01/20] Convert CONFIG_SPL_STACK to Kconfig
Hi Tom, On 2024/1/24 01:58, Tom Rini wrote: On Tue, Jan 23, 2024 at 11:53:18AM +0800, Kever Yang wrote: Hi Tom, rk3036 only has small size internal sram, so it can only use very simple SPL which only including dram init, and no SPL_FRAMEWORK support. In this convert, the CONFIG_SPL_STACK is lost for this SoC, any suggestions on this kind of issue? Does this work? diff --git a/common/spl/Kconfig b/common/spl/Kconfig index e7b84fc1fa68..9deee0fdbea8 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -372,7 +372,8 @@ config SPL_SHARES_INIT_SP_ADDR config SPL_STACK hex "Initial stack pointer location" - depends on (ARM || ARCH_JZ47XX || MICROBLAZE || RISCV) && SPL_FRAMEWORK + depends on (ARM || ARCH_JZ47XX || MICROBLAZE || RISCV) && \ + SPL_FRAMEWORK || ROCKCHIP_RK3036 This works with adding CONFIG_SPL_STACK in rk3036 board defconfig. depends on !SPL_SHARES_INIT_SP_ADDR default 0x946bb8 if ARCH_MX7 default 0x93ffb8 if ARCH_MX6 && MX6_OCRAM_256KB You will have to update the ROCKCHIP_RK3036 platforms otherwise the build will hang now. What do you mean to update the platform? The rk3036 case should be one of the available option for those "small"/low end SoCs has very limit size of internal dram, only need minimal SPL+ U-Boot, and no requirement for ATF/OPTEEwhich will have to use TPL+SPL+U-Boot. The CONFIG_SPL_STACK is used in assemble init code, it doesn't need to depends on SPL_FRAMEWORK, isn't it? Thanks, - Kever
Re: Could you please help me in resolving the " /reset.c:42:(.text.do_reset+0x20): undefined reference to `reset_cpu'?"
On Tue, Jan 23, 2024 at 4:20 PM Liu Wang wrote: > > Hi Fabio, > > Thank you for your help. > > Attached is the 'git status' and 'git log' in my porting u-boot to my > cse_ptjob_cb3_r102 control board by following README in u-boot and being > blocked with the hurdle of "undefined reference to `reset_cpu'" in hope you > spot something familiar and shed a light in my building effort. I don't have any insight into the problem, unfortunately. Also, v2020.10 is too old. You should use mainline U-Boot and upstream your board (or hire someone to do it for you).
Re: [PATCH 07/10] arm: mach-k3: am625_init: Probe AM65 CPSW NUSS
On 15:49-20240122, Chintan Vankar wrote: > > On 12/01/24 18:00, Nishanth Menon wrote: > > On 12:17-20240112, Siddharth Vadapalli wrote: > > > From: Kishon Vijay Abraham I > > > > > > In order to support Ethernet boot on AM62x, probe AM65 CPSW NUSS driver > > > in board_init_f(). > > Why? doesn't the DM framework handle this? > Can you suggest how can we do this ? Did'nt you guys just discuss this in https://lore.kernel.org/all/48c63fc4-9f06-4066-b206-a0a548936...@ti.com/ ? -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
Re: [PATCH v8 12/16] arm: dts: Introduce j784s4 u-boot dts files
On 20:28-20240123, Apurva Nandan wrote:
>
[...]
> > in j784s4-binman.dtsi:
> >
> >
> >{
> > j784s4_tiboot3_hs_fs_template: template-9 {
> >
> > and then in sk.dtsi:
> sk.dtsi means sk-uboot.dtsi or sk-binman.dtsi?
you wont need an sk-binman.dtsi with template. sk-u-boot.dtsi and
r5-sk.dts ofcourse will instantiate the required templates!
> > {
> >ti-j784s4-hs-evm.bin {
> > insert-template =<_tiboot3_hs_fs_template>;
> > };
> > };
> >
> > This allows boards to readily include the template for the binaries of
> > choice and generate just relevant output. Wont it save much confusion?
> >
> > [...]
> It is still little unclear what is the full thing that you are recommending
> to implement here.
> From what I understood, is it as follows?
>
> - Three binman files will be there: j784s4-binman.dtsi (soc binman),
> j784s4-evm-binman.dtsi and am69-sk-binman.dtsi (board binman)
Nope. just j784s4-binman.dtsi with bin file templates for different kinds
of devices.
> - j784s4-binman.dtsi will be a SoC binman, and will have only templates for
> all tiboot3 gp, hs, hsfs, and tispl/uboot
tiboot3.bin is a an example, but you should do templates for other files
(tispl, u-boot.img... )as well on similar lines. So all a board file
ideally should instantiate is device types it wants and overrides of
dtbs it needs.
> - The board binman files will include these templates and update the dtb
> files in them.
Correct.
> - Final board.dts will use the correct board-binman.dtsi files
if the templates are abstract enough, the additional code will be so
minimal that we wont need a board-binman.dtsi - just u-boot.dtsi and
r5.dtsi can include the relevant templates.
Hope this helps.
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5
849D 1736 249D
Re: [PATCH v8 02/16] arm: mach-k3: Add basic support for J784S4 SoC definition
On 20:21-20240123, Apurva Nandan wrote:
[...]
> > > +void k3_mem_init(void)
> > > +{
> > > + struct udevice *dev;
> > > + int ret, ctr = 1;
> > > +
> > > + if (IS_ENABLED(CONFIG_K3_J721E_DDRSS)) {
> > > + ret = uclass_get_device(UCLASS_RAM, 0, );
> > > + if (ret)
> > > + panic("DRAM 0 init failed: %d\n", ret);
> > > +
> > > + while (dev) {
> > why loop on dev? is it possible to have ret != 0 and dev = 0?
> >
> Some variable needs to be used for loop condition, do you want it to be ret?
> or maybe you can suggest your idea for this please.
> > > + ret = uclass_next_device_err();
> > > + if (ret) {
> > > + printf("Initialized %d DRAM controllers\n",
> > > ctr);
> > > + break;
> > > + }
> > > + ctr++;
> > What is the use of ctr++ ?? please do a limit check for instances.
> This is to keep the logic independent of board evm, so that no include of
> EVM config is needed.
> ctr is just used to notify user about how many DDR are up during boot, else
> it is not needed.
>
> I can remove the ctr and printf, if you want.
>
> For a limit check, how can we get number of DDR instances on the EVM, I
> don't know, can you please suggest some way?
>
> There is no config that stores this info afaik.
Why? J784s4 has only specific number of controllerns, correct?
A variant of the below -> but still have a question:
while (ctrl < J784S4_MAX_CONTROLLERS) {
ret = uclass_next_device_err();
if (ret) /* Question: How do we differentiate between valid
* failure and next instance not being present? */
break;
ctrl++;
}
info("Initialized %d DRAM controllers\n", ctrl - 1);
>
> >
> > [...]
> >
> > Next time, please respond to the review comment questions so that I
> > know that you have considered and decided something is not necessary
> > or something was missed in the new version - for example what happened
> > to mmc_stop/restart?
> mmc_stop/restart were removed (mentioned in series changelog)
Mentioning in diffstat of the patch helps give people the context of the
change w.r.t the path itself.
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5
849D 1736 249D
Re: [PATCH] efi_loader : Suppress error print message
On 1/23/24 19:53, Bhumkar, Tejas Arvind wrote:
[AMD Official Use Only - General]
Hi Ilias & Heinrich,
-Original Message-
From: Heinrich Schuchardt
Sent: Tuesday, January 23, 2024 3:30 PM
To: Ilias Apalodimas ; Bhumkar, Tejas Arvind
Cc: u-boot@lists.denx.de; xypron.g...@gmx.de; tr...@konsulko.com;
s...@chromium.org; Simek, Michal ; Abbarapu,
Venkatesh ; g...@xilinx.com
Subject: Re: [PATCH] efi_loader : Suppress error print message
Caution: This message originated from an External Source. Use proper caution
when opening attachments, clicking links, or responding.
On 1/23/24 09:33, Ilias Apalodimas wrote:
Hi Tejas,
On Mon, 22 Jan 2024 at 21:12, Tejas Bhumkar
wrote:
Currently, on certain Xilinx platforms, an issue has been identified,
manifesting as follows:
Hello Tejas,
thank you for bringing forward this issue.
Which defconfig are you relating to?
[Tejas]:
Checking with xilinx_zynqmp_virt_defconfig
Starting kernel ...
efi_free_pool: illegal free 0x77830040
efi_free_pool: illegal free 0x7782d040
efi_free_pool: illegal free 0x7782c040
The issue arises when the ramdisk image is relocated, placing it
within the previously allocated EFI memory region( as EFI is
established quite early in U-Boot).
Which version of U-Boot are you on? Commit 06d514d77c37 ("lmb: consider EFI
memory map") was meant to avoid such a situation.
[Tejas] :
I'm verifying against the latest changes in the master branch. The introduction of commit
06d514d77c37 ("lmb: consider EFI memory map") has resolved the occurrence of the
"efi_free_pool: illegal free" error. but, it leads to a new error, as detailed in the
following patch: https://lore.kernel.org/all/20230212150706.2967007-1-sjo...@collabora.com/
Could you, please, try to reproduce your issues with origin/master as of
today and provide the full boot log. Please, also provide the output of
the bdinfo and the printenv command as well as the sizes of the kernel
and the RAM disk.
Best regards
Heinrich
I don't mind suppressing the print for some time, but out of
curiosity, how is the ramdisk relocated? LMB should be aware of the
EFI regions by then, so I assume the relocation code doesn't check
those?
[Tejas] : I observe that the relocation of the RAM disk is taking place in the
line below.
https://github.com/u-boot/u-boot/blob/master/lib/lmb.c#L480-L491
Yes, the relocated code specifically examines the LMB region and does not
consider the EFI region.
The indicated situation is serious. If the EFI sub-system is using the same
memory
area as the ramdisk, this may lead to corruption of the ramdisk. Suppressing the
messages is by no means adequate to solve the problem.
[Tejas] :
The challenge arises when relocating the ramdisk image, inserting it into the
previously assigned EFI memory region,
established early in U-Boot. Consequently, when attempting to release memory in
the EFI region during the handover
process to the kernel in the efi_free_pool function, we first verify if the
memory was allocated by efi_allocate_pool().
The issue originates from a checksum mismatch because, during the ramdisk
relocation, we overwrite memory allocated by EFI.
This leads to the appearance of the error message: efi_free_pool: illegal free
0x77830040.
Crucially, there is no corruption of the ramdisk seen since we do not actually
releasing memory due to the checksum mismatch.
In our testing, this issue was observed only when the ramdisk size exceeded
approximately 24 MB.
Best regards
Heinrich
Thanks
/Ilias
Consequently, when
attempting to release memory in the EFI memory region during the
handover process to the kernel,we encounter memory violations.
Highlighting that EFI remains active primarily during the booting of
an EFI application, and the lmb persists while configuring images for
the boot process. Since we aren't utilizing the EFI memory region
during the boot process, there is no adverse impact even in the event
of a violation.
Currently, there is an ongoing discussion regarding the handling
strategies of three memory allocators: malloc, lmb, and EFI. This
discussion is documented in the email chain titled "Proposal: U-Boot
memory management."
Therefore, it is advisable to suppress the print message during the
boot process for now.
Signed-off-by: Tejas Bhumkar
---
lib/efi_loader/efi_memory.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/efi_loader/efi_memory.c
b/lib/efi_loader/efi_memory.c index edfad2d95a..821fe7616e 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -713,7 +713,7 @@ efi_status_t efi_free_pool(void *buffer)
/* Check that this memory was allocated by efi_allocate_pool() */
if (((uintptr_t)alloc & EFI_PAGE_MASK) ||
alloc->checksum != checksum(alloc)) {
- printf("%s: illegal free 0x%p\n", __func__, buffer);
+ debug("%s: illegal free 0x%p\n", __func__,
RE: Could you please help me in resolving the " /reset.c:42:(.text.do_reset+0x20): undefined reference to `reset_cpu'?"
Hi Fabio, Thank you for your help. Attached is the 'git status' and 'git log' in my porting u-boot to my cse_ptjob_cb3_r102 control board by following README in u-boot and being blocked with the hurdle of "undefined reference to `reset_cpu'" in hope you spot something familiar and shed a light in my building effort. Sincerely, Liu Wang - liuw@liuw-SYS-E100-12T-H:~/Downloads/u-boot$ git log commit 050acee119b3757fee3bd128f55d720fdd9bb890 (HEAD, tag: v2020.10, list) Author: Tom Rini Date: Mon Oct 5 11:15:32 2020 -0400 Prepare v2020.10 Signed-off-by: Tom Rini commit 0f3e2942c9e01b5dfc01f3dabe0e2f2ab8fd8b84 Author: Soeren Moch Date: Thu Aug 27 21:52:46 2020 +0200 board: tbs2910: Use recommended distroboot addresses According to doc/README.distro fdt_addr must not be set when DTB is not available from hardware. So remove this entry. Use address 32MB above the start of DRAM for kernel_addr_r. This way we likely can avoid the self-relocation of the compressed kernel image before it decompresses to offset 0x8000 from start of DRAM. Use address 128MB above the start of DRAM for fdt_addr_r, since this is the maximum location for the end of the kernel. So we avoid overwriting the DTB. Use 512k above that for ramdisk_addr_r. This should be enough for the DTB, rest of DRAM can be used for initrd. liuw@liuw-SYS-E100-12T-H:~/Downloads/u-boot$ - liuw@liuw-SYS-E100-12T-H:~/Downloads/u-boot$ git status HEAD detached at v2020.10 Changes not staged for commit: (use "git add ..." to update what will be committed) (use "git restore ..." to discard changes in working directory) modified: arch/arm/Kconfig modified: arch/arm/include/asm/arch-aspeed/platform.h modified: arch/arm/include/asm/global_data.h modified: cmd/bootm.c modified: cmd/i2c.c modified: cmd/load.c modified: cmd/source.c modified: common/image.c modified: fs/fs.c modified: include/command.h modified: include/ns16550.h Untracked files: (use "git add ..." to include in what will be committed) board/supermicro/ configs/cse_ptjob_cb3_r102_defconfig include/configs/cast_common.h include/configs/cse_ptjob_cb3_r102.h listBin log2024011616makeAll.yml logmakeall2024012218 makelog no changes added to commit (use "git add" and/or "git commit -a") liuw@liuw-SYS-E100-12T-H:~/Downloads/u-boot$ -Original Message- From: Fabio Estevam Sent: Monday, January 22, 2024 6:44 PM To: Liu Wang (HW) Cc: u-boot@lists.denx.de Subject: Re: Could you please help me in resolving the " /reset.c:42:(.text.do_reset+0x20): undefined reference to `reset_cpu'?" [CAUTION: External Mail] Hi Liu Wang, On Mon, Jan 22, 2024 at 10:55 PM Liu Wang wrote: > > Hi Fabio, > > Could you please help me in resolving the " > /reset.c:42:(.text.do_reset+0x20): undefined reference to `reset_cpu'?" from: > u-boot$make all: Looking at the errors below, there are several errors besides the reset_cpu one. As you are using an out-of-tree U-Boot, there is not much the U-Boot community can do to help you, sorry. You need to get assistance from the U-Boot provider that you are using.
RE: [PATCH] efi_loader : Suppress error print message
[AMD Official Use Only - General]
Hi Ilias & Heinrich,
> -Original Message-
> From: Heinrich Schuchardt
> Sent: Tuesday, January 23, 2024 3:30 PM
> To: Ilias Apalodimas ; Bhumkar, Tejas Arvind
>
> Cc: u-boot@lists.denx.de; xypron.g...@gmx.de; tr...@konsulko.com;
> s...@chromium.org; Simek, Michal ; Abbarapu,
> Venkatesh ; g...@xilinx.com
> Subject: Re: [PATCH] efi_loader : Suppress error print message
>
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> On 1/23/24 09:33, Ilias Apalodimas wrote:
> > Hi Tejas,
> >
> > On Mon, 22 Jan 2024 at 21:12, Tejas Bhumkar
> > wrote:
> >>
> >> Currently, on certain Xilinx platforms, an issue has been identified,
> >> manifesting as follows:
>
> Hello Tejas,
>
> thank you for bringing forward this issue.
>
> Which defconfig are you relating to?
[Tejas]:
Checking with xilinx_zynqmp_virt_defconfig
>
> >>
> >> Starting kernel ...
> >>
> >> efi_free_pool: illegal free 0x77830040
> >> efi_free_pool: illegal free 0x7782d040
> >> efi_free_pool: illegal free 0x7782c040
> >>
> >> The issue arises when the ramdisk image is relocated, placing it
> >> within the previously allocated EFI memory region( as EFI is
> >> established quite early in U-Boot).
>
> Which version of U-Boot are you on? Commit 06d514d77c37 ("lmb: consider EFI
> memory map") was meant to avoid such a situation.
[Tejas] :
I'm verifying against the latest changes in the master branch. The introduction
of commit 06d514d77c37 ("lmb: consider EFI memory map") has resolved the
occurrence of the "efi_free_pool: illegal free" error. but, it leads to a new
error, as detailed in the following patch:
https://lore.kernel.org/all/20230212150706.2967007-1-sjo...@collabora.com/
>
> >
> > I don't mind suppressing the print for some time, but out of
> > curiosity, how is the ramdisk relocated? LMB should be aware of the
> > EFI regions by then, so I assume the relocation code doesn't check
> > those?
[Tejas] : I observe that the relocation of the RAM disk is taking place in the
line below.
https://github.com/u-boot/u-boot/blob/master/lib/lmb.c#L480-L491
Yes, the relocated code specifically examines the LMB region and does not
consider the EFI region.
>
> The indicated situation is serious. If the EFI sub-system is using the same
> memory
> area as the ramdisk, this may lead to corruption of the ramdisk. Suppressing
> the
> messages is by no means adequate to solve the problem.
[Tejas] :
The challenge arises when relocating the ramdisk image, inserting it into the
previously assigned EFI memory region,
established early in U-Boot. Consequently, when attempting to release memory in
the EFI region during the handover
process to the kernel in the efi_free_pool function, we first verify if the
memory was allocated by efi_allocate_pool().
The issue originates from a checksum mismatch because, during the ramdisk
relocation, we overwrite memory allocated by EFI.
This leads to the appearance of the error message: efi_free_pool: illegal free
0x77830040.
Crucially, there is no corruption of the ramdisk seen since we do not actually
releasing memory due to the checksum mismatch.
In our testing, this issue was observed only when the ramdisk size exceeded
approximately 24 MB.
>
> Best regards
>
> Heinrich
>
>
> >
> > Thanks
> > /Ilias
> >
> >> Consequently, when
> >> attempting to release memory in the EFI memory region during the
> >> handover process to the kernel,we encounter memory violations.
> >>
> >> Highlighting that EFI remains active primarily during the booting of
> >> an EFI application, and the lmb persists while configuring images for
> >> the boot process. Since we aren't utilizing the EFI memory region
> >> during the boot process, there is no adverse impact even in the event
> >> of a violation.
> >>
> >> Currently, there is an ongoing discussion regarding the handling
> >> strategies of three memory allocators: malloc, lmb, and EFI. This
> >> discussion is documented in the email chain titled "Proposal: U-Boot
> >> memory management."
> >>
> >> Therefore, it is advisable to suppress the print message during the
> >> boot process for now.
> >>
> >> Signed-off-by: Tejas Bhumkar
> >> ---
> >> lib/efi_loader/efi_memory.c | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/lib/efi_loader/efi_memory.c
> >> b/lib/efi_loader/efi_memory.c index edfad2d95a..821fe7616e 100644
> >> --- a/lib/efi_loader/efi_memory.c
> >> +++ b/lib/efi_loader/efi_memory.c
> >> @@ -713,7 +713,7 @@ efi_status_t efi_free_pool(void *buffer)
> >> /* Check that this memory was allocated by efi_allocate_pool() */
> >> if (((uintptr_t)alloc & EFI_PAGE_MASK) ||
> >> alloc->checksum != checksum(alloc)) {
> >> - printf("%s: illegal free 0x%p\n", __func__, buffer);
> >> + debug("%s: illegal free 0x%p\n", __func__,
Re: [PATCH v3 4/6] rockchip: find U-boot proper boot device by inverting the logic that sets it
Hi Tom, On 1/22/24 18:54, Tom Rini wrote: On Mon, Jan 22, 2024 at 11:49:23AM +0100, Quentin Schulz wrote: Hi Kever, On 1/18/24 11:12, Kever Yang wrote: Hi Quentin, On 2024/1/18 01:22, Quentin Schulz wrote: From: Quentin Schulz BOOT_DEVICE_* is set by spl_node_to_boot_device() depending on the block device number associated with the MMC device the SPL used to load U-Boot proper from. It is NOT related to the mmc alias in the Device Tree. For SPI flashes, all SPI flashes will return BOOT_DEVICE_SPI so there's currently no way to know from which one the SPL loaded U-Boot proper from. Therefore, let's just find the first valid candidate in /chosen/u-boot,spl-boot-order that is a SPI flash and return that path. This is a best effort. While the original implementation may have worked, using the exact same mechanism but in inverted fashion makes it less likely to have surprising corner-cases or side-effects. A nice side-effect is that all existing and future Rockchip SoCs now automatically have their /chosen/u-boot,spl-boot-device set. Error happen in some 32bit SoC: +arch/arm/mach-rockchip/spl-boot-order.c: In function 'spl_perform_fixups': +arch/arm/mach-rockchip/spl-boot-order.c:242:31: error: 'struct spl_image_info' has no member named 'fdt_addr' + 242 | void *blob = spl_image->fdt_addr; + | ^~ +make[3]: *** [scripts/Makefile.build:257: spl/arch/arm/mach-rockchip/spl-boot-order.o] Error 1 It'd be nice to say **which** boards aren't working so that I can reproduce locally :) I eventually figured we have GitLab CI/CD for your maintainer branch/repo here: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines. This also helped me figure out this wasn't the only build failure and I could send another patch before you had the opportunity to tell me I had broken something else :) Giving the link of the failed pipeline would really help, please think about it for next time :) Thanks! For people interested in build-testing all Rockchip platforms locally, I used the following script: Please note that you can also build all of the rockchip platforms locally with: tools/buildman/buildman --allow-missing rk rv It won't be bootable as it will fake all require blobs, but all platforms will be built. And buildman can be told a number of things to be built, but "rockchip" only catches the cases where the board vendor is "rockhip" rather than ARCH_ROCKCHIP, but "rk" and "rv" catch all of the rk and rv SoCs. Ack, will be trying this one out, thanks for the heads up. FYI, it was also missing "px30" among the terms to pass to buildman. Now I get 101 boards, the same as with my script :) Cheers, Quentin
Re: [PATCH 18/18] board: rockchip: add Theobroma-Systems RK3588 Jaguar SBC
Hi all, On 1/23/24 15:49, Quentin Schulz wrote: From: Quentin Schulz JAGUAR is a Single-Board Computer (SBC) based around the rk3588 SoC and is targeting Autonomous Mobile Robots (AMR). It features: * LPDDR4X (up to 16GB) * 1Gbps Ethernet on RJ45 connector (KSZ9031 or KSZ9131) * PCIe 3.0 4-lane on M.2 M-key connector * PCIe 2.1 1-lane on M.2 E-key * USB 2.0 on M.2 E-key * 2x USB3 OTG type-c ports with DP Alt-Mode * USB2 host port * HDMI output * 2x camera connectors, each exposing: * 2-lane MIPI-CSI * 1v2, 1v8, 2v8 power rails * I2C bus * GPIOs * PPS input * CAN * RS485 UART * FAN connector * SD card slot * eMMC (up to 256GB) * RTC backup battery * Companion microcontroller * ISL1208 RTC emulation * AMC6821 PWM emulation * On/off buzzer control * Secure Element * 80-pin Mezzanine connector for daughterboards: * GPIOs * 1Gbps Ethernet * PCIe 2.1 1-lane * 2x 2-lane MIPI-CSI * ADC channel * I2C bus * PWM * UART * SPI * SDIO * CAN * I2S * 1v8, 3v3, 5v0, dc-in (12-24V) power rails The Device Tree comes from next-20240110 Linux kernel. Cc: Quentin Schulz Signed-off-by: Quentin Schulz --- I forgot to add the dtb rule to arch/arm/dts/Makefile but it still compiles somehow... Will give a few days to people to review the rest before sending a v2 to avoid too much unnecessary noise on the list. Cheers, Quentin
Re: [PATCH v7] fdt: Allow the devicetree to come from a bloblist
On Tue, Jan 23, 2024 at 11:27:57AM +, Conor Dooley wrote: > On Mon, Jan 22, 2024 at 06:55:01PM +, Conor Dooley wrote: > > On Mon, Jan 22, 2024 at 01:47:17PM -0500, Tom Rini wrote: > > > On Mon, Jan 22, 2024 at 06:36:31PM +, Conor Dooley wrote: > > > > Hey, > > > > > > > > On Tue, Jan 16, 2024 at 01:48:06PM +, Conor Dooley wrote: > > > > > Yo, > > > > > > > > > > On Wed, Jan 03, 2024 at 06:49:19PM -0700, Simon Glass wrote: > > > > > > Standard passage provides for a bloblist to be passed from one > > > > > > firmware > > > > > > phase to the next. That can be used to pass the devicetree along as > > > > > > well. > > > > > > Add an option to support this. > > > > > > > > > > > > Tests for this will be added as part of the Universal Payload work. > > > > > > > > > > > > Signed-off-by: Simon Glass > > > > > > > > > > Since this was merged into master, U-Boot is no longer booting on my > > > > > icicle kit (At least that's what my bisection tells me). This is a > > > > > RISC-V board and U-Boot for it is built from > > > > > microchip_mpfs_icicle_defconfig. > > > > > > > > > > There's zero output on the console from U-Boot at all, the last thing > > > > > that I see is OpenSBI before things grind to a halt. > > > > > > > > Just wondering if there's anything I can do to help this one along? > > > > Got a red CI complaining at me every morning about it :| > > > > > > Well, can you please look in to what part of this is causing the > > > failure? I don't really see what would have changed on > > > microchip_mpfs_icicle_defconfig from this as BLOBLIST isn't set before > > > nor after this change. > > > > Sure. I'll try to look into it more tomorrow. > > I gave it a try, it seems to be the FDTSRC_BLOBLIST additions that kill > it, not the actual code in fdtdec_setup(). Well that's very unexpected. Can you see what boundary we're crossing or whatever has overflowed now or something on your platform? -- Tom signature.asc Description: PGP signature
Re: [PATCH 02/16] xilinx_mbv: Remove empty config header
On Tue, Jan 23, 2024 at 08:53:21AM +0100, Michal Simek wrote: > > > On 1/22/24 23:39, Tom Rini wrote: > > Now that we support having CONFIG_SYS_CONFIG_NAME be unset to indicate a > > lack of board.h file, unset this on the xilinx_mbv platforms and remove > > the otherwise empty file. > > > > Signed-off-by: Tom Rini > > --- > > Cc: Michal Simek > > --- > > board/xilinx/mbv/Kconfig | 3 --- > > board/xilinx/mbv/MAINTAINERS | 1 - > > include/configs/xilinx_mbv.h | 6 -- > > 3 files changed, 10 deletions(-) > > delete mode 100644 include/configs/xilinx_mbv.h > > > > diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig > > index 4bc9f72c541b..d2dec397ed6f 100644 > > --- a/board/xilinx/mbv/Kconfig > > +++ b/board/xilinx/mbv/Kconfig > > @@ -9,9 +9,6 @@ config SYS_VENDOR > > config SYS_CPU > > default "generic" > > -config SYS_CONFIG_NAME > > - default "xilinx_mbv" > > - > > config TEXT_BASE > > default 0x8000 if !RISCV_SMODE > > default 0x8040 if RISCV_SMODE && ARCH_RV32I > > diff --git a/board/xilinx/mbv/MAINTAINERS b/board/xilinx/mbv/MAINTAINERS > > index 445654fe740e..db9f03388df9 100644 > > --- a/board/xilinx/mbv/MAINTAINERS > > +++ b/board/xilinx/mbv/MAINTAINERS > > @@ -4,4 +4,3 @@ S: Maintained > > F:arch/riscv/dts/xilinx-mbv* > > F:board/xilinx/mbv/ > > F:configs/xilinx_mbv* > > -F: include/configs/xilinx_mbv.h > > diff --git a/include/configs/xilinx_mbv.h b/include/configs/xilinx_mbv.h > > deleted file mode 100644 > > index dba398aeec49.. > > --- a/include/configs/xilinx_mbv.h > > +++ /dev/null > > @@ -1,6 +0,0 @@ > > -/* SPDX-License-Identifier: GPL-2.0 */ > > -/* > > - * (C) Copyright 2023, Advanced Micro Devices, Inc. > > - * > > - * Michal Simek > > - */ > > Acked-by: Michal Simek > > But maybe in future we need to revert this patch to add more options there. > Or do you plan to remove all of these configs? > I can imagine distro boot wiring but that can be done via vars file only but > it is not practical. Do you mean that plain text environment feels impractical for standard boot (which should be used instead of the pure scripts of distro_boot) ? -- Tom signature.asc Description: PGP signature
Re: [PATCH 01/20] Convert CONFIG_SPL_STACK to Kconfig
On Tue, Jan 23, 2024 at 11:53:18AM +0800, Kever Yang wrote: > Hi Tom, > > rk3036 only has small size internal sram, so it can only use very > simple SPL which only including dram init, and no SPL_FRAMEWORK > support. > In this convert, the CONFIG_SPL_STACK is lost for this SoC, any > suggestions on this kind of issue? Does this work? diff --git a/common/spl/Kconfig b/common/spl/Kconfig index e7b84fc1fa68..9deee0fdbea8 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -372,7 +372,8 @@ config SPL_SHARES_INIT_SP_ADDR config SPL_STACK hex "Initial stack pointer location" - depends on (ARM || ARCH_JZ47XX || MICROBLAZE || RISCV) && SPL_FRAMEWORK + depends on (ARM || ARCH_JZ47XX || MICROBLAZE || RISCV) && \ + SPL_FRAMEWORK || ROCKCHIP_RK3036 depends on !SPL_SHARES_INIT_SP_ADDR default 0x946bb8 if ARCH_MX7 default 0x93ffb8 if ARCH_MX6 && MX6_OCRAM_256KB You will have to update the ROCKCHIP_RK3036 platforms otherwise the build will hang now. -- Tom signature.asc Description: PGP signature
[PATCH] tools: buildman: fix non-existing SafeConfigParser in Python 3.12+
From: Quentin Schulz SafeConfigParser was renamed back in Python 3.2 (yes, no typo) to ConfigParser[1], but it was still working as an alias until it got removed in 3.12[2]. [1] https://docs.python.org/3.8/whatsnew/3.2.html#configparser [2] https://github.com/python/cpython/pull/92503 Cc: Quentin Schulz Signed-off-by: Quentin Schulz --- tools/buildman/bsettings.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/buildman/bsettings.py b/tools/buildman/bsettings.py index f7f8276e629..e225ac2ca0f 100644 --- a/tools/buildman/bsettings.py +++ b/tools/buildman/bsettings.py @@ -16,7 +16,7 @@ def setup(fname=''): global settings global config_fname -settings = configparser.SafeConfigParser() +settings = configparser.ConfigParser() if fname is not None: config_fname = fname if config_fname == '': --- base-commit: 15e7927b5a2d33666af19879577bf0c30ab088fe change-id: 20240123-safeconfigparser-778a81ef8f47 Best regards, -- Quentin Schulz
[PATCH v1 5/5] video: renesas: shift the init sequence by one step earlier
Shift all setup stages one step earlier to better fit the
existing uclass.
Signed-off-by: Svyatoslav Ryhel
---
drivers/video/renesas-r61307.c | 93 +++---
drivers/video/renesas-r69328.c | 81 +++--
2 files changed, 95 insertions(+), 79 deletions(-)
diff --git a/drivers/video/renesas-r61307.c b/drivers/video/renesas-r61307.c
index 426fdc6224..1eccaf6b1b 100644
--- a/drivers/video/renesas-r61307.c
+++ b/drivers/video/renesas-r61307.c
@@ -118,42 +118,6 @@ static struct display_timing default_timing = {
};
static int renesas_r61307_enable_backlight(struct udevice *dev)
-{
- struct renesas_r61307_priv *priv = dev_get_priv(dev);
- int ret;
-
- ret = regulator_set_enable_if_allowed(priv->vcc, 1);
- if (ret) {
- log_err("enabling vcc-supply failed (%d)\n", ret);
- return ret;
- }
- mdelay(5);
-
- ret = regulator_set_enable_if_allowed(priv->iovcc, 1);
- if (ret) {
- log_err("enabling iovcc-supply failed (%d)\n", ret);
- return ret;
- }
-
- ret = dm_gpio_set_value(>reset_gpio, 0);
- if (ret) {
- log_err("changing reset-gpio failed (%d)\n", ret);
- return ret;
- }
- mdelay(5);
-
- ret = dm_gpio_set_value(>reset_gpio, 1);
- if (ret) {
- log_err("changing reset-gpio failed (%d)\n", ret);
- return ret;
- }
-
- mdelay(5);
-
- return 0;
-}
-
-static int renesas_r61307_set_backlight(struct udevice *dev, int percent)
{
struct renesas_r61307_priv *priv = dev_get_priv(dev);
struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
@@ -205,18 +169,23 @@ static int renesas_r61307_set_backlight(struct udevice
*dev, int percent)
log_err("failed to set display on: %d\n", ret);
return ret;
}
-
mdelay(50);
+ return 0;
+}
+
+static int renesas_r61307_set_backlight(struct udevice *dev, int percent)
+{
+ struct renesas_r61307_priv *priv = dev_get_priv(dev);
+ int ret;
+
ret = backlight_enable(priv->backlight);
if (ret)
return ret;
- ret = backlight_set_brightness(priv->backlight, percent);
- if (ret)
- return ret;
+ mdelay(5);
- return 0;
+ return backlight_set_brightness(priv->backlight, percent);
}
static int renesas_r61307_timings(struct udevice *dev,
@@ -266,6 +235,46 @@ static int renesas_r61307_of_to_plat(struct udevice *dev)
return 0;
}
+static int renesas_r61307_hw_init(struct udevice *dev)
+{
+ struct renesas_r61307_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = regulator_set_enable_if_allowed(priv->vcc, 1);
+ if (ret) {
+ log_debug("%s: enabling vcc-supply failed (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+ mdelay(5);
+
+ ret = regulator_set_enable_if_allowed(priv->iovcc, 1);
+ if (ret) {
+ log_debug("%s: enabling iovcc-supply failed (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = dm_gpio_set_value(>reset_gpio, 0);
+ if (ret) {
+ log_debug("%s: changing reset-gpio failed (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+ mdelay(5);
+
+ ret = dm_gpio_set_value(>reset_gpio, 1);
+ if (ret) {
+ log_debug("%s: changing reset-gpio failed (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+
+ mdelay(5);
+
+ return 0;
+}
+
static int renesas_r61307_probe(struct udevice *dev)
{
struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
@@ -275,7 +284,7 @@ static int renesas_r61307_probe(struct udevice *dev)
plat->format = MIPI_DSI_FMT_RGB888;
plat->mode_flags = MIPI_DSI_MODE_VIDEO;
- return 0;
+ return renesas_r61307_hw_init(dev);
}
static const struct panel_ops renesas_r61307_ops = {
diff --git a/drivers/video/renesas-r69328.c b/drivers/video/renesas-r69328.c
index d2f7169468..ecf89ec021 100644
--- a/drivers/video/renesas-r69328.c
+++ b/drivers/video/renesas-r69328.c
@@ -65,37 +65,6 @@ static struct display_timing default_timing = {
static int renesas_r69328_enable_backlight(struct udevice *dev)
{
- struct renesas_r69328_priv *priv = dev_get_priv(dev);
- int ret;
-
- ret = dm_gpio_set_value(>enable_gpio, 1);
- if (ret) {
- log_err("error changing enable-gpios (%d)\n", ret);
- return ret;
- }
- mdelay(5);
-
- ret = dm_gpio_set_value(>reset_gpio, 0);
- if (ret) {
- log_err("error changing reset-gpios (%d)\n", ret);
- return ret;
- }
- mdelay(5);
-
- ret = dm_gpio_set_value(>reset_gpio, 1);
- if (ret) {
-
[PATCH v1 4/5] video: bridge: ssd2825: shift the init sequence by one step earlier
Shift all setup stages one step earlier to better fit the
existing uclass.
Signed-off-by: Svyatoslav Ryhel
---
drivers/video/bridge/ssd2825.c | 82 +++---
1 file changed, 46 insertions(+), 36 deletions(-)
diff --git a/drivers/video/bridge/ssd2825.c b/drivers/video/bridge/ssd2825.c
index cea20dcffa..9783e9e05a 100644
--- a/drivers/video/bridge/ssd2825.c
+++ b/drivers/video/bridge/ssd2825.c
@@ -351,38 +351,6 @@ static int ssd2825_bridge_enable_panel(struct udevice *dev)
struct display_timing *dt = >timing;
int ret;
- ret = clk_prepare_enable(priv->tx_clk);
- if (ret) {
- log_err("error enabling tx_clk (%d)\n", ret);
- return ret;
- }
-
- ret = dm_gpio_set_value(>power_gpio, 1);
- if (ret) {
- log_err("error changing power-gpios (%d)\n", ret);
- return ret;
- }
- mdelay(10);
-
- ret = dm_gpio_set_value(>reset_gpio, 0);
- if (ret) {
- log_err("error changing reset-gpios (%d)\n", ret);
- return ret;
- }
- mdelay(10);
-
- ret = dm_gpio_set_value(>reset_gpio, 1);
- if (ret) {
- log_err("error changing reset-gpios (%d)\n", ret);
- return ret;
- }
- mdelay(10);
-
- /* Perform panel HW setup */
- ret = panel_enable_backlight(priv->panel);
- if (ret)
- return ret;
-
/* Perform SW reset */
ssd2825_write_register(dev, SSD2825_OPERATION_CTRL_REG, 0x0100);
@@ -417,8 +385,8 @@ static int ssd2825_bridge_enable_panel(struct udevice *dev)
SSD2825_CONF_REG_ECD | SSD2825_CONF_REG_EOT);
ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x);
- /* Set up SW panel configuration */
- ret = panel_set_backlight(priv->panel, BACKLIGHT_DEFAULT);
+ /* Perform panel setup */
+ ret = panel_enable_backlight(priv->panel);
if (ret)
return ret;
@@ -427,7 +395,10 @@ static int ssd2825_bridge_enable_panel(struct udevice *dev)
static int ssd2825_bridge_set_panel(struct udevice *dev, int percent)
{
- return 0;
+ struct ssd2825_bridge_priv *priv = dev_get_priv(dev);
+
+ /* Set up SW panel configuration */
+ return panel_set_backlight(priv->panel, percent);
}
static int ssd2825_bridge_panel_timings(struct udevice *dev,
@@ -440,6 +411,45 @@ static int ssd2825_bridge_panel_timings(struct udevice
*dev,
return 0;
}
+static int ssd2825_bridge_hw_init(struct udevice *dev)
+{
+ struct ssd2825_bridge_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = clk_prepare_enable(priv->tx_clk);
+ if (ret) {
+ log_debug("%s: error enabling tx_clk (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = dm_gpio_set_value(>power_gpio, 1);
+ if (ret) {
+ log_debug("%s: error changing power-gpios (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+ mdelay(10);
+
+ ret = dm_gpio_set_value(>reset_gpio, 0);
+ if (ret) {
+ log_debug("%s: error changing reset-gpios (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+ mdelay(10);
+
+ ret = dm_gpio_set_value(>reset_gpio, 1);
+ if (ret) {
+ log_debug("%s: error changing reset-gpios (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+ mdelay(10);
+
+ return 0;
+}
+
static int ssd2825_bridge_probe(struct udevice *dev)
{
struct ssd2825_bridge_priv *priv = dev_get_priv(dev);
@@ -496,7 +506,7 @@ static int ssd2825_bridge_probe(struct udevice *dev)
return PTR_ERR(priv->tx_clk);
}
- return 0;
+ return ssd2825_bridge_hw_init(dev);
}
static const struct panel_ops ssd2825_bridge_ops = {
--
2.40.1
[PATCH v1 3/5] video: endeavoru-panel: shift the init sequence by one step earlier
Shift all setup stages one step earlier to better fit the
existing uclass.
Signed-off-by: Svyatoslav Ryhel
---
drivers/video/endeavoru-panel.c | 128 +---
1 file changed, 68 insertions(+), 60 deletions(-)
diff --git a/drivers/video/endeavoru-panel.c b/drivers/video/endeavoru-panel.c
index 79a272128b..1bff641434 100644
--- a/drivers/video/endeavoru-panel.c
+++ b/drivers/video/endeavoru-panel.c
@@ -57,61 +57,8 @@ static void dcs_write_one(struct mipi_dsi_device *dsi, u8
cmd, u8 data)
static int endeavoru_panel_enable_backlight(struct udevice *dev)
{
- struct endeavoru_panel_priv *priv = dev_get_priv(dev);
- int ret;
-
- ret = dm_gpio_set_value(>reset_gpio, 1);
- if (ret) {
- log_err("error changing reset-gpios (%d)\n", ret);
- return ret;
- }
- mdelay(5);
-
- ret = regulator_set_enable_if_allowed(priv->vddio, 1);
- if (ret) {
- log_err("error enabling iovcc-supply (%d)\n", ret);
- return ret;
- }
- mdelay(1);
-
- ret = regulator_set_enable_if_allowed(priv->vdd, 1);
- if (ret) {
- log_err("error enabling vcc-supply (%d)\n", ret);
- return ret;
- }
- mdelay(20);
-
- ret = dm_gpio_set_value(>reset_gpio, 0);
- if (ret) {
- log_err("error changing reset-gpios (%d)\n", ret);
- return ret;
- }
- mdelay(2);
-
- /* Reset panel */
- ret = dm_gpio_set_value(>reset_gpio, 1);
- if (ret) {
- log_err("error changing reset-gpios (%d)\n", ret);
- return ret;
- }
- mdelay(1);
-
- ret = dm_gpio_set_value(>reset_gpio, 0);
- if (ret) {
- log_err("error changing reset-gpios (%d)\n", ret);
- return ret;
- }
- mdelay(25);
-
- return 0;
-}
-
-static int endeavoru_panel_set_backlight(struct udevice *dev, int percent)
-{
- struct endeavoru_panel_priv *priv = dev_get_priv(dev);
struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
struct mipi_dsi_device *dsi = plat->device;
- int ret;
dcs_write_one(dsi, 0xc2, 0x08);
@@ -160,18 +107,22 @@ static int endeavoru_panel_set_backlight(struct udevice
*dev, int percent)
dcs_write_one(dsi, 0x55, 0x80);
dcs_write_one(dsi, 0x5e, 0x06);
- ret = backlight_enable(priv->backlight);
- if (ret)
- return ret;
-
/* Set backlight */
dcs_write_one(dsi, 0x51, 0x96);
- ret = backlight_set_brightness(priv->backlight, percent);
+ return 0;
+}
+
+static int endeavoru_panel_set_backlight(struct udevice *dev, int percent)
+{
+ struct endeavoru_panel_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = backlight_enable(priv->backlight);
if (ret)
return ret;
- return 0;
+ return backlight_set_brightness(priv->backlight, percent);
}
static int endeavoru_panel_timings(struct udevice *dev,
@@ -217,6 +168,63 @@ static int endeavoru_panel_of_to_plat(struct udevice *dev)
return 0;
}
+static int endeavoru_panel_hw_init(struct udevice *dev)
+{
+ struct endeavoru_panel_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = dm_gpio_set_value(>reset_gpio, 1);
+ if (ret) {
+ log_debug("%s: error changing reset-gpios (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+ mdelay(5);
+
+ ret = regulator_set_enable_if_allowed(priv->vddio, 1);
+ if (ret) {
+ log_debug("%s: error enabling iovcc-supply (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+ mdelay(1);
+
+ ret = regulator_set_enable_if_allowed(priv->vdd, 1);
+ if (ret) {
+ log_debug("%s: error enabling vcc-supply (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+ mdelay(20);
+
+ ret = dm_gpio_set_value(>reset_gpio, 0);
+ if (ret) {
+ log_debug("%s: error changing reset-gpios (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+ mdelay(2);
+
+ /* Reset panel */
+ ret = dm_gpio_set_value(>reset_gpio, 1);
+ if (ret) {
+ log_debug("%s: error changing reset-gpios (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+ mdelay(1);
+
+ ret = dm_gpio_set_value(>reset_gpio, 0);
+ if (ret) {
+ log_debug("%s: error changing reset-gpios (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+ mdelay(25);
+
+ return 0;
+}
+
static int endeavoru_panel_probe(struct udevice *dev)
{
struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
@@ -226,7 +234,7 @@ static int endeavoru_panel_probe(struct udevice
[PATCH v1 2/5] video: panel: add Samsung LTL106HL02 MIPI DSI panel driver
From: Anton Bambura
LTL106HL02 is a color active matrix TFT (Thin Film Transistor)
liquid crystal display (LCD) that uses amorphous silicon TFT as
switching devices. This model is composed of a TFT LCD panel, a
driver circuit and a backlight unit. The resolution of a 10.6"
contains 1920 x 1080 pixels and can display up to 16,8M color
with wide viewing angle.
Co-developed-by: Jonas Schwöbel
Signed-off-by: Jonas Schwöbel
Co-developed-by: Svyatoslav Ryhel
Signed-off-by: Svyatoslav Ryhel
Signed-off-by: Anton Bambura
---
drivers/video/Kconfig | 9 ++
drivers/video/Makefile | 1 +
drivers/video/samsung-ltl106hl02.c | 157 +
3 files changed, 167 insertions(+)
create mode 100644 drivers/video/samsung-ltl106hl02.c
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 05567a0095..52b515197d 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -555,6 +555,15 @@ config VIDEO_LCD_RENESAS_R69328
IPS-LCD module with Renesas R69328 IC. The panel has a 720x1280
resolution and uses 24 bit RGB per pixel.
+config VIDEO_LCD_SAMSUNG_LTL106HL02
+ tristate "Samsung LTL106HL02 1920x1080 DSI video mode panel"
+ depends on PANEL && BACKLIGHT
+ select VIDEO_MIPI_DSI
+ help
+ Say Y here if you want to enable support for Samsung LTL106HL02
+ LCD module found in Microsoft Surface 2. The panel has a FullHD
+ resolution (1920x1080).
+
config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
---help---
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index bb6d9b74b9..f3f70cd04a 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -63,6 +63,7 @@ obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) +=
orisetech_otm8009a.o
obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
obj-$(CONFIG_VIDEO_LCD_RENESAS_R61307) += renesas-r61307.o
obj-$(CONFIG_VIDEO_LCD_RENESAS_R69328) += renesas-r69328.o
+obj-$(CONFIG_VIDEO_LCD_SAMSUNG_LTL106HL02) += samsung-ltl106hl02.o
obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o
obj-$(CONFIG_VIDEO_MCDE_SIMPLE) += mcde_simple.o
diff --git a/drivers/video/samsung-ltl106hl02.c
b/drivers/video/samsung-ltl106hl02.c
new file mode 100644
index 00..5e6c11c4be
--- /dev/null
+++ b/drivers/video/samsung-ltl106hl02.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Samsung LTL106HL02-001 DSI panel driver
+ *
+ * Copyright (c) 2020 Anton Bambura
+ * Copyright (c) 2023 Svyatoslav Ryhel
+ * Copyright (c) 2024 Jonas Schwöbel
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct samsung_ltl106hl02_priv {
+ struct udevice *vdd;
+ struct udevice *backlight;
+
+ struct gpio_desc reset_gpio;
+};
+
+static struct display_timing default_timing = {
+ .pixelclock.typ = 13700,
+ .hactive.typ= 1920,
+ .hfront_porch.typ = 32,
+ .hback_porch.typ= 64,
+ .hsync_len.typ = 32,
+ .vactive.typ= 1080,
+ .vfront_porch.typ = 2,
+ .vback_porch.typ= 26,
+ .vsync_len.typ = 3,
+};
+
+static int samsung_ltl106hl02_enable_backlight(struct udevice *dev)
+{
+ struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+ struct mipi_dsi_device *dsi = plat->device;
+ int ret;
+
+ ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+ if (ret < 0) {
+ log_debug("%s: failed to exit sleep mode: %d\n",
+ __func__, ret);
+ return ret;
+ }
+ mdelay(70);
+
+ ret = mipi_dsi_dcs_set_display_on(dsi);
+ if (ret < 0) {
+ log_debug("%s: failed to enable display: %d\n",
+ __func__, ret);
+ return ret;
+ }
+ mdelay(5);
+
+ return 0;
+}
+
+static int samsung_ltl106hl02_set_backlight(struct udevice *dev, int percent)
+{
+ struct samsung_ltl106hl02_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = backlight_enable(priv->backlight);
+ if (ret)
+ return ret;
+
+ return backlight_set_brightness(priv->backlight, percent);
+}
+
+static int samsung_ltl106hl02_timings(struct udevice *dev,
+ struct display_timing *timing)
+{
+ memcpy(timing, _timing, sizeof(*timing));
+ return 0;
+}
+
+static int samsung_ltl106hl02_of_to_plat(struct udevice *dev)
+{
+ struct samsung_ltl106hl02_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
+ "backlight", >backlight);
+ if (ret) {
+ log_debug("%s: cannot get backlight: ret = %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret =
[PATCH v1 1/5] video: panel: add LG LG070WX3 MIPI DSI panel driver
The LD070WX3 is a Color Active Matrix Liquid Crystal Display with
an integral Light Emitting Diode (LED) backlight system. The
matrix employs a-Si Thin Film Transistor as the active element. It
is a transmissive type display operating in the normally Black
mode. This TFT-LCD has 7.0 inches diagonally measured active
display area with WXGA resolution (800 by 1280 pixel array).
Signed-off-by: Svyatoslav Ryhel
---
drivers/video/Kconfig | 8 ++
drivers/video/Makefile | 1 +
drivers/video/lg-ld070wx3.c | 186
3 files changed, 195 insertions(+)
create mode 100644 drivers/video/lg-ld070wx3.c
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index e2016d73d1..05567a0095 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -522,6 +522,14 @@ config VIDEO_LCD_ORISETECH_OTM8009A
Say Y here if you want to enable support for Orise Technology
otm8009a 480x800 dsi 2dl panel.
+config VIDEO_LCD_LG_LD070WX3
+ bool "LD070WX3 DSI LCD panel support"
+ depends on PANEL && BACKLIGHT
+ select VIDEO_MIPI_DSI
+ help
+ Say Y here if you want to enable support for LG LD070WX3
+ 800x1280 DSI video mode panel.
+
config VIDEO_LCD_RAYDIUM_RM68200
bool "RM68200 DSI LCD panel support"
select VIDEO_MIPI_DSI
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index fdc2937632..bb6d9b74b9 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -58,6 +58,7 @@ obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
obj-$(CONFIG_VIDEO_LCD_ENDEAVORU) += endeavoru-panel.o
obj-$(CONFIG_VIDEO_LCD_HIMAX_HX8394) += himax-hx8394.o
obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
+obj-$(CONFIG_VIDEO_LCD_LG_LD070WX3) += lg-ld070wx3.o
obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
obj-$(CONFIG_VIDEO_LCD_RENESAS_R61307) += renesas-r61307.o
diff --git a/drivers/video/lg-ld070wx3.c b/drivers/video/lg-ld070wx3.c
new file mode 100644
index 00..610a06ffe7
--- /dev/null
+++ b/drivers/video/lg-ld070wx3.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * LG LD070WX3-SL01 DSI panel driver
+ *
+ * Copyright (c) 2023 Svyatoslav Ryhel
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct lg_ld070wx3_priv {
+ struct udevice *vdd;
+ struct udevice *vcc;
+
+ struct udevice *backlight;
+};
+
+static struct display_timing default_timing = {
+ .pixelclock.typ = 7000,
+ .hactive.typ= 800,
+ .hfront_porch.typ = 32,
+ .hback_porch.typ= 48,
+ .hsync_len.typ = 8,
+ .vactive.typ= 1280,
+ .vfront_porch.typ = 5,
+ .vback_porch.typ= 3,
+ .vsync_len.typ = 1,
+};
+
+static void dcs_write_one(struct mipi_dsi_device *dsi, u8 cmd, u8 data)
+{
+ mipi_dsi_dcs_write(dsi, cmd, , 1);
+}
+
+static int lg_ld070wx3_enable_backlight(struct udevice *dev)
+{
+ struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+ struct mipi_dsi_device *dsi = plat->device;
+ int ret;
+
+ ret = mipi_dsi_dcs_soft_reset(dsi);
+ if (ret < 0) {
+ log_debug("%s: failed to soft reset panel: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ /* Delay before sending new command after soft reset */
+ mdelay(20);
+
+ /* Differential input impedance selection */
+ dcs_write_one(dsi, 0xAE, 0x0B);
+
+ /* Enter test mode 1 and 2*/
+ dcs_write_one(dsi, 0xEE, 0xEA);
+ dcs_write_one(dsi, 0xEF, 0x5F);
+
+ /* Increased MIPI CLK driving ability */
+ dcs_write_one(dsi, 0xF2, 0x68);
+
+ /* Exit test mode 1 and 2 */
+ dcs_write_one(dsi, 0xEE, 0x00);
+ dcs_write_one(dsi, 0xEF, 0x00);
+
+ return 0;
+}
+
+static int lg_ld070wx3_set_backlight(struct udevice *dev, int percent)
+{
+ struct lg_ld070wx3_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = backlight_enable(priv->backlight);
+ if (ret)
+ return ret;
+
+ return backlight_set_brightness(priv->backlight, percent);
+}
+
+static int lg_ld070wx3_timings(struct udevice *dev,
+ struct display_timing *timing)
+{
+ memcpy(timing, _timing, sizeof(*timing));
+ return 0;
+}
+
+static int lg_ld070wx3_of_to_plat(struct udevice *dev)
+{
+ struct lg_ld070wx3_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
+ "backlight", >backlight);
+ if (ret) {
+ log_debug("%s: cannot get backlight: ret = %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret =
[PATCH v1 0/5] Tegra panel improvements
The current patch set improves the logic of existing panels and bridge used by Tegra 3 devices and brings support for additional DSI panels used by Tegra 4 devices. New and existing drivers are fully reusable, contain no device specific parts, and are written according to existing datasheets. Anton Bambura (1): video: panel: add Samsung LTL106HL02 MIPI DSI panel driver Svyatoslav Ryhel (4): video: panel: add LG LG070WX3 MIPI DSI panel driver video: endeavoru-panel: shift the init sequence by one step earlier video: bridge: ssd2825: shift the init sequence by one step earlier video: renesas: shift the init sequence by one step earlier drivers/video/Kconfig | 17 +++ drivers/video/Makefile | 2 + drivers/video/bridge/ssd2825.c | 82 +++-- drivers/video/endeavoru-panel.c| 128 ++-- drivers/video/lg-ld070wx3.c| 186 + drivers/video/renesas-r61307.c | 93 --- drivers/video/renesas-r69328.c | 81 +++-- drivers/video/samsung-ltl106hl02.c | 157 8 files changed, 571 insertions(+), 175 deletions(-) create mode 100644 drivers/video/lg-ld070wx3.c create mode 100644 drivers/video/samsung-ltl106hl02.c -- 2.40.1
[PATCH v6 17/18] video: tegra20: dsi: set correct fifo depth
From: Jonas Schwöbel According to Thierry Reding's commit in the linux kernel 976cebc35bed0456a42bf96073a26f251d23b264 "drm/tegra: dsi: Make FIFO depths host parameters" correct depth of the video FIFO is 1920 *words* no *bytes* Tested-by: Ion Agorria # HTC One X Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114 Signed-off-by: Jonas Schwöbel Signed-off-by: Svyatoslav Ryhel --- drivers/video/tegra20/tegra-dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/tegra20/tegra-dsi.c b/drivers/video/tegra20/tegra-dsi.c index ddd74540f2..7d63557d1b 100644 --- a/drivers/video/tegra20/tegra-dsi.c +++ b/drivers/video/tegra20/tegra-dsi.c @@ -873,7 +873,7 @@ static int tegra_dsi_bridge_probe(struct udevice *dev) return -EINVAL; } - priv->video_fifo_depth = 480; + priv->video_fifo_depth = 1920; priv->host_fifo_depth = 64; ret = reset_get_by_name(dev, "dsi", _ctl); -- 2.40.1
[PATCH v6 18/18] video: tegra20: dsi: use set_backlight for backlight only
From: Jonas Schwöbel
Shift the backlight set further to prevent visual glitches on
panel init.
Signed-off-by: Jonas Schwöbel
Signed-off-by: Svyatoslav Ryhel
---
drivers/video/tegra20/tegra-dsi.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/video/tegra20/tegra-dsi.c
b/drivers/video/tegra20/tegra-dsi.c
index 7d63557d1b..13dae37806 100644
--- a/drivers/video/tegra20/tegra-dsi.c
+++ b/drivers/video/tegra20/tegra-dsi.c
@@ -766,10 +766,6 @@ static int tegra_dsi_encoder_enable(struct udevice *dev)
if (ret)
return ret;
- ret = panel_set_backlight(priv->panel, BACKLIGHT_DEFAULT);
- if (ret)
- return ret;
-
tegra_dsi_configure(dev, device->mode_flags);
tegra_dc_enable_controller(dev);
@@ -784,8 +780,10 @@ static int tegra_dsi_encoder_enable(struct udevice *dev)
static int tegra_dsi_bridge_set_panel(struct udevice *dev, int percent)
{
- /* Is not used in tegra dc */
- return 0;
+ struct tegra_dsi_priv *priv = dev_get_priv(dev);
+
+ /* Turn on/off backlight */
+ return panel_set_backlight(priv->panel, percent);
}
static int tegra_dsi_panel_timings(struct udevice *dev,
--
2.40.1
[PATCH v6 16/18] video: tegra20: dsi: remove pre-configuration
From: Jonas Schwöbel Configuration for DC driver command mode is not required for every panel. Removed. Tested-by: Ion Agorria # HTC One X Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114 Signed-off-by: Jonas Schwöbel Signed-off-by: Svyatoslav Ryhel --- drivers/video/tegra20/tegra-dsi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/video/tegra20/tegra-dsi.c b/drivers/video/tegra20/tegra-dsi.c index fc9ca1310a..ddd74540f2 100644 --- a/drivers/video/tegra20/tegra-dsi.c +++ b/drivers/video/tegra20/tegra-dsi.c @@ -766,8 +766,6 @@ static int tegra_dsi_encoder_enable(struct udevice *dev) if (ret) return ret; - tegra_dsi_configure(dev, 0); - ret = panel_set_backlight(priv->panel, BACKLIGHT_DEFAULT); if (ret) return ret; -- 2.40.1
[PATCH v6 15/18] video: tegra20: dsi: add reset support
Implement reset use to discard any changes which could have been
applied to DSI before and can interfere with current configuration.
Tested-by: Ion Agorria # HTC One X
Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel
---
drivers/video/tegra20/tegra-dsi.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/video/tegra20/tegra-dsi.c
b/drivers/video/tegra20/tegra-dsi.c
index 25a629535e..fc9ca1310a 100644
--- a/drivers/video/tegra20/tegra-dsi.c
+++ b/drivers/video/tegra20/tegra-dsi.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -863,6 +864,7 @@ static int tegra_dsi_bridge_probe(struct udevice *dev)
struct tegra_dsi_priv *priv = dev_get_priv(dev);
struct mipi_dsi_device *device = >device;
struct mipi_dsi_panel_plat *mipi_plat;
+ struct reset_ctl reset_ctl;
int ret;
priv->version = dev_get_driver_data(dev);
@@ -876,6 +878,13 @@ static int tegra_dsi_bridge_probe(struct udevice *dev)
priv->video_fifo_depth = 480;
priv->host_fifo_depth = 64;
+ ret = reset_get_by_name(dev, "dsi", _ctl);
+ if (ret) {
+ log_debug("%s: reset_get_by_name() failed: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
"avdd-dsi-csi-supply", >avdd);
if (ret)
@@ -914,12 +923,17 @@ static int tegra_dsi_bridge_probe(struct udevice *dev)
tegra_dsi_get_format(device->format, >format);
+ reset_assert(_ctl);
+
ret = regulator_set_enable_if_allowed(priv->avdd, true);
if (ret && ret != -ENOSYS)
return ret;
tegra_dsi_init_clocks(dev);
+ mdelay(2);
+ reset_deassert(_ctl);
+
return 0;
}
--
2.40.1
[PATCH v6 14/18] video: tegra20: dsi: add T114 support
Existing Tegra DSI driver mostly fits T114 apart MIPI calibration
which on T114 has dedicated driver. To resolve this MIPI calibration
logic was split for pre-T114 and T114+ devices.
Tested-by: Ion Agorria # HTC One X
Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel
---
drivers/video/tegra20/tegra-dsi.c | 78 ++-
.../video/tegra20/tegra-dsi.h | 24 +-
2 files changed, 96 insertions(+), 6 deletions(-)
rename arch/arm/include/asm/arch-tegra30/dsi.h =>
drivers/video/tegra20/tegra-dsi.h (90%)
diff --git a/drivers/video/tegra20/tegra-dsi.c
b/drivers/video/tegra20/tegra-dsi.c
index de225ed376..25a629535e 100644
--- a/drivers/video/tegra20/tegra-dsi.c
+++ b/drivers/video/tegra20/tegra-dsi.c
@@ -20,17 +20,24 @@
#include
#include
#include
-#include
#include "tegra-dc.h"
+#include "tegra-dsi.h"
#include "mipi-phy.h"
+/* List of supported DSI bridges */
+enum {
+ DSI_V0,
+ DSI_V1,
+};
+
struct tegra_dsi_priv {
struct mipi_dsi_host host;
struct mipi_dsi_device device;
struct mipi_dphy_timing dphy_timing;
struct udevice *panel;
+ struct udevice *mipi;
struct display_timing timing;
struct dsi_ctlr *dsi;
@@ -41,6 +48,8 @@ struct tegra_dsi_priv {
int dsi_clk;
int video_fifo_depth;
int host_fifo_depth;
+
+ u32 version;
};
static void tegra_dc_enable_controller(struct udevice *dev)
@@ -501,6 +510,41 @@ static void tegra_dsi_pad_calibrate(struct
dsi_pad_ctrl_reg *pad)
writel(value, TEGRA_VI_BASE + (CSI_CIL_PAD_CONFIG << 2));
}
+static void tegra_dsi_mipi_calibrate(struct tegra_dsi_priv *priv)
+{
+ struct dsi_pad_ctrl_reg *pad = >dsi->pad;
+ u32 value;
+ int ret;
+
+ ret = misc_set_enabled(priv->mipi, true);
+ if (ret)
+ log_debug("%s: failed to enable MIPI calibration: %d\n",
+ __func__, ret);
+
+ writel(0, >pad_ctrl);
+ writel(0, >pad_ctrl_1);
+ writel(0, >pad_ctrl_2);
+ writel(0, >pad_ctrl_3);
+ writel(0, >pad_ctrl_4);
+
+ /* DSI pad enable */
+ value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
+ writel(value, >pad_ctrl);
+
+ value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
+ DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
+ DSI_PAD_OUT_CLK(0x0);
+ writel(value, >pad_ctrl_2);
+
+ value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
+ DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
+ writel(value, >pad_ctrl_3);
+
+ ret = misc_write(priv->mipi, 0, NULL, 0);
+ if (ret)
+ log_debug("%s: MIPI calibration failed %d\n", __func__, ret);
+}
+
static void tegra_dsi_set_timeout(struct dsi_timeout_reg *rtimeout,
unsigned long bclk,
unsigned int vrefresh)
@@ -664,10 +708,25 @@ static int tegra_dsi_encoder_enable(struct udevice *dev)
u32 value;
int ret;
+ /* If for some reasone DSI is enabled then it needs to
+* be disabled in order for the panel initialization
+* commands to be properly sent.
+*/
+ value = readl(>dsi_pwr_ctrl);
+
+ if (value & DSI_POWER_CONTROL_ENABLE) {
+ value = readl(>dsi_pwr_ctrl);
+ value &= ~DSI_POWER_CONTROL_ENABLE;
+ writel(value, >dsi_pwr_ctrl);
+ }
+
/* Disable interrupt */
writel(0, >int_enable);
- tegra_dsi_pad_calibrate(>dsi->pad);
+ if (priv->version)
+ tegra_dsi_mipi_calibrate(priv);
+ else
+ tegra_dsi_pad_calibrate(>dsi->pad);
tegra_dsi_get_muldiv(device->format, , );
@@ -806,6 +865,8 @@ static int tegra_dsi_bridge_probe(struct udevice *dev)
struct mipi_dsi_panel_plat *mipi_plat;
int ret;
+ priv->version = dev_get_driver_data(dev);
+
priv->dsi = (struct dsi_ctlr *)dev_read_addr_ptr(dev);
if (!priv->dsi) {
printf("%s: No display controller address\n", __func__);
@@ -828,6 +889,16 @@ static int tegra_dsi_bridge_probe(struct udevice *dev)
return log_ret(ret);
}
+ if (priv->version) {
+ ret = uclass_get_device_by_phandle(UCLASS_MISC, dev,
+ "nvidia,mipi-calibrate",
+ >mipi);
+ if (ret) {
+ log_debug("%s: cannot get MIPI: error %d\n", __func__,
ret);
+ return ret;
+ }
+ }
+
panel_get_display_timing(priv->panel, >timing);
mipi_plat = dev_get_plat(priv->panel);
@@ -859,7 +930,8 @@ static const struct panel_ops tegra_dsi_bridge_ops = {
};
static const struct udevice_id tegra_dsi_bridge_ids[] = {
- {
[PATCH v6 13/18] video: tegra20: add MIPI calibration driver
Dedicated MIPI calibration driver is used on T114 and newer. Before
T114 MIPI calibration registers were part of VI and CSI.
Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel
---
drivers/video/tegra20/Makefile | 2 +-
drivers/video/tegra20/tegra-mipi.c | 188 +
2 files changed, 189 insertions(+), 1 deletion(-)
create mode 100644 drivers/video/tegra20/tegra-mipi.c
diff --git a/drivers/video/tegra20/Makefile b/drivers/video/tegra20/Makefile
index f0b534c579..a75aea2a87 100644
--- a/drivers/video/tegra20/Makefile
+++ b/drivers/video/tegra20/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
obj-$(CONFIG_VIDEO_TEGRA20) += tegra-dc.o
-obj-$(CONFIG_VIDEO_DSI_TEGRA30) += tegra-dsi.o mipi-phy.o
+obj-$(CONFIG_VIDEO_DSI_TEGRA30) += tegra-dsi.o tegra-mipi.o mipi-phy.o
obj-$(CONFIG_TEGRA_BACKLIGHT_PWM) += tegra-pwm-backlight.o
diff --git a/drivers/video/tegra20/tegra-mipi.c
b/drivers/video/tegra20/tegra-mipi.c
new file mode 100644
index 00..2df3c1a994
--- /dev/null
+++ b/drivers/video/tegra20/tegra-mipi.c
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013 NVIDIA Corporation
+ * Copyright (c) 2023 Svyatoslav Ryhel
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+/* MIPI control registers 0x00 ~ 0x60 */
+struct mipi_ctlr {
+ uint mipi_cal_ctrl;
+ uint mipi_cal_autocal_ctrl;
+ uint mipi_cal_status;
+
+ uint unused1[2];
+
+ uint mipi_cal_config_csia;
+ uint mipi_cal_config_csib;
+ uint mipi_cal_config_csic;
+ uint mipi_cal_config_csid;
+ uint mipi_cal_config_csie;
+
+ uint unused2[4];
+
+ uint mipi_cal_config_dsia;
+ uint mipi_cal_config_dsib;
+ uint mipi_cal_config_dsic;
+ uint mipi_cal_config_dsid;
+
+ uint unused3[4];
+
+ uint mipi_cal_bias_pad_cfg0;
+ uint mipi_cal_bias_pad_cfg1;
+ uint mipi_cal_bias_pad_cfg2;
+};
+
+#define MIPI_CAL_CTRL_NOISE_FILTER(x) (((x) & 0xf) << 26)
+#define MIPI_CAL_CTRL_PRESCALE(x) (((x) & 0x3) << 24)
+#define MIPI_CAL_CTRL_CLKEN_OVRBIT(4)
+#define MIPI_CAL_CTRL_STARTBIT(0)
+
+#define MIPI_CAL_STATUS_DONE BIT(16)
+#define MIPI_CAL_STATUS_ACTIVE BIT(0)
+
+#define MIPI_CAL_OVERIDE(x)(((x) & 0x1) << 30)
+#define MIPI_CAL_SEL(x)(((x) & 0x1) << 21)
+#define MIPI_CAL_HSPDOS(x) (((x) & 0x1f) << 16)
+#define MIPI_CAL_HSPUOS(x) (((x) & 0x1f) << 8)
+#define MIPI_CAL_TERMOS(x) (((x) & 0x1f) << 0)
+
+#define MIPI_CAL_BIAS_PAD_PDVCLAMP BIT(1)
+#define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF BIT(0)
+
+#define MIPI_CAL_BIAS_PAD_DRV_DN_REF(x) (((x) & 0x7) << 16)
+#define MIPI_CAL_BIAS_PAD_DRV_UP_REF(x) (((x) & 0x7) << 8)
+
+#define MIPI_CAL_BIAS_PAD_VCLAMP(x)(((x) & 0x7) << 16)
+#define MIPI_CAL_BIAS_PAD_VAUXP(x) (((x) & 0x7) << 4)
+#define MIPI_CAL_BIAS_PAD_PDVREG BIT(1)
+
+struct tegra_mipi_priv {
+ struct mipi_ctlr*mipi;
+ struct clk *mipi_cal;
+};
+
+static int tegra_mipi_calibrate(struct udevice *dev, int offset, const void
*buf,
+ int size)
+{
+ struct tegra_mipi_priv *priv = dev_get_priv(dev);
+ u32 value;
+
+ value = MIPI_CAL_BIAS_PAD_DRV_DN_REF(0x2) |
+ MIPI_CAL_BIAS_PAD_DRV_UP_REF(0x0);
+ writel(value, >mipi->mipi_cal_bias_pad_cfg1);
+
+ value = readl(>mipi->mipi_cal_bias_pad_cfg2);
+ value &= ~MIPI_CAL_BIAS_PAD_VCLAMP(0x7);
+ value &= ~MIPI_CAL_BIAS_PAD_VAUXP(0x7);
+ writel(value, >mipi->mipi_cal_bias_pad_cfg2);
+
+ value = MIPI_CAL_OVERIDE(0x0) | MIPI_CAL_SEL(0x1) |
+ MIPI_CAL_HSPDOS(0x0) | MIPI_CAL_HSPUOS(0x4) |
+ MIPI_CAL_TERMOS(0x5);
+ writel(value, >mipi->mipi_cal_config_dsia);
+ writel(value, >mipi->mipi_cal_config_dsib);
+
+ /* Deselect PAD C */
+ value = readl(>mipi->mipi_cal_config_dsic);
+ value &= ~(MIPI_CAL_SEL(0x1));
+ writel(value, >mipi->mipi_cal_config_dsic);
+
+ /* Deselect PAD D */
+ value = readl(>mipi->mipi_cal_config_dsid);
+ value &= ~(MIPI_CAL_SEL(0x1));
+ writel(value, >mipi->mipi_cal_config_dsid);
+
+ value = readl(>mipi->mipi_cal_ctrl);
+ value &= ~MIPI_CAL_CTRL_NOISE_FILTER(0xf);
+ value &= ~MIPI_CAL_CTRL_PRESCALE(0x3);
+ value |= MIPI_CAL_CTRL_NOISE_FILTER(0xa) |
+MIPI_CAL_CTRL_PRESCALE(0x2) |
+MIPI_CAL_CTRL_CLKEN_OVR;
+ writel(value, >mipi->mipi_cal_ctrl);
+
+ /* clear any pending status bits */
+ value = readl(>mipi->mipi_cal_status);
+ writel(value, >mipi->mipi_cal_status);
+
+ value = readl(>mipi->mipi_cal_ctrl);
+ value |= MIPI_CAL_CTRL_START;
+ writel(value, >mipi->mipi_cal_ctrl);
+
+ /*
+* Wait for min 72uS to let calibration logic finish
[PATCH v6 12/18] video: tegra20: dc: parameterize V- and H-sync polarities
Based on Thierry Reding's Linux commit:
'commit 1716b1891e1de05e2c20ccafa9f58550f3539717
("drm/tegra: rgb: Parameterize V- and H-sync polarities")'
Signed-off-by: Svyatoslav Ryhel
---
arch/arm/include/asm/arch-tegra/dc.h | 5 +
drivers/video/tegra20/tegra-dc.c | 22 --
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/dc.h
b/arch/arm/include/asm/arch-tegra/dc.h
index 6444af2993..ca3718411a 100644
--- a/arch/arm/include/asm/arch-tegra/dc.h
+++ b/arch/arm/include/asm/arch-tegra/dc.h
@@ -443,6 +443,11 @@ enum win_color_depth_id {
#defineWINDOW_D_SELECT BIT(7)
#defineWINDOW_H_SELECT BIT(8)
+/* DC_COM_PIN_OUTPUT_POLARITY1 0x307 */
+#define LHS_OUTPUT_POLARITY_LOWBIT(30)
+#define LVS_OUTPUT_POLARITY_LOWBIT(28)
+#define LSC0_OUTPUT_POLARITY_LOW BIT(24)
+
/* DC_DISP_DISP_WIN_OPTIONS 0x402 */
#defineCURSOR_ENABLE BIT(16)
#defineSOR_ENABLE BIT(25)
diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c
index caeec94468..ffa81eeac3 100644
--- a/drivers/video/tegra20/tegra-dc.c
+++ b/drivers/video/tegra20/tegra-dc.c
@@ -220,8 +220,11 @@ static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
0x0002,
};
-static void rgb_enable(struct dc_com_reg *com)
+static void rgb_enable(struct tegra_lcd_priv *priv)
{
+ struct dc_com_reg *com = >dc->com;
+ struct display_timing *dt = >timing;
+ u32 value;
int i;
for (i = 0; i < PIN_REG_COUNT; i++) {
@@ -230,6 +233,21 @@ static void rgb_enable(struct dc_com_reg *com)
writel(rgb_data_tab[i], >pin_output_data[i]);
}
+ /* configure H- and V-sync signal polarities */
+ value = readl(>pin_output_polarity[1]);
+
+ if (dt->flags & DISPLAY_FLAGS_HSYNC_LOW)
+ value |= LHS_OUTPUT_POLARITY_LOW;
+ else
+ value &= ~LHS_OUTPUT_POLARITY_LOW;
+
+ if (dt->flags & DISPLAY_FLAGS_VSYNC_LOW)
+ value |= LVS_OUTPUT_POLARITY_LOW;
+ else
+ value &= ~LVS_OUTPUT_POLARITY_LOW;
+
+ writel(value, >pin_output_polarity[1]);
+
for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
writel(rgb_sel_tab[i], >pin_output_sel[i]);
}
@@ -329,7 +347,7 @@ static int tegra_display_probe(struct tegra_lcd_priv *priv,
basic_init_timer(>dc->disp);
if (priv->soc->has_rgb)
- rgb_enable(>dc->com);
+ rgb_enable(priv);
if (priv->pixel_clock)
update_display_mode(priv);
--
2.40.1
[PATCH v6 11/18] video: tegra20: dc: clean framebuffer memory block
From: Jonas Schwöbel
Fill the framebuffer memory with zeros to avoid visual glitches.
Signed-off-by: Jonas Schwöbel
Signed-off-by: Svyatoslav Ryhel
---
drivers/video/tegra20/tegra-dc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c
index ac6833229a..caeec94468 100644
--- a/drivers/video/tegra20/tegra-dc.c
+++ b/drivers/video/tegra20/tegra-dc.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -398,6 +399,10 @@ static int tegra_lcd_probe(struct udevice *dev)
priv->scdiv = dc_plat->scdiv;
}
+ /* Clean the framebuffer area */
+ memset((u8 *)plat->base, 0, plat->size);
+ flush_dcache_all();
+
if (tegra_display_probe(priv, (void *)plat->base)) {
debug("%s: Failed to probe display driver\n", __func__);
return -1;
--
2.40.1
[PATCH v6 10/18] video: tegra20: dc: enable backlight after DC is configured
From: Jonas Schwöbel
The goal of panel_set_backlight() is to enable backlight. Hence,
it should be called at the probe end.
Signed-off-by: Jonas Schwöbel
Signed-off-by: Svyatoslav Ryhel
---
drivers/video/tegra20/tegra-dc.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c
index 000a0e02f8..ac6833229a 100644
--- a/drivers/video/tegra20/tegra-dc.c
+++ b/drivers/video/tegra20/tegra-dc.c
@@ -414,12 +414,6 @@ static int tegra_lcd_probe(struct udevice *dev)
return ret;
}
- ret = panel_set_backlight(priv->panel, BACKLIGHT_DEFAULT);
- if (ret) {
- debug("%s: Cannot set backlight to default, ret=%d\n",
__func__, ret);
- return ret;
- }
-
mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size,
DCACHE_WRITETHROUGH);
@@ -432,7 +426,7 @@ static int tegra_lcd_probe(struct udevice *dev)
debug("LCD frame buffer at %08x, size %x\n", priv->frame_buffer,
plat->size);
- return 0;
+ return panel_set_backlight(priv->panel, BACKLIGHT_DEFAULT);
}
static int tegra_lcd_of_to_plat(struct udevice *dev)
--
2.40.1
[PATCH v6 09/18] video: tegra20: dc: fix printing of framebuffer address
From: Jonas Schwöbel
Framebuffer address should not be a pointer.
Signed-off-by: Jonas Schwöbel
Signed-off-by: Svyatoslav Ryhel
---
drivers/video/tegra20/tegra-dc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c
index a8e32e6893..000a0e02f8 100644
--- a/drivers/video/tegra20/tegra-dc.c
+++ b/drivers/video/tegra20/tegra-dc.c
@@ -429,7 +429,7 @@ static int tegra_lcd_probe(struct udevice *dev)
uc_priv->xsize = priv->width;
uc_priv->ysize = priv->height;
uc_priv->bpix = priv->log2_bpp;
- debug("LCD frame buffer at %pa, size %x\n", >frame_buffer,
+ debug("LCD frame buffer at %08x, size %x\n", priv->frame_buffer,
plat->size);
return 0;
--
2.40.1
[PATCH v6 08/18] video: tegra20: dc: configure behavior if PLLD/D2 is used
If DISP1 is a PLLD/D2 child, it cannot go over 370MHz. The cause
of this is not quite clear. This can be overcomed by further
halving the PLLD/D2 if the target parent rate is over 800MHz.
This way DISP1 and DSI clocks will have the same frequency. The
shift divider in this case has to be calculated from the
original PLLD/D2 frequency and is passed from the DSI driver.
Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565
Tested-by: Ion Agorria # HTC One X
Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114
Tested-by: Jonas Schwöbel # Microsoft Surface 2
Signed-off-by: Jonas Schwöbel
Signed-off-by: Svyatoslav Ryhel
---
drivers/video/tegra20/tegra-dc.c | 34 +++
drivers/video/tegra20/tegra-dc.h | 1 +
drivers/video/tegra20/tegra-dsi.c | 14 +
3 files changed, 36 insertions(+), 13 deletions(-)
diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c
index 9a18e38cd8..a8e32e6893 100644
--- a/drivers/video/tegra20/tegra-dc.c
+++ b/drivers/video/tegra20/tegra-dc.c
@@ -48,6 +48,7 @@ struct tegra_lcd_priv {
fdt_addr_t frame_buffer;/* Address of frame buffer */
unsigned pixel_clock; /* Pixel clock in Hz */
int dc_clk[2]; /* Contains clk and its parent */
+ ulong scdiv;/* Clock divider used by disp_clk_ctrl
*/
bool rotation; /* 180 degree panel turn */
bool pipe; /* DC controller: 0 for A, 1 for B */
};
@@ -126,8 +127,6 @@ static int update_display_mode(struct tegra_lcd_priv *priv)
struct dc_disp_reg *disp = >dc->disp;
struct display_timing *dt = >timing;
unsigned long val;
- unsigned long rate;
- unsigned long div;
writel(0x0, >disp_timing_opt);
@@ -150,21 +149,11 @@ static int update_display_mode(struct tegra_lcd_priv
*priv)
writel(val, >disp_interface_ctrl);
}
- /*
-* The pixel clock divider is in 7.1 format (where the bottom bit
-* represents 0.5). Here we calculate the divider needed to get from
-* the display clock (typically 600MHz) to the pixel clock. We round
-* up or down as requried.
-*/
- rate = clock_get_periph_rate(priv->dc_clk[0], priv->dc_clk[1]);
- div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2;
- debug("Display clock %lu, divider %lu\n", rate, div);
-
if (priv->soc->has_rgb)
writel(0x00010001, >shift_clk_opt);
val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
- val |= div << SHIFT_CLK_DIVIDER_SHIFT;
+ val |= priv->scdiv << SHIFT_CLK_DIVIDER_SHIFT;
writel(val, >disp_clk_ctrl);
return 0;
@@ -314,6 +303,17 @@ static int tegra_display_probe(struct tegra_lcd_priv *priv,
rate /= 2;
#endif
+ /*
+* The pixel clock divider is in 7.1 format (where the bottom bit
+* represents 0.5). Here we calculate the divider needed to get from
+* the display clock (typically 600MHz) to the pixel clock. We round
+* up or down as required.
+*/
+ if (!priv->scdiv)
+ priv->scdiv = ((rate * 2 + priv->pixel_clock / 2)
+ / priv->pixel_clock) - 2;
+ debug("Display clock %lu, divider %lu\n", rate, priv->scdiv);
+
/*
* HOST1X is init by default at 150MHz with PLLC as parent
*/
@@ -390,6 +390,14 @@ static int tegra_lcd_probe(struct udevice *dev)
reset_deassert(_ctl);
mdelay(4);
+ /* Get shift clock divider from Tegra DSI if used */
+ if (!strcmp(priv->panel->name, TEGRA_DSI_A) ||
+ !strcmp(priv->panel->name, TEGRA_DSI_B)) {
+ struct tegra_dc_plat *dc_plat = dev_get_plat(priv->panel);
+
+ priv->scdiv = dc_plat->scdiv;
+ }
+
if (tegra_display_probe(priv, (void *)plat->base)) {
debug("%s: Failed to probe display driver\n", __func__);
return -1;
diff --git a/drivers/video/tegra20/tegra-dc.h b/drivers/video/tegra20/tegra-dc.h
index 75fc0fa4de..05042dab1c 100644
--- a/drivers/video/tegra20/tegra-dc.h
+++ b/drivers/video/tegra20/tegra-dc.h
@@ -23,6 +23,7 @@ struct tegra_dc_plat {
struct udevice *dev;/* Display controller device */
struct dc_ctlr *dc; /* Display controller regmap */
bool pipe; /* DC number: 0 for A, 1 for B */
+ ulong scdiv;/* Shift clock divider */
};
/* This holds information about a window which can be displayed */
diff --git a/drivers/video/tegra20/tegra-dsi.c
b/drivers/video/tegra20/tegra-dsi.c
index 72b91ed26b..de225ed376 100644
--- a/drivers/video/tegra20/tegra-dsi.c
+++ b/drivers/video/tegra20/tegra-dsi.c
@@ -743,6 +743,7 @@ static int tegra_dsi_panel_timings(struct udevice *dev,
static void
[PATCH v6 06/18] video: tegra20: dc: add reset support
Implement reset use to discard any changes which could have been
applied to DC before and can interfere with current configuration.
Tested-by: Agneli # Toshiba AC100 T20
Tested-by: Robert Eckelmann # ASUS TF101
Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565
Tested-by: Ion Agorria # HTC One X
Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel
---
drivers/video/tegra20/tegra-dc.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c
index 56a23b3c97..35abb6fe46 100644
--- a/drivers/video/tegra20/tegra-dc.c
+++ b/drivers/video/tegra20/tegra-dc.c
@@ -10,7 +10,9 @@
#include
#include
#include
+#include
#include
+#include
#include
#include
#include
@@ -342,6 +344,7 @@ static int tegra_lcd_probe(struct udevice *dev)
struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct tegra_lcd_priv *priv = dev_get_priv(dev);
+ struct reset_ctl reset_ctl;
int ret;
/* Initialize the Tegra display controller */
@@ -349,6 +352,20 @@ static int tegra_lcd_probe(struct udevice *dev)
funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
#endif
+ ret = reset_get_by_name(dev, "dc", _ctl);
+ if (ret) {
+ log_err("reset_get_by_name() failed: %d\n", ret);
+ return ret;
+ }
+
+ clock_disable(priv->dc_clk[0]);
+
+ /* Reset everything set before */
+ reset_assert(_ctl);
+ mdelay(4);
+ reset_deassert(_ctl);
+ mdelay(4);
+
if (tegra_display_probe(priv, (void *)plat->base)) {
debug("%s: Failed to probe display driver\n", __func__);
return -1;
--
2.40.1
[PATCH v6 07/18] video: tegra20: dc: add powergate
Add powergate use on T114 to complete resetting of DC.
Signed-off-by: Svyatoslav Ryhel
---
drivers/video/tegra20/tegra-dc.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c
index 35abb6fe46..9a18e38cd8 100644
--- a/drivers/video/tegra20/tegra-dc.c
+++ b/drivers/video/tegra20/tegra-dc.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
#include
#include "tegra-dc.h"
@@ -32,6 +33,7 @@ DECLARE_GLOBAL_DATA_PTR;
struct tegra_dc_soc_info {
bool has_timer;
bool has_rgb;
+ bool has_pgate;
};
/* Information about the display controller */
@@ -360,6 +362,28 @@ static int tegra_lcd_probe(struct udevice *dev)
clock_disable(priv->dc_clk[0]);
+ if (priv->soc->has_pgate) {
+ uint powergate;
+
+ if (priv->pipe)
+ powergate = TEGRA_POWERGATE_DISB;
+ else
+ powergate = TEGRA_POWERGATE_DIS;
+
+ ret = tegra_powergate_power_off(powergate);
+ if (ret < 0) {
+ log_err("failed to power off DISP gate: %d", ret);
+ return ret;
+ }
+
+ ret = tegra_powergate_sequence_power_up(powergate,
+ priv->dc_clk[0]);
+ if (ret < 0) {
+ log_err("failed to power up DISP gate: %d", ret);
+ return ret;
+ }
+ }
+
/* Reset everything set before */
reset_assert(_ctl);
mdelay(4);
@@ -510,16 +534,19 @@ static const struct video_ops tegra_lcd_ops = {
static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
.has_timer = true,
.has_rgb = true,
+ .has_pgate = false,
};
static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
.has_timer = false,
.has_rgb = true,
+ .has_pgate = false,
};
static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
.has_timer = false,
.has_rgb = false,
+ .has_pgate = true,
};
static const struct udevice_id tegra_lcd_ids[] = {
--
2.40.1
[PATCH v6 05/18] video: tegra20: dc: add PLLD2 parent support
T30+ SOC have second PLLD - PLLD2 which can be actively used by DC and act as main DISP1/2 clock parent. Tested-by: Agneli # Toshiba AC100 T20 Tested-by: Robert Eckelmann # ASUS TF101 Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565 Tested-by: Ion Agorria # HTC One X Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114 Signed-off-by: Svyatoslav Ryhel --- drivers/video/tegra20/tegra-dc.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c index 0e94e665ef..56a23b3c97 100644 --- a/drivers/video/tegra20/tegra-dc.c +++ b/drivers/video/tegra20/tegra-dc.c @@ -304,6 +304,12 @@ static int tegra_display_probe(struct tegra_lcd_priv *priv, if (priv->dc_clk[1] == CLOCK_ID_DISPLAY) rate /= 2; +#ifndef CONFIG_TEGRA20 + /* PLLD2 obeys same rules as PLLD but it is present only on T30+ */ + if (priv->dc_clk[1] == CLOCK_ID_DISPLAY2) + rate /= 2; +#endif + /* * HOST1X is init by default at 150MHz with PLLC as parent */ -- 2.40.1
[PATCH v6 04/18] video: tegra20: dc: pass DC id to internal devices
Tegra SoC has 2 independent display controllers called DC_A and
DC_B, they are handled differently by internal video devices like
DSI and HDMI controllers so it is important for last to know
which display controller is used to properly set up registers.
To achieve this, a pipe field was added to pdata to pass display
controller id to internal Tegra SoC devices.
Tested-by: Agneli # Toshiba AC100 T20
Tested-by: Robert Eckelmann # ASUS TF101
Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565
Tested-by: Ion Agorria # HTC One X
Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel
---
drivers/video/tegra20/tegra-dc.c | 6 ++
drivers/video/tegra20/tegra-dc.h | 3 +++
2 files changed, 9 insertions(+)
diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c
index 5d8874f323..0e94e665ef 100644
--- a/drivers/video/tegra20/tegra-dc.c
+++ b/drivers/video/tegra20/tegra-dc.c
@@ -45,6 +45,7 @@ struct tegra_lcd_priv {
unsigned pixel_clock; /* Pixel clock in Hz */
int dc_clk[2]; /* Contains clk and its parent */
bool rotation; /* 180 degree panel turn */
+ bool pipe; /* DC controller: 0 for A, 1 for B */
};
enum {
@@ -406,6 +407,9 @@ static int tegra_lcd_of_to_plat(struct udevice *dev)
priv->rotation = dev_read_bool(dev, "nvidia,180-rotation");
+ if (!strcmp(dev->name, TEGRA_DC_B))
+ priv->pipe = 1;
+
rgb = fdt_subnode_offset(blob, node, "rgb");
if (rgb < 0) {
debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n",
@@ -431,12 +435,14 @@ static int tegra_lcd_of_to_plat(struct udevice *dev)
return ret;
}
+ /* Fill the platform data for internal devices */
if (!strcmp(priv->panel->name, TEGRA_DSI_A) ||
!strcmp(priv->panel->name, TEGRA_DSI_B)) {
struct tegra_dc_plat *dc_plat = dev_get_plat(priv->panel);
dc_plat->dev = dev;
dc_plat->dc = priv->dc;
+ dc_plat->pipe = priv->pipe;
}
ret = panel_get_display_timing(priv->panel, >timing);
diff --git a/drivers/video/tegra20/tegra-dc.h b/drivers/video/tegra20/tegra-dc.h
index 5c05221038..75fc0fa4de 100644
--- a/drivers/video/tegra20/tegra-dc.h
+++ b/drivers/video/tegra20/tegra-dc.h
@@ -14,12 +14,15 @@
/* arch-tegra/dc exists only because T124 uses it */
#include
+#define TEGRA_DC_A "dc@5420"
+#define TEGRA_DC_B "dc@5424"
#define TEGRA_DSI_A"dsi@5430"
#define TEGRA_DSI_B"dsi@5440"
struct tegra_dc_plat {
struct udevice *dev;/* Display controller device */
struct dc_ctlr *dc; /* Display controller regmap */
+ bool pipe; /* DC number: 0 for A, 1 for B */
};
/* This holds information about a window which can be displayed */
--
2.40.1
[PATCH v6 03/18] video: tegra20: consolidate DC header
Consolidate HD headers and place the result into video/tegra20
since it is used only by devices from this directory.
Tested-by: Agneli # Toshiba AC100 T20
Tested-by: Robert Eckelmann # ASUS TF101
Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565
Tested-by: Ion Agorria # HTC One X
Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel
---
arch/arm/include/asm/arch-tegra/dc.h | 8
arch/arm/include/asm/arch-tegra114/display.h | 28 -
arch/arm/include/asm/arch-tegra20/display.h | 28 -
arch/arm/include/asm/arch-tegra30/display.h | 28 -
drivers/video/tegra20/tegra-dc.c | 3 +-
drivers/video/tegra20/tegra-dc.h | 41
drivers/video/tegra20/tegra-dsi.c| 2 +-
drivers/video/tegra20/tegra-pwm-backlight.c | 3 +-
8 files changed, 46 insertions(+), 95 deletions(-)
delete mode 100644 arch/arm/include/asm/arch-tegra114/display.h
delete mode 100644 arch/arm/include/asm/arch-tegra20/display.h
delete mode 100644 arch/arm/include/asm/arch-tegra30/display.h
create mode 100644 drivers/video/tegra20/tegra-dc.h
diff --git a/arch/arm/include/asm/arch-tegra/dc.h
b/arch/arm/include/asm/arch-tegra/dc.h
index 7613d84f22..6444af2993 100644
--- a/arch/arm/include/asm/arch-tegra/dc.h
+++ b/arch/arm/include/asm/arch-tegra/dc.h
@@ -569,12 +569,4 @@ enum {
#define DC_N_WINDOWS 5
#define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5)
-#define TEGRA_DSI_A"dsi@5430"
-#define TEGRA_DSI_B"dsi@5440"
-
-struct tegra_dc_plat {
- struct udevice *dev;/* Display controller device */
- struct dc_ctlr *dc; /* Display controller regmap */
-};
-
#endif /* __ASM_ARCH_TEGRA_DC_H */
diff --git a/arch/arm/include/asm/arch-tegra114/display.h
b/arch/arm/include/asm/arch-tegra114/display.h
deleted file mode 100644
index 9411525799..00
--- a/arch/arm/include/asm/arch-tegra114/display.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010
- * NVIDIA Corporation
- */
-
-#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
-#define __ASM_ARCH_TEGRA_DISPLAY_H
-
-#include
-
-/* This holds information about a window which can be displayed */
-struct disp_ctl_win {
- enum win_color_depth_id fmt;/* Color depth/format */
- unsigned intbpp;/* Bits per pixel */
- phys_addr_t phys_addr; /* Physical address in memory */
- unsigned intx; /* Horizontal address offset (bytes) */
- unsigned inty; /* Veritical address offset (bytes) */
- unsigned intw; /* Width of source window */
- unsigned inth; /* Height of source window */
- unsigned intstride; /* Number of bytes per line */
- unsigned intout_x; /* Left edge of output window (col) */
- unsigned intout_y; /* Top edge of output window (row) */
- unsigned intout_w; /* Width of output window in pixels */
- unsigned intout_h; /* Height of output window in pixels */
-};
-
-#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
diff --git a/arch/arm/include/asm/arch-tegra20/display.h
b/arch/arm/include/asm/arch-tegra20/display.h
deleted file mode 100644
index e7b3cffd46..00
--- a/arch/arm/include/asm/arch-tegra20/display.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010
- * NVIDIA Corporation
- */
-
-#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
-#define __ASM_ARCH_TEGRA_DISPLAY_H
-
-#include
-
-/* This holds information about a window which can be displayed */
-struct disp_ctl_win {
- enum win_color_depth_id fmt;/* Color depth/format */
- unsignedbpp;/* Bits per pixel */
- phys_addr_t phys_addr; /* Physical address in memory */
- unsignedx; /* Horizontal address offset (bytes) */
- unsignedy; /* Veritical address offset (bytes) */
- unsignedw; /* Width of source window */
- unsignedh; /* Height of source window */
- unsignedstride; /* Number of bytes per line */
- unsignedout_x; /* Left edge of output window (col) */
- unsignedout_y; /* Top edge of output window (row) */
- unsignedout_w; /* Width of output window in pixels */
- unsignedout_h; /* Height of output window in pixels */
-};
-
-#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
diff --git a/arch/arm/include/asm/arch-tegra30/display.h
b/arch/arm/include/asm/arch-tegra30/display.h
deleted file mode 100644
index 9411525799..00
--- a/arch/arm/include/asm/arch-tegra30/display.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *
[PATCH v6 01/18] video: tegra20: dc: diverge DC per-SOC
Diverge DC driver setup to better fit each of supported generations
of Tegra SOC.
Tested-by: Agneli # Toshiba AC100 T20
Tested-by: Robert Eckelmann # ASUS TF101
Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565
Tested-by: Ion Agorria # HTC One X
Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel
---
arch/arm/dts/tegra114-u-boot.dtsi| 13 +++
arch/arm/dts/tegra114.dtsi | 4 +-
arch/arm/dts/tegra30-u-boot.dtsi | 4 +
arch/arm/dts/tegra30.dtsi| 2 +-
arch/arm/include/asm/arch-tegra114/display.h | 28 +
arch/arm/include/asm/arch-tegra114/pwm.h | 13 +++
drivers/video/tegra20/tegra-dc.c | 107 +--
7 files changed, 133 insertions(+), 38 deletions(-)
create mode 100644 arch/arm/include/asm/arch-tegra114/display.h
create mode 100644 arch/arm/include/asm/arch-tegra114/pwm.h
diff --git a/arch/arm/dts/tegra114-u-boot.dtsi
b/arch/arm/dts/tegra114-u-boot.dtsi
index 7c11972552..6a02714a25 100644
--- a/arch/arm/dts/tegra114-u-boot.dtsi
+++ b/arch/arm/dts/tegra114-u-boot.dtsi
@@ -1,3 +1,16 @@
#include
#include "tegra-u-boot.dtsi"
+
+/ {
+ host1x@5000 {
+ bootph-all;
+ dc@5420 {
+ bootph-all;
+ };
+
+ dc@5424 {
+ bootph-all;
+ };
+ };
+};
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index 68ee7f3165..250d692f6b 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -42,7 +42,7 @@
};
dc@5420 {
- compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
+ compatible = "nvidia,tegra114-dc";
reg = <0x5420 0x0004>;
interrupts = ;
clocks = <_car TEGRA114_CLK_DISP1>,
@@ -61,7 +61,7 @@
};
dc@5424 {
- compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
+ compatible = "nvidia,tegra114-dc";
reg = <0x5424 0x0004>;
interrupts = ;
clocks = <_car TEGRA114_CLK_DISP2>,
diff --git a/arch/arm/dts/tegra30-u-boot.dtsi b/arch/arm/dts/tegra30-u-boot.dtsi
index 3038227dbe..6a02714a25 100644
--- a/arch/arm/dts/tegra30-u-boot.dtsi
+++ b/arch/arm/dts/tegra30-u-boot.dtsi
@@ -8,5 +8,9 @@
dc@5420 {
bootph-all;
};
+
+ dc@5424 {
+ bootph-all;
+ };
};
};
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
index f198bc0edb..1177e2ab1f 100644
--- a/arch/arm/dts/tegra30.dtsi
+++ b/arch/arm/dts/tegra30.dtsi
@@ -158,7 +158,7 @@
};
dc@5420 {
- compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
+ compatible = "nvidia,tegra30-dc";
reg = <0x5420 0x0004>;
interrupts = ;
clocks = <_car TEGRA30_CLK_DISP1>,
diff --git a/arch/arm/include/asm/arch-tegra114/display.h
b/arch/arm/include/asm/arch-tegra114/display.h
new file mode 100644
index 00..9411525799
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/display.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * NVIDIA Corporation
+ */
+
+#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
+#define __ASM_ARCH_TEGRA_DISPLAY_H
+
+#include
+
+/* This holds information about a window which can be displayed */
+struct disp_ctl_win {
+ enum win_color_depth_id fmt;/* Color depth/format */
+ unsigned intbpp;/* Bits per pixel */
+ phys_addr_t phys_addr; /* Physical address in memory */
+ unsigned intx; /* Horizontal address offset (bytes) */
+ unsigned inty; /* Veritical address offset (bytes) */
+ unsigned intw; /* Width of source window */
+ unsigned inth; /* Height of source window */
+ unsigned intstride; /* Number of bytes per line */
+ unsigned intout_x; /* Left edge of output window (col) */
+ unsigned intout_y; /* Top edge of output window (row) */
+ unsigned intout_w; /* Width of output window in pixels */
+ unsigned intout_h; /* Height of output window in pixels */
+};
+
+#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
diff --git a/arch/arm/include/asm/arch-tegra114/pwm.h
b/arch/arm/include/asm/arch-tegra114/pwm.h
new file mode 100644
index 00..af39151803
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/pwm.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Tegra pulse
[PATCH v6 02/18] video: tegra20: dc: fix image shift on rotated panels
Subtracting 1 from x and y fixes image shifting on rotated
panels.
Tested-by: Robert Eckelmann # ASUS Grouper E1565
Signed-off-by: Svyatoslav Ryhel
---
drivers/video/tegra20/tegra-dc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c
index 7605e77bc1..bcc2748623 100644
--- a/drivers/video/tegra20/tegra-dc.c
+++ b/drivers/video/tegra20/tegra-dc.c
@@ -242,8 +242,8 @@ static int setup_window(struct tegra_lcd_priv *priv,
struct disp_ctl_win *win)
{
if (priv->rotation) {
- win->x = priv->width * 2;
- win->y = priv->height;
+ win->x = priv->width * 2 - 1;
+ win->y = priv->height - 1;
} else {
win->x = 0;
win->y = 0;
--
2.40.1
[PATCH v6 00/18] Add T114 video support
T114 is not that different from T30 and all T30 drivers will work on T114 as well with some adjustments. Patches propose general improvements for existing Tegra DC and DSI drivers as well Tegra 114 video support (experimentl). Commits pass buildman for tegra. --- Changes from v5: - backlight enable moved to the last step of setup for DSI - parameterized V- and H-sync polarities - added framebuffer clearing on probe to avoid glitches - backlight enable moved after DC is fully configured - fixed printing framebuffer pointer instead of address - moved scdiv calculation to tegra DSI if it is used Changes from v4: - fixed typo in max rate to be divided (400KHz > 400MHz) Changes from v3: - fixed the clock divider calculation if PLLD/D2 is used - removed unnecessary pre-configuration - set correct video FIFO depth for DSI Changes from v2: - fixed image distortion on devices with 180deg rotation Changes from v1: - reworked patchset entirely - diverged DC configuration per-SOC - consolidated dc headers from different SOC gen - initial support of DC detection (tegra has 2 DC) - added PLLD2 support, resets and powergating - added T114+ MIPI calibration - added DSI detection (tegra has 2 DSI) and resets --- Jonas Schwöbel (6): video: tegra20: dc: fix printing of framebuffer address video: tegra20: dc: enable backlight after DC is configured video: tegra20: dc: clean framebuffer memory block video: tegra20: dsi: remove pre-configuration video: tegra20: dsi: set correct fifo depth video: tegra20: dsi: use set_backlight for backlight only Svyatoslav Ryhel (12): video: tegra20: dc: diverge DC per-SOC video: tegra20: dc: fix image shift on rotated panels video: tegra20: consolidate DC header video: tegra20: dc: pass DC id to internal devices video: tegra20: dc: add PLLD2 parent support video: tegra20: dc: add reset support video: tegra20: dc: add powergate video: tegra20: dc: configure behavior if PLLD/D2 is used video: tegra20: dc: parameterize V- and H-sync polarities video: tegra20: add MIPI calibration driver video: tegra20: dsi: add T114 support video: tegra20: dsi: add reset support arch/arm/dts/tegra114-u-boot.dtsi | 13 + arch/arm/dts/tegra114.dtsi| 4 +- arch/arm/dts/tegra30-u-boot.dtsi | 4 + arch/arm/dts/tegra30.dtsi | 2 +- arch/arm/include/asm/arch-tegra/dc.h | 13 +- arch/arm/include/asm/arch-tegra114/pwm.h | 13 + arch/arm/include/asm/arch-tegra20/display.h | 28 -- arch/arm/include/asm/arch-tegra30/display.h | 28 -- drivers/video/tegra20/Makefile| 2 +- drivers/video/tegra20/tegra-dc.c | 239 +- drivers/video/tegra20/tegra-dc.h | 45 drivers/video/tegra20/tegra-dsi.c | 122 - .../video/tegra20/tegra-dsi.h | 24 +- drivers/video/tegra20/tegra-mipi.c| 188 ++ drivers/video/tegra20/tegra-pwm-backlight.c | 3 +- 15 files changed, 583 insertions(+), 145 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra114/pwm.h delete mode 100644 arch/arm/include/asm/arch-tegra20/display.h delete mode 100644 arch/arm/include/asm/arch-tegra30/display.h create mode 100644 drivers/video/tegra20/tegra-dc.h rename arch/arm/include/asm/arch-tegra30/dsi.h => drivers/video/tegra20/tegra-dsi.h (90%) create mode 100644 drivers/video/tegra20/tegra-mipi.c -- 2.40.1
Re: [PATCH v4 00/11] An effort to bring DT bindings compliance within U-Boot
On Mon, Jan 22, 2024 at 6:59 PM Andre Przywara wrote: > > On Mon, 22 Jan 2024 11:49:59 -0500 > Tom Rini wrote: > > Hi Tom, > > > On Mon, Jan 22, 2024 at 11:45:15AM +, Andre Przywara wrote: > > > On Wed, 10 Jan 2024 16:05:36 +0530 > > > Sumit Garg wrote: > > > > > > Hi, > > > > > > I certainly welcome this more automatic synchronisation of the DTs, > > > however have one comment about the upcoming sync process: > > > > > > > ... > > > > However, Linux kernel DT maintainers proposed [2] for U-Boot to rather > > > > use devicetree-rebasing repo [3] which is a forked copy from Linux > > > > kernel for DT source files as well as bindings. It is tagged at every > > > > Linux kernel major release or intermideate release candidates. So here I > > > > have tried to reuse that to bring DT bingings compliance as well as a > > > > standard way to maintain a regular sync of DT source files with Linux > > > > kernel. > > > > > > > > In order to maintain devicetree files sync, U-Boot will maintains a Git > > > > subtree for devicetee-rebasing repo as `dts/upstream` sub-directory. > > > > U-Boot will regularly sync `dts/upstream/` subtree whenever the next > > > > window > > > > opens with the next available kernel major release. > > > > > > I hope this doesn't need to stay that restricted? Can we either sync more > > > often, or at least on the kernel's -rc1, and not only on a "full" release? > > > > > > The reason I ask is that we have a chicken-egg problem here: without a DT > > > merged into the kernel tree, no U-Boot board support can be merged. And > > > without U-Boot support, we cannot boot a kernel, at least not in the > > > canonical way. > > > > > > Since the U-Boot and kernel merge windows are not in phase, for sunxi I > > > try > > > to sync the kernel DTs either as early as possible (-rc1, sometimes even > > > before, when the maintainers have merged them into their tree), or > > > sometimes "out of season", if a board defconfig patch is coming up. > > > > > > Otherwise new board support, which typically has a very low regression > > > risk > > > for the rest of the code base, would need to be delayed until the next > > > release. In the worst case the U-Boot merge windows opens one week before > > > a kernel release, then new boards need to wait three months? > > > > Would it be to bad to bring in board X with OF_UPSTREAM=n for one U-Boot > > release, and then with the next one switch to OF_UPSTREAM=y (and delete > > the dts from arch/) for the next release, when we would have gotten back > > in sync? > > Ah, I didn't look into the actual patches, but if this provision is > there, that sounds surely acceptable. It might still be good to sync > earlier than the .0 kernel release: if it appears in Linus' tree, it > had already seen a good share of review and testing. And with the > U-Boot releases being always further away than the next kernel release, > we could pull fixes still in time. So we could pick the latest -rc (or > .0 release, whichever is more recent) when the U-Boot merge window > opens? That should be mostly fine IMO, but there are the occasional "oops, let's change/fix the binding before it's released". Couldn't you pull in the latest rc in the merge window, but only if the .0 release will happen before the next u-boot release. And then update from rc to .0 before the u-boot release. Also, from a quick look at the dts changes during rc releases, they tend to come in the later rc releases. Probably that's just the latency of going to sub-arch maintainer->SoC->Linus. Rob
Re: [PATCH 1/1] mmc: Don't suggest to build modules in Kconfig.
On 1/23/24 17:18, Heinrich Schuchardt wrote:
> U-Boot does not support building kernel modules.
>
> Fixes: 3c0dbed232bd ("mmc: arm_pl180_mmci: adapt driver to DM usage")
> Fixes: 36645f45a048 ("drivers: mmc: Add sdhci driver for Broadcom iProc
> platform")
> Fixes: dadd43c14368 ("mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver")
> Fixes: b312c590bcd8 ("mmc: Add MMC support for stm32h7 Socs")
> Fixes: d24b69395949 ("mmc: mtk-sd: add SD/MMC host controller driver for
> MT7623 SoC")
> Signed-off-by: Heinrich Schuchardt
> ---
> drivers/mmc/Kconfig | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index ffde442cb29..9ce331677b8 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -83,7 +83,7 @@ config ARM_PL180_MMCI
> This selects the ARM(R) AMBA(R) PrimeCell Multimedia Card
> Interface (PL180, PL181 and compatible) support.
> If you have an ARM(R) platform with a Multimedia Card slot,
> - say Y or M here.
> + say Y here.
>
> config MMC_QUIRKS
> bool "Enable quirks"
> @@ -592,7 +592,7 @@ config MMC_SDHCI_IPROC
> This selects the iProc SD/MMC controller.
>
> If you have a Broadcom IPROC platform with SD or MMC devices,
> - say Y or M here.
> + say Y here.
>
> If unsure, say N.
>
> @@ -603,7 +603,7 @@ config MMC_SDHCI_F_SDH30
> help
> This selects the Secure Digital Host Controller Interface (SDHCI)
> Needed by some Fujitsu/Socionext SoC for MMC / SD / SDIO support.
> - If you have a controller with this interface, say Y or M here.
> + If you have a controller with this interface, say Y here.
> If unsure, say N.
>
> config MMC_SDHCI_KONA
> @@ -797,7 +797,7 @@ config STM32_SDMMC2
> help
> This selects support for the SD/MMC controller on STM32H7 SoCs.
> If you have a board based on such a SoC and with a SD/MMC slot,
> - say Y or M here.
> + say Y here.
>
> config FTSDC010
> bool "Ftsdc010 SD/MMC controller Support"
> @@ -817,7 +817,7 @@ config MMC_MTK
> depends on OF_CONTROL
> help
> This selects the MediaTek(R) Secure digital and Multimedia card
> Interface.
> - If you have a machine with a integrated SD/MMC card reader, say Y or
> M here.
> + If you have a machine with a integrated SD/MMC card reader, say Y
> here.
> This is needed if support for any SD/SDIO/MMC devices is required.
> If unsure, say N.
>
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 2/4] doc: Document capsule generation through a config file
Hi Sughosh,
On Tue, Nov 21, 2023 at 12:30:26PM +0530, Sughosh Ganu wrote:
> The UEFI capsule can now be generate by specifying the capsule
> parameters through a config file. Additionally, the capsules can be
> generated as part of u-boot build, through binman. Highlight these
> changes in the documentation.
>
> Signed-off-by: Sughosh Ganu
> ---
> doc/develop/uefi/uefi.rst | 70 +++
> 1 file changed, 70 insertions(+)
>
> diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst
> index fb16ac743a..b9a9ed5491 100644
> --- a/doc/develop/uefi/uefi.rst
> +++ b/doc/develop/uefi/uefi.rst
> @@ -318,6 +318,76 @@ Run the following command
>--guid \
>
>
> +Alternatively, the capsules can be generated through a config
> +file. When generating the capsules through a config file, the Kconfig
> +symbol CONFIG_EFI_CAPSULE_CFG_FILE is to be used for specifying the
> +path to the config file.
This sounds a bit weird. The tool is compiled and used by distros. How are
they supposed to use the config file?
Briefly looking at the patches, we use those config options on testing.
Can't we add a flag in the tool itself that can be used for normal use
cases and limit those Kconfig flags in our testing only? Or alternatively
the paths for the config files can be hardcoded for sandbox and we get rid
of the config options entirely?
Thanks
/Ilias
> +
> +The config file describes the parameters that are used for generating
> +one or more capsules. The parameters for a given capsule file are
> +specified within curly braces, in the form of "key:value" pairs. All
> +the parameters that are currently supported by the mkeficapsule tool
> +can be specified through the config file.
> +
> +The following are some example payload parameters specified through
> +the config file.
> +
> +.. code-block:: none
> +
> + {
> + image-guid: 02f4d760-cfd5-43bd-8e2d-a42acb33c660
> + hardware-instance: 0
> + monotonic-count: 1
> + payload: u-boot.bin
> + image-index: 1
> + fw-version: 2
> + private-key: /path/to/priv/key
> + pub-key-cert: /path/to/pub/key
> + capsule: u-boot.capsule
> + }
> + {
> + image-guid: 4ce292da-1dd8-428d-a1c2-77743ef8b96e
> + hardware-instance: 0
> + payload: u-boot.itb
> + image-index: 2
> + fw-version: 7
> + oemflags: 0x8000
> + capsule: fit.capsule
> + }
> + {
> + capsule-type: accept
> + image-guid: 4ce292da-1dd8-428d-a1c2-77743ef8b96e
> + capsule: accept.capsule
> + }
> + {
> + capsule-type: revert
> + capsule: revert.capsule
> + }
> +
> +The following are the keys that specify the capsule parameters
> +
> +..code-block:: none
> +
> +image-guid: Image GUID
> +image-index: Image index value
> +fw-version: Image version
> +private-key: Path to the private key file used for capsule signing
> +pub-key-cert: Path to the public key crt file used for capsule signing
> +payload: Path to the capsule payload file
> +capsule: Path to the output capsule file that is generated
> +hardware-instance: Hardware Instance value
> +monotonic-count: Monotonic count value
> +capsule-type: Specifies capsule type. normal(default), accept or revert
> +oemflags: 16bit Oemflags value to be used(populated in capsule header)
> +
> +When generating capsules through a config file, the command would look
> +like
> +
> +.. code-block:: console
> +
> +$ mkeficapsule --cfg-file
> +
> +
> Capsule with firmware version
> *
>
> --
> 2.34.1
>
[PATCH 1/1] mmc: Don't suggest to build modules in Kconfig.
U-Boot does not support building kernel modules.
Fixes: 3c0dbed232bd ("mmc: arm_pl180_mmci: adapt driver to DM usage")
Fixes: 36645f45a048 ("drivers: mmc: Add sdhci driver for Broadcom iProc
platform")
Fixes: dadd43c14368 ("mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver")
Fixes: b312c590bcd8 ("mmc: Add MMC support for stm32h7 Socs")
Fixes: d24b69395949 ("mmc: mtk-sd: add SD/MMC host controller driver for MT7623
SoC")
Signed-off-by: Heinrich Schuchardt
---
drivers/mmc/Kconfig | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index ffde442cb29..9ce331677b8 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -83,7 +83,7 @@ config ARM_PL180_MMCI
This selects the ARM(R) AMBA(R) PrimeCell Multimedia Card
Interface (PL180, PL181 and compatible) support.
If you have an ARM(R) platform with a Multimedia Card slot,
- say Y or M here.
+ say Y here.
config MMC_QUIRKS
bool "Enable quirks"
@@ -592,7 +592,7 @@ config MMC_SDHCI_IPROC
This selects the iProc SD/MMC controller.
If you have a Broadcom IPROC platform with SD or MMC devices,
- say Y or M here.
+ say Y here.
If unsure, say N.
@@ -603,7 +603,7 @@ config MMC_SDHCI_F_SDH30
help
This selects the Secure Digital Host Controller Interface (SDHCI)
Needed by some Fujitsu/Socionext SoC for MMC / SD / SDIO support.
- If you have a controller with this interface, say Y or M here.
+ If you have a controller with this interface, say Y here.
If unsure, say N.
config MMC_SDHCI_KONA
@@ -797,7 +797,7 @@ config STM32_SDMMC2
help
This selects support for the SD/MMC controller on STM32H7 SoCs.
If you have a board based on such a SoC and with a SD/MMC slot,
- say Y or M here.
+ say Y here.
config FTSDC010
bool "Ftsdc010 SD/MMC controller Support"
@@ -817,7 +817,7 @@ config MMC_MTK
depends on OF_CONTROL
help
This selects the MediaTek(R) Secure digital and Multimedia card
Interface.
- If you have a machine with a integrated SD/MMC card reader, say Y or
M here.
+ If you have a machine with a integrated SD/MMC card reader, say Y
here.
This is needed if support for any SD/SDIO/MMC devices is required.
If unsure, say N.
--
2.43.0
Re: [PATCH v8 15/16] configs: Add am69_sk_* defconfig fragments
On 1/23/24 8:39 AM, Apurva Nandan wrote: Hi Andrew, On 20/01/24 00:43, Andrew Davis wrote: On 1/19/24 11:50 AM, Apurva Nandan wrote: From: Dasnavis Sabiya Add config fragments for am69_sk A72 and R5 configuration. This applies on to: j784s4_evm_a72_defconfig -> am69_sk_a72.config j784s4_evm_r5_defconfig -> am69_sk_r5.config The usage model (with the fragment) would be: make j784s4_evm_a72_defconfig am69_sk_a72.config make OR make j784s4_evm_r5_defconfig am69_sk_r5.config make Signed-off-by: Dasnavis Sabiya Signed-off-by: Apurva Nandan --- board/ti/j784s4/MAINTAINERS | 2 ++ configs/am69_sk_a72.config | 5 + configs/am69_sk_r5.config | 5 + 3 files changed, 12 insertions(+) create mode 100644 configs/am69_sk_a72.config create mode 100644 configs/am69_sk_r5.config diff --git a/board/ti/j784s4/MAINTAINERS b/board/ti/j784s4/MAINTAINERS index 4433ead66b..69be13f533 100644 --- a/board/ti/j784s4/MAINTAINERS +++ b/board/ti/j784s4/MAINTAINERS @@ -20,3 +20,5 @@ AM69 SK BOARD F: arch/arm/dts/k3-am69-sk.dts F: arch/arm/dts/k3-am69-sk-u-boot.dtsi F: arch/arm/dts/k3-am69-r5-sk.dts +F: configs/am69_sk_r5.config +F: configs/am69_sk_a72.config diff --git a/configs/am69_sk_a72.config b/configs/am69_sk_a72.config new file mode 100644 index 00..03e74a8a56 --- /dev/null +++ b/configs/am69_sk_a72.config Just going to ignore the comments on v7 about putting this in board/ti/..? Sorry, somehow this got missed. Thanks for bringing up. Anyway, we can now do includes in defconfigs, so no config fragments needed, you can just add `configs/am69_evm_a72_defconfig` with the content: ``` #include CONFIG_ARM=y CONFIG_ARCH_K3=y CONFIG_SOC_K3_J784S4=y CONFIG_TARGET_J784S4_A72_EVM=y CONFIG_DEFAULT_DEVICE_TREE="k3-am69-sk" CONFIG_SPL_OF_LIST="k3-am69-sk" CONFIG_OF_LIST="k3-am69-sk" ``` (note we need to duplicate the _ARM/_TARGET currently to not confuse buildman which seems to directly parse the configs for arch detection). I tried it, but I don't think this works as '#' signifies a comment in defconfig, isn't that true? The ability to do this was just added recently, try it again :) Andrew Andrew @@ -0,0 +1,5 @@ +# Defconfig fragment to apply on top of j784s4_evm_a72_defconfig + +CONFIG_DEFAULT_DEVICE_TREE="k3-am69-sk" +CONFIG_SPL_OF_LIST="k3-am69-sk" +CONFIG_OF_LIST="k3-am69-sk" diff --git a/configs/am69_sk_r5.config b/configs/am69_sk_r5.config new file mode 100644 index 00..c42b6f3380 --- /dev/null +++ b/configs/am69_sk_r5.config @@ -0,0 +1,5 @@ +# Defconfig fragment to apply on top of j784s4_evm_r5_defconfig + +CONFIG_DEFAULT_DEVICE_TREE="k3-am69-sk" +CONFIG_SPL_OF_LIST="k3-am69-r5-sk" +CONFIG_OF_LIST="k3-am69-r5-sk"
Re: [PATCH v8 12/16] arm: dts: Introduce j784s4 u-boot dts files
On 20/01/24 00:47, Nishanth Menon wrote:
On 23:20-20240119, Apurva Nandan wrote:
[...]
diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi
b/arch/arm/dts/k3-j784s4-binman.dtsi
new file mode 100644
index 00..d0d49b5bbe
--- /dev/null
+++ b/arch/arm/dts/k3-j784s4-binman.dtsi
@@ -0,0 +1,345 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023 Texas Instruments Incorporated -https://www.ti.com/
+ */
+
+#include "k3-binman.dtsi"
+
+#ifdef CONFIG_TARGET_J784S4_R5_EVM
+
+_yaml_tifs {
+ config = "tifs-rm-cfg.yaml";
+};
+
+ {
+ tiboot3-j784s4-hs-evm.bin {
+ filename = "tiboot3-j784s4-hs-evm.bin";
+
https://lore.kernel.org/u-boot/20240103174756.xa4rzbn4klk5gv2x@aware/
You haven't responded on thread why
"Prefer #1 - j784s4 binman template" is not feasible or not desirable.
Something like:
in j784s4-binman.dtsi:
{
j784s4_tiboot3_hs_fs_template: template-9 {
and then in sk.dtsi:
sk.dtsi means sk-uboot.dtsi or sk-binman.dtsi?
{
ti-j784s4-hs-evm.bin {
insert-template =<_tiboot3_hs_fs_template>;
};
};
This allows boards to readily include the template for the binaries of
choice and generate just relevant output. Wont it save much confusion?
[...]
It is still little unclear what is the full thing that you are
recommending to implement here.
From what I understood, is it as follows?
- Three binman files will be there: j784s4-binman.dtsi (soc binman),
j784s4-evm-binman.dtsi and am69-sk-binman.dtsi (board binman)
- j784s4-binman.dtsi will be a SoC binman, and will have only templates
for all tiboot3 gp, hs, hsfs, and tispl/uboot
- The board binman files will include these templates and update the dtb
files in them.
- Final board.dts will use the correct board-binman.dtsi files
Please correct wherever wrong.
--
Regards,
Apurva Nandan,
Texas Instruments.
Re: [PATCH v8 08/16] drivers: dma: Add support for J784S4 SoC
On 22/01/24 18:17, Roger Quadros wrote:
On 19/01/2024 19:50, Apurva Nandan wrote:
Add support for DMA in J784S4 SoC.
Signed-off-by: Jayesh Choudhary
Signed-off-by: Hari Nagalla
Signed-off-by: Apurva Nandan
Reviewed-by: Nishanth Menon
---
drivers/dma/ti/Makefile | 1 +
drivers/dma/ti/k3-psil-j784s4.c | 166 ++
drivers/dma/ti/k3-psil-priv.h | 1 +
drivers/dma/ti/k3-psil.c | 2 +
drivers/firmware/ti_sci_static_data.h | 34 ++
drivers/ram/Kconfig | 2 +-
6 files changed, 205 insertions(+), 1 deletion(-)
create mode 100644 drivers/dma/ti/k3-psil-j784s4.c
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index f4e0271efb..9e0b13e8c0 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -9,3 +9,4 @@ k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o
k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o
k3-psil-data-$(CONFIG_SOC_K3_AM625) += k3-psil-am62.o
k3-psil-data-$(CONFIG_SOC_K3_AM62A7) += k3-psil-am62a.o
+k3-psil-data-$(CONFIG_SOC_K3_J784S4) += k3-psil-j784s4.o
diff --git a/drivers/dma/ti/k3-psil-j784s4.c b/drivers/dma/ti/k3-psil-j784s4.c
new file mode 100644
index 00..7f06a1f307
--- /dev/null
+++ b/drivers/dma/ti/k3-psil-j784s4.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com
+ */
+#include
+
+#include "k3-psil-priv.h"
+
+#define PSIL_PDMA_XY_TR(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ }, \
+ }
+
+#define PSIL_PDMA_XY_PKT(x)\
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .pkt_mode = 1, \
+ }, \
+ }
+
+#define PSIL_PDMA_MCASP(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .pdma_acc32 = 1,\
+ .pdma_burst = 1,\
+ }, \
+ }
+
+#define PSIL_ETHERNET(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1,\
+ .psd_size = 16, \
+ }, \
+ }
+
+#define PSIL_SA2UL(x, tx) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1,\
+ .psd_size = 64, \
+ .notdpkt = tx, \
+ }, \
+ }
+
+/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
+static struct psil_ep j784s4_src_ep_map[] = {
+ /* PDMA_MCASP - McASP0-4 */
+ PSIL_PDMA_MCASP(0x4400),
+ PSIL_PDMA_MCASP(0x4401),
+ PSIL_PDMA_MCASP(0x4402),
+ PSIL_PDMA_MCASP(0x4403),
+ PSIL_PDMA_MCASP(0x4404),
+ /* PDMA_SPI_G0 - SPI0-3 */
+ PSIL_PDMA_XY_PKT(0x4600),
+ PSIL_PDMA_XY_PKT(0x4601),
+ PSIL_PDMA_XY_PKT(0x4602),
+ PSIL_PDMA_XY_PKT(0x4603),
+ PSIL_PDMA_XY_PKT(0x4604),
+ PSIL_PDMA_XY_PKT(0x4605),
+ PSIL_PDMA_XY_PKT(0x4606),
+ PSIL_PDMA_XY_PKT(0x4607),
+ PSIL_PDMA_XY_PKT(0x4608),
+ PSIL_PDMA_XY_PKT(0x4609),
+ PSIL_PDMA_XY_PKT(0x460a),
+ PSIL_PDMA_XY_PKT(0x460b),
+ PSIL_PDMA_XY_PKT(0x460c),
+ PSIL_PDMA_XY_PKT(0x460d),
+ PSIL_PDMA_XY_PKT(0x460e),
+ PSIL_PDMA_XY_PKT(0x460f),
+ /* PDMA_SPI_G1 - SPI4-7 */
+ PSIL_PDMA_XY_PKT(0x4610),
+ PSIL_PDMA_XY_PKT(0x4611),
+ PSIL_PDMA_XY_PKT(0x4612),
+ PSIL_PDMA_XY_PKT(0x4613),
+ PSIL_PDMA_XY_PKT(0x4614),
+
Re: [PATCH v8 02/16] arm: mach-k3: Add basic support for J784S4 SoC definition
On 20/01/24 01:04, Nishanth Menon wrote:
On 23:20-20240119, Apurva Nandan wrote:
[...]
+void k3_spl_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ /*
+* Cannot delay this further as there is a chance that
+* K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
+*/
+ store_boot_info_from_rom();
+
+ /* Make all control module registers accessible */
+ ctrl_mmr_unlock();
+
+ if (IS_ENABLED(CONFIG_CPU_V7R)) {
+ disable_linefill_optimization();
+ setup_k3_mpu_regions();
+ }
+
+ /* Init DM early */
+ ret = spl_early_init();
+
+ /* Prepare console output */
+ preloader_console_init();
+
+ if (IS_ENABLED(CONFIG_CPU_V7R)) {
+ /*
+* Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and
continue
+* regardless of the result of pinctrl. Do this without probing
the
+* device, but instead by searching the device that would
request the
+* given sequence number if probed. The UART will be used by
the system
+* firmware (SYSFW) image for various purposes and SYSFW
depends on us
Nit pick - there is no SYSFW image anymore - it is either TIFS or DM.
+* to initialize its pin settings.
+*/
+ ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, );
+ if (!ret)
+ pinctrl_select_state(dev, "default");
+
+ /*
+* Load, start up, and configure system controller firmware.
Provide
+* the U-Boot console init function to the SYSFW post-PM
configuration
+* callback hook, effectively switching on (or over) the console
+* output.
+*/
+ k3_sysfw_loader(is_rom_loaded_sysfw(), NULL, NULL);
+
+ if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
+ /*
+* Force probe of clk_k3 driver here to ensure basic
default clock
+* configuration is always done for enabling PM
services.
+*/
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(ti_clk),
+ );
+ if (ret)
+ panic("Failed to initialize clk-k3!\n");
+ }
+
+ remove_fwl_configs(cbass_hc_cfg0_fwls,
ARRAY_SIZE(cbass_hc_cfg0_fwls));
+ remove_fwl_configs(cbass_hc2_fwls, ARRAY_SIZE(cbass_hc2_fwls));
+ remove_fwl_configs(cbass_rc_cfg0_fwls,
ARRAY_SIZE(cbass_rc_cfg0_fwls));
+ remove_fwl_configs(infra_cbass0_fwls,
ARRAY_SIZE(infra_cbass0_fwls));
+ remove_fwl_configs(mcu_cbass0_fwls,
ARRAY_SIZE(mcu_cbass0_fwls));
+ remove_fwl_configs(wkup_cbass0_fwls,
ARRAY_SIZE(wkup_cbass0_fwls));
+ remove_fwl_configs(navss_cbass0_fwls,
ARRAY_SIZE(navss_cbass0_fwls));
+ }
+
+ /* Output System Firmware version info */
+ k3_sysfw_print_ver();
+}
+
+void k3_mem_init(void)
+{
+ struct udevice *dev;
+ int ret, ctr = 1;
+
+ if (IS_ENABLED(CONFIG_K3_J721E_DDRSS)) {
+ ret = uclass_get_device(UCLASS_RAM, 0, );
+ if (ret)
+ panic("DRAM 0 init failed: %d\n", ret);
+
+ while (dev) {
why loop on dev? is it possible to have ret != 0 and dev = 0?
Some variable needs to be used for loop condition, do you want it to be ret?
or maybe you can suggest your idea for this please.
+ ret = uclass_next_device_err();
+ if (ret) {
+ printf("Initialized %d DRAM controllers\n",
ctr);
+ break;
+ }
+ ctr++;
What is the use of ctr++ ?? please do a limit check for instances.
This is to keep the logic independent of board evm, so that no include
of EVM config is needed.
ctr is just used to notify user about how many DDR are up during boot,
else it is not needed.
I can remove the ctr and printf, if you want.
For a limit check, how can we get number of DDR instances on the EVM, I
don't know, can you please suggest some way?
There is no config that stores this info afaik.
[...]
Next time, please respond to the review comment questions so that I
know that you have considered and decided something is not necessary
or something was missed in the new version - for example what happened
to mmc_stop/restart?
mmc_stop/restart were removed (mentioned in series changelog)
--
Regards,
Apurva Nandan,
Texas Instruments.
[PATCH 18/18] board: rockchip: add Theobroma-Systems RK3588 Jaguar SBC
From: Quentin Schulz
JAGUAR is a Single-Board Computer (SBC) based around the rk3588 SoC and
is targeting Autonomous Mobile Robots (AMR).
It features:
* LPDDR4X (up to 16GB)
* 1Gbps Ethernet on RJ45 connector (KSZ9031 or KSZ9131)
* PCIe 3.0 4-lane on M.2 M-key connector
* PCIe 2.1 1-lane on M.2 E-key
* USB 2.0 on M.2 E-key
* 2x USB3 OTG type-c ports with DP Alt-Mode
* USB2 host port
* HDMI output
* 2x camera connectors, each exposing:
* 2-lane MIPI-CSI
* 1v2, 1v8, 2v8 power rails
* I2C bus
* GPIOs
* PPS input
* CAN
* RS485 UART
* FAN connector
* SD card slot
* eMMC (up to 256GB)
* RTC backup battery
* Companion microcontroller
* ISL1208 RTC emulation
* AMC6821 PWM emulation
* On/off buzzer control
* Secure Element
* 80-pin Mezzanine connector for daughterboards:
* GPIOs
* 1Gbps Ethernet
* PCIe 2.1 1-lane
* 2x 2-lane MIPI-CSI
* ADC channel
* I2C bus
* PWM
* UART
* SPI
* SDIO
* CAN
* I2S
* 1v8, 3v3, 5v0, dc-in (12-24V) power rails
The Device Tree comes from next-20240110 Linux kernel.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
arch/arm/dts/rk3588-jaguar-u-boot.dtsi | 32 +
arch/arm/dts/rk3588-jaguar.dts | 803 +
arch/arm/mach-rockchip/rk3588/Kconfig | 28 +
board/theobroma-systems/jaguar_rk3588/Kconfig | 16 +
board/theobroma-systems/jaguar_rk3588/MAINTAINERS | 12 +
board/theobroma-systems/jaguar_rk3588/Makefile | 10 +
board/theobroma-systems/jaguar_rk3588/README | 118 +++
.../jaguar_rk3588/jaguar_rk3588.c | 52 ++
configs/jaguar-rk3588_defconfig| 115 +++
include/configs/jaguar_rk3588.h| 15 +
10 files changed, 1201 insertions(+)
diff --git a/arch/arm/dts/rk3588-jaguar-u-boot.dtsi
b/arch/arm/dts/rk3588-jaguar-u-boot.dtsi
new file mode 100644
index 000..59a3f9b41a9
--- /dev/null
+++ b/arch/arm/dts/rk3588-jaguar-u-boot.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include "rk3588-u-boot.dtsi"
+#include
+#include
+#include
+#include
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", ,
+ };
+};
+
+_pwrseq {
+ bootph-all;
+};
+
+_reset {
+ bootph-all;
+};
+
+ {
+ bootph-all;
+};
+
+ {
+ bootph-all;
+};
diff --git a/arch/arm/dts/rk3588-jaguar.dts b/arch/arm/dts/rk3588-jaguar.dts
new file mode 100644
index 000..4ce70fb75a3
--- /dev/null
+++ b/arch/arm/dts/rk3588-jaguar.dts
@@ -0,0 +1,803 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
+ */
+
+/dts-v1/;
+#include
+#include
+#include
+#include
+#include
+#include "rk3588.dtsi"
+
+/ {
+ model = "Theobroma Systems RK3588-SBC Jaguar";
+ compatible = "tsd,rk3588-jaguar", "rockchip,rk3588";
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = < 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <180>;
+ poll-interval = <100>;
+
+ /* Can be controlled through SW2 but also GPIO1 on CP2102 on
P20 */
+ button-bios-disable {
+ label = "BIOS_DISABLE";
+ linux,code = ;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
+ aliases {
+ ethernet0 =
+ mmc0 =
+ mmc1 =
+ rtc0 = _twi;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ /* DCIN is 12-24V but standard is 12V */
+ dc_12v: dc-12v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ pinctrl-0 = <_reset>;
+ pinctrl-names = "default";
+ reset-gpios = < RK_PA3 GPIO_ACTIVE_HIGH>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ status = "okay";
+
+ /* LED1 on PCB */
+ led-1 {
+ gpios = < RK_PD4 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_HEARTBEAT;
+ linux,default-trigger = "heartbeat";
+ color = ;
+ };
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ gpios = < RK_PD5 GPIO_ACTIVE_HIGH>;
+ };
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
[PATCH 14/18] rockchip: rk3588: add constants for some register address spaces
From: Quentin Schulz
It's one thing to have the register mapped via a well-defined struct but
it's another to be able to make use of it. For that to happen, one needs
to cast the physical address memory of the beginning of the register
address space with the struct. Since this cannot change, let's hardcode
it in the include files so that users do not need to duplicate this line
of code in their own implementation.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
arch/arm/include/asm/arch-rockchip/cru_rk3588.h | 2 ++
arch/arm/include/asm/arch-rockchip/ioc_rk3588.h | 6 ++
arch/arm/mach-rockchip/rk3588/rk3588.c | 4
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
index 7f4a9085392..a4507e5fdd7 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
@@ -63,6 +63,8 @@ struct rk3588_pll {
unsigned int reserved0[3];
};
+#define CRU_BASE 0xfd7c
+
struct rk3588_cru {
struct rk3588_pll pll[18];
unsigned int reserved0[16];/* Address Offset: 0x0240 */
diff --git a/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
index 5a656f850c7..7ad98466c39 100644
--- a/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
@@ -5,6 +5,8 @@
#ifndef _ASM_ARCH_IOC_RK3588_H
#define _ASM_ARCH_IOC_RK3588_H
+#define BUS_IOC_BASE 0xfd5f8000
+
struct rk3588_bus_ioc {
unsigned int reserved[3]; /* Address Offset: 0x */
unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x000C */
@@ -48,6 +50,8 @@ struct rk3588_bus_ioc {
check_member(rk3588_bus_ioc, gpio4d_iomux_sel_h, 0x009C);
+#define PMU1_IOC_BASE 0xfd5f
+
struct rk3588_pmu1_ioc {
unsigned int gpio0a_iomux_sel_l; /* Address Offset: 0x */
unsigned int gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */
@@ -70,6 +74,8 @@ struct rk3588_pmu1_ioc {
check_member(rk3588_pmu1_ioc, xin_con, 0x0040);
+#define PMU2_IOC_BASE 0xfd5f4000
+
struct rk3588_pmu2_ioc {
unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x */
unsigned int gpio0c_iomux_sel_l; /* Address Offset: 0x0004 */
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c
b/arch/arm/mach-rockchip/rk3588/rk3588.c
index c5eeda9d751..53ee9f1cebc 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -26,10 +26,6 @@
#define FW_SYSM_MST26_REG 0xa8
#define FW_SYSM_MST27_REG 0xac
-#define PMU1_IOC_BASE 0xfd5f
-#define PMU2_IOC_BASE 0xfd5f4000
-
-#define BUS_IOC_BASE 0xfd5f8000
#define BUS_IOC_GPIO2A_IOMUX_SEL_L 0x40
#define BUS_IOC_GPIO2B_IOMUX_SEL_L 0x48
#define BUS_IOC_GPIO2D_IOMUX_SEL_L 0x58
--
2.43.0
[PATCH 16/18] rockchip: include asm/io.h directly in asm/arch-rockchip/hardware.h
From: Quentin Schulz The different macros use writel which is defined in asm/io.h, so let's include the header so users of hardware.h do not need to include asm/io.h as well. While at it, remove asm/io.h includes wherever asm/arch-rockchip/hardware.h is included already. Cc: Quentin Schulz Signed-off-by: Quentin Schulz --- arch/arm/include/asm/arch-rockchip/hardware.h| 2 ++ arch/arm/mach-rockchip/cpu-info.c| 1 - arch/arm/mach-rockchip/px30/px30.c | 1 - arch/arm/mach-rockchip/rk3036/rk3036.c | 1 - arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 1 - arch/arm/mach-rockchip/rk3066/rk3066.c | 1 - arch/arm/mach-rockchip/rk3188/rk3188.c | 1 - arch/arm/mach-rockchip/rk322x/rk322x.c | 1 - arch/arm/mach-rockchip/rk3288/rk3288.c | 1 - arch/arm/mach-rockchip/rk3308/rk3308.c | 1 - arch/arm/mach-rockchip/rk3328/rk3328.c | 1 - arch/arm/mach-rockchip/rk3368/rk3368.c | 1 - arch/arm/mach-rockchip/rk3399/rk3399.c | 1 - arch/arm/mach-rockchip/rk3568/rk3568.c | 1 - arch/arm/mach-rockchip/rk3588/rk3588.c | 1 - arch/arm/mach-rockchip/rv1126/rv1126.c | 1 - board/elgin/elgin_rv1108/elgin_rv1108.c | 1 - board/firefly/firefly-rk3308/roc_cc_rk3308.c | 1 - board/google/gru/gru.c | 1 - board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c | 1 - board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c | 1 - board/pine64/rockpro64_rk3399/rockpro64-rk3399.c | 1 - board/rockchip/evb_rv1108/evb_rv1108.c | 1 - board/theobroma-systems/puma_rk3399/puma-rk3399.c| 1 - board/vamrs/rock960_rk3399/rock960-rk3399.c | 1 - drivers/clk/rockchip/clk_pll.c | 1 - drivers/clk/rockchip/clk_px30.c | 1 - drivers/clk/rockchip/clk_rk3036.c| 1 - drivers/clk/rockchip/clk_rk3066.c| 1 - drivers/clk/rockchip/clk_rk3128.c| 1 - drivers/clk/rockchip/clk_rk3188.c| 1 - drivers/clk/rockchip/clk_rk322x.c| 1 - drivers/clk/rockchip/clk_rk3288.c| 1 - drivers/clk/rockchip/clk_rk3308.c| 1 - drivers/clk/rockchip/clk_rk3328.c| 1 - drivers/clk/rockchip/clk_rk3368.c| 1 - drivers/clk/rockchip/clk_rk3399.c| 1 - drivers/clk/rockchip/clk_rk3568.c| 1 - drivers/clk/rockchip/clk_rk3588.c| 1 - drivers/clk/rockchip/clk_rv1108.c| 1 - drivers/clk/rockchip/clk_rv1126.c| 1 - drivers/gpio/rk_gpio.c | 1 - drivers/net/gmac_rockchip.c | 1 - drivers/ram/rockchip/dmc-rk3368.c| 1 - drivers/ram/rockchip/sdram_px30.c| 1 - drivers/ram/rockchip/sdram_rk3066.c | 1 - drivers/ram/rockchip/sdram_rk3188.c | 1 - drivers/ram/rockchip/sdram_rk322x.c | 1 - drivers/ram/rockchip/sdram_rk3288.c | 1 - drivers/ram/rockchip/sdram_rk3399.c | 1 - drivers/ram/rockchip/sdram_rv1126.c | 1 - drivers/rng/rockchip_rng.c | 1 - drivers/sysreset/sysreset_rockchip.c | 1 - drivers/video/rockchip/dw_mipi_dsi_rockchip.c| 1 - drivers/video/rockchip/rk3288_hdmi.c | 1 - drivers/video/rockchip/rk3288_mipi.c | 1 - drivers/video/rockchip/rk3288_vop.c | 1 - drivers/video/rockchip/rk3399_hdmi.c | 1 - drivers/video/rockchip/rk3399_mipi.c | 1 - drivers/video/rockchip/rk3399_vop.c | 1 - drivers/video/rockchip/rk_edp.c | 1 - drivers/video/rockchip/rk_hdmi.c | 1 - drivers/video/rockchip/rk_lvds.c | 1 - 63 files changed, 2 insertions(+), 62 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/hardware.h b/arch/arm/include/asm/arch-rockchip/hardware.h index 62e8bed8f31..e4662a2d52d 100644 --- a/arch/arm/include/asm/arch-rockchip/hardware.h +++ b/arch/arm/include/asm/arch-rockchip/hardware.h @@ -6,6 +6,8 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H +#include + #define RK_CLRSETBITS(clr, set)clr) | (set)) << 16) | (set)) #define RK_SETBITS(set)RK_CLRSETBITS(0, set) #define RK_CLRBITS(clr)RK_CLRSETBITS(clr, 0) diff --git
[PATCH 17/18] rockchip: rk3588: bind MMC controllers in U-Boot proper pre-reloc
From: Quentin Schulz
Since commit 9e644284ab81 ("dm: core: Report bootph-pre-ram/sram node as
pre-reloc after relocation"), bootph-pre-ram doesn't make U-Boot proper
bind the device before relocation.
While this is usually not much of an issue, it is when there's a lookup
for devices by code running before the relocation. Such is the case of
env_init() which calls env_driver_lookup() which calls
env_get_location() which is a weak symbol and may call
arch_env_get_location() also a weak symbol. Those are two functions that
may traverse UCLASS to find some devices (e.g.
board/theobroma-systems/common/common.c:arch_env_get_location()).
This allows something in the env_init() call stack to be able to use
uclasses for SD and eMMC controller on RK3588S/RK3588. This aligns the
behavior with what seems to be all SoCs except RK356x family.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
arch/arm/dts/rk3588s-u-boot.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 960ac4abda3..bdfe13836b2 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -187,12 +187,12 @@
};
{
- bootph-pre-ram;
+ bootph-all;
u-boot,spl-fifo-mode;
};
{
- bootph-pre-ram;
+ bootph-all;
u-boot,spl-fifo-mode;
};
--
2.43.0
[PATCH 15/18] rockchip: migrate hardware.h inclusion into appropriate files
From: Quentin Schulz Nothing of the hardware.h is used in include/configs, therefore, let's move that include to the files that actually require this include. Cc: Quentin Schulz Signed-off-by: Quentin Schulz --- arch/arm/mach-rockchip/rk3066/rk3066.c | 1 + drivers/ram/rockchip/dmc-rk3368.c | 1 + drivers/ram/rockchip/sdram_rk3188.c| 1 + drivers/ram/rockchip/sdram_rk3288.c| 1 + include/configs/rk3036_common.h| 1 - include/configs/rk3066_common.h| 1 - include/configs/rk3188_common.h| 1 - include/configs/rk322x_common.h| 1 - include/configs/rk3288_common.h| 1 - include/configs/rk3368_common.h| 1 - include/configs/rv1108_common.h| 1 - 11 files changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3066/rk3066.c b/arch/arm/mach-rockchip/rk3066/rk3066.c index 78c7d894f90..6661b788295 100644 --- a/arch/arm/mach-rockchip/rk3066/rk3066.c +++ b/arch/arm/mach-rockchip/rk3066/rk3066.c @@ -7,6 +7,7 @@ #include #include #include +#include #define GRF_BASE 0x20008000 diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c index f36be941a38..74d8aed571c 100644 --- a/drivers/ram/rockchip/dmc-rk3368.c +++ b/drivers/ram/rockchip/dmc-rk3368.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c index ad9f936df55..16a68885f1f 100644 --- a/drivers/ram/rockchip/sdram_rk3188.c +++ b/drivers/ram/rockchip/sdram_rk3188.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index c99118fd612..ec6bdcb2015 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index c2abd14e114..0bf9e8b9a2e 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -5,7 +5,6 @@ #ifndef __CONFIG_RK3036_COMMON_H #define __CONFIG_RK3036_COMMON_H -#include #include "rockchip-common.h" #define CFG_SYS_HZ_CLOCK 2400 diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h index d70c8f77d48..6a3b6900463 100644 --- a/include/configs/rk3066_common.h +++ b/include/configs/rk3066_common.h @@ -6,7 +6,6 @@ #ifndef __CONFIG_RK3066_COMMON_H #define __CONFIG_RK3066_COMMON_H -#include #include "rockchip-common.h" #define CFG_IRAM_BASE 0x1008 diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index a8cee1e44d4..98f2c25f3cf 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -6,7 +6,6 @@ #ifndef __CONFIG_RK3188_COMMON_H #define __CONFIG_RK3188_COMMON_H -#include #include "rockchip-common.h" #define CFG_IRAM_BASE 0x1008 diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 15f77df3e17..bab4ca015f7 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -5,7 +5,6 @@ #ifndef __CONFIG_RK322X_COMMON_H #define __CONFIG_RK322X_COMMON_H -#include #include "rockchip-common.h" #define CFG_SYS_HZ_CLOCK 2400 diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 3063076a97a..0c449e31099 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -6,7 +6,6 @@ #ifndef __CONFIG_RK3288_COMMON_H #define __CONFIG_RK3288_COMMON_H -#include #include "rockchip-common.h" #define CFG_SYS_HZ_CLOCK 2400 diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index ccb5369b901..d488f8d477a 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -8,7 +8,6 @@ #include "rockchip-common.h" -#include #include #define CFG_SYS_SDRAM_BASE 0 diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 3bf70a0e0ae..ff28236a21d 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -5,7 +5,6 @@ #ifndef __CONFIG_RV1108_COMMON_H #define __CONFIG_RV1108_COMMON_H -#include #include "rockchip-common.h" #define CFG_IRAM_BASE 0x1008 -- 2.43.0
[PATCH 13/18] rockchip: rk3588: fix non-working SD controller if booting from other media
From: Quentin Schulz
Rockchip SoCs have some jtag/sdmmc autoswitching that simply doesn't
work really well.[00] The Linux kernel disables it for all SoCs[01], so
U-Boot needs to do the same in order to fix issues related to SD card on
RK3588. This autoswitching is enabled (by default) via the force_jtag
bitfield in SYS_GRF_SOC_CON6 in the TRM part1.
For some reason, when booting from SD card, the BootROM does mux the
SDMMC controller in the proper configuration for the RK3588-Jaguar. But
when we don't boot from SD card, U-Boot needs to set it up correctly to
allow accessing SD cards in that configuration.
Therefore, let's disable the JTAG mode for the SDMMC pins so that the SD
controller can be used either as a fallback mechanism to find U-Boot
proper when the boot medium used to load TPL/SPL cannot find U-Boot
proper, or to be used in U-Boot CLI.
Note that soc_con[0] is reserved. But considering that it's way more
user-friendly to access soc_con1 from the TRM with soc_con[1] than
soc_con[0], and that soc_con0 would actually be located at 4 bytes
before soc_con1, let's just make soc_con0 part of the soc_con array.
[00]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c9b75d51c940c25587a2ad72ec7ec60490abfb6c
[01]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/soc/rockchip/grf.c
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
arch/arm/include/asm/arch-rockchip/grf_rk3588.h | 24
arch/arm/mach-rockchip/rk3588/rk3588.c | 7 +++
2 files changed, 31 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3588.h
b/arch/arm/include/asm/arch-rockchip/grf_rk3588.h
index e0694068bb1..f0ecff97f0b 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3588.h
@@ -32,4 +32,28 @@ struct rk3588_pmu1grf {
check_member(rk3588_pmu1grf, sd_detect_cnt, 0x03b0);
+#define SYS_GRF_BASE 0xfd58c000
+
+struct rk3588_sysgrf {
+ unsigned int wdt_con0;
+ unsigned int reserved0[(0x0010 - 0x) / 4 - 1];
+ unsigned int uart_con[2];
+ unsigned int reserved1[(0x00c0 - 0x0014) / 4 - 1];
+ unsigned int gic_con0;
+ unsigned int reserved2[(0x0200 - 0x00c0) / 4 - 1];
+ unsigned int memcfg_con[32];
+ unsigned int reserved3[(0x0300 - 0x027c) / 4 - 1];
+ /* soc_con0 is reserved */
+ unsigned int soc_con[14];
+ unsigned int reserved4[(0x0380 - 0x0334) / 4 - 1];
+ unsigned int soc_status[4];
+ unsigned int reserved5[(0x0500 - 0x038c) / 4 - 1];
+ unsigned int otp_key08;
+ unsigned int otp_key0d;
+ unsigned int otp_key0e;
+ unsigned int reserved6[(0x0600 - 0x0508) / 4 - 1];
+ unsigned int chip_id;
+};
+
+check_member(rk3588_sysgrf, chip_id, 0x0600);
#endif /*__SOC_ROCKCHIP_RK3588_GRF_H__ */
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c
b/arch/arm/mach-rockchip/rk3588/rk3588.c
index 38e95a6e2b2..c5eeda9d751 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#define FIREWALL_DDR_BASE 0xfe03
#define FW_DDR_MST5_REG0x54
@@ -35,6 +36,8 @@
#define BUS_IOC_GPIO2D_IOMUX_SEL_H 0x5c
#define BUS_IOC_GPIO3A_IOMUX_SEL_L 0x60
+#define SYS_GRF_FORCE_JTAG BIT(14)
+
/**
* Boot-device identifiers used by the BROM on RK3588 when device is booted
* from SPI flash. IOMUX used for SPI flash affect the value used by the BROM
@@ -134,6 +137,7 @@ void rockchip_stimer_init(void)
int arch_cpu_init(void)
{
#ifdef CONFIG_SPL_BUILD
+ static struct rk3588_sysgrf * const sys_grf = (void *)SYS_GRF_BASE;
int secure_reg;
/* Set the SDMMC eMMC crypto_ns FSPI access secure area */
@@ -168,6 +172,9 @@ int arch_cpu_init(void)
secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
secure_reg &= 0x;
writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
+
+ /* Disable JTAG exposed on SDMMC */
+ rk_clrreg(_grf->soc_con[6], SYS_GRF_FORCE_JTAG);
#endif
return 0;
--
2.43.0
[PATCH 12/18] rockchip: transform rockchip_capsule_update_board_setup into a weak function symbol
From: Quentin Schulz
There's only one user of rockchip_capsule_update_board_setup, which is
in board.c, and only one board defines it, so instead of having a header
only for one function symbol, let's just use a weak symbol instead.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
arch/arm/include/asm/arch-rockchip/misc.h | 9 -
arch/arm/mach-rockchip/board.c| 5 -
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/misc.h
b/arch/arm/include/asm/arch-rockchip/misc.h
deleted file mode 100644
index ef37ff1661a..000
--- a/arch/arm/include/asm/arch-rockchip/misc.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * RK3399: Architecture common definitions
- *
- * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/
- * Rohan Garg
- */
-
-void rockchip_capsule_update_board_setup(void);
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index 80b4514852f..4f666aee706 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -32,7 +32,6 @@
#include
#include
#include
-#include
#include
#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION)
@@ -148,6 +147,10 @@ void set_dfu_alt_info(char *interface, char *devstr)
env_set("dfu_alt_info", buf);
}
+__weak void rockchip_capsule_update_board_setup(void)
+{
+}
+
static void gpt_capsule_update_setup(void)
{
int p, i, ret;
--
2.43.0
[PATCH 09/18] rockchip: theobroma-systems: puma: migrate to rockchip_early_misc_init_r
From: Quentin Schulz
Only setup_iodomain() and setup_boottargets differ from the original
misc_init_r from Rockchip mach code, so let's use
rockchip_early_misc_init_r instead of reimplementing the whole
misc_init_r from Rockchip.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
board/theobroma-systems/puma_rk3399/puma-rk3399.c | 20 +---
1 file changed, 1 insertion(+), 19 deletions(-)
diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c
b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
index a82f97b2d54..98a818b135d 100644
--- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c
+++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
@@ -10,7 +10,6 @@
#include
#include
#include
-#include
#include "../common/common.h"
static void setup_iodomain(void)
@@ -27,25 +26,8 @@ static void setup_iodomain(void)
rk_setreg(>io_vsel, 1 << GRF_IO_VSEL_GPIO4CD_SHIFT);
}
-int misc_init_r(void)
+int rockchip_early_misc_init_r(void)
{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
-
- ret = rockchip_setup_macaddr();
- if (ret)
- return ret;
-
setup_iodomain();
setup_boottargets();
--
2.43.0
[PATCH 11/18] rockchip: merge misc.c into board.c
From: Quentin Schulz
The functions aren't used anywhere else than in board.c, therefore,
let's not expose them anymore at all.
This merges misc.c and board.c together and removes the functions from
the misc.h header file.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
arch/arm/include/asm/arch-rockchip/misc.h | 5 --
arch/arm/mach-rockchip/Makefile | 1 -
arch/arm/mach-rockchip/board.c| 125 +++
arch/arm/mach-rockchip/misc.c | 135 --
4 files changed, 125 insertions(+), 141 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/misc.h
b/arch/arm/include/asm/arch-rockchip/misc.h
index 4155af8c3b0..ef37ff1661a 100644
--- a/arch/arm/include/asm/arch-rockchip/misc.h
+++ b/arch/arm/include/asm/arch-rockchip/misc.h
@@ -6,9 +6,4 @@
* Rohan Garg
*/
-int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
- const u32 cpuid_length,
- u8 *cpuid);
-int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length);
-int rockchip_setup_macaddr(void);
void rockchip_capsule_update_board_setup(void);
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 1dc92066bbf..c07bdaee4c3 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -23,7 +23,6 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
# meaning "turn it off".
obj-y += boot_mode.o
obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
-obj-$(CONFIG_MISC_INIT_R) += misc.o
endif
ifeq ($(CONFIG_TPL_BUILD),)
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index d5cb59c10fa..80b4514852f 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -1,20 +1,32 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd.
+ *
+ * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/
+ * Rohan Garg
+ *
+ * Based on puma-rk3399.c:
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*/
#include
#include
#include
+#include
#include
#include
#include
+#include
#include
#include
#include
+#include
+#include
#include
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -297,6 +309,119 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason
reason)
#endif
#ifdef CONFIG_MISC_INIT_R
+int rockchip_setup_macaddr(void)
+{
+#if CONFIG_IS_ENABLED(HASH) && CONFIG_IS_ENABLED(SHA256)
+ int ret;
+ const char *cpuid = env_get("cpuid#");
+ u8 hash[SHA256_SUM_LEN];
+ int size = sizeof(hash);
+ u8 mac_addr[6];
+
+ /* Only generate a MAC address, if none is set in the environment */
+ if (env_get("ethaddr"))
+ return 0;
+
+ if (!cpuid) {
+ debug("%s: could not retrieve 'cpuid#'\n", __func__);
+ return -1;
+ }
+
+ ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, );
+ if (ret) {
+ debug("%s: failed to calculate SHA256\n", __func__);
+ return -1;
+ }
+
+ /* Copy 6 bytes of the hash to base the MAC address on */
+ memcpy(mac_addr, hash, 6);
+
+ /* Make this a valid MAC address and set it */
+ mac_addr[0] &= 0xfe; /* clear multicast bit */
+ mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+
+ /* Make a valid MAC address for ethernet1 */
+ mac_addr[5] ^= 0x01;
+ eth_env_set_enetaddr("eth1addr", mac_addr);
+#endif
+ return 0;
+}
+
+int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
+ const u32 cpuid_length,
+ u8 *cpuid)
+{
+#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE) || IS_ENABLED(CONFIG_ROCKCHIP_OTP)
+ struct udevice *dev;
+ int ret;
+
+ /* retrieve the device */
+#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE)
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(rockchip_efuse), );
+#elif IS_ENABLED(CONFIG_ROCKCHIP_OTP)
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(rockchip_otp), );
+#endif
+ if (ret) {
+ debug("%s: could not find efuse device\n", __func__);
+ return -1;
+ }
+
+ /* read the cpu_id range from the efuses */
+ ret = misc_read(dev, cpuid_offset, cpuid, cpuid_length);
+ if (ret < 0) {
+ debug("%s: reading cpuid from the efuses failed\n",
+ __func__);
+ return -1;
+ }
+#endif
+ return 0;
+}
+
+int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length)
+{
+ u8 low[cpuid_length / 2], high[cpuid_length / 2];
+ char cpuid_str[cpuid_length * 2 + 1];
+ u64 serialno;
+ char
[PATCH 10/18] rockchip: theobroma-systems: ringneck: migrate to rockchip_early_misc_init_r
From: Quentin Schulz
Only setup_boottargets differs from the original misc_init_r from
Rockchip mach code, so let's use rockchip_early_misc_init_r instead of
reimplementing the whole misc_init_r from Rockchip.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
.../theobroma-systems/ringneck_px30/ringneck-px30.c | 20 +---
1 file changed, 1 insertion(+), 19 deletions(-)
diff --git a/board/theobroma-systems/ringneck_px30/ringneck-px30.c
b/board/theobroma-systems/ringneck_px30/ringneck-px30.c
index ff7e414303d..bfebfe5136d 100644
--- a/board/theobroma-systems/ringneck_px30/ringneck-px30.c
+++ b/board/theobroma-systems/ringneck_px30/ringneck-px30.c
@@ -4,29 +4,11 @@
*/
#include
-#include
#include
#include "../common/common.h"
-int misc_init_r(void)
+int rockchip_early_misc_init_r(void)
{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
-
- ret = rockchip_setup_macaddr();
- if (ret)
- return ret;
-
setup_boottargets();
return 0;
--
2.43.0
[PATCH 08/18] rockchip: pine64: rockpro64: migrate to rockchip_early_misc_init_r
From: Quentin Schulz
Only setup_iodomain() differs from the original misc_init_r from
Rockchip mach code, so let's use rockchip_early_misc_init_r instead of
reimplementing the whole misc_init_r from Rockchip.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
board/pine64/rockpro64_rk3399/rockpro64-rk3399.c | 20 ++--
1 file changed, 2 insertions(+), 18 deletions(-)
diff --git a/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c
b/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c
index d79084614f1..d0a694ead1d 100644
--- a/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c
+++ b/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c
@@ -11,7 +11,6 @@
#include
#include
#include
-#include
#define GRF_IO_VSEL_BT565_SHIFT 0
#define PMUGRF_CON0_VSEL_SHIFT 8
@@ -31,26 +30,11 @@ static void setup_iodomain(void)
rk_setreg(>soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
}
-int misc_init_r(void)
+int rockchip_early_misc_init_r(void)
{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
setup_iodomain();
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
-
- ret = rockchip_setup_macaddr();
-
- return ret;
+ return 0;
}
#endif
--
2.43.0
[PATCH 07/18] rockchip: pine64: pinephone: migrate to rockchip_early_misc_init_r
From: Quentin Schulz
Compared to the original misc_init_r from Rockchip mach code,
setup_iodomain() is added and rockchip_setup_macaddr() is not called.
It is assumed adding rockchip_setup_macaddr() back is fine.
Let's use rockchip_early_misc_init_r instead of reimplementing the whole
misc_init_r from Rockchip (the side effect being that
rockchip_setup_macaddr() is back).
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
.../pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c | 17 ++---
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
index b6ccbb9c1c4..de75ee329d8 100644
--- a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
+++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
@@ -12,7 +12,6 @@
#include
#include
#include
-#include
#include
#define GRF_IO_VSEL_BT565_GPIO2AB 1
@@ -56,23 +55,11 @@ static void setup_iodomain(void)
rk_setreg(>soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
}
-int misc_init_r(void)
+int rockchip_early_misc_init_r(void)
{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
setup_iodomain();
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
+ return 0;
- return ret;
}
#endif
--
2.43.0
[PATCH 06/18] rockchip: pine64: pinebook: migrate to rockchip_early_misc_init_r
From: Quentin Schulz
Compared to the original misc_init_r from Rockchip mach code,
setup_iodomain() is added and rockchip_setup_macaddr() is not called.
It is assumed adding rockchip_setup_macaddr() back is fine.
Let's use rockchip_early_misc_init_r instead of reimplementing the whole
misc_init_r from Rockchip (the side effect being that
rockchip_setup_macaddr() is back).
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c | 18 ++
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
index 4ad780767ea..2408a367305 100644
--- a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
+++ b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
@@ -11,7 +11,6 @@
#include
#include
#include
-#include
#include
#include
@@ -54,23 +53,10 @@ static void setup_iodomain(void)
rk_setreg(>soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
}
-int misc_init_r(void)
+int rockchip_early_misc_init_r(void)
{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
setup_iodomain();
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
-
- return ret;
+ return 0;
}
#endif
--
2.43.0
[PATCH 05/18] rockchip: google: gru: migrate to rockchip_early_misc_init_r
From: Quentin Schulz
Only setup_iodomain() differs from the original misc_init_r from
Rockchip mach code, so let's use rockchip_early_misc_init_r instead of
reimplementing the whole misc_init_r from Rockchip.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
board/google/gru/gru.c | 20 ++--
1 file changed, 2 insertions(+), 18 deletions(-)
diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c
index fbcf845e87d..ecbf702b035 100644
--- a/board/google/gru/gru.c
+++ b/board/google/gru/gru.c
@@ -11,7 +11,6 @@
#include
#include
#include
-#include
#define GRF_IO_VSEL_BT656_SHIFT 0
#define GRF_IO_VSEL_AUDIO_SHIFT 1
@@ -85,24 +84,9 @@ static void setup_iodomain(void)
1 << PMUGRF_CON0_VOL_SHIFT));
}
-int misc_init_r(void)
+int rockchip_early_misc_init_r(void)
{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
setup_iodomain();
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
-
- ret = rockchip_setup_macaddr();
-
- return ret;
+ return 0;
}
--
2.43.0
[PATCH 04/18] rockchip: add weak function symbol called at the beginning of misc_init_r
From: Quentin Schulz
Most Rockchip boards who override misc_init_r do it only to call another
function and keep the rest unchanged. Therefore to allow for less
duplication, let's just add a weak function symbol that is called inside
misc_init_r.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
arch/arm/mach-rockchip/board.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index 2620530e03f..d5cb59c10fa 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -297,6 +297,11 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason
reason)
#endif
#ifdef CONFIG_MISC_INIT_R
+__weak int rockchip_early_misc_init_r(void)
+{
+ return 0;
+}
+
__weak int misc_init_r(void)
{
const u32 cpuid_offset = CFG_CPUID_OFFSET;
@@ -304,6 +309,10 @@ __weak int misc_init_r(void)
u8 cpuid[cpuid_length];
int ret;
+ ret = rockchip_early_misc_init_r();
+ if (ret)
+ return ret;
+
ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
if (ret)
return ret;
--
2.43.0
[PATCH 03/18] rockchip: avoid out-of-bounds when computing cpuid
From: Quentin Schulz
The expected length of the cpuid, as passed with cpuid_length,
determines the size of cpuid_str string. Therefore, care should be taken
to make sure nothing is accessing data out-of-bounds.
Instead of using hardcoded values, derive them from cpuid_length.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
arch/arm/mach-rockchip/misc.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-rockchip/misc.c b/arch/arm/mach-rockchip/misc.c
index 7d03f0c2b67..15397cff009 100644
--- a/arch/arm/mach-rockchip/misc.c
+++ b/arch/arm/mach-rockchip/misc.c
@@ -102,7 +102,7 @@ int rockchip_cpuid_set(const u8 *cpuid, const u32
cpuid_length)
int i;
memset(cpuid_str, 0, sizeof(cpuid_str));
- for (i = 0; i < 16; i++)
+ for (i = 0; i < cpuid_length; i++)
sprintf(_str[i * 2], "%02x", cpuid[i]);
debug("cpuid: %s\n", cpuid_str);
@@ -111,13 +111,13 @@ int rockchip_cpuid_set(const u8 *cpuid, const u32
cpuid_length)
* Mix the cpuid bytes using the same rules as in
* ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c
*/
- for (i = 0; i < 8; i++) {
+ for (i = 0; i < cpuid_length / 2; i++) {
low[i] = cpuid[1 + (i << 1)];
high[i] = cpuid[i << 1];
}
- serialno = crc32_no_comp(0, low, 8);
- serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
+ serialno = crc32_no_comp(0, low, cpuid_length / 2);
+ serialno |= (u64)crc32_no_comp(serialno, high, cpuid_length / 2) << 32;
snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno);
oldid = env_get("cpuid#");
--
2.43.0
[PATCH 02/18] rockchip: rk3588: sync rk3588s dtsi from v6.8-rc1
From: Heiko Stuebner
This brings the real host2_xhci node as well as the pmu1grf node and
spi0 to spi4 aliases from the next-20240110 Linux kernel. So also
adapt/remove the nodes and aliases in rk3588s-u-boot.dtsi
Signed-off-by: Heiko Stuebner
[sync with v6.8-rc1]
[remove spi0 to spi4 aliases from rk3588s-u-boot.dtsi]
Signed-off-by: Quentin Schulz
---
arch/arm/dts/rk3588s-u-boot.dtsi | 36 ++
arch/arm/dts/rk3588s.dtsi| 152 +++
2 files changed, 156 insertions(+), 32 deletions(-)
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 9a5ffec926e..960ac4abda3 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -7,11 +7,6 @@
/ {
aliases {
- spi0 =
- spi1 =
- spi2 =
- spi3 =
- spi4 =
spi5 =
};
@@ -43,33 +38,6 @@
status = "disabled";
};
- usb_host2_xhci: usb@fcd0 {
- compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3",
"snps,dwc3";
- reg = <0x0 0xfcd0 0x0 0x40>;
- interrupts = ;
- clocks = < REF_CLK_USB3OTG2>, < SUSPEND_CLK_USB3OTG2>,
-< ACLK_USB3OTG2>, < CLK_UTMI_OTG2>,
-< CLK_PIPEPHY2_PIPE_U3_G>;
- clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi",
"pipe";
- dr_mode = "host";
- phys = <_psu PHY_TYPE_USB3>;
- phy-names = "usb3-phy";
- phy_type = "utmi_wide";
- resets = < SRST_A_USB3OTG2>;
- snps,dis_enblslpm_quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis-del-phy-power-chg-quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- snps,dis_rxdet_inp3_quirk;
- status = "disabled";
- };
-
- pmu1_grf: syscon@fd58a000 {
- bootph-all;
- compatible = "rockchip,rk3588-pmugrf", "syscon";
- reg = <0x0 0xfd58a000 0x0 0x2000>;
- };
-
usbdpphy0_grf: syscon@fd5c8000 {
compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
reg = <0x0 0xfd5c8000 0x0 0x4000>;
@@ -201,6 +169,10 @@
status = "okay";
};
+ {
+ bootph-all;
+};
+
_grf {
bootph-pre-ram;
status = "okay";
diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi
index 61a9a11c3bb..36b1b7acfe6 100644
--- a/arch/arm/dts/rk3588s.dtsi
+++ b/arch/arm/dts/rk3588s.dtsi
@@ -18,6 +18,38 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ gpio0 =
+ gpio1 =
+ gpio2 =
+ gpio3 =
+ gpio4 =
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
+ i2c4 =
+ i2c5 =
+ i2c6 =
+ i2c7 =
+ i2c8 =
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
+ serial4 =
+ serial5 =
+ serial6 =
+ serial7 =
+ serial8 =
+ serial9 =
+ spi0 =
+ spi1 =
+ spi2 =
+ spi3 =
+ spi4 =
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -362,6 +394,11 @@
#clock-cells = <0>;
};
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <_out>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = ,
@@ -443,11 +480,47 @@
status = "disabled";
};
+ usb_host2_xhci: usb@fcd0 {
+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
+ reg = <0x0 0xfcd0 0x0 0x40>;
+ interrupts = ;
+ clocks = < REF_CLK_USB3OTG2>, < SUSPEND_CLK_USB3OTG2>,
+< ACLK_USB3OTG2>, < CLK_UTMI_OTG2>,
+< CLK_PIPEPHY2_PIPE_U3_G>;
+ clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi",
"pipe";
+ dr_mode = "host";
+ phys = <_psu PHY_TYPE_USB3>;
+ phy-names = "usb3-phy";
+ phy_type = "utmi_wide";
+ resets = < SRST_A_USB3OTG2>;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ snps,dis_rxdet_inp3_quirk;
+ status = "disabled";
+ };
+
+ pmu1grf: syscon@fd58a000 {
+ compatible = "rockchip,rk3588-pmugrf",
[PATCH 01/18] rockchip: rk3588: use mainline pmu-grf compatible
From: Heiko Stuebner
The compatible for the pmugrf in the mainline kernel is dfferent from the
one currently used in u-boot. Adapt the -u-boot.dtsi and syscon driver
to use the correct compatible.
Signed-off-by: Heiko Stuebner
Signed-off-by: Quentin Schulz
---
arch/arm/dts/rk3588s-u-boot.dtsi | 2 +-
arch/arm/mach-rockchip/rk3588/syscon_rk3588.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index c0fd16c4022..9a5ffec926e 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -66,7 +66,7 @@
pmu1_grf: syscon@fd58a000 {
bootph-all;
- compatible = "rockchip,rk3588-pmu1-grf", "syscon";
+ compatible = "rockchip,rk3588-pmugrf", "syscon";
reg = <0x0 0xfd58a000 0x0 0x2000>;
};
diff --git a/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c
b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c
index e8772d3a382..7b2cf37d9da 100644
--- a/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c
@@ -10,7 +10,7 @@
static const struct udevice_id rk3588_syscon_ids[] = {
{ .compatible = "rockchip,rk3588-sys-grf", .data = ROCKCHIP_SYSCON_GRF
},
- { .compatible = "rockchip,rk3588-pmu1-grf", .data =
ROCKCHIP_SYSCON_PMUGRF },
+ { .compatible = "rockchip,rk3588-pmugrf", .data =
ROCKCHIP_SYSCON_PMUGRF },
{ .compatible = "rockchip,rk3588-vop-grf", .data =
ROCKCHIP_SYSCON_VOP_GRF },
{ .compatible = "rockchip,rk3588-vo-grf", .data =
ROCKCHIP_SYSCON_VO_GRF },
{ .compatible = "rockchip,pcie30-phy-grf", .data =
ROCKCHIP_SYSCON_PCIE30_PHY_GRF },
--
2.43.0
[PATCH 00/18] rockchip: add support for Theobroma JAGUAR SBC-RK3588-AMR
/gru.c | 21 +- .../pinebook-pro-rk3399/pinebook-pro-rk3399.c | 19 +- .../pinephone-pro-rk3399/pinephone-pro-rk3399.c| 18 +- board/pine64/rockpro64_rk3399/rockpro64-rk3399.c | 21 +- board/rockchip/evb_rv1108/evb_rv1108.c | 1 - board/theobroma-systems/jaguar_rk3588/Kconfig | 16 + board/theobroma-systems/jaguar_rk3588/MAINTAINERS | 12 + board/theobroma-systems/jaguar_rk3588/Makefile | 10 + board/theobroma-systems/jaguar_rk3588/README | 118 +++ .../jaguar_rk3588/jaguar_rk3588.c | 52 ++ board/theobroma-systems/puma_rk3399/puma-rk3399.c | 21 +- .../ringneck_px30/ringneck-px30.c | 20 +- board/vamrs/rock960_rk3399/rock960-rk3399.c| 1 - configs/jaguar-rk3588_defconfig| 115 +++ drivers/clk/rockchip/clk_pll.c | 1 - drivers/clk/rockchip/clk_px30.c| 1 - drivers/clk/rockchip/clk_rk3036.c | 1 - drivers/clk/rockchip/clk_rk3066.c | 1 - drivers/clk/rockchip/clk_rk3128.c | 1 - drivers/clk/rockchip/clk_rk3188.c | 1 - drivers/clk/rockchip/clk_rk322x.c | 1 - drivers/clk/rockchip/clk_rk3288.c | 1 - drivers/clk/rockchip/clk_rk3308.c | 1 - drivers/clk/rockchip/clk_rk3328.c | 1 - drivers/clk/rockchip/clk_rk3368.c | 1 - drivers/clk/rockchip/clk_rk3399.c | 1 - drivers/clk/rockchip/clk_rk3568.c | 1 - drivers/clk/rockchip/clk_rk3588.c | 1 - drivers/clk/rockchip/clk_rv1108.c | 1 - drivers/clk/rockchip/clk_rv1126.c | 1 - drivers/gpio/rk_gpio.c | 1 - drivers/net/gmac_rockchip.c| 1 - drivers/ram/rockchip/dmc-rk3368.c | 2 +- drivers/ram/rockchip/sdram_px30.c | 1 - drivers/ram/rockchip/sdram_rk3066.c| 1 - drivers/ram/rockchip/sdram_rk3188.c| 2 +- drivers/ram/rockchip/sdram_rk322x.c| 1 - drivers/ram/rockchip/sdram_rk3288.c| 2 +- drivers/ram/rockchip/sdram_rk3399.c| 1 - drivers/ram/rockchip/sdram_rv1126.c| 1 - drivers/rng/rockchip_rng.c | 1 - drivers/sysreset/sysreset_rockchip.c | 1 - drivers/video/rockchip/dw_mipi_dsi_rockchip.c | 1 - drivers/video/rockchip/rk3288_hdmi.c | 1 - drivers/video/rockchip/rk3288_mipi.c | 1 - drivers/video/rockchip/rk3288_vop.c| 1 - drivers/video/rockchip/rk3399_hdmi.c | 1 - drivers/video/rockchip/rk3399_mipi.c | 1 - drivers/video/rockchip/rk3399_vop.c| 1 - drivers/video/rockchip/rk_edp.c| 1 - drivers/video/rockchip/rk_hdmi.c | 1 - drivers/video/rockchip/rk_lvds.c | 1 - include/configs/jaguar_rk3588.h| 15 + include/configs/rk3036_common.h| 1 - include/configs/rk3066_common.h| 1 - include/configs/rk3188_common.h| 1 - include/configs/rk322x_common.h| 1 - include/configs/rk3288_common.h| 1 - include/configs/rk3368_common.h| 1 - include/configs/rv1108_common.h| 1 - 91 files changed, 1553 insertions(+), 364 deletions(-) --- base-commit: 15e7927b5a2d33666af19879577bf0c30ab088fe change-id: 20240123-jaguar-efd00e57f56c Best regards, -- Quentin Schulz
Re: [PATCH v3 07/11] lib: vsprintf: enable '%pbl' format specifier
Hi Tom, On 18.01.2024 21:22, Tom Rini wrote: On Wed, Jan 10, 2024 at 10:10:33AM +0100, lukas.funke-...@weidmueller.com wrote: From: Lukas Funke The commit enables vsprintf() to handle the '%pbl' format specifier in order to print bitmaps and its derivatives such as cpumask and nodemask [1]. This can be used to derive kernel boot parameters from bitmaks such as 'isolcpu' or 'nohz_full' [2]. [1] https://www.kernel.org/doc/Documentation/printk-formats.txt [2] https://www.kernel.org/doc/html/latest/admin-guide/kernel-parameters.html Signed-off-by: Lukas Funke This breaks building ARC platforms, and possibly others. Note that tools/buildman/buildman is happy to fetch toolchains for you, and in this case it's also just the current kernel.org cross-toolchain. Please see https://docs.u-boot.org/en/latest/develop/ci_testing.html about how to trigger a CI run prior to sending v4, thanks. Thanks for the input. I ran the pipeline on github and it failed for riscv, m86k, x86_64. The reason is the missing 'find_next_zero_bit()' implementation (actually it's faulty on x86_64). What is a good way to cope with this problem? My suggestions would be: - Add a generic 'find_next_zero_bit()'. This would be the 'Linux way' and requires refactoring of the bitops header. - Add ifdef-macro/kconfig to only enable the format specifier only for the supported platforms. This would be the 'quick way'. What would be your or the maintainers preferred solution? Best regards Lukas
Re: [PATCH v8 04/16] arm: dts: Add bootph-all for memory node
On 20/01/24 00:55, Nishanth Menon wrote:
On 23:20-20240119, Apurva Nandan wrote:
[...]
diff --git a/arch/arm/dts/k3-am69-sk.dts b/arch/arm/dts/k3-am69-sk.dts
index 9868c7049b..29884097b9 100644
--- a/arch/arm/dts/k3-am69-sk.dts
+++ b/arch/arm/dts/k3-am69-sk.dts
I think you mis-interpreted
https://lore.kernel.org/u-boot/20240103175221.ovjzcwwljnjhka2n@expire/
comment to modify kernel board.dts. I meant for you to squash that
correct change to the patch that introduces board-u-boot.dtsi and r5.dts
Now that i read my comment, I can see why it might have been
mis-interpreted. Sorry about that - please squash your v7 patch
instead to appropriate patch.
Okay, will do.
@@ -33,6 +33,7 @@
memory@8000 {
device_type = "memory";
+ bootph-all;
/* 32G RAM */
reg = <0x00 0x8000 0x00 0x8000>,
<0x08 0x8000 0x07 0x8000>;
diff --git a/arch/arm/dts/k3-j784s4-evm.dts b/arch/arm/dts/k3-j784s4-evm.dts
index f1f4c8634a..662552c872 100644
--- a/arch/arm/dts/k3-j784s4-evm.dts
+++ b/arch/arm/dts/k3-j784s4-evm.dts
@@ -31,6 +31,7 @@
memory@8000 {
device_type = "memory";
+ bootph-all;
/* 32G RAM */
reg = <0x00 0x8000 0x00 0x8000>,
<0x08 0x8000 0x07 0x8000>;
--
2.34.1
--
Regards,
Apurva Nandan,
Texas Instruments.
Re: [PATCH v8 09/16] board: ti: j784s4: Add board support for J784S4 EVM
Hi Nishanth On 20/01/24 01:09, Nishanth Menon wrote: On 23:20-20240119, Apurva Nandan wrote: Add board files for J784S4 EVM. SYS_DISABLE_DCACHE_OPS is selected in the Kconfig because J784S4/AM69 are a coherent architecture at A72 level by MSMC support. Signed-off-by: Hari Nagalla [ add env and board specific yaml files for binman ] Neither of them are part of this patch? Signed-off-by: Neha Malcom Francis [ cleaned up the env files ] no env file in this patch? Will fix. Signed-off-by: Manorit Chawdhry Signed-off-by: Dasnavis Sabiya Signed-off-by: Apurva Nandan Reviewed-by: Tom Rini [...] diff --git a/board/ti/j784s4/MAINTAINERS b/board/ti/j784s4/MAINTAINERS new file mode 100644 index 00..9e0df11503 --- /dev/null +++ b/board/ti/j784s4/MAINTAINERS @@ -0,0 +1,14 @@ +J784S4 EVM BOARD +M: Apurva Nandan +S: Maintained +F: board/ti/j784s4 +F: arch/arm/mach-k3/j784s4 +F: include/configs/j784s4_evm.h +F: arch/arm/dts/k3-j784s4.dtsi +F: arch/arm/dts/k3-j784s4-main.dtsi +F: arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi +F: arch/arm/dts/k3-j784s4-thermal.dtsi +F: arch/arm/dts/k3-j784s4-evm.dts + +AM69 SK BOARD Don't all entries need a maintainer? I am not actually sure if the above M will fall through for SK board. Okay, will add M for AM69 as well. +F: arch/arm/dts/k3-am69-sk.dts diff --git a/board/ti/j784s4/Makefile b/board/ti/j784s4/Makefile new file mode 100644 index 00..60161a8b5c --- /dev/null +++ b/board/ti/j784s4/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ +# Hari Nagalla +# + +obj-y += evm.o diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c new file mode 100644 index 00..5af3e21ff0 --- /dev/null +++ b/board/ti/j784s4/evm.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Board specific initialization for J784S4 EVM + * + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Hari Nagalla + * + */ + +#include +#include +#include +#include Are you sure we need all the above headers? Ok, will cleanup +#include "../common/fdt_ops.h" [...] -- Regards, Apurva Nandan, Texas Instruments.
Re: [PATCH v8 13/16] arm: dts: Introduce am69-sk u-boot dts files
On 22/01/24 18:28, Roger Quadros wrote:
On 19/01/2024 19:50, Apurva Nandan wrote:
From: Dasnavis Sabiya
Introduce the base dts files needed for u-boot or to augment the linux
dtbs for use in the u-boot-spl and u-boot binaries.
Signed-off-by: Dasnavis Sabiya
Signed-off-by: Apurva Nandan
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/k3-am69-r5-sk.dts | 105
arch/arm/dts/k3-am69-sk-u-boot.dtsi | 48 +
board/ti/j784s4/MAINTAINERS | 2 +
4 files changed, 156 insertions(+)
create mode 100644 arch/arm/dts/k3-am69-r5-sk.dts
create mode 100644 arch/arm/dts/k3-am69-sk-u-boot.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 876802b88e..1c5a6662f6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1412,6 +1412,7 @@ dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\
k3-j721s2-r5-common-proc-board.dtb
dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-sk.dtb \
+ k3-am69-r5-sk.dtb \
k3-j784s4-evm.dtb \
k3-j784s4-r5-evm.dtb
diff --git a/arch/arm/dts/k3-am69-r5-sk.dts b/arch/arm/dts/k3-am69-r5-sk.dts
new file mode 100644
index 00..d2e73bd1bf
--- /dev/null
+++ b/arch/arm/dts/k3-am69-r5-sk.dts
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am69-sk.dts"
+#include "k3-j784s4-ddr-evm-lp4-4266.dtsi"
+#include "k3-j784s4-ddr.dtsi"
+#include "k3-am69-sk-u-boot.dtsi"
+
+/ {
+ chosen {
+ tick-timer = _timer0;
+ };
+
+ aliases {
+ remoteproc0 =
+ remoteproc1 = _0;
+ };
+
+ a72_0: a72@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x0 0x00a9 0x0 0x10>;
+ power-domains = <_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <_pds 202 TI_SCI_PD_EXCLUSIVE>;
+ resets = <_reset 202 0>;
+ clocks = <_clks 61 0>;
+ assigned-clocks = <_clks 61 0>, <_clks 202 0>;
+ assigned-clock-parents = <_clks 61 2>;
+ assigned-clock-rates = <2>, <20>;
+ ti,sci = <>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ bootph-pre-ram;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <3>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <_proxy_mcu 21>, <_proxy_mcu 23>;
+ bootph-pre-ram;
+ };
+};
+
+_timer0 {
+ status = "okay";
+ clock-frequency = <25000>;
+ bootph-pre-ram;
+};
+
+_proxy_sa3 {
+ status = "okay";
+ bootph-pre-ram;
+};
+
+_proxy_mcu {
+ status = "okay";
+ bootph-pre-ram;
+};
+
+_mcu_wakeup {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <_proxy_mcu 4>,
+ <_proxy_mcu 5>,
+ <_proxy_sa3 5>;
+ mbox-names = "tx", "rx", "boot_notify";
+ bootph-pre-ram;
+ };
+};
+
+ {
+ mboxes= <_proxy_mcu 8>, <_proxy_mcu 6>, <_proxy_mcu
5>;
+ mbox-names = "tx", "rx", "notify";
+ ti,host-id = <4>;
+ ti,secure-host;
+ bootph-pre-ram;
+};
+
+_uart0 {
+ bootph-pre-ram;
+ status = "okay";
In k3-am69-sk.dts this is marked as reserved. Why do you need to enable it here?
Maybe a comment would help readers.
Ohkay will fix.
+};
+
+ {
+ reg = <0x0 0x4704 0x0 0x100>,
+ <0x0 0x5000 0x0 0x800>;
+};
+
+ {
+ reg = <0x0 0x4705 0x0 0x100>,
+ <0x0 0x5800 0x0 0x800>;
+};
+
+_ringacc {
+ ti,sci = <_tifs>;
+};
+
+_udmap {
+ ti,sci = <_tifs>;
+};
diff --git a/arch/arm/dts/k3-am69-sk-u-boot.dtsi
b/arch/arm/dts/k3-am69-sk-u-boot.dtsi
new file mode 100644
index 00..4f8c99a1e6
--- /dev/null
+++ b/arch/arm/dts/k3-am69-sk-u-boot.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-j784s4-binman.dtsi"
+
+_udmap {
+ reg = <0x0 0x285c 0x0 0x100>,
+ <0x0 0x284c 0x0 0x4000>,
+ <0x0 0x2a80 0x0 0x4>,
+ <0x0 0x284a 0x0 0x4000>,
+ <0x0 0x2aa0 0x0 0x4>,
+ <0x0 0x2840 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
+ bootph-pre-ram;
+};
+
+ {
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ bootph-pre-ram;
+ };
+};
+
+#ifdef
Re: [PATCH v8 15/16] configs: Add am69_sk_* defconfig fragments
Hi Andrew, On 20/01/24 00:43, Andrew Davis wrote: On 1/19/24 11:50 AM, Apurva Nandan wrote: From: Dasnavis Sabiya Add config fragments for am69_sk A72 and R5 configuration. This applies on to: j784s4_evm_a72_defconfig -> am69_sk_a72.config j784s4_evm_r5_defconfig -> am69_sk_r5.config The usage model (with the fragment) would be: make j784s4_evm_a72_defconfig am69_sk_a72.config make OR make j784s4_evm_r5_defconfig am69_sk_r5.config make Signed-off-by: Dasnavis Sabiya Signed-off-by: Apurva Nandan --- board/ti/j784s4/MAINTAINERS | 2 ++ configs/am69_sk_a72.config | 5 + configs/am69_sk_r5.config | 5 + 3 files changed, 12 insertions(+) create mode 100644 configs/am69_sk_a72.config create mode 100644 configs/am69_sk_r5.config diff --git a/board/ti/j784s4/MAINTAINERS b/board/ti/j784s4/MAINTAINERS index 4433ead66b..69be13f533 100644 --- a/board/ti/j784s4/MAINTAINERS +++ b/board/ti/j784s4/MAINTAINERS @@ -20,3 +20,5 @@ AM69 SK BOARD F: arch/arm/dts/k3-am69-sk.dts F: arch/arm/dts/k3-am69-sk-u-boot.dtsi F: arch/arm/dts/k3-am69-r5-sk.dts +F: configs/am69_sk_r5.config +F: configs/am69_sk_a72.config diff --git a/configs/am69_sk_a72.config b/configs/am69_sk_a72.config new file mode 100644 index 00..03e74a8a56 --- /dev/null +++ b/configs/am69_sk_a72.config Just going to ignore the comments on v7 about putting this in board/ti/..? Sorry, somehow this got missed. Thanks for bringing up. Anyway, we can now do includes in defconfigs, so no config fragments needed, you can just add `configs/am69_evm_a72_defconfig` with the content: ``` #include CONFIG_ARM=y CONFIG_ARCH_K3=y CONFIG_SOC_K3_J784S4=y CONFIG_TARGET_J784S4_A72_EVM=y CONFIG_DEFAULT_DEVICE_TREE="k3-am69-sk" CONFIG_SPL_OF_LIST="k3-am69-sk" CONFIG_OF_LIST="k3-am69-sk" ``` (note we need to duplicate the _ARM/_TARGET currently to not confuse buildman which seems to directly parse the configs for arch detection). I tried it, but I don't think this works as '#' signifies a comment in defconfig, isn't that true? Andrew @@ -0,0 +1,5 @@ +# Defconfig fragment to apply on top of j784s4_evm_a72_defconfig + +CONFIG_DEFAULT_DEVICE_TREE="k3-am69-sk" +CONFIG_SPL_OF_LIST="k3-am69-sk" +CONFIG_OF_LIST="k3-am69-sk" diff --git a/configs/am69_sk_r5.config b/configs/am69_sk_r5.config new file mode 100644 index 00..c42b6f3380 --- /dev/null +++ b/configs/am69_sk_r5.config @@ -0,0 +1,5 @@ +# Defconfig fragment to apply on top of j784s4_evm_r5_defconfig + +CONFIG_DEFAULT_DEVICE_TREE="k3-am69-sk" +CONFIG_SPL_OF_LIST="k3-am69-r5-sk" +CONFIG_OF_LIST="k3-am69-r5-sk" -- Regards, Apurva Nandan, Texas Instruments.
test/py framework hangs on some tests with tbot integration
Hi! I am integrating tbot with uboot test/py framework, and some tests hangs the testing, after I investigated what does this hanging, I found that if the fixture of the test occur and configured in menuconfig it won't pass. I am not sure what I am doing wrong here. can someone guide me please to run it properly? br, Adnan El Hammoudi
Re: [PATCH v5 0/7] rpi5: initial support
Hi, as requested [1]: Tested-by: Jens Maus mailto:m...@jens-maus.de>> best regards, jens [1] https://lists.denx.de/pipermail/u-boot/2024-January/544243.html > Am 23.01.2024 um 09:07 schrieb Ivan T. Ivanov : > > This is new round of patches posted earlier here[1]. They are adding basic > support for RPi5 and are based on v2 series from Dmitry Malkin[2]. > > What changed sice v4: > > * Support for SDHCI controller in 2712 was simplified a lot. It turns out > that special registers accessors are not needed[3]. > > * Latest EEPROM firmware changed "kernel" load address from 0x8 > to 0x20. And because on RPi’s CONFIG_TEXT_BASE is set to 0x8 > code execution run through the grass. Switching to position indeended > code fixed this. > > These changes have been tested on following devices: > > Raspberry Pi 5 Model B Rev 1.0 > Raspberry Pi 4 Model B Rev 1.1 > Raspberry Pi 3 Model B Plus Rev 1.3 > Raspberry Pi Zero 2 W Rev 1.0 > Raspberry Pi 2 Model B Rev 1.2 > Raspberry Pi Compute Module 4 Rev 1.0 > Raspberry Pi Compute Module 3 Rev 1.0 > > Thanks, > Ivan > > [1] https://lore.kernel.org/all/20240110122908.31612-1-iiva...@suse.de/ > [2] > https://lore.kernel.org/all/CAKRNjQ0dsWozGo4n8g58m4cCEk3n=qx1r+l24wbgpo-ip1y...@mail.gmail.com/ > [3] > https://github.com/P33M/linux/commit/8a15e5d99667cb4499836d6f360246a69f020256 > > > Dmitry Malkin (2): > rpi5: add initial memory map for bcm2712 > rpi5: Use devicetree as alternative way to read IO base addresses > > Ivan T. Ivanov (5): > rpi5: Use devicetree to retrieve board revision > bcm2835: Dynamically calculate bytes per pixel parameter > mmc: bcmstb: Add support for bcm2712 SD controller > configs: rpi_arm64: enable SDHCI BCMSTB driver > configs: rpi_arm64: build position independent code > > arch/arm/mach-bcm283x/include/mach/base.h | 5 +- > arch/arm/mach-bcm283x/include/mach/mbox.h | 3 +- > arch/arm/mach-bcm283x/include/mach/sdhci.h | 3 +- > arch/arm/mach-bcm283x/include/mach/timer.h | 3 +- > arch/arm/mach-bcm283x/include/mach/wdog.h | 3 +- > arch/arm/mach-bcm283x/init.c | 74 +++--- > board/raspberrypi/rpi/rpi.c| 22 ++- > configs/rpi_arm64_defconfig| 3 +- > drivers/mmc/bcmstb_sdhci.c | 64 +-- > drivers/video/bcm2835.c| 18 +- > 10 files changed, 171 insertions(+), 27 deletions(-) > > -- > 2.43.0 > -- Jens Maus, Dresden/Germany http://jens-maus.de/
