Re: [PATCH] riscv: dts: jh7110: Enable PLL node in SPL
On 4/16/24 9:59 PM, E Shattow wrote: On Tue, Apr 9, 2024 at 11:44 PM Bo Gan wrote: On 4/9/24 6:55 PM, E Shattow wrote: Original speed class SD cards fail with this change "unable to change mode". The BUS_ROOT clock will have to be switched to PLL2 anyway in U-Boot proper or in Linux, because it's the parent or grandparent clock for *lots* of devices, including PCIe, i2c, spi, qspi... If there's an issue with this change, then I suspect there's something wrong with the dw_mmc driver. Bo I've bisected and can confirm this change is what breaks original speed SD function on Milk-V Mars CM Lite (DFRobot mini router carrier). Class 10 speed SD media does not seem to be affected. Reverting the change allows the original speed SD media access to function again. SD access is functional in Linux with and without the change. How to troubleshoot this? Thanks, E If without the change (reverted), can you read/write the same SD media in U-boot proper? (U-boot proper will switch BUS_ROOT to PLL2). One potential problem I could think of is perhaps the SPL built is without SPL_PINCTRL_STARFIVE/JH7110 or the u-boot dts is missing the pinctrl that properly sets drive-strength and other properties of the mmc0/1 pins. What dtb are you using? I tested this with visionfive2 and it's working fine. Can you share the tree/config you used to built for Milk-V Mars CM Lite? I don't see the corresponding dts being checked- in to u-boot tree, so it helps if you can share the code. Thanks! Bo
[PATCH RFC 9/9] sunxi: video: support HDMI on H6/H616
The H6 and H616 support outputting HDMI through the Display Engine.
Set up the clocks and resets appropriately for the HDMI controller.
This turns out to be a little tricky as the HDMI clock requires a
different parent on the H6 compared to the H616. So we have to end
up choosing VIDEO1 on the H616 and VIDEO0 elsewhere.
Signed-off-by: John Watts
---
arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 9 +++
arch/arm/mach-sunxi/clock_sun50i_h6.c | 10
drivers/video/sunxi/sunxi_dw_hdmi.c | 70 ---
3 files changed, 80 insertions(+), 9 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
index dfe8d9315f..35bd3dd2d8 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -376,13 +376,21 @@ struct sunxi_ccm_reg {
/* TCON0 clock bit field */
#define CCM_TCON0_CTRL_ENABLE (0x1 << 31)
#define CCM_TCON0_CTRL_VIDEO0_4X (0x1 << 24)
+#define CCM_TCON0_CTRL_VIDEO1_4X (0x3 << 24)
#define CCM_TCON0_CTRL_M(m)m) - 1) & 0xf) << 0)
/* TCON1 clock bit field */
#define CCM_TCON1_CTRL_ENABLE (0x1 << 31)
#define CCM_TCON1_CTRL_VIDEO0_4X (0x1 << 24)
+#define CCM_TCON1_CTRL_VIDEO1_4X (0x3 << 24)
#define CCM_TCON1_CTRL_M(m)m) - 1) & 0xf) << 0)
+/* HDMI clock bit field */
+#define CCM_HDMI_CTRL_ENABLE (0x1 << 31)
+#define CCM_HDMI_CTRL_VIDEO1_4X_H6 (0x2 << 24)
+#define CCM_HDMI_CTRL_VIDEO0_4X_H616 (0x1 << 24)
+#define CCM_HDMI_CTRL_M(m) m) - 1) & 0xf) << 0)
+
/* CCM bits common to all Display Engine 2.0 clock ctrl regs */
#define CCM_DE2_CTRL_M(n) n) - 1) & 0xf) << 0)
#define CCM_DE2_CTRL_PLL_MASK (3 << 24)
@@ -399,6 +407,7 @@ void clock_set_pll3(unsigned int hz);
void clock_set_video1(unsigned int hz);
void clock_set_pll10(unsigned int hz);
unsigned int clock_get_pll3(void);
+unsigned int clock_get_video1(void);
#endif
#endif
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c
b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index 11e303f801..23b7c13e28 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -230,4 +230,14 @@ unsigned int clock_get_pll3(void)
return 12000 * n * 1000;
}
+unsigned int clock_get_video1(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ u32 rval = readl(>pll_video1_cfg);
+ int n = ((rval & CCM_VIDEO1_CTRL_N_MASK) >> CCM_VIDEO1_CTRL_N_SHIFT) +
1;
+
+ return 12000 * n * 1000;
+}
+
#endif
diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c
b/drivers/video/sunxi/sunxi_dw_hdmi.c
index 34a6b8bab7..475d61a888 100644
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -198,6 +198,12 @@ static void sunxi_dw_hdmi_pll_set(uint clk_khz, int
*phy_div)
{
int value, n, m, div, diff;
int best_n = 0, best_m = 0, best_div = 0, best_diff = 0x0FFF;
+ int step = 24000, max_m = 16, pll_value = 0;
+
+ if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
+ step = 12000;
+ max_m = 1;
+ }
/*
* Find the lowest divider resulting in a matching clock. If there
@@ -212,11 +218,11 @@ static void sunxi_dw_hdmi_pll_set(uint clk_khz, int
*phy_div)
if (target > 912000)
continue;
- for (m = 1; m <= 16; m++) {
- n = (m * target) / 24000;
+ for (m = 1; m <= max_m; m++) {
+ n = (m * target) / step;
if (n >= 1 && n <= 128) {
- value = (24000 * n) / m / div;
+ value = (step * n) / m / div;
diff = clk_khz - value;
if (diff < best_diff) {
best_diff = diff;
@@ -231,13 +237,20 @@ static void sunxi_dw_hdmi_pll_set(uint clk_khz, int
*phy_div)
*phy_div = best_div;
#if IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)
- panic("setting HDMI pll not implemented");
+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) {
+ clock_set_video1(step * best_n);
+ pll_value = clock_get_video1();
+ } else {
+ clock_set_pll3(step * best_n);
+ pll_value = clock_get_pll3();
+ }
#else
clock_set_pll3_factors(best_m, best_n);
+ pll_value = clock_get_pll3();
#endif
debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n",
- clk_khz, (clock_get_pll3() / 1000) / best_div,
+ clk_khz, (pll_value / 1000) / best_div,
best_n, best_m, best_div);
}
@@ -246,12 +259,34 @@ static void
[PATCH RFC 8/9] sunxi: Enable display engine on H6/D1
Now that all the code is present and can compile, enable the DE2 so people can use it. Signed-off-by: John Watts --- arch/arm/mach-sunxi/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index ddf9414b08..9d76e429ef 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -202,6 +202,7 @@ config SUN50I_GEN_H6 select SPL_LOAD_FIT if SPL select MMC_SUNXI_HAS_NEW_MODE select SUPPORT_SPL + select SUNXI_DE2 ---help--- Select this for sunxi SoCs which have H6 like peripherals, clocks and memory map. @@ -210,6 +211,7 @@ config SUNXI_GEN_NCAT2 bool select MMC_SUNXI_HAS_NEW_MODE select SUPPORT_SPL + select SUNXI_DE2 ---help--- Select this for sunxi SoCs which have D1 like peripherals, clocks and memory map. -- 2.44.0
[PATCH RFC 7/9] sunxi: video: dummy out HDMI on H6/D1
I don't have any hardware to implement HDMI support on, but it's still
worth making the code compile for future work.
Adding HDMI support shouldn't be too difficult, though beware: The H6
and H616 both have a different set of HDMI clock parents. Future code
will most likely need to pick VIDEO0 or VIDEO1 to run the TCON and
HDMI encoder based on the chip.
Signed-off-by: John Watts
---
drivers/video/sunxi/sunxi_dw_hdmi.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c
b/drivers/video/sunxi/sunxi_dw_hdmi.c
index 0324a050d0..34a6b8bab7 100644
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -230,7 +230,12 @@ static void sunxi_dw_hdmi_pll_set(uint clk_khz, int
*phy_div)
*phy_div = best_div;
+#if IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)
+ panic("setting HDMI pll not implemented");
+#else
clock_set_pll3_factors(best_m, best_n);
+#endif
+
debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n",
clk_khz, (clock_get_pll3() / 1000) / best_div,
best_n, best_m, best_div);
@@ -244,6 +249,9 @@ static void sunxi_dw_hdmi_lcdc_init(int mux, const struct
display_timing *edid,
int div = DIV_ROUND_UP(clock_get_pll3(), edid->pixelclock.typ);
struct sunxi_lcdc_reg *lcdc;
+#if IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)
+ panic("initializing HDMI lcdc not implemented");
+#else
if (mux == 0) {
lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
@@ -265,6 +273,7 @@ static void sunxi_dw_hdmi_lcdc_init(int mux, const struct
display_timing *edid,
writel(CCM_LCD1_CTRL_GATE | CCM_LCD1_CTRL_M(div),
>lcd1_clk_cfg);
}
+#endif
lcdc_init(lcdc);
lcdc_tcon1_mode_set(lcdc, edid, false, false);
@@ -338,6 +347,9 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)
if (priv->hvcc)
regulator_set_enable(priv->hvcc, true);
+#if IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)
+ panic("initializing HDMI not implemented");
+#else
/* Set pll3 to 297 MHz */
clock_set_pll3(29700);
@@ -347,6 +359,7 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)
/* This reset is referenced from the PHY devicetree node. */
setbits_le32(>ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
+#endif
ret = reset_deassert_bulk(>resets);
if (ret)
--
2.44.0
[PATCH RFC 6/9] sunxi: video: silence unused use_mipi_pll warning
This variable is only used sometimes, so gate it behind an #ifdef. Signed-off-by: John Watts --- drivers/video/sunxi/lcdc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c index ea21d602be..1474f6cb2e 100644 --- a/drivers/video/sunxi/lcdc.c +++ b/drivers/video/sunxi/lcdc.c @@ -216,7 +216,10 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock, int value, n, m, min_m, max_m, diff, step; int best_n = 0, best_m = 0, best_diff = 0x0FFF; int best_double = 0; + +#ifdef CONFIG_MACH_SUN6I bool use_mipi_pll = false; +#endif #ifdef CONFIG_SUNXI_DE2 step = 6000; -- 2.44.0
[PATCH RFC 5/9] sunxi: video: enable DE2 on H6/D1
This requires just a little change to clocking and reset logic.
Signed-off-by: John Watts
---
drivers/video/sunxi/sunxi_de2.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c
index e02d359cd2..9b6c41b212 100644
--- a/drivers/video/sunxi/sunxi_de2.c
+++ b/drivers/video/sunxi/sunxi_de2.c
@@ -45,6 +45,23 @@ static void sunxi_de2_composer_init(void)
writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
#endif
+#if IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)
+ if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
+ /* Set DE parent to video1 */
+ clock_set_video1(43200);
+ clrsetbits_le32(>de_clk_cfg, CCM_DE2_CTRL_PLL_MASK,
+ CCM_DE2_CTRL_VIDEO1_4X_NCAT);
+ } else {
+ /* Set DE parent to pll10 */
+ clock_set_pll10(43200);
+ clrsetbits_le32(>de_clk_cfg, CCM_DE2_CTRL_PLL_MASK,
+ CCM_DE2_CTRL_PLL10_H6);
+ }
+
+ /* Ungate the DE */
+ setbits_le32(>de_gate_reset, BIT(RESET_SHIFT));
+ setbits_le32(>de_gate_reset, BIT(GATE_SHIFT));
+#else
clock_set_pll10(43200);
/* Set DE parent to pll10 */
@@ -54,6 +71,7 @@ static void sunxi_de2_composer_init(void)
/* Set ahb gating to pass */
setbits_le32(>ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE);
setbits_le32(>ahb_gate1, 1 << AHB_GATE_OFFSET_DE);
+#endif
/* Clock on */
setbits_le32(>de_clk_cfg, CCM_DE2_CTRL_GATE);
--
2.44.0
[PATCH RFC 4/9] sunxi: video: support LCD on H6/D1
The H6/D1/R528 don't require any big changes, just some small
tweaks to support new clock and reset logic.
Signed-off-by: John Watts
---
drivers/video/sunxi/lcdc.c | 20
drivers/video/sunxi/sunxi_lcd.c | 6 --
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c
index 73033c3b85..ea21d602be 100644
--- a/drivers/video/sunxi/lcdc.c
+++ b/drivers/video/sunxi/lcdc.c
@@ -277,6 +277,12 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int
dotclock,
}
}
+#if IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)
+ /* No need to clock doubling, just ask for a higher PLL clock */
+ best_double = 0;
+ step *= 2;
+#endif
+
#ifdef CONFIG_MACH_SUN6I
/*
* Use the MIPI pll if we've been unable to find any matching setting
@@ -302,6 +308,19 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int
dotclock,
best_double + 1, step, best_n, best_m);
}
+#if IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)
+ if (tcon == 0) {
+ writel(CCM_TCON0_CTRL_VIDEO0_4X | CCM_TCON0_CTRL_ENABLE,
+ >tcon_lcd0_clk_cfg);
+ setbits_le32(>tcon_lcd_gate_reset, BIT(RESET_SHIFT));
+ setbits_le32(>tcon_lcd_gate_reset, BIT(GATE_SHIFT));
+ } else {
+ writel(CCM_TCON1_CTRL_VIDEO0_4X | CCM_TCON1_CTRL_ENABLE,
+ >tcon_tv0_clk_cfg);
+ setbits_le32(>tcon_tv_gate_reset, BIT(RESET_SHIFT));
+ setbits_le32(>tcon_tv_gate_reset, BIT(GATE_SHIFT));
+ }
+#else
if (tcon == 0) {
u32 pll;
@@ -329,6 +348,7 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int
dotclock,
setbits_le32(>lcd0_ch1_clk_cfg,
CCM_LCD_CH1_CTRL_HALF_SCLK1);
}
+#endif
#endif
*clk_div = best_m;
diff --git a/drivers/video/sunxi/sunxi_lcd.c b/drivers/video/sunxi/sunxi_lcd.c
index 7a01cc343c..3b0e63233f 100644
--- a/drivers/video/sunxi/sunxi_lcd.c
+++ b/drivers/video/sunxi/sunxi_lcd.c
@@ -26,7 +26,7 @@ struct sunxi_lcd_priv {
static void sunxi_lcdc_config_pinmux(void)
{
-#ifdef CONFIG_MACH_SUN50I
+#if IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
IS_ENABLED(CONFIG_MACH_SUN8I_R528)
int pin;
for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(21); pin++) {
@@ -47,10 +47,12 @@ static int sunxi_lcd_enable(struct udevice *dev, int bpp,
struct udevice *backlight;
int clk_div, clk_double, ret;
+#if !IS_ENABLED(CONFIG_SUN50I_GEN_H6) && !IS_ENABLED(CONFIG_MACH_SUN8I_R528)
/* Reset off */
setbits_le32(>ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
/* Clock on */
setbits_le32(>ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
+#endif
lcdc_init(lcdc);
sunxi_lcdc_config_pinmux();
@@ -146,7 +148,7 @@ U_BOOT_DRIVER(sunxi_lcd) = {
.priv_auto = sizeof(struct sunxi_lcd_priv),
};
-#ifdef CONFIG_MACH_SUN50I
+#if IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
IS_ENABLED(CONFIG_MACH_SUN8I_R528)
U_BOOT_DRVINFO(sunxi_lcd) = {
.name = "sunxi_lcd"
};
--
2.44.0
[PATCH RFC 3/9] sunxi: sun50i-h6: Specify DE2 and LCD0 base addresses
These are used for operating the LCD on the H6/H616. Signed-off-by: John Watts --- arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h index 8a3f465545..2c9fe18289 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h @@ -31,6 +31,9 @@ #define SUNXI_DRAM_PHY0_BASE 0x0480 #endif +#define SUNXI_DE2_BASE 0x0100 +#define SUNXI_LCD0_BASE0x06515000 + #define SUNXI_TWI0_BASE0x05002000 #define SUNXI_TWI1_BASE0x05002400 #define SUNXI_TWI2_BASE0x05002800 -- 2.44.0
[PATCH RFC 2/9] sunxi: ncat2: Specify DE2 and LCD0 base addresses
These are used for operating the LCD on the D1/T113. Signed-off-by: John Watts --- arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h index 908a582ae0..4ae93b5095 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h @@ -25,6 +25,9 @@ #define SUNXI_MMC1_BASE0x04021000 #define SUNXI_MMC2_BASE0x04022000 +#define SUNXI_DE2_BASE 0x0500 +#define SUNXI_LCD0_BASE0x05461000 + #define SUNXI_R_CPUCFG_BASE0x07000400 #define SUNXI_PRCM_BASE0x0701 -- 2.44.0
[PATCH RFC 1/9] sunxi: clock: support H6/D1 video clocks
This code adds support for clocking VIDEO0 and VIDEO1, as well as
registers used for the DE2.
This code deliberately uses a 12MHz step in clocking to align with
the DE2 code's expectation of double 6MHz steps.
Signed-off-by: John Watts
---
arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 56 ++
arch/arm/mach-sunxi/clock_sun50i_h6.c | 71 +++
2 files changed, 127 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
index a84a57e5b4..dfe8d9315f 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -236,6 +236,28 @@ struct sunxi_ccm_reg {
#define CCM_PLL1_CTRL_P(p) ((p) << 16)
#define CCM_PLL1_CTRL_N(n) (((n) - 1) << 8)
+/* pll3 (video0) bit field */
+#define CCM_PLL3_CTRL_EN BIT(31)
+#define CCM_PLL3_LDO_ENBIT(30)
+#define CCM_PLL3_LOCK_EN BIT(29)
+#define CCM_PLL3_LOCK BIT(28)
+#define CCM_PLL3_OUT_ENBIT(27)
+#define CCM_PLL3_INPUT_DIV2BIT(1)
+#define CCM_PLL3_CTRL_N(n) (((n) - 1) << 8)
+#define CCM_PLL3_CTRL_N_SHIFT 8
+#define CCM_PLL3_CTRL_N_MASK (0xff << CCM_PLL3_CTRL_N_SHIFT)
+
+/* video1 bit field */
+#define CCM_VIDEO1_CTRL_EN BIT(31)
+#define CCM_VIDEO1_LDO_EN BIT(30)
+#define CCM_VIDEO1_LOCK_EN BIT(29)
+#define CCM_VIDEO1_LOCKBIT(28)
+#define CCM_VIDEO1_OUT_EN BIT(27)
+#define CCM_VIDEO1_INPUT_DIV2 BIT(1)
+#define CCM_VIDEO1_CTRL_N(n) (((n) - 1) << 8)
+#define CCM_VIDEO1_CTRL_N_SHIFT8
+#define CCM_VIDEO1_CTRL_N_MASK (0xff << CCM_VIDEO1_CTRL_N_SHIFT)
+
/* pll5 bit field */
#define CCM_PLL5_CTRL_EN BIT(31)
#define CCM_PLL5_LOCK_EN BIT(29)
@@ -258,6 +280,16 @@ struct sunxi_ccm_reg {
#define CCM_PLL6_CTRL_DIV2_SHIFT 1
#define CCM_PLL6_CTRL_DIV2_MASK(0x1 <<
CCM_PLL6_CTRL_DIV2_SHIFT)
+/* pll10 bit field */
+#define CCM_PLL10_CTRL_EN BIT(31)
+#define CCM_PLL10_LOCK_EN BIT(29)
+#define CCM_PLL10_LOCK BIT(28)
+#define CCM_PLL10_OUT_EN BIT(27)
+#define CCM_PLL10_INPUT_DIV2 BIT(1)
+#define CCM_PLL10_CTRL_N(n)(((n) - 1) << 8)
+#define CCM_PLL10_CTRL_N_SHIFT 8
+#define CCM_PLL10_CTRL_N_MASK (0xff << CCM_PLL10_CTRL_N_SHIFT)
+
/* cpu_axi bit field*/
#define CCM_CPU_AXI_MUX_MASK (0x3 << 24)
#define CCM_CPU_AXI_MUX_OSC24M (0x0 << 24)
@@ -341,9 +373,33 @@ struct sunxi_ccm_reg {
#define CCM_MMC_CTRL_OCLK_DLY(a) ((void) (a), 0)
#define CCM_MMC_CTRL_SCLK_DLY(a) ((void) (a), 0)
+/* TCON0 clock bit field */
+#define CCM_TCON0_CTRL_ENABLE (0x1 << 31)
+#define CCM_TCON0_CTRL_VIDEO0_4X (0x1 << 24)
+#define CCM_TCON0_CTRL_M(m)m) - 1) & 0xf) << 0)
+
+/* TCON1 clock bit field */
+#define CCM_TCON1_CTRL_ENABLE (0x1 << 31)
+#define CCM_TCON1_CTRL_VIDEO0_4X (0x1 << 24)
+#define CCM_TCON1_CTRL_M(m)m) - 1) & 0xf) << 0)
+
+/* CCM bits common to all Display Engine 2.0 clock ctrl regs */
+#define CCM_DE2_CTRL_M(n) n) - 1) & 0xf) << 0)
+#define CCM_DE2_CTRL_PLL_MASK (3 << 24)
+#define CCM_DE2_CTRL_PLL10_H6 (0 << 24)
+#define CCM_DE2_CTRL_VIDEO1_4X_NCAT(2 << 24)
+#define CCM_DE2_CTRL_GATE (0x1 << 31)
+
#ifndef __ASSEMBLY__
void clock_set_pll1(unsigned int hz);
unsigned int clock_get_pll6(void);
+
+#ifdef CONFIG_SUNXI_DE2
+void clock_set_pll3(unsigned int hz);
+void clock_set_video1(unsigned int hz);
+void clock_set_pll10(unsigned int hz);
+unsigned int clock_get_pll3(void);
+#endif
#endif
#endif /* _SUNXI_CLOCK_SUN50I_H6_H */
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c
b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index dac3663e1b..11e303f801 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -160,3 +160,74 @@ int clock_twi_onoff(int port, int state)
return 0;
}
+
+#ifdef CONFIG_SUNXI_DE2
+
+void clock_set_pll3(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ if (clk == 0) {
+ clrbits_le32(>pll3_cfg, CCM_PLL3_CTRL_EN);
+ return;
+ }
+
+ /* PLL3 rate = 2400 * n / 2 */
+ writel(CCM_PLL3_CTRL_EN | CCM_PLL3_LOCK_EN | CCM_PLL3_OUT_EN |
CCM_PLL3_LDO_EN |
+ CCM_PLL3_INPUT_DIV2 | CCM_PLL3_CTRL_N(clk / 1200),
+ >pll3_cfg);
+
+ while (!(readl(>pll3_cfg) & CCM_PLL3_LOCK))
+ ;
+}
+
+void clock_set_video1(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+
[PATCH RFC 0/9] sunxi: video: Support LCD and HDMI output on H6/D1
This patch series is my first attempt at supporting an LCD panel on the T113. I can confirm this specific use case works, but I've added code for the H6/H616 too in the process as a lot of the logic is the same. I've also included an untested patch for HDMI support at the end in case anyone wants to work on it. It compiles and looks like it should work, but I haven't ungated/reset the slow HDMI clock, or HDMI sub. Signed-off-by: John Watts --- John Watts (9): sunxi: clock: support H6/D1 video clocks sunxi: ncat2: Specify DE2 and LCD0 base addresses sunxi: sun50i-h6: Specify DE2 and LCD0 base addresses sunxi: video: support LCD on H6/D1 sunxi: video: enable DE2 on H6/D1 sunxi: video: silence unused use_mipi_pll warning sunxi: video: dummy out HDMI on H6/D1 sunxi: Enable display engine on H6/D1 sunxi: video: support HDMI on H6/H616 arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 65 ++ arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h | 3 + arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h | 3 + arch/arm/mach-sunxi/Kconfig | 2 + arch/arm/mach-sunxi/clock_sun50i_h6.c | 81 +++ drivers/video/sunxi/lcdc.c| 23 +++ drivers/video/sunxi/sunxi_de2.c | 18 + drivers/video/sunxi/sunxi_dw_hdmi.c | 77 +++-- drivers/video/sunxi/sunxi_lcd.c | 6 +- 9 files changed, 270 insertions(+), 8 deletions(-) --- base-commit: 1f1bbbdf85b67316770a6964a4a02b73a720a167 change-id: 20240420-d1_de2-9be81d56bd85 Best regards, -- John Watts
[PATCH] ARM: stm32: Ping IWDG on exit from PSCI suspend code
Make sure the OS would not get any spurious IWDG pretimeout IRQ
right after the system wakes up. This may happen in case the SoC
got woken up by another source than the IWDG pretimeout and the
pretimeout IRQ arrived immediately afterward, but too late to be
handled by the suspend main loop. In case either of the IWDG is
enabled, ping it first and then return to the OS.
Signed-off-by: Marek Vasut
---
Cc: Igor Opaniuk
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: Simon Glass
Cc: Tom Rini
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/mach-stm32mp/stm32mp1/psci.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c
b/arch/arm/mach-stm32mp/stm32mp1/psci.c
index 4f2379df45f..e99103910d9 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/psci.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c
@@ -808,6 +808,27 @@ void __secure psci_system_suspend(u32 __always_unused
function_id,
writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR);
clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
+ /*
+* Make sure the OS would not get any spurious IWDG pretimeout IRQ
+* right after the system wakes up. This may happen in case the SoC
+* got woken up by another source than the IWDG pretimeout and the
+* pretimeout IRQ arrived immediately afterward, but too late to be
+* handled by the main loop above. In case either of the IWDG is
+* enabled, ping it first and then return to the OS.
+*/
+
+ /* Ping IWDG1 and ACK pretimer IRQ */
+ if (gic_enabled[4] & BIT(22)) {
+ writel(IWDG_KR_RELOAD_KEY, STM32_IWDG1_BASE + IWDG_KR);
+ writel(IWDG_EWCR_EWIC, STM32_IWDG1_BASE + IWDG_EWCR);
+ }
+
+ /* Ping IWDG2 and ACK pretimer IRQ */
+ if (gic_enabled[4] & BIT(23)) {
+ writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR);
+ writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR);
+ }
+
/*
* The system has resumed successfully. Rewrite LR register stored
* on stack with 'ep' value, so that on return from this PSCI call,
--
2.43.0
Re: [PULL] Pull request for u-boot master / v2024.07 = u-boot-stm32-20240419
On Fri, Apr 19, 2024 at 02:01:47PM +0200, Patrice CHOTARD wrote: > Hi Tom > > Please pull the STM32 related patches for u-boot/master, v2024.07: > u-boot-stm32-20240419 > > CI status: > https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/20430 > > > The following changes since commit 97b34f6ace539c9c16eb8565f8b58730848ba97a: > > env: mmc: print MMC device being read (2024-04-18 16:37:25 -0600) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-stm.git > tags/u-boot-stm32-20240419 > > for you to fetch changes up to b0283b5e3d37daff48b45c3f98d298844603def4: > > ARM: dts: stm32: Add led-blue for stm32mp157c-ed1-scmi-u-boot (2024-04-19 > 12:05:10 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [GIT PULL] Please pull u-boot-dfu-20240419
On Fri, Apr 19, 2024 at 11:48:58AM +0200, Mattijs Korpershoek wrote: > Hi Tom, > > Here is a new development for master: > > - new "fastboot oem board" command > > This CI job is at > https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/20427 > > Thanks, > Mattijs > > The following changes since commit 2c3fa4b8add3cb6a440184ab67debc6867d383c0: > > sandbox: don't call os_close with invalid file descriptor (2024-04-17 > 17:06:16 -0600) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-dfu.git > tags/u-boot-dfu-20240419 > > for you to fetch changes up to b2acf59baf917c3b4002c1b2094ddb46c03ab02e: > > fastboot: introduce 'oem board' subcommand (2024-04-18 14:54:38 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: Pull request for tpm-master-18042024
On Thu, Apr 18, 2024 at 08:14:01PM +0300, Ilias Apalodimas wrote:
> OP-TEE fixes only on this PR, no TPM related ones.
>
> The following changes since commit 2c3fa4b8add3cb6a440184ab67debc6867d383c0:
>
> sandbox: don't call os_close with invalid file descriptor (2024-04-17
> 17:06:16 -0600)
>
> are available in the Git repository at:
>
> https://source.denx.de/u-boot/custodians/u-boot-tpm/
> tags/tpm-master-18042024
>
> for you to fetch changes up to b905599b36e3d8158c5cd045c26278416909b422:
>
> tee: remove common.h inclusion (2024-04-18 16:04:48 +0300)
>
> Igor says:
> "The problem initially was in the TEE sandbox driver implementation
> (drivers/tee/sandbox.c) and it's limitations, which doesn't
> permit to have multiple simultaneous sessions with different TAs.
> This is what actually happened in this CI run [1], firstly "optee_rpmb"
> cmd was executed (and after execution we had one session open), and
> then "scp03", which also makes calls to OP-TEE, however it fails
> in sandbox_tee_open_session() because of this check:
>
> if (state->ta) {
> printf("A session is already open\n");
> return -EBUSY;
> }
>
> I had two ways in mind to address that:
> 1. Close a session on each optee_rpmb cmd invocation.
> I don't see any reason to keep this session open, as obviously
> there is no other mechanism (tbh, I don't know if DM calls ".remove" for
> active
> devices) to close it automatically before handing over control to
> Linux kernel. As a result we might end up with some orphaned sessions
> registered in OP-TEE OS core (obvious resource leak).
> 2. Extend TEE sandbox driver, add support for multiple
> simultaneous sessions just to handle the case.
>
> I've chosen the first approach, as IMO it was "kill two birds with one
> stone",
> I could address resource leak in OP-TEE and bypass limitations of
> TEE sandbox driver."
>
> Link:
> https://lore.kernel.org/u-boot/CAByghJZVRbnFUwJdgU534tvGA+DX2pArf0i7ySik=brxgad...@mail.gmail.com/
>
> The CI https://source.denx.de/u-boot/custodians/u-boot-tpm/-/pipelines/20414
> showed no problems
>
> Please pull
> /Ilias
>
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
[PATCH v2 6/7] dts: am62x: binman: Include firmware capsules binman nodes
Fill in the am62x SK's capsule GUID properties of the base binman capsule
nodes.
Signed-off-by: Jonathan Humphreys
---
arch/arm/dts/k3-am625-sk-binman.dtsi | 30
1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi
b/arch/arm/dts/k3-am625-sk-binman.dtsi
index dfd38d64f63..eadfa398fa3 100644
--- a/arch/arm/dts/k3-am625-sk-binman.dtsi
+++ b/arch/arm/dts/k3-am625-sk-binman.dtsi
@@ -137,6 +137,17 @@
};
};
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsule update GUIDs in string form. See am62x_evm.h
+#define AM62X_SK_TIBOOT3_IMAGE_GUID_STR "abcb83d2-9cb6-4351-b8f1-6494bbe3700a"
+
+_tiboot3 {
+ efi-capsule {
+ image-guid = AM62X_SK_TIBOOT3_IMAGE_GUID_STR;
+ };
+};
+
#endif
#ifdef CONFIG_TARGET_AM625_A53_EVM
@@ -452,4 +463,23 @@
};
};
};
+
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form. See am62x_evm.h
+#define AM62X_SK_SPL_IMAGE_GUID_STR "aee355fc-bf97-4264-8c82-437255efdc1d"
+#define AM62X_SK_UBOOT_IMAGE_GUID_STR "28ab8c6c-fca8-41d3-8ea1-5f171b7d2929"
+
+_tispl {
+ efi-capsule {
+ image-guid = AM62X_SK_SPL_IMAGE_GUID_STR;
+ };
+};
+
+_uboot {
+ efi-capsule {
+ image-guid = AM62X_SK_UBOOT_IMAGE_GUID_STR;
+ };
+};
+
#endif
--
2.34.1
[PATCH v2 4/7] dts: beagleplay: binman: Include firmware capsules binman nodes
Fill in the BeaglePlay's capsule GUID properties of the base binman capsule
nodes.
Signed-off-by: Jonathan Humphreys
---
arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi | 27
arch/arm/dts/k3-am625-r5-beagleplay.dts | 15 +++
2 files changed, 42 insertions(+)
diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
index fb2032068d1..f7c21a1f0e0 100644
--- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
@@ -205,4 +205,31 @@
};
};
};
+
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form. See beagleplay.h
+#define BEAGLEPLAY_SPL_IMAGE_GUID_STR "b2e7cc49-1a5a-4036-ae01-3387c3bef657"
+#define BEAGLEPLAY_UBOOT_IMAGE_GUID_STR "92c92b11-a7ee-486f-aaa2-713d84425b0e"
+
+_tispl {
+ efi-capsule {
+ image-guid = BEAGLEPLAY_SPL_IMAGE_GUID_STR;
+
+ blob {
+ filename = "tispl.bin_unsigned";
+ };
+ };
+};
+
+_uboot {
+ efi-capsule {
+ image-guid = BEAGLEPLAY_UBOOT_IMAGE_GUID_STR;
+
+ blob {
+ filename = "u-boot.img_unsigned";
+ };
+ };
+};
+
#endif
diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts
b/arch/arm/dts/k3-am625-r5-beagleplay.dts
index 9db58f093c8..162d4800b17 100644
--- a/arch/arm/dts/k3-am625-r5-beagleplay.dts
+++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts
@@ -114,3 +114,18 @@
};
};
+
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsule update GUIDs in string form. See beagleplay.h
+#define BEAGLEPLAY_TIBOOT3_IMAGE_GUID_STR
"0e225a09-f720-4d57-9120-e28f737f5a5e"
+
+_tiboot3 {
+ efi-capsule {
+ image-guid = BEAGLEPLAY_TIBOOT3_IMAGE_GUID_STR;
+
+ blob {
+ filename = "tiboot3-am62x-gp-evm.bin";
+ };
+ };
+};
--
2.34.1
[PATCH v2 0/7] binman: ti: create binman nodes for EFI capsules
Add binman nodes for EFI capsules of firmware components so that capsules are automatically created during the UBoot builds. This is enabled for several TI SoC based platforms: AM64, AM62, AM62p, BeaglePlay, J7, and BeagleboneAI. Changes from v1: - on GP devices, still use signed images in capsules where available - Insert board specific capsule GUIDs into the capsule node's image-guid. Jonathan Humphreys (7): dts: ti: binman: Add base K3 firmware capsule nodes dts: am64x: binman: Include firmware capsules binman nodes dts: j721e: binman: Include firmware capsules binman nodes dts: beagleplay: binman: Include firmware capsules binman nodes dts: am62px: binman: Include firmware capsules binman nodes dts: am62x: binman: Include firmware capsules binman nodes dts: beagleboneai64: binman: Include firmware capsules binman nodes arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi | 27 ++ arch/arm/dts/k3-am625-r5-beagleplay.dts | 15 ++ arch/arm/dts/k3-am625-sk-binman.dtsi | 30 arch/arm/dts/k3-am62p-sk-binman.dtsi | 29 +++ arch/arm/dts/k3-am64x-binman.dtsi | 30 arch/arm/dts/k3-binman-capsule-r5.dtsi| 21 arch/arm/dts/k3-binman-capsule.dtsi | 38 ++ .../dts/k3-j721e-beagleboneai64-u-boot.dtsi | 23 + arch/arm/dts/k3-j721e-binman.dtsi | 49 +++ arch/arm/dts/k3-j721e-r5-beagleboneai64.dts | 29 +++ 10 files changed, 291 insertions(+) create mode 100644 arch/arm/dts/k3-binman-capsule-r5.dtsi create mode 100644 arch/arm/dts/k3-binman-capsule.dtsi -- 2.34.1
[PATCH v2 2/7] dts: am64x: binman: Include firmware capsules binman nodes
Fill in the am64x SK's capsule GUID properties of the base binman capsule
nodes.
Signed-off-by: Jonathan Humphreys
---
arch/arm/dts/k3-am64x-binman.dtsi | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/k3-am64x-binman.dtsi
b/arch/arm/dts/k3-am64x-binman.dtsi
index 37817ba60d2..f768c4d946d 100644
--- a/arch/arm/dts/k3-am64x-binman.dtsi
+++ b/arch/arm/dts/k3-am64x-binman.dtsi
@@ -114,6 +114,17 @@
};
};
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsule update GUIDs in string form. See am64x_evm.h
+#define AM64X_SK_TIBOOT3_IMAGE_GUID_STR "ede0a0d5-9116-4bfb-aa54-09e97b5afe1a"
+
+_tiboot3 {
+ efi-capsule {
+ image-guid = AM64X_SK_TIBOOT3_IMAGE_GUID_STR;
+ };
+};
+
#endif
#ifdef CONFIG_TARGET_AM642_A53_EVM
@@ -373,4 +384,23 @@
};
};
};
+
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form. See am64x_evm.h
+#define AM64X_SK_SPL_IMAGE_GUID_STR "77678f5c-64d4-4910-ad75-52c9d95cdb1d"
+#define AM64X_SK_UBOOT_IMAGE_GUID_STR "c6ad43a9-7d31-4f5d-83e9-b8efecae05bf"
+
+_tispl {
+ efi-capsule {
+ image-guid = AM64X_SK_SPL_IMAGE_GUID_STR;
+ };
+};
+
+_uboot {
+ efi-capsule {
+ image-guid = AM64X_SK_UBOOT_IMAGE_GUID_STR;
+ };
+};
+
#endif
--
2.34.1
[PATCH v2 5/7] dts: am62px: binman: Include firmware capsules binman nodes
Fill in the am62px SK's capsule GUID properties of the base binman capsule
nodes.
Signed-off-by: Jonathan Humphreys
---
arch/arm/dts/k3-am62p-sk-binman.dtsi | 29
1 file changed, 29 insertions(+)
diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi
b/arch/arm/dts/k3-am62p-sk-binman.dtsi
index dea14945bf5..3ec73022c60 100644
--- a/arch/arm/dts/k3-am62p-sk-binman.dtsi
+++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi
@@ -59,6 +59,17 @@
};
};
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsule update GUIDs in string form. See am62px_evm.h
+#define AM62PX_SK_TIBOOT3_IMAGE_GUID_STR "b08471b7-be2d-4489-87a1-cab28a0cf743"
+
+_tiboot3 {
+ efi-capsule {
+ image-guid = AM62PX_SK_TIBOOT3_IMAGE_GUID_STR;
+ };
+};
+
#endif /* CONFIG_TARGET_AM62P5_R5_EVM */
#if IS_ENABLED(CONFIG_TARGET_AM62P5_A53_EVM)
@@ -170,4 +181,22 @@
};
};
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form. See am62px_evm.h
+#define AM62PX_SK_SPL_IMAGE_GUID_STR "d02ed781-6d71-4c1a-a999-3c6a41c36324"
+#define AM62PX_SK_UBOOT_IMAGE_GUID_STR "7e6aea51-965c-44ab-b388-daeb03b54f66"
+
+_tispl {
+ efi-capsule {
+ image-guid = AM62PX_SK_SPL_IMAGE_GUID_STR;
+ };
+};
+
+_uboot {
+ efi-capsule {
+ image-guid = AM62PX_SK_UBOOT_IMAGE_GUID_STR;
+ };
+};
+
#endif /* CONFIG_TARGET_AM62P5_A53_EVM */
--
2.34.1
[PATCH v2 1/7] dts: ti: binman: Add base K3 firmware capsule nodes
Create capsule files for tiboot3.bin, tispl.bin, and u-boot.img.
Signed-off-by: Jonathan Humphreys
---
arch/arm/dts/k3-binman-capsule-r5.dtsi | 21 ++
arch/arm/dts/k3-binman-capsule.dtsi| 38 ++
2 files changed, 59 insertions(+)
create mode 100644 arch/arm/dts/k3-binman-capsule-r5.dtsi
create mode 100644 arch/arm/dts/k3-binman-capsule.dtsi
diff --git a/arch/arm/dts/k3-binman-capsule-r5.dtsi
b/arch/arm/dts/k3-binman-capsule-r5.dtsi
new file mode 100644
index 000..959ceb7479d
--- /dev/null
+++ b/arch/arm/dts/k3-binman-capsule-r5.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+ {
+ capsule_tiboot3: capsule-tiboot3 {
+ filename = "tiboot3-capsule.bin";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = "----";
+ private-key = "arch/arm/mach-k3/keys/custMpk.pem";
+ public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt";
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = "tiboot3.bin";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-binman-capsule.dtsi
b/arch/arm/dts/k3-binman-capsule.dtsi
new file mode 100644
index 000..17e83c9fa44
--- /dev/null
+++ b/arch/arm/dts/k3-binman-capsule.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+ {
+ capsule_tispl: capsule-tispl {
+ filename = "tispl-capsule.bin";
+ efi-capsule {
+ image-index = <0x2>;
+ image-guid = "----";
+ private-key = "arch/arm/mach-k3/keys/custMpk.pem";
+ public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt";
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = "tispl.bin";
+ };
+ };
+ };
+};
+
+ {
+ capsule_uboot: capsule-uboot {
+ filename = "uboot-capsule.bin";
+ efi-capsule {
+ image-index = <0x3>;
+ image-guid = "----";
+ private-key = "arch/arm/mach-k3/keys/custMpk.pem";
+ public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt";
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = "u-boot.img";
+ };
+ };
+ };
+};
--
2.34.1
[PATCH v2 7/7] dts: beagleboneai64: binman: Include firmware capsules binman nodes
Fill in the BeagleBoneAI64's capsule GUID properties of the base binman capsule
nodes.
Also add it's SYSFW binman capsule node.
Signed-off-by: Jonathan Humphreys
---
.../dts/k3-j721e-beagleboneai64-u-boot.dtsi | 23 +++
arch/arm/dts/k3-j721e-r5-beagleboneai64.dts | 29 +++
2 files changed, 52 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
index e202ae16644..884f44239e1 100644
--- a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
@@ -351,4 +351,27 @@
};
};
};
+
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form. See beagleboneai64.h
+#define BEAGLEBONEAI64_SPL_IMAGE_GUID_STR
"83447222-1e26-40cd-a395-b7de0957e875"
+#define BEAGLEBONEAI64_UBOOT_IMAGE_GUID_STR
"4249ff77-c17d-4eb7-a1db-45aa9887d49e"
+
+_tispl {
+ efi-capsule {
+ image-guid = BEAGLEBONEAI64_SPL_IMAGE_GUID_STR;
+
+ blob {
+ filename = "tispl.bin_unsigned";
+ };
+ };
+};
+
+_uboot {
+ efi-capsule {
+ image-guid = BEAGLEBONEAI64_UBOOT_IMAGE_GUID_STR;
+ };
+};
+
#endif
diff --git a/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts
b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts
index 43da4dafba8..d4ef18248b0 100644
--- a/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts
+++ b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts
@@ -183,3 +183,32 @@
};
};
};
+
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsue update GUIDs. See beagleboneai64.h.
+#define BEAGLEBONEAI64_TIBOOT3_IMAGE_GUID_STR
"772a4810-2194-4923-8754-0115870ef367"
+#define BEAGLEBONEAI64_SYSFW_IMAGE_GUID_STR
"dfc9c683-49b7-46bd-b3c1-3a3b2fdb135b"
+
+_tiboot3 {
+ efi-capsule {
+ image-guid = BEAGLEBONEAI64_TIBOOT3_IMAGE_GUID_STR;
+ };
+};
+
+ {
+ capsule-sysfw {
+ filename = "sysfw-capsule.bin";
+ efi-capsule {
+ image-index = <0x4>;
+ image-guid = BEAGLEBONEAI64_SYSFW_IMAGE_GUID_STR;
+ private-key = "arch/arm/mach-k3/keys/custMpk.pem";
+ public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt";
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = "sysfw.itb";
+ };
+ };
+ };
+};
--
2.34.1
[PATCH v2 3/7] dts: j721e: binman: Include firmware capsules binman nodes
Fill in the J721e SK's capsule GUID properties of the base binman capsule
nodes.
Also add it's SYSFW binman capsule node.
Signed-off-by: Jonathan Humphreys
---
arch/arm/dts/k3-j721e-binman.dtsi | 49 +++
1 file changed, 49 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-binman.dtsi
b/arch/arm/dts/k3-j721e-binman.dtsi
index 75a6e9599b9..32cfd545e5c 100644
--- a/arch/arm/dts/k3-j721e-binman.dtsi
+++ b/arch/arm/dts/k3-j721e-binman.dtsi
@@ -207,6 +207,36 @@
};
};
};
+
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsule update GUIDs in string form. See j721e_evm.h
+#define J721E_SK_TIBOOT3_IMAGE_GUID_STR "e672b518-7cd7-4014-bd8d-40724d0ad4dc"
+#define J721E_SK_SYSFW_IMAGE_GUID_STR "6fd10680-361b-431f-80aa-899455819e11"
+
+_tiboot3 {
+ efi-capsule {
+ image-guid = J721E_SK_TIBOOT3_IMAGE_GUID_STR;
+ };
+};
+
+ {
+ capsule-sysfw {
+ filename = "sysfw-capsule.bin";
+ efi-capsule {
+ image-index = <0x4>;
+ image-guid = J721E_SK_SYSFW_IMAGE_GUID_STR;
+ private-key = "arch/arm/mach-k3/keys/custMpk.pem";
+ public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt";
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = "sysfw.itb";
+ };
+ };
+ };
+};
+
#endif
#ifdef CONFIG_TARGET_J721E_A72_EVM
@@ -585,4 +615,23 @@
};
};
};
+
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form. See j721e_evm.h
+#define J721E_SK_SPL_IMAGE_GUID_STR "86f710ad-10cf-46ea-ac67-856ae06efad2"
+#define J721E_SK_UBOOT_IMAGE_GUID_STR "81b58fb0-3b00-4add-a20a-c185bbaca1ed"
+
+_tispl {
+ efi-capsule {
+ image-guid = J721E_SK_SPL_IMAGE_GUID_STR;
+ };
+};
+
+_uboot {
+ efi-capsule {
+ image-guid = J721E_SK_UBOOT_IMAGE_GUID_STR;
+ };
+};
+
#endif
--
2.34.1
Re: [PATCH v3 04/19] doc: board: ti: am64x: document OSPI layout
On Fri, Apr 19, 2024 at 03:56:46PM -0500, Jonathan Humphreys wrote: > Signed-off-by: Jonathan Humphreys > --- > doc/board/ti/am64x_evm.rst | 48 ++ > 1 file changed, 48 insertions(+) [snip] > +Flash layout for OSPI: > + > +.. code-block:: console > + > + 0x0 ++ > + | ospi.tiboot3(1m) | > + || > +0x10 ++ > + | ospi.tispl(2m) | > + || > +0x30 ++ > + | ospi.u-boot(4m)| > + || > +0x70 ++ > + | ospi.env(128k) | > + || > +0x72 ++ > + | ospi.env.backup(128k)| > + || > +0x74 ++ > + | padding (768k)| > +0x80 ++ > + | ospi.rootfs(ubifs) | > + || > + 0x3fc ++ > + | ospi.phypattern (256k) | > + || > + ++ This should be in an SVG see doc/board/ti/j7200_evm.rst for example (and I'll set aside some non-SVG examples in doc/board/ti that should be converted). Thanks. -- Tom signature.asc Description: PGP signature
[PATCH v3 00/19] EFI: ti: Enable EFI capsule updates
Enable on disk capsule updates, which includes defining the firmware components (tiboot3, spl, u-boot) and enabling processing of raw capsule updates. This is enabled for several TI SoC based platforms: AM64, AM62, AM62p, BeaglePlay, J7, and BeagleboneAI. This series also includes enabling seral flash DFU for AM62 and MMC DFU for beagleplay. Changes from v1: - Added sysfw.itb capsule definition to beagleboneai64 - removed extra commas in structure definitions Changes from v2: - Added documentation on OSPI flash layouts - Improved comments for capsule GUIDs definitions - Defined board unique capsule GUIDs and put definitions in board specific files - Added a Capsule Update porting section to the documentation Jonathan Humphreys (19): doc: uefi: capsules: Start Capsule Update porting section board: am64x: Define capsule update firmware info configs: am64x: Enable EFI capsule update doc: board: ti: am64x: document OSPI layout board: j721e: Define capsule update firmware info configs: j721e: Enable EFI capsule update doc: board: ti: j721e: document OSPI layout board: beagleplay: Define capsule update firmware info configs: beagleplay: Enable DFU for MMC configs: beagleplay: Enable EFI capsule update board: am62px: Define capsule update firmware info configs: am62px: Enable EFI capsule update doc: board: ti: am62px: document OSPI layout configs: am62x: Enable serial flash DFU board: am62x: Define capsule update firmware info configs: am62x: Enable EFI capsule update doc: board: ti: am62x: document OSPI layout board: beagleboneai64: Define capsule update firmware info configs: beagleboneai64: Enable EFI capsule update board/beagle/beagleboneai64/Kconfig | 4 +- board/beagle/beagleboneai64/beagleboneai64.c | 38 + board/beagle/beagleplay/Kconfig | 4 +- board/beagle/beagleplay/beagleplay.c | 33 board/ti/am62px/evm.c| 32 board/ti/am62x/evm.c | 32 board/ti/am64x/evm.c | 33 board/ti/j721e/evm.c | 38 + configs/am62px_evm_a53_defconfig | 2 + configs/am62x_beagleplay_a53_defconfig | 5 ++ configs/am62x_evm_a53_defconfig | 3 + configs/am64x_evm_a53_defconfig | 2 + configs/j721e_beagleboneai64_a72_defconfig | 2 + configs/j721e_evm_a72_defconfig | 2 + doc/board/ti/am62px_sk.rst | 48 +++ doc/board/ti/am62x_sk.rst| 48 +++ doc/board/ti/am64x_evm.rst | 48 +++ doc/board/ti/j721e_evm.rst | 85 +--- doc/develop/uefi/uefi.rst| 12 +++ include/configs/am62px_evm.h | 24 ++ include/configs/am62x_evm.h | 24 ++ include/configs/am64x_evm.h | 24 ++ include/configs/beagleboneai64.h | 55 + include/configs/beagleplay.h | 41 ++ include/configs/j721e_evm.h | 29 +++ 25 files changed, 635 insertions(+), 33 deletions(-) create mode 100644 include/configs/beagleboneai64.h create mode 100644 include/configs/beagleplay.h -- 2.34.1
[PATCH v3 05/19] board: j721e: Define capsule update firmware info
Define the firmware components updatable via EFI capsule update, including
defining capsule GUIDs for the various firmware components for the SK-TDA4VM.
Signed-off-by: Jonathan Humphreys
---
board/ti/j721e/evm.c| 38 +
include/configs/j721e_evm.h | 29
2 files changed, 67 insertions(+)
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 9dc3ed6dfff..de70027b2df 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -7,6 +7,7 @@
*
*/
+#include
#include
#include
#include
@@ -32,6 +33,43 @@
DECLARE_GLOBAL_DATA_PTR;
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
+struct efi_fw_image fw_images[] = {
+ {
+ .image_type_id = J721E_SK_TIBOOT3_IMAGE_GUID,
+ .fw_name = u"J721E_SK_TIBOOT3",
+ .image_index = 1,
+ },
+ {
+ .image_type_id = J721E_SK_SPL_IMAGE_GUID,
+ .fw_name = u"J721E_SK_SPL",
+ .image_index = 2,
+ },
+ {
+ .image_type_id = J721E_SK_UBOOT_IMAGE_GUID,
+ .fw_name = u"J721E_SK_UBOOT",
+ .image_index = 3,
+ },
+ {
+ .image_type_id = J721E_SK_SYSFW_IMAGE_GUID,
+ .fw_name = u"J721E_SK_SYSFW",
+ .image_index = 4,
+ }
+};
+
+struct efi_capsule_update_info update_info = {
+ .dfu_string = "sf 0:0=tiboot3.bin raw 0 8;tispl.bin raw 8
20;u-boot.img raw 28 40;sysfw.itb raw 6C 10",
+ .num_images = ARRAY_SIZE(fw_images),
+ .images = fw_images,
+};
+
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+ env_set("dfu_alt_info", update_info.dfu_string);
+}
+
+#endif /* EFI_HAVE_CAPSULE_SUPPORT */
+
int board_init(void)
{
return 0;
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index c26438c8684..a5140ea6a11 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -22,6 +22,35 @@
#define CFG_SYS_UBOOT_BASE 0x5008
#endif
+/**
+ * define J721E_SK_TIBOOT3_IMAGE_GUID - firmware GUID for J721e sk tiboot3.bin
+ * define J721E_SK_SPL_IMAGE_GUID - firmware GUID for J721e sk SPL
+ * define J721E_SK_UBOOT_IMAGE_GUID - firmware GUID for J721e sk UBOOT
+ * define J721E_SK_SYSFW_IMAGE_GUID - firmware GUID for J721e sk SYSFW
+ *
+ * These GUIDs are used in capsules updates to identify the corresponding
+ * firmware object.
+ *
+ * Board developers using this as a starting reference should
+ * define their own GUIDs to ensure that firmware repositories (like
+ * LVFS) do not confuse them.
+ */
+#define J721E_SK_TIBOOT3_IMAGE_GUID \
+ EFI_GUID(0xe672b518, 0x7cd7, 0x4014, 0xbd, 0x8d, \
+0x40, 0x72, 0x4d, 0x0a, 0xd4, 0xdc)
+
+#define J721E_SK_SPL_IMAGE_GUID \
+ EFI_GUID(0x86f710ad, 0x10cf, 0x46ea, 0xac, 0x67, \
+0x85, 0x6a, 0xe0, 0x6e, 0xfa, 0xd2)
+
+#define J721E_SK_UBOOT_IMAGE_GUID \
+ EFI_GUID(0x81b58fb0, 0x3b00, 0x4add, 0xa2, 0x0a, \
+0xc1, 0x85, 0xbb, 0xac, 0xa1, 0xed)
+
+#define J721E_SK_SYSFW_IMAGE_GUID \
+ EFI_GUID(0x6fd10680, 0x361b, 0x431f, 0x80, 0xaa, \
+0x89, 0x94, 0x55, 0x81, 0x9e, 0x11)
+
/* Now for the remaining common defines */
#include
--
2.34.1
[PATCH v3 19/19] configs: beagleboneai64: Enable EFI capsule update
Signed-off-by: Jonathan Humphreys --- configs/j721e_beagleboneai64_a72_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/j721e_beagleboneai64_a72_defconfig b/configs/j721e_beagleboneai64_a72_defconfig index 3d234bc1a8f..e74ee68e23e 100644 --- a/configs/j721e_beagleboneai64_a72_defconfig +++ b/configs/j721e_beagleboneai64_a72_defconfig @@ -172,3 +172,5 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x6163 CONFIG_SPL_DFU=y CONFIG_LZO=y CONFIG_EFI_SET_TIME=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y -- 2.34.1
[PATCH v3 04/19] doc: board: ti: am64x: document OSPI layout
Signed-off-by: Jonathan Humphreys
---
doc/board/ti/am64x_evm.rst | 48 ++
1 file changed, 48 insertions(+)
diff --git a/doc/board/ti/am64x_evm.rst b/doc/board/ti/am64x_evm.rst
index 6ae35b3fee3..a7468fbd254 100644
--- a/doc/board/ti/am64x_evm.rst
+++ b/doc/board/ti/am64x_evm.rst
@@ -140,6 +140,54 @@ Image formats:
.. image:: img/nodm_tispl.bin.svg
:alt: tispl.bin image format
+OSPI:
+-
+ROM supports booting from OSPI from offset 0x0.
+
+Flashing images to OSPI:
+
+Below commands can be used to download tiboot3.bin, tispl.bin, and u-boot.img,
+over tftp and then flash those to OSPI at their respective addresses.
+
+.. prompt:: bash =>
+
+ sf probe
+ tftp ${loadaddr} tiboot3.bin
+ sf update $loadaddr 0x0 $filesize
+ tftp ${loadaddr} tispl.bin
+ sf update $loadaddr 0x10 $filesize
+ tftp ${loadaddr} u-boot.img
+ sf update $loadaddr 0x30 $filesize
+
+Flash layout for OSPI:
+
+.. code-block:: console
+
+ 0x0 ++
+ | ospi.tiboot3(1m) |
+ ||
+0x10 ++
+ | ospi.tispl(2m) |
+ ||
+0x30 ++
+ | ospi.u-boot(4m)|
+ ||
+0x70 ++
+ | ospi.env(128k) |
+ ||
+0x72 ++
+ | ospi.env.backup(128k)|
+ ||
+0x74 ++
+ | padding (768k)|
+0x80 ++
+ | ospi.rootfs(ubifs) |
+ ||
+ 0x3fc ++
+ | ospi.phypattern (256k) |
+ ||
+ ++
+
Switch Setting for Boot Mode
--
2.34.1
[PATCH v3 03/19] configs: am64x: Enable EFI capsule update
Signed-off-by: Jonathan Humphreys --- configs/am64x_evm_a53_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index e000549d6d0..c9bdd7b54cc 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -178,3 +178,5 @@ CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_SPL_DFU=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_EFI_SET_TIME=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y -- 2.34.1
[PATCH v3 14/19] configs: am62x: Enable serial flash DFU
Signed-off-by: Jonathan Humphreys --- configs/am62x_evm_a53_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index 6b37f8b4791..cc397f72d2c 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -68,6 +68,7 @@ CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y +CONFIG_DFU_SF=y CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y -- 2.34.1
[PATCH v3 11/19] board: am62px: Define capsule update firmware info
Define the firmware components updatable via EFI capsule update, including
defining capsule GUIDs for the various firmware components for the AM62px SK.
Signed-off-by: Jonathan Humphreys
---
board/ti/am62px/evm.c| 32
include/configs/am62px_evm.h | 24
2 files changed, 56 insertions(+)
diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c
index 97a95ce8cc2..4caf3d5b3ba 100644
--- a/board/ti/am62px/evm.c
+++ b/board/ti/am62px/evm.c
@@ -6,6 +6,7 @@
*
*/
+#include
#include
#include
#include
@@ -13,6 +14,37 @@
#include
#include
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
+struct efi_fw_image fw_images[] = {
+ {
+ .image_type_id = AM62PX_SK_TIBOOT3_IMAGE_GUID,
+ .fw_name = u"AM62PX_SK_TIBOOT3",
+ .image_index = 1,
+ },
+ {
+ .image_type_id = AM62PX_SK_SPL_IMAGE_GUID,
+ .fw_name = u"AM62PX_SK_SPL",
+ .image_index = 2,
+ },
+ {
+ .image_type_id = AM62PX_SK_UBOOT_IMAGE_GUID,
+ .fw_name = u"AM62PX_SK_UBOOT",
+ .image_index = 3,
+ }
+};
+
+struct efi_capsule_update_info update_info = {
+ .dfu_string = "sf 0:0=tiboot3.bin raw 0 8;tispl.bin raw 8
20;u-boot.img raw 28 40",
+ .num_images = ARRAY_SIZE(fw_images),
+ .images = fw_images,
+};
+
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+ env_set("dfu_alt_info", update_info.dfu_string);
+}
+#endif /* EFI_HAVE_CAPSULE_SUPPORT */
+
int board_init(void)
{
return 0;
diff --git a/include/configs/am62px_evm.h b/include/configs/am62px_evm.h
index 06b12860e21..57a1ba9dc3c 100644
--- a/include/configs/am62px_evm.h
+++ b/include/configs/am62px_evm.h
@@ -8,6 +8,30 @@
#ifndef __CONFIG_AM62PX_EVM_H
#define __CONFIG_AM62PX_EVM_H
+/**
+ * define AM62PX_SK_TIBOOT3_IMAGE_GUID - firmware GUID for AM62PX sk
tiboot3.bin
+ * define AM62PX_SK_SPL_IMAGE_GUID - firmware GUID for AM62PX sk SPL
+ * define AM62PX_SK_UBOOT_IMAGE_GUID - firmware GUID for AM62PX sk UBOOT
+ *
+ * These GUIDs are used in capsules updates to identify the corresponding
+ * firmware object.
+ *
+ * Board developers using this as a starting reference should
+ * define their own GUIDs to ensure that firmware repositories (like
+ * LVFS) do not confuse them.
+ */
+#define AM62PX_SK_TIBOOT3_IMAGE_GUID \
+ EFI_GUID(0xb08471b7, 0xbe2d, 0x4489, 0x87, 0xa1, \
+ 0xca, 0xb2, 0x8a, 0x0c, 0xf7, 0x43)
+
+#define AM62PX_SK_SPL_IMAGE_GUID \
+ EFI_GUID(0xd02ed781, 0x6d71, 0x4c1a, 0xa9, 0x99, \
+ 0x3c, 0x6a, 0x41, 0xc3, 0x63, 0x24)
+
+#define AM62PX_SK_UBOOT_IMAGE_GUID \
+ EFI_GUID(0x7e6aea51, 0x965c, 0x44ab, 0xb3, 0x88, \
+ 0xda, 0xeb, 0x03, 0xb5, 0x4f, 0x66)
+
/* Now for the remaining common defines */
#include
--
2.34.1
[PATCH v3 07/19] doc: board: ti: j721e: document OSPI layout
Signed-off-by: Jonathan Humphreys
---
doc/board/ti/j721e_evm.rst | 85 +-
1 file changed, 56 insertions(+), 29 deletions(-)
diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst
index a422a9bf1a0..a0fc37ab6d7 100644
--- a/doc/board/ti/j721e_evm.rst
+++ b/doc/board/ti/j721e_evm.rst
@@ -150,6 +150,60 @@ Image formats:
.. image:: img/sysfw.itb.svg
:alt: sysfw.itb image format
+OSPI:
+-
+ROM supports booting from OSPI from offset 0x0.
+
+Flashing images to OSPI:
+
+Below commands can be used to download tiboot3.bin, tispl.bin, u-boot.img,
+and sysfw.itb over tftp and then flash those to OSPI at their respective
+addresses.
+
+.. prompt:: bash =>
+
+ sf probe
+ tftp ${loadaddr} tiboot3.bin
+ sf update $loadaddr 0x0 $filesize
+ tftp ${loadaddr} tispl.bin
+ sf update $loadaddr 0x8 $filesize
+ tftp ${loadaddr} u-boot.img
+ sf update $loadaddr 0x28 $filesize
+ tftp ${loadaddr} sysfw.itb
+ sf update $loadaddr 0x6C $filesize
+
+Flash layout for OSPI:
+
+.. code-block:: console
+
+ 0x0 ++
+ | ospi.tiboot3(512K) |
+ ||
+ 0x8 ++
+ | ospi.tispl(2M) |
+ ||
+0x28 ++
+ | ospi.u-boot(4M)|
+ ||
+0x68 ++
+ | ospi.env(128K) |
+ ||
+0x6A ++
+ | ospi.env.backup (128K) |
+ ||
+0x6C ++
+ | ospi.sysfw(1M)|
+ ||
+0x7C ++
+ | padding (256k)|
+0x80 ++
+ | ospi.rootfs(UBIFS) |
+ ||
+ 0x3FE ++
+ | ospi.phypattern (128k) |
+ ||
+ ++
+
R5 Memory Map:
--
@@ -193,35 +247,8 @@ R5 Memory Map:
- 0x41cffbfc
- 0x41cf
-OSPI:
--
-ROM supports booting from OSPI from offset 0x0.
-
-Flashing images to OSPI:
-
-Below commands can be used to download tiboot3.bin, tispl.bin, u-boot.img,
-and sysfw.itb over tftp and then flash those to OSPI at their respective
-addresses.
-
-.. prompt:: bash =>
-
- sf probe
- tftp ${loadaddr} tiboot3.bin
- sf update $loadaddr 0x0 $filesize
- tftp ${loadaddr} tispl.bin
- sf update $loadaddr 0x8 $filesize
- tftp ${loadaddr} u-boot.img
- sf update $loadaddr 0x28 $filesize
- tftp ${loadaddr} sysfw.itb
- sf update $loadaddr 0x6C $filesize
-
-Flash layout for OSPI:
-
-.. image:: img/ospi_sysfw.svg
- :alt: OSPI flash partition layout
-
-Firmwares:
---
+Firmware:
+-
The J721e u-boot allows firmware to be loaded for the Cortex-R5 subsystem.
The CPSW5G in J7200 and CPSW9G in J721E present in MAIN domain is configured
--
2.34.1
[PATCH v3 02/19] board: am64x: Define capsule update firmware info
Define the firmware components updatable via EFI capsule update, including
defining capsule GUIDs for the various firmware components for the AM64x SK.
Signed-off-by: Jonathan Humphreys
---
board/ti/am64x/evm.c| 33 +
include/configs/am64x_evm.h | 24
2 files changed, 57 insertions(+)
diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c
index b8de69da06c..83df75a6911 100644
--- a/board/ti/am64x/evm.c
+++ b/board/ti/am64x/evm.c
@@ -7,6 +7,7 @@
*
*/
+#include
#include
#include
#include
@@ -27,6 +28,38 @@
DECLARE_GLOBAL_DATA_PTR;
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
+struct efi_fw_image fw_images[] = {
+ {
+ .image_type_id = AM64X_SK_TIBOOT3_IMAGE_GUID,
+ .fw_name = u"AM64X_SK_TIBOOT3",
+ .image_index = 1,
+ },
+ {
+ .image_type_id = AM64X_SK_SPL_IMAGE_GUID,
+ .fw_name = u"AM64X_SK_SPL",
+ .image_index = 2,
+ },
+ {
+ .image_type_id = AM64X_SK_UBOOT_IMAGE_GUID,
+ .fw_name = u"AM64X_SK_UBOOT",
+ .image_index = 3,
+ }
+};
+
+struct efi_capsule_update_info update_info = {
+ .dfu_string = "sf 0:0=tiboot3.bin raw 0 10;tispl.bin raw 10
20;u-boot.img raw 30 40",
+ .num_images = ARRAY_SIZE(fw_images),
+ .images = fw_images,
+};
+
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+ env_set("dfu_alt_info", update_info.dfu_string);
+}
+
+#endif /* EFI_HAVE_CAPSULE_SUPPORT */
+
int board_init(void)
{
return 0;
diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h
index f9f8c7bc2f6..9db83621ea8 100644
--- a/include/configs/am64x_evm.h
+++ b/include/configs/am64x_evm.h
@@ -9,6 +9,30 @@
#ifndef __CONFIG_AM642_EVM_H
#define __CONFIG_AM642_EVM_H
+/**
+ * define AM64X_SK_TIBOOT3_IMAGE_GUID - firmware GUID for AM64X sk tiboot3.bin
+ * define AM64X_SK_SPL_IMAGE_GUID - firmware GUID for AM64X sk SPL
+ * define AM64X_SK_UBOOT_IMAGE_GUID - firmware GUID for AM64X sk UBOOT
+ *
+ * These GUIDs are used in capsules updates to identify the corresponding
+ * firmware object.
+ *
+ * Board developers using this as a starting reference should
+ * define their own GUIDs to ensure that firmware repositories (like
+ * LVFS) do not confuse them.
+ */
+#define AM64X_SK_TIBOOT3_IMAGE_GUID \
+ EFI_GUID(0xede0a0d5, 0x9116, 0x4bfb, 0xaa, 0x54, \
+ 0x09, 0xe9, 0x7b, 0x5a, 0xfe, 0x1a)
+
+#define AM64X_SK_SPL_IMAGE_GUID \
+ EFI_GUID(0x77678f5c, 0x64d4, 0x4910, 0xad, 0x75, \
+ 0x52, 0xc9, 0xd9, 0x5c, 0xdb, 0x1d)
+
+#define AM64X_SK_UBOOT_IMAGE_GUID \
+ EFI_GUID(0xc6ad43a9, 0x7d31, 0x4f5d, 0x83, 0xe9, \
+ 0xb8, 0xef, 0xec, 0xae, 0x05, 0xbf)
+
/* Now for the remaining common defines */
#include
--
2.34.1
[PATCH v3 17/19] doc: board: ti: am62x: document OSPI layout
Signed-off-by: Jonathan Humphreys
---
doc/board/ti/am62x_sk.rst | 48 +++
1 file changed, 48 insertions(+)
diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst
index b12dc85f06b..bf7ea754e32 100644
--- a/doc/board/ti/am62x_sk.rst
+++ b/doc/board/ti/am62x_sk.rst
@@ -150,6 +150,54 @@ Image formats:
.. image:: img/dm_tispl.bin.svg
:alt: tispl.bin image format
+OSPI:
+-
+ROM supports booting from OSPI from offset 0x0.
+
+Flashing images to OSPI:
+
+Below commands can be used to download tiboot3.bin, tispl.bin, and u-boot.img,
+over tftp and then flash those to OSPI at their respective addresses.
+
+.. prompt:: bash =>
+
+ sf probe
+ tftp ${loadaddr} tiboot3.bin
+ sf update $loadaddr 0x0 $filesize
+ tftp ${loadaddr} tispl.bin
+ sf update $loadaddr 0x8 $filesize
+ tftp ${loadaddr} u-boot.img
+ sf update $loadaddr 0x28 $filesize
+
+Flash layout for OSPI:
+
+.. code-block:: console
+
+ 0x0 ++
+ | ospi.tiboot3(512k) |
+ ||
+ 0x8 ++
+ | ospi.tispl(2m) |
+ ||
+0x28 ++
+ | ospi.u-boot(4m)|
+ ||
+0x68 ++
+ | ospi.env(128k) |
+ ||
+0x6c ++
+ | ospi.env.backup(128k)|
+ ||
+0x74 ++
+ | padding (768k)|
+0x80 ++
+ | ospi.rootfs(ubifs) |
+ ||
+ 0x3fc ++
+ | ospi.phypattern (256k) |
+ ||
+ ++
+
A53 SPL DDR Memory Layout
-
--
2.34.1
[PATCH v3 10/19] configs: beagleplay: Enable EFI capsule update
Signed-off-by: Jonathan Humphreys --- configs/am62x_beagleplay_a53_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig index 68e103f58dc..23b9c466248 100644 --- a/configs/am62x_beagleplay_a53_defconfig +++ b/configs/am62x_beagleplay_a53_defconfig @@ -124,3 +124,5 @@ CONFIG_EXT4_WRITE=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_LZO=y CONFIG_EFI_SET_TIME=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y -- 2.34.1
[PATCH v3 18/19] board: beagleboneai64: Define capsule update firmware info
Define the firmware components updatable via EFI capsule update, including
defining capsule GUIDs for the various firmware components for the
BeagleBoneAI64.
Note this involved creating BeagleBoneAI64's own beagleboneai64.h board header
file instead of reusing j721e_evm's.
Signed-off-by: Jonathan Humphreys
---
board/beagle/beagleboneai64/Kconfig | 4 +-
board/beagle/beagleboneai64/beagleboneai64.c | 38 ++
include/configs/beagleboneai64.h | 55
3 files changed, 95 insertions(+), 2 deletions(-)
create mode 100644 include/configs/beagleboneai64.h
diff --git a/board/beagle/beagleboneai64/Kconfig
b/board/beagle/beagleboneai64/Kconfig
index 7cfccf9baf0..0f21582614d 100644
--- a/board/beagle/beagleboneai64/Kconfig
+++ b/board/beagle/beagleboneai64/Kconfig
@@ -37,7 +37,7 @@ config SYS_VENDOR
default "beagle"
config SYS_CONFIG_NAME
- default "j721e_evm"
+ default "beagleboneai64"
source "board/ti/common/Kconfig"
@@ -52,7 +52,7 @@ config SYS_VENDOR
default "beagle"
config SYS_CONFIG_NAME
- default "j721e_evm"
+ default "beagleboneai64"
source "board/ti/common/Kconfig"
diff --git a/board/beagle/beagleboneai64/beagleboneai64.c
b/board/beagle/beagleboneai64/beagleboneai64.c
index c5b4ff7df47..05dec405b81 100644
--- a/board/beagle/beagleboneai64/beagleboneai64.c
+++ b/board/beagle/beagleboneai64/beagleboneai64.c
@@ -7,6 +7,7 @@
* Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
*/
+#include
#include
#include
#include
@@ -14,6 +15,43 @@
DECLARE_GLOBAL_DATA_PTR;
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
+struct efi_fw_image fw_images[] = {
+ {
+ .image_type_id = BEAGLEBONEAI64_TIBOOT3_IMAGE_GUID,
+ .fw_name = u"BEAGLEBONEAI64_TIBOOT3",
+ .image_index = 1,
+ },
+ {
+ .image_type_id = BEAGLEBONEAI64_SPL_IMAGE_GUID,
+ .fw_name = u"BEAGLEBONEAI64_SPL",
+ .image_index = 2,
+ },
+ {
+ .image_type_id = BEAGLEBONEAI64_UBOOT_IMAGE_GUID,
+ .fw_name = u"BEAGLEBONEAI64_UBOOT",
+ .image_index = 3,
+ },
+ {
+ .image_type_id = BEAGLEBONEAI64_SYSFW_IMAGE_GUID,
+ .fw_name = u"BEAGLEBONEAI64_SYSFW",
+ .image_index = 4,
+ }
+};
+
+struct efi_capsule_update_info update_info = {
+ .dfu_string = "mmc 0=tiboot3.bin raw 0 2000 mmcpart 1;tispl.bin fat 0
1;u-boot.img fat 0 1; sysfw.itb fat 0 1",
+ .num_images = ARRAY_SIZE(fw_images),
+ .images = fw_images,
+};
+
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+ env_set("dfu_alt_info", update_info.dfu_string);
+}
+
+#endif /* EFI_HAVE_CAPSULE_SUPPORT */
+
int board_init(void)
{
return 0;
diff --git a/include/configs/beagleboneai64.h b/include/configs/beagleboneai64.h
new file mode 100644
index 000..0fcf403c1c4
--- /dev/null
+++ b/include/configs/beagleboneai64.h
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Configuration header file for BeagleBoneAI64
+ *
+ * https://beagleboard.org/ai-64
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef __CONFIG_BEAGLEBONEAI64_H
+#define __CONFIG_BEAGLEBONEAI64_H
+
+/* FLASH Configuration */
+#define CFG_SYS_FLASH_BASE 0x0
+
+/* SPL Loader Configuration */
+#define CFG_SYS_UBOOT_BASE 0x5008
+
+/**
+ * define BEAGLEBONEAI64_TIBOOT3_IMAGE_GUID - firmware GUID for BeagleBoneAI64
+ *tiboot3.bin
+ * define BEAGLEBONEAI64_SPL_IMAGE_GUID - firmware GUID for BeagleBoneAI64
+ *SPL
+ * define BEAGLEBONEAI64_UBOOT_IMAGE_GUID - firmware GUID for BeagleBoneAI64
+ *UBOOT
+ * define BEAGLEBONEAI64_SYSFW_IMAGE_GUID - firmware GUID for BeagleBoneAI64
+ *SYSFW
+ *
+ * These GUIDs are used in capsules updates to identify the corresponding
+ * firmware object.
+ *
+ * Board developers using this as a starting reference should
+ * define their own GUIDs to ensure that firmware repositories (like
+ * LVFS) do not confuse them.
+ */
+#define BEAGLEBONEAI64_TIBOOT3_IMAGE_GUID \
+ EFI_GUID(0x772a4810, 0x2194, 0x4923, 0x87, 0x54, \
+ 0x01, 0x15, 0x87, 0x0e, 0xf3, 0x67)
+
+#define BEAGLEBONEAI64_SPL_IMAGE_GUID \
+ EFI_GUID(0x83447222, 0x1e26, 0x40cd, 0xa3, 0x95, \
+ 0xb7, 0xde, 0x09, 0x57, 0xe8, 0x75)
+
+#define BEAGLEBONEAI64_UBOOT_IMAGE_GUID \
+ EFI_GUID(0x4249ff77, 0xc17d, 0x4eb7, 0xa1, 0xdb, \
+ 0x45, 0xaa, 0x98, 0x87, 0xd4, 0x9e)
+
+#define BEAGLEBONEAI64_SYSFW_IMAGE_GUID \
+ EFI_GUID(0xdfc9c683, 0x49b7, 0x46bd, 0xb3, 0xc1, \
+ 0x3a, 0x3b, 0x2f, 0xdb, 0x13, 0x5b)
+
+/* Now for the remaining common defines */
[PATCH v3 01/19] doc: uefi: capsules: Start Capsule Update porting section
Created a capsule update porting section in the documentation that outlines the steps a board developer must do when porting from an existing reference board implementation. In particular, added a big warning that new capsule GUID's need to be defined. Signed-off-by: Jonathan Humphreys --- doc/develop/uefi/uefi.rst | 12 1 file changed, 12 insertions(+) diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst index 0389b269c01..36ac75278fa 100644 --- a/doc/develop/uefi/uefi.rst +++ b/doc/develop/uefi/uefi.rst @@ -631,6 +631,18 @@ where version.dtso looks like:: The properties of image-type-id and image-index must match the value defined in the efi_fw_image array as image_type_id and image_index. +Porting Capsule Updates to new boards +* + +It is important, when using a reference board as a starting point for a custom +board, that certain steps are taken to properly support Capsule Updates. + +Capsule GUIDs need to be unique for each firmware and board. That is, if two +firmwares are built from the same source but result in different binaries +because they are built for different boards, they should have different GUIDs. +Therefore it is important when creating support for a new board, new GUIDs are +defined in the board's header file. *DO NOT* reuse capsule GUIDs. + Executing the boot manager ~~ -- 2.34.1
[PATCH v3 16/19] configs: am62x: Enable EFI capsule update
Signed-off-by: Jonathan Humphreys --- configs/am62x_evm_a53_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index cc397f72d2c..d628535a4ed 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -112,3 +112,5 @@ CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_EFI_SET_TIME=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y -- 2.34.1
[PATCH v3 12/19] configs: am62px: Enable EFI capsule update
Signed-off-by: Jonathan Humphreys --- configs/am62px_evm_a53_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/am62px_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig index 638d2e90a6b..02500e205d1 100644 --- a/configs/am62px_evm_a53_defconfig +++ b/configs/am62px_evm_a53_defconfig @@ -177,3 +177,5 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 CONFIG_SPL_DFU=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_EFI_SET_TIME=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y -- 2.34.1
[PATCH v3 08/19] board: beagleplay: Define capsule update firmware info
Define the firmware components updatable via EFI capsule update, including
defining capsule GUIDs for the various firmware components for the BeaglePlay.
Note this involved creating BeaglePlay's own beagleplay.h board header file
instead of reusing am62_evm's.
Signed-off-by: Jonathan Humphreys
---
board/beagle/beagleplay/Kconfig | 4 +--
board/beagle/beagleplay/beagleplay.c | 33 ++
include/configs/beagleplay.h | 41
3 files changed, 76 insertions(+), 2 deletions(-)
create mode 100644 include/configs/beagleplay.h
diff --git a/board/beagle/beagleplay/Kconfig b/board/beagle/beagleplay/Kconfig
index 7dbd833acb4..b0e67dc8ef3 100644
--- a/board/beagle/beagleplay/Kconfig
+++ b/board/beagle/beagleplay/Kconfig
@@ -35,7 +35,7 @@ config SYS_VENDOR
default "beagle"
config SYS_CONFIG_NAME
- default "am62x_evm"
+ default "beagleplay"
source "board/ti/common/Kconfig"
@@ -50,7 +50,7 @@ config SYS_VENDOR
default "beagle"
config SYS_CONFIG_NAME
- default "am62x_evm"
+ default "beagleplay"
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
diff --git a/board/beagle/beagleplay/beagleplay.c
b/board/beagle/beagleplay/beagleplay.c
index af36439e2e2..fe873e9f2b8 100644
--- a/board/beagle/beagleplay/beagleplay.c
+++ b/board/beagle/beagleplay/beagleplay.c
@@ -6,6 +6,7 @@
* Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
*/
+#include
#include
#include
#include
@@ -15,6 +16,38 @@
DECLARE_GLOBAL_DATA_PTR;
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
+struct efi_fw_image fw_images[] = {
+ {
+ .image_type_id = BEAGLEPLAY_TIBOOT3_IMAGE_GUID,
+ .fw_name = u"BEAGLEPLAY_TIBOOT3",
+ .image_index = 1,
+ },
+ {
+ .image_type_id = BEAGLEPLAY_SPL_IMAGE_GUID,
+ .fw_name = u"BEAGLEPLAY_SPL",
+ .image_index = 2,
+ },
+ {
+ .image_type_id = BEAGLEPLAY_UBOOT_IMAGE_GUID,
+ .fw_name = u"BEAGLEPLAY_UBOOT",
+ .image_index = 3,
+ }
+};
+
+struct efi_capsule_update_info update_info = {
+ .dfu_string = "mmc 0=tiboot3.bin raw 0 2000 mmcpart 1;tispl.bin fat 0
1;u-boot.img fat 0 1",
+ .num_images = ARRAY_SIZE(fw_images),
+ .images = fw_images,
+};
+
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+ env_set("dfu_alt_info", update_info.dfu_string);
+}
+
+#endif /* EFI_HAVE_CAPSULE_SUPPORT */
+
int board_init(void)
{
return 0;
diff --git a/include/configs/beagleplay.h b/include/configs/beagleplay.h
new file mode 100644
index 000..a1e196f10f5
--- /dev/null
+++ b/include/configs/beagleplay.h
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Configuration header file for BeaglePlay
+ *
+ * https://beagleplay.org/
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef __CONFIG_BEAGLEPLAY_H
+#define __CONFIG_BEAGLEPLAY_H
+
+/**
+ * define BEAGLEPLAY_TIBOOT3_IMAGE_GUID - firmware GUID for BeaglePlay
+ *tiboot3.bin
+ * define BEAGLEPLAY_SPL_IMAGE_GUID - firmware GUID for BeaglePlay SPL
+ * define BEAGLEPLAY_UBOOT_IMAGE_GUID - firmware GUID for BeaglePlay UBOOT
+ *
+ * These GUIDs are used in capsules updates to identify the corresponding
+ * firmware object.
+ *
+ * Board developers using this as a starting reference should
+ * define their own GUIDs to ensure that firmware repositories (like
+ * LVFS) do not confuse them.
+ */
+#define BEAGLEPLAY_TIBOOT3_IMAGE_GUID \
+ EFI_GUID(0x0e225a09, 0xf720, 0x4d57, 0x91, 0x20, \
+ 0xe2, 0x8f, 0x73, 0x7f, 0x5a, 0x5e)
+
+#define BEAGLEPLAY_SPL_IMAGE_GUID \
+ EFI_GUID(0xb2e7cc49, 0x1a5a, 0x4036, 0xae, 0x01, \
+ 0x33, 0x87, 0xc3, 0xbe, 0xf6, 0x57)
+
+#define BEAGLEPLAY_UBOOT_IMAGE_GUID \
+ EFI_GUID(0x92c92b11, 0xa7ee, 0x486f, 0xaa, 0xa2, \
+ 0x71, 0x3d, 0x84, 0x42, 0x5b, 0x0e)
+
+/* Now for the remaining common defines */
+#include
+
+#endif /* __CONFIG_BEAGLEPLAY_H */
--
2.34.1
[PATCH v3 13/19] doc: board: ti: am62px: document OSPI layout
Signed-off-by: Jonathan Humphreys
---
doc/board/ti/am62px_sk.rst | 48 ++
1 file changed, 48 insertions(+)
diff --git a/doc/board/ti/am62px_sk.rst b/doc/board/ti/am62px_sk.rst
index 1f2982c36f9..7ff20fbf8e6 100644
--- a/doc/board/ti/am62px_sk.rst
+++ b/doc/board/ti/am62px_sk.rst
@@ -156,6 +156,54 @@ Image formats:
.. image:: img/dm_tispl.bin.svg
:alt: tispl.bin image format
+OSPI:
+-
+ROM supports booting from OSPI from offset 0x0.
+
+Flashing images to OSPI:
+
+Below commands can be used to download tiboot3.bin, tispl.bin, and u-boot.img,
+over tftp and then flash those to OSPI at their respective addresses.
+
+.. prompt:: bash =>
+
+ sf probe
+ tftp ${loadaddr} tiboot3.bin
+ sf update $loadaddr 0x0 $filesize
+ tftp ${loadaddr} tispl.bin
+ sf update $loadaddr 0x8 $filesize
+ tftp ${loadaddr} u-boot.img
+ sf update $loadaddr 0x28 $filesize
+
+Flash layout for OSPI:
+
+.. code-block:: console
+
+ 0x0 ++
+ | ospi.tiboot3(512k) |
+ ||
+ 0x8 ++
+ | ospi.tispl(2m) |
+ ||
+0x28 ++
+ | ospi.u-boot(4m)|
+ ||
+0x68 ++
+ | ospi.env(128k) |
+ ||
+0x6c ++
+ | ospi.env.backup(128k)|
+ ||
+0x74 ++
+ | padding (768k)|
+0x80 ++
+ | ospi.rootfs(ubifs) |
+ ||
+ 0x3fc ++
+ | ospi.phypattern (256k) |
+ ||
+ ++
+
A53 SPL DDR Memory Layout
-
--
2.34.1
[PATCH v3 09/19] configs: beagleplay: Enable DFU for MMC
Signed-off-by: Jonathan Humphreys --- configs/am62x_beagleplay_a53_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig index 147967d3c11..68e103f58dc 100644 --- a/configs/am62x_beagleplay_a53_defconfig +++ b/configs/am62x_beagleplay_a53_defconfig @@ -70,6 +70,9 @@ CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y +CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x4 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x18 CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y -- 2.34.1
[PATCH v3 06/19] configs: j721e: Enable EFI capsule update
Signed-off-by: Jonathan Humphreys --- configs/j721e_evm_a72_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 077bf508328..b8840a556e1 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -210,3 +210,5 @@ CONFIG_UFS=y CONFIG_CADENCE_UFS=y CONFIG_TI_J721E_UFS=y CONFIG_EFI_SET_TIME=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y -- 2.34.1
[PATCH v3 15/19] board: am62x: Define capsule update firmware info
Define the firmware components updatable via EFI capsule update, including
defining capsule GUIDs for the various firmware components for the AM62x SK.
Signed-off-by: Jonathan Humphreys
---
board/ti/am62x/evm.c| 32
include/configs/am62x_evm.h | 24
2 files changed, 56 insertions(+)
diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c
index b3e8680dfab..cfcfe6add77 100644
--- a/board/ti/am62x/evm.c
+++ b/board/ti/am62x/evm.c
@@ -7,6 +7,7 @@
*
*/
+#include
#include
#include
#include
@@ -46,6 +47,37 @@ int splash_screen_prepare(void)
}
#endif
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
+struct efi_fw_image fw_images[] = {
+ {
+ .image_type_id = AM62X_SK_TIBOOT3_IMAGE_GUID,
+ .fw_name = u"AM62X_SK_TIBOOT3",
+ .image_index = 1,
+ },
+ {
+ .image_type_id = AM62X_SK_SPL_IMAGE_GUID,
+ .fw_name = u"AM62X_SK_SPL",
+ .image_index = 2,
+ },
+ {
+ .image_type_id = AM62X_SK_UBOOT_IMAGE_GUID,
+ .fw_name = u"AM62X_SK_UBOOT",
+ .image_index = 3,
+ }
+};
+
+struct efi_capsule_update_info update_info = {
+ .dfu_string = "sf 0:0=tiboot3.bin raw 0 8;tispl.bin raw 8
20;u-boot.img raw 28 40",
+ .num_images = ARRAY_SIZE(fw_images),
+ .images = fw_images,
+};
+
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+ env_set("dfu_alt_info", update_info.dfu_string);
+}
+#endif /* EFI_HAVE_CAPSULE_SUPPORT */
+
int board_init(void)
{
return 0;
diff --git a/include/configs/am62x_evm.h b/include/configs/am62x_evm.h
index c8fe59b7531..0d98f14a4bc 100644
--- a/include/configs/am62x_evm.h
+++ b/include/configs/am62x_evm.h
@@ -9,6 +9,30 @@
#ifndef __CONFIG_AM625_EVM_H
#define __CONFIG_AM625_EVM_H
+/**
+ * define AM62X_SK_TIBOOT3_IMAGE_GUID - firmware GUID for AM62X sk tiboot3.bin
+ * define AM62X_SK_SPL_IMAGE_GUID - firmware GUID for AM62X sk SPL
+ * define AM62X_SK_UBOOT_IMAGE_GUID - firmware GUID for AM62X sk UBOOT
+ *
+ * These GUIDs are used in capsules updates to identify the corresponding
+ * firmware object.
+ *
+ * Board developers using this as a starting reference should
+ * define their own GUIDs to ensure that firmware repositories (like
+ * LVFS) do not confuse them.
+ */
+#define AM62X_SK_TIBOOT3_IMAGE_GUID \
+ EFI_GUID(0xabcb83d2, 0x9cb6, 0x4351, 0xb8, 0xf1, \
+ 0x64, 0x94, 0xbb, 0xe3, 0x70, 0x0a)
+
+#define AM62X_SK_SPL_IMAGE_GUID \
+ EFI_GUID(0xaee355fc, 0xbf97, 0x4264, 0x8c, 0x82, \
+ 0x43, 0x72, 0x55, 0xef, 0xdc, 0x1d)
+
+#define AM62X_SK_UBOOT_IMAGE_GUID \
+ EFI_GUID(0x28ab8c6c, 0xfca8, 0x41d3, 0x8e, 0xa1, \
+ 0x5f, 0x17, 0x1b, 0x7d, 0x29, 0x29)
+
/* Now for the remaining common defines */
#include
--
2.34.1
Re: [PATCH] mmc: sdhci: introduce adma_write_desc() hook to struct sdhci_ops
Hi,
> Some target are failed to build. (e.g, j721e_beagleboneai64_r5)
>
> +drivers/mmc/sdhci-adma.c: In function '__sdhci_adma_write_desc':
> +drivers/mmc/sdhci-adma.c:37:43: error: 'const struct sdhci_ops' has no
> member named 'adma_write_desc'
> + 37 | if (host && host->ops && host->ops->adma_write_desc)
> + | ^~
> +drivers/mmc/sdhci-adma.c:38:26: error: 'const struct sdhci_ops' has no
> member named 'adma_write_desc'
> + 38 | host->ops->adma_write_desc(host, desc, addr, len,
> end);
> + | ^~
> +make[3]: *** [scripts/Makefile.build:257: drivers/mmc/sdhci-adma.o] Error 1
> +make[2]: *** [scripts/Makefile.build:397: drivers/mmc] Error 2
I will test v2 with CI before resubmitting so that this issue is
fixed. It is caused by the change and explanation below:
> > > diff --git a/include/sdhci.h b/include/sdhci.h
> > > index a1b74e3bd7..4bde7db5c7 100644
> > > --- a/include/sdhci.h
> > > +++ b/include/sdhci.h
> > > @@ -291,6 +291,11 @@ struct sdhci_ops {
> > > * Return: 0 if successful, -ve on error
> > > */
> > > int (*set_enhanced_strobe)(struct sdhci_host *host);
> > > +
> > > +#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
> > > + void(*adma_write_desc)(struct sdhci_host *host, void **desc,
> > > + dma_addr_t addr, int len, bool end);
> > > +#endif
> > > };
We got a little too excited about following checkpatch's
recommendations (no #ifdef CONFIG_xyz, prefer #if
CONFIG_IS_ENABLED(xyz)), which breaks down in this case:
CONFIG_IS_ENABLED(xyz) checks if:
- regular build and CONFIG_xyz is enabled (this portion succeeds)
- SPL build and CONFIG_SPL_xyz is enabled (this portion fails)
drivers/mmc/Makefile builds sdhci-adma.o based on
CONFIG_SDHCI_ADMA_HELPERS only.
There is no CONFIG_SPL_SDHCI_ADMA_HELPERS so CONFIG_IS_ENABLED fails
while building the SPL version of sdhci-adma.o as the structure
definition is different. This only appears on platforms which have
CONFIG_SPL_MMC enabled, which our platform did not, so I missed this
interaction earlier. I apologize for this mistake.
This will be fixed in v2 by changing the #if back to #ifdef
CONFIG_MMC_SDHCI_ADMA_HELPERS, which I will submit after CI finishes
running to verify on all platforms.
Thanks,
Greg
--
Greg Malysa
Timesys Corporation
Re: [PATCH v2] configs: am62px_evm_a53_defconfig: Enable MMC UHS config option
On April 16, 2024 thus sayeth Judith Mendez: > Enable MMC UHS support for to allow to enter the UHS > modes for MMC1. > s/support for/support/ Though it doesn't really matter to me. ;) > Signed-off-by: Judith Mendez > --- > Changes since v1: > - Fix typo in patch description > --- > > configs/am62px_evm_a53_defconfig | 2 ++ > 1 file changed, 2 insertions(+) > Thanks for finally getting MMC sorted so we can enable these configs Acked-by: Bryan Brattlof ~Bryan
Re: [PATCH v3] tpm-v2: allow algoirthm name to be configured for pcr_read and pcr_extend
On Fri, 19 Apr 2024 at 20:52, Tim Harvey wrote:
>
> On Fri, Apr 19, 2024 at 10:37 AM Ilias Apalodimas
> wrote:
> >
> > Also quickly looking at this, you need a new function for
> > tpm2_algorithm_to_mask() (look below)
> >
> > On Fri, 19 Apr 2024 at 20:20, Ilias Apalodimas
> > wrote:
> > >
> > > Hi Tim,
> > >
> > > On Fri, 19 Apr 2024 at 20:13, Tim Harvey wrote:
> > > >
> > > > On Sat, Apr 6, 2024 at 9:33 AM Ilias Apalodimas
> > > > wrote:
> > > > >
> > > > > Hi Tim,
> > > > >
> > > > > Thanks for the patch
> > > > >
> > > > > I'll be away next week, I'll try to find time and take a closer look.
> > > > > The pipeline [0] shows some TPM related failures
> > > > >
> > > > > [0]
> > > > > https://source.denx.de/u-boot/custodians/u-boot-tpm/-/commit/9b4be64e41454e17269a968397933eeff300c380
> > > > >
> > > >
> > > > Hi Ilias,
> > > >
> > > > I changed the output of 'tpm pcr_read' so that it shows the algo and
> > > > size causing the test in test/py/tests/test_tpm2.py to fail:
> > > > @@ -151,11 +171,12 @@ static int do_tpm_pcr_read(struct cmd_tbl
> > > > *cmdtp, int flag, int argc,
> > > >
> > > > data = map_sysmem(simple_strtoul(argv[2], NULL, 0), 0);
> > > >
> > > > - rc = tpm2_pcr_read(dev, index, priv->pcr_select_min,
> > > > TPM2_ALG_SHA256,
> > > > - data, TPM2_DIGEST_LEN, );
> > > > + rc = tpm2_pcr_read(dev, index, priv->pcr_select_min, algo,
> > > > + data, algo_len, );
> > > > if (!rc) {
> > > > - printf("PCR #%u content (%u known updates):\n", index,
> > > > updates);
> > > > - print_byte_string(data, TPM2_DIGEST_LEN);
> > > > + printf("PCR #%u %s %d byte content (%u known
> > > > updates):\n", index,
> > > > + tpm2_algorithm_name(algo), algo_len, updates);
> > > > + print_byte_string(data, algo_len);
> > > > }
> > > >
> > > > failure:
> > > > E AssertionError: assert 'PCR #10 content' in 'PCR #10 sha256 32
> > > > byte content (723 known updates):\r\r\n 00 00 00 00 00 00 00 00 00 00
> > > > 00 00 00 00 00 00\r\r\n 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> > > > 00'
> > > >
> > > > So I suppose I need to update test/py/tests/test_tpm2.py as well.
> > >
> > > Yes
> > >
> > > >
> > > > Would I update test/py/tests/test_tpm2.py in the same patch as the one
> > > > that causes the failure?
> > >
> > > Yes please, I'd like patches merged that won't break the CI
> > >
> > > >
> > > > How do I go about running the tests manually to make sure I've
> > > > addressed it?
> > >
> > > You can send a PR against U-Boots repo (in github)
> > >
> > > Cheers
> > > /Ilias
> > > >
> > > > Best Regards,
> > > >
> > > > Tim
> > > >
> > > > > Cheers
> > > > > /Ilias
> > > > >
> > > > > On Fri, 5 Apr 2024 at 03:17, Tim Harvey wrote:
> > > > > >
> > > > > > For pcr_read and pcr_extend commands allow the digest algorithm to
> > > > > > be
> > > > > > specified by an additional argument. If not specified it will
> > > > > > default to
> > > > > > SHA256 for backwards compatibility.
> > > > > >
> > > > > > A follow-on to this could be to extend all PCR banks with the
> > > > > > detected
> > > > > > algo when the argument is 'auto'.
> > > > > >
> > > > > > Signed-off-by: Tim Harvey
> > > > > > ---
> > > > > > v3:
> > > > > > - replace tpm2_supported_algorithms with struct and use this to
> > > > > > relate hash algoirthm
> > > > > >details
> > > > > > v2:
> > > > > > - use tpm2_algorithm_to_len
> > > > > > - use enum tpm2_algorithms
> > > > > > - make function names and parameter names more consistent with
> > > > > > existing
> > > > > >tpm-v2 functions
> > > > > > - fix various spelling errors
> > > > > > ---
> > > > > > cmd/tpm-v2.c | 49
> > > > > > include/tpm-v2.h | 67
> > > > > > ++-
> > > > > > lib/efi_loader/efi_tcg2.c | 4 +--
> > > > > > lib/tpm-v2.c | 62 +++-
> > > > > > 4 files changed, 143 insertions(+), 39 deletions(-)
> > > > > >
> > > > > > diff --git a/cmd/tpm-v2.c b/cmd/tpm-v2.c
> > > > > > index 7e479b9dfe36..2343b4d9cb9e 100644
> > > > > > --- a/cmd/tpm-v2.c
> > > > > > +++ b/cmd/tpm-v2.c
> > > > > > @@ -99,11 +99,19 @@ static int do_tpm2_pcr_extend(struct cmd_tbl
> > > > > > *cmdtp, int flag, int argc,
> > > > > > struct tpm_chip_priv *priv;
> > > > > > u32 index = simple_strtoul(argv[1], NULL, 0);
> > > > > > void *digest = map_sysmem(simple_strtoul(argv[2], NULL, 0),
> > > > > > 0);
> > > > > > + int algo = TPM2_ALG_SHA256;
> > > > > > + int algo_len;
> > > > > > int ret;
> > > > > > u32 rc;
> > > > > >
> > > > > > - if (argc != 3)
> > > > > > + if (argc < 3 || argc > 4)
> > > > > > return CMD_RET_USAGE;
> > > > > > + if (argc == 4) {
> > > > > > + algo =
Re: [PATCH] usb: dwc2: Add in version 4xx compatibility
Hi Mattijs, > Please avoid top-posting when replying, it makes following the > discussion more difficult: > https://www.kernel.org/doc/html/latest/process/submitting-patches.html#use-trimmed-interleaved-replies-in-email-discussions Will do. Sorry about that; I'm still learning about this approach to email. > Looking at > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=65dc2e725286106f99c6f6b78e3d9c52c15f3a9c > > we can see that the following is added: > #define DWC2_CORE_REV_MASK 0x > > This makes me believe that the versioning follows a well known pattern. I can submit a v2 next week to bring it in line with the kernel's approach. > Note that this change is also part of: > https://lore.kernel.org/all/20240328131811.94559-1-seashell11234...@gmail.com/ Or if you prefer I can also drop our patch and we can pursue this linked patch with both 4xx compatibility and the 420a reset handling. Thanks, Greg
Re: [PATCH v3 1/3] clk: imx8mm: Add support for PCIe clocks
On 4/19/24 5:29 PM, Tim Harvey wrote: Add support for PCIe clocks required to enable PCIe support on iMX8MM SoC. Signed-off-by: Tim Harvey Reviewed-by: Marek Vasut
Re: [PATCH v4 3/3] dts: support building all dtb files for a specific vendor
On 18/04/2024 20:39, Caleb Connolly wrote: This adjusts OF_UPSTREAM to behave more like the kernel by allowing for all the devicetree files for a given vendor to be compiled. This is useful for Qualcomm in particular as most boards are supported by a single U-Boot build just provided with a different DT. Signed-off-by: Caleb Connolly --- dts/Kconfig | 24 scripts/Makefile.dts | 13 + 2 files changed, 37 insertions(+) diff --git a/dts/Kconfig b/dts/Kconfig index b9b6367154ef..6883a000a052 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -100,8 +100,32 @@ config OF_UPSTREAM However, newer boards whose devicetree source files haven't landed in the dts/upstream subtree, they can override this option to have the DT build from existing U-Boot tree location instead. +config OF_UPSTREAM_BUILD_VENDOR + bool "Build all devicetree files for a particular vendor" + depends on OF_UPSTREAM + help + Enable building all devicetree files for a particular vendor. This + is useful for generic U-Boot configurations where many boards can + be supported with a single binary. + + This is only available for platforms using upstream devicetree. + +config OF_UPSTREAM_VENDOR + string "Vendor to build all upstream devicetree files for" + depends on OF_UPSTREAM_BUILD_VENDOR + default "qcom" if ARCH_SNAPDRAGON + default "rockchip" if ARCH_ROCKCHIP + default "amlogic" if ARCH_MESON + default "allwinner" if ARCH_SUNXI + default "mediatek" if ARCH_MEDIATEK + default "marvell" if ARCH_MVEBU || ARCH_KIRKWOOD + default "xilinx" if ARCH_VERSAL || ARCH_ZYNQ + default "nvidia" if ARCH_TEGRA + help + Select the vendor to build all devicetree files for. + choice prompt "Provider of DTB for DT control" depends on OF_CONTROL diff --git a/scripts/Makefile.dts b/scripts/Makefile.dts index 5e2429c6170c..790f3c508f19 100644 --- a/scripts/Makefile.dts +++ b/scripts/Makefile.dts @@ -1,3 +1,16 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-y += $(patsubst %,%.dtb,$(subst ",,$(CONFIG_DEFAULT_DEVICE_TREE) $(CONFIG_OF_LIST) $(CONFIG_SPL_OF_LIST))) + +ifeq ($(CONFIG_OF_UPSTREAM_BUILD_VENDOR),y) +ifeq ($(CONFIG_ARM64),y) +dt_dir := $(srctree)/dts/upstream/src/arm64 +else +dt_dir := $(srctree)/dts/upstream/src/$(ARCH) +endif + +dtb-vendor_dts := $(patsubst %.dts,%.dtb,$(wildcard $(dt_dir)/$(subst ",,$(CONFIG_OF_UPSTREAM_VENDOR))/*.dts)) + +dtb-y += $(subst $(dt_dir)/,,$(dtb-vendor_dts)) + +endif Reviewed-by: Neil Armstrong Tested-by: Neil Armstrong # on Amlogic boards builds Reduced the whole Amlogic buildman build from 4.50 minutes to 2.30minutes! Thanks, Neil
Re: [PATCH v3] tpm-v2: allow algoirthm name to be configured for pcr_read and pcr_extend
On Fri, Apr 19, 2024 at 10:37 AM Ilias Apalodimas
wrote:
>
> Also quickly looking at this, you need a new function for
> tpm2_algorithm_to_mask() (look below)
>
> On Fri, 19 Apr 2024 at 20:20, Ilias Apalodimas
> wrote:
> >
> > Hi Tim,
> >
> > On Fri, 19 Apr 2024 at 20:13, Tim Harvey wrote:
> > >
> > > On Sat, Apr 6, 2024 at 9:33 AM Ilias Apalodimas
> > > wrote:
> > > >
> > > > Hi Tim,
> > > >
> > > > Thanks for the patch
> > > >
> > > > I'll be away next week, I'll try to find time and take a closer look.
> > > > The pipeline [0] shows some TPM related failures
> > > >
> > > > [0]
> > > > https://source.denx.de/u-boot/custodians/u-boot-tpm/-/commit/9b4be64e41454e17269a968397933eeff300c380
> > > >
> > >
> > > Hi Ilias,
> > >
> > > I changed the output of 'tpm pcr_read' so that it shows the algo and
> > > size causing the test in test/py/tests/test_tpm2.py to fail:
> > > @@ -151,11 +171,12 @@ static int do_tpm_pcr_read(struct cmd_tbl
> > > *cmdtp, int flag, int argc,
> > >
> > > data = map_sysmem(simple_strtoul(argv[2], NULL, 0), 0);
> > >
> > > - rc = tpm2_pcr_read(dev, index, priv->pcr_select_min,
> > > TPM2_ALG_SHA256,
> > > - data, TPM2_DIGEST_LEN, );
> > > + rc = tpm2_pcr_read(dev, index, priv->pcr_select_min, algo,
> > > + data, algo_len, );
> > > if (!rc) {
> > > - printf("PCR #%u content (%u known updates):\n", index,
> > > updates);
> > > - print_byte_string(data, TPM2_DIGEST_LEN);
> > > + printf("PCR #%u %s %d byte content (%u known
> > > updates):\n", index,
> > > + tpm2_algorithm_name(algo), algo_len, updates);
> > > + print_byte_string(data, algo_len);
> > > }
> > >
> > > failure:
> > > E AssertionError: assert 'PCR #10 content' in 'PCR #10 sha256 32
> > > byte content (723 known updates):\r\r\n 00 00 00 00 00 00 00 00 00 00
> > > 00 00 00 00 00 00\r\r\n 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> > > 00'
> > >
> > > So I suppose I need to update test/py/tests/test_tpm2.py as well.
> >
> > Yes
> >
> > >
> > > Would I update test/py/tests/test_tpm2.py in the same patch as the one
> > > that causes the failure?
> >
> > Yes please, I'd like patches merged that won't break the CI
> >
> > >
> > > How do I go about running the tests manually to make sure I've addressed
> > > it?
> >
> > You can send a PR against U-Boots repo (in github)
> >
> > Cheers
> > /Ilias
> > >
> > > Best Regards,
> > >
> > > Tim
> > >
> > > > Cheers
> > > > /Ilias
> > > >
> > > > On Fri, 5 Apr 2024 at 03:17, Tim Harvey wrote:
> > > > >
> > > > > For pcr_read and pcr_extend commands allow the digest algorithm to be
> > > > > specified by an additional argument. If not specified it will default
> > > > > to
> > > > > SHA256 for backwards compatibility.
> > > > >
> > > > > A follow-on to this could be to extend all PCR banks with the detected
> > > > > algo when the argument is 'auto'.
> > > > >
> > > > > Signed-off-by: Tim Harvey
> > > > > ---
> > > > > v3:
> > > > > - replace tpm2_supported_algorithms with struct and use this to
> > > > > relate hash algoirthm
> > > > >details
> > > > > v2:
> > > > > - use tpm2_algorithm_to_len
> > > > > - use enum tpm2_algorithms
> > > > > - make function names and parameter names more consistent with
> > > > > existing
> > > > >tpm-v2 functions
> > > > > - fix various spelling errors
> > > > > ---
> > > > > cmd/tpm-v2.c | 49
> > > > > include/tpm-v2.h | 67
> > > > > ++-
> > > > > lib/efi_loader/efi_tcg2.c | 4 +--
> > > > > lib/tpm-v2.c | 62 +++-
> > > > > 4 files changed, 143 insertions(+), 39 deletions(-)
> > > > >
> > > > > diff --git a/cmd/tpm-v2.c b/cmd/tpm-v2.c
> > > > > index 7e479b9dfe36..2343b4d9cb9e 100644
> > > > > --- a/cmd/tpm-v2.c
> > > > > +++ b/cmd/tpm-v2.c
> > > > > @@ -99,11 +99,19 @@ static int do_tpm2_pcr_extend(struct cmd_tbl
> > > > > *cmdtp, int flag, int argc,
> > > > > struct tpm_chip_priv *priv;
> > > > > u32 index = simple_strtoul(argv[1], NULL, 0);
> > > > > void *digest = map_sysmem(simple_strtoul(argv[2], NULL, 0),
> > > > > 0);
> > > > > + int algo = TPM2_ALG_SHA256;
> > > > > + int algo_len;
> > > > > int ret;
> > > > > u32 rc;
> > > > >
> > > > > - if (argc != 3)
> > > > > + if (argc < 3 || argc > 4)
> > > > > return CMD_RET_USAGE;
> > > > > + if (argc == 4) {
> > > > > + algo = tpm2_name_to_algorithm(argv[3]);
> > > > > + if (algo < 0)
> > > > > + return CMD_RET_FAILURE;
> > > > > + }
> > > > > + algo_len = tpm2_algorithm_to_len(algo);
> > > > >
> > > > > ret = get_tpm();
> > > > > if (ret)
> > > > > @@ -116,8 +124,12 @@ static int do_tpm2_pcr_extend(struct cmd_tbl
>
Re: [PATCH v3] tpm-v2: allow algoirthm name to be configured for pcr_read and pcr_extend
Also quickly looking at this, you need a new function for
tpm2_algorithm_to_mask() (look below)
On Fri, 19 Apr 2024 at 20:20, Ilias Apalodimas
wrote:
>
> Hi Tim,
>
> On Fri, 19 Apr 2024 at 20:13, Tim Harvey wrote:
> >
> > On Sat, Apr 6, 2024 at 9:33 AM Ilias Apalodimas
> > wrote:
> > >
> > > Hi Tim,
> > >
> > > Thanks for the patch
> > >
> > > I'll be away next week, I'll try to find time and take a closer look.
> > > The pipeline [0] shows some TPM related failures
> > >
> > > [0]
> > > https://source.denx.de/u-boot/custodians/u-boot-tpm/-/commit/9b4be64e41454e17269a968397933eeff300c380
> > >
> >
> > Hi Ilias,
> >
> > I changed the output of 'tpm pcr_read' so that it shows the algo and
> > size causing the test in test/py/tests/test_tpm2.py to fail:
> > @@ -151,11 +171,12 @@ static int do_tpm_pcr_read(struct cmd_tbl
> > *cmdtp, int flag, int argc,
> >
> > data = map_sysmem(simple_strtoul(argv[2], NULL, 0), 0);
> >
> > - rc = tpm2_pcr_read(dev, index, priv->pcr_select_min,
> > TPM2_ALG_SHA256,
> > - data, TPM2_DIGEST_LEN, );
> > + rc = tpm2_pcr_read(dev, index, priv->pcr_select_min, algo,
> > + data, algo_len, );
> > if (!rc) {
> > - printf("PCR #%u content (%u known updates):\n", index,
> > updates);
> > - print_byte_string(data, TPM2_DIGEST_LEN);
> > + printf("PCR #%u %s %d byte content (%u known
> > updates):\n", index,
> > + tpm2_algorithm_name(algo), algo_len, updates);
> > + print_byte_string(data, algo_len);
> > }
> >
> > failure:
> > E AssertionError: assert 'PCR #10 content' in 'PCR #10 sha256 32
> > byte content (723 known updates):\r\r\n 00 00 00 00 00 00 00 00 00 00
> > 00 00 00 00 00 00\r\r\n 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> > 00'
> >
> > So I suppose I need to update test/py/tests/test_tpm2.py as well.
>
> Yes
>
> >
> > Would I update test/py/tests/test_tpm2.py in the same patch as the one
> > that causes the failure?
>
> Yes please, I'd like patches merged that won't break the CI
>
> >
> > How do I go about running the tests manually to make sure I've addressed it?
>
> You can send a PR against U-Boots repo (in github)
>
> Cheers
> /Ilias
> >
> > Best Regards,
> >
> > Tim
> >
> > > Cheers
> > > /Ilias
> > >
> > > On Fri, 5 Apr 2024 at 03:17, Tim Harvey wrote:
> > > >
> > > > For pcr_read and pcr_extend commands allow the digest algorithm to be
> > > > specified by an additional argument. If not specified it will default to
> > > > SHA256 for backwards compatibility.
> > > >
> > > > A follow-on to this could be to extend all PCR banks with the detected
> > > > algo when the argument is 'auto'.
> > > >
> > > > Signed-off-by: Tim Harvey
> > > > ---
> > > > v3:
> > > > - replace tpm2_supported_algorithms with struct and use this to relate
> > > > hash algoirthm
> > > >details
> > > > v2:
> > > > - use tpm2_algorithm_to_len
> > > > - use enum tpm2_algorithms
> > > > - make function names and parameter names more consistent with existing
> > > >tpm-v2 functions
> > > > - fix various spelling errors
> > > > ---
> > > > cmd/tpm-v2.c | 49
> > > > include/tpm-v2.h | 67 ++-
> > > > lib/efi_loader/efi_tcg2.c | 4 +--
> > > > lib/tpm-v2.c | 62 +++-
> > > > 4 files changed, 143 insertions(+), 39 deletions(-)
> > > >
> > > > diff --git a/cmd/tpm-v2.c b/cmd/tpm-v2.c
> > > > index 7e479b9dfe36..2343b4d9cb9e 100644
> > > > --- a/cmd/tpm-v2.c
> > > > +++ b/cmd/tpm-v2.c
> > > > @@ -99,11 +99,19 @@ static int do_tpm2_pcr_extend(struct cmd_tbl
> > > > *cmdtp, int flag, int argc,
> > > > struct tpm_chip_priv *priv;
> > > > u32 index = simple_strtoul(argv[1], NULL, 0);
> > > > void *digest = map_sysmem(simple_strtoul(argv[2], NULL, 0), 0);
> > > > + int algo = TPM2_ALG_SHA256;
> > > > + int algo_len;
> > > > int ret;
> > > > u32 rc;
> > > >
> > > > - if (argc != 3)
> > > > + if (argc < 3 || argc > 4)
> > > > return CMD_RET_USAGE;
> > > > + if (argc == 4) {
> > > > + algo = tpm2_name_to_algorithm(argv[3]);
> > > > + if (algo < 0)
> > > > + return CMD_RET_FAILURE;
> > > > + }
> > > > + algo_len = tpm2_algorithm_to_len(algo);
> > > >
> > > > ret = get_tpm();
> > > > if (ret)
> > > > @@ -116,8 +124,12 @@ static int do_tpm2_pcr_extend(struct cmd_tbl
> > > > *cmdtp, int flag, int argc,
> > > > if (index >= priv->pcr_count)
> > > > return -EINVAL;
> > > >
> > > > - rc = tpm2_pcr_extend(dev, index, TPM2_ALG_SHA256, digest,
> > > > -TPM2_DIGEST_LEN);
> > > > + rc = tpm2_pcr_extend(dev, index, algo, digest, algo_len);
> > > > + if (!rc) {
> > > > +
Re: [PATCH v3] tpm-v2: allow algoirthm name to be configured for pcr_read and pcr_extend
Hi Tim,
On Fri, 19 Apr 2024 at 20:13, Tim Harvey wrote:
>
> On Sat, Apr 6, 2024 at 9:33 AM Ilias Apalodimas
> wrote:
> >
> > Hi Tim,
> >
> > Thanks for the patch
> >
> > I'll be away next week, I'll try to find time and take a closer look.
> > The pipeline [0] shows some TPM related failures
> >
> > [0]
> > https://source.denx.de/u-boot/custodians/u-boot-tpm/-/commit/9b4be64e41454e17269a968397933eeff300c380
> >
>
> Hi Ilias,
>
> I changed the output of 'tpm pcr_read' so that it shows the algo and
> size causing the test in test/py/tests/test_tpm2.py to fail:
> @@ -151,11 +171,12 @@ static int do_tpm_pcr_read(struct cmd_tbl
> *cmdtp, int flag, int argc,
>
> data = map_sysmem(simple_strtoul(argv[2], NULL, 0), 0);
>
> - rc = tpm2_pcr_read(dev, index, priv->pcr_select_min, TPM2_ALG_SHA256,
> - data, TPM2_DIGEST_LEN, );
> + rc = tpm2_pcr_read(dev, index, priv->pcr_select_min, algo,
> + data, algo_len, );
> if (!rc) {
> - printf("PCR #%u content (%u known updates):\n", index,
> updates);
> - print_byte_string(data, TPM2_DIGEST_LEN);
> + printf("PCR #%u %s %d byte content (%u known
> updates):\n", index,
> + tpm2_algorithm_name(algo), algo_len, updates);
> + print_byte_string(data, algo_len);
> }
>
> failure:
> E AssertionError: assert 'PCR #10 content' in 'PCR #10 sha256 32
> byte content (723 known updates):\r\r\n 00 00 00 00 00 00 00 00 00 00
> 00 00 00 00 00 00\r\r\n 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00'
>
> So I suppose I need to update test/py/tests/test_tpm2.py as well.
Yes
>
> Would I update test/py/tests/test_tpm2.py in the same patch as the one
> that causes the failure?
Yes please, I'd like patches merged that won't break the CI
>
> How do I go about running the tests manually to make sure I've addressed it?
You can send a PR against U-Boots repo (in github)
Cheers
/Ilias
>
> Best Regards,
>
> Tim
>
> > Cheers
> > /Ilias
> >
> > On Fri, 5 Apr 2024 at 03:17, Tim Harvey wrote:
> > >
> > > For pcr_read and pcr_extend commands allow the digest algorithm to be
> > > specified by an additional argument. If not specified it will default to
> > > SHA256 for backwards compatibility.
> > >
> > > A follow-on to this could be to extend all PCR banks with the detected
> > > algo when the argument is 'auto'.
> > >
> > > Signed-off-by: Tim Harvey
> > > ---
> > > v3:
> > > - replace tpm2_supported_algorithms with struct and use this to relate
> > > hash algoirthm
> > >details
> > > v2:
> > > - use tpm2_algorithm_to_len
> > > - use enum tpm2_algorithms
> > > - make function names and parameter names more consistent with existing
> > >tpm-v2 functions
> > > - fix various spelling errors
> > > ---
> > > cmd/tpm-v2.c | 49
> > > include/tpm-v2.h | 67 ++-
> > > lib/efi_loader/efi_tcg2.c | 4 +--
> > > lib/tpm-v2.c | 62 +++-
> > > 4 files changed, 143 insertions(+), 39 deletions(-)
> > >
> > > diff --git a/cmd/tpm-v2.c b/cmd/tpm-v2.c
> > > index 7e479b9dfe36..2343b4d9cb9e 100644
> > > --- a/cmd/tpm-v2.c
> > > +++ b/cmd/tpm-v2.c
> > > @@ -99,11 +99,19 @@ static int do_tpm2_pcr_extend(struct cmd_tbl *cmdtp,
> > > int flag, int argc,
> > > struct tpm_chip_priv *priv;
> > > u32 index = simple_strtoul(argv[1], NULL, 0);
> > > void *digest = map_sysmem(simple_strtoul(argv[2], NULL, 0), 0);
> > > + int algo = TPM2_ALG_SHA256;
> > > + int algo_len;
> > > int ret;
> > > u32 rc;
> > >
> > > - if (argc != 3)
> > > + if (argc < 3 || argc > 4)
> > > return CMD_RET_USAGE;
> > > + if (argc == 4) {
> > > + algo = tpm2_name_to_algorithm(argv[3]);
> > > + if (algo < 0)
> > > + return CMD_RET_FAILURE;
> > > + }
> > > + algo_len = tpm2_algorithm_to_len(algo);
> > >
> > > ret = get_tpm();
> > > if (ret)
> > > @@ -116,8 +124,12 @@ static int do_tpm2_pcr_extend(struct cmd_tbl *cmdtp,
> > > int flag, int argc,
> > > if (index >= priv->pcr_count)
> > > return -EINVAL;
> > >
> > > - rc = tpm2_pcr_extend(dev, index, TPM2_ALG_SHA256, digest,
> > > -TPM2_DIGEST_LEN);
> > > + rc = tpm2_pcr_extend(dev, index, algo, digest, algo_len);
> > > + if (!rc) {
> > > + printf("PCR #%u extended with %d byte %s digest\n", index,
> > > + algo_len, tpm2_algorithm_name(algo));
> > > + print_byte_string(digest, algo_len);
> > > + }
> > >
> > > unmap_sysmem(digest);
> > >
> > > @@ -127,15 +139,23 @@ static int do_tpm2_pcr_extend(struct cmd_tbl
> > > *cmdtp, int flag, int argc,
> > > static int do_tpm_pcr_read(struct cmd_tbl *cmdtp, int
Re: [PATCH v6 01/18] video: tegra20: dc: diverge DC per-SOC
пт, 19 квіт. 2024 р. о 19:26 Thierry Reding пише:
>
> On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote:
> [...]
> > diff --git a/arch/arm/include/asm/arch-tegra114/display.h
> > b/arch/arm/include/asm/arch-tegra114/display.h
> > new file mode 100644
> > index 00..9411525799
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-tegra114/display.h
> > @@ -0,0 +1,28 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * (C) Copyright 2010
> > + * NVIDIA Corporation
> > + */
> > +
> > +#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
> > +#define __ASM_ARCH_TEGRA_DISPLAY_H
> > +
> > +#include
> > +
> > +/* This holds information about a window which can be displayed */
> > +struct disp_ctl_win {
> > + enum win_color_depth_id fmt;/* Color depth/format */
> > + unsigned intbpp;/* Bits per pixel */
> > + phys_addr_t phys_addr; /* Physical address in memory */
> > + unsigned intx; /* Horizontal address offset (bytes)
> > */
> > + unsigned inty; /* Veritical address offset (bytes) */
> > + unsigned intw; /* Width of source window */
> > + unsigned inth; /* Height of source window */
> > + unsigned intstride; /* Number of bytes per line */
> > + unsigned intout_x; /* Left edge of output window (col) */
> > + unsigned intout_y; /* Top edge of output window (row) */
> > + unsigned intout_w; /* Width of output window in pixels */
> > + unsigned intout_h; /* Height of output window in pixels
> > */
> > +};
> > +
> > +#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
>
> One of the earlier patches in the series gets rid of this per-SoC header
> file in favor of a common one. Did this end up here by mistake? It
> doesn't seem to be used.
>
> > diff --git a/drivers/video/tegra20/tegra-dc.c
> > b/drivers/video/tegra20/tegra-dc.c
> > index f53ad46397..7605e77bc1 100644
> > --- a/drivers/video/tegra20/tegra-dc.c
> > +++ b/drivers/video/tegra20/tegra-dc.c
> > @@ -3,7 +3,6 @@
> > * Copyright (c) 2011 The Chromium OS Authors.
> > */
> >
> > -#include
> > #include
> > #include
> > #include
> > @@ -23,10 +22,15 @@
> > #include
> > #include
> > #include
> > -#include
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > +/* Holder of Tegra per-SOC DC differences */
> > +struct tegra_dc_soc_info {
> > + bool has_timer;
> > + bool has_rgb;
> > +};
> > +
> > /* Information about the display controller */
> > struct tegra_lcd_priv {
> > int width; /* width in pixels */
> > @@ -35,6 +39,7 @@ struct tegra_lcd_priv {
> > struct display_timing timing;
> > struct udevice *panel;
> > struct dc_ctlr *dc; /* Display controller regmap */
> > + const struct tegra_dc_soc_info *soc;
> > fdt_addr_t frame_buffer;/* Address of frame buffer */
> > unsigned pixel_clock; /* Pixel clock in Hz */
> > int dc_clk[2]; /* Contains clk and its parent */
> > @@ -43,8 +48,8 @@ struct tegra_lcd_priv {
> >
> > enum {
> > /* Maximum LCD size we support */
> > - LCD_MAX_WIDTH = 1920,
> > - LCD_MAX_HEIGHT = 1200,
> > + LCD_MAX_WIDTH = 2560,
> > + LCD_MAX_HEIGHT = 1600,
> > LCD_MAX_LOG2_BPP= VIDEO_BPP16,
> > };
> >
> > @@ -110,9 +115,9 @@ static void update_window(struct tegra_lcd_priv *priv,
> > writel(val, >cmd.state_ctrl);
> > }
> >
> > -static int update_display_mode(struct dc_disp_reg *disp,
> > -struct tegra_lcd_priv *priv)
> > +static int update_display_mode(struct tegra_lcd_priv *priv)
> > {
> > + struct dc_disp_reg *disp = >dc->disp;
> > struct display_timing *dt = >timing;
> > unsigned long val;
> > unsigned long rate;
> > @@ -128,14 +133,16 @@ static int update_display_mode(struct dc_disp_reg
> > *disp,
> > >front_porch);
> > writel(dt->hactive.typ | (dt->vactive.typ << 16), >disp_active);
> >
> > - val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
> > - val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
> > - writel(val, >data_enable_opt);
> > + if (priv->soc->has_rgb) {
> > + val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
> > + val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
> > + writel(val, >data_enable_opt);
> >
> > - val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
> > - val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
> > - val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
> > - writel(val, >disp_interface_ctrl);
> > + val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
> > + val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
> > + val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
> > + writel(val, >disp_interface_ctrl);
> > + }
> >
> > /*
> >* The
Re: [PATCH v3] tpm-v2: allow algoirthm name to be configured for pcr_read and pcr_extend
On Sat, Apr 6, 2024 at 9:33 AM Ilias Apalodimas
wrote:
>
> Hi Tim,
>
> Thanks for the patch
>
> I'll be away next week, I'll try to find time and take a closer look.
> The pipeline [0] shows some TPM related failures
>
> [0]
> https://source.denx.de/u-boot/custodians/u-boot-tpm/-/commit/9b4be64e41454e17269a968397933eeff300c380
>
Hi Ilias,
I changed the output of 'tpm pcr_read' so that it shows the algo and
size causing the test in test/py/tests/test_tpm2.py to fail:
@@ -151,11 +171,12 @@ static int do_tpm_pcr_read(struct cmd_tbl
*cmdtp, int flag, int argc,
data = map_sysmem(simple_strtoul(argv[2], NULL, 0), 0);
- rc = tpm2_pcr_read(dev, index, priv->pcr_select_min, TPM2_ALG_SHA256,
- data, TPM2_DIGEST_LEN, );
+ rc = tpm2_pcr_read(dev, index, priv->pcr_select_min, algo,
+ data, algo_len, );
if (!rc) {
- printf("PCR #%u content (%u known updates):\n", index, updates);
- print_byte_string(data, TPM2_DIGEST_LEN);
+ printf("PCR #%u %s %d byte content (%u known
updates):\n", index,
+ tpm2_algorithm_name(algo), algo_len, updates);
+ print_byte_string(data, algo_len);
}
failure:
E AssertionError: assert 'PCR #10 content' in 'PCR #10 sha256 32
byte content (723 known updates):\r\r\n 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00\r\r\n 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00'
So I suppose I need to update test/py/tests/test_tpm2.py as well.
Would I update test/py/tests/test_tpm2.py in the same patch as the one
that causes the failure?
How do I go about running the tests manually to make sure I've addressed it?
Best Regards,
Tim
> Cheers
> /Ilias
>
> On Fri, 5 Apr 2024 at 03:17, Tim Harvey wrote:
> >
> > For pcr_read and pcr_extend commands allow the digest algorithm to be
> > specified by an additional argument. If not specified it will default to
> > SHA256 for backwards compatibility.
> >
> > A follow-on to this could be to extend all PCR banks with the detected
> > algo when the argument is 'auto'.
> >
> > Signed-off-by: Tim Harvey
> > ---
> > v3:
> > - replace tpm2_supported_algorithms with struct and use this to relate
> > hash algoirthm
> >details
> > v2:
> > - use tpm2_algorithm_to_len
> > - use enum tpm2_algorithms
> > - make function names and parameter names more consistent with existing
> >tpm-v2 functions
> > - fix various spelling errors
> > ---
> > cmd/tpm-v2.c | 49
> > include/tpm-v2.h | 67 ++-
> > lib/efi_loader/efi_tcg2.c | 4 +--
> > lib/tpm-v2.c | 62 +++-
> > 4 files changed, 143 insertions(+), 39 deletions(-)
> >
> > diff --git a/cmd/tpm-v2.c b/cmd/tpm-v2.c
> > index 7e479b9dfe36..2343b4d9cb9e 100644
> > --- a/cmd/tpm-v2.c
> > +++ b/cmd/tpm-v2.c
> > @@ -99,11 +99,19 @@ static int do_tpm2_pcr_extend(struct cmd_tbl *cmdtp,
> > int flag, int argc,
> > struct tpm_chip_priv *priv;
> > u32 index = simple_strtoul(argv[1], NULL, 0);
> > void *digest = map_sysmem(simple_strtoul(argv[2], NULL, 0), 0);
> > + int algo = TPM2_ALG_SHA256;
> > + int algo_len;
> > int ret;
> > u32 rc;
> >
> > - if (argc != 3)
> > + if (argc < 3 || argc > 4)
> > return CMD_RET_USAGE;
> > + if (argc == 4) {
> > + algo = tpm2_name_to_algorithm(argv[3]);
> > + if (algo < 0)
> > + return CMD_RET_FAILURE;
> > + }
> > + algo_len = tpm2_algorithm_to_len(algo);
> >
> > ret = get_tpm();
> > if (ret)
> > @@ -116,8 +124,12 @@ static int do_tpm2_pcr_extend(struct cmd_tbl *cmdtp,
> > int flag, int argc,
> > if (index >= priv->pcr_count)
> > return -EINVAL;
> >
> > - rc = tpm2_pcr_extend(dev, index, TPM2_ALG_SHA256, digest,
> > -TPM2_DIGEST_LEN);
> > + rc = tpm2_pcr_extend(dev, index, algo, digest, algo_len);
> > + if (!rc) {
> > + printf("PCR #%u extended with %d byte %s digest\n", index,
> > + algo_len, tpm2_algorithm_name(algo));
> > + print_byte_string(digest, algo_len);
> > + }
> >
> > unmap_sysmem(digest);
> >
> > @@ -127,15 +139,23 @@ static int do_tpm2_pcr_extend(struct cmd_tbl *cmdtp,
> > int flag, int argc,
> > static int do_tpm_pcr_read(struct cmd_tbl *cmdtp, int flag, int argc,
> >char *const argv[])
> > {
> > + enum tpm2_algorithms algo = TPM2_ALG_SHA256;
> > struct udevice *dev;
> > struct tpm_chip_priv *priv;
> > u32 index, rc;
> > + int algo_len;
> > unsigned int updates;
> > void *data;
> > int ret;
> >
> > - if (argc != 3)
> > + if (argc < 3 || argc > 4)
> > return CMD_RET_USAGE;
Re: [PATCH v6 09/18] video: tegra20: dc: fix printing of framebuffer address
On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote:
> From: Jonas Schwöbel
>
> Framebuffer address should not be a pointer.
>
> Signed-off-by: Jonas Schwöbel
> Signed-off-by: Svyatoslav Ryhel
> ---
> drivers/video/tegra20/tegra-dc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/video/tegra20/tegra-dc.c
> b/drivers/video/tegra20/tegra-dc.c
> index a8e32e6893..000a0e02f8 100644
> --- a/drivers/video/tegra20/tegra-dc.c
> +++ b/drivers/video/tegra20/tegra-dc.c
> @@ -429,7 +429,7 @@ static int tegra_lcd_probe(struct udevice *dev)
> uc_priv->xsize = priv->width;
> uc_priv->ysize = priv->height;
> uc_priv->bpix = priv->log2_bpp;
> - debug("LCD frame buffer at %pa, size %x\n", >frame_buffer,
> + debug("LCD frame buffer at %08x, size %x\n", priv->frame_buffer,
%pa is usually treated in a special way. At least it is on Linux, not
sure if the U-Boot printf implementation uses this, too. Looking at
doc/develop/printf.rst, it seems like this is supported, and given that
priv->frame_buffer is fdt_addr_t, %pa seems totally appropriate here.
Thierry
signature.asc
Description: PGP signature
Re: [PATCH v6 04/18] video: tegra20: dc: pass DC id to internal devices
пт, 19 квіт. 2024 р. о 19:58 Thierry Reding пише:
>
> On Fri Apr 19, 2024 at 6:44 PM CEST, Svyatoslav Ryhel wrote:
> > пт, 19 квіт. 2024 р. о 19:38 Thierry Reding пише:
> > >
> > > On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote:
> > > > Tegra SoC has 2 independent display controllers called DC_A and
> > > > DC_B, they are handled differently by internal video devices like
> > > > DSI and HDMI controllers so it is important for last to know
> > > > which display controller is used to properly set up registers.
> > > > To achieve this, a pipe field was added to pdata to pass display
> > > > controller id to internal Tegra SoC devices.
> > > >
> > > > Tested-by: Agneli # Toshiba AC100 T20
> > > > Tested-by: Robert Eckelmann # ASUS TF101
> > > > Tested-by: Andreas Westman Dorcsak # ASUS Grouper
> > > > E1565
> > > > Tested-by: Ion Agorria # HTC One X
> > > > Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114
> > > > Signed-off-by: Svyatoslav Ryhel
> > > > ---
> > > > drivers/video/tegra20/tegra-dc.c | 6 ++
> > > > drivers/video/tegra20/tegra-dc.h | 3 +++
> > > > 2 files changed, 9 insertions(+)
> > > >
> > > > diff --git a/drivers/video/tegra20/tegra-dc.c
> > > > b/drivers/video/tegra20/tegra-dc.c
> > > > index 5d8874f323..0e94e665ef 100644
> > > > --- a/drivers/video/tegra20/tegra-dc.c
> > > > +++ b/drivers/video/tegra20/tegra-dc.c
> > > > @@ -45,6 +45,7 @@ struct tegra_lcd_priv {
> > > > unsigned pixel_clock; /* Pixel clock in Hz */
> > > > int dc_clk[2]; /* Contains clk and its parent */
> > > > bool rotation; /* 180 degree panel turn */
> > > > + bool pipe; /* DC controller: 0 for A, 1 for
> > > > B */
> > >
> > > Bool is a poor choice, even if there's only two of them. This is a
> > > proper index, so it should be some sort of integer.
> > >
> > > Also, the device tree bindings for the display controller specify a
> > > "nvidia,head" property that can be used to identify these. If you add
> > > that to the U-Boot DT you can avoid looking up by name to map this
> > > value.
> > >
> >
> > Thanks for pointing to this property. May we apply this patch set as is
> > since it is well tested and confirmed to work and I will prepare a follow
> > up patches to adjust device tree relations? Would what be ok?
>
> Well, there's a few other things that I think should be addressed, but
> if you'd like to keep this one patch as-is and clean this up later, I
> guess that's fine.
May you send me a list of stuff which you think may be improved?
I would gladly adjust whatever I can in follow up.
> Thierry
Re: [PATCH v6 12/18] video: tegra20: dc: parameterize V- and H-sync polarities
On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote:
> Based on Thierry Reding's Linux commit:
>
> 'commit 1716b1891e1de05e2c20ccafa9f58550f3539717
> ("drm/tegra: rgb: Parameterize V- and H-sync polarities")'
>
> Signed-off-by: Svyatoslav Ryhel
> ---
> arch/arm/include/asm/arch-tegra/dc.h | 5 +
> drivers/video/tegra20/tegra-dc.c | 22 --
> 2 files changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-tegra/dc.h
> b/arch/arm/include/asm/arch-tegra/dc.h
> index 6444af2993..ca3718411a 100644
> --- a/arch/arm/include/asm/arch-tegra/dc.h
> +++ b/arch/arm/include/asm/arch-tegra/dc.h
> @@ -443,6 +443,11 @@ enum win_color_depth_id {
> #define WINDOW_D_SELECT BIT(7)
> #define WINDOW_H_SELECT BIT(8)
>
> +/* DC_COM_PIN_OUTPUT_POLARITY1 0x307 */
> +#define LHS_OUTPUT_POLARITY_LOW BIT(30)
> +#define LVS_OUTPUT_POLARITY_LOW BIT(28)
> +#define LSC0_OUTPUT_POLARITY_LOW BIT(24)
This definition seems to be unused, other than that:
Reviewed-by: Thierry Reding
signature.asc
Description: PGP signature
Re: [PATCH v6 04/18] video: tegra20: dc: pass DC id to internal devices
On Fri Apr 19, 2024 at 6:44 PM CEST, Svyatoslav Ryhel wrote:
> пт, 19 квіт. 2024 р. о 19:38 Thierry Reding пише:
> >
> > On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote:
> > > Tegra SoC has 2 independent display controllers called DC_A and
> > > DC_B, they are handled differently by internal video devices like
> > > DSI and HDMI controllers so it is important for last to know
> > > which display controller is used to properly set up registers.
> > > To achieve this, a pipe field was added to pdata to pass display
> > > controller id to internal Tegra SoC devices.
> > >
> > > Tested-by: Agneli # Toshiba AC100 T20
> > > Tested-by: Robert Eckelmann # ASUS TF101
> > > Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565
> > > Tested-by: Ion Agorria # HTC One X
> > > Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114
> > > Signed-off-by: Svyatoslav Ryhel
> > > ---
> > > drivers/video/tegra20/tegra-dc.c | 6 ++
> > > drivers/video/tegra20/tegra-dc.h | 3 +++
> > > 2 files changed, 9 insertions(+)
> > >
> > > diff --git a/drivers/video/tegra20/tegra-dc.c
> > > b/drivers/video/tegra20/tegra-dc.c
> > > index 5d8874f323..0e94e665ef 100644
> > > --- a/drivers/video/tegra20/tegra-dc.c
> > > +++ b/drivers/video/tegra20/tegra-dc.c
> > > @@ -45,6 +45,7 @@ struct tegra_lcd_priv {
> > > unsigned pixel_clock; /* Pixel clock in Hz */
> > > int dc_clk[2]; /* Contains clk and its parent */
> > > bool rotation; /* 180 degree panel turn */
> > > + bool pipe; /* DC controller: 0 for A, 1 for B
> > > */
> >
> > Bool is a poor choice, even if there's only two of them. This is a
> > proper index, so it should be some sort of integer.
> >
> > Also, the device tree bindings for the display controller specify a
> > "nvidia,head" property that can be used to identify these. If you add
> > that to the U-Boot DT you can avoid looking up by name to map this
> > value.
> >
>
> Thanks for pointing to this property. May we apply this patch set as is
> since it is well tested and confirmed to work and I will prepare a follow
> up patches to adjust device tree relations? Would what be ok?
Well, there's a few other things that I think should be addressed, but
if you'd like to keep this one patch as-is and clean this up later, I
guess that's fine.
Thierry
signature.asc
Description: PGP signature
Re: [PATCH v6 07/18] video: tegra20: dc: add powergate
On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > Add powergate use on T114 to complete resetting of DC. > > Signed-off-by: Svyatoslav Ryhel > --- > drivers/video/tegra20/tegra-dc.c | 27 +++ > 1 file changed, 27 insertions(+) Seems correct: Reviewed-by: Thierry Reding signature.asc Description: PGP signature
Re: [PATCH v6 11/18] video: tegra20: dc: clean framebuffer memory block
On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > From: Jonas Schwöbel > > Fill the framebuffer memory with zeros to avoid visual glitches. > > Signed-off-by: Jonas Schwöbel > Signed-off-by: Svyatoslav Ryhel > --- > drivers/video/tegra20/tegra-dc.c | 5 + > 1 file changed, 5 insertions(+) Makes sense: Reviewed-by: Thierry Reding signature.asc Description: PGP signature
Re: [PATCH v6 06/18] video: tegra20: dc: add reset support
пт, 19 квіт. 2024 р. о 19:46 Thierry Reding пише:
>
> On Fri Apr 19, 2024 at 6:37 PM CEST, Svyatoslav Ryhel wrote:
> > пт, 19 квіт. 2024 р. о 19:05 Thierry Reding пише:
> > >
> > > On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote:
> > > > Implement reset use to discard any changes which could have been
> > > > applied to DC before and can interfere with current configuration.
> > > >
> > > > Tested-by: Agneli # Toshiba AC100 T20
> > > > Tested-by: Robert Eckelmann # ASUS TF101
> > > > Tested-by: Andreas Westman Dorcsak # ASUS Grouper
> > > > E1565
> > > > Tested-by: Ion Agorria # HTC One X
> > > > Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114
> > > > Signed-off-by: Svyatoslav Ryhel
> > > > ---
> > > > drivers/video/tegra20/tegra-dc.c | 17 +
> > > > 1 file changed, 17 insertions(+)
> > > >
> > > > diff --git a/drivers/video/tegra20/tegra-dc.c
> > > > b/drivers/video/tegra20/tegra-dc.c
> > > > index 56a23b3c97..35abb6fe46 100644
> > > > --- a/drivers/video/tegra20/tegra-dc.c
> > > > +++ b/drivers/video/tegra20/tegra-dc.c
> > > > @@ -10,7 +10,9 @@
> > > > #include
> > > > #include
> > > > #include
> > > > +#include
> > > > #include
> > > > +#include
> > > > #include
> > > > #include
> > > > #include
> > > > @@ -342,6 +344,7 @@ static int tegra_lcd_probe(struct udevice *dev)
> > > > struct video_uc_plat *plat = dev_get_uclass_plat(dev);
> > > > struct video_priv *uc_priv = dev_get_uclass_priv(dev);
> > > > struct tegra_lcd_priv *priv = dev_get_priv(dev);
> > > > + struct reset_ctl reset_ctl;
> > > > int ret;
> > > >
> > > > /* Initialize the Tegra display controller */
> > > > @@ -349,6 +352,20 @@ static int tegra_lcd_probe(struct udevice *dev)
> > > > funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
> > > > #endif
> > > >
> > > > + ret = reset_get_by_name(dev, "dc", _ctl);
> > > > + if (ret) {
> > > > + log_err("reset_get_by_name() failed: %d\n", ret);
> > > > + return ret;
> > > > + }
> > > > +
> > > > + clock_disable(priv->dc_clk[0]);
> > > > +
> > > > + /* Reset everything set before */
> > > > + reset_assert(_ctl);
> > > > + mdelay(4);
> > > > + reset_deassert(_ctl);
> > > > + mdelay(4);
> > >
> > > Are you sure this works as intended? It's been a long time since I
> > > worked on this, but I seem to recall that most of these resets are
> > > actually synchronous, so in order for them to do what they're supposed
> > > to the clock needs to be kept running.
> > >
> > > The Linux driver certainly does this differently.
> >
> > You have point, but I have tried to mostly adapt Linux tegra dc driver,
> > which has same logic in probe. Maybe I have not understood it properly.
> > Testing on T20, T30 and T114 passed without issues so far.
>
> Maybe look again. What it does is (basically):
>
> clock_enable();
> mdelay(4);
> reset_assert();
> mdelay(4);
> clock_disable();
>
> That should ensure that it's completely reset at that point. Now before
> any subsequent register accesses happen it will do this:
>
> clock_enable();
> reset_deassert();
>
> to take it out of reset again. Perhaps that's something you want to keep
> doing in probe() in U-Boot. In that case maybe you want something like
> this instead:
>
> clock_enable();
> mdelay(4);
> reset_assert();
> mdelay(4);
> reset_deassert();
>
You are correct. I assume This patch may be dropped entirely. Thanks.
> Thierry
Re: [PATCH v6 15/18] video: tegra20: dsi: add reset support
On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote:
> Implement reset use to discard any changes which could have been
> applied to DSI before and can interfere with current configuration.
>
> Tested-by: Ion Agorria # HTC One X
> Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114
> Signed-off-by: Svyatoslav Ryhel
> ---
> drivers/video/tegra20/tegra-dsi.c | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/video/tegra20/tegra-dsi.c
> b/drivers/video/tegra20/tegra-dsi.c
> index 25a629535e..fc9ca1310a 100644
> --- a/drivers/video/tegra20/tegra-dsi.c
> +++ b/drivers/video/tegra20/tegra-dsi.c
> @@ -12,6 +12,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -863,6 +864,7 @@ static int tegra_dsi_bridge_probe(struct udevice *dev)
> struct tegra_dsi_priv *priv = dev_get_priv(dev);
> struct mipi_dsi_device *device = >device;
> struct mipi_dsi_panel_plat *mipi_plat;
> + struct reset_ctl reset_ctl;
> int ret;
>
> priv->version = dev_get_driver_data(dev);
> @@ -876,6 +878,13 @@ static int tegra_dsi_bridge_probe(struct udevice *dev)
> priv->video_fifo_depth = 480;
> priv->host_fifo_depth = 64;
>
> + ret = reset_get_by_name(dev, "dsi", _ctl);
> + if (ret) {
> + log_debug("%s: reset_get_by_name() failed: %d\n",
> + __func__, ret);
> + return ret;
> + }
> +
> ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
> "avdd-dsi-csi-supply", >avdd);
> if (ret)
> @@ -914,12 +923,17 @@ static int tegra_dsi_bridge_probe(struct udevice *dev)
>
> tegra_dsi_get_format(device->format, >format);
>
> + reset_assert(_ctl);
> +
> ret = regulator_set_enable_if_allowed(priv->avdd, true);
> if (ret && ret != -ENOSYS)
> return ret;
>
> tegra_dsi_init_clocks(dev);
>
> + mdelay(2);
> + reset_deassert(_ctl);
> +
> return 0;
> }
Looks like tegra_dsi_init_clocks() already does the mdelay() and
reset_deassert()? Or perhaps I'm again looking at things in the wrong
order?
Thierry
signature.asc
Description: PGP signature
Re: [PATCH v6 05/18] video: tegra20: dc: add PLLD2 parent support
On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > T30+ SOC have second PLLD - PLLD2 which can be actively used by > DC and act as main DISP1/2 clock parent. > > Tested-by: Agneli # Toshiba AC100 T20 > Tested-by: Robert Eckelmann # ASUS TF101 > Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565 > Tested-by: Ion Agorria # HTC One X > Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114 > Signed-off-by: Svyatoslav Ryhel > --- > drivers/video/tegra20/tegra-dc.c | 6 ++ > 1 file changed, 6 insertions(+) Reviewed-by: Thierry Reding signature.asc Description: PGP signature
Re: [PATCH v6 08/18] video: tegra20: dc: configure behavior if PLLD/D2 is used
On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > If DISP1 is a PLLD/D2 child, it cannot go over 370MHz. The cause > of this is not quite clear. This can be overcomed by further > halving the PLLD/D2 if the target parent rate is over 800MHz. > This way DISP1 and DSI clocks will have the same frequency. The > shift divider in this case has to be calculated from the > original PLLD/D2 frequency and is passed from the DSI driver. > > Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565 > Tested-by: Ion Agorria # HTC One X > Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114 > Tested-by: Jonas Schwöbel # Microsoft Surface 2 > Signed-off-by: Jonas Schwöbel > Signed-off-by: Svyatoslav Ryhel > --- > drivers/video/tegra20/tegra-dc.c | 34 +++ > drivers/video/tegra20/tegra-dc.h | 1 + > drivers/video/tegra20/tegra-dsi.c | 14 + > 3 files changed, 36 insertions(+), 13 deletions(-) I'm not very familiar with these clocks, but seeing that this was extensively tested, I guess this is okay, so: Acked-by: Thierry Reding signature.asc Description: PGP signature
Re: [PATCH v6 06/18] video: tegra20: dc: add reset support
On Fri Apr 19, 2024 at 6:37 PM CEST, Svyatoslav Ryhel wrote:
> пт, 19 квіт. 2024 р. о 19:05 Thierry Reding пише:
> >
> > On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote:
> > > Implement reset use to discard any changes which could have been
> > > applied to DC before and can interfere with current configuration.
> > >
> > > Tested-by: Agneli # Toshiba AC100 T20
> > > Tested-by: Robert Eckelmann # ASUS TF101
> > > Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565
> > > Tested-by: Ion Agorria # HTC One X
> > > Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114
> > > Signed-off-by: Svyatoslav Ryhel
> > > ---
> > > drivers/video/tegra20/tegra-dc.c | 17 +
> > > 1 file changed, 17 insertions(+)
> > >
> > > diff --git a/drivers/video/tegra20/tegra-dc.c
> > > b/drivers/video/tegra20/tegra-dc.c
> > > index 56a23b3c97..35abb6fe46 100644
> > > --- a/drivers/video/tegra20/tegra-dc.c
> > > +++ b/drivers/video/tegra20/tegra-dc.c
> > > @@ -10,7 +10,9 @@
> > > #include
> > > #include
> > > #include
> > > +#include
> > > #include
> > > +#include
> > > #include
> > > #include
> > > #include
> > > @@ -342,6 +344,7 @@ static int tegra_lcd_probe(struct udevice *dev)
> > > struct video_uc_plat *plat = dev_get_uclass_plat(dev);
> > > struct video_priv *uc_priv = dev_get_uclass_priv(dev);
> > > struct tegra_lcd_priv *priv = dev_get_priv(dev);
> > > + struct reset_ctl reset_ctl;
> > > int ret;
> > >
> > > /* Initialize the Tegra display controller */
> > > @@ -349,6 +352,20 @@ static int tegra_lcd_probe(struct udevice *dev)
> > > funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
> > > #endif
> > >
> > > + ret = reset_get_by_name(dev, "dc", _ctl);
> > > + if (ret) {
> > > + log_err("reset_get_by_name() failed: %d\n", ret);
> > > + return ret;
> > > + }
> > > +
> > > + clock_disable(priv->dc_clk[0]);
> > > +
> > > + /* Reset everything set before */
> > > + reset_assert(_ctl);
> > > + mdelay(4);
> > > + reset_deassert(_ctl);
> > > + mdelay(4);
> >
> > Are you sure this works as intended? It's been a long time since I
> > worked on this, but I seem to recall that most of these resets are
> > actually synchronous, so in order for them to do what they're supposed
> > to the clock needs to be kept running.
> >
> > The Linux driver certainly does this differently.
>
> You have point, but I have tried to mostly adapt Linux tegra dc driver,
> which has same logic in probe. Maybe I have not understood it properly.
> Testing on T20, T30 and T114 passed without issues so far.
Maybe look again. What it does is (basically):
clock_enable();
mdelay(4);
reset_assert();
mdelay(4);
clock_disable();
That should ensure that it's completely reset at that point. Now before
any subsequent register accesses happen it will do this:
clock_enable();
reset_deassert();
to take it out of reset again. Perhaps that's something you want to keep
doing in probe() in U-Boot. In that case maybe you want something like
this instead:
clock_enable();
mdelay(4);
reset_assert();
mdelay(4);
reset_deassert();
Thierry
signature.asc
Description: PGP signature
Re: [PATCH v6 04/18] video: tegra20: dc: pass DC id to internal devices
пт, 19 квіт. 2024 р. о 19:38 Thierry Reding пише:
>
> On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote:
> > Tegra SoC has 2 independent display controllers called DC_A and
> > DC_B, they are handled differently by internal video devices like
> > DSI and HDMI controllers so it is important for last to know
> > which display controller is used to properly set up registers.
> > To achieve this, a pipe field was added to pdata to pass display
> > controller id to internal Tegra SoC devices.
> >
> > Tested-by: Agneli # Toshiba AC100 T20
> > Tested-by: Robert Eckelmann # ASUS TF101
> > Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565
> > Tested-by: Ion Agorria # HTC One X
> > Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114
> > Signed-off-by: Svyatoslav Ryhel
> > ---
> > drivers/video/tegra20/tegra-dc.c | 6 ++
> > drivers/video/tegra20/tegra-dc.h | 3 +++
> > 2 files changed, 9 insertions(+)
> >
> > diff --git a/drivers/video/tegra20/tegra-dc.c
> > b/drivers/video/tegra20/tegra-dc.c
> > index 5d8874f323..0e94e665ef 100644
> > --- a/drivers/video/tegra20/tegra-dc.c
> > +++ b/drivers/video/tegra20/tegra-dc.c
> > @@ -45,6 +45,7 @@ struct tegra_lcd_priv {
> > unsigned pixel_clock; /* Pixel clock in Hz */
> > int dc_clk[2]; /* Contains clk and its parent */
> > bool rotation; /* 180 degree panel turn */
> > + bool pipe; /* DC controller: 0 for A, 1 for B */
>
> Bool is a poor choice, even if there's only two of them. This is a
> proper index, so it should be some sort of integer.
>
> Also, the device tree bindings for the display controller specify a
> "nvidia,head" property that can be used to identify these. If you add
> that to the U-Boot DT you can avoid looking up by name to map this
> value.
>
Thanks for pointing to this property. May we apply this patch set as is
since it is well tested and confirmed to work and I will prepare a follow
up patches to adjust device tree relations? Would what be ok?
> Thierry
Re: [PATCH v6 16/18] video: tegra20: dsi: remove pre-configuration
On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > From: Jonas Schwöbel > > Configuration for DC driver command mode is not required for > every panel. Removed. > > Tested-by: Ion Agorria # HTC One X > Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114 > Signed-off-by: Jonas Schwöbel > Signed-off-by: Svyatoslav Ryhel > --- > drivers/video/tegra20/tegra-dsi.c | 2 -- > 1 file changed, 2 deletions(-) Yeah, this seems completely unnecessary. Reviewed-by: Thierry Reding signature.asc Description: PGP signature
Re: [PATCH v6 04/18] video: tegra20: dc: pass DC id to internal devices
On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote:
> Tegra SoC has 2 independent display controllers called DC_A and
> DC_B, they are handled differently by internal video devices like
> DSI and HDMI controllers so it is important for last to know
> which display controller is used to properly set up registers.
> To achieve this, a pipe field was added to pdata to pass display
> controller id to internal Tegra SoC devices.
>
> Tested-by: Agneli # Toshiba AC100 T20
> Tested-by: Robert Eckelmann # ASUS TF101
> Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565
> Tested-by: Ion Agorria # HTC One X
> Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114
> Signed-off-by: Svyatoslav Ryhel
> ---
> drivers/video/tegra20/tegra-dc.c | 6 ++
> drivers/video/tegra20/tegra-dc.h | 3 +++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/video/tegra20/tegra-dc.c
> b/drivers/video/tegra20/tegra-dc.c
> index 5d8874f323..0e94e665ef 100644
> --- a/drivers/video/tegra20/tegra-dc.c
> +++ b/drivers/video/tegra20/tegra-dc.c
> @@ -45,6 +45,7 @@ struct tegra_lcd_priv {
> unsigned pixel_clock; /* Pixel clock in Hz */
> int dc_clk[2]; /* Contains clk and its parent */
> bool rotation; /* 180 degree panel turn */
> + bool pipe; /* DC controller: 0 for A, 1 for B */
Bool is a poor choice, even if there's only two of them. This is a
proper index, so it should be some sort of integer.
Also, the device tree bindings for the display controller specify a
"nvidia,head" property that can be used to identify these. If you add
that to the U-Boot DT you can avoid looking up by name to map this
value.
Thierry
signature.asc
Description: PGP signature
Re: [PATCH v6 06/18] video: tegra20: dc: add reset support
пт, 19 квіт. 2024 р. о 19:05 Thierry Reding пише:
>
> On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote:
> > Implement reset use to discard any changes which could have been
> > applied to DC before and can interfere with current configuration.
> >
> > Tested-by: Agneli # Toshiba AC100 T20
> > Tested-by: Robert Eckelmann # ASUS TF101
> > Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565
> > Tested-by: Ion Agorria # HTC One X
> > Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114
> > Signed-off-by: Svyatoslav Ryhel
> > ---
> > drivers/video/tegra20/tegra-dc.c | 17 +
> > 1 file changed, 17 insertions(+)
> >
> > diff --git a/drivers/video/tegra20/tegra-dc.c
> > b/drivers/video/tegra20/tegra-dc.c
> > index 56a23b3c97..35abb6fe46 100644
> > --- a/drivers/video/tegra20/tegra-dc.c
> > +++ b/drivers/video/tegra20/tegra-dc.c
> > @@ -10,7 +10,9 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > +#include
> > #include
> > #include
> > #include
> > @@ -342,6 +344,7 @@ static int tegra_lcd_probe(struct udevice *dev)
> > struct video_uc_plat *plat = dev_get_uclass_plat(dev);
> > struct video_priv *uc_priv = dev_get_uclass_priv(dev);
> > struct tegra_lcd_priv *priv = dev_get_priv(dev);
> > + struct reset_ctl reset_ctl;
> > int ret;
> >
> > /* Initialize the Tegra display controller */
> > @@ -349,6 +352,20 @@ static int tegra_lcd_probe(struct udevice *dev)
> > funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
> > #endif
> >
> > + ret = reset_get_by_name(dev, "dc", _ctl);
> > + if (ret) {
> > + log_err("reset_get_by_name() failed: %d\n", ret);
> > + return ret;
> > + }
> > +
> > + clock_disable(priv->dc_clk[0]);
> > +
> > + /* Reset everything set before */
> > + reset_assert(_ctl);
> > + mdelay(4);
> > + reset_deassert(_ctl);
> > + mdelay(4);
>
> Are you sure this works as intended? It's been a long time since I
> worked on this, but I seem to recall that most of these resets are
> actually synchronous, so in order for them to do what they're supposed
> to the clock needs to be kept running.
>
> The Linux driver certainly does this differently.
You have point, but I have tried to mostly adapt Linux tegra dc driver,
which has same logic in probe. Maybe I have not understood it properly.
Testing on T20, T30 and T114 passed without issues so far.
> Thierry
Re: [PATCH v6 10/18] video: tegra20: dc: enable backlight after DC is configured
On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > From: Jonas Schwöbel > > The goal of panel_set_backlight() is to enable backlight. Hence, > it should be called at the probe end. > > Signed-off-by: Jonas Schwöbel > Signed-off-by: Svyatoslav Ryhel > --- > drivers/video/tegra20/tegra-dc.c | 8 +--- > 1 file changed, 1 insertion(+), 7 deletions(-) Reviewed-by: Thierry Reding signature.asc Description: PGP signature
Re: [PATCH v6 01/18] video: tegra20: dc: diverge DC per-SOC
On Fri Apr 19, 2024 at 6:26 PM CEST, Thierry Reding wrote:
> On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote:
> [...]
> > diff --git a/arch/arm/include/asm/arch-tegra114/display.h
> > b/arch/arm/include/asm/arch-tegra114/display.h
> > new file mode 100644
> > index 00..9411525799
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-tegra114/display.h
> > @@ -0,0 +1,28 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * (C) Copyright 2010
> > + * NVIDIA Corporation
> > + */
> > +
> > +#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
> > +#define __ASM_ARCH_TEGRA_DISPLAY_H
> > +
> > +#include
> > +
> > +/* This holds information about a window which can be displayed */
> > +struct disp_ctl_win {
> > + enum win_color_depth_id fmt;/* Color depth/format */
> > + unsigned intbpp;/* Bits per pixel */
> > + phys_addr_t phys_addr; /* Physical address in memory */
> > + unsigned intx; /* Horizontal address offset (bytes) */
> > + unsigned inty; /* Veritical address offset (bytes) */
> > + unsigned intw; /* Width of source window */
> > + unsigned inth; /* Height of source window */
> > + unsigned intstride; /* Number of bytes per line */
> > + unsigned intout_x; /* Left edge of output window (col) */
> > + unsigned intout_y; /* Top edge of output window (row) */
> > + unsigned intout_w; /* Width of output window in pixels */
> > + unsigned intout_h; /* Height of output window in pixels */
> > +};
> > +
> > +#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
>
> One of the earlier patches in the series gets rid of this per-SoC header
> file in favor of a common one. Did this end up here by mistake? It
> doesn't seem to be used.
Nevermind, my MUA sorted these patches weirdly, so it appeared as if
this was later in the series than it actually was.
Thierry
signature.asc
Description: PGP signature
Re: [PATCH v6 02/18] video: tegra20: dc: fix image shift on rotated panels
On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > Subtracting 1 from x and y fixes image shifting on rotated > panels. > > Tested-by: Robert Eckelmann # ASUS Grouper E1565 > Signed-off-by: Svyatoslav Ryhel > --- > drivers/video/tegra20/tegra-dc.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Yeah, looks like we have that same fixup in Linux: Reviewed-by: Thierry Reding signature.asc Description: PGP signature
Re: [PATCH v6 17/18] video: tegra20: dsi: set correct fifo depth
On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > From: Jonas Schwöbel > > According to Thierry Reding's commit in the linux kernel > > 976cebc35bed0456a42bf96073a26f251d23b264 > "drm/tegra: dsi: Make FIFO depths host parameters" > > correct depth of the video FIFO is 1920 *words* no *bytes* > > Tested-by: Ion Agorria # HTC One X > Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114 > Signed-off-by: Jonas Schwöbel > Signed-off-by: Svyatoslav Ryhel > --- > drivers/video/tegra20/tegra-dsi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Thierry Reding signature.asc Description: PGP signature
Re: [PATCH v6 14/18] video: tegra20: dsi: add T114 support
On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > Existing Tegra DSI driver mostly fits T114 apart MIPI calibration > which on T114 has dedicated driver. To resolve this MIPI calibration > logic was split for pre-T114 and T114+ devices. > > Tested-by: Ion Agorria # HTC One X > Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114 > Signed-off-by: Svyatoslav Ryhel > --- > drivers/video/tegra20/tegra-dsi.c | 78 ++- > .../video/tegra20/tegra-dsi.h | 24 +- > 2 files changed, 96 insertions(+), 6 deletions(-) > rename arch/arm/include/asm/arch-tegra30/dsi.h => > drivers/video/tegra20/tegra-dsi.h (90%) Reviewed-by: Thierry Reding signature.asc Description: PGP signature
Re: [PATCH v6 01/18] video: tegra20: dc: diverge DC per-SOC
On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote:
[...]
> diff --git a/arch/arm/include/asm/arch-tegra114/display.h
> b/arch/arm/include/asm/arch-tegra114/display.h
> new file mode 100644
> index 00..9411525799
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-tegra114/display.h
> @@ -0,0 +1,28 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * (C) Copyright 2010
> + * NVIDIA Corporation
> + */
> +
> +#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
> +#define __ASM_ARCH_TEGRA_DISPLAY_H
> +
> +#include
> +
> +/* This holds information about a window which can be displayed */
> +struct disp_ctl_win {
> + enum win_color_depth_id fmt;/* Color depth/format */
> + unsigned intbpp;/* Bits per pixel */
> + phys_addr_t phys_addr; /* Physical address in memory */
> + unsigned intx; /* Horizontal address offset (bytes) */
> + unsigned inty; /* Veritical address offset (bytes) */
> + unsigned intw; /* Width of source window */
> + unsigned inth; /* Height of source window */
> + unsigned intstride; /* Number of bytes per line */
> + unsigned intout_x; /* Left edge of output window (col) */
> + unsigned intout_y; /* Top edge of output window (row) */
> + unsigned intout_w; /* Width of output window in pixels */
> + unsigned intout_h; /* Height of output window in pixels */
> +};
> +
> +#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
One of the earlier patches in the series gets rid of this per-SoC header
file in favor of a common one. Did this end up here by mistake? It
doesn't seem to be used.
> diff --git a/drivers/video/tegra20/tegra-dc.c
> b/drivers/video/tegra20/tegra-dc.c
> index f53ad46397..7605e77bc1 100644
> --- a/drivers/video/tegra20/tegra-dc.c
> +++ b/drivers/video/tegra20/tegra-dc.c
> @@ -3,7 +3,6 @@
> * Copyright (c) 2011 The Chromium OS Authors.
> */
>
> -#include
> #include
> #include
> #include
> @@ -23,10 +22,15 @@
> #include
> #include
> #include
> -#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +/* Holder of Tegra per-SOC DC differences */
> +struct tegra_dc_soc_info {
> + bool has_timer;
> + bool has_rgb;
> +};
> +
> /* Information about the display controller */
> struct tegra_lcd_priv {
> int width; /* width in pixels */
> @@ -35,6 +39,7 @@ struct tegra_lcd_priv {
> struct display_timing timing;
> struct udevice *panel;
> struct dc_ctlr *dc; /* Display controller regmap */
> + const struct tegra_dc_soc_info *soc;
> fdt_addr_t frame_buffer;/* Address of frame buffer */
> unsigned pixel_clock; /* Pixel clock in Hz */
> int dc_clk[2]; /* Contains clk and its parent */
> @@ -43,8 +48,8 @@ struct tegra_lcd_priv {
>
> enum {
> /* Maximum LCD size we support */
> - LCD_MAX_WIDTH = 1920,
> - LCD_MAX_HEIGHT = 1200,
> + LCD_MAX_WIDTH = 2560,
> + LCD_MAX_HEIGHT = 1600,
> LCD_MAX_LOG2_BPP= VIDEO_BPP16,
> };
>
> @@ -110,9 +115,9 @@ static void update_window(struct tegra_lcd_priv *priv,
> writel(val, >cmd.state_ctrl);
> }
>
> -static int update_display_mode(struct dc_disp_reg *disp,
> -struct tegra_lcd_priv *priv)
> +static int update_display_mode(struct tegra_lcd_priv *priv)
> {
> + struct dc_disp_reg *disp = >dc->disp;
> struct display_timing *dt = >timing;
> unsigned long val;
> unsigned long rate;
> @@ -128,14 +133,16 @@ static int update_display_mode(struct dc_disp_reg *disp,
> >front_porch);
> writel(dt->hactive.typ | (dt->vactive.typ << 16), >disp_active);
>
> - val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
> - val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
> - writel(val, >data_enable_opt);
> + if (priv->soc->has_rgb) {
> + val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
> + val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
> + writel(val, >data_enable_opt);
>
> - val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
> - val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
> - val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
> - writel(val, >disp_interface_ctrl);
> + val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
> + val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
> + val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
> + writel(val, >disp_interface_ctrl);
> + }
>
> /*
>* The pixel clock divider is in 7.1 format (where the bottom bit
> @@ -147,7 +154,8 @@ static int update_display_mode(struct dc_disp_reg *disp,
> div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2;
> debug("Display clock %lu, divider %lu\n", rate, div);
>
> -
[PATCH 5/5] board: phytec: Add SOM detection for AM6x
Add all functions to read each SOM option from the EEPROM
image and detect whether it's the correct product for this
image.
Signed-off-by: Daniel Schultz
---
board/phytec/common/Kconfig | 18 +++
board/phytec/common/Makefile| 1 +
board/phytec/common/am6_som_detection.c | 159
board/phytec/common/am6_som_detection.h | 36 ++
board/phytec/phycore_am62x/Kconfig | 4 +
board/phytec/phycore_am64x/Kconfig | 4 +
6 files changed, 222 insertions(+)
create mode 100644 board/phytec/common/am6_som_detection.c
create mode 100644 board/phytec/common/am6_som_detection.h
diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig
index 3b1c5aa0d02..1077f0f4b61 100644
--- a/board/phytec/common/Kconfig
+++ b/board/phytec/common/Kconfig
@@ -11,3 +11,21 @@ config PHYTEC_IMX8M_SOM_DETECTION
help
Support of I2C EEPROM based SoM detection. Supported
for PHYTEC i.MX8MM/i.MX8MP boards
+
+config PHYTEC_AM62_SOM_DETECTION
+ bool "Support SoM detection for AM62x PHYTEC platforms"
+ depends on (TARGET_PHYCORE_AM62X_A53 || TARGET_PHYCORE_AM62X_R5) && \
+ PHYTEC_SOM_DETECTION
+ default y
+ help
+ Support of I2C EEPROM based SoM detection. Supported
+ for PHYTEC AM62x boards.
+
+config PHYTEC_AM64_SOM_DETECTION
+ bool "Support SoM detection for AM64x PHYTEC platforms"
+ depends on (TARGET_PHYCORE_AM64X_A53 || TARGET_PHYCORE_AM64X_R5) && \
+ PHYTEC_SOM_DETECTION
+ default y
+ help
+ Support of I2C EEPROM based SoM detection. Supported
+ for PHYTEC AM64x boards.
diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile
index 35c81741306..3feb00fd1ec 100644
--- a/board/phytec/common/Makefile
+++ b/board/phytec/common/Makefile
@@ -8,4 +8,5 @@ obj- := __dummy__.o
endif
obj-y += phytec_som_detection.o
+obj-$(CONFIG_ARCH_K3) += am6_som_detection.o
obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o
diff --git a/board/phytec/common/am6_som_detection.c
b/board/phytec/common/am6_som_detection.c
new file mode 100644
index 000..2e9884dab44
--- /dev/null
+++ b/board/phytec/common/am6_som_detection.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Daniel Schultz
+ */
+
+#include
+
+#include "am6_som_detection.h"
+
+extern struct phytec_eeprom_data eeprom_data;
+
+#if IS_ENABLED(CONFIG_PHYTEC_AM62_SOM_DETECTION) || \
+ IS_ENABLED(CONFIG_PHYTEC_AM64_SOM_DETECTION)
+
+/* Check if the SoM is actually one of the following products:
+ * - phyCORE-AM62x
+ * - phyCORE-AM64x
+ *
+ * Returns 0 in case it's a known SoM. Otherwise, returns -1.
+ */
+int phytec_am6_detect(struct phytec_eeprom_data *data)
+{
+ char *opt;
+ u8 som;
+
+ if (!data)
+ data = _data;
+
+ /* We cannot do the check for early API revisions */
+ if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2)
+ return -1;
+
+ som = data->payload.data.data_api2.som_no;
+ debug("%s: som id: %u\n", __func__, som);
+
+ opt = phytec_get_opt(data);
+ if (!opt)
+ return -1;
+
+ if (som == PHYTEC_AM62X_SOM && soc_is_am62x())
+ return 0;
+
+ if (som == PHYTEC_AM64X_SOM && soc_is_am64x())
+ return 0;
+
+ return -1;
+}
+
+static u8 phytec_check_opt(struct phytec_eeprom_data *data, u8 option)
+{
+ char *opt;
+
+ if (!data)
+ data = _data;
+
+ if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2)
+ return PHYTEC_EEPROM_INVAL;
+
+ if (option > 8)
+ return PHYTEC_EEPROM_INVAL;
+
+ opt = phytec_get_opt(data);
+ if (opt)
+ return PHYTEC_GET_OPTION(opt[option]);
+ return PHYTEC_EEPROM_INVAL;
+}
+
+/*
+ * Reads LPDDR4 ram size from EEPROM.
+ *
+ * returns:
+ * - The size
+ * - PHYTEC_EEPROM_INVAL when the data is invalid.
+ */
+u8 __maybe_unused phytec_get_am62_ddr_size(struct phytec_eeprom_data *data)
+{
+ u8 ddr_id = phytec_check_opt(data, 3);
+
+ pr_debug("%s: ddr id: %u\n", __func__, ddr_id);
+ return ddr_id;
+}
+
+/*
+ * Reads SPI-NOR flash size and type from EEPROM.
+ *
+ * returns:
+ * - PHYTEC_EEPROM_VALUE_X if no SPI is poulated.
+ * - Otherwise a board depended code for the size.
+ * - PHYTEC_EEPROM_INVAL when the data is invalid.
+ */
+u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data)
+{
+ u8 spi = phytec_check_opt(data, 5);
+
+ pr_debug("%s: spi: %u\n", __func__, spi);
+ return spi;
+}
+
+/*
+ * Reads Ethernet phy information from EEPROM.
+ *
+ * returns:
+ * - 0x0 no ethernet phy is populated.
+ * - 0x1 if 10/100/1000 MBit Phy is populated.
+ * - PHYTEC_EEPROM_INVAL when the data is invalid.
+ */
+u8 __maybe_unused phytec_get_am62_eth(struct
[PATCH 4/5] board: phytec: common: Fix eepom is empty check
The ptr variable is currently defined as int and sizeof
returns the size of the eeprom data struct as Byte (32 in total).
In case the eeprom is empty, the check, if the eeprom is empty,
will most likely stop after 8 iterations because it will continue
with the stack which should contain some data. Therefore, the
init function will detect an empty EEPROM as API0 and return with
the valid flag set to True.
Fixes: dc22188cdc8 ("board: phytec: Add common PHYTEC SoM detection")
Signed-off-by: Daniel Schultz
---
board/phytec/common/phytec_som_detection.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/phytec/common/phytec_som_detection.c
b/board/phytec/common/phytec_som_detection.c
index 5a4cc9e8b02..78c173df20d 100644
--- a/board/phytec/common/phytec_som_detection.c
+++ b/board/phytec/common/phytec_som_detection.c
@@ -53,7 +53,7 @@ int phytec_eeprom_data_init(struct phytec_eeprom_data *data,
{
int ret, i;
unsigned int crc;
- int *ptr;
+ u8 *ptr;
const unsigned int payload_size = sizeof(struct phytec_eeprom_payload);
if (!data)
@@ -85,7 +85,7 @@ int phytec_eeprom_data_init(struct phytec_eeprom_data *data,
goto err;
}
- ptr = (int *)data;
+ ptr = (u8 *)data;
for (i = 0; i < payload_size; ++i)
if (ptr[i] != 0x0)
break;
--
2.25.1
[PATCH 3/5] board: phytec: check eeprom_data validity
From: Yannic Moog
For all of the functions that access the eeprom_data, make sure these
data are valid. Use the valid member of the phytec_eeprom_data struct.
This fixes a bug where only the API revision check guarded against
accessing rubbish. But if API revision was e.g. 6, eeprom setup failed
before, but phytec_get_imx8m_eth would still happily access the data.
Fixes: dc22188cdc8 ("board: phytec: Add common PHYTEC SoM detection")
Signed-off-by: Yannic Moog
Signed-off-by: Daniel Schultz
---
board/phytec/common/imx8m_som_detection.c | 11 +++
board/phytec/common/phytec_som_detection.c | 10 +++---
2 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/board/phytec/common/imx8m_som_detection.c
b/board/phytec/common/imx8m_som_detection.c
index 7571076a09e..ee34a5b9579 100644
--- a/board/phytec/common/imx8m_som_detection.c
+++ b/board/phytec/common/imx8m_som_detection.c
@@ -34,7 +34,7 @@ int __maybe_unused phytec_imx8m_detect(struct
phytec_eeprom_data *data)
data = _data;
/* We can not do the check for early API revisions */
- if (data->payload.api_rev < PHYTEC_API_REV2)
+ if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2)
return -1;
som = data->payload.data.data_api2.som_no;
@@ -75,6 +75,9 @@ u8 __maybe_unused phytec_get_imx8m_ddr_size(struct
phytec_eeprom_data *data)
if (!data)
data = _data;
+ if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2)
+ return PHYTEC_EEPROM_INVAL;
+
opt = phytec_get_opt(data);
if (opt)
ddr_id = PHYTEC_GET_OPTION(opt[2]);
@@ -99,7 +102,7 @@ u8 __maybe_unused phytec_get_imx8m_spi(struct
phytec_eeprom_data *data)
if (!data)
data = _data;
- if (data->payload.api_rev < PHYTEC_API_REV2)
+ if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2)
return PHYTEC_EEPROM_INVAL;
opt = phytec_get_opt(data);
@@ -126,7 +129,7 @@ u8 __maybe_unused phytec_get_imx8m_eth(struct
phytec_eeprom_data *data)
if (!data)
data = _data;
- if (data->payload.api_rev < PHYTEC_API_REV2)
+ if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2)
return PHYTEC_EEPROM_INVAL;
opt = phytec_get_opt(data);
@@ -154,7 +157,7 @@ u8 __maybe_unused phytec_get_imx8mp_rtc(struct
phytec_eeprom_data *data)
if (!data)
data = _data;
- if (data->payload.api_rev < PHYTEC_API_REV2)
+ if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2)
return PHYTEC_EEPROM_INVAL;
opt = phytec_get_opt(data);
diff --git a/board/phytec/common/phytec_som_detection.c
b/board/phytec/common/phytec_som_detection.c
index 7913764be0a..5a4cc9e8b02 100644
--- a/board/phytec/common/phytec_som_detection.c
+++ b/board/phytec/common/phytec_som_detection.c
@@ -128,7 +128,7 @@ void __maybe_unused phytec_print_som_info(struct
phytec_eeprom_data *data)
if (!data)
data = _data;
- if (data->payload.api_rev < PHYTEC_API_REV2)
+ if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2)
return;
api2 = >payload.data.data_api2;
@@ -190,6 +190,9 @@ char * __maybe_unused phytec_get_opt(struct
phytec_eeprom_data *data)
if (!data)
data = _data;
+ if (!data->valid)
+ return NULL;
+
if (data->payload.api_rev < PHYTEC_API_REV2)
opt = data->payload.data.data_api0.opt;
else
@@ -205,7 +208,7 @@ u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data
*data)
if (!data)
data = _data;
- if (data->payload.api_rev < PHYTEC_API_REV2)
+ if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2)
return PHYTEC_EEPROM_INVAL;
api2 = >payload.data.data_api2;
@@ -217,7 +220,8 @@ u8 __maybe_unused phytec_get_som_type(struct
phytec_eeprom_data *data)
{
if (!data)
data = _data;
- if (data->payload.api_rev < PHYTEC_API_REV2)
+
+ if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2)
return PHYTEC_EEPROM_INVAL;
return data->payload.data.data_api2.som_type;
--
2.25.1
[PATCH 2/5] board: phytec: introduce eeprom struct member 'valid'
From: Yannic Moog
Add a new nember to the eeprom_data that indicates whether the
associated data is valid or not. Make use of this new member in the
phytec_eeprom_data_init function by setting the valid value
appropriately.
Move the eeprom data to a new struct payload that holds
the payload of the eeprom.
Signed-off-by: Yannic Moog
Signed-off-by: Daniel Schultz
---
board/phytec/common/imx8m_som_detection.c | 10 ++--
board/phytec/common/phytec_som_detection.c | 56 --
board/phytec/common/phytec_som_detection.h | 11 +++--
3 files changed, 45 insertions(+), 32 deletions(-)
diff --git a/board/phytec/common/imx8m_som_detection.c
b/board/phytec/common/imx8m_som_detection.c
index 214b75db3b0..7571076a09e 100644
--- a/board/phytec/common/imx8m_som_detection.c
+++ b/board/phytec/common/imx8m_som_detection.c
@@ -34,10 +34,10 @@ int __maybe_unused phytec_imx8m_detect(struct
phytec_eeprom_data *data)
data = _data;
/* We can not do the check for early API revisions */
- if (data->api_rev < PHYTEC_API_REV2)
+ if (data->payload.api_rev < PHYTEC_API_REV2)
return -1;
- som = data->data.data_api2.som_no;
+ som = data->payload.data.data_api2.som_no;
debug("%s: som id: %u\n", __func__, som);
opt = phytec_get_opt(data);
@@ -99,7 +99,7 @@ u8 __maybe_unused phytec_get_imx8m_spi(struct
phytec_eeprom_data *data)
if (!data)
data = _data;
- if (data->api_rev < PHYTEC_API_REV2)
+ if (data->payload.api_rev < PHYTEC_API_REV2)
return PHYTEC_EEPROM_INVAL;
opt = phytec_get_opt(data);
@@ -126,7 +126,7 @@ u8 __maybe_unused phytec_get_imx8m_eth(struct
phytec_eeprom_data *data)
if (!data)
data = _data;
- if (data->api_rev < PHYTEC_API_REV2)
+ if (data->payload.api_rev < PHYTEC_API_REV2)
return PHYTEC_EEPROM_INVAL;
opt = phytec_get_opt(data);
@@ -154,7 +154,7 @@ u8 __maybe_unused phytec_get_imx8mp_rtc(struct
phytec_eeprom_data *data)
if (!data)
data = _data;
- if (data->api_rev < PHYTEC_API_REV2)
+ if (data->payload.api_rev < PHYTEC_API_REV2)
return PHYTEC_EEPROM_INVAL;
opt = phytec_get_opt(data);
diff --git a/board/phytec/common/phytec_som_detection.c
b/board/phytec/common/phytec_som_detection.c
index d167a77c25b..7913764be0a 100644
--- a/board/phytec/common/phytec_som_detection.c
+++ b/board/phytec/common/phytec_som_detection.c
@@ -54,6 +54,7 @@ int phytec_eeprom_data_init(struct phytec_eeprom_data *data,
int ret, i;
unsigned int crc;
int *ptr;
+ const unsigned int payload_size = sizeof(struct phytec_eeprom_payload);
if (!data)
data = _data;
@@ -64,14 +65,13 @@ int phytec_eeprom_data_init(struct phytec_eeprom_data *data,
ret = i2c_get_chip_for_busnum(bus_num, addr, 2, );
if (ret) {
pr_err("%s: i2c EEPROM not found: %i.\n", __func__, ret);
- return ret;
+ goto err;
}
- ret = dm_i2c_read(dev, 0, (uint8_t *)data,
- sizeof(struct phytec_eeprom_data));
+ ret = dm_i2c_read(dev, 0, (uint8_t *)data, payload_size);
if (ret) {
- pr_err("%s: Unable to read EEPROM data\n", __func__);
- return ret;
+ pr_err("%s: Unable to read EEPROM data: %i\n", __func__, ret);
+ goto err;
}
#else
i2c_set_bus_num(bus_num);
@@ -79,36 +79,44 @@ int phytec_eeprom_data_init(struct phytec_eeprom_data *data,
sizeof(struct phytec_eeprom_data));
#endif
- if (data->api_rev == 0xff) {
+ if (data->payload.api_rev == 0xff) {
pr_err("%s: EEPROM is not flashed. Prototype?\n", __func__);
- return -EINVAL;
+ ret = -EINVAL;
+ goto err;
}
ptr = (int *)data;
- for (i = 0; i < sizeof(struct phytec_eeprom_data); i++)
+ for (i = 0; i < payload_size; ++i)
if (ptr[i] != 0x0)
break;
- if (i == sizeof(struct phytec_eeprom_data)) {
+ if (i == payload_size) {
pr_err("%s: EEPROM data is all zero. Erased?\n", __func__);
- return -EINVAL;
+ ret = -EINVAL;
+ goto err;
}
/* We are done here for early revisions */
- if (data->api_rev <= PHYTEC_API_REV1)
+ if (data->payload.api_rev <= PHYTEC_API_REV1) {
+ data->valid = true;
return 0;
+ }
- crc = crc8(0, (const unsigned char *)data,
- sizeof(struct phytec_eeprom_data));
+ crc = crc8(0, (const unsigned char *)>payload, payload_size);
debug("%s: crc: %x\n", __func__, crc);
if (crc) {
- pr_err("%s: CRC mismatch. EEPROM data is not usable\n",
+
[PATCH 1/5] board: phytec: common: Generic "add extension" function
Add a generic function to apply overlays in our board code to not
implement the same logic in different PHYTEC products.
Signed-off-by: Daniel Schultz
---
board/phytec/common/phytec_som_detection.c | 33 ++
board/phytec/common/phytec_som_detection.h | 5
2 files changed, 38 insertions(+)
diff --git a/board/phytec/common/phytec_som_detection.c
b/board/phytec/common/phytec_som_detection.c
index a56e0f60d62..d167a77c25b 100644
--- a/board/phytec/common/phytec_som_detection.c
+++ b/board/phytec/common/phytec_som_detection.c
@@ -9,6 +9,8 @@
#include
#include
#include
+#include
+#include
#include "phytec_som_detection.h"
@@ -213,6 +215,28 @@ u8 __maybe_unused phytec_get_som_type(struct
phytec_eeprom_data *data)
return data->data.data_api2.som_type;
}
+#if IS_ENABLED(CONFIG_CMD_EXTENSION)
+struct extension *phytec_add_extension(const char *name, const char *overlay,
+ const char *other)
+{
+ struct extension *extension;
+
+ if (strlen(overlay) > sizeof(extension->overlay)) {
+ pr_err("Overlay name %s is longer than %lu.\n", overlay,
+ sizeof(extension->overlay));
+ return NULL;
+ }
+
+ extension = calloc(1, sizeof(struct extension));
+ snprintf(extension->name, sizeof(extension->name), name);
+ snprintf(extension->overlay, sizeof(extension->overlay), overlay);
+ snprintf(extension->other, sizeof(extension->other), other);
+ snprintf(extension->owner, sizeof(extension->owner), "PHYTEC");
+
+ return extension;
+}
+#endif /* IS_ENABLED(CONFIG_CMD_EXTENSION) */
+
#else
inline int phytec_eeprom_data_setup(struct phytec_eeprom_data *data,
@@ -253,4 +277,13 @@ u8 __maybe_unused phytec_get_som_type(struct
phytec_eeprom_data *data)
return PHYTEC_EEPROM_INVAL;
}
+#if IS_ENABLED(CONFIG_CMD_EXTENSION)
+inline struct extension *phytec_add_extension(const char *name,
+ const char *overlay,
+ const char *other)
+{
+ return NULL;
+}
+#endif /* IS_ENABLED(CONFIG_CMD_EXTENSION) */
+
#endif /* IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) */
diff --git a/board/phytec/common/phytec_som_detection.h
b/board/phytec/common/phytec_som_detection.h
index 7edbfa3ca5c..ea99a687fee 100644
--- a/board/phytec/common/phytec_som_detection.h
+++ b/board/phytec/common/phytec_som_detection.h
@@ -76,4 +76,9 @@ char * __maybe_unused phytec_get_opt(struct
phytec_eeprom_data *data);
u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data);
u8 __maybe_unused phytec_get_som_type(struct phytec_eeprom_data *data);
+#if IS_ENABLED(CONFIG_CMD_EXTENSION)
+struct extension *phytec_add_extension(const char *name, const char *overlay,
+ const char *other);
+#endif /* IS_ENABLED(CONFIG_CMD_EXTENSION) */
+
#endif /* _PHYTEC_SOM_DETECTION_H */
--
2.25.1
[PATCH 0/5] Update PHYTEC SOM Detection
This patch series extends PHYTEC's SOM detection by minor fixes, a generic helper function and a new valid flag. Moreover, it adds a module to provide access to the SOM detection for our TI AM6 products. Daniel Schultz (3): board: phytec: common: Generic "add extension" function board: phytec: common: Fix eepom is empty check board: phytec: Add SOM detection for AM6x Yannic Moog (2): board: phytec: introduce eeprom struct member 'valid' board: phytec: check eeprom_data validity board/phytec/common/Kconfig| 18 +++ board/phytec/common/Makefile | 1 + board/phytec/common/am6_som_detection.c| 159 + board/phytec/common/am6_som_detection.h| 36 + board/phytec/common/imx8m_som_detection.c | 13 +- board/phytec/common/phytec_som_detection.c | 97 + board/phytec/common/phytec_som_detection.h | 16 ++- board/phytec/phycore_am62x/Kconfig | 4 + board/phytec/phycore_am64x/Kconfig | 4 + 9 files changed, 314 insertions(+), 34 deletions(-) create mode 100644 board/phytec/common/am6_som_detection.c create mode 100644 board/phytec/common/am6_som_detection.h -- 2.25.1
Re: [PATCH v6 13/18] video: tegra20: add MIPI calibration driver
On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > Dedicated MIPI calibration driver is used on T114 and newer. Before > T114 MIPI calibration registers were part of VI and CSI. > > Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114 > Signed-off-by: Svyatoslav Ryhel > --- > drivers/video/tegra20/Makefile | 2 +- > drivers/video/tegra20/tegra-mipi.c | 188 + > 2 files changed, 189 insertions(+), 1 deletion(-) > create mode 100644 drivers/video/tegra20/tegra-mipi.c This looks like an adequate copy of what we have in the Linux kernel. It's slightly suboptimal because most of the register values are hard- coded for Tegra114, but I guess that can always be improved later on. Reviewed-by: Thierry Reding signature.asc Description: PGP signature
Re: [PATCH v6 06/18] video: tegra20: dc: add reset support
On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote:
> Implement reset use to discard any changes which could have been
> applied to DC before and can interfere with current configuration.
>
> Tested-by: Agneli # Toshiba AC100 T20
> Tested-by: Robert Eckelmann # ASUS TF101
> Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565
> Tested-by: Ion Agorria # HTC One X
> Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114
> Signed-off-by: Svyatoslav Ryhel
> ---
> drivers/video/tegra20/tegra-dc.c | 17 +
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/video/tegra20/tegra-dc.c
> b/drivers/video/tegra20/tegra-dc.c
> index 56a23b3c97..35abb6fe46 100644
> --- a/drivers/video/tegra20/tegra-dc.c
> +++ b/drivers/video/tegra20/tegra-dc.c
> @@ -10,7 +10,9 @@
> #include
> #include
> #include
> +#include
> #include
> +#include
> #include
> #include
> #include
> @@ -342,6 +344,7 @@ static int tegra_lcd_probe(struct udevice *dev)
> struct video_uc_plat *plat = dev_get_uclass_plat(dev);
> struct video_priv *uc_priv = dev_get_uclass_priv(dev);
> struct tegra_lcd_priv *priv = dev_get_priv(dev);
> + struct reset_ctl reset_ctl;
> int ret;
>
> /* Initialize the Tegra display controller */
> @@ -349,6 +352,20 @@ static int tegra_lcd_probe(struct udevice *dev)
> funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
> #endif
>
> + ret = reset_get_by_name(dev, "dc", _ctl);
> + if (ret) {
> + log_err("reset_get_by_name() failed: %d\n", ret);
> + return ret;
> + }
> +
> + clock_disable(priv->dc_clk[0]);
> +
> + /* Reset everything set before */
> + reset_assert(_ctl);
> + mdelay(4);
> + reset_deassert(_ctl);
> + mdelay(4);
Are you sure this works as intended? It's been a long time since I
worked on this, but I seem to recall that most of these resets are
actually synchronous, so in order for them to do what they're supposed
to the clock needs to be kept running.
The Linux driver certainly does this differently.
Thierry
signature.asc
Description: PGP signature
Re: [PATCH v6 18/18] video: tegra20: dsi: use set_backlight for backlight only
On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > From: Jonas Schwöbel > > Shift the backlight set further to prevent visual glitches on > panel init. > > Signed-off-by: Jonas Schwöbel > Signed-off-by: Svyatoslav Ryhel > --- > drivers/video/tegra20/tegra-dsi.c | 10 -- > 1 file changed, 4 insertions(+), 6 deletions(-) I vaguely recall that some devices may have had the panel and the backlight hooked up to the same regulator or enable GPIO, so calling panel_set_backlight() too late may cause the DSI panel to malfunction. That said, I'm not familiar with panel_set_backlight(), so perhaps it always only sets the brightness and the power may already be on earlier? Ah... nevermind... I see that panel_enable_backlight() is called prior to panel_set_backlight(), so this looks like it should be fine. Reviewed-by: Thierry Reding signature.asc Description: PGP signature
Re: [PATCH v6 03/18] video: tegra20: consolidate DC header
On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > Consolidate HD headers and place the result into video/tegra20 Was this supposed to be "DC" headers like in the subject? Other than that this makes sense, so: Reviewed-by: Thierry Reding signature.asc Description: PGP signature
[PATCH v3 3/3] imx8mm_venice_defconfig: Enable PCIe/NVMe support
Enable PCIe/NVMe support. Also, enable the reset driver which is a prerequisite for PCIe support. Signed-off-by: Tim Harvey --- v3: no changes v2: no changes --- configs/imx8mm_venice_defconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 517b70b69477..0f97b4b84243 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-venice-gw71xx-0x" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_IMX8MM_VENICE=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y @@ -20,6 +21,7 @@ CONFIG_SPL_STACK=0x92 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x3f8000 CONFIG_SYS_LOAD_ADDR=0x4820 +CONFIG_PCI=y CONFIG_SYS_MEMTEST_START=0x4000 CONFIG_SYS_MEMTEST_END=0x8000 CONFIG_FIT=y @@ -60,6 +62,7 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP6=y @@ -120,6 +123,9 @@ CONFIG_PHY_GIGE=y CONFIG_FEC_MXC=y CONFIG_KSZ9477=y CONFIG_MII=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_IMX=y +CONFIG_PHY_IMX8M_PCIE=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y -- 2.25.1
[PATCH v3 2/3] pci: dw_imx: add support for IMX8MM
Add support for the IMX8MM SoC by adding driver data with the compatible
string of the GPR controller.
Reviewed-by: Marek Vasut
Signed-off-by: Tim Harvey
---
v3: collected tags
v2: do not cache chip info in priv per Marek's suggestion
---
drivers/pci/pcie_dw_imx.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pcie_dw_imx.c b/drivers/pci/pcie_dw_imx.c
index a2ee228224b5..fdb463710ba1 100644
--- a/drivers/pci/pcie_dw_imx.c
+++ b/drivers/pci/pcie_dw_imx.c
@@ -56,6 +56,18 @@ struct pcie_dw_imx {
struct udevice *vpcie;
};
+struct pcie_chip_info {
+ const char *gpr;
+};
+
+static const struct pcie_chip_info imx8mm_chip_info = {
+ .gpr = "fsl,imx8mm-iomuxc-gpr",
+};
+
+static const struct pcie_chip_info imx8mp_chip_info = {
+ .gpr = "fsl,imx8mp-iomuxc-gpr",
+};
+
static void pcie_dw_configure(struct pcie_dw_imx *priv, u32 cap_speed)
{
dw_pcie_dbi_write_enable(>dw, true);
@@ -242,6 +254,7 @@ static int pcie_dw_imx_remove(struct udevice *dev)
static int pcie_dw_imx_of_to_plat(struct udevice *dev)
{
+ struct pcie_chip_info *info = (void *)dev_get_driver_data(dev);
struct pcie_dw_imx *priv = dev_get_priv(dev);
ofnode gpr;
int ret;
@@ -287,7 +300,7 @@ static int pcie_dw_imx_of_to_plat(struct udevice *dev)
goto err_phy;
}
- gpr = ofnode_by_compatible(ofnode_null(), "fsl,imx8mp-iomuxc-gpr");
+ gpr = ofnode_by_compatible(ofnode_null(), info->gpr);
if (ofnode_equal(gpr, ofnode_null())) {
dev_err(dev, "unable to find GPR node\n");
ret = -ENODEV;
@@ -322,7 +335,8 @@ static const struct dm_pci_ops pcie_dw_imx_ops = {
};
static const struct udevice_id pcie_dw_imx_ids[] = {
- { .compatible = "fsl,imx8mp-pcie" },
+ { .compatible = "fsl,imx8mm-pcie", .data = (ulong)_chip_info, },
+ { .compatible = "fsl,imx8mp-pcie", .data = (ulong)_chip_info, },
{ }
};
--
2.25.1
[PATCH v3 1/3] clk: imx8mm: Add support for PCIe clocks
Add support for PCIe clocks required to enable PCIe support on
iMX8MM SoC.
Signed-off-by: Tim Harvey
---
v3: wrap pcie clk config around IS_ENABLED to avoid SPL growth as
suggested by Marek
---
drivers/clk/imx/clk-imx8mm.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index b5c253e49663..1a00dd1d287b 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -66,6 +66,17 @@ static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m",
"sys_pll1_160m", "sys_
static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m",
"sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
"video_pll1_out", "audio_pll2_out",
"sys_pll1_133m", };
+#if CONFIG_IS_ENABLED(PCIE_DW_IMX)
+static const char *imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m",
"sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m",
+ "sys_pll1_800m",
"sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", };
+
+static const char *imx8mm_pcie1_phy_sels[] = {"clock-osc-24m",
"sys_pll2_100m", "sys_pll2_500m", "clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4",
"sys_pll1_400m", };
+
+static const char *imx8mm_pcie1_aux_sels[] = {"clock-osc-24m",
"sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out",
+ "sys_pll2_100m", "sys_pll1_80m",
"sys_pll1_160m", "sys_pll1_200m", };
+#endif
+
#ifndef CONFIG_SPL_BUILD
static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
"sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll1_out", };
@@ -256,6 +267,17 @@ static int imx8mm_clk_probe(struct udevice *dev)
imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base +
0x8b80));
/* IP */
+#if CONFIG_IS_ENABLED(PCIE_DW_IMX)
+ clk_dm(IMX8MM_CLK_PCIE1_CTRL,
+ imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels,
+ base + 0xa300));
+ clk_dm(IMX8MM_CLK_PCIE1_PHY,
+ imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels,
+ base + 0xa380));
+ clk_dm(IMX8MM_CLK_PCIE1_AUX,
+ imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels,
+ base + 0xa400));
+#endif
clk_dm(IMX8MM_CLK_USDHC1,
imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels,
base + 0xac00));
@@ -339,6 +361,11 @@ static int imx8mm_clk_probe(struct udevice *dev)
imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
#endif
+#if CONFIG_IS_ENABLED(PCIE_DW_IMX)
+ clk_dm(IMX8MM_CLK_PCIE1_ROOT,
+ imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0));
+#endif
+
#if CONFIG_IS_ENABLED(DM_SPI)
clk_dm(IMX8MM_CLK_ECSPI1,
imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base +
0xb280));
--
2.25.1
Re: [PATCH v4 0/7] Add SE HMBSC board support
Hi Caleb, On Fri, 12 Apr 2024 at 02:54, Sumit Garg wrote: > > SE HMIBSC board is based on Qcom APQ8016 SoC. One of the major > difference from db410c is serial port where HMIBSC board uses UART1 as > the debug console with an RS232 port, patch #2 - #5 adds corresponding > driver support. > > Patch #6 adds main HMIBSC board specific bits, features: > - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306) > - 2GiB RAM > - 64GiB eMMC, SD slot > - WiFi and Bluetooth > - 2x Host, 1x Device USB port > - HDMI > - Discrete TPM2 chip over SPI > > Features enabled in U-Boot: > - RAUC updates (refer [2] for more details) > - Environment protection > - USB based ethernet adaptors > > Feedback is very much welcome. > > Changes in v4: > - Rebased on top of qcom-main [4]. > - Split out board DTS patch as #6. > - Convert to text based environment as hmibsc.env. > - MMC regression has been reported for qcom-main branch here [5]. > - Collected further review tag. I haven't seen any further comments on this series. Can you help pick it up? -Sumit > > Changes in v3: > - Rebased on top of qcom-next [1]. > - Collected some review tags. > - Incorporated misc. comments from Caleb and Stephen. > - Split patch#4 as requested. > - Linux HMIBSC board DTS has already been reviewed here [3], I have > incorporated that for U-Boot too. > > Changes in v2: > - Rebased on top on qcom-next [1]. > - Added patch#1 as a fix for generic qcom board support. > - Added patch#4 to enable driving GPIO pins based on pinctrl > configuration. This replaces the custom GPIO configuration. > - Added proper DTS file for HMIBSC board based on Linux DT pattern. > - Merged board support patches into a single patch#5. > > [1] > https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-next?ref_type=heads > [2] https://rauc.readthedocs.io/en/latest/ > [3] > https://lore.kernel.org/linux-kernel/20240403043416.3800259-4-sumit.g...@linaro.org/ > [4] > https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-main/?ref_type=heads > [5] > https://lore.kernel.org/all/cafa6wyo+3vroudfuvh390taviqx8pmqroqdtsn0yu6bd5yy...@mail.gmail.com/ > > Sumit Garg (7): > qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default > apq8016: Add support for UART1 clocks and pinmux > serial_msm: Enable RS232 flow control > pinctrl: qcom: Add support for driving GPIO pins output > pinctrl: qcom: apq8016: Add GPIO pinctrl function > arm: dts: qcom: Add Schneider HMIBSC board dts > board: add support for Schneider HMIBSC board > > arch/arm/Kconfig | 2 +- > arch/arm/dts/apq8016-schneider-hmibsc.dts | 491 ++ > board/schneider/hmibsc/MAINTAINERS| 6 + > board/schneider/hmibsc/hmibsc.env | 40 ++ > configs/hmibsc_defconfig | 87 > doc/board/index.rst | 1 + > doc/board/schneider/hmibsc.rst| 45 ++ > doc/board/schneider/index.rst | 9 + > drivers/clk/qcom/clock-apq8016.c | 38 +- > drivers/pinctrl/qcom/pinctrl-apq8016.c| 2 + > drivers/pinctrl/qcom/pinctrl-qcom.c | 25 +- > drivers/serial/serial_msm.c | 24 +- > include/configs/hmibsc.h | 16 + > 13 files changed, 760 insertions(+), 26 deletions(-) > create mode 100644 arch/arm/dts/apq8016-schneider-hmibsc.dts > create mode 100644 board/schneider/hmibsc/MAINTAINERS > create mode 100644 board/schneider/hmibsc/hmibsc.env > create mode 100644 configs/hmibsc_defconfig > create mode 100644 doc/board/schneider/hmibsc.rst > create mode 100644 doc/board/schneider/index.rst > create mode 100644 include/configs/hmibsc.h > > -- > 2.34.1 >
Re: [PATCH] ARM: imx: Enable kaslrseed command on DH i.MX8M Plus DHCOM
On Thu, Apr 18, 2024 at 11:42 AM Marek Vasut wrote:
>
> On 4/18/24 8:02 PM, Fabio Estevam wrote:
> > Hi Tim,
> >
> > On Thu, Apr 18, 2024 at 2:54 PM Tim Harvey wrote:
> >
> >> Fabio, if you enable CONFIG_DM_RNG on an imx8m{m,p}_evk do you get the
> >> following in the SPL?
> >> Couldn't bind rng driver (-96)
> >> SEC0: RNG instantiated
> >>
> >> sec_init failed!
> >
> > Yes, if I add CONFIG_DM_RNG=y to imx8mm_evk_defconfig I get:
> >
> > U-Boot SPL 2024.04-00793-g3434b88d2c2f-dirty (Apr 18 2024 - 14:58:57 -0300)
> > No pmic
> > Couldn't bind rng driver (-96)
> > SEC0: RNG instantiated
> >
> > sec_init failed!
>
> Interesting. Which TFA blob version do you use ? I used the mainline
> 2.10 for my tests.
Marek,
Were you able to reproduce this as well with the board you enabled
DM_RNG for? If it does work fine what dtb were you using... perhaps
there is something in its u-boot.dtsi that we need?
The error -EPFNOSUPPORT is interesting and helps point to the only
place it can be where the comment says the strange errno is to make
this easier to find:
https://elixir.bootlin.com/u-boot/latest/source/drivers/core/uclass.c#L70:
if (!uc_drv) {
debug("Cannot find uclass for id %d: please add the
UCLASS_DRIVER() declaration for this UCLASS_... id\n",
id);
/*
* Use a strange error to make this case easier to find. When
* a uclass is not available it can prevent driver model from
* starting up and this failure is otherwise hard to debug.
*/
return -EPFNOSUPPORT;
}
I'm not very familiar with the dm driver binding - does the
U-BOOT_DRIVER usage in drivers/crypto/fsl/rng.c need to be refactored
to use UCLASS_DRIVER for it to be usable in both SPL and U-Boot?
Honestly I don't know why we need DM_RNG in SPL anyway and we could
just add support for disabling it there to avoid unwanted bloat.
Tim
Re: [PATCH v4 2/3] dt-bindings: drop generic headers
On 18/04/2024 20:39, Caleb Connolly wrote: Drop all the subsystem headers that are compatible with the headers in dts/upstream. Signed-off-by: Caleb Connolly --- include/dt-bindings/ata/ahci.h | 20 - include/dt-bindings/gpio/gpio.h| 42 -- include/dt-bindings/input/gpio-keys.h | 13 - include/dt-bindings/input/input.h | 17 - include/dt-bindings/input/linux-event-codes.h | 806 - include/dt-bindings/interrupt-controller/irq.h | 19 - include/dt-bindings/leds/common.h | 106 include/dt-bindings/mux/mux.h | 17 - include/dt-bindings/phy/phy.h | 26 - include/dt-bindings/pwm/pwm.h | 14 - include/dt-bindings/spmi/spmi.h| 10 - include/dt-bindings/thermal/thermal.h | 15 - include/dt-bindings/usb/pd.h | 88 --- 13 files changed, 1193 deletions(-) Reviewed-by: Neil Armstrong
Re: [PATCH 3/3] qcom_defconfig: set SYS_INIT_SP_BSS_OFFSET
On 18/04/2024 19:24, Caleb Connolly wrote: Give us lots of room for the appended FDT. Signed-off-by: Caleb Connolly --- configs/qcom_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 218a9a769682..7b589f0bf7a7 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -3,8 +3,9 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_SNAPDRAGON=y CONFIG_DEFAULT_DEVICE_TREE="qcom/sdm845-db845c" CONFIG_SYS_LOAD_ADDR=0x0 +CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 CONFIG_BUTTON_CMD=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTSTD_FULL=y Reviewed-by: Neil Armstrong
Re: [PATCH 2/3] arm: dts: drop qcom dts files
On 18/04/2024 19:24, Caleb Connolly wrote: These files are all identical (or older) than those in dts/upstream. Drop them as we now use upstream DTS files with OF_UPSTREAM. Signed-off-by: Caleb Connolly --- arch/arm/dts/apq8016-sbc.dts| 729 arch/arm/dts/apq8096-db820c.dts | 1137 -- arch/arm/dts/msm8916-pm8916.dtsi| 157 - arch/arm/dts/msm8916.dtsi | 2702 - arch/arm/dts/msm8996.dtsi | 3884 -- arch/arm/dts/pm8916.dtsi| 178 - arch/arm/dts/pm8994.dtsi| 152 - arch/arm/dts/pm8998.dtsi| 130 - arch/arm/dts/pmi8994.dtsi | 65 - arch/arm/dts/pmi8998.dtsi | 98 - arch/arm/dts/pms405.dtsi| 149 - arch/arm/dts/qcs404-evb-4000.dts| 96 - arch/arm/dts/qcs404-evb.dtsi| 389 -- arch/arm/dts/qcs404.dtsi| 1829 - arch/arm/dts/sdm845-db845c.dts | 1190 -- arch/arm/dts/sdm845-samsung-starqltechn.dts | 460 --- arch/arm/dts/sdm845-wcd9340.dtsi| 86 - arch/arm/dts/sdm845.dtsi| 5752 --- 18 files changed, 19183 deletions(-) Reviewed-by: Neil Armstrong
Re: [PATCH 1/3] mach-snapdragon: use OF_UPSTREAM
On 18/04/2024 19:24, Caleb Connolly wrote: Switch to using upstream DT from dts/upstream. Signed-off-by: Caleb Connolly --- MAINTAINERS | 4 arch/arm/Kconfig | 1 + configs/dragonboard410c_defconfig | 2 +- configs/dragonboard820c_defconfig | 2 +- configs/qcom_defconfig| 2 +- 5 files changed, 4 insertions(+), 7 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index c0d2b5138fca..d0a4a28b401d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -605,12 +605,8 @@ M: Neil Armstrong R:Sumit Garg L:u-boot-q...@groups.io S:Maintained T:git https://source.denx.de/u-boot/custodians/u-boot-snapdragon.git -F: arch/arm/dts/msm8*.dtsi -F: arch/arm/dts/pm8???.dtsi -F: arch/arm/dts/pms405.dtsi -F: arch/arm/dts/sdm845.dtsi F:drivers/*/*/pm8???-* F:drivers/gpio/msm_gpio.c F:drivers/mmc/msm_sdhci.c F:drivers/phy/msm8916-usbh-phy.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 23ee25269a24..2931c82eb11f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1088,8 +1088,9 @@ config ARCH_SNAPDRAGON select BOARD_LATE_INIT select OF_BOARD select SAVE_PREV_BL_FDT_ADDR select LINUX_KERNEL_IMAGE_HEADER + imply OF_UPSTREAM imply CMD_DM config ARCH_SOCFPGA bool "Altera SOCFPGA family" diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index 260a8349d3b2..9ef04fd45546 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -8,9 +8,9 @@ CONFIG_SYS_MALLOC_LEN=0x802000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 -CONFIG_DEFAULT_DEVICE_TREE="apq8016-sbc" +CONFIG_DEFAULT_DEVICE_TREE="qcom/apq8016-sbc" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C" CONFIG_SYS_LOAD_ADDR=0x8008 CONFIG_REMAKE_ELF=y diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig index ebc80eb2a464..f6b2cb09ba31 100644 --- a/configs/dragonboard820c_defconfig +++ b/configs/dragonboard820c_defconfig @@ -6,9 +6,9 @@ CONFIG_TEXT_BASE=0x8008 CONFIG_SYS_MALLOC_LEN=0x804000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0 CONFIG_ENV_SIZE=0x4000 -CONFIG_DEFAULT_DEVICE_TREE="apq8096-db820c" +CONFIG_DEFAULT_DEVICE_TREE="qcom/apq8096-db820c" CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 820C" CONFIG_SYS_LOAD_ADDR=0x8008 CONFIG_DISTRO_DEFAULTS=y CONFIG_USE_BOOTARGS=y diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index ee3ed89cbc8a..218a9a769682 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -1,9 +1,9 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_SNAPDRAGON=y -CONFIG_DEFAULT_DEVICE_TREE="sdm845-db845c" +CONFIG_DEFAULT_DEVICE_TREE="qcom/sdm845-db845c" CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_BUTTON_CMD=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y Reviewed-by: Neil Armstrong
Re: [PATCH v2 0/7] Tegra panel improvements
On Fri, Apr 19, 2024 at 02:29:20PM +0300, Svyatoslav Ryhel wrote: > Hello Tom! This patch set is hanging in patchwork for 3 month > without any comments. If no one has anything to say, may you > pick it into master? There's a number of video related patches outstanding currently, Anatolij will you be able to put together a PR soon? Thanks. > > Best regards, > Svyatoslav R. > > ср, 31 січ. 2024 р. о 08:57 Svyatoslav Ryhel пише: > > > > The current patch set improves the logic of existing panels and > > bridge used by Tegra 3 devices and brings support for additional > > DSI panels used by Tegra 4 devices. > > > > New and existing drivers are fully reusable, contain no device > > specific parts, and are written according to existing datasheets. > > > > --- > > Changes from v1: > > - improved ssd2825 code style > > - added TC358768 RGB to DSI bridge bringup commit (used by TF700T) > > - added Parade DP501 transmitter bringup (used by Lenovo Ideapad Yoga 11) > > --- > > > > Anton Bambura (1): > > video: panel: add Samsung LTL106HL02 MIPI DSI panel driver > > > > Jonas Schwöbel (1): > > video: bridge: add basic support for the Parade DP501 transmitter > > > > Svyatoslav Ryhel (5): > > video: panel: add LG LG070WX3 MIPI DSI panel driver > > video: bridge: add Toshiba TC358768 RGB to DSI bridge support > > video: endeavoru-panel: shift the init sequence by one step earlier > > video: bridge: ssd2825: shift the init sequence by one step earlier > > video: renesas: shift the init sequence by one step earlier > > > > drivers/video/Kconfig | 17 + > > drivers/video/Makefile | 2 + > > drivers/video/bridge/Kconfig | 19 + > > drivers/video/bridge/Makefile | 2 + > > drivers/video/bridge/dp501.c | 579 + > > drivers/video/bridge/ssd2825.c | 86 +-- > > drivers/video/bridge/tc358768.c| 985 + > > drivers/video/endeavoru-panel.c| 128 ++-- > > drivers/video/lg-ld070wx3.c| 186 ++ > > drivers/video/renesas-r61307.c | 93 +-- > > drivers/video/renesas-r69328.c | 81 +-- > > drivers/video/samsung-ltl106hl02.c | 157 + > > 12 files changed, 2155 insertions(+), 180 deletions(-) > > create mode 100644 drivers/video/bridge/dp501.c > > create mode 100644 drivers/video/bridge/tc358768.c > > create mode 100644 drivers/video/lg-ld070wx3.c > > create mode 100644 drivers/video/samsung-ltl106hl02.c > > > > -- > > 2.40.1 > > -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/1] efi_loader: superfluous efi_restore_gd after EFI_CALL
On Fri, 19 Apr 2024 at 12:59, Heinrich Schuchardt wrote: > > EFI_CALL() invokes __efi_entry_check() which executes set_gd(efi_gd). > There is no need to execute set_gd(efi_gd) again via efi_restore_gd(). > > Signed-off-by: Heinrich Schuchardt > --- > cmd/bootefi.c | 1 - > cmd/efidebug.c | 2 -- > lib/efi_loader/efi_helper.c | 2 -- > 3 files changed, 5 deletions(-) > > diff --git a/cmd/bootefi.c b/cmd/bootefi.c > index 578dbb19a7e..c1454ffb948 100644 > --- a/cmd/bootefi.c > +++ b/cmd/bootefi.c > @@ -107,7 +107,6 @@ static int do_efi_selftest(void) > > /* Execute the test */ > ret = EFI_CALL(efi_selftest(_obj->header, )); > - efi_restore_gd(); > free(loaded_image_info->load_options); > efi_free_pool(test_device_path); > efi_free_pool(test_image_path); > diff --git a/cmd/efidebug.c b/cmd/efidebug.c > index 32c64711b6c..30def6b6831 100644 > --- a/cmd/efidebug.c > +++ b/cmd/efidebug.c > @@ -1466,8 +1466,6 @@ static __maybe_unused int do_efi_test_bootmgr(struct > cmd_tbl *cmdtp, int flag, > if (ret && exit_data) > efi_free_pool(exit_data); > > - efi_restore_gd(); > - > free(load_options); > return CMD_RET_SUCCESS; > } > diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c > index 58761fae784..88c3586787e 100644 > --- a/lib/efi_loader/efi_helper.c > +++ b/lib/efi_loader/efi_helper.c > @@ -544,8 +544,6 @@ efi_status_t do_bootefi_exec(efi_handle_t handle, void > *load_options) > } > } > > - efi_restore_gd(); > - > out: > free(load_options); > > -- > 2.43.0 > Reviewed-by: Ilias Apalodimas
Re: [PATCH 2/3] mach-ipq40xx: import GPIO header from mach-snapgradon
On Thu, Apr 18, 2024 at 1:02 PM Caleb Connolly
wrote:
>
> Hi Robert,
>
> On 18/04/2024 10:14, Robert Marko wrote:
> > Pinctrl driver was refactored and moved, but the required header that
> > it depends on was not included.
>
> Thanks for these patches!
>
> I'm a bit worried about duplicating this header file, we could probably
> move it to the main include directory instead?
Hi Caleb,
That works for me as its a straight copy from mach-snapdragon.
>
> Alternatively, do you think it would be sensible to combine
> mach-snapdragon with mach-ipq40xx ?
>
> I received some patches a while ago from some Qualcomm engineers trying
> to introduce support for newer IPQ SoCs, where they also seem to want to
> build U-Boot as 32-bit (something I guess ipq40xx may also do?).
If it's possible, I would prefer to keep mach-ipq40xx separate and
probably convert it
to mach-ipq later since I would also love to see some newer SoC-s as well.
While Snapdragon and IPQ40xx are similar currently they will diverge for sure.
I dont understand why Qualcomm still insists on building the stock
U-Boot in ARMv7 32-bit
compatibility mode for all of the Cortex-A53 based IPQ807x/60xx/50xx and so on.
Regards,
Robert
>
> I'm easy either way, just want to get a better understanding of this.
>
> Kind regards,
> >
> > Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx")
> > Signed-off-by: Robert Marko
> > ---
> > arch/arm/mach-ipq40xx/include/mach/gpio.h | 37 +++
> > 1 file changed, 31 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/arm/mach-ipq40xx/include/mach/gpio.h
> > b/arch/arm/mach-ipq40xx/include/mach/gpio.h
> > index a45747c0fe..53c6ae0649 100644
> > --- a/arch/arm/mach-ipq40xx/include/mach/gpio.h
> > +++ b/arch/arm/mach-ipq40xx/include/mach/gpio.h
> > @@ -1,10 +1,35 @@
> > /* SPDX-License-Identifier: GPL-2.0+ */
> > /*
> > - * Empty gpio.h
> > + * Qualcomm common pin control data.
> > *
> > - * This file must stay as arch/arm/include/asm/gpio.h requires it.
> > - *
> > - * Copyright (c) 2019 Sartura Ltd.
> > - *
> > - * Author: Robert Marko
> > + * Copyright (C) 2023 Linaro Ltd.
> > */
> > +#ifndef _QCOM_GPIO_H_
> > +#define _QCOM_GPIO_H_
> > +
> > +#include
> > +#include
> > +
> > +struct msm_pin_data {
> > + int pin_count;
> > + const unsigned int *pin_offsets;
> > + /* Index of first special pin, these are ignored for now */
> > + unsigned int special_pins_start;
> > +};
> > +
> > +static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int
> > selector)
> > +{
> > + u32 out = (selector * 0x1000);
> > +
> > + if (offs)
> > + return out + offs[selector];
> > +
> > + return out;
> > +}
> > +
> > +static inline bool qcom_is_special_pin(const struct msm_pin_data *pindata,
> > unsigned int pin)
> > +{
> > + return pindata->special_pins_start && pin >=
> > pindata->special_pins_start;
> > +}
> > +
> > +#endif /* _QCOM_GPIO_H_ */
>
> --
> // Caleb (they/them)
--
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
1 Zagreb, Croatia
Email: robert.ma...@sartura.hr
Web: www.sartura.hr
Re: [PATCH 3/3] ARM: dts: stm32: Fix partition node name for stm32mp15xx-dhcom-u-boot
On 4/17/24 11:00, Patrick DELAUNAY wrote:
> Hi,
>
> On 3/8/24 14:50, Patrice Chotard wrote:
>> Fix flash@0 partition node name with correct offset.
>>
>> Fixes: 90f992e6a58c ("arm: dts: stm32: Add partitions in flash0 and nand
>> node for stm32mp15xx-dhcom/dhcor")
>>
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 6 +++---
>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
>> b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
>> index 2f70b0690d2..1b445619325 100644
>> --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
>> +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
>> @@ -106,15 +106,15 @@
>> label = "fsbl2";
>> reg = <0x0004 0x0004>;
>> };
>> - partition@50 {
>> + partition@8 {
>> label = "uboot";
>> reg = <0x0008 0x0016>;
>> };
>> - partition@90 {
>> + partition@1e {
>> label = "env1";
>> reg = <0x001E 0x0001>;
>> };
>> - partition@98 {
>> + partition@1f {
>> label = "env2";
>> reg = <0x001F 0x0001>;
>> };
>
>
>
> Reviewed-by: Patrick Delaunay
>
> Thanks
> Patrick
>
Applied on u-boot-stm32/master
Re: [PATCH 1/3] ARM: dts: stm32: Fix partition node name for stm32mp157c-ev1-u-boot
On 4/17/24 10:59, Patrick DELAUNAY wrote:
> Hi,
>
> On 3/8/24 14:50, Patrice Chotard wrote:
>> Fix flash@0 and nand@0 partition node name with correct offset.
>>
>> Fixes: e91d3c61767b ("arm: dts: stm32: Add partitions in flash0 and nand
>> node for stm32mp15xx-ev1")
>>
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi | 8
>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
>> b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
>> index 139940bd5d4..3515347e91d 100644
>> --- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
>> +++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
>> @@ -33,11 +33,11 @@
>> label = "fsbl1";
>> reg = <0x 0x0004>;
>> };
>> - partition@8 {
>> + partition@4 {
>> label = "fsbl2";
>> reg = <0x0004 0x0004>;
>> };
>> - partition@10 {
>> + partition@8 {
>> label = "ssbl";
>> reg = <0x0008 0x0020>;
>> };
>> @@ -58,7 +58,7 @@
>> label = "fsbl2";
>> reg = <0x0004 0x0004>;
>> };
>> - partition@10 {
>> + partition@8 {
>> label = "fip";
>> reg = <0x0008 0x0040>;
>> };
>> @@ -112,7 +112,7 @@
>> label = "fip2";
>> reg = <0x0060 0x0040>;
>> };
>> - partition@120 {
>> + partition@a0 {
>> label = "UBI";
>> reg = <0x00a0 0x3f60>;
>> };
>
>
> Reviewed-by: Patrick Delaunay
>
> Thanks
> Patrick
>
>
Applied on u-boot-stm32/master
