Re: [PATCH v3 1/3] clk: imx8mm: Add support for PCIe clocks
Hi Tim,
On Fri, 19 Apr 2024 at 08:29, Tim Harvey wrote:
>
> Add support for PCIe clocks required to enable PCIe support on
> iMX8MM SoC.
>
> Signed-off-by: Tim Harvey
> ---
> v3: wrap pcie clk config around IS_ENABLED to avoid SPL growth as
> suggested by Marek
> ---
> drivers/clk/imx/clk-imx8mm.c | 27 +++
> 1 file changed, 27 insertions(+)
>
Although I was at EOSS last week, it is really nice to see more iMX
SoCs adopting the modern PCIe DW iMX driver.
-Sumit
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
> index b5c253e49663..1a00dd1d287b 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -66,6 +66,17 @@ static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m",
> "sys_pll1_160m", "sys_
> static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m",
> "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
> "video_pll1_out", "audio_pll2_out",
> "sys_pll1_133m", };
>
> +#if CONFIG_IS_ENABLED(PCIE_DW_IMX)
> +static const char *imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m",
> "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m",
> + "sys_pll1_800m",
> "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", };
> +
> +static const char *imx8mm_pcie1_phy_sels[] = {"clock-osc-24m",
> "sys_pll2_100m", "sys_pll2_500m", "clk_ext1", "clk_ext2",
> + "clk_ext3", "clk_ext4",
> "sys_pll1_400m", };
> +
> +static const char *imx8mm_pcie1_aux_sels[] = {"clock-osc-24m",
> "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out",
> + "sys_pll2_100m",
> "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", };
> +#endif
> +
> #ifndef CONFIG_SPL_BUILD
> static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m",
> "sys_pll1_160m", "sys_pll1_40m",
> "sys_pll3_out", "clk_ext1",
> "sys_pll1_80m", "video_pll1_out", };
> @@ -256,6 +267,17 @@ static int imx8mm_clk_probe(struct udevice *dev)
> imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base +
> 0x8b80));
>
> /* IP */
> +#if CONFIG_IS_ENABLED(PCIE_DW_IMX)
> + clk_dm(IMX8MM_CLK_PCIE1_CTRL,
> + imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels,
> + base + 0xa300));
> + clk_dm(IMX8MM_CLK_PCIE1_PHY,
> + imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels,
> + base + 0xa380));
> + clk_dm(IMX8MM_CLK_PCIE1_AUX,
> + imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels,
> + base + 0xa400));
> +#endif
> clk_dm(IMX8MM_CLK_USDHC1,
>imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels,
>base + 0xac00));
> @@ -339,6 +361,11 @@ static int imx8mm_clk_probe(struct udevice *dev)
>imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
> #endif
>
> +#if CONFIG_IS_ENABLED(PCIE_DW_IMX)
> + clk_dm(IMX8MM_CLK_PCIE1_ROOT,
> + imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250,
> 0));
> +#endif
> +
> #if CONFIG_IS_ENABLED(DM_SPI)
> clk_dm(IMX8MM_CLK_ECSPI1,
>imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base +
> 0xb280));
> --
> 2.25.1
>
[PATCH 19/19] ARM: dts: stm32: Add support for STM32MP13xx DHCOR SoM and DHSBC board
This stm32mp135f-dhcor-dhsbc board is a stack of DHCOR SoM based on
STM32MP135F SoC (900MHz / crypto capabilities) populated on DHSBC
carrier board.
The SoM contains the following peripherals:
- STPMIC (power delivery)
- 512MB DDR3L memory
- eMMC and SDIO WiFi module
The DHSBC carrier board contains the following peripherals:
- Two RGMII Ethernet ports
- USB-A Host port, USB-C peripheral port, USB-C power supply plug
- Expansion connector
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/Makefile | 1 +
.../dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi | 25 ++
arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts | 383 ++
arch/arm/dts/stm32mp13xx-dhcor-som.dtsi | 308 ++
arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi| 55 +++
configs/stm32mp13_dhcor_defconfig | 148 +++
6 files changed, 920 insertions(+)
create mode 100644 arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
create mode 100644 arch/arm/dts/stm32mp13xx-dhcor-som.dtsi
create mode 100644 arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi
create mode 100644 configs/stm32mp13_dhcor_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b1c9c6222e5..ca1e3bf3fc8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1290,6 +1290,7 @@ dtb-$(CONFIG_ASPEED_AST2600) += \
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
dtb-$(CONFIG_STM32MP13X) += \
+ stm32mp135f-dhcor-dhsbc.dtb \
stm32mp135f-dk.dtb
dtb-$(CONFIG_STM32MP15X) += \
diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
new file mode 100644
index 000..d718aae16ca
--- /dev/null
+++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2024 Marek Vasut
+ */
+
+#include "stm32mp13xx-dhcor-u-boot.dtsi"
+
+ {
+ bootph-all;
+};
+
+_pins_b {
+ bootph-all;
+
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
+
+ {
+ bootph-all;
+};
diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
new file mode 100644
index 000..fc1c48ad56d
--- /dev/null
+++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
@@ -0,0 +1,383 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2024 Marek Vasut
+ *
+ * DHCOR STM32MP13 variant:
+ * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG
+ * DHCOR PCB number: 718-100 or newer
+ * DHSBC PCB number: 719-100 or newer
+ */
+
+/dts-v1/;
+
+#include
+#include "stm32mp135.dtsi"
+#include "stm32mp13xf.dtsi"
+#include "stm32mp13xx-dhcor-som.dtsi"
+
+/ {
+ model = "DH electronics STM32MP135F DHCOR DHSBC";
+ compatible = "dh,stm32mp135f-dhcor-dhsbc",
+"dh,stm32mp135f-dhcor-som",
+"st,stm32mp135";
+
+ aliases {
+ ethernet0 =
+ ethernet1 =
+ serial2 =
+ serial3 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins_a _usb_cc_pins_b>;
+ vdda-supply = <_adc>;
+ vref-supply = <_adc>;
+ status = "okay";
+
+ adc1: adc@0 {
+ status = "okay";
+
+ /*
+* Type-C USB_PWR_CC1 & USB_PWR_CC2 on in2 & in11.
+* Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
+* 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
+* Use arbitrary margin here (e.g. 5us).
+*
+* The pinmux pins must be set as ANALOG, use datasheet
+* DS13483 Table 7. STM32MP135C/F ball definitions to
+* find out which 'pin name' maps to which 'additional
+* functions', which lists the mapping between pin and
+* ADC channel. In this case, PA5 maps to ADC1_INP2 and
+* PF13 maps to ADC1_INP11 .
+*/
+ channel@2 {
+ reg = <2>;
+ st,min-sample-time-ns = <5000>;
+ };
+
+ channel@11 {
+ reg = <11>;
+ st,min-sample-time-ns = <5000>;
+ };
+
+ /* Expansion connector: INP12:pin29 */
+ channel@12 {
+ reg = <12>;
+ st,min-sample-time-ns = <5000>;
+ };
+ };
+};
+
+ {
+ status = "okay";
+ pinctrl-0 = <_rgmii_pins_a>;
+ pinctrl-1 = <_rgmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rgmii-id";
+ phy-handle =
[PATCH 18/19] ARM: dts: stm32: Add alternate pinmux for MP13 UART7 pins
Add another mux option for UART7 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 41 +
1 file changed, 41 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 7014c7a6d23..c01d39f03ea 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -647,6 +647,47 @@
};
};
+ uart7_pins_a: uart7-0 {
+ pins1 {
+ pinmux = , /* UART7_TX */
+; /* UART7_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = , /* UART7_RX */
+; /* UART7_CTS_NSS
*/
+ bias-disable;
+ };
+ };
+
+ uart7_idle_pins_a: uart7-idle-0 {
+ pins1 {
+ pinmux = , /* UART7_TX */
+; /*
UART7_CTS_NSS */
+ };
+ pins2 {
+ pinmux = ; /* UART7_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = ; /* UART7_RX */
+ bias-disable;
+ };
+ };
+
+ uart7_sleep_pins_a: uart7-sleep-0 {
+ pins {
+ pinmux = , /* UART7_TX */
+, /* UART7_RTS
*/
+, /* UART7_RX */
+; /*
UART7_CTS_NSS */
+ };
+ };
+
uart8_pins_a: uart8-0 {
pins1 {
pinmux = ; /* UART8_TX */
--
2.43.0
[PATCH 17/19] ARM: dts: stm32: Add alternate pinmux for MP13 UART4 pins
Add another mux option for UART4 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 30 +
1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 65f91265a4d..7014c7a6d23 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -617,6 +617,36 @@
};
};
+ uart4_pins_b: uart4-1 {
+ pins1 {
+ pinmux = ; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = ; /* UART4_RX */
+ bias-pull-up;
+ };
+ };
+
+ uart4_idle_pins_b: uart4-idle-1 {
+ pins1 {
+ pinmux = ; /* UART4_TX */
+ };
+ pins2 {
+ pinmux = ; /* UART4_RX */
+ bias-pull-up;
+ };
+ };
+
+ uart4_sleep_pins_b: uart4-sleep-1 {
+ pins {
+ pinmux = , /* UART4_TX */
+; /* UART4_RX */
+ };
+ };
+
uart8_pins_a: uart8-0 {
pins1 {
pinmux = ; /* UART8_TX */
--
2.43.0
[PATCH 16/19] ARM: dts: stm32: Add alternate pinmux for MP13 USART2 pins
Add another mux option for USART2 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 41 +
1 file changed, 41 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index dae015a0ddf..65f91265a4d 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -758,4 +758,45 @@
; /*
USART2_CTS_NSS */
};
};
+
+ usart2_pins_b: usart2-0 {
+ pins1 {
+ pinmux = , /* USART2_TX */
+; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = , /* USART2_RX */
+; /*
USART2_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ usart2_idle_pins_b: usart2-idle-0 {
+ pins1 {
+ pinmux = , /* USART2_TX
*/
+; /*
USART2_CTS_NSS */
+ };
+ pins2 {
+ pinmux = ; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = ; /* USART2_RX */
+ bias-disable;
+ };
+ };
+
+ usart2_sleep_pins_b: usart2-sleep-0 {
+ pins {
+ pinmux = , /* USART2_TX
*/
+, /* USART2_RTS
*/
+, /* USART2_RX
*/
+; /*
USART2_CTS_NSS */
+ };
+ };
};
--
2.43.0
[PATCH 15/19] ARM: dts: stm32: Add alternate pinmux for MP13 USART1 pins
Add another mux option for USART1 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 30 +
1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 7abd227e69f..dae015a0ddf 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -688,6 +688,36 @@
};
};
+ usart1_pins_b: usart1-1 {
+ pins1 {
+ pinmux = ; /* USART1_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = ; /* USART1_RX */
+ bias-pull-up;
+ };
+ };
+
+ usart1_idle_pins_b: usart1-idle-1 {
+ pins1 {
+ pinmux = ; /* USART1_TX */
+ };
+ pins2 {
+ pinmux = ; /* USART1_RX */
+ bias-pull-up;
+ };
+ };
+
+ usart1_sleep_pins_b: usart1-sleep-1 {
+ pins {
+ pinmux = , /* USART1_TX */
+; /* USART1_RX
*/
+ };
+ };
+
usart2_pins_a: usart2-0 {
pins1 {
pinmux = , /* USART2_TX */
--
2.43.0
[PATCH 14/19] ARM: dts: stm32: Add alternate pinmux for MP13 SPI3 pins
Add another mux option for SPI3 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 17acd2850d3..7abd227e69f 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -534,6 +534,29 @@
};
};
+ spi3_pins_a: spi3-0 {
+ pins1 {
+ pinmux = , /* SPI3_SCK */
+; /* SPI3_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = ; /* SPI3_MISO */
+ bias-disable;
+ };
+ };
+
+ spi3_sleep_pins_a: spi3-sleep-0 {
+ pins {
+ pinmux = , /* SPI3_SCK */
+, /* SPI3_MISO */
+; /* SPI3_MOSI */
+ };
+ };
+
spi5_pins_a: spi5-0 {
pins1 {
pinmux = , /* SPI5_SCK */
--
2.43.0
[PATCH 13/19] ARM: dts: stm32: Add alternate pinmux for MP13 SPI2 pins
Add another mux option for SPI2 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index c6967e82b5d..17acd2850d3 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -511,6 +511,29 @@
};
};
+ spi2_pins_a: spi2-0 {
+ pins1 {
+ pinmux = , /* SPI2_SCK */
+; /* SPI2_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = ; /* SPI2_MISO */
+ bias-disable;
+ };
+ };
+
+ spi2_sleep_pins_a: spi2-sleep-0 {
+ pins {
+ pinmux = , /* SPI2_SCK */
+, /* SPI2_MISO */
+; /* SPI2_MOSI
*/
+ };
+ };
+
spi5_pins_a: spi5-0 {
pins1 {
pinmux = , /* SPI5_SCK */
--
2.43.0
[PATCH 12/19] ARM: dts: stm32: Add alternate pinmux for MP13 SDMMC2 D4..D7 pins
Add another mux option for SDMMC2 D4..D7 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index f2b41104a58..c6967e82b5d 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -490,6 +490,27 @@
};
};
+ sdmmc2_d47_pins_a: sdmmc2-d47-0 {
+ pins {
+ pinmux = , /* SDMMC2_D4 */
+, /* SDMMC2_D5 */
+, /* SDMMC2_D6 */
+; /* SDMMC2_D7 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
+ pins {
+ pinmux = , /* SDMMC2_D4 */
+, /* SDMMC2_D5 */
+, /* SDMMC2_D6 */
+; /* SDMMC2_D7 */
+ };
+ };
+
spi5_pins_a: spi5-0 {
pins1 {
pinmux = , /* SPI5_SCK */
--
2.43.0
[PATCH 11/19] ARM: dts: stm32: Add alternate pinmux for MP13 SAI1 pins
Add another mux option for SAI1 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 32 +
1 file changed, 32 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 77a222903de..f2b41104a58 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -356,6 +356,38 @@
};
};
+ sai1a_pins_a: sai1a-0 {
+ pins {
+ pinmux = , /* SAI1_SCK_A */
+, /* SAI1_SD_A */
+; /* SAI1_FS_A */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sai1a_sleep_pins_a: sai1a-sleep-0 {
+ pins {
+ pinmux = , /* SAI1_SCK_A
*/
+, /* SAI1_SD_A */
+; /* SAI1_FS_A
*/
+ };
+ };
+
+ sai1b_pins_a: sai1b-0 {
+ pins {
+ pinmux = ; /* SAI1_SD_B */
+ bias-disable;
+ };
+ };
+
+ sai1b_sleep_pins_a: sai1b-sleep-0 {
+ pins {
+ pinmux = ; /* SAI1_SD_B */
+ };
+ };
+
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = , /* SDMMC1_D0 */
--
2.43.0
[PATCH 10/19] ARM: dts: stm32: Add alternate pinmux for MP13 QSPI pins
Add another mux option for QSPI pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 51 +
1 file changed, 51 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index cf070fbd7f7..77a222903de 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -305,6 +305,57 @@
};
};
+ qspi_clk_pins_a: qspi-clk-0 {
+ pins {
+ pinmux = ; /* QSPI_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ };
+
+ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
+ pins {
+ pinmux = ; /* QSPI_CLK */
+ };
+ };
+
+ qspi_bk1_pins_a: qspi-bk1-0 {
+ pins {
+ pinmux = , /* QSPI_BK1_IO0
*/
+, /* QSPI_BK1_IO1
*/
+, /* QSPI_BK1_IO2
*/
+; /* QSPI_BK1_IO3
*/
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
+ pins {
+ pinmux = , /*
QSPI_BK1_IO0 */
+, /*
QSPI_BK1_IO1 */
+, /*
QSPI_BK1_IO2 */
+; /*
QSPI_BK1_IO3 */
+ };
+ };
+
+ qspi_cs1_pins_a: qspi-cs1-0 {
+ pins {
+ pinmux = ; /* QSPI_BK1_NCS */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
+ pins {
+ pinmux = ; /*
QSPI_BK1_NCS */
+ };
+ };
+
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = , /* SDMMC1_D0 */
--
2.43.0
[PATCH 09/19] ARM: dts: stm32: Add alternate pinmux for MP13 PWM13 pins
Add another mux option for PWM13 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index d19408f19f9..cf070fbd7f7 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -275,6 +275,21 @@
};
};
+ pwm13_pins_a: pwm13-0 {
+ pins {
+ pinmux = ; /* TIM13_CH1 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm13_sleep_pins_a: pwm13-sleep-0 {
+ pins {
+ pinmux = ; /* TIM13_CH1 */
+ };
+ };
+
pwm14_pins_a: pwm14-0 {
pins {
pinmux = ; /* TIM14_CH1 */
--
2.43.0
[PATCH 08/19] ARM: dts: stm32: Add alternate pinmux for MP13 PWM5 pins
Add another mux option for PWM5 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index b58bf6c0024..d19408f19f9 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -245,6 +245,21 @@
};
};
+ pwm5_pins_a: pwm5-0 {
+ pins {
+ pinmux = ; /* TIM5_CH3 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm5_sleep_pins_a: pwm5-sleep-0 {
+ pins {
+ pinmux = ; /* TIM5_CH3 */
+ };
+ };
+
pwm8_pins_a: pwm8-0 {
pins {
pinmux = ; /* TIM8_CH3 */
--
2.43.0
[PATCH 07/19] ARM: dts: stm32: Add alternate pinmux for MP13 MCAN2 pins
Add another mux option for MCAN2 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index b38174504ff..b58bf6c0024 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -188,6 +188,26 @@
};
};
+ m_can2_pins_a: m-can2-0 {
+ pins1 {
+ pinmux = ; /* CAN2_TX */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = ; /* CAN2_RX */
+ bias-disable;
+ };
+ };
+
+ m_can2_sleep_pins_a: m_can2-sleep-0 {
+ pins {
+ pinmux = , /* CAN2_TX */
+; /* CAN2_RX */
+ };
+ };
+
mcp23017_pins_a: mcp23017-0 {
pins {
pinmux = ;
--
2.43.0
[PATCH 06/19] ARM: dts: stm32: Add alternate pinmux for MP13 MCAN1 pins
Add another mux option for MCAN1 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index cfbae71efc7..b38174504ff 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -168,6 +168,26 @@
};
};
+ m_can1_pins_a: m-can1-0 {
+ pins1 {
+ pinmux = ; /* CAN1_TX */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = ; /* CAN1_RX */
+ bias-disable;
+ };
+ };
+
+ m_can1_sleep_pins_a: m_can1-sleep-0 {
+ pins {
+ pinmux = , /* CAN1_TX */
+; /* CAN1_RX */
+ };
+ };
+
mcp23017_pins_a: mcp23017-0 {
pins {
pinmux = ;
--
2.43.0
[PATCH 05/19] ARM: dts: stm32: Add alternate pinmux for MP13 I2C5 pins
Add another mux option for I2C5 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 899f0f98e1a..cfbae71efc7 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -151,6 +151,23 @@
};
};
+ i2c5_pins_b: i2c5-1 {
+ pins {
+ pinmux = , /* I2C5_SCL */
+; /* I2C5_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c5_sleep_pins_b: i2c5-sleep-1 {
+ pins {
+ pinmux = , /* I2C5_SCL */
+; /* I2C5_SDA */
+ };
+ };
+
mcp23017_pins_a: mcp23017-0 {
pins {
pinmux = ;
--
2.43.0
[PATCH 04/19] ARM: dts: stm32: Add alternate pinmux for MP13 ETH2 pins
Add another mux option for ETH2 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 45 +
1 file changed, 45 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index c709d64edcc..899f0f98e1a 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -72,6 +72,51 @@
};
};
+ eth2_rgmii_pins_a: eth2-rgmii-0 {
+ pins1 {
+ pinmux = , /*
ETH_RGMII_TXD0 */
+, /*
ETH_RGMII_TXD1 */
+, /*
ETH_RGMII_TXD2 */
+, /*
ETH_RGMII_TXD3 */
+, /*
ETH_RGMII_TX_CTL */
+, /*
ETH_RGMII_GTX_CLK */
+, /* ETH_MDIO */
+; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = , /*
ETH_RGMII_RXD0 */
+, /*
ETH_RGMII_RXD1 */
+, /*
ETH_RGMII_RXD2 */
+, /*
ETH_RGMII_RXD3 */
+, /*
ETH_RGMII_RX_CTL */
+; /*
ETH_RGMII_RX_CLK */
+ bias-disable;
+ };
+ };
+
+ eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 {
+ pins1 {
+ pinmux = , /*
ETH_RGMII_TXD0 */
+, /*
ETH_RGMII_TXD1 */
+, /*
ETH_RGMII_TXD2 */
+, /*
ETH_RGMII_TXD3 */
+, /*
ETH_RGMII_TX_CTL */
+, /*
ETH_RGMII_GTX_CLK */
+, /* ETH_MDIO */
+, /* ETH_MDC */
+, /*
ETH_RGMII_RXD0 */
+, /*
ETH_RGMII_RXD1 */
+, /*
ETH_RGMII_RXD2 */
+, /*
ETH_RGMII_RXD3 */
+, /*
ETH_RGMII_RX_CTL */
+; /*
ETH_RGMII_RX_CLK */
+ };
+ };
+
i2c1_pins_a: i2c1-0 {
pins {
pinmux = , /* I2C1_SCL */
--
2.43.0
[PATCH 03/19] ARM: dts: stm32: Add alternate pinmux for MP13 ETH1 pins
Add another mux option for ETH1 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 46 +
1 file changed, 46 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 396fb6eee84..c709d64edcc 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -26,6 +26,52 @@
};
};
+ eth1_rgmii_pins_a: eth1-rgmii-0 {
+ pins1 {
+ pinmux = , /*
ETH_RGMII_TXD0 */
+, /*
ETH_RGMII_TXD1 */
+, /*
ETH_RGMII_TXD2 */
+, /*
ETH_RGMII_TXD3 */
+, /*
ETH_RGMII_TX_CTL */
+, /*
ETH_RGMII_GTX_CLK */
+, /* ETH_MDIO */
+; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = , /*
ETH_RGMII_RXD0 */
+, /*
ETH_RGMII_RXD1 */
+, /*
ETH_RGMII_RXD2 */
+, /*
ETH_RGMII_RXD3 */
+, /*
ETH_RGMII_RX_CTL */
+; /*
ETH_RGMII_RX_CLK */
+ bias-disable;
+ };
+
+ };
+
+ eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
+ pins1 {
+ pinmux = , /*
ETH_RGMII_TXD0 */
+, /*
ETH_RGMII_TXD1 */
+, /*
ETH_RGMII_TXD2 */
+, /*
ETH_RGMII_TXD3 */
+, /*
ETH_RGMII_TX_CTL */
+, /*
ETH_RGMII_GTX_CLK */
+, /* ETH_MDIO */
+, /* ETH_MDC */
+, /*
ETH_RGMII_RXD0 */
+, /*
ETH_RGMII_RXD1 */
+, /*
ETH_RGMII_RXD1 */
+, /*
ETH_RGMII_RXD1 */
+, /*
ETH_RGMII_RX_CTL */
+; /*
ETH_RGMII_RX_CLK */
+ };
+ };
+
i2c1_pins_a: i2c1-0 {
pins {
pinmux = , /* I2C1_SCL */
--
2.43.0
[PATCH 02/19] ARM: dts: stm32: Add alternate pinmux for MP13 ADC CC pins
Add another mux option for ADC CC pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 03ded415390..396fb6eee84 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -19,6 +19,13 @@
};
};
+ adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 {
+ pins {
+ pinmux = , /* ADC1_INP2 */
+; /* ADC1_INP11
*/
+ };
+ };
+
i2c1_pins_a: i2c1-0 {
pins {
pinmux = , /* I2C1_SCL */
--
2.43.0
[PATCH 01/19] ARM: dts: stm32: Add alternate pinmux for MP13 ADC pins
Add another mux option for ADC pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 27e0c382678..03ded415390 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -6,6 +6,12 @@
#include
{
+ adc1_pins_a: adc1-pins-0 {
+ pins {
+ pinmux = ; /* ADC1 in12 */
+ };
+ };
+
adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
pins {
pinmux = , /* ADC1 in6 */
--
2.43.0
[PATCH] ARM: dts: stm32: add eth1 and eth2 support on stm32mp13
From: Christophe Roullier
Add both ethernet MACs based on GMAC SNPS IP on stm32mp13.
Signed-off-by: Christophe Roullier
---
Cc: Christophe Roullier
Cc: Joe Hershberger
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: Ramon Fried
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp131.dtsi | 37
arch/arm/dts/stm32mp133.dtsi | 30 +
2 files changed, 67 insertions(+)
diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
index 159ba8f8c9c..ad331b73d18 100644
--- a/arch/arm/dts/stm32mp131.dtsi
+++ b/arch/arm/dts/stm32mp131.dtsi
@@ -1328,6 +1328,37 @@
status = "disabled";
};
+ eth1: eth1@5800a000 {
+ compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
+ reg = <0x5800a000 0x2000>;
+ reg-names = "stmmaceth";
+ interrupts-extended = < GIC_SPI 62
IRQ_TYPE_LEVEL_HIGH>,
+ < 68 1>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
+ "ethstp",
+ "eth-ck";
+ clocks = < ETH1MAC>,
+< ETH1TX>,
+< ETH1RX>,
+< ETH1STP>,
+< ETH1CK_K>;
+ st,syscon = < 0x4 0xff>;
+ snps,mixed-burst;
+ snps,pbl = <2>;
+ snps,axi-config = <_axi_config_1>;
+ snps,tso;
+ status = "disabled";
+
+ stmmac_axi_config_1: stmmac-axi-config {
+ snps,wr_osr_lmt = <0x7>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+ };
+
usbh_ohci: usb@5800c000 {
compatible = "generic-ohci";
reg = <0x5800c000 0x1000>;
@@ -1404,6 +1435,12 @@
ts_cal2: calib@5e {
reg = <0x5e 0x2>;
};
+ ethernet_mac1_address: mac1@e4 {
+ reg = <0xe4 0x6>;
+ };
+ ethernet_mac2_address: mac2@ea {
+ reg = <0xea 0x6>;
+ };
};
/*
diff --git a/arch/arm/dts/stm32mp133.dtsi b/arch/arm/dts/stm32mp133.dtsi
index df451c3c2a2..5cd5bde9535 100644
--- a/arch/arm/dts/stm32mp133.dtsi
+++ b/arch/arm/dts/stm32mp133.dtsi
@@ -64,5 +64,35 @@
};
};
};
+
+ eth2: eth2@5800e000 {
+ compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
+ reg = <0x5800e000 0x2000>;
+ reg-names = "stmmaceth";
+ interrupts-extended = < GIC_SPI 97
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
+ "ethstp",
+ "eth-ck";
+ clocks = < ETH2MAC>,
+< ETH2TX>,
+< ETH2RX>,
+< ETH2STP>,
+< ETH2CK_K>;
+ st,syscon = < 0x4 0xff00>;
+ snps,mixed-burst;
+ snps,pbl = <2>;
+ snps,axi-config = <_axi_config_2>;
+ snps,tso;
+ status = "disabled";
+
+ stmmac_axi_config_2: stmmac-axi-config {
+ snps,wr_osr_lmt = <0x7>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+ };
};
};
--
2.43.0
Re: [PATCH] clk: imx8mn: add video clocks support
Hi Fabio On Sun, Apr 21, 2024 at 10:24 PM Fabio Estevam wrote: > > Hi Michael, > > On Sun, Apr 21, 2024 at 11:07 AM Michael Trimarchi > wrote: > > > > Add clocks support for the video subsystem. > > > > Signed-off-by: Michael Trimarchi > > Which target will make use of these clocks? > > As-is this patch adds only dead code. > > Adding a defconfig that uses these newly introduced clocks would be nice. > You are right, I will wrap it and enable only on CONFIG_VIDEO > Also, to avoid size increase, please protect this code against > CONFIG_VIDEO or something, like done here: > https://source.denx.de/u-boot/custodians/u-boot-imx/-/commit/2b3310ef13998dfd03196a0806e03035212b102c Working on display panel integration on imx8m, trying to progress merging things up. Michael -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 mich...@amarulasolutions.com __ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 i...@amarulasolutions.com www.amarulasolutions.com
[PATCH v1] tee: sandbox: check for buffer size
Add additional check for buffer size when reading out persistent
storage value and provide back actual value size.
Signed-off-by: Igor Opaniuk
---
drivers/tee/sandbox.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/tee/sandbox.c b/drivers/tee/sandbox.c
index 8ad7c09efdd..86b16a3bb8d 100644
--- a/drivers/tee/sandbox.c
+++ b/drivers/tee/sandbox.c
@@ -174,7 +174,7 @@ static u32 ta_avb_invoke_func(struct udevice *dev, u32
func, uint num_params,
uint slot;
u64 val;
char *value;
- u32 value_sz;
+ u32 value_sz, tmp_sz;
switch (func) {
case TA_AVB_CMD_READ_ROLLBACK_INDEX:
@@ -267,8 +267,12 @@ static u32 ta_avb_invoke_func(struct udevice *dev, u32
func, uint num_params,
if (!ep)
return TEE_ERROR_ITEM_NOT_FOUND;
- value_sz = strlen(ep->data) + 1;
- memcpy(value, ep->data, value_sz);
+ tmp_sz = strlen(ep->data) + 1;
+ if (value_sz < tmp_sz)
+ return TEE_ERROR_SHORT_BUFFER;
+
+ memcpy(value, ep->data, tmp_sz);
+ params[1].u.memref.size = tmp_sz;
return TEE_SUCCESS;
case TA_AVB_CMD_WRITE_PERSIST_VALUE:
--
2.34.1
Re: [PATCH] usb: dwc2: update reset method for host and device mode
On 3/28/24 2:14 PM, Kongyang Liu wrote:
[...]
@@ -464,12 +464,26 @@ static void reconfig_usbd(struct dwc2_udc *dev)
{
/* 2. Soft-reset OTG Core and then unreset again. */
int i;
- unsigned int uTemp = writel(CORE_SOFT_RESET, >grstctl);
+ unsigned int uTemp;
uint32_t dflt_gusbcfg;
uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz;
u32 max_hw_ep;
int pdata_hw_ep;
Drop this newline
+ u32 snpsid, greset;
+
+ snpsid = readl(>gsnpsid);
+ writel(CORE_SOFT_RESET, >grstctl);
+ if ((snpsid & SNPSID_VER_MASK) < (SNPSID_VER_420a & SNPSID_VER_MASK)) {
Can you use FIELD_GET()/FIELD_PREP() for this ?
+ wait_for_bit_le32(>grstctl, CORE_SOFT_RESET, false, 1000,
false);
+ } else {
+ wait_for_bit_le32(>grstctl, CORE_SOFT_RESET_DONE, true,
1000, false);
+ greset = readl(>grstctl);
+ greset &= ~CORE_SOFT_RESET;
+ greset |= CORE_SOFT_RESET_DONE;
+ writel(greset, >grstctl);
clrsetbits_le32()
[...]
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 637eb2dd06..1baeff96ee 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -159,6 +159,7 @@ static void dwc_otg_core_reset(struct udevice *dev,
struct dwc2_core_regs *regs)
{
int ret;
+ u32 snpsid, greset;
/* Wait for AHB master IDLE state. */
ret = wait_for_bit_le32(>grstctl, DWC2_GRSTCTL_AHBIDLE,
@@ -167,9 +168,20 @@ static void dwc_otg_core_reset(struct udevice *dev,
dev_info(dev, "%s: Timeout!\n", __func__);
/* Core Soft Reset */
+ snpsid = readl(>gsnpsid);
writel(DWC2_GRSTCTL_CSFTRST, >grstctl);
- ret = wait_for_bit_le32(>grstctl, DWC2_GRSTCTL_CSFTRST,
- false, 1000, false);
+ if ((snpsid & DWC2_SNPSID_VER_MASK) < (DWC2_SNPSID_DEVID_VER_420a &
DWC2_SNPSID_VER_MASK)) {
+ ret = wait_for_bit_le32(>grstctl, DWC2_GRSTCTL_CSFTRST,
+ false, 1000, false);
+ } else {
+ ret = wait_for_bit_le32(>grstctl,
DWC2_GRSTCTL_GSFTRST_DONE,
+ true, 1000, false);
+ greset = readl(>grstctl);
+ greset &= ~DWC2_GRSTCTL_CSFTRST;
+ greset |= DWC2_GRSTCTL_GSFTRST_DONE;
+ writel(greset, >grstctl);
Same comments as above.
Maybe this should be pulled into dedicated function to avoid duplication?
+ }
+
if (ret)
dev_info(dev, "%s: Timeout!\n", __func__);
@@ -1180,7 +1192,8 @@ static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
snpsid >> 12 & 0xf, snpsid & 0xfff);
if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
- (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
+ (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx
&&
+ (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_4xx) {
Try FIELD_GET/FIELD_PREP
Re: [PATCH] usb: dwc3: support USB 3.1 controllers
On 4/11/24 6:05 PM, Caleb Connolly wrote: The revision is different for these, add the additional check as in xhci-dwc3 core_init code. Signed-off-by: Caleb Connolly Is there a matching Linux kernel patch , or does Linux do some other check ?
Re: [PATCH 1/2] ARM: dts: stm32: add PWR regulators support on stm32mp131
On 3/19/24 3:45 AM, Marek Vasut wrote: This patch adds STM32 PWR regulators DT support on stm32mp131. This requires TFA to clear RCC_SECCFGR, is disabled by default and can only be enabled on board DT level. Signed-off-by: Marek Vasut It seems these patches have been missed from the recent PR ? Is there any feedback on those patches ?
Re: [PATCH] clk: imx8mn: add video clocks support
Hi Michael, On Sun, Apr 21, 2024 at 11:07 AM Michael Trimarchi wrote: > > Add clocks support for the video subsystem. > > Signed-off-by: Michael Trimarchi Which target will make use of these clocks? As-is this patch adds only dead code. Adding a defconfig that uses these newly introduced clocks would be nice. Also, to avoid size increase, please protect this code against CONFIG_VIDEO or something, like done here: https://source.denx.de/u-boot/custodians/u-boot-imx/-/commit/2b3310ef13998dfd03196a0806e03035212b102c
[PATCH] rockchip: rk3328: Fix bootph prop for vop node
The vop node should not be included in TPL/SPL control FDT, it should
only be included at U-Boot proper pre-reloc phase.
Change to use bootph-some-ram prop to fix this.
Fixes: 6794063d5065 ("ARM: dts: rk3328: Enable VOP for bootph-all")
Signed-off-by: Jonas Karlman
---
arch/arm/dts/rk3328-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
index 7c5067cf002e..d3608bd0e2b2 100644
--- a/arch/arm/dts/rk3328-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-u-boot.dtsi
@@ -131,7 +131,7 @@
};
{
- bootph-all;
+ bootph-some-ram;
};
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
--
2.43.2
[PATCH v2 2/3] rockchip: rk3328: Enable ARMv8 crypto extensions
The RK3328 SoC support ARMv8 Cryptography Extensions and use of the ARMv8 crypto extensions help speed up FIT checksum validation in SPL. Imply ARMV8_SET_SMPEN and ARMV8_CRYPTO to take advantage of the crypto extensions for SHA256 when validating checksum of FIT images. Also imply OF_LIVE to help speed up init of U-Boot proper. Signed-off-by: Jonas Karlman --- v2: No change, rebase on latest master bransh --- arch/arm/mach-rockchip/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index ee0f338995b9..651ecfe9b8fd 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -180,8 +180,11 @@ config ROCKCHIP_RK3328 select SUPPORT_TPL select TPL select TPL_NEEDS_SEPARATE_STACK if TPL + imply ARMV8_CRYPTO + imply ARMV8_SET_SMPEN imply MISC imply MISC_INIT_R + imply OF_LIVE imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_EFUSE -- 2.43.2
[PATCH v2 3/3] rockchip: io-domain: Add support for RK3328
Port the RK3328 part of the Rockchip IO-domain driver from linux.
This differs from linux version in that pmu io iodomain bit is enabled
in the write ops instead of in an init ops as in linux, this way we can
avoid keeping a full state of all supply that have been configured.
Enable by default on all RK3328 boards, skip rk3328-evb because this
target is typically also used on miscellaneous boards and boxes not
fully supported by U-Boot.
Signed-off-by: Jonas Karlman
---
v2: No change
---
arch/arm/mach-rockchip/rk3328/syscon_rk3328.c | 3 ++
configs/evb-rk3328_defconfig | 1 +
drivers/misc/Kconfig | 2 +-
drivers/misc/rockchip-io-domain.c | 38 +++
4 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c
b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c
index daf74a0e2d37..d2f267e63534 100644
--- a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c
+++ b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c
@@ -17,4 +17,7 @@ U_BOOT_DRIVER(rockchip_rk3328_grf) = {
.name = "rockchip_rk3328_grf",
.id = UCLASS_SYSCON,
.of_match = rk3328_syscon_ids,
+#if CONFIG_IS_ENABLED(OF_REAL)
+ .bind = dm_scan_fdt_dev,
+#endif
};
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index 75a0e0f286bd..53ad6777ec50 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -57,6 +57,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+# CONFIG_ROCKCHIP_IODOMAIN is not set
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PHY_MOTORCOMM=y
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 6b06888454f4..6009d55f400e 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -104,7 +104,7 @@ config ROCKCHIP_OTP
config ROCKCHIP_IODOMAIN
bool "Rockchip IO-domain driver support"
depends on DM_REGULATOR && ARCH_ROCKCHIP
- default y if ROCKCHIP_RK3568
+ default y if ROCKCHIP_RK3328 || ROCKCHIP_RK3568
help
Enable support for IO-domains in Rockchip SoCs. It is necessary
for the IO-domain setting of the SoC to match the voltage supplied
diff --git a/drivers/misc/rockchip-io-domain.c
b/drivers/misc/rockchip-io-domain.c
index 0ffea32ef07f..04d4d07c4127 100644
--- a/drivers/misc/rockchip-io-domain.c
+++ b/drivers/misc/rockchip-io-domain.c
@@ -27,6 +27,10 @@
#define MAX_VOLTAGE_1_8198
#define MAX_VOLTAGE_3_3360
+#define RK3328_SOC_CON40x410
+#define RK3328_SOC_CON4_VCCIO2 BIT(7)
+#define RK3328_SOC_VCCIO2_SUPPLY_NUM 1
+
#define RK3399_PMUGRF_CON0 0x180
#define RK3399_PMUGRF_CON0_VSELBIT(8)
#define RK3399_PMUGRF_VSEL_SUPPLY_NUM 9
@@ -95,6 +99,22 @@ static int rockchip_iodomain_write(struct regmap *grf, uint
offset, int idx, int
return regmap_write(grf, offset, val);
}
+static int rk3328_iodomain_write(struct regmap *grf, uint offset, int idx, int
uV)
+{
+ int ret = rockchip_iodomain_write(grf, offset, idx, uV);
+
+ if (!ret && idx == RK3328_SOC_VCCIO2_SUPPLY_NUM) {
+ /*
+* set vccio2 iodomain to also use this framework
+* instead of a special gpio.
+*/
+ u32 val = RK3328_SOC_CON4_VCCIO2 | (RK3328_SOC_CON4_VCCIO2 <<
16);
+ ret = regmap_write(grf, RK3328_SOC_CON4, val);
+ }
+
+ return ret;
+}
+
static int rk3399_pmu_iodomain_write(struct regmap *grf, uint offset, int idx,
int uV)
{
int ret = rockchip_iodomain_write(grf, offset, idx, uV);
@@ -111,6 +131,20 @@ static int rk3399_pmu_iodomain_write(struct regmap *grf,
uint offset, int idx, i
return ret;
}
+static const struct rockchip_iodomain_soc_data soc_data_rk3328 = {
+ .grf_offset = 0x410,
+ .supply_names = {
+ "vccio1-supply",
+ "vccio2-supply",
+ "vccio3-supply",
+ "vccio4-supply",
+ "vccio5-supply",
+ "vccio6-supply",
+ "pmuio-supply",
+ },
+ .write = rk3328_iodomain_write,
+};
+
static const struct rockchip_iodomain_soc_data soc_data_rk3399 = {
.grf_offset = 0xe640,
.supply_names = {
@@ -156,6 +190,10 @@ static const struct rockchip_iodomain_soc_data
soc_data_rk3568_pmu = {
};
static const struct udevice_id rockchip_iodomain_ids[] = {
+ {
+ .compatible = "rockchip,rk3328-io-voltage-domain",
+ .data = (ulong)_data_rk3328,
+ },
{
.compatible = "rockchip,rk3399-io-voltage-domain",
.data = (ulong)_data_rk3399,
--
2.43.2
[PATCH v2 1/3] rockchip: rk3328: Sort imply statements alphabetically
Sort imply statements under ROCKCHIP_RK3328 alphabetically and remove ENABLE_ARM_SOC_BOOT0_HOOK, DEBUG_UART_BOARD_INIT and SYS_NS16550, they are already implyed or selected by ARCH_ROCKCHIP. Signed-off-by: Jonas Karlman --- v2: No change, rebase on latest master bransh --- arch/arm/mach-rockchip/Kconfig | 11 --- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 4f22d9bde9f9..ee0f338995b9 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -180,19 +180,16 @@ config ROCKCHIP_RK3328 select SUPPORT_TPL select TPL select TPL_NEEDS_SEPARATE_STACK if TPL + imply MISC + imply MISC_INIT_R imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_EFUSE imply ROCKCHIP_SDRAM_COMMON imply SPL_ROCKCHIP_COMMON_BOARD + imply SPL_SEPARATE_BSS imply SPL_SERIAL imply TPL_SERIAL - imply SPL_SEPARATE_BSS - select ENABLE_ARM_SOC_BOOT0_HOOK - select DEBUG_UART_BOARD_INIT - select SYS_NS16550 - imply MISC - imply ROCKCHIP_EFUSE - imply MISC_INIT_R help The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two -- 2.43.2
[PATCH v2 0/3] rockchip: rk3328: Add IO-domain driver and speed up boot
This series adds support for RK3328 to the IO-domain driver, it also enabled ARMv8 crypto extensions and OF_LIVE to speed up boot on rk3328 boards. Before this series init time is around 4.1 seconds on a Rock64 v2.0: => bootstage report Timer summary in microseconds (11 records): MarkElapsed Stage 63,628 SPL 284,173220,545 end phase 342,709 58,536 board_init_f 967,537624,828 board_init_r 2,980,332 2,012,795 eth_common_init 4,141,289 1,160,957 eth_initialize 4,141,545256 main_loop 4,146,525 4,980 cli_loop Accumulated time: 71,396 dm_spl 329,994 dm_f 12,355 dm_r After this series init time is around 1.3 seconds on same Rock64 v2.0: => bootstage report Timer summary in microseconds (12 records): MarkElapsed Stage 63,628 SPL 284,173220,545 end phase 303,282 19,109 board_init_f 942,973639,691 board_init_r 1,194,831251,858 eth_common_init 1,363,405168,574 eth_initialize 1,363,609204 main_loop 1,363,738129 cli_loop Accumulated time: 113,648 dm_spl 344,913 dm_f 6,788 of_live 17,895 dm_r Changes in v2: - Rebase on latest master bransh Jonas Karlman (3): rockchip: rk3328: Sort imply statements alphabetically rockchip: rk3328: Enable ARMv8 crypto extensions rockchip: io-domain: Add support for RK3328 arch/arm/mach-rockchip/Kconfig| 14 +++ arch/arm/mach-rockchip/rk3328/syscon_rk3328.c | 3 ++ configs/evb-rk3328_defconfig | 1 + drivers/misc/Kconfig | 2 +- drivers/misc/rockchip-io-domain.c | 38 +++ 5 files changed, 50 insertions(+), 8 deletions(-) -- 2.43.2
Re: [GIT PULL] u-boot-video/video-20240421
On Sun, Apr 21, 2024 at 03:52:13PM +0200, Anatolij Gustschin wrote: > Hi Tom, > > please pull video driver updates for v2024.07-rc1. > > CI: https://source.denx.de/u-boot/custodians/u-boot-video/-/pipelines/20466 > > Thanks, > Anatolij > > The following changes since commit af04f37a78c7e61597fb9ed6db2c8f8d7f8b0f92: > > Merge tag 'u-boot-stm32-20240419' of > https://source.denx.de/u-boot/custodians/u-boot-stm (2024-04-19 14:25:04 > -0600) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-video.git > tags/video-20240421 > > for you to fetch changes up to efe1ceec7ef0c2ce2344dbe066fca0d389a0b4f3: > > boot: Move framebuffer reservation to separate helper (2024-04-21 09:07:02 > +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PATCH] clk: imx8mn: add video clocks support
Add clocks support for the video subsystem.
Signed-off-by: Michael Trimarchi
---
drivers/clk/imx/clk-imx8mn.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 457acb8a40..baac79dd29 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -23,6 +23,7 @@ static const char *arm_pll_bypass_sels[] = {"arm_pll",
"arm_pll_ref_sel", };
static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
+static const char *video_pll_bypass_sels[] = {"video_pll",
"video_pll_ref_sel", };
static const char *imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out",
"sys_pll2_500m", "sys_pll2_1000m",
"sys_pll1_800m", "sys_pll1_400m",
"audio_pll1_out", "sys_pll3_out", };
@@ -30,6 +31,10 @@ static const char *imx8mn_a53_sels[] = {"clock-osc-24m",
"arm_pll_out", "sys_pll
static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m",
"sys_pll1_800m", "sys_pll1_400m",
"sys_pll2_125m", "sys_pll3_out",
"audio_pll1_out", "video_pll_out", };
+static const char *imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll_out",
"audio_pll2_out",
+ "audio_pll1_out",
"sys_pll1_800m", "sys_pll2_1000m",
+ "sys_pll3_out", "clk_ext4", };
+
static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m",
"sys_pll1_800m", "sys_pll2_250m",
"sys_pll2_200m", "audio_pll1_out",
"video_pll_out", "sys_pll3_out", };
@@ -139,6 +144,9 @@ static int imx8mn_clk_probe(struct udevice *dev)
clk_dm(IMX8MN_SYS_PLL3_REF_SEL,
imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MN_VIDEO_PLL1_REF_SEL,
+ imx_clk_mux("video_pll_ref_sel", base + 0x28, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MN_DRAM_PLL,
imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
@@ -155,6 +163,9 @@ static int imx8mn_clk_probe(struct udevice *dev)
clk_dm(IMX8MN_SYS_PLL3,
imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
base + 0x114, _1416x_pll));
+ clk_dm(IMX8MN_VIDEO_PLL1,
+ imx_clk_pll14xx("video_pll", "video_pll_ref_sel",
+ base + 0x28, _1443x_pll));
/* PLL bypass out */
clk_dm(IMX8MN_DRAM_PLL_BYPASS,
@@ -183,6 +194,12 @@ static int imx8mn_clk_probe(struct udevice *dev)
ARRAY_SIZE(sys_pll3_bypass_sels),
CLK_SET_RATE_PARENT));
+ clk_dm(IMX8MN_VIDEO_PLL1_BYPASS,
+ imx_clk_mux_flags("video_pll_bypass", base + 0x28, 16, 1,
+video_pll_bypass_sels,
+ARRAY_SIZE(video_pll_bypass_sels),
+CLK_SET_RATE_PARENT));
+
/* PLL out gate */
clk_dm(IMX8MN_DRAM_PLL_OUT,
imx_clk_gate("dram_pll_out", "dram_pll_bypass",
@@ -199,6 +216,9 @@ static int imx8mn_clk_probe(struct udevice *dev)
clk_dm(IMX8MN_SYS_PLL3_OUT,
imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
base + 0x114, 11));
+ clk_dm(IMX8MN_VIDEO_PLL1_OUT,
+ imx_clk_gate("video_pll_out", "video_pll_bypass",
+ base + 0x28, 13));
/* SYS PLL fixed output */
clk_dm(IMX8MN_SYS_PLL1_40M,
@@ -275,6 +295,9 @@ static int imx8mn_clk_probe(struct udevice *dev)
clk_dm(IMX8MN_CLK_USDHC2,
imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels,
base + 0xac80));
+
+ clk_dm(IMX8MN_CLK_DISP_PIXEL,
+ imx8m_clk_composite("disp_pixel", imx8mn_disp_pixel_sels, base +
0xa500));
clk_dm(IMX8MN_CLK_I2C1,
imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00));
clk_dm(IMX8MN_CLK_I2C2,
--
2.40.1
[GIT PULL] u-boot-video/video-20240421
Hi Tom, please pull video driver updates for v2024.07-rc1. CI: https://source.denx.de/u-boot/custodians/u-boot-video/-/pipelines/20466 Thanks, Anatolij The following changes since commit af04f37a78c7e61597fb9ed6db2c8f8d7f8b0f92: Merge tag 'u-boot-stm32-20240419' of https://source.denx.de/u-boot/custodians/u-boot-stm (2024-04-19 14:25:04 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-video.git tags/video-20240421 for you to fetch changes up to efe1ceec7ef0c2ce2344dbe066fca0d389a0b4f3: boot: Move framebuffer reservation to separate helper (2024-04-21 09:07:02 +0200) - simple_panel: support timing parsing from EDID - dw_hdmi: fix gcc-14 compiler warnings - dw_hdmi: support vendor PHY for HDMI - rockchip: add Rockchip INNO HDMI PHY driver - rockchip: RK3328 HDMI and VOP support - evb-rk3328: enable vidconsole support - Tegra DC and DSI improvements and Tegra 114 support - add LG LG070WX3 MIPI DSI panel driver - add Samsung LTL106HL02 MIPI DSI panel driver - add Toshiba TC358768 RGB to DSI bridge support - add basic support for the Parade DP501 transmitter - Tegra 3 panel and bridge driver improvements - simplefb: modernise DT parsing - fdt_simplefb: Enumerate framebuffer info from video handoff - preserve framebuffer if SPL is passing video hand-off - fdt_support: allow reserving FB region without simplefb Anton Bambura (1): video: panel: add Samsung LTL106HL02 MIPI DSI panel driver Caleb Connolly (1): video: simplefb: modernise DT parsing Devarsh Thakkar (3): boot: fdt_simplefb: Enumerate framebuffer info from video handoff video: Assume video to be active if SPL is passing video hand-off boot: Move framebuffer reservation to separate helper Jagan Teki (17): video: rockchip: hdmi: Detect hpd after controller init video: dw_hdmi: Add Vendor PHY handling video: dw_hdmi: Extend the HPD detection video: dw_hdmi: Add read_hpd hook video: dw_hdmi: Add setup_hpd hook video: rockchip: vop: Simplify rkvop_enable video: rockchip: vop: Add win offset support video: rockchip: vop: Add dsp offset support clk: rockchip: rk3328: Add VOP clk support clk: rk3328: Add get hdmiphy clock phy: rockchip: Add Rockchip INNO HDMI PHY driver video: rockchip: Add rk3328 hdmi support video: rockchip: Add rk3328 vop support ARM: dts: rk3328: Enable VOP for bootph-all rockchip: Enable preconsole for rk3328 configs: evb-rk3328: Enable vidconsole for rk3328 configs: Enable HDMI Out for ROC-RK3328-CC Jonas Schwöbel (7): video: tegra20: dc: fix printing of framebuffer address video: tegra20: dc: enable backlight after DC is configured video: tegra20: dc: clean framebuffer memory block video: tegra20: dsi: remove pre-configuration video: tegra20: dsi: set correct fifo depth video: tegra20: dsi: use set_backlight for backlight only video: bridge: add basic support for the Parade DP501 transmitter Khem Raj (1): video: dw_hdmi: Fix compiler warnings with gcc-14 Svyatoslav Ryhel (18): video: simple_panel: simplify platform data pass video: simple_panel: add EDID support video: tegra20: dc: diverge DC per-SOC video: tegra20: dc: fix image shift on rotated panels video: tegra20: consolidate DC header video: tegra20: dc: pass DC id to internal devices video: tegra20: dc: add PLLD2 parent support video: tegra20: dc: add powergate video: tegra20: dc: configure behavior if PLLD/D2 is used video: tegra20: dc: parameterize V- and H-sync polarities video: tegra20: add MIPI calibration driver video: tegra20: dsi: add T114 support video: tegra20: dsi: add reset support video: panel: add LG LG070WX3 MIPI DSI panel driver video: bridge: add Toshiba TC358768 RGB to DSI bridge support video: endeavoru-panel: shift the init sequence by one step earlier video: bridge: ssd2825: shift the init sequence by one step earlier video: renesas: shift the init sequence by one step earlier arch/arm/dts/rk3328-u-boot.dtsi| 4 + arch/arm/dts/tegra114-u-boot.dtsi | 13 + arch/arm/dts/tegra114.dtsi | 4 +- arch/arm/dts/tegra30-u-boot.dtsi | 4 + arch/arm/dts/tegra30.dtsi | 2 +- arch/arm/include/asm/arch-rockchip/cru_rk3328.h| 34 + arch/arm/include/asm/arch-tegra/dc.h | 13 +- arch/arm/include/asm/arch-tegra114/pwm.h | 13 + arch/arm/include/asm/arch-tegra20/display.h| 28 - arch/arm/include/asm/arch-tegra30/display.h| 28 - arch/arm/mach-rockchip/Kconfig | 1 + boot/fdt_simplefb.c
